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-rw-r--r--MAINTAINERS8
-rw-r--r--arch/arm/mach-omap2/Kconfig18
-rw-r--r--arch/arm/mach-omap2/Makefile8
-rw-r--r--arch/arm/mach-omap2/board-3430sdp.c632
-rw-r--r--arch/arm/mach-omap2/board-am3517crane.c1
-rw-r--r--arch/arm/mach-omap2/board-cm-t35.c3
-rw-r--r--arch/arm/mach-omap2/board-cm-t3517.c3
-rw-r--r--arch/arm/mach-omap2/board-flash.c3
-rw-r--r--arch/arm/mach-omap2/board-flash.h1
-rw-r--r--arch/arm/mach-omap2/board-n8x0.c2
-rw-r--r--arch/arm/mach-omap2/board-omap3pandora.c2
-rw-r--r--arch/arm/mach-omap2/board-rx51-peripherals.c32
-rw-r--r--arch/arm/mach-omap2/board-ti8168evm.c62
-rw-r--r--arch/arm/mach-omap2/devices.c26
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.c3
-rw-r--r--arch/arm/mach-omap2/gpmc-nand.h27
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.c3
-rw-r--r--arch/arm/mach-omap2/gpmc-onenand.h24
-rw-r--r--arch/arm/mach-omap2/gpmc-smc91x.c186
-rw-r--r--arch/arm/mach-omap2/gpmc-smc91x.h42
-rw-r--r--arch/arm/mach-omap2/gpmc.h227
-rw-r--r--arch/arm/mach-omap2/pm34xx.c2
-rw-r--r--drivers/memory/Kconfig8
-rw-r--r--drivers/memory/Makefile1
-rw-r--r--drivers/memory/omap-gpmc.c (renamed from arch/arm/mach-omap2/gpmc.c)385
-rw-r--r--include/linux/omap-gpmc.h199
26 files changed, 553 insertions, 1355 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index e3a96e42193c..0d6469a2cf70 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -6702,6 +6702,14 @@ L: linux-omap@vger.kernel.org
6702S: Maintained 6702S: Maintained
6703F: sound/soc/omap/ 6703F: sound/soc/omap/
6704 6704
6705OMAP GENERAL PURPOSE MEMORY CONTROLLER SUPPORT
6706M: Roger Quadros <rogerq@ti.com>
6707M: Tony Lindgren <tony@atomide.com>
6708L: linux-omap@vger.kernel.org
6709S: Maintained
6710F: drivers/memory/omap-gpmc.c
6711F: arch/arm/mach-omap2/*gpmc*
6712
6705OMAP FRAMEBUFFER SUPPORT 6713OMAP FRAMEBUFFER SUPPORT
6706M: Tomi Valkeinen <tomi.valkeinen@ti.com> 6714M: Tomi Valkeinen <tomi.valkeinen@ti.com>
6707L: linux-fbdev@vger.kernel.org 6715L: linux-fbdev@vger.kernel.org
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index f4d06aea8460..6e249324fdd7 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -79,7 +79,9 @@ config ARCH_OMAP2PLUS
79 select CLKSRC_MMIO 79 select CLKSRC_MMIO
80 select GENERIC_IRQ_CHIP 80 select GENERIC_IRQ_CHIP
81 select MACH_OMAP_GENERIC 81 select MACH_OMAP_GENERIC
82 select MEMORY
82 select OMAP_DM_TIMER 83 select OMAP_DM_TIMER
84 select OMAP_GPMC
83 select PINCTRL 85 select PINCTRL
84 select SOC_BUS 86 select SOC_BUS
85 select TI_PRIV_EDMA 87 select TI_PRIV_EDMA
@@ -235,12 +237,6 @@ config MACH_TOUCHBOOK
235 default y 237 default y
236 select OMAP_PACKAGE_CBB 238 select OMAP_PACKAGE_CBB
237 239
238config MACH_OMAP_3430SDP
239 bool "OMAP 3430 SDP board"
240 depends on ARCH_OMAP3
241 default y
242 select OMAP_PACKAGE_CBB
243
244config MACH_NOKIA_N810 240config MACH_NOKIA_N810
245 bool 241 bool
246 242
@@ -282,16 +278,6 @@ config MACH_SBC3530
282 default y 278 default y
283 select OMAP_PACKAGE_CUS 279 select OMAP_PACKAGE_CUS
284 280
285config MACH_TI8168EVM
286 bool "TI8168 Evaluation Module"
287 depends on SOC_TI81XX
288 default y
289
290config MACH_TI8148EVM
291 bool "TI8148 Evaluation Module"
292 depends on SOC_TI81XX
293 default y
294
295config OMAP3_EMU 281config OMAP3_EMU
296 bool "OMAP3 debugging peripherals" 282 bool "OMAP3 debugging peripherals"
297 depends on ARCH_OMAP3 283 depends on ARCH_OMAP3
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 3b653b3ac268..08cc94474d17 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -6,7 +6,7 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
6 -I$(srctree)/arch/arm/plat-omap/include 6 -I$(srctree)/arch/arm/plat-omap/include
7 7
8# Common support 8# Common support
9obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o gpmc.o timer.o pm.o \ 9obj-y := id.o io.o control.o mux.o devices.o fb.o serial.o timer.o pm.o \
10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \ 10 common.o gpio.o dma.o wd_timer.o display.o i2c.o hdq1w.o omap_hwmod.o \
11 omap_device.o sram.o drm.o 11 omap_device.o sram.o drm.o
12 12
@@ -246,7 +246,6 @@ obj-$(CONFIG_MACH_OMAP3530_LV_SOM) += board-omap3logic.o
246obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o 246obj-$(CONFIG_MACH_OMAP3_TORPEDO) += board-omap3logic.o
247obj-$(CONFIG_MACH_OVERO) += board-overo.o 247obj-$(CONFIG_MACH_OVERO) += board-overo.o
248obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o 248obj-$(CONFIG_MACH_OMAP3_PANDORA) += board-omap3pandora.o
249obj-$(CONFIG_MACH_OMAP_3430SDP) += board-3430sdp.o
250obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o 249obj-$(CONFIG_MACH_NOKIA_N8X0) += board-n8x0.o
251obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o 250obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51.o sdram-nokia.o
252obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o 251obj-$(CONFIG_MACH_NOKIA_RX51) += board-rx51-peripherals.o
@@ -260,8 +259,6 @@ obj-$(CONFIG_MACH_OMAP3517EVM) += board-am3517evm.o
260obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o 259obj-$(CONFIG_MACH_CRANEBOARD) += board-am3517crane.o
261 260
262obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o 261obj-$(CONFIG_MACH_SBC3530) += board-omap3stalker.o
263obj-$(CONFIG_MACH_TI8168EVM) += board-ti8168evm.o
264obj-$(CONFIG_MACH_TI8148EVM) += board-ti8168evm.o
265 262
266# Platform specific device init code 263# Platform specific device init code
267 264
@@ -284,9 +281,6 @@ obj-y += $(onenand-m) $(onenand-y)
284nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o 281nand-$(CONFIG_MTD_NAND_OMAP2) := gpmc-nand.o
285obj-y += $(nand-m) $(nand-y) 282obj-y += $(nand-m) $(nand-y)
286 283
287smc91x-$(CONFIG_SMC91X) := gpmc-smc91x.o
288obj-y += $(smc91x-m) $(smc91x-y)
289
290smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o 284smsc911x-$(CONFIG_SMSC911X) := gpmc-smsc911x.o
291obj-y += $(smsc911x-m) $(smsc911x-y) 285obj-y += $(smsc911x-m) $(smsc911x-y)
292ifneq ($(CONFIG_HWSPINLOCK_OMAP),) 286ifneq ($(CONFIG_HWSPINLOCK_OMAP),)
diff --git a/arch/arm/mach-omap2/board-3430sdp.c b/arch/arm/mach-omap2/board-3430sdp.c
deleted file mode 100644
index d21a3048d06b..000000000000
--- a/arch/arm/mach-omap2/board-3430sdp.c
+++ /dev/null
@@ -1,632 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/board-3430sdp.c
3 *
4 * Copyright (C) 2007 Texas Instruments
5 *
6 * Modified from mach-omap2/board-generic.c
7 *
8 * Initial code: Syed Mohammed Khasim
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/delay.h>
19#include <linux/input.h>
20#include <linux/input/matrix_keypad.h>
21#include <linux/spi/spi.h>
22#include <linux/i2c/twl.h>
23#include <linux/regulator/machine.h>
24#include <linux/io.h>
25#include <linux/gpio.h>
26#include <linux/mmc/host.h>
27#include <linux/platform_data/spi-omap2-mcspi.h>
28#include <linux/platform_data/omap-twl4030.h>
29#include <linux/usb/phy.h>
30
31#include <asm/mach-types.h>
32#include <asm/mach/arch.h>
33#include <asm/mach/map.h>
34
35#include "common.h"
36#include <linux/omap-dma.h>
37#include <video/omapdss.h>
38#include <video/omap-panel-data.h>
39
40#include "gpmc.h"
41#include "gpmc-smc91x.h"
42
43#include "soc.h"
44#include "board-flash.h"
45#include "mux.h"
46#include "sdram-qimonda-hyb18m512160af-6.h"
47#include "hsmmc.h"
48#include "pm.h"
49#include "control.h"
50#include "common-board-devices.h"
51
52#define CONFIG_DISABLE_HFCLK 1
53
54#define SDP3430_TS_GPIO_IRQ_SDPV1 3
55#define SDP3430_TS_GPIO_IRQ_SDPV2 2
56
57#define ENABLE_VAUX3_DEDICATED 0x03
58#define ENABLE_VAUX3_DEV_GRP 0x20
59
60#define TWL4030_MSECURE_GPIO 22
61
62static uint32_t board_keymap[] = {
63 KEY(0, 0, KEY_LEFT),
64 KEY(0, 1, KEY_RIGHT),
65 KEY(0, 2, KEY_A),
66 KEY(0, 3, KEY_B),
67 KEY(0, 4, KEY_C),
68 KEY(1, 0, KEY_DOWN),
69 KEY(1, 1, KEY_UP),
70 KEY(1, 2, KEY_E),
71 KEY(1, 3, KEY_F),
72 KEY(1, 4, KEY_G),
73 KEY(2, 0, KEY_ENTER),
74 KEY(2, 1, KEY_I),
75 KEY(2, 2, KEY_J),
76 KEY(2, 3, KEY_K),
77 KEY(2, 4, KEY_3),
78 KEY(3, 0, KEY_M),
79 KEY(3, 1, KEY_N),
80 KEY(3, 2, KEY_O),
81 KEY(3, 3, KEY_P),
82 KEY(3, 4, KEY_Q),
83 KEY(4, 0, KEY_R),
84 KEY(4, 1, KEY_4),
85 KEY(4, 2, KEY_T),
86 KEY(4, 3, KEY_U),
87 KEY(4, 4, KEY_D),
88 KEY(5, 0, KEY_V),
89 KEY(5, 1, KEY_W),
90 KEY(5, 2, KEY_L),
91 KEY(5, 3, KEY_S),
92 KEY(5, 4, KEY_H),
93 0
94};
95
96static struct matrix_keymap_data board_map_data = {
97 .keymap = board_keymap,
98 .keymap_size = ARRAY_SIZE(board_keymap),
99};
100
101static struct twl4030_keypad_data sdp3430_kp_data = {
102 .keymap_data = &board_map_data,
103 .rows = 5,
104 .cols = 6,
105 .rep = 1,
106};
107
108#define SDP3430_LCD_PANEL_BACKLIGHT_GPIO 8
109#define SDP3430_LCD_PANEL_ENABLE_GPIO 5
110
111static void __init sdp3430_display_init(void)
112{
113 int r;
114
115 /*
116 * the backlight GPIO doesn't directly go to the panel, it enables
117 * an internal circuit on 3430sdp to create the signal V_BKL_28V,
118 * this is connected to LED+ pin of the sharp panel. This GPIO
119 * is left enabled in the board file, and not passed to the panel
120 * as platform_data.
121 */
122 r = gpio_request_one(SDP3430_LCD_PANEL_BACKLIGHT_GPIO,
123 GPIOF_OUT_INIT_HIGH, "LCD Backlight");
124 if (r)
125 pr_err("failed to get LCD Backlight GPIO\n");
126
127}
128
129static struct panel_sharp_ls037v7dw01_platform_data sdp3430_lcd_pdata = {
130 .name = "lcd",
131 .source = "dpi.0",
132
133 .data_lines = 16,
134
135 .resb_gpio = SDP3430_LCD_PANEL_ENABLE_GPIO,
136 .ini_gpio = -1,
137 .mo_gpio = -1,
138 .lr_gpio = -1,
139 .ud_gpio = -1,
140};
141
142static struct platform_device sdp3430_lcd_device = {
143 .name = "panel-sharp-ls037v7dw01",
144 .id = 0,
145 .dev.platform_data = &sdp3430_lcd_pdata,
146};
147
148static struct connector_dvi_platform_data sdp3430_dvi_connector_pdata = {
149 .name = "dvi",
150 .source = "tfp410.0",
151 .i2c_bus_num = -1,
152};
153
154static struct platform_device sdp3430_dvi_connector_device = {
155 .name = "connector-dvi",
156 .id = 0,
157 .dev.platform_data = &sdp3430_dvi_connector_pdata,
158};
159
160static struct encoder_tfp410_platform_data sdp3430_tfp410_pdata = {
161 .name = "tfp410.0",
162 .source = "dpi.0",
163 .data_lines = 24,
164 .power_down_gpio = -1,
165};
166
167static struct platform_device sdp3430_tfp410_device = {
168 .name = "tfp410",
169 .id = 0,
170 .dev.platform_data = &sdp3430_tfp410_pdata,
171};
172
173static struct connector_atv_platform_data sdp3430_tv_pdata = {
174 .name = "tv",
175 .source = "venc.0",
176 .connector_type = OMAP_DSS_VENC_TYPE_SVIDEO,
177 .invert_polarity = false,
178};
179
180static struct platform_device sdp3430_tv_connector_device = {
181 .name = "connector-analog-tv",
182 .id = 0,
183 .dev.platform_data = &sdp3430_tv_pdata,
184};
185
186static struct omap_dss_board_info sdp3430_dss_data = {
187 .default_display_name = "lcd",
188};
189
190static struct omap2_hsmmc_info mmc[] = {
191 {
192 .mmc = 1,
193 /* 8 bits (default) requires S6.3 == ON,
194 * so the SIM card isn't used; else 4 bits.
195 */
196 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
197 .gpio_wp = 4,
198 .deferred = true,
199 },
200 {
201 .mmc = 2,
202 .caps = MMC_CAP_4_BIT_DATA | MMC_CAP_8_BIT_DATA,
203 .gpio_wp = 7,
204 .deferred = true,
205 },
206 {} /* Terminator */
207};
208
209static struct omap_tw4030_pdata omap_twl4030_audio_data = {
210 .voice_connected = true,
211 .custom_routing = true,
212
213 .has_hs = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
214 .has_hf = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
215
216 .has_mainmic = true,
217 .has_submic = true,
218 .has_hsmic = true,
219 .has_linein = OMAP_TWL4030_LEFT | OMAP_TWL4030_RIGHT,
220};
221
222static int sdp3430_twl_gpio_setup(struct device *dev,
223 unsigned gpio, unsigned ngpio)
224{
225 /* gpio + 0 is "mmc0_cd" (input/IRQ),
226 * gpio + 1 is "mmc1_cd" (input/IRQ)
227 */
228 mmc[0].gpio_cd = gpio + 0;
229 mmc[1].gpio_cd = gpio + 1;
230 omap_hsmmc_late_init(mmc);
231
232 /* gpio + 7 is "sub_lcd_en_bkl" (output/PWM1) */
233 gpio_request_one(gpio + 7, GPIOF_OUT_INIT_LOW, "sub_lcd_en_bkl");
234
235 /* gpio + 15 is "sub_lcd_nRST" (output) */
236 gpio_request_one(gpio + 15, GPIOF_OUT_INIT_LOW, "sub_lcd_nRST");
237
238 omap_twl4030_audio_data.jack_detect = gpio + 2;
239 omap_twl4030_audio_init("SDP3430", &omap_twl4030_audio_data);
240
241 return 0;
242}
243
244static struct twl4030_gpio_platform_data sdp3430_gpio_data = {
245 .pulldowns = BIT(2) | BIT(6) | BIT(8) | BIT(13)
246 | BIT(16) | BIT(17),
247 .setup = sdp3430_twl_gpio_setup,
248};
249
250/* regulator consumer mappings */
251
252/* ads7846 on SPI */
253static struct regulator_consumer_supply sdp3430_vaux3_supplies[] = {
254 REGULATOR_SUPPLY("vcc", "spi1.0"),
255};
256
257static struct regulator_consumer_supply sdp3430_vmmc1_supplies[] = {
258 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.0"),
259};
260
261static struct regulator_consumer_supply sdp3430_vsim_supplies[] = {
262 REGULATOR_SUPPLY("vmmc_aux", "omap_hsmmc.0"),
263};
264
265static struct regulator_consumer_supply sdp3430_vmmc2_supplies[] = {
266 REGULATOR_SUPPLY("vmmc", "omap_hsmmc.1"),
267};
268
269/*
270 * Apply all the fixed voltages since most versions of U-Boot
271 * don't bother with that initialization.
272 */
273
274/* VAUX1 for mainboard (irda and sub-lcd) */
275static struct regulator_init_data sdp3430_vaux1 = {
276 .constraints = {
277 .min_uV = 2800000,
278 .max_uV = 2800000,
279 .apply_uV = true,
280 .valid_modes_mask = REGULATOR_MODE_NORMAL
281 | REGULATOR_MODE_STANDBY,
282 .valid_ops_mask = REGULATOR_CHANGE_MODE
283 | REGULATOR_CHANGE_STATUS,
284 },
285};
286
287/* VAUX2 for camera module */
288static struct regulator_init_data sdp3430_vaux2 = {
289 .constraints = {
290 .min_uV = 2800000,
291 .max_uV = 2800000,
292 .apply_uV = true,
293 .valid_modes_mask = REGULATOR_MODE_NORMAL
294 | REGULATOR_MODE_STANDBY,
295 .valid_ops_mask = REGULATOR_CHANGE_MODE
296 | REGULATOR_CHANGE_STATUS,
297 },
298};
299
300/* VAUX3 for LCD board */
301static struct regulator_init_data sdp3430_vaux3 = {
302 .constraints = {
303 .min_uV = 2800000,
304 .max_uV = 2800000,
305 .apply_uV = true,
306 .valid_modes_mask = REGULATOR_MODE_NORMAL
307 | REGULATOR_MODE_STANDBY,
308 .valid_ops_mask = REGULATOR_CHANGE_MODE
309 | REGULATOR_CHANGE_STATUS,
310 },
311 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vaux3_supplies),
312 .consumer_supplies = sdp3430_vaux3_supplies,
313};
314
315/* VAUX4 for OMAP VDD_CSI2 (camera) */
316static struct regulator_init_data sdp3430_vaux4 = {
317 .constraints = {
318 .min_uV = 1800000,
319 .max_uV = 1800000,
320 .apply_uV = true,
321 .valid_modes_mask = REGULATOR_MODE_NORMAL
322 | REGULATOR_MODE_STANDBY,
323 .valid_ops_mask = REGULATOR_CHANGE_MODE
324 | REGULATOR_CHANGE_STATUS,
325 },
326};
327
328/* VMMC1 for OMAP VDD_MMC1 (i/o) and MMC1 card */
329static struct regulator_init_data sdp3430_vmmc1 = {
330 .constraints = {
331 .min_uV = 1850000,
332 .max_uV = 3150000,
333 .valid_modes_mask = REGULATOR_MODE_NORMAL
334 | REGULATOR_MODE_STANDBY,
335 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
336 | REGULATOR_CHANGE_MODE
337 | REGULATOR_CHANGE_STATUS,
338 },
339 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc1_supplies),
340 .consumer_supplies = sdp3430_vmmc1_supplies,
341};
342
343/* VMMC2 for MMC2 card */
344static struct regulator_init_data sdp3430_vmmc2 = {
345 .constraints = {
346 .min_uV = 1850000,
347 .max_uV = 1850000,
348 .apply_uV = true,
349 .valid_modes_mask = REGULATOR_MODE_NORMAL
350 | REGULATOR_MODE_STANDBY,
351 .valid_ops_mask = REGULATOR_CHANGE_MODE
352 | REGULATOR_CHANGE_STATUS,
353 },
354 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vmmc2_supplies),
355 .consumer_supplies = sdp3430_vmmc2_supplies,
356};
357
358/* VSIM for OMAP VDD_MMC1A (i/o for DAT4..DAT7) */
359static struct regulator_init_data sdp3430_vsim = {
360 .constraints = {
361 .min_uV = 1800000,
362 .max_uV = 3000000,
363 .valid_modes_mask = REGULATOR_MODE_NORMAL
364 | REGULATOR_MODE_STANDBY,
365 .valid_ops_mask = REGULATOR_CHANGE_VOLTAGE
366 | REGULATOR_CHANGE_MODE
367 | REGULATOR_CHANGE_STATUS,
368 },
369 .num_consumer_supplies = ARRAY_SIZE(sdp3430_vsim_supplies),
370 .consumer_supplies = sdp3430_vsim_supplies,
371};
372
373static struct twl4030_platform_data sdp3430_twldata = {
374 /* platform_data for children goes here */
375 .gpio = &sdp3430_gpio_data,
376 .keypad = &sdp3430_kp_data,
377
378 .vaux1 = &sdp3430_vaux1,
379 .vaux2 = &sdp3430_vaux2,
380 .vaux3 = &sdp3430_vaux3,
381 .vaux4 = &sdp3430_vaux4,
382 .vmmc1 = &sdp3430_vmmc1,
383 .vmmc2 = &sdp3430_vmmc2,
384 .vsim = &sdp3430_vsim,
385};
386
387static int __init omap3430_i2c_init(void)
388{
389 /* i2c1 for PMIC only */
390 omap3_pmic_get_config(&sdp3430_twldata,
391 TWL_COMMON_PDATA_USB | TWL_COMMON_PDATA_BCI |
392 TWL_COMMON_PDATA_MADC | TWL_COMMON_PDATA_AUDIO,
393 TWL_COMMON_REGULATOR_VDAC | TWL_COMMON_REGULATOR_VPLL2);
394 sdp3430_twldata.vdac->constraints.apply_uV = true;
395 sdp3430_twldata.vpll2->constraints.apply_uV = true;
396 sdp3430_twldata.vpll2->constraints.name = "VDVI";
397
398 sdp3430_twldata.audio->codec->hs_extmute = 1;
399 sdp3430_twldata.audio->codec->hs_extmute_gpio = -EINVAL;
400
401 omap3_pmic_init("twl4030", &sdp3430_twldata);
402
403 /* i2c2 on camera connector (for sensor control) and optional isp1301 */
404 omap_register_i2c_bus(2, 400, NULL, 0);
405 /* i2c3 on display connector (for DVI, tfp410) */
406 omap_register_i2c_bus(3, 400, NULL, 0);
407 return 0;
408}
409
410#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
411
412static struct omap_smc91x_platform_data board_smc91x_data = {
413 .cs = 3,
414 .flags = GPMC_MUX_ADD_DATA | GPMC_TIMINGS_SMC91C96 |
415 IORESOURCE_IRQ_LOWLEVEL,
416};
417
418static void __init board_smc91x_init(void)
419{
420 if (omap_rev() > OMAP3430_REV_ES1_0)
421 board_smc91x_data.gpio_irq = 6;
422 else
423 board_smc91x_data.gpio_irq = 29;
424
425 gpmc_smc91x_init(&board_smc91x_data);
426}
427
428#else
429
430static inline void board_smc91x_init(void)
431{
432}
433
434#endif
435
436static void enable_board_wakeup_source(void)
437{
438 /* T2 interrupt line (keypad) */
439 omap_mux_init_signal("sys_nirq",
440 OMAP_WAKEUP_EN | OMAP_PIN_INPUT_PULLUP);
441}
442
443static struct usbhs_phy_data phy_data[] __initdata = {
444 {
445 .port = 1,
446 .reset_gpio = 57,
447 .vcc_gpio = -EINVAL,
448 },
449 {
450 .port = 2,
451 .reset_gpio = 61,
452 .vcc_gpio = -EINVAL,
453 },
454};
455
456static struct usbhs_omap_platform_data usbhs_bdata __initdata = {
457
458 .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
459 .port_mode[1] = OMAP_EHCI_PORT_MODE_PHY,
460};
461
462#ifdef CONFIG_OMAP_MUX
463static struct omap_board_mux board_mux[] __initdata = {
464 { .reg_offset = OMAP_MUX_TERMINATOR },
465};
466#else
467#define board_mux NULL
468#endif
469
470/*
471 * SDP3430 V2 Board CS organization
472 * Different from SDP3430 V1. Now 4 switches used to specify CS
473 *
474 * See also the Switch S8 settings in the comments.
475 */
476static char chip_sel_3430[][GPMC_CS_NUM] = {
477 {PDC_NOR, PDC_NAND, PDC_ONENAND, DBG_MPDB, 0, 0, 0, 0}, /* S8:1111 */
478 {PDC_ONENAND, PDC_NAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1110 */
479 {PDC_NAND, PDC_ONENAND, PDC_NOR, DBG_MPDB, 0, 0, 0, 0}, /* S8:1101 */
480};
481
482static struct mtd_partition sdp_nor_partitions[] = {
483 /* bootloader (U-Boot, etc) in first sector */
484 {
485 .name = "Bootloader-NOR",
486 .offset = 0,
487 .size = SZ_256K,
488 .mask_flags = MTD_WRITEABLE, /* force read-only */
489 },
490 /* bootloader params in the next sector */
491 {
492 .name = "Params-NOR",
493 .offset = MTDPART_OFS_APPEND,
494 .size = SZ_256K,
495 .mask_flags = 0,
496 },
497 /* kernel */
498 {
499 .name = "Kernel-NOR",
500 .offset = MTDPART_OFS_APPEND,
501 .size = SZ_2M,
502 .mask_flags = 0
503 },
504 /* file system */
505 {
506 .name = "Filesystem-NOR",
507 .offset = MTDPART_OFS_APPEND,
508 .size = MTDPART_SIZ_FULL,
509 .mask_flags = 0
510 }
511};
512
513static struct mtd_partition sdp_onenand_partitions[] = {
514 {
515 .name = "X-Loader-OneNAND",
516 .offset = 0,
517 .size = 4 * (64 * 2048),
518 .mask_flags = MTD_WRITEABLE /* force read-only */
519 },
520 {
521 .name = "U-Boot-OneNAND",
522 .offset = MTDPART_OFS_APPEND,
523 .size = 2 * (64 * 2048),
524 .mask_flags = MTD_WRITEABLE /* force read-only */
525 },
526 {
527 .name = "U-Boot Environment-OneNAND",
528 .offset = MTDPART_OFS_APPEND,
529 .size = 1 * (64 * 2048),
530 },
531 {
532 .name = "Kernel-OneNAND",
533 .offset = MTDPART_OFS_APPEND,
534 .size = 16 * (64 * 2048),
535 },
536 {
537 .name = "File System-OneNAND",
538 .offset = MTDPART_OFS_APPEND,
539 .size = MTDPART_SIZ_FULL,
540 },
541};
542
543static struct mtd_partition sdp_nand_partitions[] = {
544 /* All the partition sizes are listed in terms of NAND block size */
545 {
546 .name = "X-Loader-NAND",
547 .offset = 0,
548 .size = 4 * (64 * 2048),
549 .mask_flags = MTD_WRITEABLE, /* force read-only */
550 },
551 {
552 .name = "U-Boot-NAND",
553 .offset = MTDPART_OFS_APPEND, /* Offset = 0x80000 */
554 .size = 10 * (64 * 2048),
555 .mask_flags = MTD_WRITEABLE, /* force read-only */
556 },
557 {
558 .name = "Boot Env-NAND",
559
560 .offset = MTDPART_OFS_APPEND, /* Offset = 0x1c0000 */
561 .size = 6 * (64 * 2048),
562 },
563 {
564 .name = "Kernel-NAND",
565 .offset = MTDPART_OFS_APPEND, /* Offset = 0x280000 */
566 .size = 40 * (64 * 2048),
567 },
568 {
569 .name = "File System - NAND",
570 .size = MTDPART_SIZ_FULL,
571 .offset = MTDPART_OFS_APPEND, /* Offset = 0x780000 */
572 },
573};
574
575static struct flash_partitions sdp_flash_partitions[] = {
576 {
577 .parts = sdp_nor_partitions,
578 .nr_parts = ARRAY_SIZE(sdp_nor_partitions),
579 },
580 {
581 .parts = sdp_onenand_partitions,
582 .nr_parts = ARRAY_SIZE(sdp_onenand_partitions),
583 },
584 {
585 .parts = sdp_nand_partitions,
586 .nr_parts = ARRAY_SIZE(sdp_nand_partitions),
587 },
588};
589
590static void __init omap_3430sdp_init(void)
591{
592 int gpio_pendown;
593
594 omap3_mux_init(board_mux, OMAP_PACKAGE_CBB);
595 omap_hsmmc_init(mmc);
596 omap3430_i2c_init();
597 omap_display_init(&sdp3430_dss_data);
598 platform_device_register(&sdp3430_lcd_device);
599 platform_device_register(&sdp3430_tfp410_device);
600 platform_device_register(&sdp3430_dvi_connector_device);
601 platform_device_register(&sdp3430_tv_connector_device);
602
603 if (omap_rev() > OMAP3430_REV_ES1_0)
604 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV2;
605 else
606 gpio_pendown = SDP3430_TS_GPIO_IRQ_SDPV1;
607 omap_ads7846_init(1, gpio_pendown, 310, NULL);
608 omap_serial_init();
609 omap_sdrc_init(hyb18m512160af6_sdrc_params, NULL);
610 usb_bind_phy("musb-hdrc.0.auto", 0, "twl4030_usb");
611 usb_musb_init(NULL);
612 board_smc91x_init();
613 board_flash_init(sdp_flash_partitions, chip_sel_3430, 0);
614 sdp3430_display_init();
615 enable_board_wakeup_source();
616
617 usbhs_init_phys(phy_data, ARRAY_SIZE(phy_data));
618 usbhs_init(&usbhs_bdata);
619}
620
621MACHINE_START(OMAP_3430SDP, "OMAP3430 3430SDP board")
622 /* Maintainer: Syed Khasim - Texas Instruments Inc */
623 .atag_offset = 0x100,
624 .reserve = omap_reserve,
625 .map_io = omap3_map_io,
626 .init_early = omap3430_init_early,
627 .init_irq = omap3_init_irq,
628 .init_machine = omap_3430sdp_init,
629 .init_late = omap3430_init_late,
630 .init_time = omap3_sync32k_timer_init,
631 .restart = omap3xxx_restart,
632MACHINE_END
diff --git a/arch/arm/mach-omap2/board-am3517crane.c b/arch/arm/mach-omap2/board-am3517crane.c
index 212c3160de18..8168ddabaeda 100644
--- a/arch/arm/mach-omap2/board-am3517crane.c
+++ b/arch/arm/mach-omap2/board-am3517crane.c
@@ -24,6 +24,7 @@
24#include <linux/mtd/mtd.h> 24#include <linux/mtd/mtd.h>
25#include <linux/mtd/nand.h> 25#include <linux/mtd/nand.h>
26#include <linux/mtd/partitions.h> 26#include <linux/mtd/partitions.h>
27#include <linux/omap-gpmc.h>
27 28
28#include <asm/mach-types.h> 29#include <asm/mach-types.h>
29#include <asm/mach/arch.h> 30#include <asm/mach/arch.h>
diff --git a/arch/arm/mach-omap2/board-cm-t35.c b/arch/arm/mach-omap2/board-cm-t35.c
index c6df8eec4553..91738a14ecbe 100644
--- a/arch/arm/mach-omap2/board-cm-t35.c
+++ b/arch/arm/mach-omap2/board-cm-t35.c
@@ -25,6 +25,7 @@
25#include <linux/input/matrix_keypad.h> 25#include <linux/input/matrix_keypad.h>
26#include <linux/delay.h> 26#include <linux/delay.h>
27#include <linux/gpio.h> 27#include <linux/gpio.h>
28#include <linux/omap-gpmc.h>
28#include <linux/platform_data/gpio-omap.h> 29#include <linux/platform_data/gpio-omap.h>
29 30
30#include <linux/platform_data/at24.h> 31#include <linux/platform_data/at24.h>
@@ -51,8 +52,6 @@
51#include "sdram-micron-mt46h32m32lf-6.h" 52#include "sdram-micron-mt46h32m32lf-6.h"
52#include "hsmmc.h" 53#include "hsmmc.h"
53#include "common-board-devices.h" 54#include "common-board-devices.h"
54#include "gpmc.h"
55#include "gpmc-nand.h"
56 55
57#define CM_T35_GPIO_PENDOWN 57 56#define CM_T35_GPIO_PENDOWN 57
58#define SB_T35_USB_HUB_RESET_GPIO 167 57#define SB_T35_USB_HUB_RESET_GPIO 167
diff --git a/arch/arm/mach-omap2/board-cm-t3517.c b/arch/arm/mach-omap2/board-cm-t3517.c
index 8a2c1677964c..794756df8529 100644
--- a/arch/arm/mach-omap2/board-cm-t3517.c
+++ b/arch/arm/mach-omap2/board-cm-t3517.c
@@ -28,6 +28,7 @@
28#include <linux/delay.h> 28#include <linux/delay.h>
29#include <linux/gpio.h> 29#include <linux/gpio.h>
30#include <linux/leds.h> 30#include <linux/leds.h>
31#include <linux/omap-gpmc.h>
31#include <linux/rtc-v3020.h> 32#include <linux/rtc-v3020.h>
32#include <linux/mtd/mtd.h> 33#include <linux/mtd/mtd.h>
33#include <linux/mtd/nand.h> 34#include <linux/mtd/nand.h>
@@ -41,7 +42,6 @@
41 42
42#include "common.h" 43#include "common.h"
43#include <linux/platform_data/mtd-nand-omap2.h> 44#include <linux/platform_data/mtd-nand-omap2.h>
44#include "gpmc.h"
45 45
46#include "am35xx.h" 46#include "am35xx.h"
47 47
@@ -50,7 +50,6 @@
50#include "hsmmc.h" 50#include "hsmmc.h"
51#include "common-board-devices.h" 51#include "common-board-devices.h"
52#include "am35xx-emac.h" 52#include "am35xx-emac.h"
53#include "gpmc-nand.h"
54 53
55#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE) 54#if defined(CONFIG_LEDS_GPIO) || defined(CONFIG_LEDS_GPIO_MODULE)
56static struct gpio_led cm_t3517_leds[] = { 55static struct gpio_led cm_t3517_leds[] = {
diff --git a/arch/arm/mach-omap2/board-flash.c b/arch/arm/mach-omap2/board-flash.c
index 2d245c2e641c..70b21cc279ba 100644
--- a/arch/arm/mach-omap2/board-flash.c
+++ b/arch/arm/mach-omap2/board-flash.c
@@ -13,6 +13,7 @@
13 */ 13 */
14 14
15#include <linux/kernel.h> 15#include <linux/kernel.h>
16#include <linux/omap-gpmc.h>
16#include <linux/platform_device.h> 17#include <linux/platform_device.h>
17#include <linux/mtd/physmap.h> 18#include <linux/mtd/physmap.h>
18#include <linux/io.h> 19#include <linux/io.h>
@@ -23,8 +24,6 @@
23#include "soc.h" 24#include "soc.h"
24#include "common.h" 25#include "common.h"
25#include "board-flash.h" 26#include "board-flash.h"
26#include "gpmc-onenand.h"
27#include "gpmc-nand.h"
28 27
29#define REG_FPGA_REV 0x10 28#define REG_FPGA_REV 0x10
30#define REG_FPGA_DIP_SWITCH_INPUT2 0x60 29#define REG_FPGA_DIP_SWITCH_INPUT2 0x60
diff --git a/arch/arm/mach-omap2/board-flash.h b/arch/arm/mach-omap2/board-flash.h
index 2fb5d41a9fae..ea9aaebe11e7 100644
--- a/arch/arm/mach-omap2/board-flash.h
+++ b/arch/arm/mach-omap2/board-flash.h
@@ -12,7 +12,6 @@
12 */ 12 */
13#include <linux/mtd/mtd.h> 13#include <linux/mtd/mtd.h>
14#include <linux/mtd/partitions.h> 14#include <linux/mtd/partitions.h>
15#include "gpmc.h"
16 15
17#define PDC_NOR 1 16#define PDC_NOR 1
18#define PDC_NAND 2 17#define PDC_NAND 2
diff --git a/arch/arm/mach-omap2/board-n8x0.c b/arch/arm/mach-omap2/board-n8x0.c
index e0ad64fde20e..b6443a4e0c78 100644
--- a/arch/arm/mach-omap2/board-n8x0.c
+++ b/arch/arm/mach-omap2/board-n8x0.c
@@ -23,7 +23,6 @@
23#include <linux/usb/musb.h> 23#include <linux/usb/musb.h>
24#include <linux/mmc/host.h> 24#include <linux/mmc/host.h>
25#include <linux/platform_data/spi-omap2-mcspi.h> 25#include <linux/platform_data/spi-omap2-mcspi.h>
26#include <linux/platform_data/mtd-onenand-omap2.h>
27#include <linux/platform_data/mmc-omap.h> 26#include <linux/platform_data/mmc-omap.h>
28#include <linux/mfd/menelaus.h> 27#include <linux/mfd/menelaus.h>
29#include <sound/tlv320aic3x.h> 28#include <sound/tlv320aic3x.h>
@@ -34,7 +33,6 @@
34#include "common.h" 33#include "common.h"
35#include "mmc.h" 34#include "mmc.h"
36#include "soc.h" 35#include "soc.h"
37#include "gpmc-onenand.h"
38#include "common-board-devices.h" 36#include "common-board-devices.h"
39 37
40#define TUSB6010_ASYNC_CS 1 38#define TUSB6010_ASYNC_CS 1
diff --git a/arch/arm/mach-omap2/board-omap3pandora.c b/arch/arm/mach-omap2/board-omap3pandora.c
index f32201656cf3..7f1708738c30 100644
--- a/arch/arm/mach-omap2/board-omap3pandora.c
+++ b/arch/arm/mach-omap2/board-omap3pandora.c
@@ -24,6 +24,7 @@
24#include <linux/spi/spi.h> 24#include <linux/spi/spi.h>
25#include <linux/regulator/machine.h> 25#include <linux/regulator/machine.h>
26#include <linux/i2c/twl.h> 26#include <linux/i2c/twl.h>
27#include <linux/omap-gpmc.h>
27#include <linux/wl12xx.h> 28#include <linux/wl12xx.h>
28#include <linux/mtd/partitions.h> 29#include <linux/mtd/partitions.h>
29#include <linux/mtd/nand.h> 30#include <linux/mtd/nand.h>
@@ -51,7 +52,6 @@
51#include "sdram-micron-mt46h32m32lf-6.h" 52#include "sdram-micron-mt46h32m32lf-6.h"
52#include "hsmmc.h" 53#include "hsmmc.h"
53#include "common-board-devices.h" 54#include "common-board-devices.h"
54#include "gpmc-nand.h"
55 55
56#define PANDORA_WIFI_IRQ_GPIO 21 56#define PANDORA_WIFI_IRQ_GPIO 21
57#define PANDORA_WIFI_NRESET_GPIO 23 57#define PANDORA_WIFI_NRESET_GPIO 23
diff --git a/arch/arm/mach-omap2/board-rx51-peripherals.c b/arch/arm/mach-omap2/board-rx51-peripherals.c
index 3d5040f82e90..03502abe4f2e 100644
--- a/arch/arm/mach-omap2/board-rx51-peripherals.c
+++ b/arch/arm/mach-omap2/board-rx51-peripherals.c
@@ -23,6 +23,7 @@
23#include <linux/regulator/machine.h> 23#include <linux/regulator/machine.h>
24#include <linux/gpio.h> 24#include <linux/gpio.h>
25#include <linux/gpio_keys.h> 25#include <linux/gpio_keys.h>
26#include <linux/omap-gpmc.h>
26#include <linux/mmc/host.h> 27#include <linux/mmc/host.h>
27#include <linux/power/isp1704_charger.h> 28#include <linux/power/isp1704_charger.h>
28#include <linux/platform_data/spi-omap2-mcspi.h> 29#include <linux/platform_data/spi-omap2-mcspi.h>
@@ -32,7 +33,6 @@
32 33
33#include "common.h" 34#include "common.h"
34#include <linux/omap-dma.h> 35#include <linux/omap-dma.h>
35#include "gpmc-smc91x.h"
36 36
37#include "board-rx51.h" 37#include "board-rx51.h"
38 38
@@ -55,8 +55,6 @@
55#include "omap-pm.h" 55#include "omap-pm.h"
56#include "hsmmc.h" 56#include "hsmmc.h"
57#include "common-board-devices.h" 57#include "common-board-devices.h"
58#include "gpmc.h"
59#include "gpmc-onenand.h"
60#include "soc.h" 58#include "soc.h"
61#include "omap-secure.h" 59#include "omap-secure.h"
62 60
@@ -1144,33 +1142,6 @@ static struct omap_onenand_platform_data board_onenand_data[] = {
1144}; 1142};
1145#endif 1143#endif
1146 1144
1147#if defined(CONFIG_SMC91X) || defined(CONFIG_SMC91X_MODULE)
1148
1149static struct omap_smc91x_platform_data board_smc91x_data = {
1150 .cs = 1,
1151 .gpio_irq = 54,
1152 .gpio_pwrdwn = 86,
1153 .gpio_reset = 164,
1154 .flags = GPMC_TIMINGS_SMC91C96 | IORESOURCE_IRQ_HIGHLEVEL,
1155};
1156
1157static void __init board_smc91x_init(void)
1158{
1159 omap_mux_init_gpio(54, OMAP_PIN_INPUT_PULLDOWN);
1160 omap_mux_init_gpio(86, OMAP_PIN_OUTPUT);
1161 omap_mux_init_gpio(164, OMAP_PIN_OUTPUT);
1162
1163 gpmc_smc91x_init(&board_smc91x_data);
1164}
1165
1166#else
1167
1168static inline void board_smc91x_init(void)
1169{
1170}
1171
1172#endif
1173
1174static struct gpio rx51_wl1251_gpios[] __initdata = { 1145static struct gpio rx51_wl1251_gpios[] __initdata = {
1175 { RX51_WL1251_IRQ_GPIO, GPIOF_IN, "wl1251 irq" }, 1146 { RX51_WL1251_IRQ_GPIO, GPIOF_IN, "wl1251 irq" },
1176}; 1147};
@@ -1301,7 +1272,6 @@ void __init rx51_peripherals_init(void)
1301 rx51_i2c_init(); 1272 rx51_i2c_init();
1302 regulator_has_full_constraints(); 1273 regulator_has_full_constraints();
1303 gpmc_onenand_init(board_onenand_data); 1274 gpmc_onenand_init(board_onenand_data);
1304 board_smc91x_init();
1305 rx51_add_gpio_keys(); 1275 rx51_add_gpio_keys();
1306 rx51_init_wl1251(); 1276 rx51_init_wl1251();
1307 rx51_init_tsc2005(); 1277 rx51_init_tsc2005();
diff --git a/arch/arm/mach-omap2/board-ti8168evm.c b/arch/arm/mach-omap2/board-ti8168evm.c
deleted file mode 100644
index 6273c286e1d8..000000000000
--- a/arch/arm/mach-omap2/board-ti8168evm.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * Code for TI8168/TI8148 EVM.
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc. - http://www.ti.com/
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/platform_device.h>
18#include <linux/usb/musb.h>
19
20#include <asm/mach-types.h>
21#include <asm/mach/arch.h>
22#include <asm/mach/map.h>
23
24#include "common.h"
25
26static struct omap_musb_board_data musb_board_data = {
27 .set_phy_power = ti81xx_musb_phy_power,
28 .interface_type = MUSB_INTERFACE_ULPI,
29 .mode = MUSB_OTG,
30 .power = 500,
31};
32
33static void __init ti81xx_evm_init(void)
34{
35 omap_serial_init();
36 omap_sdrc_init(NULL, NULL);
37 usb_musb_init(&musb_board_data);
38}
39
40MACHINE_START(TI8168EVM, "ti8168evm")
41 /* Maintainer: Texas Instruments */
42 .atag_offset = 0x100,
43 .map_io = ti81xx_map_io,
44 .init_early = ti81xx_init_early,
45 .init_irq = ti81xx_init_irq,
46 .init_time = omap3_sync32k_timer_init,
47 .init_machine = ti81xx_evm_init,
48 .init_late = ti81xx_init_late,
49 .restart = omap44xx_restart,
50MACHINE_END
51
52MACHINE_START(TI8148EVM, "ti8148evm")
53 /* Maintainer: Texas Instruments */
54 .atag_offset = 0x100,
55 .map_io = ti81xx_map_io,
56 .init_early = ti81xx_init_early,
57 .init_irq = ti81xx_init_irq,
58 .init_time = omap3_sync32k_timer_init,
59 .init_machine = ti81xx_evm_init,
60 .init_late = ti81xx_init_late,
61 .restart = omap44xx_restart,
62MACHINE_END
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index 492ef1607115..a7bc4ce81e19 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -411,3 +411,29 @@ static int __init omap2_init_devices(void)
411 return 0; 411 return 0;
412} 412}
413omap_arch_initcall(omap2_init_devices); 413omap_arch_initcall(omap2_init_devices);
414
415static int __init omap_gpmc_init(void)
416{
417 struct omap_hwmod *oh;
418 struct platform_device *pdev;
419 char *oh_name = "gpmc";
420
421 /*
422 * if the board boots up with a populated DT, do not
423 * manually add the device from this initcall
424 */
425 if (of_have_populated_dt())
426 return -ENODEV;
427
428 oh = omap_hwmod_lookup(oh_name);
429 if (!oh) {
430 pr_err("Could not look up %s\n", oh_name);
431 return -ENODEV;
432 }
433
434 pdev = omap_device_build("omap-gpmc", -1, oh, NULL, 0);
435 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
436
437 return PTR_RET(pdev);
438}
439omap_postcore_initcall(omap_gpmc_init);
diff --git a/arch/arm/mach-omap2/gpmc-nand.c b/arch/arm/mach-omap2/gpmc-nand.c
index cb7764314f17..d5951b17b736 100644
--- a/arch/arm/mach-omap2/gpmc-nand.c
+++ b/arch/arm/mach-omap2/gpmc-nand.c
@@ -12,14 +12,13 @@
12#include <linux/kernel.h> 12#include <linux/kernel.h>
13#include <linux/platform_device.h> 13#include <linux/platform_device.h>
14#include <linux/io.h> 14#include <linux/io.h>
15#include <linux/omap-gpmc.h>
15#include <linux/mtd/nand.h> 16#include <linux/mtd/nand.h>
16#include <linux/platform_data/mtd-nand-omap2.h> 17#include <linux/platform_data/mtd-nand-omap2.h>
17 18
18#include <asm/mach/flash.h> 19#include <asm/mach/flash.h>
19 20
20#include "gpmc.h"
21#include "soc.h" 21#include "soc.h"
22#include "gpmc-nand.h"
23 22
24/* minimum size for IO mapping */ 23/* minimum size for IO mapping */
25#define NAND_IO_SIZE 4 24#define NAND_IO_SIZE 4
diff --git a/arch/arm/mach-omap2/gpmc-nand.h b/arch/arm/mach-omap2/gpmc-nand.h
deleted file mode 100644
index d59e1281e851..000000000000
--- a/arch/arm/mach-omap2/gpmc-nand.h
+++ /dev/null
@@ -1,27 +0,0 @@
1/*
2 * arch/arm/mach-omap2/gpmc-nand.h
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __OMAP2_GPMC_NAND_H
11#define __OMAP2_GPMC_NAND_H
12
13#include "gpmc.h"
14#include <linux/platform_data/mtd-nand-omap2.h>
15
16#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
17extern int gpmc_nand_init(struct omap_nand_platform_data *d,
18 struct gpmc_timings *gpmc_t);
19#else
20static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
21 struct gpmc_timings *gpmc_t)
22{
23 return 0;
24}
25#endif
26
27#endif
diff --git a/arch/arm/mach-omap2/gpmc-onenand.c b/arch/arm/mach-omap2/gpmc-onenand.c
index 8b6876c98ce1..53d197e0c1f3 100644
--- a/arch/arm/mach-omap2/gpmc-onenand.c
+++ b/arch/arm/mach-omap2/gpmc-onenand.c
@@ -15,14 +15,13 @@
15#include <linux/platform_device.h> 15#include <linux/platform_device.h>
16#include <linux/mtd/onenand_regs.h> 16#include <linux/mtd/onenand_regs.h>
17#include <linux/io.h> 17#include <linux/io.h>
18#include <linux/omap-gpmc.h>
18#include <linux/platform_data/mtd-onenand-omap2.h> 19#include <linux/platform_data/mtd-onenand-omap2.h>
19#include <linux/err.h> 20#include <linux/err.h>
20 21
21#include <asm/mach/flash.h> 22#include <asm/mach/flash.h>
22 23
23#include "gpmc.h"
24#include "soc.h" 24#include "soc.h"
25#include "gpmc-onenand.h"
26 25
27#define ONENAND_IO_SIZE SZ_128K 26#define ONENAND_IO_SIZE SZ_128K
28 27
diff --git a/arch/arm/mach-omap2/gpmc-onenand.h b/arch/arm/mach-omap2/gpmc-onenand.h
deleted file mode 100644
index 216f23a8b45c..000000000000
--- a/arch/arm/mach-omap2/gpmc-onenand.h
+++ /dev/null
@@ -1,24 +0,0 @@
1/*
2 * arch/arm/mach-omap2/gpmc-onenand.h
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10#ifndef __OMAP2_GPMC_ONENAND_H
11#define __OMAP2_GPMC_ONENAND_H
12
13#include <linux/platform_data/mtd-onenand-omap2.h>
14
15#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
16extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
17#else
18#define board_onenand_data NULL
19static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
20{
21}
22#endif
23
24#endif
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.c b/arch/arm/mach-omap2/gpmc-smc91x.c
deleted file mode 100644
index 61a063595e66..000000000000
--- a/arch/arm/mach-omap2/gpmc-smc91x.c
+++ /dev/null
@@ -1,186 +0,0 @@
1/*
2 * linux/arch/arm/mach-omap2/gpmc-smc91x.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Contact: Tony Lindgren
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11
12#include <linux/kernel.h>
13#include <linux/platform_device.h>
14#include <linux/gpio.h>
15#include <linux/delay.h>
16#include <linux/interrupt.h>
17#include <linux/io.h>
18#include <linux/smc91x.h>
19
20#include "gpmc.h"
21#include "gpmc-smc91x.h"
22
23#include "soc.h"
24
25static struct omap_smc91x_platform_data *gpmc_cfg;
26
27static struct resource gpmc_smc91x_resources[] = {
28 [0] = {
29 .flags = IORESOURCE_MEM,
30 },
31 [1] = {
32 .flags = IORESOURCE_IRQ,
33 },
34};
35
36static struct smc91x_platdata gpmc_smc91x_info = {
37 .flags = SMC91X_USE_16BIT | SMC91X_NOWAIT | SMC91X_IO_SHIFT_0,
38 .leda = RPC_LED_100_10,
39 .ledb = RPC_LED_TX_RX,
40};
41
42static struct platform_device gpmc_smc91x_device = {
43 .name = "smc91x",
44 .id = -1,
45 .dev = {
46 .platform_data = &gpmc_smc91x_info,
47 },
48 .num_resources = ARRAY_SIZE(gpmc_smc91x_resources),
49 .resource = gpmc_smc91x_resources,
50};
51
52static struct gpmc_settings smc91x_settings = {
53 .device_width = GPMC_DEVWIDTH_16BIT,
54};
55
56/*
57 * Set the gpmc timings for smc91c96. The timings are taken
58 * from the data sheet available at:
59 * http://www.smsc.com/main/catalog/lan91c96.html
60 * REVISIT: Level shifters can add at least to the access latency.
61 */
62static int smc91c96_gpmc_retime(void)
63{
64 struct gpmc_timings t;
65 struct gpmc_device_timings dev_t;
66 const int t3 = 10; /* Figure 12.2 read and 12.4 write */
67 const int t4_r = 20; /* Figure 12.2 read */
68 const int t4_w = 5; /* Figure 12.4 write */
69 const int t5 = 25; /* Figure 12.2 read */
70 const int t6 = 15; /* Figure 12.2 read */
71 const int t7 = 5; /* Figure 12.4 write */
72 const int t8 = 5; /* Figure 12.4 write */
73 const int t20 = 185; /* Figure 12.2 read and 12.4 write */
74
75 /*
76 * FIXME: Calculate the address and data bus muxed timings.
77 * Note that at least adv_rd_off needs to be changed according
78 * to omap3430 TRM Figure 11-11. Are the sdp boards using the
79 * FPGA in between smc91x and omap as the timings are different
80 * from above?
81 */
82 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
83 return 0;
84
85 memset(&dev_t, 0, sizeof(dev_t));
86
87 dev_t.t_oeasu = t3 * 1000;
88 dev_t.t_oe = t5 * 1000;
89 dev_t.t_cez_r = t4_r * 1000;
90 dev_t.t_oez = t6 * 1000;
91 dev_t.t_rd_cycle = (t20 - t3) * 1000;
92
93 dev_t.t_weasu = t3 * 1000;
94 dev_t.t_wpl = t7 * 1000;
95 dev_t.t_wph = t8 * 1000;
96 dev_t.t_cez_w = t4_w * 1000;
97 dev_t.t_wr_cycle = (t20 - t3) * 1000;
98
99 gpmc_calc_timings(&t, &smc91x_settings, &dev_t);
100
101 return gpmc_cs_set_timings(gpmc_cfg->cs, &t);
102}
103
104/*
105 * Initialize smc91x device connected to the GPMC. Note that we
106 * assume that pin multiplexing is done in the board-*.c file,
107 * or in the bootloader.
108 */
109void __init gpmc_smc91x_init(struct omap_smc91x_platform_data *board_data)
110{
111 unsigned long cs_mem_base;
112 int ret;
113
114 gpmc_cfg = board_data;
115
116 if (gpmc_cfg->flags & GPMC_TIMINGS_SMC91C96)
117 gpmc_cfg->retime = smc91c96_gpmc_retime;
118
119 if (gpmc_cs_request(gpmc_cfg->cs, SZ_16M, &cs_mem_base) < 0) {
120 printk(KERN_ERR "Failed to request GPMC mem for smc91x\n");
121 return;
122 }
123
124 gpmc_smc91x_resources[0].start = cs_mem_base + 0x300;
125 gpmc_smc91x_resources[0].end = cs_mem_base + 0x30f;
126 gpmc_smc91x_resources[1].flags |= (gpmc_cfg->flags & IRQF_TRIGGER_MASK);
127
128 if (gpmc_cfg->flags & GPMC_MUX_ADD_DATA)
129 smc91x_settings.mux_add_data = GPMC_MUX_AD;
130 if (gpmc_cfg->flags & GPMC_READ_MON)
131 smc91x_settings.wait_on_read = true;
132 if (gpmc_cfg->flags & GPMC_WRITE_MON)
133 smc91x_settings.wait_on_write = true;
134 if (gpmc_cfg->wait_pin)
135 smc91x_settings.wait_pin = gpmc_cfg->wait_pin;
136 ret = gpmc_cs_program_settings(gpmc_cfg->cs, &smc91x_settings);
137 if (ret < 0)
138 goto free1;
139
140 if (gpmc_cfg->retime) {
141 ret = gpmc_cfg->retime();
142 if (ret != 0)
143 goto free1;
144 }
145
146 if (gpio_request_one(gpmc_cfg->gpio_irq, GPIOF_IN, "SMC91X irq") < 0)
147 goto free1;
148
149 gpmc_smc91x_resources[1].start = gpio_to_irq(gpmc_cfg->gpio_irq);
150
151 if (gpmc_cfg->gpio_pwrdwn) {
152 ret = gpio_request_one(gpmc_cfg->gpio_pwrdwn,
153 GPIOF_OUT_INIT_LOW, "SMC91X powerdown");
154 if (ret)
155 goto free2;
156 }
157
158 if (gpmc_cfg->gpio_reset) {
159 ret = gpio_request_one(gpmc_cfg->gpio_reset,
160 GPIOF_OUT_INIT_LOW, "SMC91X reset");
161 if (ret)
162 goto free3;
163
164 gpio_set_value(gpmc_cfg->gpio_reset, 1);
165 msleep(100);
166 gpio_set_value(gpmc_cfg->gpio_reset, 0);
167 }
168
169 if (platform_device_register(&gpmc_smc91x_device) < 0) {
170 printk(KERN_ERR "Unable to register smc91x device\n");
171 gpio_free(gpmc_cfg->gpio_reset);
172 goto free3;
173 }
174
175 return;
176
177free3:
178 if (gpmc_cfg->gpio_pwrdwn)
179 gpio_free(gpmc_cfg->gpio_pwrdwn);
180free2:
181 gpio_free(gpmc_cfg->gpio_irq);
182free1:
183 gpmc_cs_free(gpmc_cfg->cs);
184
185 printk(KERN_ERR "Could not initialize smc91x\n");
186}
diff --git a/arch/arm/mach-omap2/gpmc-smc91x.h b/arch/arm/mach-omap2/gpmc-smc91x.h
deleted file mode 100644
index b64fbee4d567..000000000000
--- a/arch/arm/mach-omap2/gpmc-smc91x.h
+++ /dev/null
@@ -1,42 +0,0 @@
1/*
2 * arch/arm/plat-omap/include/mach/gpmc-smc91x.h
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARCH_OMAP_GPMC_SMC91X_H__
12
13#define GPMC_TIMINGS_SMC91C96 (1 << 4)
14#define GPMC_MUX_ADD_DATA (1 << 5) /* GPMC_CONFIG1_MUXADDDATA */
15#define GPMC_READ_MON (1 << 6) /* GPMC_CONFIG1_WAIT_READ_MON */
16#define GPMC_WRITE_MON (1 << 7) /* GPMC_CONFIG1_WAIT_WRITE_MON */
17
18struct omap_smc91x_platform_data {
19 int cs;
20 int gpio_irq;
21 int gpio_pwrdwn;
22 int gpio_reset;
23 int wait_pin; /* Optional GPMC_CONFIG1_WAITPINSELECT */
24 u32 flags;
25 int (*retime)(void);
26};
27
28#if defined(CONFIG_SMC91X) || \
29 defined(CONFIG_SMC91X_MODULE)
30
31extern void gpmc_smc91x_init(struct omap_smc91x_platform_data *d);
32
33#else
34
35#define board_smc91x_data NULL
36
37static inline void gpmc_smc91x_init(struct omap_smc91x_platform_data *d)
38{
39}
40
41#endif
42#endif
diff --git a/arch/arm/mach-omap2/gpmc.h b/arch/arm/mach-omap2/gpmc.h
index 707f6d58edd5..9caa41a6cb04 100644
--- a/arch/arm/mach-omap2/gpmc.h
+++ b/arch/arm/mach-omap2/gpmc.h
@@ -6,226 +6,9 @@
6 * This program is free software; you can redistribute it and/or modify 6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as 7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation. 8 * published by the Free Software Foundation.
9 *
10 * Do not include this file in any new code, this will get removed
11 * once omap3 boots in device tree only mode.
12 *
9 */ 13 */
10 14#include <linux/omap-gpmc.h>
11#ifndef __OMAP2_GPMC_H
12#define __OMAP2_GPMC_H
13
14#include <linux/platform_data/mtd-nand-omap2.h>
15
16/* Maximum Number of Chip Selects */
17#define GPMC_CS_NUM 8
18
19#define GPMC_CS_CONFIG1 0x00
20#define GPMC_CS_CONFIG2 0x04
21#define GPMC_CS_CONFIG3 0x08
22#define GPMC_CS_CONFIG4 0x0c
23#define GPMC_CS_CONFIG5 0x10
24#define GPMC_CS_CONFIG6 0x14
25#define GPMC_CS_CONFIG7 0x18
26#define GPMC_CS_NAND_COMMAND 0x1c
27#define GPMC_CS_NAND_ADDRESS 0x20
28#define GPMC_CS_NAND_DATA 0x24
29
30/* Control Commands */
31#define GPMC_CONFIG_RDY_BSY 0x00000001
32#define GPMC_CONFIG_DEV_SIZE 0x00000002
33#define GPMC_CONFIG_DEV_TYPE 0x00000003
34#define GPMC_SET_IRQ_STATUS 0x00000004
35#define GPMC_CONFIG_WP 0x00000005
36
37#define GPMC_ENABLE_IRQ 0x0000000d
38
39/* ECC commands */
40#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
41#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
42#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
43
44#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
45#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
46#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
47#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
48#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
49#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
50#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
51#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
52#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
53#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
54#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
55#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
56#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
57#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
58#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
59#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
60#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
61#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
62#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
63#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
64#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
65#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
66#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
67#define GPMC_CONFIG7_CSVALID (1 << 6)
68
69#define GPMC_DEVICETYPE_NOR 0
70#define GPMC_DEVICETYPE_NAND 2
71#define GPMC_CONFIG_WRITEPROTECT 0x00000010
72#define WR_RD_PIN_MONITORING 0x00600000
73#define GPMC_IRQ_FIFOEVENTENABLE 0x01
74#define GPMC_IRQ_COUNT_EVENT 0x02
75
76#define GPMC_BURST_4 4 /* 4 word burst */
77#define GPMC_BURST_8 8 /* 8 word burst */
78#define GPMC_BURST_16 16 /* 16 word burst */
79#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
80#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
81#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
82#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
83
84/* bool type time settings */
85struct gpmc_bool_timings {
86 bool cycle2cyclediffcsen;
87 bool cycle2cyclesamecsen;
88 bool we_extra_delay;
89 bool oe_extra_delay;
90 bool adv_extra_delay;
91 bool cs_extra_delay;
92 bool time_para_granularity;
93};
94
95/*
96 * Note that all values in this struct are in nanoseconds except sync_clk
97 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
98 */
99struct gpmc_timings {
100 /* Minimum clock period for synchronous mode (in picoseconds) */
101 u32 sync_clk;
102
103 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
104 u32 cs_on; /* Assertion time */
105 u32 cs_rd_off; /* Read deassertion time */
106 u32 cs_wr_off; /* Write deassertion time */
107
108 /* ADV signal timings corresponding to GPMC_CONFIG3 */
109 u32 adv_on; /* Assertion time */
110 u32 adv_rd_off; /* Read deassertion time */
111 u32 adv_wr_off; /* Write deassertion time */
112
113 /* WE signals timings corresponding to GPMC_CONFIG4 */
114 u32 we_on; /* WE assertion time */
115 u32 we_off; /* WE deassertion time */
116
117 /* OE signals timings corresponding to GPMC_CONFIG4 */
118 u32 oe_on; /* OE assertion time */
119 u32 oe_off; /* OE deassertion time */
120
121 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
122 u32 page_burst_access; /* Multiple access word delay */
123 u32 access; /* Start-cycle to first data valid delay */
124 u32 rd_cycle; /* Total read cycle time */
125 u32 wr_cycle; /* Total write cycle time */
126
127 u32 bus_turnaround;
128 u32 cycle2cycle_delay;
129
130 u32 wait_monitoring;
131 u32 clk_activation;
132
133 /* The following are only on OMAP3430 */
134 u32 wr_access; /* WRACCESSTIME */
135 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
136
137 struct gpmc_bool_timings bool_timings;
138};
139
140/* Device timings in picoseconds */
141struct gpmc_device_timings {
142 u32 t_ceasu; /* address setup to CS valid */
143 u32 t_avdasu; /* address setup to ADV valid */
144 /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
145 * of tusb using these timings even for sync whilst
146 * ideally for adv_rd/(wr)_off it should have considered
147 * t_avdh instead. This indirectly necessitates r/w
148 * variations of t_avdp as it is possible to have one
149 * sync & other async
150 */
151 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
152 u32 t_avdp_w;
153 u32 t_aavdh; /* address hold time */
154 u32 t_oeasu; /* address setup to OE valid */
155 u32 t_aa; /* access time from ADV assertion */
156 u32 t_iaa; /* initial access time */
157 u32 t_oe; /* access time from OE assertion */
158 u32 t_ce; /* access time from CS asertion */
159 u32 t_rd_cycle; /* read cycle time */
160 u32 t_cez_r; /* read CS deassertion to high Z */
161 u32 t_cez_w; /* write CS deassertion to high Z */
162 u32 t_oez; /* OE deassertion to high Z */
163 u32 t_weasu; /* address setup to WE valid */
164 u32 t_wpl; /* write assertion time */
165 u32 t_wph; /* write deassertion time */
166 u32 t_wr_cycle; /* write cycle time */
167
168 u32 clk;
169 u32 t_bacc; /* burst access valid clock to output delay */
170 u32 t_ces; /* CS setup time to clk */
171 u32 t_avds; /* ADV setup time to clk */
172 u32 t_avdh; /* ADV hold time from clk */
173 u32 t_ach; /* address hold time from clk */
174 u32 t_rdyo; /* clk to ready valid */
175
176 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
177 u32 t_ce_avd; /* CS on to ADV on delay */
178
179 /* XXX: check the possibility of combining
180 * cyc_aavhd_oe & cyc_aavdh_we
181 */
182 u8 cyc_aavdh_oe;/* read address hold time in cycles */
183 u8 cyc_aavdh_we;/* write address hold time in cycles */
184 u8 cyc_oe; /* access time from OE assertion in cycles */
185 u8 cyc_wpl; /* write deassertion time in cycles */
186 u32 cyc_iaa; /* initial access time in cycles */
187
188 /* extra delays */
189 bool ce_xdelay;
190 bool avd_xdelay;
191 bool oe_xdelay;
192 bool we_xdelay;
193};
194
195struct gpmc_settings {
196 bool burst_wrap; /* enables wrap bursting */
197 bool burst_read; /* enables read page/burst mode */
198 bool burst_write; /* enables write page/burst mode */
199 bool device_nand; /* device is NAND */
200 bool sync_read; /* enables synchronous reads */
201 bool sync_write; /* enables synchronous writes */
202 bool wait_on_read; /* monitor wait on reads */
203 bool wait_on_write; /* monitor wait on writes */
204 u32 burst_len; /* page/burst length */
205 u32 device_width; /* device bus width (8 or 16 bit) */
206 u32 mux_add_data; /* multiplex address & data */
207 u32 wait_pin; /* wait-pin to be used */
208};
209
210extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
211 struct gpmc_settings *gpmc_s,
212 struct gpmc_device_timings *dev_t);
213
214extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
215extern int gpmc_get_client_irq(unsigned irq_config);
216
217extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
218
219extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
220extern int gpmc_calc_divider(unsigned int sync_clk);
221extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
222extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
223extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
224extern void gpmc_cs_free(int cs);
225extern void omap3_gpmc_save_context(void);
226extern void omap3_gpmc_restore_context(void);
227extern int gpmc_configure(int cmd, int wval);
228extern void gpmc_read_settings_dt(struct device_node *np,
229 struct gpmc_settings *p);
230
231#endif
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 175564c88a30..88721df6001d 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -29,6 +29,7 @@
29#include <linux/delay.h> 29#include <linux/delay.h>
30#include <linux/slab.h> 30#include <linux/slab.h>
31#include <linux/omap-dma.h> 31#include <linux/omap-dma.h>
32#include <linux/omap-gpmc.h>
32#include <linux/platform_data/gpio-omap.h> 33#include <linux/platform_data/gpio-omap.h>
33 34
34#include <trace/events/power.h> 35#include <trace/events/power.h>
@@ -43,7 +44,6 @@
43#include "common.h" 44#include "common.h"
44#include "cm3xxx.h" 45#include "cm3xxx.h"
45#include "cm-regbits-34xx.h" 46#include "cm-regbits-34xx.h"
46#include "gpmc.h"
47#include "prm-regbits-34xx.h" 47#include "prm-regbits-34xx.h"
48#include "prm3xxx.h" 48#include "prm3xxx.h"
49#include "pm.h" 49#include "pm.h"
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index 08bd4cfca2a4..191383d8c94d 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -41,6 +41,14 @@ config TI_EMIF
41 parameters and other settings during frequency, voltage and 41 parameters and other settings during frequency, voltage and
42 temperature changes 42 temperature changes
43 43
44config OMAP_GPMC
45 bool
46 help
47 This driver is for the General Purpose Memory Controller (GPMC)
48 present on Texas Instruments SoCs (e.g. OMAP2+). GPMC allows
49 interfacing to a variety of asynchronous as well as synchronous
50 memory drives like NOR, NAND, OneNAND, SRAM.
51
44config MVEBU_DEVBUS 52config MVEBU_DEVBUS
45 bool "Marvell EBU Device Bus Controller" 53 bool "Marvell EBU Device Bus Controller"
46 default y 54 default y
diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile
index ad98bb232623..6b6548124473 100644
--- a/drivers/memory/Makefile
+++ b/drivers/memory/Makefile
@@ -8,6 +8,7 @@ endif
8obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o 8obj-$(CONFIG_ATMEL_SDRAMC) += atmel-sdramc.o
9obj-$(CONFIG_TI_AEMIF) += ti-aemif.o 9obj-$(CONFIG_TI_AEMIF) += ti-aemif.o
10obj-$(CONFIG_TI_EMIF) += emif.o 10obj-$(CONFIG_TI_EMIF) += emif.o
11obj-$(CONFIG_OMAP_GPMC) += omap-gpmc.o
11obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o 12obj-$(CONFIG_FSL_CORENET_CF) += fsl-corenet-cf.o
12obj-$(CONFIG_FSL_IFC) += fsl_ifc.o 13obj-$(CONFIG_FSL_IFC) += fsl_ifc.o
13obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o 14obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o
diff --git a/arch/arm/mach-omap2/gpmc.c b/drivers/memory/omap-gpmc.c
index 8fb5bbce102f..ffc5e60c0664 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/drivers/memory/omap-gpmc.c
@@ -29,20 +29,15 @@
29#include <linux/of_address.h> 29#include <linux/of_address.h>
30#include <linux/of_mtd.h> 30#include <linux/of_mtd.h>
31#include <linux/of_device.h> 31#include <linux/of_device.h>
32#include <linux/omap-gpmc.h>
32#include <linux/mtd/nand.h> 33#include <linux/mtd/nand.h>
33#include <linux/pm_runtime.h> 34#include <linux/pm_runtime.h>
34 35
35#include <linux/platform_data/mtd-nand-omap2.h> 36#include <linux/platform_data/mtd-nand-omap2.h>
37#include <linux/platform_data/mtd-onenand-omap2.h>
36 38
37#include <asm/mach-types.h> 39#include <asm/mach-types.h>
38 40
39#include "soc.h"
40#include "common.h"
41#include "omap_device.h"
42#include "gpmc.h"
43#include "gpmc-nand.h"
44#include "gpmc-onenand.h"
45
46#define DEVICE_NAME "omap-gpmc" 41#define DEVICE_NAME "omap-gpmc"
47 42
48/* GPMC register offsets */ 43/* GPMC register offsets */
@@ -85,6 +80,8 @@
85#define GPMC_ECC_CTRL_ECCREG8 0x008 80#define GPMC_ECC_CTRL_ECCREG8 0x008
86#define GPMC_ECC_CTRL_ECCREG9 0x009 81#define GPMC_ECC_CTRL_ECCREG9 0x009
87 82
83#define GPMC_CONFIG_LIMITEDADDRESS BIT(1)
84
88#define GPMC_CONFIG2_CSEXTRADELAY BIT(7) 85#define GPMC_CONFIG2_CSEXTRADELAY BIT(7)
89#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7) 86#define GPMC_CONFIG3_ADVEXTRADELAY BIT(7)
90#define GPMC_CONFIG4_OEEXTRADELAY BIT(7) 87#define GPMC_CONFIG4_OEEXTRADELAY BIT(7)
@@ -114,10 +111,73 @@
114 111
115#define GPMC_NR_WAITPINS 4 112#define GPMC_NR_WAITPINS 4
116 113
114#define GPMC_CS_CONFIG1 0x00
115#define GPMC_CS_CONFIG2 0x04
116#define GPMC_CS_CONFIG3 0x08
117#define GPMC_CS_CONFIG4 0x0c
118#define GPMC_CS_CONFIG5 0x10
119#define GPMC_CS_CONFIG6 0x14
120#define GPMC_CS_CONFIG7 0x18
121#define GPMC_CS_NAND_COMMAND 0x1c
122#define GPMC_CS_NAND_ADDRESS 0x20
123#define GPMC_CS_NAND_DATA 0x24
124
125/* Control Commands */
126#define GPMC_CONFIG_RDY_BSY 0x00000001
127#define GPMC_CONFIG_DEV_SIZE 0x00000002
128#define GPMC_CONFIG_DEV_TYPE 0x00000003
129#define GPMC_SET_IRQ_STATUS 0x00000004
130
131#define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31)
132#define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30)
133#define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29)
134#define GPMC_CONFIG1_READTYPE_SYNC (1 << 29)
135#define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
136#define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27)
137#define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27)
138#define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25)
139#define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23)
140#define GPMC_CONFIG1_WAIT_READ_MON (1 << 22)
141#define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21)
142#define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18)
143#define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16)
144#define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12)
145#define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1)
146#define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10)
147#define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0)
148#define GPMC_CONFIG1_MUXTYPE(val) ((val & 3) << 8)
149#define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4)
150#define GPMC_CONFIG1_FCLK_DIV(val) (val & 3)
151#define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1))
152#define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2))
153#define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3))
154#define GPMC_CONFIG7_CSVALID (1 << 6)
155
156#define GPMC_DEVICETYPE_NOR 0
157#define GPMC_DEVICETYPE_NAND 2
158#define GPMC_CONFIG_WRITEPROTECT 0x00000010
159#define WR_RD_PIN_MONITORING 0x00600000
160
161#define GPMC_ENABLE_IRQ 0x0000000d
162
163/* ECC commands */
164#define GPMC_ECC_READ 0 /* Reset Hardware ECC for read */
165#define GPMC_ECC_WRITE 1 /* Reset Hardware ECC for write */
166#define GPMC_ECC_READSYN 2 /* Reset before syndrom is read back */
167
117/* XXX: Only NAND irq has been considered,currently these are the only ones used 168/* XXX: Only NAND irq has been considered,currently these are the only ones used
118 */ 169 */
119#define GPMC_NR_IRQ 2 170#define GPMC_NR_IRQ 2
120 171
172struct gpmc_cs_data {
173 const char *name;
174
175#define GPMC_CS_RESERVED (1 << 0)
176 u32 flags;
177
178 struct resource mem;
179};
180
121struct gpmc_client_irq { 181struct gpmc_client_irq {
122 unsigned irq; 182 unsigned irq;
123 u32 bitmask; 183 u32 bitmask;
@@ -155,10 +215,9 @@ static struct irq_chip gpmc_irq_chip;
155static int gpmc_irq_start; 215static int gpmc_irq_start;
156 216
157static struct resource gpmc_mem_root; 217static struct resource gpmc_mem_root;
158static struct resource gpmc_cs_mem[GPMC_CS_NUM]; 218static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
159static DEFINE_SPINLOCK(gpmc_mem_lock); 219static DEFINE_SPINLOCK(gpmc_mem_lock);
160/* Define chip-selects as reserved by default until probe completes */ 220/* Define chip-selects as reserved by default until probe completes */
161static unsigned int gpmc_cs_map = ((1 << GPMC_CS_NUM) - 1);
162static unsigned int gpmc_cs_num = GPMC_CS_NUM; 221static unsigned int gpmc_cs_num = GPMC_CS_NUM;
163static unsigned int gpmc_nr_waitpins; 222static unsigned int gpmc_nr_waitpins;
164static struct device *gpmc_dev; 223static struct device *gpmc_dev;
@@ -202,11 +261,6 @@ static unsigned long gpmc_get_fclk_period(void)
202{ 261{
203 unsigned long rate = clk_get_rate(gpmc_l3_clk); 262 unsigned long rate = clk_get_rate(gpmc_l3_clk);
204 263
205 if (rate == 0) {
206 printk(KERN_WARNING "gpmc_l3_clk not enabled\n");
207 return 0;
208 }
209
210 rate /= 1000; 264 rate /= 1000;
211 rate = 1000000000 / rate; /* In picoseconds */ 265 rate = 1000000000 / rate; /* In picoseconds */
212 266
@@ -284,12 +338,130 @@ static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
284} 338}
285 339
286#ifdef DEBUG 340#ifdef DEBUG
287static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, 341static int get_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
288 int time, const char *name) 342 bool raw, bool noval, int shift,
343 const char *name)
344{
345 u32 l;
346 int nr_bits, max_value, mask;
347
348 l = gpmc_cs_read_reg(cs, reg);
349 nr_bits = end_bit - st_bit + 1;
350 max_value = (1 << nr_bits) - 1;
351 mask = max_value << st_bit;
352 l = (l & mask) >> st_bit;
353 if (shift)
354 l = (shift << l);
355 if (noval && (l == 0))
356 return 0;
357 if (!raw) {
358 unsigned int time_ns_min, time_ns, time_ns_max;
359
360 time_ns_min = gpmc_ticks_to_ns(l ? l - 1 : 0);
361 time_ns = gpmc_ticks_to_ns(l);
362 time_ns_max = gpmc_ticks_to_ns(l + 1 > max_value ?
363 max_value : l + 1);
364 pr_info("gpmc,%s = <%u> (%u - %u ns, %i ticks)\n",
365 name, time_ns, time_ns_min, time_ns_max, l);
366 } else {
367 pr_info("gpmc,%s = <%u>\n", name, l);
368 }
369
370 return l;
371}
372
373#define GPMC_PRINT_CONFIG(cs, config) \
374 pr_info("cs%i %s: 0x%08x\n", cs, #config, \
375 gpmc_cs_read_reg(cs, config))
376#define GPMC_GET_RAW(reg, st, end, field) \
377 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 0, 0, field)
378#define GPMC_GET_RAW_BOOL(reg, st, end, field) \
379 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, 0, field)
380#define GPMC_GET_RAW_SHIFT(reg, st, end, shift, field) \
381 get_gpmc_timing_reg(cs, (reg), (st), (end), 1, 1, (shift), field)
382#define GPMC_GET_TICKS(reg, st, end, field) \
383 get_gpmc_timing_reg(cs, (reg), (st), (end), 0, 0, 0, field)
384
385static void gpmc_show_regs(int cs, const char *desc)
386{
387 pr_info("gpmc cs%i %s:\n", cs, desc);
388 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
389 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
390 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
391 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
392 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
393 GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
394}
395
396/*
397 * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
398 * see commit c9fb809.
399 */
400static void gpmc_cs_show_timings(int cs, const char *desc)
401{
402 gpmc_show_regs(cs, desc);
403
404 pr_info("gpmc cs%i access configuration:\n", cs);
405 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 4, 4, "time-para-granularity");
406 GPMC_GET_RAW(GPMC_CS_CONFIG1, 8, 9, "mux-add-data");
407 GPMC_GET_RAW(GPMC_CS_CONFIG1, 12, 13, "device-width");
408 GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
409 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
410 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
411 GPMC_GET_RAW_SHIFT(GPMC_CS_CONFIG1, 23, 24, 4, "burst-length");
412 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
413 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
414 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
415 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
416 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
417
418 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2, 7, 7, "cs-extra-delay");
419
420 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3, 7, 7, "adv-extra-delay");
421
422 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
423 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 7, 7, "oe-extra-delay");
424
425 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 7, 7, "cycle2cycle-samecsen");
426 GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6, 6, 6, "cycle2cycle-diffcsen");
427
428 pr_info("gpmc cs%i timings configuration:\n", cs);
429 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 0, 3, "cs-on-ns");
430 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 8, 12, "cs-rd-off-ns");
431 GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
432
433 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 0, 3, "adv-on-ns");
434 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 8, 12, "adv-rd-off-ns");
435 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
436
437 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 0, 3, "oe-on-ns");
438 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 8, 12, "oe-off-ns");
439 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
440 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
441
442 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 0, 4, "rd-cycle-ns");
443 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 8, 12, "wr-cycle-ns");
444 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
445
446 GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
447
448 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
449 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
450
451 GPMC_GET_TICKS(GPMC_CS_CONFIG1, 18, 19, "wait-monitoring-ns");
452 GPMC_GET_TICKS(GPMC_CS_CONFIG1, 25, 26, "clk-activation-ns");
453
454 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
455 GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
456}
289#else 457#else
290static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, 458static inline void gpmc_cs_show_timings(int cs, const char *desc)
291 int time) 459{
460}
292#endif 461#endif
462
463static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
464 int time, const char *name)
293{ 465{
294 u32 l; 466 u32 l;
295 int ticks, mask, nr_bits; 467 int ticks, mask, nr_bits;
@@ -299,15 +471,15 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
299 else 471 else
300 ticks = gpmc_ns_to_ticks(time); 472 ticks = gpmc_ns_to_ticks(time);
301 nr_bits = end_bit - st_bit + 1; 473 nr_bits = end_bit - st_bit + 1;
302 if (ticks >= 1 << nr_bits) { 474 mask = (1 << nr_bits) - 1;
303#ifdef DEBUG 475
304 printk(KERN_INFO "GPMC CS%d: %-10s* %3d ns, %3d ticks >= %d\n", 476 if (ticks > mask) {
305 cs, name, time, ticks, 1 << nr_bits); 477 pr_err("%s: GPMC error! CS%d: %s: %d ns, %d ticks > %d\n",
306#endif 478 __func__, cs, name, time, ticks, mask);
479
307 return -1; 480 return -1;
308 } 481 }
309 482
310 mask = (1 << nr_bits) - 1;
311 l = gpmc_cs_read_reg(cs, reg); 483 l = gpmc_cs_read_reg(cs, reg);
312#ifdef DEBUG 484#ifdef DEBUG
313 printk(KERN_INFO 485 printk(KERN_INFO
@@ -322,16 +494,10 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
322 return 0; 494 return 0;
323} 495}
324 496
325#ifdef DEBUG
326#define GPMC_SET_ONE(reg, st, end, field) \ 497#define GPMC_SET_ONE(reg, st, end, field) \
327 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \ 498 if (set_gpmc_timing_reg(cs, (reg), (st), (end), \
328 t->field, #field) < 0) \ 499 t->field, #field) < 0) \
329 return -1 500 return -1
330#else
331#define GPMC_SET_ONE(reg, st, end, field) \
332 if (set_gpmc_timing_reg(cs, (reg), (st), (end), t->field) < 0) \
333 return -1
334#endif
335 501
336int gpmc_calc_divider(unsigned int sync_clk) 502int gpmc_calc_divider(unsigned int sync_clk)
337{ 503{
@@ -353,6 +519,7 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
353 int div; 519 int div;
354 u32 l; 520 u32 l;
355 521
522 gpmc_cs_show_timings(cs, "before gpmc_cs_set_timings");
356 div = gpmc_calc_divider(t->sync_clk); 523 div = gpmc_calc_divider(t->sync_clk);
357 if (div < 0) 524 if (div < 0)
358 return div; 525 return div;
@@ -402,11 +569,12 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
402 } 569 }
403 570
404 gpmc_cs_bool_timings(cs, &t->bool_timings); 571 gpmc_cs_bool_timings(cs, &t->bool_timings);
572 gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
405 573
406 return 0; 574 return 0;
407} 575}
408 576
409static int gpmc_cs_enable_mem(int cs, u32 base, u32 size) 577static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
410{ 578{
411 u32 l; 579 u32 l;
412 u32 mask; 580 u32 mask;
@@ -430,6 +598,15 @@ static int gpmc_cs_enable_mem(int cs, u32 base, u32 size)
430 return 0; 598 return 0;
431} 599}
432 600
601static void gpmc_cs_enable_mem(int cs)
602{
603 u32 l;
604
605 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
606 l |= GPMC_CONFIG7_CSVALID;
607 gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
608}
609
433static void gpmc_cs_disable_mem(int cs) 610static void gpmc_cs_disable_mem(int cs)
434{ 611{
435 u32 l; 612 u32 l;
@@ -460,13 +637,30 @@ static int gpmc_cs_mem_enabled(int cs)
460 637
461static void gpmc_cs_set_reserved(int cs, int reserved) 638static void gpmc_cs_set_reserved(int cs, int reserved)
462{ 639{
463 gpmc_cs_map &= ~(1 << cs); 640 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
464 gpmc_cs_map |= (reserved ? 1 : 0) << cs; 641
642 gpmc->flags |= GPMC_CS_RESERVED;
465} 643}
466 644
467static bool gpmc_cs_reserved(int cs) 645static bool gpmc_cs_reserved(int cs)
468{ 646{
469 return gpmc_cs_map & (1 << cs); 647 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
648
649 return gpmc->flags & GPMC_CS_RESERVED;
650}
651
652static void gpmc_cs_set_name(int cs, const char *name)
653{
654 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
655
656 gpmc->name = name;
657}
658
659const char *gpmc_cs_get_name(int cs)
660{
661 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
662
663 return gpmc->name;
470} 664}
471 665
472static unsigned long gpmc_mem_align(unsigned long size) 666static unsigned long gpmc_mem_align(unsigned long size)
@@ -485,7 +679,8 @@ static unsigned long gpmc_mem_align(unsigned long size)
485 679
486static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size) 680static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
487{ 681{
488 struct resource *res = &gpmc_cs_mem[cs]; 682 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
683 struct resource *res = &gpmc->mem;
489 int r; 684 int r;
490 685
491 size = gpmc_mem_align(size); 686 size = gpmc_mem_align(size);
@@ -500,7 +695,8 @@ static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
500 695
501static int gpmc_cs_delete_mem(int cs) 696static int gpmc_cs_delete_mem(int cs)
502{ 697{
503 struct resource *res = &gpmc_cs_mem[cs]; 698 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
699 struct resource *res = &gpmc->mem;
504 int r; 700 int r;
505 701
506 spin_lock(&gpmc_mem_lock); 702 spin_lock(&gpmc_mem_lock);
@@ -541,23 +737,24 @@ static int gpmc_cs_remap(int cs, u32 base)
541 gpmc_cs_get_memconf(cs, &old_base, &size); 737 gpmc_cs_get_memconf(cs, &old_base, &size);
542 if (base == old_base) 738 if (base == old_base)
543 return 0; 739 return 0;
544 gpmc_cs_disable_mem(cs); 740
545 ret = gpmc_cs_delete_mem(cs); 741 ret = gpmc_cs_delete_mem(cs);
546 if (ret < 0) 742 if (ret < 0)
547 return ret; 743 return ret;
744
548 ret = gpmc_cs_insert_mem(cs, base, size); 745 ret = gpmc_cs_insert_mem(cs, base, size);
549 if (ret < 0) 746 if (ret < 0)
550 return ret; 747 return ret;
551 ret = gpmc_cs_enable_mem(cs, base, size);
552 if (ret < 0)
553 return ret;
554 748
555 return 0; 749 ret = gpmc_cs_set_memconf(cs, base, size);
750
751 return ret;
556} 752}
557 753
558int gpmc_cs_request(int cs, unsigned long size, unsigned long *base) 754int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
559{ 755{
560 struct resource *res = &gpmc_cs_mem[cs]; 756 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
757 struct resource *res = &gpmc->mem;
561 int r = -1; 758 int r = -1;
562 759
563 if (cs > gpmc_cs_num) { 760 if (cs > gpmc_cs_num) {
@@ -581,12 +778,17 @@ int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
581 if (r < 0) 778 if (r < 0)
582 goto out; 779 goto out;
583 780
584 r = gpmc_cs_enable_mem(cs, res->start, resource_size(res)); 781 /* Disable CS while changing base address and size mask */
782 gpmc_cs_disable_mem(cs);
783
784 r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
585 if (r < 0) { 785 if (r < 0) {
586 release_resource(res); 786 release_resource(res);
587 goto out; 787 goto out;
588 } 788 }
589 789
790 /* Enable CS */
791 gpmc_cs_enable_mem(cs);
590 *base = res->start; 792 *base = res->start;
591 gpmc_cs_set_reserved(cs, 1); 793 gpmc_cs_set_reserved(cs, 1);
592out: 794out:
@@ -597,7 +799,8 @@ EXPORT_SYMBOL(gpmc_cs_request);
597 799
598void gpmc_cs_free(int cs) 800void gpmc_cs_free(int cs)
599{ 801{
600 struct resource *res = &gpmc_cs_mem[cs]; 802 struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
803 struct resource *res = &gpmc->mem;
601 804
602 spin_lock(&gpmc_mem_lock); 805 spin_lock(&gpmc_mem_lock);
603 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) { 806 if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
@@ -1509,7 +1712,9 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
1509 struct gpmc_timings gpmc_t; 1712 struct gpmc_timings gpmc_t;
1510 struct resource res; 1713 struct resource res;
1511 unsigned long base; 1714 unsigned long base;
1715 const char *name;
1512 int ret, cs; 1716 int ret, cs;
1717 u32 val;
1513 1718
1514 if (of_property_read_u32(child, "reg", &cs) < 0) { 1719 if (of_property_read_u32(child, "reg", &cs) < 0) {
1515 dev_err(&pdev->dev, "%s has no 'reg' property\n", 1720 dev_err(&pdev->dev, "%s has no 'reg' property\n",
@@ -1523,28 +1728,41 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
1523 return -ENODEV; 1728 return -ENODEV;
1524 } 1729 }
1525 1730
1731 /*
1732 * Check if we have multiple instances of the same device
1733 * on a single chip select. If so, use the already initialized
1734 * timings.
1735 */
1736 name = gpmc_cs_get_name(cs);
1737 if (name && child->name && of_node_cmp(child->name, name) == 0)
1738 goto no_timings;
1739
1526 ret = gpmc_cs_request(cs, resource_size(&res), &base); 1740 ret = gpmc_cs_request(cs, resource_size(&res), &base);
1527 if (ret < 0) { 1741 if (ret < 0) {
1528 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); 1742 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
1529 return ret; 1743 return ret;
1530 } 1744 }
1745 gpmc_cs_set_name(cs, child->name);
1746
1747 gpmc_read_settings_dt(child, &gpmc_s);
1748 gpmc_read_timings_dt(child, &gpmc_t);
1531 1749
1532 /* 1750 /*
1533 * For some GPMC devices we still need to rely on the bootloader 1751 * For some GPMC devices we still need to rely on the bootloader
1534 * timings because the devices can be connected via FPGA. So far 1752 * timings because the devices can be connected via FPGA.
1535 * the list is smc91x on the omap2 SDP boards, and 8250 on zooms. 1753 * REVISIT: Add timing support from slls644g.pdf.
1536 * REVISIT: Add timing support from slls644g.pdf and from the
1537 * lan91c96 manual.
1538 */ 1754 */
1539 if (of_device_is_compatible(child, "ns16550a") || 1755 if (!gpmc_t.cs_rd_off) {
1540 of_device_is_compatible(child, "smsc,lan91c94") || 1756 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
1541 of_device_is_compatible(child, "smsc,lan91c111")) { 1757 cs);
1542 dev_warn(&pdev->dev, 1758 gpmc_cs_show_timings(cs,
1543 "%s using bootloader timings on CS%d\n", 1759 "please add GPMC bootloader timings to .dts");
1544 child->name, cs);
1545 goto no_timings; 1760 goto no_timings;
1546 } 1761 }
1547 1762
1763 /* CS must be disabled while making changes to gpmc configuration */
1764 gpmc_cs_disable_mem(cs);
1765
1548 /* 1766 /*
1549 * FIXME: gpmc_cs_request() will map the CS to an arbitary 1767 * FIXME: gpmc_cs_request() will map the CS to an arbitary
1550 * location in the gpmc address space. When booting with 1768 * location in the gpmc address space. When booting with
@@ -1560,8 +1778,6 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
1560 goto err; 1778 goto err;
1561 } 1779 }
1562 1780
1563 gpmc_read_settings_dt(child, &gpmc_s);
1564
1565 ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width); 1781 ret = of_property_read_u32(child, "bank-width", &gpmc_s.device_width);
1566 if (ret < 0) 1782 if (ret < 0)
1567 goto err; 1783 goto err;
@@ -1570,8 +1786,20 @@ static int gpmc_probe_generic_child(struct platform_device *pdev,
1570 if (ret < 0) 1786 if (ret < 0)
1571 goto err; 1787 goto err;
1572 1788
1573 gpmc_read_timings_dt(child, &gpmc_t); 1789 ret = gpmc_cs_set_timings(cs, &gpmc_t);
1574 gpmc_cs_set_timings(cs, &gpmc_t); 1790 if (ret) {
1791 dev_err(&pdev->dev, "failed to set gpmc timings for: %s\n",
1792 child->name);
1793 goto err;
1794 }
1795
1796 /* Clear limited address i.e. enable A26-A11 */
1797 val = gpmc_read_reg(GPMC_CONFIG);
1798 val &= ~GPMC_CONFIG_LIMITEDADDRESS;
1799 gpmc_write_reg(GPMC_CONFIG, val);
1800
1801 /* Enable CS region */
1802 gpmc_cs_enable_mem(cs);
1575 1803
1576no_timings: 1804no_timings:
1577 if (of_platform_device_create(child, NULL, &pdev->dev)) 1805 if (of_platform_device_create(child, NULL, &pdev->dev))
@@ -1668,13 +1896,18 @@ static int gpmc_probe(struct platform_device *pdev)
1668 else 1896 else
1669 gpmc_irq = res->start; 1897 gpmc_irq = res->start;
1670 1898
1671 gpmc_l3_clk = clk_get(&pdev->dev, "fck"); 1899 gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
1672 if (IS_ERR(gpmc_l3_clk)) { 1900 if (IS_ERR(gpmc_l3_clk)) {
1673 dev_err(&pdev->dev, "error: clk_get\n"); 1901 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
1674 gpmc_irq = 0; 1902 gpmc_irq = 0;
1675 return PTR_ERR(gpmc_l3_clk); 1903 return PTR_ERR(gpmc_l3_clk);
1676 } 1904 }
1677 1905
1906 if (!clk_get_rate(gpmc_l3_clk)) {
1907 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
1908 return -EINVAL;
1909 }
1910
1678 pm_runtime_enable(&pdev->dev); 1911 pm_runtime_enable(&pdev->dev);
1679 pm_runtime_get_sync(&pdev->dev); 1912 pm_runtime_get_sync(&pdev->dev);
1680 1913
@@ -1706,9 +1939,6 @@ static int gpmc_probe(struct platform_device *pdev)
1706 if (gpmc_setup_irq() < 0) 1939 if (gpmc_setup_irq() < 0)
1707 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n"); 1940 dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
1708 1941
1709 /* Now the GPMC is initialised, unreserve the chip-selects */
1710 gpmc_cs_map = 0;
1711
1712 if (!pdev->dev.of_node) { 1942 if (!pdev->dev.of_node) {
1713 gpmc_cs_num = GPMC_CS_NUM; 1943 gpmc_cs_num = GPMC_CS_NUM;
1714 gpmc_nr_waitpins = GPMC_NR_WAITPINS; 1944 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
@@ -1717,7 +1947,6 @@ static int gpmc_probe(struct platform_device *pdev)
1717 rc = gpmc_probe_dt(pdev); 1947 rc = gpmc_probe_dt(pdev);
1718 if (rc < 0) { 1948 if (rc < 0) {
1719 pm_runtime_put_sync(&pdev->dev); 1949 pm_runtime_put_sync(&pdev->dev);
1720 clk_put(gpmc_l3_clk);
1721 dev_err(gpmc_dev, "failed to probe DT parameters\n"); 1950 dev_err(gpmc_dev, "failed to probe DT parameters\n");
1722 return rc; 1951 return rc;
1723 } 1952 }
@@ -1775,35 +2004,9 @@ static __exit void gpmc_exit(void)
1775 2004
1776} 2005}
1777 2006
1778omap_postcore_initcall(gpmc_init); 2007postcore_initcall(gpmc_init);
1779module_exit(gpmc_exit); 2008module_exit(gpmc_exit);
1780 2009
1781static int __init omap_gpmc_init(void)
1782{
1783 struct omap_hwmod *oh;
1784 struct platform_device *pdev;
1785 char *oh_name = "gpmc";
1786
1787 /*
1788 * if the board boots up with a populated DT, do not
1789 * manually add the device from this initcall
1790 */
1791 if (of_have_populated_dt())
1792 return -ENODEV;
1793
1794 oh = omap_hwmod_lookup(oh_name);
1795 if (!oh) {
1796 pr_err("Could not look up %s\n", oh_name);
1797 return -ENODEV;
1798 }
1799
1800 pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0);
1801 WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
1802
1803 return PTR_RET(pdev);
1804}
1805omap_postcore_initcall(omap_gpmc_init);
1806
1807static irqreturn_t gpmc_handle_irq(int irq, void *dev) 2010static irqreturn_t gpmc_handle_irq(int irq, void *dev)
1808{ 2011{
1809 int i; 2012 int i;
diff --git a/include/linux/omap-gpmc.h b/include/linux/omap-gpmc.h
new file mode 100644
index 000000000000..c2080eebbb47
--- /dev/null
+++ b/include/linux/omap-gpmc.h
@@ -0,0 +1,199 @@
1/*
2 * OMAP GPMC (General Purpose Memory Controller) defines
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms of the GNU General Public License as published by the
6 * Free Software Foundation; either version 2 of the License, or (at your
7 * option) any later version.
8 */
9
10/* Maximum Number of Chip Selects */
11#define GPMC_CS_NUM 8
12
13#define GPMC_CONFIG_WP 0x00000005
14
15#define GPMC_IRQ_FIFOEVENTENABLE 0x01
16#define GPMC_IRQ_COUNT_EVENT 0x02
17
18#define GPMC_BURST_4 4 /* 4 word burst */
19#define GPMC_BURST_8 8 /* 8 word burst */
20#define GPMC_BURST_16 16 /* 16 word burst */
21#define GPMC_DEVWIDTH_8BIT 1 /* 8-bit device width */
22#define GPMC_DEVWIDTH_16BIT 2 /* 16-bit device width */
23#define GPMC_MUX_AAD 1 /* Addr-Addr-Data multiplex */
24#define GPMC_MUX_AD 2 /* Addr-Data multiplex */
25
26/* bool type time settings */
27struct gpmc_bool_timings {
28 bool cycle2cyclediffcsen;
29 bool cycle2cyclesamecsen;
30 bool we_extra_delay;
31 bool oe_extra_delay;
32 bool adv_extra_delay;
33 bool cs_extra_delay;
34 bool time_para_granularity;
35};
36
37/*
38 * Note that all values in this struct are in nanoseconds except sync_clk
39 * (which is in picoseconds), while the register values are in gpmc_fck cycles.
40 */
41struct gpmc_timings {
42 /* Minimum clock period for synchronous mode (in picoseconds) */
43 u32 sync_clk;
44
45 /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
46 u32 cs_on; /* Assertion time */
47 u32 cs_rd_off; /* Read deassertion time */
48 u32 cs_wr_off; /* Write deassertion time */
49
50 /* ADV signal timings corresponding to GPMC_CONFIG3 */
51 u32 adv_on; /* Assertion time */
52 u32 adv_rd_off; /* Read deassertion time */
53 u32 adv_wr_off; /* Write deassertion time */
54
55 /* WE signals timings corresponding to GPMC_CONFIG4 */
56 u32 we_on; /* WE assertion time */
57 u32 we_off; /* WE deassertion time */
58
59 /* OE signals timings corresponding to GPMC_CONFIG4 */
60 u32 oe_on; /* OE assertion time */
61 u32 oe_off; /* OE deassertion time */
62
63 /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
64 u32 page_burst_access; /* Multiple access word delay */
65 u32 access; /* Start-cycle to first data valid delay */
66 u32 rd_cycle; /* Total read cycle time */
67 u32 wr_cycle; /* Total write cycle time */
68
69 u32 bus_turnaround;
70 u32 cycle2cycle_delay;
71
72 u32 wait_monitoring;
73 u32 clk_activation;
74
75 /* The following are only on OMAP3430 */
76 u32 wr_access; /* WRACCESSTIME */
77 u32 wr_data_mux_bus; /* WRDATAONADMUXBUS */
78
79 struct gpmc_bool_timings bool_timings;
80};
81
82/* Device timings in picoseconds */
83struct gpmc_device_timings {
84 u32 t_ceasu; /* address setup to CS valid */
85 u32 t_avdasu; /* address setup to ADV valid */
86 /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
87 * of tusb using these timings even for sync whilst
88 * ideally for adv_rd/(wr)_off it should have considered
89 * t_avdh instead. This indirectly necessitates r/w
90 * variations of t_avdp as it is possible to have one
91 * sync & other async
92 */
93 u32 t_avdp_r; /* ADV low time (what about t_cer ?) */
94 u32 t_avdp_w;
95 u32 t_aavdh; /* address hold time */
96 u32 t_oeasu; /* address setup to OE valid */
97 u32 t_aa; /* access time from ADV assertion */
98 u32 t_iaa; /* initial access time */
99 u32 t_oe; /* access time from OE assertion */
100 u32 t_ce; /* access time from CS asertion */
101 u32 t_rd_cycle; /* read cycle time */
102 u32 t_cez_r; /* read CS deassertion to high Z */
103 u32 t_cez_w; /* write CS deassertion to high Z */
104 u32 t_oez; /* OE deassertion to high Z */
105 u32 t_weasu; /* address setup to WE valid */
106 u32 t_wpl; /* write assertion time */
107 u32 t_wph; /* write deassertion time */
108 u32 t_wr_cycle; /* write cycle time */
109
110 u32 clk;
111 u32 t_bacc; /* burst access valid clock to output delay */
112 u32 t_ces; /* CS setup time to clk */
113 u32 t_avds; /* ADV setup time to clk */
114 u32 t_avdh; /* ADV hold time from clk */
115 u32 t_ach; /* address hold time from clk */
116 u32 t_rdyo; /* clk to ready valid */
117
118 u32 t_ce_rdyz; /* XXX: description ?, or use t_cez instead */
119 u32 t_ce_avd; /* CS on to ADV on delay */
120
121 /* XXX: check the possibility of combining
122 * cyc_aavhd_oe & cyc_aavdh_we
123 */
124 u8 cyc_aavdh_oe;/* read address hold time in cycles */
125 u8 cyc_aavdh_we;/* write address hold time in cycles */
126 u8 cyc_oe; /* access time from OE assertion in cycles */
127 u8 cyc_wpl; /* write deassertion time in cycles */
128 u32 cyc_iaa; /* initial access time in cycles */
129
130 /* extra delays */
131 bool ce_xdelay;
132 bool avd_xdelay;
133 bool oe_xdelay;
134 bool we_xdelay;
135};
136
137struct gpmc_settings {
138 bool burst_wrap; /* enables wrap bursting */
139 bool burst_read; /* enables read page/burst mode */
140 bool burst_write; /* enables write page/burst mode */
141 bool device_nand; /* device is NAND */
142 bool sync_read; /* enables synchronous reads */
143 bool sync_write; /* enables synchronous writes */
144 bool wait_on_read; /* monitor wait on reads */
145 bool wait_on_write; /* monitor wait on writes */
146 u32 burst_len; /* page/burst length */
147 u32 device_width; /* device bus width (8 or 16 bit) */
148 u32 mux_add_data; /* multiplex address & data */
149 u32 wait_pin; /* wait-pin to be used */
150};
151
152extern int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
153 struct gpmc_settings *gpmc_s,
154 struct gpmc_device_timings *dev_t);
155
156struct gpmc_nand_regs;
157struct device_node;
158
159extern void gpmc_update_nand_reg(struct gpmc_nand_regs *reg, int cs);
160extern int gpmc_get_client_irq(unsigned irq_config);
161
162extern unsigned int gpmc_ticks_to_ns(unsigned int ticks);
163
164extern void gpmc_cs_write_reg(int cs, int idx, u32 val);
165extern int gpmc_calc_divider(unsigned int sync_clk);
166extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t);
167extern int gpmc_cs_program_settings(int cs, struct gpmc_settings *p);
168extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base);
169extern void gpmc_cs_free(int cs);
170extern int gpmc_configure(int cmd, int wval);
171extern void gpmc_read_settings_dt(struct device_node *np,
172 struct gpmc_settings *p);
173
174extern void omap3_gpmc_save_context(void);
175extern void omap3_gpmc_restore_context(void);
176
177struct gpmc_timings;
178struct omap_nand_platform_data;
179struct omap_onenand_platform_data;
180
181#if IS_ENABLED(CONFIG_MTD_NAND_OMAP2)
182extern int gpmc_nand_init(struct omap_nand_platform_data *d,
183 struct gpmc_timings *gpmc_t);
184#else
185static inline int gpmc_nand_init(struct omap_nand_platform_data *d,
186 struct gpmc_timings *gpmc_t)
187{
188 return 0;
189}
190#endif
191
192#if IS_ENABLED(CONFIG_MTD_ONENAND_OMAP2)
193extern void gpmc_onenand_init(struct omap_onenand_platform_data *d);
194#else
195#define board_onenand_data NULL
196static inline void gpmc_onenand_init(struct omap_onenand_platform_data *d)
197{
198}
199#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-06-03 11:18:12 -0400