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-rw-r--r--arch/blackfin/Makefile6
-rw-r--r--arch/blackfin/boot/Makefile16
-rw-r--r--arch/blackfin/include/asm/atomic.h2
-rw-r--r--arch/blackfin/include/asm/bfin_sdh.h31
-rw-r--r--arch/blackfin/include/asm/bitops.h1
-rw-r--r--arch/blackfin/include/asm/def_LPBlackfin.h2
-rw-r--r--arch/blackfin/include/asm/mem_init.h9
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbinit.c16
-rw-r--r--arch/blackfin/kernel/cplb-nompu/cplbmgr.c27
-rw-r--r--arch/blackfin/kernel/cplbinfo.c9
-rw-r--r--arch/blackfin/kernel/setup.c2
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c1
-rw-r--r--arch/blackfin/mach-bf538/boards/ezkit.c1
-rw-r--r--arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h2
14 files changed, 101 insertions, 24 deletions
diff --git a/arch/blackfin/Makefile b/arch/blackfin/Makefile
index 66cf00095b84..1fce08632ad7 100644
--- a/arch/blackfin/Makefile
+++ b/arch/blackfin/Makefile
@@ -141,11 +141,11 @@ archclean:
141 141
142INSTALL_PATH ?= /tftpboot 142INSTALL_PATH ?= /tftpboot
143boot := arch/$(ARCH)/boot 143boot := arch/$(ARCH)/boot
144BOOT_TARGETS = vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip 144BOOT_TARGETS = uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
145PHONY += $(BOOT_TARGETS) install 145PHONY += $(BOOT_TARGETS) install
146KBUILD_IMAGE := $(boot)/vmImage 146KBUILD_IMAGE := $(boot)/uImage
147 147
148all: vmImage 148all: uImage
149 149
150$(BOOT_TARGETS): vmlinux 150$(BOOT_TARGETS): vmlinux
151 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@ 151 $(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
diff --git a/arch/blackfin/boot/Makefile b/arch/blackfin/boot/Makefile
index f7d27d50d02c..3efaa094fb90 100644
--- a/arch/blackfin/boot/Makefile
+++ b/arch/blackfin/boot/Makefile
@@ -6,7 +6,7 @@
6# for more details. 6# for more details.
7# 7#
8 8
9targets := vmImage vmImage.bin vmImage.bz2 vmImage.gz vmImage.lzma vmImage.lzo vmImage.xip 9targets := uImage uImage.bin uImage.bz2 uImage.gz uImage.lzma uImage.lzo uImage.xip
10extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip 10extra-y += vmlinux.bin vmlinux.bin.gz vmlinux.bin.bz2 vmlinux.bin.lzma vmlinux.bin.lzo vmlinux.bin.xip
11 11
12ifeq ($(CONFIG_RAMKERNEL),y) 12ifeq ($(CONFIG_RAMKERNEL),y)
@@ -39,22 +39,22 @@ quiet_cmd_mk_bin_xip = BIN $@
39$(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE 39$(obj)/vmlinux.bin.xip: $(obj)/vmlinux.bin FORCE
40 $(call if_changed,mk_bin_xip) 40 $(call if_changed,mk_bin_xip)
41 41
42$(obj)/vmImage.bin: $(obj)/vmlinux.bin 42$(obj)/uImage.bin: $(obj)/vmlinux.bin
43 $(call if_changed,uimage,none) 43 $(call if_changed,uimage,none)
44 44
45$(obj)/vmImage.bz2: $(obj)/vmlinux.bin.bz2 45$(obj)/uImage.bz2: $(obj)/vmlinux.bin.bz2
46 $(call if_changed,uimage,bzip2) 46 $(call if_changed,uimage,bzip2)
47 47
48$(obj)/vmImage.gz: $(obj)/vmlinux.bin.gz 48$(obj)/uImage.gz: $(obj)/vmlinux.bin.gz
49 $(call if_changed,uimage,gzip) 49 $(call if_changed,uimage,gzip)
50 50
51$(obj)/vmImage.lzma: $(obj)/vmlinux.bin.lzma 51$(obj)/uImage.lzma: $(obj)/vmlinux.bin.lzma
52 $(call if_changed,uimage,lzma) 52 $(call if_changed,uimage,lzma)
53 53
54$(obj)/vmImage.lzo: $(obj)/vmlinux.bin.lzo 54$(obj)/uImage.lzo: $(obj)/vmlinux.bin.lzo
55 $(call if_changed,uimage,lzo) 55 $(call if_changed,uimage,lzo)
56 56
57$(obj)/vmImage.xip: $(obj)/vmlinux.bin.xip 57$(obj)/uImage.xip: $(obj)/vmlinux.bin.xip
58 $(call if_changed,uimage,none) 58 $(call if_changed,uimage,none)
59 59
60suffix-y := bin 60suffix-y := bin
@@ -64,7 +64,7 @@ suffix-$(CONFIG_KERNEL_LZMA) := lzma
64suffix-$(CONFIG_KERNEL_LZO) := lzo 64suffix-$(CONFIG_KERNEL_LZO) := lzo
65suffix-$(CONFIG_ROMKERNEL) := xip 65suffix-$(CONFIG_ROMKERNEL) := xip
66 66
67$(obj)/vmImage: $(obj)/vmImage.$(suffix-y) 67$(obj)/uImage: $(obj)/uImage.$(suffix-y)
68 @ln -sf $(notdir $<) $@ 68 @ln -sf $(notdir $<) $@
69 69
70install: 70install:
diff --git a/arch/blackfin/include/asm/atomic.h b/arch/blackfin/include/asm/atomic.h
index c8db653c72d2..a107a98e9978 100644
--- a/arch/blackfin/include/asm/atomic.h
+++ b/arch/blackfin/include/asm/atomic.h
@@ -11,7 +11,9 @@
11 11
12#ifdef CONFIG_SMP 12#ifdef CONFIG_SMP
13 13
14#include <asm/barrier.h>
14#include <linux/linkage.h> 15#include <linux/linkage.h>
16#include <linux/types.h>
15 17
16asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr); 18asmlinkage int __raw_uncached_fetch_asm(const volatile int *ptr);
17asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value); 19asmlinkage int __raw_atomic_update_asm(volatile int *ptr, int value);
diff --git a/arch/blackfin/include/asm/bfin_sdh.h b/arch/blackfin/include/asm/bfin_sdh.h
index 6a4cfe2d3367..a99957ea9e9b 100644
--- a/arch/blackfin/include/asm/bfin_sdh.h
+++ b/arch/blackfin/include/asm/bfin_sdh.h
@@ -24,18 +24,27 @@ struct bfin_sd_host {
24#define CMD_INT_E (1 << 8) /* Command Interrupt */ 24#define CMD_INT_E (1 << 8) /* Command Interrupt */
25#define CMD_PEND_E (1 << 9) /* Command Pending */ 25#define CMD_PEND_E (1 << 9) /* Command Pending */
26#define CMD_E (1 << 10) /* Command Enable */ 26#define CMD_E (1 << 10) /* Command Enable */
27#ifdef RSI_BLKSZ
28#define CMD_CRC_CHECK_D (1 << 11) /* CRC Check is disabled */
29#define CMD_DATA0_BUSY (1 << 12) /* Check for Busy State on the DATA0 pin */
30#endif
27 31
28/* SDH_PWR_CTL bitmasks */ 32/* SDH_PWR_CTL bitmasks */
33#ifndef RSI_BLKSZ
29#define PWR_ON 0x3 /* Power On */ 34#define PWR_ON 0x3 /* Power On */
30#define SD_CMD_OD (1 << 6) /* Open Drain Output */ 35#define SD_CMD_OD (1 << 6) /* Open Drain Output */
31#define ROD_CTL (1 << 7) /* Rod Control */ 36#define ROD_CTL (1 << 7) /* Rod Control */
37#endif
32 38
33/* SDH_CLK_CTL bitmasks */ 39/* SDH_CLK_CTL bitmasks */
34#define CLKDIV 0xff /* MC_CLK Divisor */ 40#define CLKDIV 0xff /* MC_CLK Divisor */
35#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */ 41#define CLK_E (1 << 8) /* MC_CLK Bus Clock Enable */
36#define PWR_SV_E (1 << 9) /* Power Save Enable */ 42#define PWR_SV_E (1 << 9) /* Power Save Enable */
37#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */ 43#define CLKDIV_BYPASS (1 << 10) /* Bypass Divisor */
38#define WIDE_BUS (1 << 11) /* Wide Bus Mode Enable */ 44#define BUS_MODE_MASK 0x1800 /* Bus Mode Mask */
45#define STD_BUS_1 0x000 /* Standard Bus 1 bit mode */
46#define WIDE_BUS_4 0x800 /* Wide Bus 4 bit mode */
47#define BYTE_BUS_8 0x1000 /* Byte Bus 8 bit mode */
39 48
40/* SDH_RESP_CMD bitmasks */ 49/* SDH_RESP_CMD bitmasks */
41#define RESP_CMD 0x3f /* Response Command */ 50#define RESP_CMD 0x3f /* Response Command */
@@ -45,7 +54,13 @@ struct bfin_sd_host {
45#define DTX_DIR (1 << 1) /* Data Transfer Direction */ 54#define DTX_DIR (1 << 1) /* Data Transfer Direction */
46#define DTX_MODE (1 << 2) /* Data Transfer Mode */ 55#define DTX_MODE (1 << 2) /* Data Transfer Mode */
47#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */ 56#define DTX_DMA_E (1 << 3) /* Data Transfer DMA Enable */
57#ifndef RSI_BLKSZ
48#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */ 58#define DTX_BLK_LGTH (0xf << 4) /* Data Transfer Block Length */
59#else
60
61/* Bit masks for SDH_BLK_SIZE */
62#define DTX_BLK_LGTH 0x1fff /* Data Transfer Block Length */
63#endif
49 64
50/* SDH_STATUS bitmasks */ 65/* SDH_STATUS bitmasks */
51#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */ 66#define CMD_CRC_FAIL (1 << 0) /* CMD CRC Fail */
@@ -114,10 +129,14 @@ struct bfin_sd_host {
114/* SDH_E_STATUS bitmasks */ 129/* SDH_E_STATUS bitmasks */
115#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */ 130#define SDIO_INT_DET (1 << 1) /* SDIO Int Detected */
116#define SD_CARD_DET (1 << 4) /* SD Card Detect */ 131#define SD_CARD_DET (1 << 4) /* SD Card Detect */
132#define SD_CARD_BUSYMODE (1 << 31) /* Card is in Busy mode */
133#define SD_CARD_SLPMODE (1 << 30) /* Card in Sleep Mode */
134#define SD_CARD_READY (1 << 17) /* Card Ready */
117 135
118/* SDH_E_MASK bitmasks */ 136/* SDH_E_MASK bitmasks */
119#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */ 137#define SDIO_MSK (1 << 1) /* Mask SDIO Int Detected */
120#define SCD_MSK (1 << 6) /* Mask Card Detect */ 138#define SCD_MSK (1 << 4) /* Mask Card Detect */
139#define CARD_READY_MSK (1 << 16) /* Mask Card Ready */
121 140
122/* SDH_CFG bitmasks */ 141/* SDH_CFG bitmasks */
123#define CLKS_EN (1 << 0) /* Clocks Enable */ 142#define CLKS_EN (1 << 0) /* Clocks Enable */
@@ -126,7 +145,15 @@ struct bfin_sd_host {
126#define SD_RST (1 << 4) /* SDMMC Reset */ 145#define SD_RST (1 << 4) /* SDMMC Reset */
127#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */ 146#define PUP_SDDAT (1 << 5) /* Pull-up SD_DAT */
128#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */ 147#define PUP_SDDAT3 (1 << 6) /* Pull-up SD_DAT3 */
148#ifndef RSI_BLKSZ
129#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */ 149#define PD_SDDAT3 (1 << 7) /* Pull-down SD_DAT3 */
150#else
151#define PWR_ON 0x600 /* Power On */
152#define SD_CMD_OD (1 << 11) /* Open Drain Output */
153#define BOOT_EN (1 << 12) /* Boot Enable */
154#define BOOT_MODE (1 << 13) /* Alternate Boot Mode */
155#define BOOT_ACK_EN (1 << 14) /* Boot ACK is expected */
156#endif
130 157
131/* SDH_RD_WAIT_EN bitmasks */ 158/* SDH_RD_WAIT_EN bitmasks */
132#define RWR (1 << 0) /* Read Wait Request */ 159#define RWR (1 << 0) /* Read Wait Request */
diff --git a/arch/blackfin/include/asm/bitops.h b/arch/blackfin/include/asm/bitops.h
index 8a0fed16058f..0ca40dd44724 100644
--- a/arch/blackfin/include/asm/bitops.h
+++ b/arch/blackfin/include/asm/bitops.h
@@ -41,6 +41,7 @@
41#include <asm-generic/bitops/non-atomic.h> 41#include <asm-generic/bitops/non-atomic.h>
42#else 42#else
43 43
44#include <asm/barrier.h>
44#include <asm/byteorder.h> /* swab32 */ 45#include <asm/byteorder.h> /* swab32 */
45#include <linux/linkage.h> 46#include <linux/linkage.h>
46 47
diff --git a/arch/blackfin/include/asm/def_LPBlackfin.h b/arch/blackfin/include/asm/def_LPBlackfin.h
index fe0ca03a1cb2..ca67145c6a45 100644
--- a/arch/blackfin/include/asm/def_LPBlackfin.h
+++ b/arch/blackfin/include/asm/def_LPBlackfin.h
@@ -622,10 +622,12 @@ do { \
622#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */ 622#define PAGE_SIZE_4KB 0x00010000 /* 4 KB page size */
623#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */ 623#define PAGE_SIZE_1MB 0x00020000 /* 1 MB page size */
624#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */ 624#define PAGE_SIZE_4MB 0x00030000 /* 4 MB page size */
625#ifdef CONFIG_BF60x
625#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */ 626#define PAGE_SIZE_16KB 0x00040000 /* 16 KB page size */
626#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */ 627#define PAGE_SIZE_64KB 0x00050000 /* 64 KB page size */
627#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */ 628#define PAGE_SIZE_16MB 0x00060000 /* 16 MB page size */
628#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */ 629#define PAGE_SIZE_64MB 0x00070000 /* 64 MB page size */
630#endif
629#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not 631#define CPLB_L1SRAM 0x00000020 /* 0=SRAM mapped in L1, 0=SRAM not
630 * mapped to L1 632 * mapped to L1
631 */ 633 */
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 9b33e7247864..c865b33eeb68 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -335,6 +335,7 @@
335struct ddr_config { 335struct ddr_config {
336 u32 ddr_clk; 336 u32 ddr_clk;
337 u32 dmc_ddrctl; 337 u32 dmc_ddrctl;
338 u32 dmc_effctl;
338 u32 dmc_ddrcfg; 339 u32 dmc_ddrcfg;
339 u32 dmc_ddrtr0; 340 u32 dmc_ddrtr0;
340 u32 dmc_ddrtr1; 341 u32 dmc_ddrtr1;
@@ -348,6 +349,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
348 [0] = { 349 [0] = {
349 .ddr_clk = 125, 350 .ddr_clk = 125,
350 .dmc_ddrctl = 0x00000904, 351 .dmc_ddrctl = 0x00000904,
352 .dmc_effctl = 0x004400C0,
351 .dmc_ddrcfg = 0x00000422, 353 .dmc_ddrcfg = 0x00000422,
352 .dmc_ddrtr0 = 0x20705212, 354 .dmc_ddrtr0 = 0x20705212,
353 .dmc_ddrtr1 = 0x201003CF, 355 .dmc_ddrtr1 = 0x201003CF,
@@ -358,6 +360,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
358 [1] = { 360 [1] = {
359 .ddr_clk = 133, 361 .ddr_clk = 133,
360 .dmc_ddrctl = 0x00000904, 362 .dmc_ddrctl = 0x00000904,
363 .dmc_effctl = 0x004400C0,
361 .dmc_ddrcfg = 0x00000422, 364 .dmc_ddrcfg = 0x00000422,
362 .dmc_ddrtr0 = 0x20806313, 365 .dmc_ddrtr0 = 0x20806313,
363 .dmc_ddrtr1 = 0x2013040D, 366 .dmc_ddrtr1 = 0x2013040D,
@@ -368,6 +371,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
368 [2] = { 371 [2] = {
369 .ddr_clk = 150, 372 .ddr_clk = 150,
370 .dmc_ddrctl = 0x00000904, 373 .dmc_ddrctl = 0x00000904,
374 .dmc_effctl = 0x004400C0,
371 .dmc_ddrcfg = 0x00000422, 375 .dmc_ddrcfg = 0x00000422,
372 .dmc_ddrtr0 = 0x20A07323, 376 .dmc_ddrtr0 = 0x20A07323,
373 .dmc_ddrtr1 = 0x20160492, 377 .dmc_ddrtr1 = 0x20160492,
@@ -378,6 +382,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
378 [3] = { 382 [3] = {
379 .ddr_clk = 166, 383 .ddr_clk = 166,
380 .dmc_ddrctl = 0x00000904, 384 .dmc_ddrctl = 0x00000904,
385 .dmc_effctl = 0x004400C0,
381 .dmc_ddrcfg = 0x00000422, 386 .dmc_ddrcfg = 0x00000422,
382 .dmc_ddrtr0 = 0x20A07323, 387 .dmc_ddrtr0 = 0x20A07323,
383 .dmc_ddrtr1 = 0x2016050E, 388 .dmc_ddrtr1 = 0x2016050E,
@@ -388,6 +393,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
388 [4] = { 393 [4] = {
389 .ddr_clk = 200, 394 .ddr_clk = 200,
390 .dmc_ddrctl = 0x00000904, 395 .dmc_ddrctl = 0x00000904,
396 .dmc_effctl = 0x004400C0,
391 .dmc_ddrcfg = 0x00000422, 397 .dmc_ddrcfg = 0x00000422,
392 .dmc_ddrtr0 = 0x20a07323, 398 .dmc_ddrtr0 = 0x20a07323,
393 .dmc_ddrtr1 = 0x2016050f, 399 .dmc_ddrtr1 = 0x2016050f,
@@ -398,6 +404,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
398 [5] = { 404 [5] = {
399 .ddr_clk = 225, 405 .ddr_clk = 225,
400 .dmc_ddrctl = 0x00000904, 406 .dmc_ddrctl = 0x00000904,
407 .dmc_effctl = 0x004400C0,
401 .dmc_ddrcfg = 0x00000422, 408 .dmc_ddrcfg = 0x00000422,
402 .dmc_ddrtr0 = 0x20E0A424, 409 .dmc_ddrtr0 = 0x20E0A424,
403 .dmc_ddrtr1 = 0x302006DB, 410 .dmc_ddrtr1 = 0x302006DB,
@@ -408,6 +415,7 @@ static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1")))
408 [6] = { 415 [6] = {
409 .ddr_clk = 250, 416 .ddr_clk = 250,
410 .dmc_ddrctl = 0x00000904, 417 .dmc_ddrctl = 0x00000904,
418 .dmc_effctl = 0x004400C0,
411 .dmc_ddrcfg = 0x00000422, 419 .dmc_ddrcfg = 0x00000422,
412 .dmc_ddrtr0 = 0x20E0A424, 420 .dmc_ddrtr0 = 0x20E0A424,
413 .dmc_ddrtr1 = 0x3020079E, 421 .dmc_ddrtr1 = 0x3020079E,
@@ -469,6 +477,7 @@ static inline void init_dmc(u32 dmc_clk)
469 bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2); 477 bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
470 bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr); 478 bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
471 bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1); 479 bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
480 bfin_write_DMC0_EFFCTL(ddr_config_table[i].dmc_effctl);
472 bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl); 481 bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
473 break; 482 break;
474 } 483 }
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 34e96ce02aa9..b49a53b583d5 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -30,6 +30,7 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
30{ 30{
31 int i_d, i_i; 31 int i_d, i_i;
32 unsigned long addr; 32 unsigned long addr;
33 unsigned long cplb_pageflags, cplb_pagesize;
33 34
34 struct cplb_entry *d_tbl = dcplb_tbl[cpu]; 35 struct cplb_entry *d_tbl = dcplb_tbl[cpu];
35 struct cplb_entry *i_tbl = icplb_tbl[cpu]; 36 struct cplb_entry *i_tbl = icplb_tbl[cpu];
@@ -49,11 +50,20 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
49 /* Cover kernel memory with 4M pages. */ 50 /* Cover kernel memory with 4M pages. */
50 addr = 0; 51 addr = 0;
51 52
52 for (; addr < memory_start; addr += 4 * 1024 * 1024) { 53#ifdef PAGE_SIZE_16MB
54 cplb_pageflags = PAGE_SIZE_16MB;
55 cplb_pagesize = SIZE_16M;
56#else
57 cplb_pageflags = PAGE_SIZE_4MB;
58 cplb_pagesize = SIZE_4M;
59#endif
60
61
62 for (; addr < memory_start; addr += cplb_pagesize) {
53 d_tbl[i_d].addr = addr; 63 d_tbl[i_d].addr = addr;
54 d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB; 64 d_tbl[i_d++].data = SDRAM_DGENERIC | cplb_pageflags;
55 i_tbl[i_i].addr = addr; 65 i_tbl[i_i].addr = addr;
56 i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB; 66 i_tbl[i_i++].data = SDRAM_IGENERIC | cplb_pageflags;
57 } 67 }
58 68
59#ifdef CONFIG_ROMKERNEL 69#ifdef CONFIG_ROMKERNEL
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
index e854f9066cbd..79cc0f6dcdd5 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbmgr.c
@@ -145,7 +145,7 @@ MGR_ATTR static int dcplb_miss(int cpu)
145 unsigned long addr = bfin_read_DCPLB_FAULT_ADDR(); 145 unsigned long addr = bfin_read_DCPLB_FAULT_ADDR();
146 int status = bfin_read_DCPLB_STATUS(); 146 int status = bfin_read_DCPLB_STATUS();
147 int idx; 147 int idx;
148 unsigned long d_data, base, addr1, eaddr; 148 unsigned long d_data, base, addr1, eaddr, cplb_pagesize, cplb_pageflags;
149 149
150 nr_dcplb_miss[cpu]++; 150 nr_dcplb_miss[cpu]++;
151 if (unlikely(status & FAULT_USERSUPV)) 151 if (unlikely(status & FAULT_USERSUPV))
@@ -167,18 +167,37 @@ MGR_ATTR static int dcplb_miss(int cpu)
167 if (unlikely(d_data == 0)) 167 if (unlikely(d_data == 0))
168 return CPLB_NO_ADDR_MATCH; 168 return CPLB_NO_ADDR_MATCH;
169 169
170 addr1 = addr & ~(SIZE_4M - 1);
171 addr &= ~(SIZE_1M - 1); 170 addr &= ~(SIZE_1M - 1);
172 d_data |= PAGE_SIZE_1MB; 171 d_data |= PAGE_SIZE_1MB;
173 if (addr1 >= base && (addr1 + SIZE_4M) <= eaddr) { 172
173 /* BF60x support large than 4M CPLB page size */
174#ifdef PAGE_SIZE_16MB
175 cplb_pageflags = PAGE_SIZE_16MB;
176 cplb_pagesize = SIZE_16M;
177#else
178 cplb_pageflags = PAGE_SIZE_4MB;
179 cplb_pagesize = SIZE_4M;
180#endif
181
182find_pagesize:
183 addr1 = addr & ~(cplb_pagesize - 1);
184 if (addr1 >= base && (addr1 + cplb_pagesize) <= eaddr) {
174 /* 185 /*
175 * This works because 186 * This works because
176 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB. 187 * (PAGE_SIZE_4MB & PAGE_SIZE_1MB) == PAGE_SIZE_1MB.
177 */ 188 */
178 d_data |= PAGE_SIZE_4MB; 189 d_data |= cplb_pageflags;
179 addr = addr1; 190 addr = addr1;
191 goto found_pagesize;
192 } else {
193 if (cplb_pagesize > SIZE_4M) {
194 cplb_pageflags = PAGE_SIZE_4MB;
195 cplb_pagesize = SIZE_4M;
196 goto find_pagesize;
197 }
180 } 198 }
181 199
200found_pagesize:
182#ifdef CONFIG_BF60x 201#ifdef CONFIG_BF60x
183 if ((addr >= ASYNC_BANK0_BASE) 202 if ((addr >= ASYNC_BANK0_BASE)
184 && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE)) 203 && (addr < ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE))
diff --git a/arch/blackfin/kernel/cplbinfo.c b/arch/blackfin/kernel/cplbinfo.c
index 404045dcc5e4..5b80d59e66e5 100644
--- a/arch/blackfin/kernel/cplbinfo.c
+++ b/arch/blackfin/kernel/cplbinfo.c
@@ -17,8 +17,13 @@
17#include <asm/cplbinit.h> 17#include <asm/cplbinit.h>
18#include <asm/blackfin.h> 18#include <asm/blackfin.h>
19 19
20static char const page_strtbl[][3] = { "1K", "4K", "1M", "4M" }; 20static char const page_strtbl[][4] = {
21#define page(flags) (((flags) & 0x30000) >> 16) 21 "1K", "4K", "1M", "4M",
22#ifdef CONFIG_BF60x
23 "16K", "64K", "16M", "64M",
24#endif
25};
26#define page(flags) (((flags) & 0x70000) >> 16)
22#define strpage(flags) page_strtbl[page(flags)] 27#define strpage(flags) page_strtbl[page(flags)]
23 28
24struct cplbinfo_data { 29struct cplbinfo_data {
diff --git a/arch/blackfin/kernel/setup.c b/arch/blackfin/kernel/setup.c
index fb96e607adcf..107b306b06f1 100644
--- a/arch/blackfin/kernel/setup.c
+++ b/arch/blackfin/kernel/setup.c
@@ -1314,7 +1314,7 @@ static int show_cpuinfo(struct seq_file *m, void *v)
1314 seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid()); 1314 seq_printf(m, "(Compiled for Rev %d)", bfin_compiled_revid());
1315 } 1315 }
1316 1316
1317 seq_printf(m, "\ncpu MHz\t\t: %lu.%03lu/%lu.%03lu\n", 1317 seq_printf(m, "\ncpu MHz\t\t: %lu.%06lu/%lu.%06lu\n",
1318 cclk/1000000, cclk%1000000, 1318 cclk/1000000, cclk%1000000,
1319 sclk/1000000, sclk%1000000); 1319 sclk/1000000, sclk%1000000);
1320 seq_printf(m, "bogomips\t: %lu.%02lu\n" 1320 seq_printf(m, "bogomips\t: %lu.%02lu\n"
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 95114ed395ac..6a3a14bcd3a1 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -455,6 +455,7 @@ static struct platform_device bfin_async_nand_device = {
455static void bfin_plat_nand_init(void) 455static void bfin_plat_nand_init(void)
456{ 456{
457 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat"); 457 gpio_request(BFIN_NAND_PLAT_READY, "bfin_nand_plat");
458 gpio_direction_input(BFIN_NAND_PLAT_READY);
458} 459}
459#else 460#else
460static void bfin_plat_nand_init(void) {} 461static void bfin_plat_nand_init(void) {}
diff --git a/arch/blackfin/mach-bf538/boards/ezkit.c b/arch/blackfin/mach-bf538/boards/ezkit.c
index a4fce0370c1d..755f0dc12010 100644
--- a/arch/blackfin/mach-bf538/boards/ezkit.c
+++ b/arch/blackfin/mach-bf538/boards/ezkit.c
@@ -764,7 +764,6 @@ static struct platform_device i2c_bfin_twi1_device = {
764 .num_resources = ARRAY_SIZE(bfin_twi1_resource), 764 .num_resources = ARRAY_SIZE(bfin_twi1_resource),
765 .resource = bfin_twi1_resource, 765 .resource = bfin_twi1_resource,
766}; 766};
767#endif /* CONFIG_BF542 */
768#endif /* CONFIG_I2C_BLACKFIN_TWI */ 767#endif /* CONFIG_I2C_BLACKFIN_TWI */
769 768
770#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE) 769#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
diff --git a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
index 4954cf3f7e16..102ee4025ac9 100644
--- a/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
+++ b/arch/blackfin/mach-bf609/include/mach/cdefBF60x_base.h
@@ -312,6 +312,8 @@
312#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val) 312#define bfin_write_DMC0_EMR1(val) bfin_write32(DMC0_EMR1, val)
313#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL) 313#define bfin_read_DMC0_CTL() bfin_read32(DMC0_CTL)
314#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val) 314#define bfin_write_DMC0_CTL(val) bfin_write32(DMC0_CTL, val)
315#define bfin_read_DMC0_EFFCTL() bfin_read32(DMC0_EFFCTL)
316#define bfin_write_DMC0_EFFCTL(val) bfin_write32(DMC0_EFFCTL, val)
315#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT) 317#define bfin_read_DMC0_STAT() bfin_read32(DMC0_STAT)
316#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val) 318#define bfin_write_DMC0_STAT(val) bfin_write32(DMC0_STAT, val)
317#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL) 319#define bfin_read_DMC0_DLLCTL() bfin_read32(DMC0_DLLCTL)
generated by cgit v1.2.2 (git 2.25.0) at 2026-04-28 15:03:02 -0400