diff options
-rw-r--r-- | drivers/net/sfc/efx.c | 1 | ||||
-rw-r--r-- | drivers/net/sfc/falcon_xmac.c | 88 | ||||
-rw-r--r-- | drivers/net/sfc/net_driver.h | 2 | ||||
-rw-r--r-- | drivers/net/sfc/sfe4001.c | 12 | ||||
-rw-r--r-- | drivers/net/sfc/tenxpress.c | 51 | ||||
-rw-r--r-- | drivers/net/sfc/workarounds.h | 2 | ||||
-rw-r--r-- | drivers/net/sfc/xfp_phy.c | 1 |
7 files changed, 1 insertions, 156 deletions
diff --git a/drivers/net/sfc/efx.c b/drivers/net/sfc/efx.c index 6d3eb823488e..f65e313c2be2 100644 --- a/drivers/net/sfc/efx.c +++ b/drivers/net/sfc/efx.c | |||
@@ -1750,7 +1750,6 @@ static struct efx_phy_operations efx_dummy_phy_operations = { | |||
1750 | .check_hw = efx_port_dummy_op_int, | 1750 | .check_hw = efx_port_dummy_op_int, |
1751 | .fini = efx_port_dummy_op_void, | 1751 | .fini = efx_port_dummy_op_void, |
1752 | .clear_interrupt = efx_port_dummy_op_void, | 1752 | .clear_interrupt = efx_port_dummy_op_void, |
1753 | .reset_xaui = efx_port_dummy_op_void, | ||
1754 | }; | 1753 | }; |
1755 | 1754 | ||
1756 | static struct efx_board efx_dummy_board_info = { | 1755 | static struct efx_board efx_dummy_board_info = { |
diff --git a/drivers/net/sfc/falcon_xmac.c b/drivers/net/sfc/falcon_xmac.c index 0d9f68ff71e7..d4012314dd01 100644 --- a/drivers/net/sfc/falcon_xmac.c +++ b/drivers/net/sfc/falcon_xmac.c | |||
@@ -78,79 +78,7 @@ static void falcon_setup_xaui(struct efx_nic *efx) | |||
78 | falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG); | 78 | falcon_write(efx, &txdrv, XX_TXDRV_CTL_REG); |
79 | } | 79 | } |
80 | 80 | ||
81 | static void falcon_hold_xaui_in_rst(struct efx_nic *efx) | 81 | int falcon_reset_xaui(struct efx_nic *efx) |
82 | { | ||
83 | efx_oword_t reg; | ||
84 | |||
85 | EFX_ZERO_OWORD(reg); | ||
86 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 1); | ||
87 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 1); | ||
88 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 1); | ||
89 | EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 1); | ||
90 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 1); | ||
91 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 1); | ||
92 | EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 1); | ||
93 | EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 1); | ||
94 | EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 1); | ||
95 | EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 1); | ||
96 | EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSRX_EN, 1); | ||
97 | EFX_SET_OWORD_FIELD(reg, XX_RSTXGXSTX_EN, 1); | ||
98 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
99 | udelay(10); | ||
100 | } | ||
101 | |||
102 | static int _falcon_reset_xaui_a(struct efx_nic *efx) | ||
103 | { | ||
104 | efx_oword_t reg; | ||
105 | |||
106 | falcon_hold_xaui_in_rst(efx); | ||
107 | falcon_read(efx, ®, XX_PWR_RST_REG); | ||
108 | |||
109 | /* Follow the RAMBUS XAUI data reset sequencing | ||
110 | * Channels A and B first: power down, reset PLL, reset, clear | ||
111 | */ | ||
112 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNA_EN, 0); | ||
113 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNB_EN, 0); | ||
114 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
115 | udelay(10); | ||
116 | |||
117 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLAB_EN, 0); | ||
118 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
119 | udelay(10); | ||
120 | |||
121 | EFX_SET_OWORD_FIELD(reg, XX_RESETA_EN, 0); | ||
122 | EFX_SET_OWORD_FIELD(reg, XX_RESETB_EN, 0); | ||
123 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
124 | udelay(10); | ||
125 | |||
126 | /* Channels C and D: power down, reset PLL, reset, clear */ | ||
127 | EFX_SET_OWORD_FIELD(reg, XX_PWRDNC_EN, 0); | ||
128 | EFX_SET_OWORD_FIELD(reg, XX_PWRDND_EN, 0); | ||
129 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
130 | udelay(10); | ||
131 | |||
132 | EFX_SET_OWORD_FIELD(reg, XX_RSTPLLCD_EN, 0); | ||
133 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
134 | udelay(10); | ||
135 | |||
136 | EFX_SET_OWORD_FIELD(reg, XX_RESETC_EN, 0); | ||
137 | EFX_SET_OWORD_FIELD(reg, XX_RESETD_EN, 0); | ||
138 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
139 | udelay(10); | ||
140 | |||
141 | /* Setup XAUI */ | ||
142 | falcon_setup_xaui(efx); | ||
143 | udelay(10); | ||
144 | |||
145 | /* Take XGXS out of reset */ | ||
146 | EFX_ZERO_OWORD(reg); | ||
147 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
148 | udelay(10); | ||
149 | |||
150 | return 0; | ||
151 | } | ||
152 | |||
153 | static int _falcon_reset_xaui_b(struct efx_nic *efx) | ||
154 | { | 82 | { |
155 | efx_oword_t reg; | 83 | efx_oword_t reg; |
156 | int count; | 84 | int count; |
@@ -171,20 +99,6 @@ static int _falcon_reset_xaui_b(struct efx_nic *efx) | |||
171 | return -ETIMEDOUT; | 99 | return -ETIMEDOUT; |
172 | } | 100 | } |
173 | 101 | ||
174 | int falcon_reset_xaui(struct efx_nic *efx) | ||
175 | { | ||
176 | int rc; | ||
177 | |||
178 | if (EFX_WORKAROUND_9388(efx)) { | ||
179 | falcon_hold_xaui_in_rst(efx); | ||
180 | efx->phy_op->reset_xaui(efx); | ||
181 | rc = _falcon_reset_xaui_a(efx); | ||
182 | } else { | ||
183 | rc = _falcon_reset_xaui_b(efx); | ||
184 | } | ||
185 | return rc; | ||
186 | } | ||
187 | |||
188 | static bool falcon_xgmii_status(struct efx_nic *efx) | 102 | static bool falcon_xgmii_status(struct efx_nic *efx) |
189 | { | 103 | { |
190 | efx_oword_t reg; | 104 | efx_oword_t reg; |
diff --git a/drivers/net/sfc/net_driver.h b/drivers/net/sfc/net_driver.h index 567df00090fb..be3d2ba3b74e 100644 --- a/drivers/net/sfc/net_driver.h +++ b/drivers/net/sfc/net_driver.h | |||
@@ -503,7 +503,6 @@ enum efx_fc_type { | |||
503 | * @clear_interrupt: Clear down interrupt | 503 | * @clear_interrupt: Clear down interrupt |
504 | * @blink: Blink LEDs | 504 | * @blink: Blink LEDs |
505 | * @check_hw: Check hardware | 505 | * @check_hw: Check hardware |
506 | * @reset_xaui: Reset XAUI side of PHY for (software sequenced reset) | ||
507 | * @mmds: MMD presence mask | 506 | * @mmds: MMD presence mask |
508 | * @loopbacks: Supported loopback modes mask | 507 | * @loopbacks: Supported loopback modes mask |
509 | */ | 508 | */ |
@@ -513,7 +512,6 @@ struct efx_phy_operations { | |||
513 | void (*reconfigure) (struct efx_nic *efx); | 512 | void (*reconfigure) (struct efx_nic *efx); |
514 | void (*clear_interrupt) (struct efx_nic *efx); | 513 | void (*clear_interrupt) (struct efx_nic *efx); |
515 | int (*check_hw) (struct efx_nic *efx); | 514 | int (*check_hw) (struct efx_nic *efx); |
516 | void (*reset_xaui) (struct efx_nic *efx); | ||
517 | int (*test) (struct efx_nic *efx); | 515 | int (*test) (struct efx_nic *efx); |
518 | int mmds; | 516 | int mmds; |
519 | unsigned loopbacks; | 517 | unsigned loopbacks; |
diff --git a/drivers/net/sfc/sfe4001.c b/drivers/net/sfc/sfe4001.c index b7005da55d5e..fe4e3fd22330 100644 --- a/drivers/net/sfc/sfe4001.c +++ b/drivers/net/sfc/sfe4001.c | |||
@@ -129,18 +129,6 @@ static int sfe4001_poweron(struct efx_nic *efx) | |||
129 | unsigned int i, j; | 129 | unsigned int i, j; |
130 | int rc; | 130 | int rc; |
131 | u8 out; | 131 | u8 out; |
132 | efx_oword_t reg; | ||
133 | |||
134 | /* Ensure that XGXS and XAUI SerDes are held in reset */ | ||
135 | EFX_POPULATE_OWORD_7(reg, XX_PWRDNA_EN, 1, | ||
136 | XX_PWRDNB_EN, 1, | ||
137 | XX_RSTPLLAB_EN, 1, | ||
138 | XX_RESETA_EN, 1, | ||
139 | XX_RESETB_EN, 1, | ||
140 | XX_RSTXGXSRX_EN, 1, | ||
141 | XX_RSTXGXSTX_EN, 1); | ||
142 | falcon_write(efx, ®, XX_PWR_RST_REG); | ||
143 | udelay(10); | ||
144 | 132 | ||
145 | /* Clear any previous over-temperature alert */ | 133 | /* Clear any previous over-temperature alert */ |
146 | rc = i2c_smbus_read_byte_data(hwmon_client, RSL); | 134 | rc = i2c_smbus_read_byte_data(hwmon_client, RSL); |
diff --git a/drivers/net/sfc/tenxpress.c b/drivers/net/sfc/tenxpress.c index 8412dbe1e8fb..77e7f3a94b25 100644 --- a/drivers/net/sfc/tenxpress.c +++ b/drivers/net/sfc/tenxpress.c | |||
@@ -146,8 +146,6 @@ static int tenxpress_phy_check(struct efx_nic *efx) | |||
146 | return 0; | 146 | return 0; |
147 | } | 147 | } |
148 | 148 | ||
149 | static void tenxpress_reset_xaui(struct efx_nic *efx); | ||
150 | |||
151 | static int tenxpress_init(struct efx_nic *efx) | 149 | static int tenxpress_init(struct efx_nic *efx) |
152 | { | 150 | { |
153 | int rc, reg; | 151 | int rc, reg; |
@@ -428,54 +426,6 @@ void tenxpress_phy_blink(struct efx_nic *efx, bool blink) | |||
428 | PMA_PMD_LED_OVERR_REG, reg); | 426 | PMA_PMD_LED_OVERR_REG, reg); |
429 | } | 427 | } |
430 | 428 | ||
431 | static void tenxpress_reset_xaui(struct efx_nic *efx) | ||
432 | { | ||
433 | int phy = efx->mii.phy_id; | ||
434 | int clk_ctrl, test_select, soft_rst2; | ||
435 | |||
436 | /* Real work is done on clock_ctrl other resets are thought to be | ||
437 | * optional but make the reset more reliable | ||
438 | */ | ||
439 | |||
440 | /* Read */ | ||
441 | clk_ctrl = mdio_clause45_read(efx, phy, MDIO_MMD_PCS, | ||
442 | PCS_CLOCK_CTRL_REG); | ||
443 | test_select = mdio_clause45_read(efx, phy, MDIO_MMD_PCS, | ||
444 | PCS_TEST_SELECT_REG); | ||
445 | soft_rst2 = mdio_clause45_read(efx, phy, MDIO_MMD_PCS, | ||
446 | PCS_SOFT_RST2_REG); | ||
447 | |||
448 | /* Put in reset */ | ||
449 | test_select &= ~(1 << CLK312_EN_LBN); | ||
450 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | ||
451 | PCS_TEST_SELECT_REG, test_select); | ||
452 | |||
453 | soft_rst2 &= ~((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN)); | ||
454 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | ||
455 | PCS_SOFT_RST2_REG, soft_rst2); | ||
456 | |||
457 | clk_ctrl &= ~(1 << PLL312_RST_N_LBN); | ||
458 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | ||
459 | PCS_CLOCK_CTRL_REG, clk_ctrl); | ||
460 | udelay(10); | ||
461 | |||
462 | /* Remove reset */ | ||
463 | clk_ctrl |= (1 << PLL312_RST_N_LBN); | ||
464 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | ||
465 | PCS_CLOCK_CTRL_REG, clk_ctrl); | ||
466 | udelay(10); | ||
467 | |||
468 | soft_rst2 |= ((1 << XGXS_RST_N_LBN) | (1 << SERDES_RST_N_LBN)); | ||
469 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | ||
470 | PCS_SOFT_RST2_REG, soft_rst2); | ||
471 | udelay(10); | ||
472 | |||
473 | test_select |= (1 << CLK312_EN_LBN); | ||
474 | mdio_clause45_write(efx, phy, MDIO_MMD_PCS, | ||
475 | PCS_TEST_SELECT_REG, test_select); | ||
476 | udelay(10); | ||
477 | } | ||
478 | |||
479 | static int tenxpress_phy_test(struct efx_nic *efx) | 429 | static int tenxpress_phy_test(struct efx_nic *efx) |
480 | { | 430 | { |
481 | /* BIST is automatically run after a special software reset */ | 431 | /* BIST is automatically run after a special software reset */ |
@@ -488,7 +438,6 @@ struct efx_phy_operations falcon_tenxpress_phy_ops = { | |||
488 | .check_hw = tenxpress_phy_check_hw, | 438 | .check_hw = tenxpress_phy_check_hw, |
489 | .fini = tenxpress_phy_fini, | 439 | .fini = tenxpress_phy_fini, |
490 | .clear_interrupt = tenxpress_phy_clear_interrupt, | 440 | .clear_interrupt = tenxpress_phy_clear_interrupt, |
491 | .reset_xaui = tenxpress_reset_xaui, | ||
492 | .test = tenxpress_phy_test, | 441 | .test = tenxpress_phy_test, |
493 | .mmds = TENXPRESS_REQUIRED_DEVS, | 442 | .mmds = TENXPRESS_REQUIRED_DEVS, |
494 | .loopbacks = TENXPRESS_LOOPBACKS, | 443 | .loopbacks = TENXPRESS_LOOPBACKS, |
diff --git a/drivers/net/sfc/workarounds.h b/drivers/net/sfc/workarounds.h index a824f5998c04..fa7b49d69288 100644 --- a/drivers/net/sfc/workarounds.h +++ b/drivers/net/sfc/workarounds.h | |||
@@ -24,8 +24,6 @@ | |||
24 | #define EFX_WORKAROUND_7575 EFX_WORKAROUND_ALWAYS | 24 | #define EFX_WORKAROUND_7575 EFX_WORKAROUND_ALWAYS |
25 | /* TX pkt parser problem with <= 16 byte TXes */ | 25 | /* TX pkt parser problem with <= 16 byte TXes */ |
26 | #define EFX_WORKAROUND_9141 EFX_WORKAROUND_ALWAYS | 26 | #define EFX_WORKAROUND_9141 EFX_WORKAROUND_ALWAYS |
27 | /* XGXS and XAUI reset sequencing in SW */ | ||
28 | #define EFX_WORKAROUND_9388 EFX_WORKAROUND_ALWAYS | ||
29 | /* Low rate CRC errors require XAUI reset */ | 27 | /* Low rate CRC errors require XAUI reset */ |
30 | #define EFX_WORKAROUND_10750 EFX_WORKAROUND_ALWAYS | 28 | #define EFX_WORKAROUND_10750 EFX_WORKAROUND_ALWAYS |
31 | /* TX_EV_PKT_ERR can be caused by a dangling TX descriptor | 29 | /* TX_EV_PKT_ERR can be caused by a dangling TX descriptor |
diff --git a/drivers/net/sfc/xfp_phy.c b/drivers/net/sfc/xfp_phy.c index f6edecc2e588..276151df3a70 100644 --- a/drivers/net/sfc/xfp_phy.c +++ b/drivers/net/sfc/xfp_phy.c | |||
@@ -165,7 +165,6 @@ struct efx_phy_operations falcon_xfp_phy_ops = { | |||
165 | .check_hw = xfp_phy_check_hw, | 165 | .check_hw = xfp_phy_check_hw, |
166 | .fini = xfp_phy_fini, | 166 | .fini = xfp_phy_fini, |
167 | .clear_interrupt = xfp_phy_clear_interrupt, | 167 | .clear_interrupt = xfp_phy_clear_interrupt, |
168 | .reset_xaui = efx_port_dummy_op_void, | ||
169 | .mmds = XFP_REQUIRED_DEVS, | 168 | .mmds = XFP_REQUIRED_DEVS, |
170 | .loopbacks = XFP_LOOPBACKS, | 169 | .loopbacks = XFP_LOOPBACKS, |
171 | }; | 170 | }; |