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-rw-r--r--arch/blackfin/Kconfig2
-rw-r--r--arch/blackfin/configs/BF533-EZKIT_defconfig7
-rw-r--r--arch/blackfin/configs/BF609-EZKIT_defconfig16
-rw-r--r--arch/blackfin/kernel/bfin_gpio.c4
-rw-r--r--arch/blackfin/kernel/reboot.c1
-rw-r--r--arch/blackfin/mach-bf537/boards/cm_bf537e.c130
-rw-r--r--arch/blackfin/mach-bf537/boards/stamp.c2
-rw-r--r--arch/blackfin/mach-bf609/include/mach/defBF609.h271
-rw-r--r--arch/blackfin/mach-common/cpufreq.c9
-rw-r--r--arch/blackfin/mach-common/ints-priority.c1
-rw-r--r--arch/blackfin/mach-common/smp.c4
11 files changed, 416 insertions, 31 deletions
diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index c7092e6057c5..99224c4eb86b 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -298,7 +298,7 @@ config BF_REV_0_3
298 298
299config BF_REV_0_4 299config BF_REV_0_4
300 bool "0.4" 300 bool "0.4"
301 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539) 301 depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539 || BF54x)
302 302
303config BF_REV_0_5 303config BF_REV_0_5
304 bool "0.5" 304 bool "0.5"
diff --git a/arch/blackfin/configs/BF533-EZKIT_defconfig b/arch/blackfin/configs/BF533-EZKIT_defconfig
index 127f20df75a0..16273a922056 100644
--- a/arch/blackfin/configs/BF533-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF533-EZKIT_defconfig
@@ -52,10 +52,13 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
52CONFIG_MTD=y 52CONFIG_MTD=y
53CONFIG_MTD_CHAR=m 53CONFIG_MTD_CHAR=m
54CONFIG_MTD_BLOCK=y 54CONFIG_MTD_BLOCK=y
55CONFIG_MTD_JEDECPROBE=m 55CONFIG_MTD_JEDECPROBE=y
56CONFIG_MTD_CFI_AMDSTD=y
56CONFIG_MTD_RAM=y 57CONFIG_MTD_RAM=y
57CONFIG_MTD_ROM=m 58CONFIG_MTD_ROM=y
58CONFIG_MTD_COMPLEX_MAPPINGS=y 59CONFIG_MTD_COMPLEX_MAPPINGS=y
60CONFIG_MTD_PHYSMAP=y
61CONFIG_MTD_PLATRAM=y
59CONFIG_BLK_DEV_RAM=y 62CONFIG_BLK_DEV_RAM=y
60CONFIG_NETDEVICES=y 63CONFIG_NETDEVICES=y
61# CONFIG_NET_VENDOR_BROADCOM is not set 64# CONFIG_NET_VENDOR_BROADCOM is not set
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig
index f4b02350e415..13eb73231a9a 100644
--- a/arch/blackfin/configs/BF609-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF609-EZKIT_defconfig
@@ -1,5 +1,6 @@
1CONFIG_EXPERIMENTAL=y 1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y 2CONFIG_SYSVIPC=y
3CONFIG_HIGH_RES_TIMERS=y
3CONFIG_IKCONFIG=y 4CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y 5CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=14 6CONFIG_LOG_BUF_SHIFT=14
@@ -24,7 +25,6 @@ CONFIG_BF609=y
24CONFIG_PINT1_ASSIGN=0x01010000 25CONFIG_PINT1_ASSIGN=0x01010000
25CONFIG_PINT2_ASSIGN=0x07000101 26CONFIG_PINT2_ASSIGN=0x07000101
26CONFIG_PINT3_ASSIGN=0x02020303 27CONFIG_PINT3_ASSIGN=0x02020303
27CONFIG_HIGH_RES_TIMERS=y
28CONFIG_IP_CHECKSUM_L1=y 28CONFIG_IP_CHECKSUM_L1=y
29CONFIG_SYSCALL_TAB_L1=y 29CONFIG_SYSCALL_TAB_L1=y
30CONFIG_CPLB_SWITCH_TAB_L1=y 30CONFIG_CPLB_SWITCH_TAB_L1=y
@@ -116,9 +116,6 @@ CONFIG_SND_PCM_OSS=m
116# CONFIG_SND_SPI is not set 116# CONFIG_SND_SPI is not set
117# CONFIG_SND_USB is not set 117# CONFIG_SND_USB is not set
118CONFIG_SND_SOC=m 118CONFIG_SND_SOC=m
119CONFIG_SND_BF6XX_I2S=m
120CONFIG_SND_SOC_BFIN_EVAL_ADAU1X61=m
121CONFIG_SND_SOC_ALL_CODECS=m
122CONFIG_USB=y 119CONFIG_USB=y
123CONFIG_USB_MUSB_HDRC=y 120CONFIG_USB_MUSB_HDRC=y
124CONFIG_USB_MUSB_BLACKFIN=m 121CONFIG_USB_MUSB_BLACKFIN=m
@@ -136,7 +133,6 @@ CONFIG_VFAT_FS=y
136CONFIG_JFFS2_FS=m 133CONFIG_JFFS2_FS=m
137CONFIG_UBIFS_FS=m 134CONFIG_UBIFS_FS=m
138CONFIG_NFS_FS=m 135CONFIG_NFS_FS=m
139CONFIG_NFS_V3=y
140CONFIG_NLS_CODEPAGE_437=y 136CONFIG_NLS_CODEPAGE_437=y
141CONFIG_NLS_ISO8859_1=y 137CONFIG_NLS_ISO8859_1=y
142CONFIG_DEBUG_FS=y 138CONFIG_DEBUG_FS=y
@@ -149,9 +145,9 @@ CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION_ONE=y
149CONFIG_EARLY_PRINTK=y 145CONFIG_EARLY_PRINTK=y
150CONFIG_CPLB_INFO=y 146CONFIG_CPLB_INFO=y
151CONFIG_BFIN_PSEUDODBG_INSNS=y 147CONFIG_BFIN_PSEUDODBG_INSNS=y
152CONFIG_CRYPTO_HMAC=y 148CONFIG_CRYPTO_HMAC=m
153CONFIG_CRYPTO_MD4=y 149CONFIG_CRYPTO_MD4=m
154CONFIG_CRYPTO_MD5=y 150CONFIG_CRYPTO_MD5=m
155CONFIG_CRYPTO_ARC4=y 151CONFIG_CRYPTO_ARC4=m
156# CONFIG_CRYPTO_ANSI_CPRNG is not set 152# CONFIG_CRYPTO_ANSI_CPRNG is not set
157CONFIG_CRYPTO_DEV_BFIN_CRC=y 153CONFIG_CRYPTO_DEV_BFIN_CRC=m
diff --git a/arch/blackfin/kernel/bfin_gpio.c b/arch/blackfin/kernel/bfin_gpio.c
index 83139aaf3072..ed978f1c5cb9 100644
--- a/arch/blackfin/kernel/bfin_gpio.c
+++ b/arch/blackfin/kernel/bfin_gpio.c
@@ -1265,8 +1265,8 @@ static __init int gpio_register_proc(void)
1265{ 1265{
1266 struct proc_dir_entry *proc_gpio; 1266 struct proc_dir_entry *proc_gpio;
1267 1267
1268 proc_gpio = proc_create("gpio", S_IRUGO, NULL, &gpio_proc_ops); 1268 proc_gpio = proc_create("gpio", 0, NULL, &gpio_proc_ops);
1269 return proc_gpio != NULL; 1269 return proc_gpio == NULL;
1270} 1270}
1271__initcall(gpio_register_proc); 1271__initcall(gpio_register_proc);
1272#endif 1272#endif
diff --git a/arch/blackfin/kernel/reboot.c b/arch/blackfin/kernel/reboot.c
index 5272e6eefd92..c4f50a328501 100644
--- a/arch/blackfin/kernel/reboot.c
+++ b/arch/blackfin/kernel/reboot.c
@@ -86,7 +86,6 @@ void native_machine_restart(char *cmd)
86void machine_restart(char *cmd) 86void machine_restart(char *cmd)
87{ 87{
88 native_machine_restart(cmd); 88 native_machine_restart(cmd);
89 local_irq_disable();
90 if (smp_processor_id()) 89 if (smp_processor_id())
91 smp_call_function((void *)bfin_reset, 0, 1); 90 smp_call_function((void *)bfin_reset, 0, 1);
92 else 91 else
diff --git a/arch/blackfin/mach-bf537/boards/cm_bf537e.c b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
index 9408ab56d87f..85e4fc9f9c22 100644
--- a/arch/blackfin/mach-bf537/boards/cm_bf537e.c
+++ b/arch/blackfin/mach-bf537/boards/cm_bf537e.c
@@ -25,6 +25,7 @@
25#include <asm/bfin5xx_spi.h> 25#include <asm/bfin5xx_spi.h>
26#include <asm/portmux.h> 26#include <asm/portmux.h>
27#include <asm/dpmc.h> 27#include <asm/dpmc.h>
28#include <asm/bfin_sport.h>
28 29
29/* 30/*
30 * Name the Board for the /proc/cpuinfo 31 * Name the Board for the /proc/cpuinfo
@@ -143,6 +144,71 @@ static struct platform_device bfin_spi0_device = {
143}; 144};
144#endif /* spi master and devices */ 145#endif /* spi master and devices */
145 146
147#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
148
149/* SPORT SPI controller data */
150static struct bfin5xx_spi_master bfin_sport_spi0_info = {
151 .num_chipselect = MAX_BLACKFIN_GPIOS,
152 .enable_dma = 0, /* master don't support DMA */
153 .pin_req = {P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_DRPRI,
154 P_SPORT0_RSCLK, P_SPORT0_TFS, P_SPORT0_RFS, 0},
155};
156
157static struct resource bfin_sport_spi0_resource[] = {
158 [0] = {
159 .start = SPORT0_TCR1,
160 .end = SPORT0_TCR1 + 0xFF,
161 .flags = IORESOURCE_MEM,
162 },
163 [1] = {
164 .start = IRQ_SPORT0_ERROR,
165 .end = IRQ_SPORT0_ERROR,
166 .flags = IORESOURCE_IRQ,
167 },
168};
169
170static struct platform_device bfin_sport_spi0_device = {
171 .name = "bfin-sport-spi",
172 .id = 1, /* Bus number */
173 .num_resources = ARRAY_SIZE(bfin_sport_spi0_resource),
174 .resource = bfin_sport_spi0_resource,
175 .dev = {
176 .platform_data = &bfin_sport_spi0_info, /* Passed to driver */
177 },
178};
179
180static struct bfin5xx_spi_master bfin_sport_spi1_info = {
181 .num_chipselect = MAX_BLACKFIN_GPIOS,
182 .enable_dma = 0, /* master don't support DMA */
183 .pin_req = {P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_DRPRI,
184 P_SPORT1_RSCLK, P_SPORT1_TFS, P_SPORT1_RFS, 0},
185};
186
187static struct resource bfin_sport_spi1_resource[] = {
188 [0] = {
189 .start = SPORT1_TCR1,
190 .end = SPORT1_TCR1 + 0xFF,
191 .flags = IORESOURCE_MEM,
192 },
193 [1] = {
194 .start = IRQ_SPORT1_ERROR,
195 .end = IRQ_SPORT1_ERROR,
196 .flags = IORESOURCE_IRQ,
197 },
198};
199
200static struct platform_device bfin_sport_spi1_device = {
201 .name = "bfin-sport-spi",
202 .id = 2, /* Bus number */
203 .num_resources = ARRAY_SIZE(bfin_sport_spi1_resource),
204 .resource = bfin_sport_spi1_resource,
205 .dev = {
206 .platform_data = &bfin_sport_spi1_info, /* Passed to driver */
207 },
208};
209
210#endif /* sport spi master and devices */
211
146#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE) 212#if defined(CONFIG_RTC_DRV_BFIN) || defined(CONFIG_RTC_DRV_BFIN_MODULE)
147static struct platform_device rtc_device = { 213static struct platform_device rtc_device = {
148 .name = "rtc-bfin", 214 .name = "rtc-bfin",
@@ -512,6 +578,13 @@ static struct platform_device i2c_bfin_twi_device = {
512}; 578};
513#endif 579#endif
514 580
581#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) \
582|| defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
583unsigned short bfin_sport0_peripherals[] = {
584 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
585 P_SPORT0_DRPRI, P_SPORT0_RSCLK, P_SPORT0_DRSEC, P_SPORT0_DTSEC, 0
586};
587#endif
515#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE) 588#if defined(CONFIG_SERIAL_BFIN_SPORT) || defined(CONFIG_SERIAL_BFIN_SPORT_MODULE)
516#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART 589#ifdef CONFIG_SERIAL_BFIN_SPORT0_UART
517static struct resource bfin_sport0_uart_resources[] = { 590static struct resource bfin_sport0_uart_resources[] = {
@@ -532,11 +605,6 @@ static struct resource bfin_sport0_uart_resources[] = {
532 }, 605 },
533}; 606};
534 607
535static unsigned short bfin_sport0_peripherals[] = {
536 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
537 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
538};
539
540static struct platform_device bfin_sport0_uart_device = { 608static struct platform_device bfin_sport0_uart_device = {
541 .name = "bfin-sport-uart", 609 .name = "bfin-sport-uart",
542 .id = 0, 610 .id = 0,
@@ -582,6 +650,49 @@ static struct platform_device bfin_sport1_uart_device = {
582}; 650};
583#endif 651#endif
584#endif 652#endif
653#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
654static struct resource bfin_sport0_resources[] = {
655 {
656 .start = SPORT0_TCR1,
657 .end = SPORT0_MRCS3+4,
658 .flags = IORESOURCE_MEM,
659 },
660 {
661 .start = IRQ_SPORT0_RX,
662 .end = IRQ_SPORT0_RX+1,
663 .flags = IORESOURCE_IRQ,
664 },
665 {
666 .start = IRQ_SPORT0_TX,
667 .end = IRQ_SPORT0_TX+1,
668 .flags = IORESOURCE_IRQ,
669 },
670 {
671 .start = IRQ_SPORT0_ERROR,
672 .end = IRQ_SPORT0_ERROR,
673 .flags = IORESOURCE_IRQ,
674 },
675 {
676 .start = CH_SPORT0_TX,
677 .end = CH_SPORT0_TX,
678 .flags = IORESOURCE_DMA,
679 },
680 {
681 .start = CH_SPORT0_RX,
682 .end = CH_SPORT0_RX,
683 .flags = IORESOURCE_DMA,
684 },
685};
686static struct platform_device bfin_sport0_device = {
687 .name = "bfin_sport_raw",
688 .id = 0,
689 .num_resources = ARRAY_SIZE(bfin_sport0_resources),
690 .resource = bfin_sport0_resources,
691 .dev = {
692 .platform_data = &bfin_sport0_peripherals, /* Passed to driver */
693 },
694};
695#endif
585 696
586#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) 697#if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)
587#include <linux/bfin_mac.h> 698#include <linux/bfin_mac.h>
@@ -684,6 +795,10 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
684 795
685 &bfin_dpmc, 796 &bfin_dpmc,
686 797
798#if defined(CONFIG_BFIN_SPORT) || defined(CONFIG_BFIN_SPORT_MODULE)
799 &bfin_sport0_device,
800#endif
801
687#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE) 802#if defined(CONFIG_FB_HITACHI_TX09) || defined(CONFIG_FB_HITACHI_TX09_MODULE)
688 &hitachi_fb_device, 803 &hitachi_fb_device,
689#endif 804#endif
@@ -744,6 +859,11 @@ static struct platform_device *cm_bf537e_devices[] __initdata = {
744 &bfin_spi0_device, 859 &bfin_spi0_device,
745#endif 860#endif
746 861
862#if defined(CONFIG_SPI_BFIN_SPORT) || defined(CONFIG_SPI_BFIN_SPORT_MODULE)
863 &bfin_sport_spi0_device,
864 &bfin_sport_spi1_device,
865#endif
866
747#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE) 867#if defined(CONFIG_PATA_PLATFORM) || defined(CONFIG_PATA_PLATFORM_MODULE)
748 &bfin_pata_device, 868 &bfin_pata_device,
749#endif 869#endif
diff --git a/arch/blackfin/mach-bf537/boards/stamp.c b/arch/blackfin/mach-bf537/boards/stamp.c
index 307bd7e62f43..95114ed395ac 100644
--- a/arch/blackfin/mach-bf537/boards/stamp.c
+++ b/arch/blackfin/mach-bf537/boards/stamp.c
@@ -1525,7 +1525,7 @@ static struct platform_device bfin_sport_spi1_device = {
1525 1525
1526#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE) 1526#if defined(CONFIG_FB_BF537_LQ035) || defined(CONFIG_FB_BF537_LQ035_MODULE)
1527static struct platform_device bfin_fb_device = { 1527static struct platform_device bfin_fb_device = {
1528 .name = "bf537-lq035", 1528 .name = "bf537_lq035",
1529}; 1529};
1530#endif 1530#endif
1531 1531
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF609.h b/arch/blackfin/mach-bf609/include/mach/defBF609.h
index 19690cc42113..8045ade34370 100644
--- a/arch/blackfin/mach-bf609/include/mach/defBF609.h
+++ b/arch/blackfin/mach-bf609/include/mach/defBF609.h
@@ -11,5 +11,276 @@
11#include "defBF60x_base.h" 11#include "defBF60x_base.h"
12 12
13/* The following are the #defines needed by ADSP-BF609 that are not in the common header */ 13/* The following are the #defines needed by ADSP-BF609 that are not in the common header */
14/* =========================
15 PIXC Registers
16 ========================= */
17
18/* =========================
19 PIXC0
20 ========================= */
21#define PIXC0_CTL 0xFFC19000 /* PIXC0 Control Register */
22#define PIXC0_PPL 0xFFC19004 /* PIXC0 Pixels Per Line Register */
23#define PIXC0_LPF 0xFFC19008 /* PIXC0 Line Per Frame Register */
24#define PIXC0_HSTART_A 0xFFC1900C /* PIXC0 Overlay A Horizontal Start Register */
25#define PIXC0_HEND_A 0xFFC19010 /* PIXC0 Overlay A Horizontal End Register */
26#define PIXC0_VSTART_A 0xFFC19014 /* PIXC0 Overlay A Vertical Start Register */
27#define PIXC0_VEND_A 0xFFC19018 /* PIXC0 Overlay A Vertical End Register */
28#define PIXC0_TRANSP_A 0xFFC1901C /* PIXC0 Overlay A Transparency Ratio Register */
29#define PIXC0_HSTART_B 0xFFC19020 /* PIXC0 Overlay B Horizontal Start Register */
30#define PIXC0_HEND_B 0xFFC19024 /* PIXC0 Overlay B Horizontal End Register */
31#define PIXC0_VSTART_B 0xFFC19028 /* PIXC0 Overlay B Vertical Start Register */
32#define PIXC0_VEND_B 0xFFC1902C /* PIXC0 Overlay B Vertical End Register */
33#define PIXC0_TRANSP_B 0xFFC19030 /* PIXC0 Overlay B Transparency Ratio Register */
34#define PIXC0_IRQSTAT 0xFFC1903C /* PIXC0 Interrupt Status Register */
35#define PIXC0_CONRY 0xFFC19040 /* PIXC0 RY Conversion Component Register */
36#define PIXC0_CONGU 0xFFC19044 /* PIXC0 GU Conversion Component Register */
37#define PIXC0_CONBV 0xFFC19048 /* PIXC0 BV Conversion Component Register */
38#define PIXC0_CCBIAS 0xFFC1904C /* PIXC0 Conversion Bias Register */
39#define PIXC0_TC 0xFFC19050 /* PIXC0 Transparency Register */
40#define PIXC0_REVID 0xFFC19054 /* PIXC0 PIXC Revision Id */
41
42/* =========================
43 PVP Registers
44 ========================= */
45
46/* =========================
47 PVP0
48 ========================= */
49#define PVP0_REVID 0xFFC1A000 /* PVP0 Revision ID */
50#define PVP0_CTL 0xFFC1A004 /* PVP0 Control */
51#define PVP0_IMSK0 0xFFC1A008 /* PVP0 INTn interrupt line masks */
52#define PVP0_IMSK1 0xFFC1A00C /* PVP0 INTn interrupt line masks */
53#define PVP0_STAT 0xFFC1A010 /* PVP0 Status */
54#define PVP0_ILAT 0xFFC1A014 /* PVP0 Latched status */
55#define PVP0_IREQ0 0xFFC1A018 /* PVP0 INT0 masked latched status */
56#define PVP0_IREQ1 0xFFC1A01C /* PVP0 INT0 masked latched status */
57#define PVP0_OPF0_CFG 0xFFC1A020 /* PVP0 Config */
58#define PVP0_OPF1_CFG 0xFFC1A040 /* PVP0 Config */
59#define PVP0_OPF2_CFG 0xFFC1A060 /* PVP0 Config */
60#define PVP0_OPF0_CTL 0xFFC1A024 /* PVP0 Control */
61#define PVP0_OPF1_CTL 0xFFC1A044 /* PVP0 Control */
62#define PVP0_OPF2_CTL 0xFFC1A064 /* PVP0 Control */
63#define PVP0_OPF3_CFG 0xFFC1A080 /* PVP0 Config */
64#define PVP0_OPF3_CTL 0xFFC1A084 /* PVP0 Control */
65#define PVP0_PEC_CFG 0xFFC1A0A0 /* PVP0 Config */
66#define PVP0_PEC_CTL 0xFFC1A0A4 /* PVP0 Control */
67#define PVP0_PEC_D1TH0 0xFFC1A0A8 /* PVP0 Lower Hysteresis Threshold */
68#define PVP0_PEC_D1TH1 0xFFC1A0AC /* PVP0 Upper Hysteresis Threshold */
69#define PVP0_PEC_D2TH0 0xFFC1A0B0 /* PVP0 Weak Zero Crossing Threshold */
70#define PVP0_PEC_D2TH1 0xFFC1A0B4 /* PVP0 Strong Zero Crossing Threshold */
71#define PVP0_IIM0_CFG 0xFFC1A0C0 /* PVP0 Config */
72#define PVP0_IIM1_CFG 0xFFC1A0E0 /* PVP0 Config */
73#define PVP0_IIM0_CTL 0xFFC1A0C4 /* PVP0 Control */
74#define PVP0_IIM1_CTL 0xFFC1A0E4 /* PVP0 Control */
75#define PVP0_IIM0_SCALE 0xFFC1A0C8 /* PVP0 Scaler Values */
76#define PVP0_IIM1_SCALE 0xFFC1A0E8 /* PVP0 Scaler Values */
77#define PVP0_IIM0_SOVF_STAT 0xFFC1A0CC /* PVP0 Signed Overflow Status */
78#define PVP0_IIM1_SOVF_STAT 0xFFC1A0EC /* PVP0 Signed Overflow Status */
79#define PVP0_IIM0_UOVF_STAT 0xFFC1A0D0 /* PVP0 Unsigned Overflow Status */
80#define PVP0_IIM1_UOVF_STAT 0xFFC1A0F0 /* PVP0 Unsigned Overflow Status */
81#define PVP0_ACU_CFG 0xFFC1A100 /* PVP0 ACU Configuration Register */
82#define PVP0_ACU_CTL 0xFFC1A104 /* PVP0 ACU Control Register */
83#define PVP0_ACU_OFFSET 0xFFC1A108 /* PVP0 SUM constant register */
84#define PVP0_ACU_FACTOR 0xFFC1A10C /* PVP0 PROD constant register */
85#define PVP0_ACU_SHIFT 0xFFC1A110 /* PVP0 Shift constant register */
86#define PVP0_ACU_MIN 0xFFC1A114 /* PVP0 Lower saturation threshold set to MIN */
87#define PVP0_ACU_MAX 0xFFC1A118 /* PVP0 Upper saturation threshold set to MAX */
88#define PVP0_UDS_CFG 0xFFC1A140 /* PVP0 UDS Configuration Register */
89#define PVP0_UDS_CTL 0xFFC1A144 /* PVP0 UDS Control Register */
90#define PVP0_UDS_OHCNT 0xFFC1A148 /* PVP0 UDS Output H Dimension */
91#define PVP0_UDS_OVCNT 0xFFC1A14C /* PVP0 UDS Output V Dimension */
92#define PVP0_UDS_HAVG 0xFFC1A150 /* PVP0 UDS H Taps */
93#define PVP0_UDS_VAVG 0xFFC1A154 /* PVP0 UDS V Taps */
94#define PVP0_IPF0_CFG 0xFFC1A180 /* PVP0 Configuration */
95#define PVP0_IPF0_PIPECTL 0xFFC1A184 /* PVP0 Pipe Control */
96#define PVP0_IPF1_PIPECTL 0xFFC1A1C4 /* PVP0 Pipe Control */
97#define PVP0_IPF0_CTL 0xFFC1A188 /* PVP0 Control */
98#define PVP0_IPF1_CTL 0xFFC1A1C8 /* PVP0 Control */
99#define PVP0_IPF0_TAG 0xFFC1A18C /* PVP0 TAG Value */
100#define PVP0_IPF1_TAG 0xFFC1A1CC /* PVP0 TAG Value */
101#define PVP0_IPF0_FCNT 0xFFC1A190 /* PVP0 Frame Count */
102#define PVP0_IPF1_FCNT 0xFFC1A1D0 /* PVP0 Frame Count */
103#define PVP0_IPF0_HCNT 0xFFC1A194 /* PVP0 Horizontal Count */
104#define PVP0_IPF1_HCNT 0xFFC1A1D4 /* PVP0 Horizontal Count */
105#define PVP0_IPF0_VCNT 0xFFC1A198 /* PVP0 Vertical Count */
106#define PVP0_IPF1_VCNT 0xFFC1A1D8 /* PVP0 Vertical Count */
107#define PVP0_IPF0_HPOS 0xFFC1A19C /* PVP0 Horizontal Position */
108#define PVP0_IPF0_VPOS 0xFFC1A1A0 /* PVP0 Vertical Position */
109#define PVP0_IPF0_TAG_STAT 0xFFC1A1A4 /* PVP0 TAG Status */
110#define PVP0_IPF1_TAG_STAT 0xFFC1A1E4 /* PVP0 TAG Status */
111#define PVP0_IPF1_CFG 0xFFC1A1C0 /* PVP0 Configuration */
112#define PVP0_CNV0_CFG 0xFFC1A200 /* PVP0 Configuration */
113#define PVP0_CNV1_CFG 0xFFC1A280 /* PVP0 Configuration */
114#define PVP0_CNV2_CFG 0xFFC1A300 /* PVP0 Configuration */
115#define PVP0_CNV3_CFG 0xFFC1A380 /* PVP0 Configuration */
116#define PVP0_CNV0_CTL 0xFFC1A204 /* PVP0 Control */
117#define PVP0_CNV1_CTL 0xFFC1A284 /* PVP0 Control */
118#define PVP0_CNV2_CTL 0xFFC1A304 /* PVP0 Control */
119#define PVP0_CNV3_CTL 0xFFC1A384 /* PVP0 Control */
120#define PVP0_CNV0_C00C01 0xFFC1A208 /* PVP0 Coefficients 0, 0 and 0, 1 */
121#define PVP0_CNV1_C00C01 0xFFC1A288 /* PVP0 Coefficients 0, 0 and 0, 1 */
122#define PVP0_CNV2_C00C01 0xFFC1A308 /* PVP0 Coefficients 0, 0 and 0, 1 */
123#define PVP0_CNV3_C00C01 0xFFC1A388 /* PVP0 Coefficients 0, 0 and 0, 1 */
124#define PVP0_CNV0_C02C03 0xFFC1A20C /* PVP0 Coefficients 0, 2 and 0, 3 */
125#define PVP0_CNV1_C02C03 0xFFC1A28C /* PVP0 Coefficients 0, 2 and 0, 3 */
126#define PVP0_CNV2_C02C03 0xFFC1A30C /* PVP0 Coefficients 0, 2 and 0, 3 */
127#define PVP0_CNV3_C02C03 0xFFC1A38C /* PVP0 Coefficients 0, 2 and 0, 3 */
128#define PVP0_CNV0_C04 0xFFC1A210 /* PVP0 Coefficient 0, 4 */
129#define PVP0_CNV1_C04 0xFFC1A290 /* PVP0 Coefficient 0, 4 */
130#define PVP0_CNV2_C04 0xFFC1A310 /* PVP0 Coefficient 0, 4 */
131#define PVP0_CNV3_C04 0xFFC1A390 /* PVP0 Coefficient 0, 4 */
132#define PVP0_CNV0_C10C11 0xFFC1A214 /* PVP0 Coefficients 1, 0 and 1, 1 */
133#define PVP0_CNV1_C10C11 0xFFC1A294 /* PVP0 Coefficients 1, 0 and 1, 1 */
134#define PVP0_CNV2_C10C11 0xFFC1A314 /* PVP0 Coefficients 1, 0 and 1, 1 */
135#define PVP0_CNV3_C10C11 0xFFC1A394 /* PVP0 Coefficients 1, 0 and 1, 1 */
136#define PVP0_CNV0_C12C13 0xFFC1A218 /* PVP0 Coefficients 1, 2 and 1, 3 */
137#define PVP0_CNV1_C12C13 0xFFC1A298 /* PVP0 Coefficients 1, 2 and 1, 3 */
138#define PVP0_CNV2_C12C13 0xFFC1A318 /* PVP0 Coefficients 1, 2 and 1, 3 */
139#define PVP0_CNV3_C12C13 0xFFC1A398 /* PVP0 Coefficients 1, 2 and 1, 3 */
140#define PVP0_CNV0_C14 0xFFC1A21C /* PVP0 Coefficient 1, 4 */
141#define PVP0_CNV1_C14 0xFFC1A29C /* PVP0 Coefficient 1, 4 */
142#define PVP0_CNV2_C14 0xFFC1A31C /* PVP0 Coefficient 1, 4 */
143#define PVP0_CNV3_C14 0xFFC1A39C /* PVP0 Coefficient 1, 4 */
144#define PVP0_CNV0_C20C21 0xFFC1A220 /* PVP0 Coefficients 2, 0 and 2, 1 */
145#define PVP0_CNV1_C20C21 0xFFC1A2A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
146#define PVP0_CNV2_C20C21 0xFFC1A320 /* PVP0 Coefficients 2, 0 and 2, 1 */
147#define PVP0_CNV3_C20C21 0xFFC1A3A0 /* PVP0 Coefficients 2, 0 and 2, 1 */
148#define PVP0_CNV0_C22C23 0xFFC1A224 /* PVP0 Coefficients 2, 2 and 2, 3 */
149#define PVP0_CNV1_C22C23 0xFFC1A2A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
150#define PVP0_CNV2_C22C23 0xFFC1A324 /* PVP0 Coefficients 2, 2 and 2, 3 */
151#define PVP0_CNV3_C22C23 0xFFC1A3A4 /* PVP0 Coefficients 2, 2 and 2, 3 */
152#define PVP0_CNV0_C24 0xFFC1A228 /* PVP0 Coefficient 2,4 */
153#define PVP0_CNV1_C24 0xFFC1A2A8 /* PVP0 Coefficient 2,4 */
154#define PVP0_CNV2_C24 0xFFC1A328 /* PVP0 Coefficient 2,4 */
155#define PVP0_CNV3_C24 0xFFC1A3A8 /* PVP0 Coefficient 2,4 */
156#define PVP0_CNV0_C30C31 0xFFC1A22C /* PVP0 Coefficients 3, 0 and 3, 1 */
157#define PVP0_CNV1_C30C31 0xFFC1A2AC /* PVP0 Coefficients 3, 0 and 3, 1 */
158#define PVP0_CNV2_C30C31 0xFFC1A32C /* PVP0 Coefficients 3, 0 and 3, 1 */
159#define PVP0_CNV3_C30C31 0xFFC1A3AC /* PVP0 Coefficients 3, 0 and 3, 1 */
160#define PVP0_CNV0_C32C33 0xFFC1A230 /* PVP0 Coefficients 3, 2 and 3, 3 */
161#define PVP0_CNV1_C32C33 0xFFC1A2B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
162#define PVP0_CNV2_C32C33 0xFFC1A330 /* PVP0 Coefficients 3, 2 and 3, 3 */
163#define PVP0_CNV3_C32C33 0xFFC1A3B0 /* PVP0 Coefficients 3, 2 and 3, 3 */
164#define PVP0_CNV0_C34 0xFFC1A234 /* PVP0 Coefficient 3, 4 */
165#define PVP0_CNV1_C34 0xFFC1A2B4 /* PVP0 Coefficient 3, 4 */
166#define PVP0_CNV2_C34 0xFFC1A334 /* PVP0 Coefficient 3, 4 */
167#define PVP0_CNV3_C34 0xFFC1A3B4 /* PVP0 Coefficient 3, 4 */
168#define PVP0_CNV0_C40C41 0xFFC1A238 /* PVP0 Coefficients 4, 0 and 4, 1 */
169#define PVP0_CNV1_C40C41 0xFFC1A2B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
170#define PVP0_CNV2_C40C41 0xFFC1A338 /* PVP0 Coefficients 4, 0 and 4, 1 */
171#define PVP0_CNV3_C40C41 0xFFC1A3B8 /* PVP0 Coefficients 4, 0 and 4, 1 */
172#define PVP0_CNV0_C42C43 0xFFC1A23C /* PVP0 Coefficients 4, 2 and 4, 3 */
173#define PVP0_CNV1_C42C43 0xFFC1A2BC /* PVP0 Coefficients 4, 2 and 4, 3 */
174#define PVP0_CNV2_C42C43 0xFFC1A33C /* PVP0 Coefficients 4, 2 and 4, 3 */
175#define PVP0_CNV3_C42C43 0xFFC1A3BC /* PVP0 Coefficients 4, 2 and 4, 3 */
176#define PVP0_CNV0_C44 0xFFC1A240 /* PVP0 Coefficient 4, 4 */
177#define PVP0_CNV1_C44 0xFFC1A2C0 /* PVP0 Coefficient 4, 4 */
178#define PVP0_CNV2_C44 0xFFC1A340 /* PVP0 Coefficient 4, 4 */
179#define PVP0_CNV3_C44 0xFFC1A3C0 /* PVP0 Coefficient 4, 4 */
180#define PVP0_CNV0_SCALE 0xFFC1A244 /* PVP0 Scaling factor */
181#define PVP0_CNV1_SCALE 0xFFC1A2C4 /* PVP0 Scaling factor */
182#define PVP0_CNV2_SCALE 0xFFC1A344 /* PVP0 Scaling factor */
183#define PVP0_CNV3_SCALE 0xFFC1A3C4 /* PVP0 Scaling factor */
184#define PVP0_THC0_CFG 0xFFC1A400 /* PVP0 Configuration */
185#define PVP0_THC1_CFG 0xFFC1A500 /* PVP0 Configuration */
186#define PVP0_THC0_CTL 0xFFC1A404 /* PVP0 Control */
187#define PVP0_THC1_CTL 0xFFC1A504 /* PVP0 Control */
188#define PVP0_THC0_HFCNT 0xFFC1A408 /* PVP0 Number of frames */
189#define PVP0_THC1_HFCNT 0xFFC1A508 /* PVP0 Number of frames */
190#define PVP0_THC0_RMAXREP 0xFFC1A40C /* PVP0 Maximum number of RLE reports */
191#define PVP0_THC1_RMAXREP 0xFFC1A50C /* PVP0 Maximum number of RLE reports */
192#define PVP0_THC0_CMINVAL 0xFFC1A410 /* PVP0 Min clip value */
193#define PVP0_THC1_CMINVAL 0xFFC1A510 /* PVP0 Min clip value */
194#define PVP0_THC0_CMINTH 0xFFC1A414 /* PVP0 Clip Min Threshold */
195#define PVP0_THC1_CMINTH 0xFFC1A514 /* PVP0 Clip Min Threshold */
196#define PVP0_THC0_CMAXTH 0xFFC1A418 /* PVP0 Clip Max Threshold */
197#define PVP0_THC1_CMAXTH 0xFFC1A518 /* PVP0 Clip Max Threshold */
198#define PVP0_THC0_CMAXVAL 0xFFC1A41C /* PVP0 Max clip value */
199#define PVP0_THC1_CMAXVAL 0xFFC1A51C /* PVP0 Max clip value */
200#define PVP0_THC0_TH0 0xFFC1A420 /* PVP0 Threshold Value */
201#define PVP0_THC1_TH0 0xFFC1A520 /* PVP0 Threshold Value */
202#define PVP0_THC0_TH1 0xFFC1A424 /* PVP0 Threshold Value */
203#define PVP0_THC1_TH1 0xFFC1A524 /* PVP0 Threshold Value */
204#define PVP0_THC0_TH2 0xFFC1A428 /* PVP0 Threshold Value */
205#define PVP0_THC1_TH2 0xFFC1A528 /* PVP0 Threshold Value */
206#define PVP0_THC0_TH3 0xFFC1A42C /* PVP0 Threshold Value */
207#define PVP0_THC1_TH3 0xFFC1A52C /* PVP0 Threshold Value */
208#define PVP0_THC0_TH4 0xFFC1A430 /* PVP0 Threshold Value */
209#define PVP0_THC1_TH4 0xFFC1A530 /* PVP0 Threshold Value */
210#define PVP0_THC0_TH5 0xFFC1A434 /* PVP0 Threshold Value */
211#define PVP0_THC1_TH5 0xFFC1A534 /* PVP0 Threshold Value */
212#define PVP0_THC0_TH6 0xFFC1A438 /* PVP0 Threshold Value */
213#define PVP0_THC1_TH6 0xFFC1A538 /* PVP0 Threshold Value */
214#define PVP0_THC0_TH7 0xFFC1A43C /* PVP0 Threshold Value */
215#define PVP0_THC1_TH7 0xFFC1A53C /* PVP0 Threshold Value */
216#define PVP0_THC0_TH8 0xFFC1A440 /* PVP0 Threshold Value */
217#define PVP0_THC1_TH8 0xFFC1A540 /* PVP0 Threshold Value */
218#define PVP0_THC0_TH9 0xFFC1A444 /* PVP0 Threshold Value */
219#define PVP0_THC1_TH9 0xFFC1A544 /* PVP0 Threshold Value */
220#define PVP0_THC0_TH10 0xFFC1A448 /* PVP0 Threshold Value */
221#define PVP0_THC1_TH10 0xFFC1A548 /* PVP0 Threshold Value */
222#define PVP0_THC0_TH11 0xFFC1A44C /* PVP0 Threshold Value */
223#define PVP0_THC1_TH11 0xFFC1A54C /* PVP0 Threshold Value */
224#define PVP0_THC0_TH12 0xFFC1A450 /* PVP0 Threshold Value */
225#define PVP0_THC1_TH12 0xFFC1A550 /* PVP0 Threshold Value */
226#define PVP0_THC0_TH13 0xFFC1A454 /* PVP0 Threshold Value */
227#define PVP0_THC1_TH13 0xFFC1A554 /* PVP0 Threshold Value */
228#define PVP0_THC0_TH14 0xFFC1A458 /* PVP0 Threshold Value */
229#define PVP0_THC1_TH14 0xFFC1A558 /* PVP0 Threshold Value */
230#define PVP0_THC0_TH15 0xFFC1A45C /* PVP0 Threshold Value */
231#define PVP0_THC1_TH15 0xFFC1A55C /* PVP0 Threshold Value */
232#define PVP0_THC0_HHPOS 0xFFC1A460 /* PVP0 Window start X-coordinate */
233#define PVP0_THC1_HHPOS 0xFFC1A560 /* PVP0 Window start X-coordinate */
234#define PVP0_THC0_HVPOS 0xFFC1A464 /* PVP0 Window start Y-coordinate */
235#define PVP0_THC1_HVPOS 0xFFC1A564 /* PVP0 Window start Y-coordinate */
236#define PVP0_THC0_HHCNT 0xFFC1A468 /* PVP0 Window width in X dimension */
237#define PVP0_THC1_HHCNT 0xFFC1A568 /* PVP0 Window width in X dimension */
238#define PVP0_THC0_HVCNT 0xFFC1A46C /* PVP0 Window width in Y dimension */
239#define PVP0_THC1_HVCNT 0xFFC1A56C /* PVP0 Window width in Y dimension */
240#define PVP0_THC0_RHPOS 0xFFC1A470 /* PVP0 Window start X-coordinate */
241#define PVP0_THC1_RHPOS 0xFFC1A570 /* PVP0 Window start X-coordinate */
242#define PVP0_THC0_RVPOS 0xFFC1A474 /* PVP0 Window start Y-coordinate */
243#define PVP0_THC1_RVPOS 0xFFC1A574 /* PVP0 Window start Y-coordinate */
244#define PVP0_THC0_RHCNT 0xFFC1A478 /* PVP0 Window width in X dimension */
245#define PVP0_THC1_RHCNT 0xFFC1A578 /* PVP0 Window width in X dimension */
246#define PVP0_THC0_RVCNT 0xFFC1A47C /* PVP0 Window width in Y dimension */
247#define PVP0_THC1_RVCNT 0xFFC1A57C /* PVP0 Window width in Y dimension */
248#define PVP0_THC0_HFCNT_STAT 0xFFC1A480 /* PVP0 Current Frame counter */
249#define PVP0_THC1_HFCNT_STAT 0xFFC1A580 /* PVP0 Current Frame counter */
250#define PVP0_THC0_HCNT0_STAT 0xFFC1A484 /* PVP0 Histogram counter value */
251#define PVP0_THC1_HCNT0_STAT 0xFFC1A584 /* PVP0 Histogram counter value */
252#define PVP0_THC0_HCNT1_STAT 0xFFC1A488 /* PVP0 Histogram counter value */
253#define PVP0_THC1_HCNT1_STAT 0xFFC1A588 /* PVP0 Histogram counter value */
254#define PVP0_THC0_HCNT2_STAT 0xFFC1A48C /* PVP0 Histogram counter value */
255#define PVP0_THC1_HCNT2_STAT 0xFFC1A58C /* PVP0 Histogram counter value */
256#define PVP0_THC0_HCNT3_STAT 0xFFC1A490 /* PVP0 Histogram counter value */
257#define PVP0_THC1_HCNT3_STAT 0xFFC1A590 /* PVP0 Histogram counter value */
258#define PVP0_THC0_HCNT4_STAT 0xFFC1A494 /* PVP0 Histogram counter value */
259#define PVP0_THC1_HCNT4_STAT 0xFFC1A594 /* PVP0 Histogram counter value */
260#define PVP0_THC0_HCNT5_STAT 0xFFC1A498 /* PVP0 Histogram counter value */
261#define PVP0_THC1_HCNT5_STAT 0xFFC1A598 /* PVP0 Histogram counter value */
262#define PVP0_THC0_HCNT6_STAT 0xFFC1A49C /* PVP0 Histogram counter value */
263#define PVP0_THC1_HCNT6_STAT 0xFFC1A59C /* PVP0 Histogram counter value */
264#define PVP0_THC0_HCNT7_STAT 0xFFC1A4A0 /* PVP0 Histogram counter value */
265#define PVP0_THC1_HCNT7_STAT 0xFFC1A5A0 /* PVP0 Histogram counter value */
266#define PVP0_THC0_HCNT8_STAT 0xFFC1A4A4 /* PVP0 Histogram counter value */
267#define PVP0_THC1_HCNT8_STAT 0xFFC1A5A4 /* PVP0 Histogram counter value */
268#define PVP0_THC0_HCNT9_STAT 0xFFC1A4A8 /* PVP0 Histogram counter value */
269#define PVP0_THC1_HCNT9_STAT 0xFFC1A5A8 /* PVP0 Histogram counter value */
270#define PVP0_THC0_HCNT10_STAT 0xFFC1A4AC /* PVP0 Histogram counter value */
271#define PVP0_THC1_HCNT10_STAT 0xFFC1A5AC /* PVP0 Histogram counter value */
272#define PVP0_THC0_HCNT11_STAT 0xFFC1A4B0 /* PVP0 Histogram counter value */
273#define PVP0_THC1_HCNT11_STAT 0xFFC1A5B0 /* PVP0 Histogram counter value */
274#define PVP0_THC0_HCNT12_STAT 0xFFC1A4B4 /* PVP0 Histogram counter value */
275#define PVP0_THC1_HCNT12_STAT 0xFFC1A5B4 /* PVP0 Histogram counter value */
276#define PVP0_THC0_HCNT13_STAT 0xFFC1A4B8 /* PVP0 Histogram counter value */
277#define PVP0_THC1_HCNT13_STAT 0xFFC1A5B8 /* PVP0 Histogram counter value */
278#define PVP0_THC0_HCNT14_STAT 0xFFC1A4BC /* PVP0 Histogram counter value */
279#define PVP0_THC1_HCNT14_STAT 0xFFC1A5BC /* PVP0 Histogram counter value */
280#define PVP0_THC0_HCNT15_STAT 0xFFC1A4C0 /* PVP0 Histogram counter value */
281#define PVP0_THC1_HCNT15_STAT 0xFFC1A5C0 /* PVP0 Histogram counter value */
282#define PVP0_THC0_RREP_STAT 0xFFC1A4C4 /* PVP0 Number of RLE Reports */
283#define PVP0_THC1_RREP_STAT 0xFFC1A5C4 /* PVP0 Number of RLE Reports */
284#define PVP0_PMA_CFG 0xFFC1A600 /* PVP0 PMA Configuration Register */
14 285
15#endif /* _DEF_BF609_H */ 286#endif /* _DEF_BF609_H */
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index c854a27cbeab..d88bd31319e6 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -77,15 +77,14 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
77 csel = bfin_read32(CGU0_DIV) & 0x1F; 77 csel = bfin_read32(CGU0_DIV) & 0x1F;
78#endif 78#endif
79 79
80 for (index = 0; (cclk >> index) >= min_cclk && csel <= 3; index++, csel++) { 80 for (index = 0; (cclk >> index) >= min_cclk && csel <= 3 && index < 3; index++, csel++) {
81 bfin_freq_table[index].frequency = cclk >> index; 81 bfin_freq_table[index].frequency = cclk >> index;
82#ifndef CONFIG_BF60x 82#ifndef CONFIG_BF60x
83 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */ 83 dpm_state_table[index].csel = csel << 4; /* Shift now into PLL_DIV bitpos */
84 dpm_state_table[index].tscale = (TIME_SCALE / (1 << csel)) - 1;
85#else 84#else
86 dpm_state_table[index].csel = csel; 85 dpm_state_table[index].csel = csel;
87 dpm_state_table[index].tscale = TIME_SCALE >> index;
88#endif 86#endif
87 dpm_state_table[index].tscale = (TIME_SCALE >> index) - 1;
89 88
90 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n", 89 pr_debug("cpufreq: freq:%d csel:0x%x tscale:%d\n",
91 bfin_freq_table[index].frequency, 90 bfin_freq_table[index].frequency,
@@ -135,7 +134,7 @@ static int bfin_target(struct cpufreq_policy *poli,
135 unsigned int plldiv; 134 unsigned int plldiv;
136#endif 135#endif
137 unsigned int index, cpu; 136 unsigned int index, cpu;
138 unsigned long flags, cclk_hz; 137 unsigned long cclk_hz;
139 struct cpufreq_freqs freqs; 138 struct cpufreq_freqs freqs;
140 static unsigned long lpj_ref; 139 static unsigned long lpj_ref;
141 static unsigned int lpj_ref_freq; 140 static unsigned int lpj_ref_freq;
@@ -166,7 +165,6 @@ static int bfin_target(struct cpufreq_policy *poli,
166 165
167 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 166 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
168 if (cpu == CPUFREQ_CPU) { 167 if (cpu == CPUFREQ_CPU) {
169 flags = hard_local_irq_save();
170#ifndef CONFIG_BF60x 168#ifndef CONFIG_BF60x
171 plldiv = (bfin_read_PLL_DIV() & SSEL) | 169 plldiv = (bfin_read_PLL_DIV() & SSEL) |
172 dpm_state_table[index].csel; 170 dpm_state_table[index].csel;
@@ -195,7 +193,6 @@ static int bfin_target(struct cpufreq_policy *poli,
195 loops_per_jiffy = cpufreq_scale(lpj_ref, 193 loops_per_jiffy = cpufreq_scale(lpj_ref,
196 lpj_ref_freq, freqs.new); 194 lpj_ref_freq, freqs.new);
197 } 195 }
198 hard_local_irq_restore(flags);
199 } 196 }
200 /* TODO: just test case for cycles clock source, remove later */ 197 /* TODO: just test case for cycles clock source, remove later */
201 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE); 198 cpufreq_notify_transition(&freqs, CPUFREQ_POSTCHANGE);
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 7ca09ec2ca53..902bebc434c6 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -1441,7 +1441,6 @@ int __init init_arch_irq(void)
1441 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | 1441 IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
1442 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; 1442 IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
1443 1443
1444 bfin_sti(bfin_irq_flags);
1445 1444
1446 /* This implicitly covers ANOMALY_05000171 1445 /* This implicitly covers ANOMALY_05000171
1447 * Boot-ROM code modifies SICA_IWRx wakeup registers 1446 * Boot-ROM code modifies SICA_IWRx wakeup registers
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index a40151306b77..bb61ae4986e4 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -146,7 +146,7 @@ static irqreturn_t ipi_handler_int1(int irq, void *dev_instance)
146 platform_clear_ipi(cpu, IRQ_SUPPLE_1); 146 platform_clear_ipi(cpu, IRQ_SUPPLE_1);
147 147
148 bfin_ipi_data = &__get_cpu_var(bfin_ipi); 148 bfin_ipi_data = &__get_cpu_var(bfin_ipi);
149 149 smp_mb();
150 while ((pending = xchg(&bfin_ipi_data->bits, 0)) != 0) { 150 while ((pending = xchg(&bfin_ipi_data->bits, 0)) != 0) {
151 msg = 0; 151 msg = 0;
152 do { 152 do {
@@ -195,7 +195,7 @@ void send_ipi(const struct cpumask *cpumask, enum ipi_message_type msg)
195 unsigned long flags; 195 unsigned long flags;
196 196
197 local_irq_save(flags); 197 local_irq_save(flags);
198 198 smp_mb();
199 for_each_cpu(cpu, cpumask) { 199 for_each_cpu(cpu, cpumask) {
200 bfin_ipi_data = &per_cpu(bfin_ipi, cpu); 200 bfin_ipi_data = &per_cpu(bfin_ipi, cpu);
201 smp_mb(); 201 smp_mb();
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-02 06:32:17 -0500