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-rw-r--r--arch/x86/pci/mrst.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/arch/x86/pci/mrst.c b/arch/x86/pci/mrst.c
index 6eb18c42a28a..0e0fabf17342 100644
--- a/arch/x86/pci/mrst.c
+++ b/arch/x86/pci/mrst.c
@@ -141,6 +141,11 @@ static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
141 */ 141 */
142static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg) 142static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
143{ 143{
144 if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
145 || devfn == PCI_DEVFN(0, 0)
146 || devfn == PCI_DEVFN(3, 0)))
147 return 1;
148
144 /* This is a workaround for A0 LNC bug where PCI status register does 149 /* This is a workaround for A0 LNC bug where PCI status register does
145 * not have new CAP bit set. can not be written by SW either. 150 * not have new CAP bit set. can not be written by SW either.
146 * 151 *
@@ -150,10 +155,7 @@ static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
150 */ 155 */
151 if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE) 156 if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
152 return 0; 157 return 0;
153 if (bus == 0 && (devfn == PCI_DEVFN(2, 0) 158
154 || devfn == PCI_DEVFN(0, 0)
155 || devfn == PCI_DEVFN(3, 0)))
156 return 1;
157 return 0; /* langwell on others */ 159 return 0; /* langwell on others */
158} 160}
159 161