diff options
| -rw-r--r-- | drivers/iio/adc/at91_adc.c | 11 |
1 files changed, 6 insertions, 5 deletions
diff --git a/drivers/iio/adc/at91_adc.c b/drivers/iio/adc/at91_adc.c index 84be63bdf038..0f16b553e063 100644 --- a/drivers/iio/adc/at91_adc.c +++ b/drivers/iio/adc/at91_adc.c | |||
| @@ -556,7 +556,7 @@ static const struct iio_info at91_adc_info = { | |||
| 556 | 556 | ||
| 557 | static int at91_adc_probe(struct platform_device *pdev) | 557 | static int at91_adc_probe(struct platform_device *pdev) |
| 558 | { | 558 | { |
| 559 | unsigned int prsc, mstrclk, ticks, adc_clk, shtim; | 559 | unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim; |
| 560 | int ret; | 560 | int ret; |
| 561 | struct iio_dev *idev; | 561 | struct iio_dev *idev; |
| 562 | struct at91_adc_state *st; | 562 | struct at91_adc_state *st; |
| @@ -649,6 +649,7 @@ static int at91_adc_probe(struct platform_device *pdev) | |||
| 649 | */ | 649 | */ |
| 650 | mstrclk = clk_get_rate(st->clk); | 650 | mstrclk = clk_get_rate(st->clk); |
| 651 | adc_clk = clk_get_rate(st->adc_clk); | 651 | adc_clk = clk_get_rate(st->adc_clk); |
| 652 | adc_clk_khz = adc_clk / 1000; | ||
| 652 | prsc = (mstrclk / (2 * adc_clk)) - 1; | 653 | prsc = (mstrclk / (2 * adc_clk)) - 1; |
| 653 | 654 | ||
| 654 | if (!st->startup_time) { | 655 | if (!st->startup_time) { |
| @@ -662,15 +663,15 @@ static int at91_adc_probe(struct platform_device *pdev) | |||
| 662 | * defined in the electrical characteristics of the board, divided by 8. | 663 | * defined in the electrical characteristics of the board, divided by 8. |
| 663 | * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock | 664 | * The formula thus is : Startup Time = (ticks + 1) * 8 / ADC Clock |
| 664 | */ | 665 | */ |
| 665 | ticks = round_up((st->startup_time * adc_clk / | 666 | ticks = round_up((st->startup_time * adc_clk_khz / |
| 666 | 1000000) - 1, 8) / 8; | 667 | 1000) - 1, 8) / 8; |
| 667 | /* | 668 | /* |
| 668 | * a minimal Sample and Hold Time is necessary for the ADC to guarantee | 669 | * a minimal Sample and Hold Time is necessary for the ADC to guarantee |
| 669 | * the best converted final value between two channels selection | 670 | * the best converted final value between two channels selection |
| 670 | * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock | 671 | * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock |
| 671 | */ | 672 | */ |
| 672 | shtim = round_up((st->sample_hold_time * adc_clk / | 673 | shtim = round_up((st->sample_hold_time * adc_clk_khz / |
| 673 | 1000000) - 1, 1); | 674 | 1000) - 1, 1); |
| 674 | 675 | ||
| 675 | reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; | 676 | reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask; |
| 676 | reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; | 677 | reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask; |
