3 files changed, 27 insertions, 5 deletions

diff --git a/arch/mips/dec/time.c b/arch/mips/dec/time.c
index 56ebc7f2bede..1914e56f0d96 100644
--- a/arch/mips/dec/time.c
+++ b/arch/mips/dec/time.c
@@ -125,12 +125,16 @@ int rtc_mips_set_mmss(unsigned long nowtime)
 
 void __init plat_time_init(void)
 {
+        int ioasic_clock = 0;
         u32 start, end;
         int i = HZ / 8;
 
         /* Set up the rate of periodic DS1287 interrupts. */
         ds1287_set_base_clock(HZ);
 
+        /* On some I/O ASIC systems we have the I/O ASIC's counter.  */
+        if (IOASIC)
+                ioasic_clock = dec_ioasic_clocksource_init() == 0;
         if (cpu_has_counter) {
                 ds1287_timer_state();
                 while (!ds1287_timer_state())
@@ -147,9 +151,21 @@ void __init plat_time_init(void)
                 mips_hpt_frequency = (end - start) * 8;
                 printk(KERN_INFO "MIPS counter frequency %dHz\n",
                         mips_hpt_frequency);
-        } else if (IOASIC)
-                /* For pre-R4k systems we use the I/O ASIC's counter.  */
-                dec_ioasic_clocksource_init();
+
+                /*
+                 * All R4k DECstations suffer from the CP0 Count erratum,
+                 * so we can't use the timer as a clock source, and a clock
+                 * event both at a time.  An accurate wall clock is more
+                 * important than a high-precision interval timer so only
+                 * use the timer as a clock source, and not a clock event
+                 * if there's no I/O ASIC counter available to serve as a
+                 * clock source.
+                 */
+                if (!ioasic_clock) {
+                        init_r4k_clocksource();
+                        mips_hpt_frequency = 0;
+                }
+        }
 
         ds1287_clockevent_init(dec_interrupt[DEC_IRQ_RTC]);
 }
diff --git a/arch/mips/include/asm/dec/ioasic.h b/arch/mips/include/asm/dec/ioasic.h
index 98badd6bf22d..be4d62a5a10e 100644
--- a/arch/mips/include/asm/dec/ioasic.h
+++ b/arch/mips/include/asm/dec/ioasic.h
@@ -33,6 +33,6 @@ static inline u32 ioasic_read(unsigned int reg)
 
 extern void init_ioasic_irqs(int base);
 
-extern void dec_ioasic_clocksource_init(void);
+extern int dec_ioasic_clocksource_init(void);
 
 #endif /* __ASM_DEC_IOASIC_H */
diff --git a/arch/mips/kernel/csrc-ioasic.c b/arch/mips/kernel/csrc-ioasic.c
index 87e88feb4a25..6cbbf6e106b9 100644
--- a/arch/mips/kernel/csrc-ioasic.c
+++ b/arch/mips/kernel/csrc-ioasic.c
@@ -37,7 +37,7 @@ static struct clocksource clocksource_dec = {
         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 };
 
-void __init dec_ioasic_clocksource_init(void)
+int __init dec_ioasic_clocksource_init(void)
 {
         unsigned int freq;
         u32 start, end;
@@ -56,8 +56,14 @@ void __init dec_ioasic_clocksource_init(void)
         end = dec_ioasic_hpt_read(&clocksource_dec);
 
         freq = (end - start) * 8;
+
+        /* An early revision of the I/O ASIC didn't have the counter.  */
+        if (!freq)
+                return -ENXIO;
+
         printk(KERN_INFO "I/O ASIC clock frequency %dHz\n", freq);
 
         clocksource_dec.rating = 200 + freq / 10000000;
         clocksource_register_hz(&clocksource_dec, freq);
+        return 0;
 }