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-rw-r--r--drivers/net/wireless/iwlwifi/iwl-3945.c36
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-4965.c64
-rw-r--r--drivers/net/wireless/iwlwifi/iwl-io.h98
-rw-r--r--drivers/net/wireless/iwlwifi/iwl3945-base.c40
-rw-r--r--drivers/net/wireless/iwlwifi/iwl4965-base.c38
5 files changed, 119 insertions, 157 deletions
diff --git a/drivers/net/wireless/iwlwifi/iwl-3945.c b/drivers/net/wireless/iwlwifi/iwl-3945.c
index 1fda41107df1..59e2fa270924 100644
--- a/drivers/net/wireless/iwlwifi/iwl-3945.c
+++ b/drivers/net/wireless/iwlwifi/iwl-3945.c
@@ -733,7 +733,7 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
733 rc = pci_read_config_dword(priv->pci_dev, 733 rc = pci_read_config_dword(priv->pci_dev,
734 PCI_POWER_SOURCE, &val); 734 PCI_POWER_SOURCE, &val);
735 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) { 735 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) {
736 iwl_set_bits_mask_restricted_reg(priv, APMG_PS_CTRL_REG, 736 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
737 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 737 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
738 ~APMG_PS_CTRL_MSK_PWR_SRC); 738 ~APMG_PS_CTRL_MSK_PWR_SRC);
739 iwl_release_restricted_access(priv); 739 iwl_release_restricted_access(priv);
@@ -744,7 +744,7 @@ static int iwl3945_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
744 } else 744 } else
745 iwl_release_restricted_access(priv); 745 iwl_release_restricted_access(priv);
746 } else { 746 } else {
747 iwl_set_bits_mask_restricted_reg(priv, APMG_PS_CTRL_REG, 747 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
748 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 748 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
749 ~APMG_PS_CTRL_MSK_PWR_SRC); 749 ~APMG_PS_CTRL_MSK_PWR_SRC);
750 750
@@ -806,18 +806,18 @@ static int iwl3945_tx_reset(struct iwl_priv *priv)
806 } 806 }
807 807
808 /* bypass mode */ 808 /* bypass mode */
809 iwl_write_restricted_reg(priv, SCD_MODE_REG, 0x2); 809 iwl_write_prph(priv, SCD_MODE_REG, 0x2);
810 810
811 /* RA 0 is active */ 811 /* RA 0 is active */
812 iwl_write_restricted_reg(priv, SCD_ARASTAT_REG, 0x01); 812 iwl_write_prph(priv, SCD_ARASTAT_REG, 0x01);
813 813
814 /* all 6 fifo are active */ 814 /* all 6 fifo are active */
815 iwl_write_restricted_reg(priv, SCD_TXFACT_REG, 0x3f); 815 iwl_write_prph(priv, SCD_TXFACT_REG, 0x3f);
816 816
817 iwl_write_restricted_reg(priv, SCD_SBYP_MODE_1_REG, 0x010000); 817 iwl_write_prph(priv, SCD_SBYP_MODE_1_REG, 0x010000);
818 iwl_write_restricted_reg(priv, SCD_SBYP_MODE_2_REG, 0x030002); 818 iwl_write_prph(priv, SCD_SBYP_MODE_2_REG, 0x030002);
819 iwl_write_restricted_reg(priv, SCD_TXF4MF_REG, 0x000004); 819 iwl_write_prph(priv, SCD_TXF4MF_REG, 0x000004);
820 iwl_write_restricted_reg(priv, SCD_TXF5MF_REG, 0x000005); 820 iwl_write_prph(priv, SCD_TXF5MF_REG, 0x000005);
821 821
822 iwl_write_restricted(priv, FH_TSSR_CBB_BASE, 822 iwl_write_restricted(priv, FH_TSSR_CBB_BASE,
823 priv->hw_setting.shared_phys); 823 priv->hw_setting.shared_phys);
@@ -902,11 +902,11 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
902 spin_unlock_irqrestore(&priv->lock, flags); 902 spin_unlock_irqrestore(&priv->lock, flags);
903 return rc; 903 return rc;
904 } 904 }
905 iwl_write_restricted_reg(priv, APMG_CLK_EN_REG, 905 iwl_write_prph(priv, APMG_CLK_EN_REG,
906 APMG_CLK_VAL_DMA_CLK_RQT | 906 APMG_CLK_VAL_DMA_CLK_RQT |
907 APMG_CLK_VAL_BSM_CLK_RQT); 907 APMG_CLK_VAL_BSM_CLK_RQT);
908 udelay(20); 908 udelay(20);
909 iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG, 909 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
910 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 910 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
911 iwl_release_restricted_access(priv); 911 iwl_release_restricted_access(priv);
912 spin_unlock_irqrestore(&priv->lock, flags); 912 spin_unlock_irqrestore(&priv->lock, flags);
@@ -1045,7 +1045,7 @@ void iwl_hw_txq_ctx_stop(struct iwl_priv *priv)
1045 } 1045 }
1046 1046
1047 /* stop SCD */ 1047 /* stop SCD */
1048 iwl_write_restricted_reg(priv, SCD_MODE_REG, 0); 1048 iwl_write_prph(priv, SCD_MODE_REG, 0);
1049 1049
1050 /* reset TFD queues */ 1050 /* reset TFD queues */
1051 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) { 1051 for (queue = TFD_QUEUE_MIN; queue < TFD_QUEUE_MAX; queue++) {
@@ -1111,7 +1111,7 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
1111 1111
1112 rc = iwl_grab_restricted_access(priv); 1112 rc = iwl_grab_restricted_access(priv);
1113 if (!rc) { 1113 if (!rc) {
1114 iwl_write_restricted_reg(priv, APMG_CLK_CTRL_REG, 1114 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
1115 APMG_CLK_VAL_BSM_CLK_RQT); 1115 APMG_CLK_VAL_BSM_CLK_RQT);
1116 1116
1117 udelay(10); 1117 udelay(10);
@@ -1119,20 +1119,20 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
1119 iwl_set_bit(priv, CSR_GP_CNTRL, 1119 iwl_set_bit(priv, CSR_GP_CNTRL,
1120 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1120 CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
1121 1121
1122 iwl_write_restricted_reg(priv, APMG_RTC_INT_MSK_REG, 0x0); 1122 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0);
1123 iwl_write_restricted_reg(priv, APMG_RTC_INT_STT_REG, 1123 iwl_write_prph(priv, APMG_RTC_INT_STT_REG,
1124 0xFFFFFFFF); 1124 0xFFFFFFFF);
1125 1125
1126 /* enable DMA */ 1126 /* enable DMA */
1127 iwl_write_restricted_reg(priv, APMG_CLK_EN_REG, 1127 iwl_write_prph(priv, APMG_CLK_EN_REG,
1128 APMG_CLK_VAL_DMA_CLK_RQT | 1128 APMG_CLK_VAL_DMA_CLK_RQT |
1129 APMG_CLK_VAL_BSM_CLK_RQT); 1129 APMG_CLK_VAL_BSM_CLK_RQT);
1130 udelay(10); 1130 udelay(10);
1131 1131
1132 iwl_set_bits_restricted_reg(priv, APMG_PS_CTRL_REG, 1132 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
1133 APMG_PS_CTRL_VAL_RESET_REQ); 1133 APMG_PS_CTRL_VAL_RESET_REQ);
1134 udelay(5); 1134 udelay(5);
1135 iwl_clear_bits_restricted_reg(priv, APMG_PS_CTRL_REG, 1135 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
1136 APMG_PS_CTRL_VAL_RESET_REQ); 1136 APMG_PS_CTRL_VAL_RESET_REQ);
1137 iwl_release_restricted_access(priv); 1137 iwl_release_restricted_access(priv);
1138 } 1138 }
diff --git a/drivers/net/wireless/iwlwifi/iwl-4965.c b/drivers/net/wireless/iwlwifi/iwl-4965.c
index a728c45b0d33..1e56dfa0cfbc 100644
--- a/drivers/net/wireless/iwlwifi/iwl-4965.c
+++ b/drivers/net/wireless/iwlwifi/iwl-4965.c
@@ -192,37 +192,35 @@ u8 iwl_hw_find_station(struct iwl_priv *priv, const u8 *addr)
192 192
193static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max) 193static int iwl4965_nic_set_pwr_src(struct iwl_priv *priv, int pwr_max)
194{ 194{
195 int rc = 0; 195 int ret;
196 unsigned long flags; 196 unsigned long flags;
197 197
198 spin_lock_irqsave(&priv->lock, flags); 198 spin_lock_irqsave(&priv->lock, flags);
199 rc = iwl_grab_restricted_access(priv); 199 ret = iwl_grab_restricted_access(priv);
200 if (rc) { 200 if (ret) {
201 spin_unlock_irqrestore(&priv->lock, flags); 201 spin_unlock_irqrestore(&priv->lock, flags);
202 return rc; 202 return ret;
203 } 203 }
204 204
205 if (!pwr_max) { 205 if (!pwr_max) {
206 u32 val; 206 u32 val;
207 207
208 rc = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE, 208 ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
209 &val); 209 &val);
210 210
211 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT) 211 if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
212 iwl_set_bits_mask_restricted_reg( 212 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
213 priv, APMG_PS_CTRL_REG,
214 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 213 APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
215 ~APMG_PS_CTRL_MSK_PWR_SRC); 214 ~APMG_PS_CTRL_MSK_PWR_SRC);
216 } else 215 } else
217 iwl_set_bits_mask_restricted_reg( 216 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
218 priv, APMG_PS_CTRL_REG,
219 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 217 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
220 ~APMG_PS_CTRL_MSK_PWR_SRC); 218 ~APMG_PS_CTRL_MSK_PWR_SRC);
221 219
222 iwl_release_restricted_access(priv); 220 iwl_release_restricted_access(priv);
223 spin_unlock_irqrestore(&priv->lock, flags); 221 spin_unlock_irqrestore(&priv->lock, flags);
224 222
225 return rc; 223 return ret;
226} 224}
227 225
228static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) 226static int iwl4965_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
@@ -384,7 +382,7 @@ static int iwl4965_txq_ctx_reset(struct iwl_priv *priv)
384 goto error_reset; 382 goto error_reset;
385 } 383 }
386 384
387 iwl_write_restricted_reg(priv, SCD_TXFACT, 0); 385 iwl_write_prph(priv, SCD_TXFACT, 0);
388 iwl_release_restricted_access(priv); 386 iwl_release_restricted_access(priv);
389 spin_unlock_irqrestore(&priv->lock, flags); 387 spin_unlock_irqrestore(&priv->lock, flags);
390 388
@@ -449,16 +447,16 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
449 return rc; 447 return rc;
450 } 448 }
451 449
452 iwl_read_restricted_reg(priv, APMG_CLK_CTRL_REG); 450 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
453 451
454 iwl_write_restricted_reg(priv, APMG_CLK_CTRL_REG, 452 iwl_write_prph(priv, APMG_CLK_CTRL_REG,
455 APMG_CLK_VAL_DMA_CLK_RQT | 453 APMG_CLK_VAL_DMA_CLK_RQT |
456 APMG_CLK_VAL_BSM_CLK_RQT); 454 APMG_CLK_VAL_BSM_CLK_RQT);
457 iwl_read_restricted_reg(priv, APMG_CLK_CTRL_REG); 455 iwl_read_prph(priv, APMG_CLK_CTRL_REG);
458 456
459 udelay(20); 457 udelay(20);
460 458
461 iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG, 459 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
462 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 460 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
463 461
464 iwl_release_restricted_access(priv); 462 iwl_release_restricted_access(priv);
@@ -514,11 +512,11 @@ int iwl_hw_nic_init(struct iwl_priv *priv)
514 return rc; 512 return rc;
515 } 513 }
516 514
517 iwl_read_restricted_reg(priv, APMG_PS_CTRL_REG); 515 iwl_read_prph(priv, APMG_PS_CTRL_REG);
518 iwl_set_bits_restricted_reg(priv, APMG_PS_CTRL_REG, 516 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG,
519 APMG_PS_CTRL_VAL_RESET_REQ); 517 APMG_PS_CTRL_VAL_RESET_REQ);
520 udelay(5); 518 udelay(5);
521 iwl_clear_bits_restricted_reg(priv, APMG_PS_CTRL_REG, 519 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG,
522 APMG_PS_CTRL_VAL_RESET_REQ); 520 APMG_PS_CTRL_VAL_RESET_REQ);
523 521
524 iwl_release_restricted_access(priv); 522 iwl_release_restricted_access(priv);
@@ -645,13 +643,13 @@ int iwl_hw_nic_reset(struct iwl_priv *priv)
645 643
646 rc = iwl_grab_restricted_access(priv); 644 rc = iwl_grab_restricted_access(priv);
647 if (!rc) { 645 if (!rc) {
648 iwl_write_restricted_reg(priv, APMG_CLK_EN_REG, 646 iwl_write_prph(priv, APMG_CLK_EN_REG,
649 APMG_CLK_VAL_DMA_CLK_RQT | 647 APMG_CLK_VAL_DMA_CLK_RQT |
650 APMG_CLK_VAL_BSM_CLK_RQT); 648 APMG_CLK_VAL_BSM_CLK_RQT);
651 649
652 udelay(10); 650 udelay(10);
653 651
654 iwl_set_bits_restricted_reg(priv, APMG_PCIDEV_STT_REG, 652 iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
655 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 653 APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
656 654
657 iwl_release_restricted_access(priv); 655 iwl_release_restricted_access(priv);
@@ -1585,7 +1583,7 @@ static void iwl4965_set_wr_ptrs(struct iwl_priv *priv, int txq_id, u32 index)
1585{ 1583{
1586 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 1584 iwl_write_restricted(priv, HBUS_TARG_WRPTR,
1587 (index & 0xff) | (txq_id << 8)); 1585 (index & 0xff) | (txq_id << 8));
1588 iwl_write_restricted_reg(priv, SCD_QUEUE_RDPTR(txq_id), index); 1586 iwl_write_prph(priv, SCD_QUEUE_RDPTR(txq_id), index);
1589} 1587}
1590 1588
1591/* 1589/*
@@ -1598,7 +1596,7 @@ static void iwl4965_tx_queue_set_status(struct iwl_priv *priv,
1598 int txq_id = txq->q.id; 1596 int txq_id = txq->q.id;
1599 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0; 1597 int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
1600 1598
1601 iwl_write_restricted_reg(priv, SCD_QUEUE_STATUS_BITS(txq_id), 1599 iwl_write_prph(priv, SCD_QUEUE_STATUS_BITS(txq_id),
1602 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) | 1600 (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
1603 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) | 1601 (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
1604 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) | 1602 (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
@@ -1656,7 +1654,7 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1656 return rc; 1654 return rc;
1657 } 1655 }
1658 1656
1659 priv->scd_base_addr = iwl_read_restricted_reg(priv, SCD_SRAM_BASE_ADDR); 1657 priv->scd_base_addr = iwl_read_prph(priv, SCD_SRAM_BASE_ADDR);
1660 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET; 1658 a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
1661 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4) 1659 for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
1662 iwl_write_restricted_mem(priv, a, 0); 1660 iwl_write_restricted_mem(priv, a, 0);
@@ -1665,14 +1663,14 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1665 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4) 1663 for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
1666 iwl_write_restricted_mem(priv, a, 0); 1664 iwl_write_restricted_mem(priv, a, 0);
1667 1665
1668 iwl_write_restricted_reg(priv, SCD_DRAM_BASE_ADDR, 1666 iwl_write_prph(priv, SCD_DRAM_BASE_ADDR,
1669 (priv->hw_setting.shared_phys + 1667 (priv->hw_setting.shared_phys +
1670 offsetof(struct iwl_shared, queues_byte_cnt_tbls)) >> 10); 1668 offsetof(struct iwl_shared, queues_byte_cnt_tbls)) >> 10);
1671 iwl_write_restricted_reg(priv, SCD_QUEUECHAIN_SEL, 0); 1669 iwl_write_prph(priv, SCD_QUEUECHAIN_SEL, 0);
1672 1670
1673 /* initiate the queues */ 1671 /* initiate the queues */
1674 for (i = 0; i < priv->hw_setting.max_txq_num; i++) { 1672 for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
1675 iwl_write_restricted_reg(priv, SCD_QUEUE_RDPTR(i), 0); 1673 iwl_write_prph(priv, SCD_QUEUE_RDPTR(i), 0);
1676 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8)); 1674 iwl_write_restricted(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
1677 iwl_write_restricted_mem(priv, priv->scd_base_addr + 1675 iwl_write_restricted_mem(priv, priv->scd_base_addr +
1678 SCD_CONTEXT_QUEUE_OFFSET(i), 1676 SCD_CONTEXT_QUEUE_OFFSET(i),
@@ -1687,10 +1685,10 @@ int iwl4965_alive_notify(struct iwl_priv *priv)
1687 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 1685 SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
1688 1686
1689 } 1687 }
1690 iwl_write_restricted_reg(priv, SCD_INTERRUPT_MASK, 1688 iwl_write_prph(priv, SCD_INTERRUPT_MASK,
1691 (1 << priv->hw_setting.max_txq_num) - 1); 1689 (1 << priv->hw_setting.max_txq_num) - 1);
1692 1690
1693 iwl_write_restricted_reg(priv, SCD_TXFACT, 1691 iwl_write_prph(priv, SCD_TXFACT,
1694 SCD_TXFACT_REG_TXFIFO_MASK(0, 7)); 1692 SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
1695 1693
1696 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0); 1694 iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
@@ -4140,7 +4138,7 @@ static void iwl4965_rx_reply_compressed_ba(struct iwl_priv *priv,
4140 4138
4141static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id) 4139static void iwl4965_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
4142{ 4140{
4143 iwl_write_restricted_reg(priv, 4141 iwl_write_prph(priv,
4144 SCD_QUEUE_STATUS_BITS(txq_id), 4142 SCD_QUEUE_STATUS_BITS(txq_id),
4145 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)| 4143 (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
4146 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 4144 (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
@@ -4201,7 +4199,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4201 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id); 4199 iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
4202 4200
4203 4201
4204 iwl_set_bits_restricted_reg(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id)); 4202 iwl_set_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1<<txq_id));
4205 4203
4206 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 4204 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4207 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 4205 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
@@ -4219,7 +4217,7 @@ static int iwl4965_tx_queue_agg_enable(struct iwl_priv *priv, int txq_id,
4219 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) 4217 (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
4220 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 4218 & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
4221 4219
4222 iwl_set_bits_restricted_reg(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); 4220 iwl_set_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
4223 4221
4224 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1); 4222 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
4225 4223
@@ -4253,14 +4251,14 @@ static int iwl4965_tx_queue_agg_disable(struct iwl_priv *priv, u16 txq_id,
4253 4251
4254 iwl4965_tx_queue_stop_scheduler(priv, txq_id); 4252 iwl4965_tx_queue_stop_scheduler(priv, txq_id);
4255 4253
4256 iwl_clear_bits_restricted_reg(priv, SCD_QUEUECHAIN_SEL, (1 << txq_id)); 4254 iwl_clear_bits_prph(priv, SCD_QUEUECHAIN_SEL, (1 << txq_id));
4257 4255
4258 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 4256 priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
4259 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 4257 priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
4260 /* supposes that ssn_idx is valid (!= 0xFFF) */ 4258 /* supposes that ssn_idx is valid (!= 0xFFF) */
4261 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx); 4259 iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
4262 4260
4263 iwl_clear_bits_restricted_reg(priv, SCD_INTERRUPT_MASK, (1 << txq_id)); 4261 iwl_clear_bits_prph(priv, SCD_INTERRUPT_MASK, (1 << txq_id));
4264 iwl4965_txq_ctx_deactivate(priv, txq_id); 4262 iwl4965_txq_ctx_deactivate(priv, txq_id);
4265 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0); 4263 iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
4266 4264
diff --git a/drivers/net/wireless/iwlwifi/iwl-io.h b/drivers/net/wireless/iwlwifi/iwl-io.h
index 8a8b96fcf48d..b78afed9c799 100644
--- a/drivers/net/wireless/iwlwifi/iwl-io.h
+++ b/drivers/net/wireless/iwlwifi/iwl-io.h
@@ -330,27 +330,26 @@ static inline int __iwl_poll_restricted_bit(const char *f, u32 l,
330#define iwl_poll_restricted_bit _iwl_poll_restricted_bit 330#define iwl_poll_restricted_bit _iwl_poll_restricted_bit
331#endif 331#endif
332 332
333static inline u32 _iwl_read_restricted_reg(struct iwl_priv *priv, u32 reg) 333static inline u32 _iwl_read_prph(struct iwl_priv *priv, u32 reg)
334{ 334{
335 _iwl_write_restricted(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24)); 335 _iwl_write_restricted(priv, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
336 return _iwl_read_restricted(priv, HBUS_TARG_PRPH_RDAT); 336 return _iwl_read_restricted(priv, HBUS_TARG_PRPH_RDAT);
337} 337}
338#ifdef CONFIG_IWLWIFI_DEBUG 338#ifdef CONFIG_IWLWIFI_DEBUG
339static inline u32 __iwl_read_restricted_reg(u32 line, 339static inline u32 __iwl_read_prph(u32 line, struct iwl_priv *priv, u32 reg)
340 struct iwl_priv *priv, u32 reg)
341{ 340{
342 if (!atomic_read(&priv->restrict_refcnt)) 341 if (!atomic_read(&priv->restrict_refcnt))
343 IWL_ERROR("Unrestricted access from line %d\n", line); 342 IWL_ERROR("Unrestricted access from line %d\n", line);
344 return _iwl_read_restricted_reg(priv, reg); 343 return _iwl_read_prph(priv, reg);
345} 344}
346 345
347#define iwl_read_restricted_reg(priv, reg) \ 346#define iwl_read_prph(priv, reg) \
348 __iwl_read_restricted_reg(__LINE__, priv, reg) 347 __iwl_read_prph(__LINE__, priv, reg)
349#else 348#else
350#define iwl_read_restricted_reg _iwl_read_restricted_reg 349#define iwl_read_prph _iwl_read_prph
351#endif 350#endif
352 351
353static inline void _iwl_write_restricted_reg(struct iwl_priv *priv, 352static inline void _iwl_write_prph(struct iwl_priv *priv,
354 u32 addr, u32 val) 353 u32 addr, u32 val)
355{ 354{
356 _iwl_write_restricted(priv, HBUS_TARG_PRPH_WADDR, 355 _iwl_write_restricted(priv, HBUS_TARG_PRPH_WADDR,
@@ -358,61 +357,58 @@ static inline void _iwl_write_restricted_reg(struct iwl_priv *priv,
358 _iwl_write_restricted(priv, HBUS_TARG_PRPH_WDAT, val); 357 _iwl_write_restricted(priv, HBUS_TARG_PRPH_WDAT, val);
359} 358}
360#ifdef CONFIG_IWLWIFI_DEBUG 359#ifdef CONFIG_IWLWIFI_DEBUG
361static inline void __iwl_write_restricted_reg(u32 line, 360static inline void __iwl_write_prph(u32 line, struct iwl_priv *priv,
362 struct iwl_priv *priv,
363 u32 addr, u32 val) 361 u32 addr, u32 val)
364{ 362{
365 if (!atomic_read(&priv->restrict_refcnt)) 363 if (!atomic_read(&priv->restrict_refcnt))
366 IWL_ERROR("Unrestricted access from line %d\n", line); 364 IWL_ERROR("Unrestricted access from line %d\n", line);
367 _iwl_write_restricted_reg(priv, addr, val); 365 _iwl_write_prph(priv, addr, val);
368} 366}
369 367
370#define iwl_write_restricted_reg(priv, addr, val) \ 368#define iwl_write_prph(priv, addr, val) \
371 __iwl_write_restricted_reg(__LINE__, priv, addr, val); 369 __iwl_write_prph(__LINE__, priv, addr, val);
372#else 370#else
373#define iwl_write_restricted_reg _iwl_write_restricted_reg 371#define iwl_write_prph _iwl_write_prph
374#endif 372#endif
375 373
376#define _iwl_set_bits_restricted_reg(priv, reg, mask) \ 374#define _iwl_set_bits_prph(priv, reg, mask) \
377 _iwl_write_restricted_reg(priv, reg, \ 375 _iwl_write_prph(priv, reg, (_iwl_read_prph(priv, reg) | mask))
378 (_iwl_read_restricted_reg(priv, reg) | mask))
379#ifdef CONFIG_IWLWIFI_DEBUG 376#ifdef CONFIG_IWLWIFI_DEBUG
380static inline void __iwl_set_bits_restricted_reg(u32 line, struct iwl_priv 377static inline void __iwl_set_bits_prph(u32 line, struct iwl_priv *priv,
381 *priv, u32 reg, u32 mask) 378 u32 reg, u32 mask)
382{ 379{
383 if (!atomic_read(&priv->restrict_refcnt)) 380 if (!atomic_read(&priv->restrict_refcnt))
384 IWL_ERROR("Unrestricted access from line %d\n", line); 381 IWL_ERROR("Unrestricted access from line %d\n", line);
385 _iwl_set_bits_restricted_reg(priv, reg, mask); 382 _iwl_set_bits_prph(priv, reg, mask);
386} 383}
387#define iwl_set_bits_restricted_reg(priv, reg, mask) \ 384#define iwl_set_bits_prph(priv, reg, mask) \
388 __iwl_set_bits_restricted_reg(__LINE__, priv, reg, mask) 385 __iwl_set_bits_prph(__LINE__, priv, reg, mask)
389#else 386#else
390#define iwl_set_bits_restricted_reg _iwl_set_bits_restricted_reg 387#define iwl_set_bits_prph _iwl_set_bits_prph
391#endif 388#endif
392 389
393#define _iwl_set_bits_mask_restricted_reg(priv, reg, bits, mask) \ 390#define _iwl_set_bits_mask_prph(priv, reg, bits, mask) \
394 _iwl_write_restricted_reg( \ 391 _iwl_write_prph(priv, reg, ((_iwl_read_prph(priv, reg) & mask) | bits))
395 priv, reg, ((_iwl_read_restricted_reg(priv, reg) & mask) | bits)) 392
396#ifdef CONFIG_IWLWIFI_DEBUG 393#ifdef CONFIG_IWLWIFI_DEBUG
397static inline void __iwl_set_bits_mask_restricted_reg(u32 line, 394static inline void __iwl_set_bits_mask_prph(u32 line,
398 struct iwl_priv *priv, u32 reg, u32 bits, u32 mask) 395 struct iwl_priv *priv, u32 reg, u32 bits, u32 mask)
399{ 396{
400 if (!atomic_read(&priv->restrict_refcnt)) 397 if (!atomic_read(&priv->restrict_refcnt))
401 IWL_ERROR("Unrestricted access from line %d\n", line); 398 IWL_ERROR("Unrestricted access from line %d\n", line);
402 _iwl_set_bits_mask_restricted_reg(priv, reg, bits, mask); 399 _iwl_set_bits_mask_prph(priv, reg, bits, mask);
403} 400}
404 401#define iwl_set_bits_mask_prph(priv, reg, bits, mask) \
405#define iwl_set_bits_mask_restricted_reg(priv, reg, bits, mask) \ 402 __iwl_set_bits_mask_prph(__LINE__, priv, reg, bits, mask)
406 __iwl_set_bits_mask_restricted_reg(__LINE__, priv, reg, bits, mask)
407#else 403#else
408#define iwl_set_bits_mask_restricted_reg _iwl_set_bits_mask_restricted_reg 404#define iwl_set_bits_mask_prph _iwl_set_bits_mask_prph
409#endif 405#endif
410 406
411static inline void iwl_clear_bits_restricted_reg(struct iwl_priv 407static inline void iwl_clear_bits_prph(struct iwl_priv
412 *priv, u32 reg, u32 mask) 408 *priv, u32 reg, u32 mask)
413{ 409{
414 u32 val = _iwl_read_restricted_reg(priv, reg); 410 u32 val = _iwl_read_prph(priv, reg);
415 _iwl_write_restricted_reg(priv, reg, (val & ~mask)); 411 _iwl_write_prph(priv, reg, (val & ~mask));
416} 412}
417 413
418static inline u32 iwl_read_restricted_mem(struct iwl_priv *priv, u32 addr) 414static inline u32 iwl_read_restricted_mem(struct iwl_priv *priv, u32 addr)
@@ -435,36 +431,4 @@ static inline void iwl_write_restricted_mems(struct iwl_priv *priv, u32 addr,
435 for (; 0 < len; len -= sizeof(u32), values++) 431 for (; 0 < len; len -= sizeof(u32), values++)
436 iwl_write_restricted(priv, HBUS_TARG_MEM_WDAT, *values); 432 iwl_write_restricted(priv, HBUS_TARG_MEM_WDAT, *values);
437} 433}
438
439static inline void iwl_write_restricted_regs(struct iwl_priv *priv, u32 reg,
440 u32 len, u8 *values)
441{
442 u32 reg_offset = reg;
443 u32 aligment = reg & 0x3;
444
445 /* write any non-dword-aligned stuff at the beginning */
446 if (len < sizeof(u32)) {
447 if ((aligment + len) <= sizeof(u32)) {
448 u8 size;
449 u32 value = 0;
450 size = len - 1;
451 memcpy(&value, values, len);
452 reg_offset = (reg_offset & 0x0000FFFF);
453
454 _iwl_write_restricted(priv,
455 HBUS_TARG_PRPH_WADDR,
456 (reg_offset | (size << 24)));
457 _iwl_write_restricted(priv, HBUS_TARG_PRPH_WDAT,
458 value);
459 }
460
461 return;
462 }
463
464 /* now write all the dword-aligned stuff */
465 for (; reg_offset < (reg + len);
466 reg_offset += sizeof(u32), values += sizeof(u32))
467 _iwl_write_restricted_reg(priv, reg_offset, *((u32 *) values));
468}
469
470#endif 434#endif
diff --git a/drivers/net/wireless/iwlwifi/iwl3945-base.c b/drivers/net/wireless/iwlwifi/iwl3945-base.c
index c6606e1af51d..676023a0a76f 100644
--- a/drivers/net/wireless/iwlwifi/iwl3945-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl3945-base.c
@@ -5623,11 +5623,11 @@ static int iwl_verify_bsm(struct iwl_priv *priv)
5623 IWL_DEBUG_INFO("Begin verify bsm\n"); 5623 IWL_DEBUG_INFO("Begin verify bsm\n");
5624 5624
5625 /* verify BSM SRAM contents */ 5625 /* verify BSM SRAM contents */
5626 val = iwl_read_restricted_reg(priv, BSM_WR_DWCOUNT_REG); 5626 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
5627 for (reg = BSM_SRAM_LOWER_BOUND; 5627 for (reg = BSM_SRAM_LOWER_BOUND;
5628 reg < BSM_SRAM_LOWER_BOUND + len; 5628 reg < BSM_SRAM_LOWER_BOUND + len;
5629 reg += sizeof(u32), image ++) { 5629 reg += sizeof(u32), image ++) {
5630 val = iwl_read_restricted_reg(priv, reg); 5630 val = iwl_read_prph(priv, reg);
5631 if (val != le32_to_cpu(*image)) { 5631 if (val != le32_to_cpu(*image)) {
5632 IWL_ERROR("BSM uCode verification failed at " 5632 IWL_ERROR("BSM uCode verification failed at "
5633 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", 5633 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
@@ -5708,16 +5708,16 @@ static int iwl_load_bsm(struct iwl_priv *priv)
5708 if (rc) 5708 if (rc)
5709 return rc; 5709 return rc;
5710 5710
5711 iwl_write_restricted_reg(priv, BSM_DRAM_INST_PTR_REG, pinst); 5711 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
5712 iwl_write_restricted_reg(priv, BSM_DRAM_DATA_PTR_REG, pdata); 5712 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
5713 iwl_write_restricted_reg(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); 5713 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
5714 iwl_write_restricted_reg(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); 5714 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
5715 5715
5716 /* Fill BSM memory with bootstrap instructions */ 5716 /* Fill BSM memory with bootstrap instructions */
5717 for (reg_offset = BSM_SRAM_LOWER_BOUND; 5717 for (reg_offset = BSM_SRAM_LOWER_BOUND;
5718 reg_offset < BSM_SRAM_LOWER_BOUND + len; 5718 reg_offset < BSM_SRAM_LOWER_BOUND + len;
5719 reg_offset += sizeof(u32), image++) 5719 reg_offset += sizeof(u32), image++)
5720 _iwl_write_restricted_reg(priv, reg_offset, 5720 _iwl_write_prph(priv, reg_offset,
5721 le32_to_cpu(*image)); 5721 le32_to_cpu(*image));
5722 5722
5723 rc = iwl_verify_bsm(priv); 5723 rc = iwl_verify_bsm(priv);
@@ -5727,19 +5727,19 @@ static int iwl_load_bsm(struct iwl_priv *priv)
5727 } 5727 }
5728 5728
5729 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ 5729 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
5730 iwl_write_restricted_reg(priv, BSM_WR_MEM_SRC_REG, 0x0); 5730 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
5731 iwl_write_restricted_reg(priv, BSM_WR_MEM_DST_REG, 5731 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
5732 RTC_INST_LOWER_BOUND); 5732 RTC_INST_LOWER_BOUND);
5733 iwl_write_restricted_reg(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); 5733 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
5734 5734
5735 /* Load bootstrap code into instruction SRAM now, 5735 /* Load bootstrap code into instruction SRAM now,
5736 * to prepare to load "initialize" uCode */ 5736 * to prepare to load "initialize" uCode */
5737 iwl_write_restricted_reg(priv, BSM_WR_CTRL_REG, 5737 iwl_write_prph(priv, BSM_WR_CTRL_REG,
5738 BSM_WR_CTRL_REG_BIT_START); 5738 BSM_WR_CTRL_REG_BIT_START);
5739 5739
5740 /* Wait for load of bootstrap uCode to finish */ 5740 /* Wait for load of bootstrap uCode to finish */
5741 for (i = 0; i < 100; i++) { 5741 for (i = 0; i < 100; i++) {
5742 done = iwl_read_restricted_reg(priv, BSM_WR_CTRL_REG); 5742 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
5743 if (!(done & BSM_WR_CTRL_REG_BIT_START)) 5743 if (!(done & BSM_WR_CTRL_REG_BIT_START))
5744 break; 5744 break;
5745 udelay(10); 5745 udelay(10);
@@ -5753,7 +5753,7 @@ static int iwl_load_bsm(struct iwl_priv *priv)
5753 5753
5754 /* Enable future boot loads whenever power management unit triggers it 5754 /* Enable future boot loads whenever power management unit triggers it
5755 * (e.g. when powering back up after power-save shutdown) */ 5755 * (e.g. when powering back up after power-save shutdown) */
5756 iwl_write_restricted_reg(priv, BSM_WR_CTRL_REG, 5756 iwl_write_prph(priv, BSM_WR_CTRL_REG,
5757 BSM_WR_CTRL_REG_BIT_START_EN); 5757 BSM_WR_CTRL_REG_BIT_START_EN);
5758 5758
5759 iwl_release_restricted_access(priv); 5759 iwl_release_restricted_access(priv);
@@ -6004,14 +6004,14 @@ static int iwl_set_ucode_ptrs(struct iwl_priv *priv)
6004 } 6004 }
6005 6005
6006 /* Tell bootstrap uCode where to find image to load */ 6006 /* Tell bootstrap uCode where to find image to load */
6007 iwl_write_restricted_reg(priv, BSM_DRAM_INST_PTR_REG, pinst); 6007 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
6008 iwl_write_restricted_reg(priv, BSM_DRAM_DATA_PTR_REG, pdata); 6008 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
6009 iwl_write_restricted_reg(priv, BSM_DRAM_DATA_BYTECOUNT_REG, 6009 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
6010 priv->ucode_data.len); 6010 priv->ucode_data.len);
6011 6011
6012 /* Inst bytecount must be last to set up, bit 31 signals uCode 6012 /* Inst bytecount must be last to set up, bit 31 signals uCode
6013 * that all new ptr/size info is in place */ 6013 * that all new ptr/size info is in place */
6014 iwl_write_restricted_reg(priv, BSM_DRAM_INST_BYTECOUNT_REG, 6014 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
6015 priv->ucode_code.len | BSM_DRAM_INST_LOAD); 6015 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
6016 6016
6017 iwl_release_restricted_access(priv); 6017 iwl_release_restricted_access(priv);
@@ -6109,7 +6109,7 @@ static void iwl_alive_start(struct iwl_priv *priv)
6109 return; 6109 return;
6110 } 6110 }
6111 6111
6112 rfkill = iwl_read_restricted_reg(priv, APMG_RFKILL_REG); 6112 rfkill = iwl_read_prph(priv, APMG_RFKILL_REG);
6113 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill); 6113 IWL_DEBUG_INFO("RFKILL status: 0x%x\n", rfkill);
6114 iwl_release_restricted_access(priv); 6114 iwl_release_restricted_access(priv);
6115 6115
@@ -6274,7 +6274,7 @@ static void __iwl_down(struct iwl_priv *priv)
6274 6274
6275 spin_lock_irqsave(&priv->lock, flags); 6275 spin_lock_irqsave(&priv->lock, flags);
6276 if (!iwl_grab_restricted_access(priv)) { 6276 if (!iwl_grab_restricted_access(priv)) {
6277 iwl_write_restricted_reg(priv, APMG_CLK_DIS_REG, 6277 iwl_write_prph(priv, APMG_CLK_DIS_REG,
6278 APMG_CLK_VAL_DMA_CLK_RQT); 6278 APMG_CLK_VAL_DMA_CLK_RQT);
6279 iwl_release_restricted_access(priv); 6279 iwl_release_restricted_access(priv);
6280 } 6280 }
@@ -8674,7 +8674,7 @@ static void iwl_resume(struct iwl_priv *priv)
8674 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 8674 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
8675 8675
8676 if (!iwl_grab_restricted_access(priv)) { 8676 if (!iwl_grab_restricted_access(priv)) {
8677 iwl_write_restricted_reg(priv, APMG_CLK_DIS_REG, 8677 iwl_write_prph(priv, APMG_CLK_DIS_REG,
8678 APMG_CLK_VAL_DMA_CLK_RQT); 8678 APMG_CLK_VAL_DMA_CLK_RQT);
8679 iwl_release_restricted_access(priv); 8679 iwl_release_restricted_access(priv);
8680 } 8680 }
diff --git a/drivers/net/wireless/iwlwifi/iwl4965-base.c b/drivers/net/wireless/iwlwifi/iwl4965-base.c
index 60174202ca1e..e74f71fdaf92 100644
--- a/drivers/net/wireless/iwlwifi/iwl4965-base.c
+++ b/drivers/net/wireless/iwlwifi/iwl4965-base.c
@@ -6002,11 +6002,11 @@ static int iwl_verify_bsm(struct iwl_priv *priv)
6002 IWL_DEBUG_INFO("Begin verify bsm\n"); 6002 IWL_DEBUG_INFO("Begin verify bsm\n");
6003 6003
6004 /* verify BSM SRAM contents */ 6004 /* verify BSM SRAM contents */
6005 val = iwl_read_restricted_reg(priv, BSM_WR_DWCOUNT_REG); 6005 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG);
6006 for (reg = BSM_SRAM_LOWER_BOUND; 6006 for (reg = BSM_SRAM_LOWER_BOUND;
6007 reg < BSM_SRAM_LOWER_BOUND + len; 6007 reg < BSM_SRAM_LOWER_BOUND + len;
6008 reg += sizeof(u32), image ++) { 6008 reg += sizeof(u32), image ++) {
6009 val = iwl_read_restricted_reg(priv, reg); 6009 val = iwl_read_prph(priv, reg);
6010 if (val != le32_to_cpu(*image)) { 6010 if (val != le32_to_cpu(*image)) {
6011 IWL_ERROR("BSM uCode verification failed at " 6011 IWL_ERROR("BSM uCode verification failed at "
6012 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", 6012 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n",
@@ -6087,16 +6087,16 @@ static int iwl_load_bsm(struct iwl_priv *priv)
6087 if (rc) 6087 if (rc)
6088 return rc; 6088 return rc;
6089 6089
6090 iwl_write_restricted_reg(priv, BSM_DRAM_INST_PTR_REG, pinst); 6090 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
6091 iwl_write_restricted_reg(priv, BSM_DRAM_DATA_PTR_REG, pdata); 6091 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
6092 iwl_write_restricted_reg(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); 6092 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len);
6093 iwl_write_restricted_reg(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); 6093 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len);
6094 6094
6095 /* Fill BSM memory with bootstrap instructions */ 6095 /* Fill BSM memory with bootstrap instructions */
6096 for (reg_offset = BSM_SRAM_LOWER_BOUND; 6096 for (reg_offset = BSM_SRAM_LOWER_BOUND;
6097 reg_offset < BSM_SRAM_LOWER_BOUND + len; 6097 reg_offset < BSM_SRAM_LOWER_BOUND + len;
6098 reg_offset += sizeof(u32), image++) 6098 reg_offset += sizeof(u32), image++)
6099 _iwl_write_restricted_reg(priv, reg_offset, 6099 _iwl_write_prph(priv, reg_offset,
6100 le32_to_cpu(*image)); 6100 le32_to_cpu(*image));
6101 6101
6102 rc = iwl_verify_bsm(priv); 6102 rc = iwl_verify_bsm(priv);
@@ -6106,19 +6106,19 @@ static int iwl_load_bsm(struct iwl_priv *priv)
6106 } 6106 }
6107 6107
6108 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ 6108 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */
6109 iwl_write_restricted_reg(priv, BSM_WR_MEM_SRC_REG, 0x0); 6109 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0);
6110 iwl_write_restricted_reg(priv, BSM_WR_MEM_DST_REG, 6110 iwl_write_prph(priv, BSM_WR_MEM_DST_REG,
6111 RTC_INST_LOWER_BOUND); 6111 RTC_INST_LOWER_BOUND);
6112 iwl_write_restricted_reg(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); 6112 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32));
6113 6113
6114 /* Load bootstrap code into instruction SRAM now, 6114 /* Load bootstrap code into instruction SRAM now,
6115 * to prepare to load "initialize" uCode */ 6115 * to prepare to load "initialize" uCode */
6116 iwl_write_restricted_reg(priv, BSM_WR_CTRL_REG, 6116 iwl_write_prph(priv, BSM_WR_CTRL_REG,
6117 BSM_WR_CTRL_REG_BIT_START); 6117 BSM_WR_CTRL_REG_BIT_START);
6118 6118
6119 /* Wait for load of bootstrap uCode to finish */ 6119 /* Wait for load of bootstrap uCode to finish */
6120 for (i = 0; i < 100; i++) { 6120 for (i = 0; i < 100; i++) {
6121 done = iwl_read_restricted_reg(priv, BSM_WR_CTRL_REG); 6121 done = iwl_read_prph(priv, BSM_WR_CTRL_REG);
6122 if (!(done & BSM_WR_CTRL_REG_BIT_START)) 6122 if (!(done & BSM_WR_CTRL_REG_BIT_START))
6123 break; 6123 break;
6124 udelay(10); 6124 udelay(10);
@@ -6132,7 +6132,7 @@ static int iwl_load_bsm(struct iwl_priv *priv)
6132 6132
6133 /* Enable future boot loads whenever power management unit triggers it 6133 /* Enable future boot loads whenever power management unit triggers it
6134 * (e.g. when powering back up after power-save shutdown) */ 6134 * (e.g. when powering back up after power-save shutdown) */
6135 iwl_write_restricted_reg(priv, BSM_WR_CTRL_REG, 6135 iwl_write_prph(priv, BSM_WR_CTRL_REG,
6136 BSM_WR_CTRL_REG_BIT_START_EN); 6136 BSM_WR_CTRL_REG_BIT_START_EN);
6137 6137
6138 iwl_release_restricted_access(priv); 6138 iwl_release_restricted_access(priv);
@@ -6387,14 +6387,14 @@ static int iwl_set_ucode_ptrs(struct iwl_priv *priv)
6387 } 6387 }
6388 6388
6389 /* Tell bootstrap uCode where to find image to load */ 6389 /* Tell bootstrap uCode where to find image to load */
6390 iwl_write_restricted_reg(priv, BSM_DRAM_INST_PTR_REG, pinst); 6390 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst);
6391 iwl_write_restricted_reg(priv, BSM_DRAM_DATA_PTR_REG, pdata); 6391 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata);
6392 iwl_write_restricted_reg(priv, BSM_DRAM_DATA_BYTECOUNT_REG, 6392 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG,
6393 priv->ucode_data.len); 6393 priv->ucode_data.len);
6394 6394
6395 /* Inst bytecount must be last to set up, bit 31 signals uCode 6395 /* Inst bytecount must be last to set up, bit 31 signals uCode
6396 * that all new ptr/size info is in place */ 6396 * that all new ptr/size info is in place */
6397 iwl_write_restricted_reg(priv, BSM_DRAM_INST_BYTECOUNT_REG, 6397 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG,
6398 priv->ucode_code.len | BSM_DRAM_INST_LOAD); 6398 priv->ucode_code.len | BSM_DRAM_INST_LOAD);
6399 6399
6400 iwl_release_restricted_access(priv); 6400 iwl_release_restricted_access(priv);
@@ -6639,7 +6639,7 @@ static void __iwl_down(struct iwl_priv *priv)
6639 6639
6640 spin_lock_irqsave(&priv->lock, flags); 6640 spin_lock_irqsave(&priv->lock, flags);
6641 if (!iwl_grab_restricted_access(priv)) { 6641 if (!iwl_grab_restricted_access(priv)) {
6642 iwl_write_restricted_reg(priv, APMG_CLK_DIS_REG, 6642 iwl_write_prph(priv, APMG_CLK_DIS_REG,
6643 APMG_CLK_VAL_DMA_CLK_RQT); 6643 APMG_CLK_VAL_DMA_CLK_RQT);
6644 iwl_release_restricted_access(priv); 6644 iwl_release_restricted_access(priv);
6645 } 6645 }
@@ -9300,7 +9300,7 @@ static void iwl_resume(struct iwl_priv *priv)
9300 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 9300 iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
9301 9301
9302 if (!iwl_grab_restricted_access(priv)) { 9302 if (!iwl_grab_restricted_access(priv)) {
9303 iwl_write_restricted_reg(priv, APMG_CLK_DIS_REG, 9303 iwl_write_prph(priv, APMG_CLK_DIS_REG,
9304 APMG_CLK_VAL_DMA_CLK_RQT); 9304 APMG_CLK_VAL_DMA_CLK_RQT);
9305 iwl_release_restricted_access(priv); 9305 iwl_release_restricted_access(priv);
9306 } 9306 }
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-29 04:05:51 -0500