11 files changed, 88 insertions, 51 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 88913a47cd34..a69a3d0d3acf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3754,17 +3754,6 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                         continue;
                 }
 
-                if (intel_encoder->type == INTEL_OUTPUT_EDP) {
-                        /* Use VBT settings if we have an eDP panel */
-                        unsigned int edp_bpc = dev_priv->edp.bpp / 3;
-
-                        if (edp_bpc < display_bpc) {
-                                DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
-                                display_bpc = edp_bpc;
-                        }
-                        continue;
-                }
-
                 /* Not one of the known troublemakers, check the EDID */
                 list_for_each_entry(connector, &dev->mode_config.connector_list,
                                     head) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0a56b9ab0f58..a6c426afaa7a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1174,10 +1174,14 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
 
         pp = ironlake_get_pp_control(dev_priv);
-        pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
+        /* We need to switch off panel power _and_ force vdd, for otherwise some
+         * panels get very unhappy and cease to work. */
+        pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
         I915_WRITE(PCH_PP_CONTROL, pp);
         POSTING_READ(PCH_PP_CONTROL);
 
+        intel_dp->want_panel_vdd = false;
+
         ironlake_wait_panel_off(intel_dp);
 }
 
@@ -1287,11 +1291,9 @@ static void intel_dp_prepare(struct drm_encoder *encoder)
          * ensure that we have vdd while we switch off the panel. */
         ironlake_edp_panel_vdd_on(intel_dp);
         ironlake_edp_backlight_off(intel_dp);
-        ironlake_edp_panel_off(intel_dp);
-
         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+        ironlake_edp_panel_off(intel_dp);
         intel_dp_link_down(intel_dp);
-        ironlake_edp_panel_vdd_off(intel_dp, false);
 }
 
 static void intel_dp_commit(struct drm_encoder *encoder)
@@ -1326,11 +1328,9 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
                 /* Switching the panel off requires vdd. */
                 ironlake_edp_panel_vdd_on(intel_dp);
                 ironlake_edp_backlight_off(intel_dp);
-                ironlake_edp_panel_off(intel_dp);
-
                 intel_dp_sink_dpms(intel_dp, mode);
+                ironlake_edp_panel_off(intel_dp);
                 intel_dp_link_down(intel_dp);
-                ironlake_edp_panel_vdd_off(intel_dp, false);
 
                 if (is_cpu_edp(intel_dp))
                         ironlake_edp_pll_off(encoder);
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d79500bc1ce5..b9755f6378d8 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -486,9 +486,6 @@ int intel_setup_gmbus(struct drm_device *dev)
                 bus->dev_priv = dev_priv;
 
                 bus->adapter.algo = &gmbus_algorithm;
-                ret = i2c_add_adapter(&bus->adapter);
-                if (ret)
-                        goto err;
 
                 /* By default use a conservative clock rate */
                 bus->reg0 = port | GMBUS_RATE_100KHZ;
@@ -498,6 +495,10 @@ int intel_setup_gmbus(struct drm_device *dev)
                         bus->force_bit = true;
 
                 intel_gpio_setup(bus, port);
+
+                ret = i2c_add_adapter(&bus->adapter);
+                if (ret)
+                        goto err;
         }
 
         intel_i2c_reset(dev_priv->dev);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 9474488db948..3df4f5fa892a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -311,9 +311,6 @@ void intel_panel_enable_backlight(struct drm_device *dev,
         if (dev_priv->backlight_level == 0)
                 dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
 
-        dev_priv->backlight_enabled = true;
-        intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
-
         if (INTEL_INFO(dev)->gen >= 4) {
                 uint32_t reg, tmp;
 
@@ -326,7 +323,7 @@ void intel_panel_enable_backlight(struct drm_device *dev,
                  * we don't track the backlight dpms state, hence check whether
                  * we have to do anything first. */
                 if (tmp & BLM_PWM_ENABLE)
-                        return;
+                        goto set_level;
 
                 if (dev_priv->num_pipe == 3)
                         tmp &= ~BLM_PIPE_SELECT_IVB;
@@ -347,6 +344,14 @@ void intel_panel_enable_backlight(struct drm_device *dev,
                         I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
                 }
         }
+
+set_level:
+        /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
+         * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
+         * registers are set.
+         */
+        dev_priv->backlight_enabled = true;
+        intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
 }
 
 static void intel_panel_init_backlight(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 414af1e2973b..e2a73b38abe9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -227,31 +227,36 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
          * number of bits based on the write domains has little performance
          * impact.
          */
-        flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
-        flags |= PIPE_CONTROL_TLB_INVALIDATE;
-        flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-        flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
-        /*
-         * Ensure that any following seqno writes only happen when the render
-         * cache is indeed flushed (but only if the caller actually wants that).
-         */
-        if (flush_domains)
+        if (flush_domains) {
+                flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+                flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+                /*
+                 * Ensure that any following seqno writes only happen
+                 * when the render cache is indeed flushed.
+                 */
                 flags |= PIPE_CONTROL_CS_STALL;
+        }
+        if (invalidate_domains) {
+                flags |= PIPE_CONTROL_TLB_INVALIDATE;
+                flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+                /*
+                 * TLB invalidate requires a post-sync write.
+                 */
+                flags |= PIPE_CONTROL_QW_WRITE;
+        }
 
-        ret = intel_ring_begin(ring, 6);
+        ret = intel_ring_begin(ring, 4);
         if (ret)
                 return ret;
 
-        intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
+        intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
         intel_ring_emit(ring, flags);
         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
-        intel_ring_emit(ring, 0); /* lower dword */
-        intel_ring_emit(ring, 0); /* uppwer dword */
-        intel_ring_emit(ring, MI_NOOP);
+        intel_ring_emit(ring, 0);
         intel_ring_advance(ring);
 
         return 0;
diff --git a/drivers/gpu/drm/nouveau/nouveau_i2c.c b/drivers/gpu/drm/nouveau/nouveau_i2c.c
index 77e564667b5c..240cf962c999 100644
--- a/drivers/gpu/drm/nouveau/nouveau_i2c.c
+++ b/drivers/gpu/drm/nouveau/nouveau_i2c.c
@@ -229,7 +229,7 @@ nouveau_i2c_init(struct drm_device *dev)
                         }
                         break;
                 case 6: /* NV50- DP AUX */
-                        port->drive = entry[0];
+                        port->drive = entry[0] & 0x0f;
                         port->sense = port->drive;
                         port->adapter.algo = &nouveau_dp_i2c_algo;
                         break;
diff --git a/drivers/gpu/drm/nouveau/nouveau_state.c b/drivers/gpu/drm/nouveau/nouveau_state.c
index 1cdfd6e757ce..1866dbb49979 100644
--- a/drivers/gpu/drm/nouveau/nouveau_state.c
+++ b/drivers/gpu/drm/nouveau/nouveau_state.c
@@ -731,7 +731,6 @@ nouveau_card_init(struct drm_device *dev)
                         case 0xa3:
                         case 0xa5:
                         case 0xa8:
-                        case 0xaf:
                                 nva3_copy_create(dev);
                                 break;
                         }
diff --git a/drivers/gpu/drm/nouveau/nv84_fifo.c b/drivers/gpu/drm/nouveau/nv84_fifo.c
index cc82d799fc3b..c564c5e4c30a 100644
--- a/drivers/gpu/drm/nouveau/nv84_fifo.c
+++ b/drivers/gpu/drm/nouveau/nv84_fifo.c
@@ -117,17 +117,22 @@ nv84_fifo_context_del(struct nouveau_channel *chan, int engine)
         struct drm_device *dev = chan->dev;
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         unsigned long flags;
+        u32 save;
 
         /* remove channel from playlist, will context switch if active */
         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
         nv_mask(dev, 0x002600 + (chan->id * 4), 0x80000000, 0x00000000);
         nv50_fifo_playlist_update(dev);
 
+        save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
+
         /* tell any engines on this channel to unload their contexts */
         nv_wr32(dev, 0x0032fc, chan->ramin->vinst >> 12);
         if (!nv_wait_ne(dev, 0x0032fc, 0xffffffff, 0xffffffff))
                 NV_INFO(dev, "PFIFO: channel %d unload timeout\n", chan->id);
 
+        nv_wr32(dev, 0x002520, save);
+
         nv_wr32(dev, 0x002600 + (chan->id * 4), 0x00000000);
         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
 
@@ -184,10 +189,13 @@ nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend)
         struct drm_nouveau_private *dev_priv = dev->dev_private;
         struct nv84_fifo_priv *priv = nv_engine(dev, engine);
         int i;
+        u32 save;
 
         /* set playlist length to zero, fifo will unload context */
         nv_wr32(dev, 0x0032ec, 0);
 
+        save = nv_mask(dev, 0x002520, 0x0000003f, 0x15);
+
         /* tell all connected engines to unload their contexts */
         for (i = 0; i < priv->base.channels; i++) {
                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
@@ -199,6 +207,7 @@ nv84_fifo_fini(struct drm_device *dev, int engine, bool suspend)
                 }
         }
 
+        nv_wr32(dev, 0x002520, save);
         nv_wr32(dev, 0x002140, 0);
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nvc0_pm.c b/drivers/gpu/drm/nouveau/nvc0_pm.c
index 7c95c44e2887..4e712b10ebdb 100644
--- a/drivers/gpu/drm/nouveau/nvc0_pm.c
+++ b/drivers/gpu/drm/nouveau/nvc0_pm.c
@@ -557,7 +557,7 @@ prog_mem(struct drm_device *dev, struct nvc0_pm_state *info)
         nouveau_mem_exec(&exec, info->perflvl);
 
         if (dev_priv->chipset < 0xd0)
-                nv_wr32(dev, 0x611200, 0x00003300);
+                nv_wr32(dev, 0x611200, 0x00003330);
         else
                 nv_wr32(dev, 0x62c000, 0x03030300);
 }
diff --git a/drivers/gpu/drm/nouveau/nvd0_display.c b/drivers/gpu/drm/nouveau/nvd0_display.c
index d0d60e1e7f95..dac525b2994e 100644
--- a/drivers/gpu/drm/nouveau/nvd0_display.c
+++ b/drivers/gpu/drm/nouveau/nvd0_display.c
@@ -790,7 +790,7 @@ nvd0_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
         struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
         int ch = EVO_CURS(nv_crtc->index);
 
-        evo_piow(crtc->dev, ch, 0x0084, (y << 16) | x);
+        evo_piow(crtc->dev, ch, 0x0084, (y << 16) | (x & 0xffff));
         evo_piow(crtc->dev, ch, 0x0080, 0x00000000);
         return 0;
 }
diff --git a/drivers/gpu/drm/nouveau/nve0_fifo.c b/drivers/gpu/drm/nouveau/nve0_fifo.c
index 1855ecbd843b..e98d144e6eb9 100644
--- a/drivers/gpu/drm/nouveau/nve0_fifo.c
+++ b/drivers/gpu/drm/nouveau/nve0_fifo.c
@@ -294,6 +294,25 @@ nve0_fifo_isr_vm_fault(struct drm_device *dev, int unit)
         printk(" on channel 0x%010llx\n", (u64)inst << 12);
 }
 
+static int
+nve0_fifo_page_flip(struct drm_device *dev, u32 chid)
+{
+        struct nve0_fifo_priv *priv = nv_engine(dev, NVOBJ_ENGINE_FIFO);
+        struct drm_nouveau_private *dev_priv = dev->dev_private;
+        struct nouveau_channel *chan = NULL;
+        unsigned long flags;
+        int ret = -EINVAL;
+
+        spin_lock_irqsave(&dev_priv->channels.lock, flags);
+        if (likely(chid >= 0 && chid < priv->base.channels)) {
+                chan = dev_priv->channels.ptr[chid];
+                if (likely(chan))
+                        ret = nouveau_finish_page_flip(chan, NULL);
+        }
+        spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
+        return ret;
+}
+
 static void
 nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
 {
@@ -303,11 +322,21 @@ nve0_fifo_isr_subfifo_intr(struct drm_device *dev, int unit)
         u32 chid = nv_rd32(dev, 0x040120 + (unit * 0x2000)) & 0x7f;
         u32 subc = (addr & 0x00070000);
         u32 mthd = (addr & 0x00003ffc);
+        u32 show = stat;
+
+        if (stat & 0x00200000) {
+                if (mthd == 0x0054) {
+                        if (!nve0_fifo_page_flip(dev, chid))
+                                show &= ~0x00200000;
+                }
+        }
 
-        NV_INFO(dev, "PSUBFIFO %d:", unit);
-        nouveau_bitfield_print(nve0_fifo_subfifo_intr, stat);
-        NV_INFO(dev, "PSUBFIFO %d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
-                unit, chid, subc, mthd, data);
+        if (show) {
+                NV_INFO(dev, "PFIFO%d:", unit);
+                nouveau_bitfield_print(nve0_fifo_subfifo_intr, show);
+                NV_INFO(dev, "PFIFO%d: ch %d subc %d mthd 0x%04x data 0x%08x\n",
+                        unit, chid, subc, mthd, data);
+        }
 
         nv_wr32(dev, 0x0400c0 + (unit * 0x2000), 0x80600008);
         nv_wr32(dev, 0x040108 + (unit * 0x2000), stat);