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-rw-r--r--Documentation/Makefile2
-rw-r--r--Documentation/arm/Makefile1
-rw-r--r--Documentation/arm/SH-Mobile/Makefile7
-rw-r--r--Documentation/arm/SH-Mobile/vrl4.c170
-rw-r--r--Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt29
-rw-r--r--Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt42
-rw-r--r--Documentation/cgroups/unified-hierarchy.txt4
-rw-r--r--Documentation/devicetree/bindings/arm/shmobile.txt4
-rw-r--r--Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt25
-rw-r--r--Documentation/devicetree/bindings/i2c/trivial-devices.txt1
-rw-r--r--Documentation/filesystems/dlmfs.txt4
-rw-r--r--Documentation/filesystems/ocfs2.txt4
-rw-r--r--MAINTAINERS4
-rw-r--r--Makefile2
-rw-r--r--arch/arm/Kconfig30
-rw-r--r--arch/arm/Kconfig.debug10
-rw-r--r--arch/arm/boot/compressed/Makefile15
-rw-r--r--arch/arm/boot/compressed/head-shmobile.S30
-rw-r--r--arch/arm/boot/compressed/mmcif-sh7372.c88
-rw-r--r--arch/arm/boot/compressed/sdhi-sh7372.c95
-rw-r--r--arch/arm/boot/compressed/sdhi-shmobile.c449
-rw-r--r--arch/arm/boot/compressed/sdhi-shmobile.h11
-rw-r--r--arch/arm/boot/dts/Makefile2
-rw-r--r--arch/arm/boot/dts/am335x-bone-common.dtsi1
-rw-r--r--arch/arm/boot/dts/am437x-idk-evm.dts25
-rw-r--r--arch/arm/boot/dts/am57xx-beagle-x15.dts8
-rw-r--r--arch/arm/boot/dts/dm8168-evm.dts25
-rw-r--r--arch/arm/boot/dts/dm816x.dtsi34
-rw-r--r--arch/arm/boot/dts/dra7-evm.dts8
-rw-r--r--arch/arm/boot/dts/dra7.dtsi8
-rw-r--r--arch/arm/boot/dts/dra72-evm.dts8
-rw-r--r--arch/arm/boot/dts/omap2.dtsi4
-rw-r--r--arch/arm/boot/dts/omap3-n900.dts9
-rw-r--r--arch/arm/boot/dts/omap3.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4.dtsi4
-rw-r--r--arch/arm/boot/dts/omap5.dtsi8
-rw-r--r--arch/arm/boot/dts/r8a7778-bockw.dts174
-rw-r--r--arch/arm/boot/dts/r8a7778.dtsi293
-rw-r--r--arch/arm/boot/dts/sh7372-mackerel.dts26
-rw-r--r--arch/arm/boot/dts/sh7372.dtsi35
-rw-r--r--arch/arm/configs/mackerel_defconfig157
-rw-r--r--arch/arm/configs/multi_v7_defconfig82
-rw-r--r--arch/arm/configs/omap2plus_defconfig4
-rw-r--r--arch/arm/mach-asm9260/Kconfig2
-rw-r--r--arch/arm/mach-shmobile/Kconfig20
-rw-r--r--arch/arm/mach-shmobile/Makefile6
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot1
-rw-r--r--arch/arm/mach-shmobile/board-bockw-reference.c2
-rw-r--r--arch/arm/mach-shmobile/board-mackerel.c1522
-rw-r--r--arch/arm/mach-shmobile/clock-sh7372.c620
-rw-r--r--arch/arm/mach-shmobile/clock.c11
-rw-r--r--arch/arm/mach-shmobile/common.h1
-rw-r--r--arch/arm/mach-shmobile/entry-intc.S54
-rw-r--r--arch/arm/mach-shmobile/include/mach/clkdev.h7
-rw-r--r--arch/arm/mach-shmobile/include/mach/head-mackerel.txt93
-rw-r--r--arch/arm/mach-shmobile/include/mach/mmc-mackerel.h38
-rw-r--r--arch/arm/mach-shmobile/include/mach/mmc.h16
-rw-r--r--arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h21
-rw-r--r--arch/arm/mach-shmobile/include/mach/sdhi.h16
-rw-r--r--arch/arm/mach-shmobile/include/mach/system.h11
-rw-r--r--arch/arm/mach-shmobile/include/mach/uncompress.h19
-rw-r--r--arch/arm/mach-shmobile/include/mach/zboot.h5
-rw-r--r--arch/arm/mach-shmobile/intc-sh7372.c672
-rw-r--r--arch/arm/mach-shmobile/pm-sh7372.c549
-rw-r--r--arch/arm/mach-shmobile/setup-r8a7778.c19
-rw-r--r--arch/arm/mach-shmobile/setup-sh7372.c1016
-rw-r--r--arch/arm/mach-shmobile/sh7372.h84
-rw-r--r--arch/arm/mach-shmobile/sleep-sh7372.S98
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7779.c7
-rw-r--r--arch/arm/tools/mach-types1
-rw-r--r--arch/arm64/boot/dts/arm/foundation-v8.dts8
-rw-r--r--arch/arm64/boot/dts/arm/juno.dts14
-rw-r--r--arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts8
-rw-r--r--arch/arm64/crypto/Makefile2
-rw-r--r--arch/arm64/include/asm/assembler.h5
-rw-r--r--arch/arm64/include/asm/cpuidle.h2
-rw-r--r--arch/arm64/include/asm/insn.h6
-rw-r--r--arch/arm64/include/asm/pgtable.h2
-rw-r--r--arch/arm64/include/asm/processor.h3
-rw-r--r--arch/arm64/include/asm/tlbflush.h5
-rw-r--r--arch/arm64/kernel/Makefile5
-rw-r--r--arch/arm64/kernel/ftrace.c2
-rw-r--r--arch/arm64/kernel/insn.c4
-rw-r--r--arch/arm64/kernel/psci-call.S28
-rw-r--r--arch/arm64/kernel/psci.c37
-rw-r--r--arch/arm64/kernel/signal32.c5
-rw-r--r--arch/arm64/kernel/vdso/gettimeofday.S3
-rw-r--r--arch/arm64/mm/dma-mapping.c16
-rw-r--r--arch/arm64/mm/init.c14
-rw-r--r--arch/frv/include/asm/pgtable.h2
-rw-r--r--arch/m32r/include/asm/pgtable-2level.h1
-rw-r--r--arch/m68k/include/asm/pgtable_mm.h2
-rw-r--r--arch/metag/include/asm/processor.h4
-rw-r--r--arch/mn10300/include/asm/pgtable.h2
-rw-r--r--arch/parisc/include/asm/pgtable.h1
-rw-r--r--arch/s390/include/asm/pgtable.h2
-rw-r--r--arch/x86/kernel/cpu/common.c6
-rw-r--r--arch/x86/kernel/cpu/intel.c4
-rw-r--r--arch/x86/kernel/entry_32.S3
-rw-r--r--arch/x86/kernel/entry_64.S3
-rw-r--r--arch/x86/kernel/kprobes/core.c54
-rw-r--r--arch/x86/kernel/kprobes/opt.c2
-rw-r--r--arch/x86/lguest/Kconfig4
-rw-r--r--arch/x86/platform/intel-mid/intel-mid.c2
-rw-r--r--arch/x86/xen/enlighten.c20
-rw-r--r--drivers/block/nvme-core.c99
-rw-r--r--drivers/block/zram/zram_drv.c2
-rw-r--r--drivers/clk/shmobile/Makefile1
-rw-r--r--drivers/clk/shmobile/clk-r8a7778.c143
-rw-r--r--drivers/clocksource/Kconfig16
-rw-r--r--drivers/clocksource/mtk_timer.c9
-rw-r--r--drivers/clocksource/pxa_timer.c2
-rw-r--r--drivers/gpio/gpio-tps65912.c14
-rw-r--r--drivers/gpio/gpiolib-of.c9
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c10
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h8
-rw-r--r--drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c2
-rw-r--r--drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c2
-rw-r--r--drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c2
-rw-r--r--drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c3
-rw-r--r--drivers/gpu/drm/drm_crtc.c3
-rw-r--r--drivers/gpu/drm/i915/i915_drv.h15
-rw-r--r--drivers/gpu/drm/i915/i915_gem.c3
-rw-r--r--drivers/gpu/drm/i915/i915_gem_stolen.c6
-rw-r--r--drivers/gpu/drm/i915/i915_gem_tiling.c7
-rw-r--r--drivers/gpu/drm/i915/i915_irq.c22
-rw-r--r--drivers/gpu/drm/i915/intel_display.c34
-rw-r--r--drivers/gpu/drm/i915/intel_lrc.c8
-rw-r--r--drivers/gpu/drm/radeon/atombios_dp.c7
-rw-r--r--drivers/gpu/drm/radeon/atombios_encoders.c21
-rw-r--r--drivers/gpu/drm/radeon/cik.c8
-rw-r--r--drivers/gpu/drm/radeon/cikd.h4
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c7
-rw-r--r--drivers/gpu/drm/radeon/evergreend.h4
-rw-r--r--drivers/gpu/drm/radeon/ni.c10
-rw-r--r--drivers/gpu/drm/radeon/nid.h4
-rw-r--r--drivers/gpu/drm/radeon/r600_dpm.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c16
-rw-r--r--drivers/gpu/drm/radeon/radeon_encoders.c3
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c6
-rw-r--r--drivers/gpu/drm/radeon/si.c22
-rw-r--r--drivers/gpu/drm/radeon/sid.h4
-rw-r--r--drivers/gpu/drm/tegra/dc.c79
-rw-r--r--drivers/gpu/drm/tegra/hdmi.c8
-rw-r--r--drivers/hid/hid-core.c2
-rw-r--r--drivers/hid/hid-ids.h2
-rw-r--r--drivers/hid/hid-microsoft.c2
-rw-r--r--drivers/hid/hid-saitek.c2
-rw-r--r--drivers/hid/hid-sensor-hub.c8
-rw-r--r--drivers/hid/hid-sony.c6
-rw-r--r--drivers/hid/i2c-hid/i2c-hid.c7
-rw-r--r--drivers/hid/wacom_wac.c11
-rw-r--r--drivers/hwmon/ads7828.c3
-rw-r--r--drivers/md/md.c14
-rw-r--r--drivers/md/raid1.c5
-rw-r--r--drivers/md/raid5.c13
-rw-r--r--drivers/rtc/rtc-ds1685.c18
-rw-r--r--drivers/sh/pm_runtime.c2
-rw-r--r--drivers/thermal/int340x_thermal/int3400_thermal.c10
-rw-r--r--drivers/thermal/intel_powerclamp.c1
-rw-r--r--drivers/thermal/rcar_thermal.c26
-rw-r--r--drivers/thermal/samsung/exynos_tmu.c38
-rw-r--r--drivers/thermal/ti-soc-thermal/ti-bandgap.c2
-rw-r--r--drivers/thermal/ti-soc-thermal/ti-thermal-common.c2
-rw-r--r--drivers/xen/Makefile2
-rw-r--r--drivers/xen/preempt.c44
-rw-r--r--drivers/xen/privcmd.c2
-rw-r--r--drivers/xen/xen-scsiback.c14
-rw-r--r--fs/btrfs/volumes.c9
-rw-r--r--fs/nilfs2/btree.c47
-rw-r--r--fs/xfs/xfs_file.c14
-rw-r--r--fs/xfs/xfs_inode.c4
-rw-r--r--fs/xfs/xfs_inode.h9
-rw-r--r--fs/xfs/xfs_iops.c36
-rw-r--r--fs/xfs/xfs_pnfs.c4
-rw-r--r--fs/xfs/xfs_qm.c5
-rw-r--r--include/drm/i915_pciids.h4
-rw-r--r--include/dt-bindings/clock/r8a7778-clock.h71
-rw-r--r--include/linux/clk/shmobile.h1
-rw-r--r--include/linux/hid-sensor-hub.h5
-rw-r--r--include/linux/thermal.h56
-rw-r--r--include/xen/xen-ops.h26
-rw-r--r--kernel/livepatch/core.c10
-rw-r--r--kernel/locking/rtmutex.c1
-rw-r--r--kernel/sys.c3
-rw-r--r--mm/memcontrol.c16
-rw-r--r--mm/nommu.c4
-rw-r--r--mm/page_alloc.c9
-rw-r--r--mm/shmem.c3
-rw-r--r--scripts/gdb/linux/__init__.py1
-rw-r--r--sound/core/pcm_native.c2
-rw-r--r--sound/firewire/amdtp.c5
-rw-r--r--sound/firewire/bebob/bebob.c20
-rw-r--r--sound/firewire/bebob/bebob_stream.c16
-rw-r--r--sound/firewire/dice/dice-stream.c18
-rw-r--r--sound/firewire/dice/dice.c16
-rw-r--r--sound/firewire/fireworks/fireworks.c20
-rw-r--r--sound/firewire/fireworks/fireworks_stream.c19
-rw-r--r--sound/firewire/oxfw/oxfw-stream.c6
-rw-r--r--sound/firewire/oxfw/oxfw.c21
-rw-r--r--sound/pci/hda/hda_controller.c5
-rw-r--r--sound/pci/hda/hda_intel.c2
-rw-r--r--sound/pci/hda/patch_sigmatel.c17
-rw-r--r--tools/perf/bench/mem-memcpy.c4
-rw-r--r--tools/perf/config/Makefile.arch4
-rw-r--r--tools/perf/config/feature-checks/Makefile2
-rw-r--r--tools/perf/config/feature-checks/test-pthread-attr-setaffinity-np.c3
-rw-r--r--tools/perf/util/cloexec.c18
-rw-r--r--tools/perf/util/evlist.h2
-rw-r--r--tools/perf/util/symbol-elf.c5
-rw-r--r--tools/thermal/tmon/.gitignore1
-rw-r--r--tools/thermal/tmon/Makefile15
-rw-r--r--tools/thermal/tmon/tmon.82
-rw-r--r--tools/thermal/tmon/tmon.c14
-rw-r--r--tools/thermal/tmon/tui.c45
215 files changed, 1971 insertions, 6648 deletions
diff --git a/Documentation/Makefile b/Documentation/Makefile
index 6883a1b9b351..bc0548201755 100644
--- a/Documentation/Makefile
+++ b/Documentation/Makefile
@@ -1,4 +1,4 @@
1subdir-y := accounting arm auxdisplay blackfin connector \ 1subdir-y := accounting auxdisplay blackfin connector \
2 filesystems filesystems ia64 laptops mic misc-devices \ 2 filesystems filesystems ia64 laptops mic misc-devices \
3 networking pcmcia prctl ptp spi timers vDSO video4linux \ 3 networking pcmcia prctl ptp spi timers vDSO video4linux \
4 watchdog 4 watchdog
diff --git a/Documentation/arm/Makefile b/Documentation/arm/Makefile
deleted file mode 100644
index 732c77050cff..000000000000
--- a/Documentation/arm/Makefile
+++ /dev/null
@@ -1 +0,0 @@
1subdir-y := SH-Mobile
diff --git a/Documentation/arm/SH-Mobile/Makefile b/Documentation/arm/SH-Mobile/Makefile
deleted file mode 100644
index bca8a7ef6bbe..000000000000
--- a/Documentation/arm/SH-Mobile/Makefile
+++ /dev/null
@@ -1,7 +0,0 @@
1# List of programs to build
2hostprogs-y := vrl4
3
4# Tell kbuild to always build the programs
5always := $(hostprogs-y)
6
7HOSTCFLAGS_vrl4.o += -I$(objtree)/usr/include -I$(srctree)/tools/include
diff --git a/Documentation/arm/SH-Mobile/vrl4.c b/Documentation/arm/SH-Mobile/vrl4.c
deleted file mode 100644
index f4cd8ad4e720..000000000000
--- a/Documentation/arm/SH-Mobile/vrl4.c
+++ /dev/null
@@ -1,170 +0,0 @@
1/*
2 * vrl4 format generator
3 *
4 * Copyright (C) 2010 Simon Horman
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11/*
12 * usage: vrl4 < zImage > out
13 * dd if=out of=/dev/sdx bs=512 seek=1 # Write the image to sector 1
14 *
15 * Reads a zImage from stdin and writes a vrl4 image to stdout.
16 * In practice this means writing a padded vrl4 header to stdout followed
17 * by the zImage.
18 *
19 * The padding places the zImage at ALIGN bytes into the output.
20 * The vrl4 uses ALIGN + START_BASE as the start_address.
21 * This is where the mask ROM will jump to after verifying the header.
22 *
23 * The header sets copy_size to min(sizeof(zImage), MAX_BOOT_PROG_LEN) + ALIGN.
24 * That is, the mask ROM will load the padded header (ALIGN bytes)
25 * And then MAX_BOOT_PROG_LEN bytes of the image, or the entire image,
26 * whichever is smaller.
27 *
28 * The zImage is not modified in any way.
29 */
30
31#define _BSD_SOURCE
32#include <endian.h>
33#include <unistd.h>
34#include <stdint.h>
35#include <stdio.h>
36#include <errno.h>
37#include <tools/endian.h>
38
39struct hdr {
40 uint32_t magic1;
41 uint32_t reserved1;
42 uint32_t magic2;
43 uint32_t reserved2;
44 uint16_t copy_size;
45 uint16_t boot_options;
46 uint32_t reserved3;
47 uint32_t start_address;
48 uint32_t reserved4;
49 uint32_t reserved5;
50 char reserved6[308];
51};
52
53#define DECLARE_HDR(h) \
54 struct hdr (h) = { \
55 .magic1 = htole32(0xea000000), \
56 .reserved1 = htole32(0x56), \
57 .magic2 = htole32(0xe59ff008), \
58 .reserved3 = htole16(0x1) }
59
60/* Align to 512 bytes, the MMCIF sector size */
61#define ALIGN_BITS 9
62#define ALIGN (1 << ALIGN_BITS)
63
64#define START_BASE 0xe55b0000
65
66/*
67 * With an alignment of 512 the header uses the first sector.
68 * There is a 128 sector (64kbyte) limit on the data loaded by the mask ROM.
69 * So there are 127 sectors left for the boot programme. But in practice
70 * Only a small portion of a zImage is needed, 16 sectors should be more
71 * than enough.
72 *
73 * Note that this sets how much of the zImage is copied by the mask ROM.
74 * The entire zImage is present after the header and is loaded
75 * by the code in the boot program (which is the first portion of the zImage).
76 */
77#define MAX_BOOT_PROG_LEN (16 * 512)
78
79#define ROUND_UP(x) ((x + ALIGN - 1) & ~(ALIGN - 1))
80
81static ssize_t do_read(int fd, void *buf, size_t count)
82{
83 size_t offset = 0;
84 ssize_t l;
85
86 while (offset < count) {
87 l = read(fd, buf + offset, count - offset);
88 if (!l)
89 break;
90 if (l < 0) {
91 if (errno == EAGAIN || errno == EWOULDBLOCK)
92 continue;
93 perror("read");
94 return -1;
95 }
96 offset += l;
97 }
98
99 return offset;
100}
101
102static ssize_t do_write(int fd, const void *buf, size_t count)
103{
104 size_t offset = 0;
105 ssize_t l;
106
107 while (offset < count) {
108 l = write(fd, buf + offset, count - offset);
109 if (l < 0) {
110 if (errno == EAGAIN || errno == EWOULDBLOCK)
111 continue;
112 perror("write");
113 return -1;
114 }
115 offset += l;
116 }
117
118 return offset;
119}
120
121static ssize_t write_zero(int fd, size_t len)
122{
123 size_t i = len;
124
125 while (i--) {
126 const char x = 0;
127 if (do_write(fd, &x, 1) < 0)
128 return -1;
129 }
130
131 return len;
132}
133
134int main(void)
135{
136 DECLARE_HDR(hdr);
137 char boot_program[MAX_BOOT_PROG_LEN];
138 size_t aligned_hdr_len, alligned_prog_len;
139 ssize_t prog_len;
140
141 prog_len = do_read(0, boot_program, sizeof(boot_program));
142 if (prog_len <= 0)
143 return -1;
144
145 aligned_hdr_len = ROUND_UP(sizeof(hdr));
146 hdr.start_address = htole32(START_BASE + aligned_hdr_len);
147 alligned_prog_len = ROUND_UP(prog_len);
148 hdr.copy_size = htole16(aligned_hdr_len + alligned_prog_len);
149
150 if (do_write(1, &hdr, sizeof(hdr)) < 0)
151 return -1;
152 if (write_zero(1, aligned_hdr_len - sizeof(hdr)) < 0)
153 return -1;
154
155 if (do_write(1, boot_program, prog_len) < 0)
156 return 1;
157
158 /* Write out the rest of the kernel */
159 while (1) {
160 prog_len = do_read(0, boot_program, sizeof(boot_program));
161 if (prog_len < 0)
162 return 1;
163 if (prog_len == 0)
164 break;
165 if (do_write(1, boot_program, prog_len) < 0)
166 return 1;
167 }
168
169 return 0;
170}
diff --git a/Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt b/Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt
deleted file mode 100644
index efff8ae2713d..000000000000
--- a/Documentation/arm/SH-Mobile/zboot-rom-mmcif.txt
+++ /dev/null
@@ -1,29 +0,0 @@
1ROM-able zImage boot from MMC
2-----------------------------
3
4An ROM-able zImage compiled with ZBOOT_ROM_MMCIF may be written to MMC and
5SuperH Mobile ARM will to boot directly from the MMCIF hardware block.
6
7This is achieved by the mask ROM loading the first portion of the image into
8MERAM and then jumping to it. This portion contains loader code which
9copies the entire image to SDRAM and jumps to it. From there the zImage
10boot code proceeds as normal, uncompressing the image into its final
11location and then jumping to it.
12
13This code has been tested on an AP4EB board using the developer 1A eMMC
14boot mode which is configured using the following jumper settings.
15The board used for testing required a patched mask ROM in order for
16this mode to function.
17
18 8 7 6 5 4 3 2 1
19 x|x|x|x|x| |x|
20S4 -+-+-+-+-+-+-+-
21 | | | | |x| |x on
22
23The zImage must be written to the MMC card at sector 1 (512 bytes) in
24vrl4 format. A utility vrl4 is supplied to accomplish this.
25
26e.g.
27 vrl4 < zImage | dd of=/dev/sdX bs=512 seek=1
28
29A dual-voltage MMC 4.0 card was used for testing.
diff --git a/Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt b/Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt
deleted file mode 100644
index 441959846e1a..000000000000
--- a/Documentation/arm/SH-Mobile/zboot-rom-sdhi.txt
+++ /dev/null
@@ -1,42 +0,0 @@
1ROM-able zImage boot from eSD
2-----------------------------
3
4An ROM-able zImage compiled with ZBOOT_ROM_SDHI may be written to eSD and
5SuperH Mobile ARM will to boot directly from the SDHI hardware block.
6
7This is achieved by the mask ROM loading the first portion of the image into
8MERAM and then jumping to it. This portion contains loader code which
9copies the entire image to SDRAM and jumps to it. From there the zImage
10boot code proceeds as normal, uncompressing the image into its final
11location and then jumping to it.
12
13This code has been tested on an mackerel board using the developer 1A eSD
14boot mode which is configured using the following jumper settings.
15
16 8 7 6 5 4 3 2 1
17 x|x|x|x| |x|x|
18S4 -+-+-+-+-+-+-+-
19 | | | |x| | |x on
20
21The eSD card needs to be present in SDHI slot 1 (CN7).
22As such S1 and S33 also need to be configured as per
23the notes in arch/arm/mach-shmobile/board-mackerel.c.
24
25A partial zImage must be written to physical partition #1 (boot)
26of the eSD at sector 0 in vrl4 format. A utility vrl4 is supplied to
27accomplish this.
28
29e.g.
30 vrl4 < zImage | dd of=/dev/sdX bs=512 count=17
31
32A full copy of _the same_ zImage should be written to physical partition #1
33(boot) of the eSD at sector 0. This should _not_ be in vrl4 format.
34
35 vrl4 < zImage | dd of=/dev/sdX bs=512
36
37Note: The commands above assume that the physical partition has been
38switched. No such facility currently exists in the Linux Kernel.
39
40Physical partitions are described in the eSD specification. At the time of
41writing they are not the same as partitions that are typically configured
42using fdisk and visible through /proc/partitions
diff --git a/Documentation/cgroups/unified-hierarchy.txt b/Documentation/cgroups/unified-hierarchy.txt
index 71daa35ec2d9..eb102fb72213 100644
--- a/Documentation/cgroups/unified-hierarchy.txt
+++ b/Documentation/cgroups/unified-hierarchy.txt
@@ -404,8 +404,8 @@ supported and the interface files "release_agent" and
404 be understood as an underflow into the highest possible value, -2 or 404 be understood as an underflow into the highest possible value, -2 or
405 -10M etc. do not work, so it's not consistent. 405 -10M etc. do not work, so it's not consistent.
406 406
407 memory.low, memory.high, and memory.max will use the string 407 memory.low, memory.high, and memory.max will use the string "max" to
408 "infinity" to indicate and set the highest possible value. 408 indicate and set the highest possible value.
409 409
4105. Planned Changes 4105. Planned Changes
411 411
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 18a8591b5c39..2f8043ee438d 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -7,8 +7,6 @@ SoCs:
7 compatible = "renesas,emev2" 7 compatible = "renesas,emev2"
8 - RZ/A1H (R7S72100) 8 - RZ/A1H (R7S72100)
9 compatible = "renesas,r7s72100" 9 compatible = "renesas,r7s72100"
10 - SH-Mobile AP4 (R8A73720/SH7372)
11 compatible = "renesas,sh7372"
12 - SH-Mobile AG5 (R8A73A00/SH73A0) 10 - SH-Mobile AG5 (R8A73A00/SH73A0)
13 compatible = "renesas,sh73a0" 11 compatible = "renesas,sh73a0"
14 - R-Mobile APE6 (R8A73A40) 12 - R-Mobile APE6 (R8A73A40)
@@ -59,8 +57,6 @@ Boards:
59 compatible = "renesas,kzm9g-reference", "renesas,sh73a0" 57 compatible = "renesas,kzm9g-reference", "renesas,sh73a0"
60 - Lager (RTP0RC7790SEB00010S) 58 - Lager (RTP0RC7790SEB00010S)
61 compatible = "renesas,lager", "renesas,r8a7790" 59 compatible = "renesas,lager", "renesas,r8a7790"
62 - Mackerel (R0P7372LC0016RL, AP4 EVM 2nd)
63 compatible = "renesas,mackerel"
64 - Marzen 60 - Marzen
65 compatible = "renesas,marzen", "renesas,r8a7779" 61 compatible = "renesas,marzen", "renesas,r8a7779"
66 62
diff --git a/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
new file mode 100644
index 000000000000..2f3747fdcf1c
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/renesas,r8a7778-cpg-clocks.txt
@@ -0,0 +1,25 @@
1* Renesas R8A7778 Clock Pulse Generator (CPG)
2
3The CPG generates core clocks for the R8A7778. It includes two PLLs and
4several fixed ratio dividers
5
6Required Properties:
7
8 - compatible: Must be "renesas,r8a7778-cpg-clocks"
9 - reg: Base address and length of the memory resource used by the CPG
10 - #clock-cells: Must be 1
11 - clock-output-names: The names of the clocks. Supported clocks are
12 "plla", "pllb", "b", "out", "p", "s", and "s1".
13
14
15Example
16-------
17
18 cpg_clocks: cpg_clocks@ffc80000 {
19 compatible = "renesas,r8a7778-cpg-clocks";
20 reg = <0xffc80000 0x80>;
21 #clock-cells = <1>;
22 clocks = <&extal_clk>;
23 clock-output-names = "plla", "pllb", "b",
24 "out", "p", "s", "s1";
25 };
diff --git a/Documentation/devicetree/bindings/i2c/trivial-devices.txt b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
index aaa8325004d2..7cbd62ba1f6c 100644
--- a/Documentation/devicetree/bindings/i2c/trivial-devices.txt
+++ b/Documentation/devicetree/bindings/i2c/trivial-devices.txt
@@ -77,6 +77,7 @@ nxp,pca9556 Octal SMBus and I2C registered interface
77nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset 77nxp,pca9557 8-bit I2C-bus and SMBus I/O port with reset
78nxp,pcf8563 Real-time clock/calendar 78nxp,pcf8563 Real-time clock/calendar
79nxp,pcf85063 Tiny Real-Time Clock 79nxp,pcf85063 Tiny Real-Time Clock
80oki,ml86v7667 OKI ML86V7667 video decoder
80ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus 81ovti,ov5642 OV5642: Color CMOS QSXGA (5-megapixel) Image Sensor with OmniBSI and Embedded TrueFocus
81pericom,pt7c4338 Real-time Clock Module 82pericom,pt7c4338 Real-time Clock Module
82plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch 83plx,pex8648 48-Lane, 12-Port PCI Express Gen 2 (5.0 GT/s) Switch
diff --git a/Documentation/filesystems/dlmfs.txt b/Documentation/filesystems/dlmfs.txt
index 1b528b2ad809..fcf4d509d118 100644
--- a/Documentation/filesystems/dlmfs.txt
+++ b/Documentation/filesystems/dlmfs.txt
@@ -5,8 +5,8 @@ system.
5 5
6dlmfs is built with OCFS2 as it requires most of its infrastructure. 6dlmfs is built with OCFS2 as it requires most of its infrastructure.
7 7
8Project web page: http://oss.oracle.com/projects/ocfs2 8Project web page: http://ocfs2.wiki.kernel.org
9Tools web page: http://oss.oracle.com/projects/ocfs2-tools 9Tools web page: https://github.com/markfasheh/ocfs2-tools
10OCFS2 mailing lists: http://oss.oracle.com/projects/ocfs2/mailman/ 10OCFS2 mailing lists: http://oss.oracle.com/projects/ocfs2/mailman/
11 11
12All code copyright 2005 Oracle except when otherwise noted. 12All code copyright 2005 Oracle except when otherwise noted.
diff --git a/Documentation/filesystems/ocfs2.txt b/Documentation/filesystems/ocfs2.txt
index 28f8c08201e2..4c49e5410595 100644
--- a/Documentation/filesystems/ocfs2.txt
+++ b/Documentation/filesystems/ocfs2.txt
@@ -8,8 +8,8 @@ also make it attractive for non-clustered use.
8You'll want to install the ocfs2-tools package in order to at least 8You'll want to install the ocfs2-tools package in order to at least
9get "mount.ocfs2" and "ocfs2_hb_ctl". 9get "mount.ocfs2" and "ocfs2_hb_ctl".
10 10
11Project web page: http://oss.oracle.com/projects/ocfs2 11Project web page: http://ocfs2.wiki.kernel.org
12Tools web page: http://oss.oracle.com/projects/ocfs2-tools 12Tools git tree: https://github.com/markfasheh/ocfs2-tools
13OCFS2 mailing lists: http://oss.oracle.com/projects/ocfs2/mailman/ 13OCFS2 mailing lists: http://oss.oracle.com/projects/ocfs2/mailman/
14 14
15All code copyright 2005 Oracle except when otherwise noted. 15All code copyright 2005 Oracle except when otherwise noted.
diff --git a/MAINTAINERS b/MAINTAINERS
index 5181e7a8d803..931043310346 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1417,7 +1417,6 @@ F: arch/arm/boot/dts/sh*
1417F: arch/arm/configs/armadillo800eva_defconfig 1417F: arch/arm/configs/armadillo800eva_defconfig
1418F: arch/arm/configs/bockw_defconfig 1418F: arch/arm/configs/bockw_defconfig
1419F: arch/arm/configs/kzm9g_defconfig 1419F: arch/arm/configs/kzm9g_defconfig
1420F: arch/arm/configs/mackerel_defconfig
1421F: arch/arm/configs/marzen_defconfig 1420F: arch/arm/configs/marzen_defconfig
1422F: arch/arm/configs/shmobile_defconfig 1421F: arch/arm/configs/shmobile_defconfig
1423F: arch/arm/include/debug/renesas-scif.S 1422F: arch/arm/include/debug/renesas-scif.S
@@ -7212,8 +7211,7 @@ ORACLE CLUSTER FILESYSTEM 2 (OCFS2)
7212M: Mark Fasheh <mfasheh@suse.com> 7211M: Mark Fasheh <mfasheh@suse.com>
7213M: Joel Becker <jlbec@evilplan.org> 7212M: Joel Becker <jlbec@evilplan.org>
7214L: ocfs2-devel@oss.oracle.com (moderated for non-subscribers) 7213L: ocfs2-devel@oss.oracle.com (moderated for non-subscribers)
7215W: http://oss.oracle.com/projects/ocfs2/ 7214W: http://ocfs2.wiki.kernel.org
7216T: git git://git.kernel.org/pub/scm/linux/kernel/git/jlbec/ocfs2.git
7217S: Supported 7215S: Supported
7218F: Documentation/filesystems/ocfs2.txt 7216F: Documentation/filesystems/ocfs2.txt
7219F: Documentation/filesystems/dlmfs.txt 7217F: Documentation/filesystems/dlmfs.txt
diff --git a/Makefile b/Makefile
index 9fab639727c7..e6a9b1b94656 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
1VERSION = 4 1VERSION = 4
2PATCHLEVEL = 0 2PATCHLEVEL = 0
3SUBLEVEL = 0 3SUBLEVEL = 0
4EXTRAVERSION = -rc1 4EXTRAVERSION = -rc2
5NAME = Hurr durr I'ma sheep 5NAME = Hurr durr I'ma sheep
6 6
7# *DOCUMENTATION* 7# *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 9f1f09a2bc9b..55f1d9ba4b20 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -646,7 +646,6 @@ config ARCH_SHMOBILE_LEGACY
646 select GENERIC_CLOCKEVENTS 646 select GENERIC_CLOCKEVENTS
647 select HAVE_ARM_SCU if SMP 647 select HAVE_ARM_SCU if SMP
648 select HAVE_ARM_TWD if SMP 648 select HAVE_ARM_TWD if SMP
649 select HAVE_MACH_CLKDEV
650 select HAVE_SMP 649 select HAVE_SMP
651 select MIGHT_HAVE_CACHE_L2X0 650 select MIGHT_HAVE_CACHE_L2X0
652 select MULTI_IRQ_HANDLER 651 select MULTI_IRQ_HANDLER
@@ -1848,35 +1847,6 @@ config ZBOOT_ROM
1848 Say Y here if you intend to execute your compressed kernel image 1847 Say Y here if you intend to execute your compressed kernel image
1849 (zImage) directly from ROM or flash. If unsure, say N. 1848 (zImage) directly from ROM or flash. If unsure, say N.
1850 1849
1851choice
1852 prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1853 depends on ZBOOT_ROM && ARCH_SH7372
1854 default ZBOOT_ROM_NONE
1855 help
1856 Include experimental SD/MMC loading code in the ROM-able zImage.
1857 With this enabled it is possible to write the ROM-able zImage
1858 kernel image to an MMC or SD card and boot the kernel straight
1859 from the reset vector. At reset the processor Mask ROM will load
1860 the first part of the ROM-able zImage which in turn loads the
1861 rest the kernel image to RAM.
1862
1863config ZBOOT_ROM_NONE
1864 bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1865 help
1866 Do not load image from SD or MMC
1867
1868config ZBOOT_ROM_MMCIF
1869 bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1870 help
1871 Load image from MMCIF hardware block.
1872
1873config ZBOOT_ROM_SH_MOBILE_SDHI
1874 bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1875 help
1876 Load image from SDHI hardware block
1877
1878endchoice
1879
1880config ARM_APPENDED_DTB 1850config ARM_APPENDED_DTB
1881 bool "Use appended device tree blob to zImage (EXPERIMENTAL)" 1851 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1882 depends on OF 1852 depends on OF
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index 970de7518341..6e55ed915332 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -821,12 +821,11 @@ choice
821 via SCIF2 on Renesas R-Car E2 (R8A7794). 821 via SCIF2 on Renesas R-Car E2 (R8A7794).
822 822
823 config DEBUG_RMOBILE_SCIFA0 823 config DEBUG_RMOBILE_SCIFA0
824 bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4/SH7372" 824 bool "Kernel low-level debugging messages via SCIFA0 on R8A73A4"
825 depends on ARCH_R8A73A4 || ARCH_SH7372 825 depends on ARCH_R8A73A4
826 help 826 help
827 Say Y here if you want kernel low-level debugging support 827 Say Y here if you want kernel low-level debugging support
828 via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4) or SH-Mobile 828 via SCIFA0 on Renesas R-Mobile APE6 (R8A73A4).
829 AP4 (SH7372).
830 829
831 config DEBUG_RMOBILE_SCIFA1 830 config DEBUG_RMOBILE_SCIFA1
832 bool "Kernel low-level debugging messages via SCIFA1 on R8A7740" 831 bool "Kernel low-level debugging messages via SCIFA1 on R8A7740"
@@ -1573,7 +1572,8 @@ config DEBUG_UNCOMPRESS
1573config UNCOMPRESS_INCLUDE 1572config UNCOMPRESS_INCLUDE
1574 string 1573 string
1575 default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \ 1574 default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
1576 PLAT_SAMSUNG || ARCH_EFM32 1575 PLAT_SAMSUNG || ARCH_EFM32 || \
1576 ARCH_SHMOBILE_LEGACY
1577 default "mach/uncompress.h" 1577 default "mach/uncompress.h"
1578 1578
1579config EARLY_PRINTK 1579config EARLY_PRINTK
diff --git a/arch/arm/boot/compressed/Makefile b/arch/arm/boot/compressed/Makefile
index 3ea230aa94b7..6e1fb2b2ecc7 100644
--- a/arch/arm/boot/compressed/Makefile
+++ b/arch/arm/boot/compressed/Makefile
@@ -6,21 +6,6 @@
6 6
7OBJS = 7OBJS =
8 8
9# Ensure that MMCIF loader code appears early in the image
10# to minimise that number of bocks that have to be read in
11# order to load it.
12ifeq ($(CONFIG_ZBOOT_ROM_MMCIF),y)
13OBJS += mmcif-sh7372.o
14endif
15
16# Ensure that SDHI loader code appears early in the image
17# to minimise that number of bocks that have to be read in
18# order to load it.
19ifeq ($(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI),y)
20OBJS += sdhi-shmobile.o
21OBJS += sdhi-sh7372.o
22endif
23
24AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET) 9AFLAGS_head.o += -DTEXT_OFFSET=$(TEXT_OFFSET)
25HEAD = head.o 10HEAD = head.o
26OBJS += misc.o decompress.o 11OBJS += misc.o decompress.o
diff --git a/arch/arm/boot/compressed/head-shmobile.S b/arch/arm/boot/compressed/head-shmobile.S
index e7f80928949c..22a75259faa3 100644
--- a/arch/arm/boot/compressed/head-shmobile.S
+++ b/arch/arm/boot/compressed/head-shmobile.S
@@ -25,36 +25,6 @@
25 /* load board-specific initialization code */ 25 /* load board-specific initialization code */
26#include <mach/zboot.h> 26#include <mach/zboot.h>
27 27
28#if defined(CONFIG_ZBOOT_ROM_MMCIF) || defined(CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI)
29 /* Load image from MMC/SD */
30 adr sp, __tmp_stack + 256
31 ldr r0, __image_start
32 ldr r1, __image_end
33 subs r1, r1, r0
34 ldr r0, __load_base
35 bl mmc_loader
36
37 /* Jump to loaded code */
38 ldr r0, __loaded
39 ldr r1, __image_start
40 sub r0, r0, r1
41 ldr r1, __load_base
42 add pc, r0, r1
43
44__image_start:
45 .long _start
46__image_end:
47 .long _got_end
48__load_base:
49 .long MEMORY_START + 0x02000000 @ Load at 32Mb into SDRAM
50__loaded:
51 .long __continue
52 .align
53__tmp_stack:
54 .space 256
55__continue:
56#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
57
58 adr r0, dtb_info 28 adr r0, dtb_info
59 ldmia r0, {r1, r3, r4, r5, r7} 29 ldmia r0, {r1, r3, r4, r5, r7}
60 30
diff --git a/arch/arm/boot/compressed/mmcif-sh7372.c b/arch/arm/boot/compressed/mmcif-sh7372.c
deleted file mode 100644
index 672ae95db5c3..000000000000
--- a/arch/arm/boot/compressed/mmcif-sh7372.c
+++ /dev/null
@@ -1,88 +0,0 @@
1/*
2 * sh7372 MMCIF loader
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Simon Horman
6 *
7 * This file is subject to the terms and conditions of the GNU General Public
8 * License. See the file "COPYING" in the main directory of this archive
9 * for more details.
10 */
11
12#include <linux/mmc/sh_mmcif.h>
13#include <linux/mmc/boot.h>
14#include <mach/mmc.h>
15
16#define MMCIF_BASE (void __iomem *)0xe6bd0000
17
18#define PORT84CR (void __iomem *)0xe6050054
19#define PORT85CR (void __iomem *)0xe6050055
20#define PORT86CR (void __iomem *)0xe6050056
21#define PORT87CR (void __iomem *)0xe6050057
22#define PORT88CR (void __iomem *)0xe6050058
23#define PORT89CR (void __iomem *)0xe6050059
24#define PORT90CR (void __iomem *)0xe605005a
25#define PORT91CR (void __iomem *)0xe605005b
26#define PORT92CR (void __iomem *)0xe605005c
27#define PORT99CR (void __iomem *)0xe6050063
28
29#define SMSTPCR3 (void __iomem *)0xe615013c
30
31/* SH7372 specific MMCIF loader
32 *
33 * loads the zImage from an MMC card starting from block 1.
34 *
35 * The image must be start with a vrl4 header and
36 * the zImage must start at offset 512 of the image. That is,
37 * at block 2 (=byte 1024) on the media
38 *
39 * Use the following line to write the vrl4 formated zImage
40 * to an MMC card
41 * # dd if=vrl4.out of=/dev/sdx bs=512 seek=1
42 */
43asmlinkage void mmc_loader(unsigned char *buf, unsigned long len)
44{
45 mmc_init_progress();
46 mmc_update_progress(MMC_PROGRESS_ENTER);
47
48 /* Initialise MMC
49 * registers: PORT84CR-PORT92CR
50 * (MMCD0_0-MMCD0_7,MMCCMD0 Control)
51 * value: 0x04 - select function 4
52 */
53 __raw_writeb(0x04, PORT84CR);
54 __raw_writeb(0x04, PORT85CR);
55 __raw_writeb(0x04, PORT86CR);
56 __raw_writeb(0x04, PORT87CR);
57 __raw_writeb(0x04, PORT88CR);
58 __raw_writeb(0x04, PORT89CR);
59 __raw_writeb(0x04, PORT90CR);
60 __raw_writeb(0x04, PORT91CR);
61 __raw_writeb(0x04, PORT92CR);
62
63 /* Initialise MMC
64 * registers: PORT99CR (MMCCLK0 Control)
65 * value: 0x10 | 0x04 - enable output | select function 4
66 */
67 __raw_writeb(0x14, PORT99CR);
68
69 /* Enable clock to MMC hardware block */
70 __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 12), SMSTPCR3);
71
72 mmc_update_progress(MMC_PROGRESS_INIT);
73
74 /* setup MMCIF hardware */
75 sh_mmcif_boot_init(MMCIF_BASE);
76
77 mmc_update_progress(MMC_PROGRESS_LOAD);
78
79 /* load kernel via MMCIF interface */
80 sh_mmcif_boot_do_read(MMCIF_BASE, 2, /* Kernel is at block 2 */
81 (len + SH_MMCIF_BBS - 1) / SH_MMCIF_BBS, buf);
82
83
84 /* Disable clock to MMC hardware block */
85 __raw_writel(__raw_readl(SMSTPCR3) | (1 << 12), SMSTPCR3);
86
87 mmc_update_progress(MMC_PROGRESS_DONE);
88}
diff --git a/arch/arm/boot/compressed/sdhi-sh7372.c b/arch/arm/boot/compressed/sdhi-sh7372.c
deleted file mode 100644
index d279294f2381..000000000000
--- a/arch/arm/boot/compressed/sdhi-sh7372.c
+++ /dev/null
@@ -1,95 +0,0 @@
1/*
2 * SuperH Mobile SDHI
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Kuninori Morimoto
6 * Copyright (C) 2010 Simon Horman
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 *
12 * Parts inspired by u-boot
13 */
14
15#include <linux/io.h>
16#include <mach/mmc.h>
17#include <linux/mmc/boot.h>
18#include <linux/mmc/tmio.h>
19
20#include "sdhi-shmobile.h"
21
22#define PORT179CR 0xe60520b3
23#define PORT180CR 0xe60520b4
24#define PORT181CR 0xe60520b5
25#define PORT182CR 0xe60520b6
26#define PORT183CR 0xe60520b7
27#define PORT184CR 0xe60520b8
28
29#define SMSTPCR3 0xe615013c
30
31#define CR_INPUT_ENABLE 0x10
32#define CR_FUNCTION1 0x01
33
34#define SDHI1_BASE (void __iomem *)0xe6860000
35#define SDHI_BASE SDHI1_BASE
36
37/* SuperH Mobile SDHI loader
38 *
39 * loads the zImage from an SD card starting from block 0
40 * on physical partition 1
41 *
42 * The image must be start with a vrl4 header and
43 * the zImage must start at offset 512 of the image. That is,
44 * at block 1 (=byte 512) of physical partition 1
45 *
46 * Use the following line to write the vrl4 formated zImage
47 * to an SD card
48 * # dd if=vrl4.out of=/dev/sdx bs=512
49 */
50asmlinkage void mmc_loader(unsigned short *buf, unsigned long len)
51{
52 int high_capacity;
53
54 mmc_init_progress();
55
56 mmc_update_progress(MMC_PROGRESS_ENTER);
57 /* Initialise SDHI1 */
58 /* PORT184CR: GPIO_FN_SDHICMD1 Control */
59 __raw_writeb(CR_FUNCTION1, PORT184CR);
60 /* PORT179CR: GPIO_FN_SDHICLK1 Control */
61 __raw_writeb(CR_INPUT_ENABLE|CR_FUNCTION1, PORT179CR);
62 /* PORT181CR: GPIO_FN_SDHID1_3 Control */
63 __raw_writeb(CR_FUNCTION1, PORT183CR);
64 /* PORT182CR: GPIO_FN_SDHID1_2 Control */
65 __raw_writeb(CR_FUNCTION1, PORT182CR);
66 /* PORT183CR: GPIO_FN_SDHID1_1 Control */
67 __raw_writeb(CR_FUNCTION1, PORT181CR);
68 /* PORT180CR: GPIO_FN_SDHID1_0 Control */
69 __raw_writeb(CR_FUNCTION1, PORT180CR);
70
71 /* Enable clock to SDHI1 hardware block */
72 __raw_writel(__raw_readl(SMSTPCR3) & ~(1 << 13), SMSTPCR3);
73
74 /* setup SDHI hardware */
75 mmc_update_progress(MMC_PROGRESS_INIT);
76 high_capacity = sdhi_boot_init(SDHI_BASE);
77 if (high_capacity < 0)
78 goto err;
79
80 mmc_update_progress(MMC_PROGRESS_LOAD);
81 /* load kernel */
82 if (sdhi_boot_do_read(SDHI_BASE, high_capacity,
83 0, /* Kernel is at block 1 */
84 (len + TMIO_BBS - 1) / TMIO_BBS, buf))
85 goto err;
86
87 /* Disable clock to SDHI1 hardware block */
88 __raw_writel(__raw_readl(SMSTPCR3) | (1 << 13), SMSTPCR3);
89
90 mmc_update_progress(MMC_PROGRESS_DONE);
91
92 return;
93err:
94 for(;;);
95}
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.c b/arch/arm/boot/compressed/sdhi-shmobile.c
deleted file mode 100644
index bd3d46980955..000000000000
--- a/arch/arm/boot/compressed/sdhi-shmobile.c
+++ /dev/null
@@ -1,449 +0,0 @@
1/*
2 * SuperH Mobile SDHI
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2010 Kuninori Morimoto
6 * Copyright (C) 2010 Simon Horman
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 *
12 * Parts inspired by u-boot
13 */
14
15#include <linux/io.h>
16#include <linux/mmc/host.h>
17#include <linux/mmc/core.h>
18#include <linux/mmc/mmc.h>
19#include <linux/mmc/sd.h>
20#include <linux/mmc/tmio.h>
21#include <mach/sdhi.h>
22
23#define OCR_FASTBOOT (1<<29)
24#define OCR_HCS (1<<30)
25#define OCR_BUSY (1<<31)
26
27#define RESP_CMD12 0x00000030
28
29static inline u16 sd_ctrl_read16(void __iomem *base, int addr)
30{
31 return __raw_readw(base + addr);
32}
33
34static inline u32 sd_ctrl_read32(void __iomem *base, int addr)
35{
36 return __raw_readw(base + addr) |
37 __raw_readw(base + addr + 2) << 16;
38}
39
40static inline void sd_ctrl_write16(void __iomem *base, int addr, u16 val)
41{
42 __raw_writew(val, base + addr);
43}
44
45static inline void sd_ctrl_write32(void __iomem *base, int addr, u32 val)
46{
47 __raw_writew(val, base + addr);
48 __raw_writew(val >> 16, base + addr + 2);
49}
50
51#define ALL_ERROR (TMIO_STAT_CMD_IDX_ERR | TMIO_STAT_CRCFAIL | \
52 TMIO_STAT_STOPBIT_ERR | TMIO_STAT_DATATIMEOUT | \
53 TMIO_STAT_RXOVERFLOW | TMIO_STAT_TXUNDERRUN | \
54 TMIO_STAT_CMDTIMEOUT | TMIO_STAT_ILL_ACCESS | \
55 TMIO_STAT_ILL_FUNC)
56
57static int sdhi_intr(void __iomem *base)
58{
59 unsigned long state = sd_ctrl_read32(base, CTL_STATUS);
60
61 if (state & ALL_ERROR) {
62 sd_ctrl_write32(base, CTL_STATUS, ~ALL_ERROR);
63 sd_ctrl_write32(base, CTL_IRQ_MASK,
64 ALL_ERROR |
65 sd_ctrl_read32(base, CTL_IRQ_MASK));
66 return -EINVAL;
67 }
68 if (state & TMIO_STAT_CMDRESPEND) {
69 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
70 sd_ctrl_write32(base, CTL_IRQ_MASK,
71 TMIO_STAT_CMDRESPEND |
72 sd_ctrl_read32(base, CTL_IRQ_MASK));
73 return 0;
74 }
75 if (state & TMIO_STAT_RXRDY) {
76 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_RXRDY);
77 sd_ctrl_write32(base, CTL_IRQ_MASK,
78 TMIO_STAT_RXRDY | TMIO_STAT_TXUNDERRUN |
79 sd_ctrl_read32(base, CTL_IRQ_MASK));
80 return 0;
81 }
82 if (state & TMIO_STAT_DATAEND) {
83 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_DATAEND);
84 sd_ctrl_write32(base, CTL_IRQ_MASK,
85 TMIO_STAT_DATAEND |
86 sd_ctrl_read32(base, CTL_IRQ_MASK));
87 return 0;
88 }
89
90 return -EAGAIN;
91}
92
93static int sdhi_boot_wait_resp_end(void __iomem *base)
94{
95 int err = -EAGAIN, timeout = 10000000;
96
97 while (timeout--) {
98 err = sdhi_intr(base);
99 if (err != -EAGAIN)
100 break;
101 udelay(1);
102 }
103
104 return err;
105}
106
107/* SDHI_CLK_CTRL */
108#define CLK_MMC_ENABLE (1 << 8)
109#define CLK_MMC_INIT (1 << 6) /* clk / 256 */
110
111static void sdhi_boot_mmc_clk_stop(void __iomem *base)
112{
113 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, 0x0000);
114 msleep(10);
115 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, ~CLK_MMC_ENABLE &
116 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
117 msleep(10);
118}
119
120static void sdhi_boot_mmc_clk_start(void __iomem *base)
121{
122 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL, CLK_MMC_ENABLE |
123 sd_ctrl_read16(base, CTL_SD_CARD_CLK_CTL));
124 msleep(10);
125 sd_ctrl_write16(base, CTL_CLK_AND_WAIT_CTL, CLK_MMC_ENABLE);
126 msleep(10);
127}
128
129static void sdhi_boot_reset(void __iomem *base)
130{
131 sd_ctrl_write16(base, CTL_RESET_SD, 0x0000);
132 msleep(10);
133 sd_ctrl_write16(base, CTL_RESET_SD, 0x0001);
134 msleep(10);
135}
136
137/* Set MMC clock / power.
138 * Note: This controller uses a simple divider scheme therefore it cannot
139 * run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
140 * MMC wont run that fast, it has to be clocked at 12MHz which is the next
141 * slowest setting.
142 */
143static int sdhi_boot_mmc_set_ios(void __iomem *base, struct mmc_ios *ios)
144{
145 if (sd_ctrl_read32(base, CTL_STATUS) & TMIO_STAT_CMD_BUSY)
146 return -EBUSY;
147
148 if (ios->clock)
149 sd_ctrl_write16(base, CTL_SD_CARD_CLK_CTL,
150 ios->clock | CLK_MMC_ENABLE);
151
152 /* Power sequence - OFF -> ON -> UP */
153 switch (ios->power_mode) {
154 case MMC_POWER_OFF: /* power down SD bus */
155 sdhi_boot_mmc_clk_stop(base);
156 break;
157 case MMC_POWER_ON: /* power up SD bus */
158 break;
159 case MMC_POWER_UP: /* start bus clock */
160 sdhi_boot_mmc_clk_start(base);
161 break;
162 }
163
164 switch (ios->bus_width) {
165 case MMC_BUS_WIDTH_1:
166 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x80e0);
167 break;
168 case MMC_BUS_WIDTH_4:
169 sd_ctrl_write16(base, CTL_SD_MEM_CARD_OPT, 0x00e0);
170 break;
171 }
172
173 /* Let things settle. delay taken from winCE driver */
174 udelay(140);
175
176 return 0;
177}
178
179/* These are the bitmasks the tmio chip requires to implement the MMC response
180 * types. Note that R1 and R6 are the same in this scheme. */
181#define RESP_NONE 0x0300
182#define RESP_R1 0x0400
183#define RESP_R1B 0x0500
184#define RESP_R2 0x0600
185#define RESP_R3 0x0700
186#define DATA_PRESENT 0x0800
187#define TRANSFER_READ 0x1000
188
189static int sdhi_boot_request(void __iomem *base, struct mmc_command *cmd)
190{
191 int err, c = cmd->opcode;
192
193 switch (mmc_resp_type(cmd)) {
194 case MMC_RSP_NONE: c |= RESP_NONE; break;
195 case MMC_RSP_R1: c |= RESP_R1; break;
196 case MMC_RSP_R1B: c |= RESP_R1B; break;
197 case MMC_RSP_R2: c |= RESP_R2; break;
198 case MMC_RSP_R3: c |= RESP_R3; break;
199 default:
200 return -EINVAL;
201 }
202
203 /* No interrupts so this may not be cleared */
204 sd_ctrl_write32(base, CTL_STATUS, ~TMIO_STAT_CMDRESPEND);
205
206 sd_ctrl_write32(base, CTL_IRQ_MASK, TMIO_STAT_CMDRESPEND |
207 sd_ctrl_read32(base, CTL_IRQ_MASK));
208 sd_ctrl_write32(base, CTL_ARG_REG, cmd->arg);
209 sd_ctrl_write16(base, CTL_SD_CMD, c);
210
211
212 sd_ctrl_write32(base, CTL_IRQ_MASK,
213 ~(TMIO_STAT_CMDRESPEND | ALL_ERROR) &
214 sd_ctrl_read32(base, CTL_IRQ_MASK));
215
216 err = sdhi_boot_wait_resp_end(base);
217 if (err)
218 return err;
219
220 cmd->resp[0] = sd_ctrl_read32(base, CTL_RESPONSE);
221
222 return 0;
223}
224
225static int sdhi_boot_do_read_single(void __iomem *base, int high_capacity,
226 unsigned long block, unsigned short *buf)
227{
228 int err, i;
229
230 /* CMD17 - Read */
231 {
232 struct mmc_command cmd;
233
234 cmd.opcode = MMC_READ_SINGLE_BLOCK | \
235 TRANSFER_READ | DATA_PRESENT;
236 if (high_capacity)
237 cmd.arg = block;
238 else
239 cmd.arg = block * TMIO_BBS;
240 cmd.flags = MMC_RSP_R1;
241 err = sdhi_boot_request(base, &cmd);
242 if (err)
243 return err;
244 }
245
246 sd_ctrl_write32(base, CTL_IRQ_MASK,
247 ~(TMIO_STAT_DATAEND | TMIO_STAT_RXRDY |
248 TMIO_STAT_TXUNDERRUN) &
249 sd_ctrl_read32(base, CTL_IRQ_MASK));
250 err = sdhi_boot_wait_resp_end(base);
251 if (err)
252 return err;
253
254 sd_ctrl_write16(base, CTL_SD_XFER_LEN, TMIO_BBS);
255 for (i = 0; i < TMIO_BBS / sizeof(*buf); i++)
256 *buf++ = sd_ctrl_read16(base, RESP_CMD12);
257
258 err = sdhi_boot_wait_resp_end(base);
259 if (err)
260 return err;
261
262 return 0;
263}
264
265int sdhi_boot_do_read(void __iomem *base, int high_capacity,
266 unsigned long offset, unsigned short count,
267 unsigned short *buf)
268{
269 unsigned long i;
270 int err = 0;
271
272 for (i = 0; i < count; i++) {
273 err = sdhi_boot_do_read_single(base, high_capacity, offset + i,
274 buf + (i * TMIO_BBS /
275 sizeof(*buf)));
276 if (err)
277 return err;
278 }
279
280 return 0;
281}
282
283#define VOLTAGES (MMC_VDD_32_33 | MMC_VDD_33_34)
284
285int sdhi_boot_init(void __iomem *base)
286{
287 bool sd_v2 = false, sd_v1_0 = false;
288 unsigned short cid;
289 int err, high_capacity = 0;
290
291 sdhi_boot_mmc_clk_stop(base);
292 sdhi_boot_reset(base);
293
294 /* mmc0: clock 400000Hz busmode 1 powermode 2 cs 0 Vdd 21 width 0 timing 0 */
295 {
296 struct mmc_ios ios;
297 ios.power_mode = MMC_POWER_ON;
298 ios.bus_width = MMC_BUS_WIDTH_1;
299 ios.clock = CLK_MMC_INIT;
300 err = sdhi_boot_mmc_set_ios(base, &ios);
301 if (err)
302 return err;
303 }
304
305 /* CMD0 */
306 {
307 struct mmc_command cmd;
308 msleep(1);
309 cmd.opcode = MMC_GO_IDLE_STATE;
310 cmd.arg = 0;
311 cmd.flags = MMC_RSP_NONE;
312 err = sdhi_boot_request(base, &cmd);
313 if (err)
314 return err;
315 msleep(2);
316 }
317
318 /* CMD8 - Test for SD version 2 */
319 {
320 struct mmc_command cmd;
321 cmd.opcode = SD_SEND_IF_COND;
322 cmd.arg = (VOLTAGES != 0) << 8 | 0xaa;
323 cmd.flags = MMC_RSP_R1;
324 err = sdhi_boot_request(base, &cmd); /* Ignore error */
325 if ((cmd.resp[0] & 0xff) == 0xaa)
326 sd_v2 = true;
327 }
328
329 /* CMD55 - Get OCR (SD) */
330 {
331 int timeout = 1000;
332 struct mmc_command cmd;
333
334 cmd.arg = 0;
335
336 do {
337 cmd.opcode = MMC_APP_CMD;
338 cmd.flags = MMC_RSP_R1;
339 cmd.arg = 0;
340 err = sdhi_boot_request(base, &cmd);
341 if (err)
342 break;
343
344 cmd.opcode = SD_APP_OP_COND;
345 cmd.flags = MMC_RSP_R3;
346 cmd.arg = (VOLTAGES & 0xff8000);
347 if (sd_v2)
348 cmd.arg |= OCR_HCS;
349 cmd.arg |= OCR_FASTBOOT;
350 err = sdhi_boot_request(base, &cmd);
351 if (err)
352 break;
353
354 msleep(1);
355 } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
356
357 if (!err && timeout) {
358 if (!sd_v2)
359 sd_v1_0 = true;
360 high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
361 }
362 }
363
364 /* CMD1 - Get OCR (MMC) */
365 if (!sd_v2 && !sd_v1_0) {
366 int timeout = 1000;
367 struct mmc_command cmd;
368
369 do {
370 cmd.opcode = MMC_SEND_OP_COND;
371 cmd.arg = VOLTAGES | OCR_HCS;
372 cmd.flags = MMC_RSP_R3;
373 err = sdhi_boot_request(base, &cmd);
374 if (err)
375 return err;
376
377 msleep(1);
378 } while((!(cmd.resp[0] & OCR_BUSY)) && --timeout);
379
380 if (!timeout)
381 return -EAGAIN;
382
383 high_capacity = (cmd.resp[0] & OCR_HCS) == OCR_HCS;
384 }
385
386 /* CMD2 - Get CID */
387 {
388 struct mmc_command cmd;
389 cmd.opcode = MMC_ALL_SEND_CID;
390 cmd.arg = 0;
391 cmd.flags = MMC_RSP_R2;
392 err = sdhi_boot_request(base, &cmd);
393 if (err)
394 return err;
395 }
396
397 /* CMD3
398 * MMC: Set the relative address
399 * SD: Get the relative address
400 * Also puts the card into the standby state
401 */
402 {
403 struct mmc_command cmd;
404 cmd.opcode = MMC_SET_RELATIVE_ADDR;
405 cmd.arg = 0;
406 cmd.flags = MMC_RSP_R1;
407 err = sdhi_boot_request(base, &cmd);
408 if (err)
409 return err;
410 cid = cmd.resp[0] >> 16;
411 }
412
413 /* CMD9 - Get CSD */
414 {
415 struct mmc_command cmd;
416 cmd.opcode = MMC_SEND_CSD;
417 cmd.arg = cid << 16;
418 cmd.flags = MMC_RSP_R2;
419 err = sdhi_boot_request(base, &cmd);
420 if (err)
421 return err;
422 }
423
424 /* CMD7 - Select the card */
425 {
426 struct mmc_command cmd;
427 cmd.opcode = MMC_SELECT_CARD;
428 //cmd.arg = rca << 16;
429 cmd.arg = cid << 16;
430 //cmd.flags = MMC_RSP_R1B;
431 cmd.flags = MMC_RSP_R1;
432 err = sdhi_boot_request(base, &cmd);
433 if (err)
434 return err;
435 }
436
437 /* CMD16 - Set the block size */
438 {
439 struct mmc_command cmd;
440 cmd.opcode = MMC_SET_BLOCKLEN;
441 cmd.arg = TMIO_BBS;
442 cmd.flags = MMC_RSP_R1;
443 err = sdhi_boot_request(base, &cmd);
444 if (err)
445 return err;
446 }
447
448 return high_capacity;
449}
diff --git a/arch/arm/boot/compressed/sdhi-shmobile.h b/arch/arm/boot/compressed/sdhi-shmobile.h
deleted file mode 100644
index 92eaa09f985e..000000000000
--- a/arch/arm/boot/compressed/sdhi-shmobile.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef SDHI_MOBILE_H
2#define SDHI_MOBILE_H
3
4#include <linux/compiler.h>
5
6int sdhi_boot_do_read(void __iomem *base, int high_capacity,
7 unsigned long offset, unsigned short count,
8 unsigned short *buf);
9int sdhi_boot_init(void __iomem *base);
10
11#endif
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 3dbd553361c8..5d258e00c5e7 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -468,7 +468,6 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
468 r8a7778-bockw.dtb \ 468 r8a7778-bockw.dtb \
469 r8a7778-bockw-reference.dtb \ 469 r8a7778-bockw-reference.dtb \
470 r8a7779-marzen.dtb \ 470 r8a7779-marzen.dtb \
471 sh7372-mackerel.dtb \
472 sh73a0-kzm9g.dtb \ 471 sh73a0-kzm9g.dtb \
473 sh73a0-kzm9g-reference.dtb 472 sh73a0-kzm9g-reference.dtb
474dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ 473dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
@@ -476,6 +475,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
476 r7s72100-genmai.dtb \ 475 r7s72100-genmai.dtb \
477 r8a73a4-ape6evm.dtb \ 476 r8a73a4-ape6evm.dtb \
478 r8a7740-armadillo800eva.dtb \ 477 r8a7740-armadillo800eva.dtb \
478 r8a7778-bockw.dtb \
479 r8a7779-marzen.dtb \ 479 r8a7779-marzen.dtb \
480 r8a7790-lager.dtb \ 480 r8a7790-lager.dtb \
481 r8a7791-henninger.dtb \ 481 r8a7791-henninger.dtb \
diff --git a/arch/arm/boot/dts/am335x-bone-common.dtsi b/arch/arm/boot/dts/am335x-bone-common.dtsi
index 6cc25ed912ee..2c6248d9a9ef 100644
--- a/arch/arm/boot/dts/am335x-bone-common.dtsi
+++ b/arch/arm/boot/dts/am335x-bone-common.dtsi
@@ -195,6 +195,7 @@
195 195
196&usb0 { 196&usb0 {
197 status = "okay"; 197 status = "okay";
198 dr_mode = "peripheral";
198}; 199};
199 200
200&usb1 { 201&usb1 {
diff --git a/arch/arm/boot/dts/am437x-idk-evm.dts b/arch/arm/boot/dts/am437x-idk-evm.dts
index f9a17e2ca8cb..0198f5a62b96 100644
--- a/arch/arm/boot/dts/am437x-idk-evm.dts
+++ b/arch/arm/boot/dts/am437x-idk-evm.dts
@@ -133,20 +133,6 @@
133 >; 133 >;
134 }; 134 };
135 135
136 i2c1_pins_default: i2c1_pins_default {
137 pinctrl-single,pins = <
138 0x15c (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_cs0.i2c1_scl */
139 0x158 (PIN_INPUT | SLEWCTRL_FAST | MUX_MODE2) /* spi0_d1.i2c1_sda */
140 >;
141 };
142
143 i2c1_pins_sleep: i2c1_pins_sleep {
144 pinctrl-single,pins = <
145 0x15c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_cs0.i2c1_scl */
146 0x158 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d1.i2c1_sda */
147 >;
148 };
149
150 mmc1_pins_default: pinmux_mmc1_pins_default { 136 mmc1_pins_default: pinmux_mmc1_pins_default {
151 pinctrl-single,pins = < 137 pinctrl-single,pins = <
152 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */ 138 0x100 (PIN_INPUT | MUX_MODE0) /* mmc0_clk.mmc0_clk */
@@ -254,7 +240,7 @@
254 status = "okay"; 240 status = "okay";
255 pinctrl-names = "default", "sleep"; 241 pinctrl-names = "default", "sleep";
256 pinctrl-0 = <&i2c0_pins_default>; 242 pinctrl-0 = <&i2c0_pins_default>;
257 pinctrl-1 = <&i2c0_pins_default>; 243 pinctrl-1 = <&i2c0_pins_sleep>;
258 clock-frequency = <400000>; 244 clock-frequency = <400000>;
259 245
260 at24@50 { 246 at24@50 {
@@ -262,17 +248,10 @@
262 pagesize = <64>; 248 pagesize = <64>;
263 reg = <0x50>; 249 reg = <0x50>;
264 }; 250 };
265};
266
267&i2c1 {
268 status = "okay";
269 pinctrl-names = "default", "sleep";
270 pinctrl-0 = <&i2c1_pins_default>;
271 pinctrl-1 = <&i2c1_pins_default>;
272 clock-frequency = <400000>;
273 251
274 tps: tps62362@60 { 252 tps: tps62362@60 {
275 compatible = "ti,tps62362"; 253 compatible = "ti,tps62362";
254 reg = <0x60>;
276 regulator-name = "VDD_MPU"; 255 regulator-name = "VDD_MPU";
277 regulator-min-microvolt = <950000>; 256 regulator-min-microvolt = <950000>;
278 regulator-max-microvolt = <1330000>; 257 regulator-max-microvolt = <1330000>;
diff --git a/arch/arm/boot/dts/am57xx-beagle-x15.dts b/arch/arm/boot/dts/am57xx-beagle-x15.dts
index 03750af3b49a..6463f9ef2b54 100644
--- a/arch/arm/boot/dts/am57xx-beagle-x15.dts
+++ b/arch/arm/boot/dts/am57xx-beagle-x15.dts
@@ -549,14 +549,6 @@
549 pinctrl-0 = <&usb1_pins>; 549 pinctrl-0 = <&usb1_pins>;
550}; 550};
551 551
552&omap_dwc3_1 {
553 extcon = <&extcon_usb1>;
554};
555
556&omap_dwc3_2 {
557 extcon = <&extcon_usb2>;
558};
559
560&usb2 { 552&usb2 {
561 dr_mode = "peripheral"; 553 dr_mode = "peripheral";
562}; 554};
diff --git a/arch/arm/boot/dts/dm8168-evm.dts b/arch/arm/boot/dts/dm8168-evm.dts
index 857d0289ad4d..d3a29c1b8417 100644
--- a/arch/arm/boot/dts/dm8168-evm.dts
+++ b/arch/arm/boot/dts/dm8168-evm.dts
@@ -35,6 +35,18 @@
35 DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */ 35 DM816X_IOPAD(0x0aac, PIN_INPUT | MUX_MODE0) /* SPI_D1 */
36 >; 36 >;
37 }; 37 };
38
39 usb0_pins: pinmux_usb0_pins {
40 pinctrl-single,pins = <
41 DM816X_IOPAD(0x0d00, MUX_MODE0) /* USB0_DRVVBUS */
42 >;
43 };
44
45 usb1_pins: pinmux_usb0_pins {
46 pinctrl-single,pins = <
47 DM816X_IOPAD(0x0d04, MUX_MODE0) /* USB1_DRVVBUS */
48 >;
49 };
38}; 50};
39 51
40&i2c1 { 52&i2c1 {
@@ -127,3 +139,16 @@
127&mmc1 { 139&mmc1 {
128 vmmc-supply = <&vmmcsd_fixed>; 140 vmmc-supply = <&vmmcsd_fixed>;
129}; 141};
142
143/* At least dm8168-evm rev c won't support multipoint, later may */
144&usb0 {
145 pinctrl-names = "default";
146 pinctrl-0 = <&usb0_pins>;
147 mentor,multipoint = <0>;
148};
149
150&usb1 {
151 pinctrl-names = "default";
152 pinctrl-0 = <&usb1_pins>;
153 mentor,multipoint = <0>;
154};
diff --git a/arch/arm/boot/dts/dm816x.dtsi b/arch/arm/boot/dts/dm816x.dtsi
index d98d0f7de380..3c97b5f2addc 100644
--- a/arch/arm/boot/dts/dm816x.dtsi
+++ b/arch/arm/boot/dts/dm816x.dtsi
@@ -97,10 +97,31 @@
97 97
98 /* Device Configuration Registers */ 98 /* Device Configuration Registers */
99 scm_conf: syscon@600 { 99 scm_conf: syscon@600 {
100 compatible = "syscon"; 100 compatible = "syscon", "simple-bus";
101 reg = <0x600 0x110>; 101 reg = <0x600 0x110>;
102 #address-cells = <1>; 102 #address-cells = <1>;
103 #size-cells = <1>; 103 #size-cells = <1>;
104 ranges = <0 0x600 0x110>;
105
106 usb_phy0: usb-phy@20 {
107 compatible = "ti,dm8168-usb-phy";
108 reg = <0x20 0x8>;
109 reg-names = "phy";
110 clocks = <&main_fapll 6>;
111 clock-names = "refclk";
112 #phy-cells = <0>;
113 syscon = <&scm_conf>;
114 };
115
116 usb_phy1: usb-phy@28 {
117 compatible = "ti,dm8168-usb-phy";
118 reg = <0x28 0x8>;
119 reg-names = "phy";
120 clocks = <&main_fapll 6>;
121 clock-names = "refclk";
122 #phy-cells = <0>;
123 syscon = <&scm_conf>;
124 };
104 }; 125 };
105 126
106 scrm_clocks: clocks { 127 scrm_clocks: clocks {
@@ -357,7 +378,10 @@
357 reg-names = "mc", "control"; 378 reg-names = "mc", "control";
358 interrupts = <18>; 379 interrupts = <18>;
359 interrupt-names = "mc"; 380 interrupt-names = "mc";
360 dr_mode = "otg"; 381 dr_mode = "host";
382 interface-type = <0>;
383 phys = <&usb_phy0>;
384 phy-names = "usb2-phy";
361 mentor,multipoint = <1>; 385 mentor,multipoint = <1>;
362 mentor,num-eps = <16>; 386 mentor,num-eps = <16>;
363 mentor,ram-bits = <12>; 387 mentor,ram-bits = <12>;
@@ -366,13 +390,15 @@
366 390
367 usb1: usb@47401800 { 391 usb1: usb@47401800 {
368 compatible = "ti,musb-am33xx"; 392 compatible = "ti,musb-am33xx";
369 status = "disabled";
370 reg = <0x47401c00 0x400 393 reg = <0x47401c00 0x400
371 0x47401800 0x200>; 394 0x47401800 0x200>;
372 reg-names = "mc", "control"; 395 reg-names = "mc", "control";
373 interrupts = <19>; 396 interrupts = <19>;
374 interrupt-names = "mc"; 397 interrupt-names = "mc";
375 dr_mode = "otg"; 398 dr_mode = "host";
399 interface-type = <0>;
400 phys = <&usb_phy1>;
401 phy-names = "usb2-phy";
376 mentor,multipoint = <1>; 402 mentor,multipoint = <1>;
377 mentor,num-eps = <16>; 403 mentor,num-eps = <16>;
378 mentor,ram-bits = <12>; 404 mentor,ram-bits = <12>;
diff --git a/arch/arm/boot/dts/dra7-evm.dts b/arch/arm/boot/dts/dra7-evm.dts
index 746cddb1b8f5..3290a96ba586 100644
--- a/arch/arm/boot/dts/dra7-evm.dts
+++ b/arch/arm/boot/dts/dra7-evm.dts
@@ -543,14 +543,6 @@
543 }; 543 };
544}; 544};
545 545
546&omap_dwc3_1 {
547 extcon = <&extcon_usb1>;
548};
549
550&omap_dwc3_2 {
551 extcon = <&extcon_usb2>;
552};
553
554&usb1 { 546&usb1 {
555 dr_mode = "peripheral"; 547 dr_mode = "peripheral";
556 pinctrl-names = "default"; 548 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 5827fedafd43..127608d79033 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -249,8 +249,8 @@
249 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 249 <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
250 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 250 <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
251 #dma-cells = <1>; 251 #dma-cells = <1>;
252 #dma-channels = <32>; 252 dma-channels = <32>;
253 #dma-requests = <127>; 253 dma-requests = <127>;
254 }; 254 };
255 255
256 gpio1: gpio@4ae10000 { 256 gpio1: gpio@4ae10000 {
@@ -1090,8 +1090,8 @@
1090 <0x4A096800 0x40>; /* pll_ctrl */ 1090 <0x4A096800 0x40>; /* pll_ctrl */
1091 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 1091 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
1092 ctrl-module = <&omap_control_sata>; 1092 ctrl-module = <&omap_control_sata>;
1093 clocks = <&sys_clkin1>; 1093 clocks = <&sys_clkin1>, <&sata_ref_clk>;
1094 clock-names = "sysclk"; 1094 clock-names = "sysclk", "refclk";
1095 #phy-cells = <0>; 1095 #phy-cells = <0>;
1096 }; 1096 };
1097 1097
diff --git a/arch/arm/boot/dts/dra72-evm.dts b/arch/arm/boot/dts/dra72-evm.dts
index 4d8711713610..e0264d0bf7b9 100644
--- a/arch/arm/boot/dts/dra72-evm.dts
+++ b/arch/arm/boot/dts/dra72-evm.dts
@@ -380,14 +380,6 @@
380 phy-supply = <&ldo4_reg>; 380 phy-supply = <&ldo4_reg>;
381}; 381};
382 382
383&omap_dwc3_1 {
384 extcon = <&extcon_usb1>;
385};
386
387&omap_dwc3_2 {
388 extcon = <&extcon_usb2>;
389};
390
391&usb1 { 383&usb1 {
392 dr_mode = "peripheral"; 384 dr_mode = "peripheral";
393 pinctrl-names = "default"; 385 pinctrl-names = "default";
diff --git a/arch/arm/boot/dts/omap2.dtsi b/arch/arm/boot/dts/omap2.dtsi
index 59d1c297bb30..578fa2a54dce 100644
--- a/arch/arm/boot/dts/omap2.dtsi
+++ b/arch/arm/boot/dts/omap2.dtsi
@@ -87,8 +87,8 @@
87 <14>, 87 <14>,
88 <15>; 88 <15>;
89 #dma-cells = <1>; 89 #dma-cells = <1>;
90 #dma-channels = <32>; 90 dma-channels = <32>;
91 #dma-requests = <64>; 91 dma-requests = <64>;
92 }; 92 };
93 93
94 i2c1: i2c@48070000 { 94 i2c1: i2c@48070000 {
diff --git a/arch/arm/boot/dts/omap3-n900.dts b/arch/arm/boot/dts/omap3-n900.dts
index 60403273f83e..db80f9d376fa 100644
--- a/arch/arm/boot/dts/omap3-n900.dts
+++ b/arch/arm/boot/dts/omap3-n900.dts
@@ -16,6 +16,13 @@
16 model = "Nokia N900"; 16 model = "Nokia N900";
17 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3"; 17 compatible = "nokia,omap3-n900", "ti,omap3430", "ti,omap3";
18 18
19 aliases {
20 i2c0;
21 i2c1 = &i2c1;
22 i2c2 = &i2c2;
23 i2c3 = &i2c3;
24 };
25
19 cpus { 26 cpus {
20 cpu@0 { 27 cpu@0 {
21 cpu0-supply = <&vcc>; 28 cpu0-supply = <&vcc>;
@@ -704,7 +711,7 @@
704 compatible = "smsc,lan91c94"; 711 compatible = "smsc,lan91c94";
705 interrupt-parent = <&gpio2>; 712 interrupt-parent = <&gpio2>;
706 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */ 713 interrupts = <22 IRQ_TYPE_LEVEL_HIGH>; /* gpio54 */
707 reg = <1 0x300 0xf>; /* 16 byte IO range at offset 0x300 */ 714 reg = <1 0 0xf>; /* 16 byte IO range */
708 bank-width = <2>; 715 bank-width = <2>;
709 pinctrl-names = "default"; 716 pinctrl-names = "default";
710 pinctrl-0 = <&ethernet_pins>; 717 pinctrl-0 = <&ethernet_pins>;
diff --git a/arch/arm/boot/dts/omap3.dtsi b/arch/arm/boot/dts/omap3.dtsi
index 01b71111bd55..f4f78c40b564 100644
--- a/arch/arm/boot/dts/omap3.dtsi
+++ b/arch/arm/boot/dts/omap3.dtsi
@@ -155,8 +155,8 @@
155 <14>, 155 <14>,
156 <15>; 156 <15>;
157 #dma-cells = <1>; 157 #dma-cells = <1>;
158 #dma-channels = <32>; 158 dma-channels = <32>;
159 #dma-requests = <96>; 159 dma-requests = <96>;
160 }; 160 };
161 161
162 omap3_pmx_core: pinmux@48002030 { 162 omap3_pmx_core: pinmux@48002030 {
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index 074147cebae4..87401d9f4d8b 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -223,8 +223,8 @@
223 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 223 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 224 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
225 #dma-cells = <1>; 225 #dma-cells = <1>;
226 #dma-channels = <32>; 226 dma-channels = <32>;
227 #dma-requests = <127>; 227 dma-requests = <127>;
228 }; 228 };
229 229
230 gpio1: gpio@4a310000 { 230 gpio1: gpio@4a310000 {
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index b321fdf42c9f..ddff674bd05e 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -238,8 +238,8 @@
238 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 238 <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
239 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 239 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
240 #dma-cells = <1>; 240 #dma-cells = <1>;
241 #dma-channels = <32>; 241 dma-channels = <32>;
242 #dma-requests = <127>; 242 dma-requests = <127>;
243 }; 243 };
244 244
245 gpio1: gpio@4ae10000 { 245 gpio1: gpio@4ae10000 {
@@ -929,8 +929,8 @@
929 <0x4A096800 0x40>; /* pll_ctrl */ 929 <0x4A096800 0x40>; /* pll_ctrl */
930 reg-names = "phy_rx", "phy_tx", "pll_ctrl"; 930 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
931 ctrl-module = <&omap_control_sata>; 931 ctrl-module = <&omap_control_sata>;
932 clocks = <&sys_clkin>; 932 clocks = <&sys_clkin>, <&sata_ref_clk>;
933 clock-names = "sysclk"; 933 clock-names = "sysclk", "refclk";
934 #phy-cells = <0>; 934 #phy-cells = <0>;
935 }; 935 };
936 }; 936 };
diff --git a/arch/arm/boot/dts/r8a7778-bockw.dts b/arch/arm/boot/dts/r8a7778-bockw.dts
index 46a884d45175..787fa6f9f46d 100644
--- a/arch/arm/boot/dts/r8a7778-bockw.dts
+++ b/arch/arm/boot/dts/r8a7778-bockw.dts
@@ -16,17 +16,191 @@
16 16
17/dts-v1/; 17/dts-v1/;
18#include "r8a7778.dtsi" 18#include "r8a7778.dtsi"
19#include <dt-bindings/interrupt-controller/irq.h>
20#include <dt-bindings/gpio/gpio.h>
19 21
20/ { 22/ {
21 model = "bockw"; 23 model = "bockw";
22 compatible = "renesas,bockw", "renesas,r8a7778"; 24 compatible = "renesas,bockw", "renesas,r8a7778";
23 25
26 aliases {
27 serial0 = &scif0;
28 };
29
24 chosen { 30 chosen {
25 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw"; 31 bootargs = "console=ttySC0,115200 ignore_loglevel ip=dhcp root=/dev/nfs rw";
32 stdout-path = &scif0;
26 }; 33 };
27 34
28 memory { 35 memory {
29 device_type = "memory"; 36 device_type = "memory";
30 reg = <0x60000000 0x10000000>; 37 reg = <0x60000000 0x10000000>;
31 }; 38 };
39
40 fixedregulator3v3: fixedregulator@0 {
41 compatible = "regulator-fixed";
42 regulator-name = "fixed-3.3V";
43 regulator-min-microvolt = <3300000>;
44 regulator-max-microvolt = <3300000>;
45 regulator-boot-on;
46 regulator-always-on;
47 };
48
49 sound {
50 compatible = "simple-audio-card";
51
52 simple-audio-card,format = "left_j";
53 simple-audio-card,bitclock-master = <&sndcodec>;
54 simple-audio-card,frame-master = <&sndcodec>;
55
56 sndcpu: simple-audio-card,cpu {
57 sound-dai = <&rcar_sound>;
58 };
59
60 sndcodec: simple-audio-card,codec {
61 sound-dai = <&ak4643>;
62 system-clock-frequency = <11289600>;
63 };
64 };
65};
66
67&bsc {
68 ethernet@18300000 {
69 compatible = "smsc,lan9220", "smsc,lan9115";
70 reg = <0x18300000 0x1000>;
71
72 phy-mode = "mii";
73 interrupt-parent = <&irqpin>;
74 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
75 reg-io-width = <4>;
76 vddvario-supply = <&fixedregulator3v3>;
77 vdd33a-supply = <&fixedregulator3v3>;
78 };
79};
80
81&extal_clk {
82 clock-frequency = <33333333>;
83};
84
85&i2c0 {
86 status = "okay";
87
88 ak4643: sound-codec@12 {
89 compatible = "asahi-kasei,ak4643";
90 #sound-dai-cells = <0>;
91 reg = <0x12>;
92 };
93
94 camera@41 {
95 compatible = "oki,ml86v7667";
96 reg = <0x41>;
97 };
98
99 camera@43 {
100 compatible = "oki,ml86v7667";
101 reg = <0x43>;
102 };
103
104 rx8581: rtc@51 {
105 compatible = "epson,rx8581";
106 reg = <0x51>;
107 };
108};
109
110&mmcif {
111 pinctrl-0 = <&mmc_pins>;
112 pinctrl-names = "default";
113
114 vmmc-supply = <&fixedregulator3v3>;
115 bus-width = <8>;
116 broken-cd;
117 status = "okay";
118};
119
120&irqpin {
121 status = "okay";
122};
123
124&tmu0 {
125 status = "okay";
126};
127
128&pfc {
129 scif0_pins: serial0 {
130 renesas,groups = "scif0_data_a", "scif0_ctrl";
131 renesas,function = "scif0";
132 };
133
134 mmc_pins: mmc {
135 renesas,groups = "mmc_data8", "mmc_ctrl";
136 renesas,function = "mmc";
137 };
138
139 sdhi0_pins: sd0 {
140 renesas,groups = "sdhi0_data4", "sdhi0_ctrl",
141 "sdhi0_cd";
142 renesas,function = "sdhi0";
143 };
144
145 hspi0_pins: hspi0 {
146 renesas,groups = "hspi0_a";
147 renesas,function = "hspi0";
148 };
149
150 usb0_pins: usb0 {
151 renesas,groups = "usb0";
152 renesas,function = "usb0";
153 };
154
155 usb1_pins: usb1 {
156 renesas,groups = "usb1";
157 renesas,function = "usb1";
158 };
159
160 vin0_pins: vin0 {
161 renesas,groups = "vin0_data8", "vin0_clk";
162 renesas,function = "vin0";
163 };
164
165 vin1_pins: vin1 {
166 renesas,groups = "vin1_data8", "vin1_clk";
167 renesas,function = "vin1";
168 };
169};
170
171&sdhi0 {
172 pinctrl-0 = <&sdhi0_pins>;
173 pinctrl-names = "default";
174
175 vmmc-supply = <&fixedregulator3v3>;
176 bus-width = <4>;
177 status = "okay";
178 wp-gpios = <&gpio3 18 GPIO_ACTIVE_HIGH>;
179};
180
181&hspi0 {
182 pinctrl-0 = <&hspi0_pins>;
183 pinctrl-names = "default";
184 status = "okay";
185
186 flash: flash@0 {
187 #address-cells = <1>;
188 #size-cells = <1>;
189 compatible = "spansion,s25fl008k";
190 reg = <0>;
191 spi-max-frequency = <104000000>;
192 m25p,fast-read;
193
194 partition@0 {
195 label = "data(spi)";
196 reg = <0x00000000 0x00100000>;
197 };
198 };
199};
200
201&scif0 {
202 pinctrl-0 = <&scif0_pins>;
203 pinctrl-names = "default";
204
205 status = "okay";
32}; 206};
diff --git a/arch/arm/boot/dts/r8a7778.dtsi b/arch/arm/boot/dts/r8a7778.dtsi
index ef8533910029..868f97309533 100644
--- a/arch/arm/boot/dts/r8a7778.dtsi
+++ b/arch/arm/boot/dts/r8a7778.dtsi
@@ -16,6 +16,7 @@
16 16
17/include/ "skeleton.dtsi" 17/include/ "skeleton.dtsi"
18 18
19#include <dt-bindings/clock/r8a7778-clock.h>
19#include <dt-bindings/interrupt-controller/irq.h> 20#include <dt-bindings/interrupt-controller/irq.h>
20 21
21/ { 22/ {
@@ -40,6 +41,24 @@
40 spi2 = &hspi2; 41 spi2 = &hspi2;
41 }; 42 };
42 43
44 bsc: bus@1c000000 {
45 compatible = "simple-bus";
46 #address-cells = <1>;
47 #size-cells = <1>;
48 ranges = <0 0 0x1c000000>;
49 };
50
51 ether: ethernet@fde00000 {
52 compatible = "renesas,ether-r8a7778";
53 reg = <0xfde00000 0x400>;
54 interrupts = <0 105 IRQ_TYPE_LEVEL_HIGH>;
55 clocks = <&mstp1_clks R8A7778_CLK_ETHER>;
56 phy-mode = "rmii";
57 #address-cells = <1>;
58 #size-cells = <0>;
59 status = "disabled";
60 };
61
43 gic: interrupt-controller@fe438000 { 62 gic: interrupt-controller@fe438000 {
44 compatible = "arm,cortex-a9-gic"; 63 compatible = "arm,cortex-a9-gic";
45 #interrupt-cells = <3>; 64 #interrupt-cells = <3>;
@@ -132,6 +151,7 @@
132 compatible = "renesas,i2c-r8a7778"; 151 compatible = "renesas,i2c-r8a7778";
133 reg = <0xffc70000 0x1000>; 152 reg = <0xffc70000 0x1000>;
134 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; 153 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&mstp0_clks R8A7778_CLK_I2C0>;
135 status = "disabled"; 155 status = "disabled";
136 }; 156 };
137 157
@@ -141,6 +161,7 @@
141 compatible = "renesas,i2c-r8a7778"; 161 compatible = "renesas,i2c-r8a7778";
142 reg = <0xffc71000 0x1000>; 162 reg = <0xffc71000 0x1000>;
143 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 163 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
164 clocks = <&mstp0_clks R8A7778_CLK_I2C1>;
144 status = "disabled"; 165 status = "disabled";
145 }; 166 };
146 167
@@ -150,6 +171,7 @@
150 compatible = "renesas,i2c-r8a7778"; 171 compatible = "renesas,i2c-r8a7778";
151 reg = <0xffc72000 0x1000>; 172 reg = <0xffc72000 0x1000>;
152 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>; 173 interrupts = <0 76 IRQ_TYPE_LEVEL_HIGH>;
174 clocks = <&mstp0_clks R8A7778_CLK_I2C2>;
153 status = "disabled"; 175 status = "disabled";
154 }; 176 };
155 177
@@ -159,6 +181,7 @@
159 compatible = "renesas,i2c-r8a7778"; 181 compatible = "renesas,i2c-r8a7778";
160 reg = <0xffc73000 0x1000>; 182 reg = <0xffc73000 0x1000>;
161 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>; 183 interrupts = <0 77 IRQ_TYPE_LEVEL_HIGH>;
184 clocks = <&mstp0_clks R8A7778_CLK_I2C3>;
162 status = "disabled"; 185 status = "disabled";
163 }; 186 };
164 187
@@ -168,6 +191,8 @@
168 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>, 191 interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>,
169 <0 33 IRQ_TYPE_LEVEL_HIGH>, 192 <0 33 IRQ_TYPE_LEVEL_HIGH>,
170 <0 34 IRQ_TYPE_LEVEL_HIGH>; 193 <0 34 IRQ_TYPE_LEVEL_HIGH>;
194 clocks = <&mstp0_clks R8A7778_CLK_TMU0>;
195 clock-names = "fck";
171 196
172 #renesas,channels = <3>; 197 #renesas,channels = <3>;
173 198
@@ -180,6 +205,8 @@
180 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>, 205 interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>,
181 <0 37 IRQ_TYPE_LEVEL_HIGH>, 206 <0 37 IRQ_TYPE_LEVEL_HIGH>,
182 <0 38 IRQ_TYPE_LEVEL_HIGH>; 207 <0 38 IRQ_TYPE_LEVEL_HIGH>;
208 clocks = <&mstp0_clks R8A7778_CLK_TMU1>;
209 clock-names = "fck";
183 210
184 #renesas,channels = <3>; 211 #renesas,channels = <3>;
185 212
@@ -192,16 +219,75 @@
192 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>, 219 interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>,
193 <0 41 IRQ_TYPE_LEVEL_HIGH>, 220 <0 41 IRQ_TYPE_LEVEL_HIGH>,
194 <0 42 IRQ_TYPE_LEVEL_HIGH>; 221 <0 42 IRQ_TYPE_LEVEL_HIGH>;
222 clocks = <&mstp0_clks R8A7778_CLK_TMU2>;
223 clock-names = "fck";
195 224
196 #renesas,channels = <3>; 225 #renesas,channels = <3>;
197 226
198 status = "disabled"; 227 status = "disabled";
199 }; 228 };
200 229
230 rcar_sound: sound@ffd90000 {
231 #sound-dai-cells = <1>;
232 compatible = "renesas,rcar_sound-r8a7778", "renesas,rcar_sound-gen1";
233 reg = <0xffd90000 0x1000>, /* SRU */
234 <0xffd91000 0x1240>, /* SSI */
235 <0xfffe0000 0x24>; /* ADG */
236 clocks = <&mstp3_clks R8A7778_CLK_SSI8>,
237 <&mstp3_clks R8A7778_CLK_SSI7>,
238 <&mstp3_clks R8A7778_CLK_SSI6>,
239 <&mstp3_clks R8A7778_CLK_SSI5>,
240 <&mstp3_clks R8A7778_CLK_SSI4>,
241 <&mstp0_clks R8A7778_CLK_SSI3>,
242 <&mstp0_clks R8A7778_CLK_SSI2>,
243 <&mstp0_clks R8A7778_CLK_SSI1>,
244 <&mstp0_clks R8A7778_CLK_SSI0>,
245 <&mstp5_clks R8A7778_CLK_SRU_SRC8>,
246 <&mstp5_clks R8A7778_CLK_SRU_SRC7>,
247 <&mstp5_clks R8A7778_CLK_SRU_SRC6>,
248 <&mstp5_clks R8A7778_CLK_SRU_SRC5>,
249 <&mstp5_clks R8A7778_CLK_SRU_SRC4>,
250 <&mstp5_clks R8A7778_CLK_SRU_SRC3>,
251 <&mstp5_clks R8A7778_CLK_SRU_SRC2>,
252 <&mstp5_clks R8A7778_CLK_SRU_SRC1>,
253 <&mstp5_clks R8A7778_CLK_SRU_SRC0>,
254 <&audio_clk_a>, <&audio_clk_b>, <&audio_clk_c>,
255 <&cpg_clocks R8A7778_CLK_S1>;
256 clock-names = "ssi.8", "ssi.7", "ssi.6", "ssi.5", "ssi.4",
257 "ssi.3", "ssi.2", "ssi.1", "ssi.0",
258 "src.8", "src.7", "src.6", "src.5", "src.4",
259 "src.3", "src.2", "src.1", "src.0",
260 "clk_a", "clk_b", "clk_c", "clk_i";
261
262 status = "disabled";
263
264 rcar_sound,src {
265 src3: src@3 { };
266 src4: src@4 { };
267 src5: src@5 { };
268 src6: src@6 { };
269 src7: src@7 { };
270 src8: src@8 { };
271 src9: src@9 { };
272 };
273
274 rcar_sound,ssi {
275 ssi3: ssi@3 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
276 ssi4: ssi@4 { interrupts = <0 0x85 IRQ_TYPE_LEVEL_HIGH>; };
277 ssi5: ssi@5 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
278 ssi6: ssi@6 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
279 ssi7: ssi@7 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
280 ssi8: ssi@8 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
281 ssi9: ssi@9 { interrupts = <0 0x86 IRQ_TYPE_LEVEL_HIGH>; };
282 };
283 };
284
201 scif0: serial@ffe40000 { 285 scif0: serial@ffe40000 {
202 compatible = "renesas,scif-r8a7778", "renesas,scif"; 286 compatible = "renesas,scif-r8a7778", "renesas,scif";
203 reg = <0xffe40000 0x100>; 287 reg = <0xffe40000 0x100>;
204 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>; 288 interrupts = <0 70 IRQ_TYPE_LEVEL_HIGH>;
289 clocks = <&mstp0_clks R8A7778_CLK_SCIF0>;
290 clock-names = "sci_ick";
205 status = "disabled"; 291 status = "disabled";
206 }; 292 };
207 293
@@ -209,6 +295,8 @@
209 compatible = "renesas,scif-r8a7778", "renesas,scif"; 295 compatible = "renesas,scif-r8a7778", "renesas,scif";
210 reg = <0xffe41000 0x100>; 296 reg = <0xffe41000 0x100>;
211 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>; 297 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>;
298 clocks = <&mstp0_clks R8A7778_CLK_SCIF1>;
299 clock-names = "sci_ick";
212 status = "disabled"; 300 status = "disabled";
213 }; 301 };
214 302
@@ -216,6 +304,8 @@
216 compatible = "renesas,scif-r8a7778", "renesas,scif"; 304 compatible = "renesas,scif-r8a7778", "renesas,scif";
217 reg = <0xffe42000 0x100>; 305 reg = <0xffe42000 0x100>;
218 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 306 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
307 clocks = <&mstp0_clks R8A7778_CLK_SCIF2>;
308 clock-names = "sci_ick";
219 status = "disabled"; 309 status = "disabled";
220 }; 310 };
221 311
@@ -223,6 +313,8 @@
223 compatible = "renesas,scif-r8a7778", "renesas,scif"; 313 compatible = "renesas,scif-r8a7778", "renesas,scif";
224 reg = <0xffe43000 0x100>; 314 reg = <0xffe43000 0x100>;
225 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 315 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
316 clocks = <&mstp0_clks R8A7778_CLK_SCIF3>;
317 clock-names = "sci_ick";
226 status = "disabled"; 318 status = "disabled";
227 }; 319 };
228 320
@@ -230,6 +322,8 @@
230 compatible = "renesas,scif-r8a7778", "renesas,scif"; 322 compatible = "renesas,scif-r8a7778", "renesas,scif";
231 reg = <0xffe44000 0x100>; 323 reg = <0xffe44000 0x100>;
232 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 324 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
325 clocks = <&mstp0_clks R8A7778_CLK_SCIF4>;
326 clock-names = "sci_ick";
233 status = "disabled"; 327 status = "disabled";
234 }; 328 };
235 329
@@ -237,6 +331,8 @@
237 compatible = "renesas,scif-r8a7778", "renesas,scif"; 331 compatible = "renesas,scif-r8a7778", "renesas,scif";
238 reg = <0xffe45000 0x100>; 332 reg = <0xffe45000 0x100>;
239 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 333 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
334 clocks = <&mstp0_clks R8A7778_CLK_SCIF5>;
335 clock-names = "sci_ick";
240 status = "disabled"; 336 status = "disabled";
241 }; 337 };
242 338
@@ -244,6 +340,7 @@
244 compatible = "renesas,sh-mmcif"; 340 compatible = "renesas,sh-mmcif";
245 reg = <0xffe4e000 0x100>; 341 reg = <0xffe4e000 0x100>;
246 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>; 342 interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&mstp3_clks R8A7778_CLK_MMC>;
247 status = "disabled"; 344 status = "disabled";
248 }; 345 };
249 346
@@ -251,6 +348,7 @@
251 compatible = "renesas,sdhi-r8a7778"; 348 compatible = "renesas,sdhi-r8a7778";
252 reg = <0xffe4c000 0x100>; 349 reg = <0xffe4c000 0x100>;
253 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>; 350 interrupts = <0 87 IRQ_TYPE_LEVEL_HIGH>;
351 clocks = <&mstp3_clks R8A7778_CLK_SDHI0>;
254 status = "disabled"; 352 status = "disabled";
255 }; 353 };
256 354
@@ -258,6 +356,7 @@
258 compatible = "renesas,sdhi-r8a7778"; 356 compatible = "renesas,sdhi-r8a7778";
259 reg = <0xffe4d000 0x100>; 357 reg = <0xffe4d000 0x100>;
260 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>; 358 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH>;
359 clocks = <&mstp3_clks R8A7778_CLK_SDHI1>;
261 status = "disabled"; 360 status = "disabled";
262 }; 361 };
263 362
@@ -265,6 +364,7 @@
265 compatible = "renesas,sdhi-r8a7778"; 364 compatible = "renesas,sdhi-r8a7778";
266 reg = <0xffe4f000 0x100>; 365 reg = <0xffe4f000 0x100>;
267 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; 366 interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
367 clocks = <&mstp3_clks R8A7778_CLK_SDHI2>;
268 status = "disabled"; 368 status = "disabled";
269 }; 369 };
270 370
@@ -272,6 +372,7 @@
272 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 372 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
273 reg = <0xfffc7000 0x18>; 373 reg = <0xfffc7000 0x18>;
274 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>; 374 interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
375 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
275 #address-cells = <1>; 376 #address-cells = <1>;
276 #size-cells = <0>; 377 #size-cells = <0>;
277 status = "disabled"; 378 status = "disabled";
@@ -281,6 +382,7 @@
281 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 382 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
282 reg = <0xfffc8000 0x18>; 383 reg = <0xfffc8000 0x18>;
283 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>; 384 interrupts = <0 84 IRQ_TYPE_LEVEL_HIGH>;
385 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
284 #address-cells = <1>; 386 #address-cells = <1>;
285 #size-cells = <0>; 387 #size-cells = <0>;
286 status = "disabled"; 388 status = "disabled";
@@ -290,8 +392,199 @@
290 compatible = "renesas,hspi-r8a7778", "renesas,hspi"; 392 compatible = "renesas,hspi-r8a7778", "renesas,hspi";
291 reg = <0xfffc6000 0x18>; 393 reg = <0xfffc6000 0x18>;
292 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>; 394 interrupts = <0 85 IRQ_TYPE_LEVEL_HIGH>;
395 clocks = <&mstp0_clks R8A7778_CLK_HSPI>;
293 #address-cells = <1>; 396 #address-cells = <1>;
294 #size-cells = <0>; 397 #size-cells = <0>;
295 status = "disabled"; 398 status = "disabled";
296 }; 399 };
400
401 clocks {
402 #address-cells = <1>;
403 #size-cells = <1>;
404 ranges;
405
406 /* External input clock */
407 extal_clk: extal_clk {
408 compatible = "fixed-clock";
409 #clock-cells = <0>;
410 clock-frequency = <0>;
411 clock-output-names = "extal";
412 };
413
414 /* Special CPG clocks */
415 cpg_clocks: cpg_clocks@ffc80000 {
416 compatible = "renesas,r8a7778-cpg-clocks";
417 reg = <0xffc80000 0x80>;
418 #clock-cells = <1>;
419 clocks = <&extal_clk>;
420 clock-output-names = "plla", "pllb", "b",
421 "out", "p", "s", "s1";
422 };
423
424 /* Audio clocks; frequencies are set by boards if applicable. */
425 audio_clk_a: audio_clk_a {
426 compatible = "fixed-clock";
427 #clock-cells = <0>;
428 clock-output-names = "audio_clk_a";
429 };
430 audio_clk_b: audio_clk_b {
431 compatible = "fixed-clock";
432 #clock-cells = <0>;
433 clock-output-names = "audio_clk_b";
434 };
435 audio_clk_c: audio_clk_c {
436 compatible = "fixed-clock";
437 #clock-cells = <0>;
438 clock-output-names = "audio_clk_c";
439 };
440
441 /* Fixed ratio clocks */
442 g_clk: g_clk {
443 compatible = "fixed-factor-clock";
444 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
445 #clock-cells = <0>;
446 clock-div = <12>;
447 clock-mult = <1>;
448 clock-output-names = "g";
449 };
450 i_clk: i_clk {
451 compatible = "fixed-factor-clock";
452 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
453 #clock-cells = <0>;
454 clock-div = <1>;
455 clock-mult = <1>;
456 clock-output-names = "i";
457 };
458 s3_clk: s3_clk {
459 compatible = "fixed-factor-clock";
460 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
461 #clock-cells = <0>;
462 clock-div = <4>;
463 clock-mult = <1>;
464 clock-output-names = "s3";
465 };
466 s4_clk: s4_clk {
467 compatible = "fixed-factor-clock";
468 clocks = <&cpg_clocks R8A7778_CLK_PLLA>;
469 #clock-cells = <0>;
470 clock-div = <8>;
471 clock-mult = <1>;
472 clock-output-names = "s4";
473 };
474 z_clk: z_clk {
475 compatible = "fixed-factor-clock";
476 clocks = <&cpg_clocks R8A7778_CLK_PLLB>;
477 #clock-cells = <0>;
478 clock-div = <1>;
479 clock-mult = <1>;
480 clock-output-names = "z";
481 };
482
483 /* Gate clocks */
484 mstp0_clks: mstp0_clks@ffc80030 {
485 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
486 reg = <0xffc80030 4>;
487 clocks = <&cpg_clocks R8A7778_CLK_P>,
488 <&cpg_clocks R8A7778_CLK_P>,
489 <&cpg_clocks R8A7778_CLK_P>,
490 <&cpg_clocks R8A7778_CLK_P>,
491 <&cpg_clocks R8A7778_CLK_P>,
492 <&cpg_clocks R8A7778_CLK_P>,
493 <&cpg_clocks R8A7778_CLK_P>,
494 <&cpg_clocks R8A7778_CLK_P>,
495 <&cpg_clocks R8A7778_CLK_P>,
496 <&cpg_clocks R8A7778_CLK_P>,
497 <&cpg_clocks R8A7778_CLK_P>,
498 <&cpg_clocks R8A7778_CLK_P>,
499 <&cpg_clocks R8A7778_CLK_P>,
500 <&cpg_clocks R8A7778_CLK_P>,
501 <&cpg_clocks R8A7778_CLK_P>,
502 <&cpg_clocks R8A7778_CLK_P>,
503 <&cpg_clocks R8A7778_CLK_P>,
504 <&cpg_clocks R8A7778_CLK_P>,
505 <&cpg_clocks R8A7778_CLK_S>;
506 #clock-cells = <1>;
507 clock-indices = <
508 R8A7778_CLK_I2C0 R8A7778_CLK_I2C1
509 R8A7778_CLK_I2C2 R8A7778_CLK_I2C3
510 R8A7778_CLK_SCIF0 R8A7778_CLK_SCIF1
511 R8A7778_CLK_SCIF2 R8A7778_CLK_SCIF3
512 R8A7778_CLK_SCIF4 R8A7778_CLK_SCIF5
513 R8A7778_CLK_TMU0 R8A7778_CLK_TMU1
514 R8A7778_CLK_TMU2 R8A7778_CLK_SSI0
515 R8A7778_CLK_SSI1 R8A7778_CLK_SSI2
516 R8A7778_CLK_SSI3 R8A7778_CLK_SRU
517 R8A7778_CLK_HSPI
518 >;
519 clock-output-names =
520 "i2c0", "i2c1", "i2c2", "i2c3", "scif0",
521 "scif1", "scif2", "scif3", "scif4", "scif5",
522 "tmu0", "tmu1", "tmu2", "ssi0", "ssi1",
523 "ssi2", "ssi3", "sru", "hspi";
524 };
525 mstp1_clks: mstp1_clks@ffc80034 {
526 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
527 reg = <0xffc80034 4>, <0xffc80044 4>;
528 clocks = <&cpg_clocks R8A7778_CLK_P>,
529 <&cpg_clocks R8A7778_CLK_S>,
530 <&cpg_clocks R8A7778_CLK_S>,
531 <&cpg_clocks R8A7778_CLK_P>;
532 #clock-cells = <1>;
533 clock-indices = <
534 R8A7778_CLK_ETHER R8A7778_CLK_VIN0
535 R8A7778_CLK_VIN1 R8A7778_CLK_USB
536 >;
537 clock-output-names =
538 "ether", "vin0", "vin1", "usb";
539 };
540 mstp3_clks: mstp3_clks@ffc8003c {
541 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
542 reg = <0xffc8003c 4>;
543 clocks = <&s4_clk>,
544 <&cpg_clocks R8A7778_CLK_P>,
545 <&cpg_clocks R8A7778_CLK_P>,
546 <&cpg_clocks R8A7778_CLK_P>,
547 <&cpg_clocks R8A7778_CLK_P>,
548 <&cpg_clocks R8A7778_CLK_P>,
549 <&cpg_clocks R8A7778_CLK_P>,
550 <&cpg_clocks R8A7778_CLK_P>,
551 <&cpg_clocks R8A7778_CLK_P>;
552 #clock-cells = <1>;
553 clock-indices = <
554 R8A7778_CLK_MMC R8A7778_CLK_SDHI0
555 R8A7778_CLK_SDHI1 R8A7778_CLK_SDHI2
556 R8A7778_CLK_SSI4 R8A7778_CLK_SSI5
557 R8A7778_CLK_SSI6 R8A7778_CLK_SSI7
558 R8A7778_CLK_SSI8
559 >;
560 clock-output-names =
561 "mmc", "sdhi0", "sdhi1", "sdhi2", "ssi4",
562 "ssi5", "ssi6", "ssi7", "ssi8";
563 };
564 mstp5_clks: mstp5_clks@ffc80054 {
565 compatible = "renesas,r8a7778-mstp-clocks", "renesas,cpg-mstp-clocks";
566 reg = <0xffc80054 4>;
567 clocks = <&cpg_clocks R8A7778_CLK_P>,
568 <&cpg_clocks R8A7778_CLK_P>,
569 <&cpg_clocks R8A7778_CLK_P>,
570 <&cpg_clocks R8A7778_CLK_P>,
571 <&cpg_clocks R8A7778_CLK_P>,
572 <&cpg_clocks R8A7778_CLK_P>,
573 <&cpg_clocks R8A7778_CLK_P>,
574 <&cpg_clocks R8A7778_CLK_P>,
575 <&cpg_clocks R8A7778_CLK_P>;
576 #clock-cells = <1>;
577 clock-indices = <
578 R8A7778_CLK_SRU_SRC0 R8A7778_CLK_SRU_SRC1
579 R8A7778_CLK_SRU_SRC2 R8A7778_CLK_SRU_SRC3
580 R8A7778_CLK_SRU_SRC4 R8A7778_CLK_SRU_SRC5
581 R8A7778_CLK_SRU_SRC6 R8A7778_CLK_SRU_SRC7
582 R8A7778_CLK_SRU_SRC8
583 >;
584 clock-output-names =
585 "sru-src0", "sru-src1", "sru-src2",
586 "sru-src3", "sru-src4", "sru-src5",
587 "sru-src6", "sru-src7", "sru-src8";
588 };
589 };
297}; 590};
diff --git a/arch/arm/boot/dts/sh7372-mackerel.dts b/arch/arm/boot/dts/sh7372-mackerel.dts
deleted file mode 100644
index a759a276c9a9..000000000000
--- a/arch/arm/boot/dts/sh7372-mackerel.dts
+++ /dev/null
@@ -1,26 +0,0 @@
1/*
2 * Device Tree Source for the mackerel board
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/dts-v1/;
12#include "sh7372.dtsi"
13
14/ {
15 model = "Mackerel (AP4 EVM 2nd)";
16 compatible = "renesas,mackerel";
17
18 chosen {
19 bootargs = "console=tty0, console=ttySC0,115200 earlyprintk=sh-sci.0,115200 root=/dev/nfs nfsroot=,tcp,v3 ip=dhcp mem=240m rw";
20 };
21
22 memory {
23 device_type = "memory";
24 reg = <0x40000000 0x10000000>;
25 };
26};
diff --git a/arch/arm/boot/dts/sh7372.dtsi b/arch/arm/boot/dts/sh7372.dtsi
deleted file mode 100644
index f863a10cb1b2..000000000000
--- a/arch/arm/boot/dts/sh7372.dtsi
+++ /dev/null
@@ -1,35 +0,0 @@
1/*
2 * Device Tree Source for the sh7372 SoC
3 *
4 * Copyright (C) 2012 Renesas Solutions Corp.
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 compatible = "renesas,sh7372";
15
16 cpus {
17 #address-cells = <1>;
18 #size-cells = <0>;
19
20 cpu@0 {
21 compatible = "arm,cortex-a8";
22 device_type = "cpu";
23 reg = <0x0>;
24 clock-frequency = <800000000>;
25 };
26 };
27
28 pfc: pfc@e6050000 {
29 compatible = "renesas,pfc-sh7372";
30 reg = <0xe6050000 0x8000>,
31 <0xe605801c 0x1c>;
32 gpio-controller;
33 #gpio-cells = <2>;
34 };
35};
diff --git a/arch/arm/configs/mackerel_defconfig b/arch/arm/configs/mackerel_defconfig
deleted file mode 100644
index 05a529311b4d..000000000000
--- a/arch/arm/configs/mackerel_defconfig
+++ /dev/null
@@ -1,157 +0,0 @@
1CONFIG_EXPERIMENTAL=y
2CONFIG_SYSVIPC=y
3CONFIG_IKCONFIG=y
4CONFIG_IKCONFIG_PROC=y
5CONFIG_LOG_BUF_SHIFT=16
6# CONFIG_UTS_NS is not set
7# CONFIG_IPC_NS is not set
8# CONFIG_USER_NS is not set
9# CONFIG_PID_NS is not set
10# CONFIG_NET_NS is not set
11CONFIG_SLAB=y
12CONFIG_MODULES=y
13CONFIG_MODULE_UNLOAD=y
14# CONFIG_BLK_DEV_BSG is not set
15# CONFIG_IOSCHED_DEADLINE is not set
16# CONFIG_IOSCHED_CFQ is not set
17CONFIG_ARCH_SHMOBILE_LEGACY=y
18CONFIG_ARCH_SH7372=y
19CONFIG_MACH_MACKEREL=y
20CONFIG_MEMORY_SIZE=0x10000000
21CONFIG_AEABI=y
22# CONFIG_OABI_COMPAT is not set
23CONFIG_FORCE_MAX_ZONEORDER=15
24CONFIG_ZBOOT_ROM_TEXT=0x0
25CONFIG_ZBOOT_ROM_BSS=0x0
26CONFIG_ARM_APPENDED_DTB=y
27CONFIG_KEXEC=y
28CONFIG_VFP=y
29# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
30CONFIG_PM=y
31CONFIG_NET=y
32CONFIG_PACKET=y
33CONFIG_UNIX=y
34CONFIG_INET=y
35CONFIG_IP_MULTICAST=y
36CONFIG_IP_PNP=y
37CONFIG_IP_PNP_DHCP=y
38# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
39# CONFIG_INET_XFRM_MODE_TUNNEL is not set
40# CONFIG_INET_XFRM_MODE_BEET is not set
41# CONFIG_IPV6 is not set
42# CONFIG_WIRELESS is not set
43CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
44CONFIG_DEVTMPFS=y
45CONFIG_DEVTMPFS_MOUNT=y
46# CONFIG_FIRMWARE_IN_KERNEL is not set
47CONFIG_MTD=y
48CONFIG_MTD_CONCAT=y
49CONFIG_MTD_PARTITIONS=y
50CONFIG_MTD_CHAR=y
51CONFIG_MTD_BLOCK=y
52CONFIG_MTD_CFI=y
53CONFIG_MTD_CFI_ADV_OPTIONS=y
54CONFIG_MTD_CFI_INTELEXT=y
55CONFIG_MTD_PHYSMAP=y
56CONFIG_MTD_ARM_INTEGRATOR=y
57CONFIG_MTD_BLOCK2MTD=y
58CONFIG_SCSI=y
59CONFIG_BLK_DEV_SD=y
60# CONFIG_SCSI_LOWLEVEL is not set
61CONFIG_NETDEVICES=y
62CONFIG_NET_ETHERNET=y
63CONFIG_SMSC911X=y
64# CONFIG_NETDEV_1000 is not set
65# CONFIG_NETDEV_10000 is not set
66# CONFIG_WLAN is not set
67# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
68# CONFIG_INPUT_KEYBOARD is not set
69# CONFIG_INPUT_MOUSE is not set
70CONFIG_SERIAL_SH_SCI=y
71CONFIG_SERIAL_SH_SCI_NR_UARTS=8
72CONFIG_SERIAL_SH_SCI_CONSOLE=y
73# CONFIG_LEGACY_PTYS is not set
74# CONFIG_HW_RANDOM is not set
75CONFIG_I2C=y
76CONFIG_I2C_SH_MOBILE=y
77# CONFIG_HWMON is not set
78# CONFIG_MFD_SUPPORT is not set
79CONFIG_REGULATOR=y
80CONFIG_FB=y
81CONFIG_FB_MODE_HELPERS=y
82CONFIG_FB_SH_MOBILE_LCDC=y
83CONFIG_FB_SH_MOBILE_HDMI=y
84CONFIG_FRAMEBUFFER_CONSOLE=y
85CONFIG_LOGO=y
86# CONFIG_LOGO_LINUX_MONO is not set
87# CONFIG_LOGO_LINUX_CLUT224 is not set
88# CONFIG_SND_SUPPORT_OLD_API is not set
89# CONFIG_SND_VERBOSE_PROCFS is not set
90# CONFIG_SND_DRIVERS is not set
91# CONFIG_SND_ARM is not set
92CONFIG_SND_SOC_SH4_FSI=y
93CONFIG_USB=y
94CONFIG_USB_RENESAS_USBHS_HCD=y
95CONFIG_USB_RENESAS_USBHS=y
96CONFIG_USB_STORAGE=y
97CONFIG_USB_GADGET=y
98CONFIG_USB_RENESAS_USBHS_UDC=y
99CONFIG_MMC=y
100CONFIG_MMC_SDHI=y
101CONFIG_MMC_SH_MMCIF=y
102CONFIG_DMADEVICES=y
103CONFIG_SH_DMAE=y
104CONFIG_EXT2_FS=y
105CONFIG_EXT2_FS_XATTR=y
106CONFIG_EXT2_FS_POSIX_ACL=y
107CONFIG_EXT2_FS_SECURITY=y
108CONFIG_EXT2_FS_XIP=y
109CONFIG_EXT3_FS=y
110# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
111CONFIG_EXT3_FS_POSIX_ACL=y
112CONFIG_EXT3_FS_SECURITY=y
113# CONFIG_DNOTIFY is not set
114CONFIG_MSDOS_FS=y
115CONFIG_VFAT_FS=y
116CONFIG_TMPFS=y
117# CONFIG_MISC_FILESYSTEMS is not set
118CONFIG_NFS_FS=y
119CONFIG_NFS_V3=y
120CONFIG_NFS_V3_ACL=y
121CONFIG_NFS_V4=y
122CONFIG_NFS_V4_1=y
123CONFIG_ROOT_NFS=y
124CONFIG_NLS_CODEPAGE_437=y
125CONFIG_NLS_CODEPAGE_737=y
126CONFIG_NLS_CODEPAGE_775=y
127CONFIG_NLS_CODEPAGE_850=y
128CONFIG_NLS_CODEPAGE_852=y
129CONFIG_NLS_CODEPAGE_855=y
130CONFIG_NLS_CODEPAGE_857=y
131CONFIG_NLS_CODEPAGE_860=y
132CONFIG_NLS_CODEPAGE_861=y
133CONFIG_NLS_CODEPAGE_862=y
134CONFIG_NLS_CODEPAGE_863=y
135CONFIG_NLS_CODEPAGE_864=y
136CONFIG_NLS_CODEPAGE_865=y
137CONFIG_NLS_CODEPAGE_866=y
138CONFIG_NLS_CODEPAGE_869=y
139CONFIG_NLS_ISO8859_1=y
140CONFIG_NLS_ISO8859_2=y
141CONFIG_NLS_ISO8859_3=y
142CONFIG_NLS_ISO8859_4=y
143CONFIG_NLS_ISO8859_5=y
144CONFIG_NLS_ISO8859_6=y
145CONFIG_NLS_ISO8859_7=y
146CONFIG_NLS_ISO8859_9=y
147CONFIG_NLS_ISO8859_13=y
148CONFIG_NLS_ISO8859_14=y
149CONFIG_NLS_ISO8859_15=y
150CONFIG_NLS_KOI8_R=y
151CONFIG_NLS_KOI8_U=y
152CONFIG_NLS_UTF8=y
153# CONFIG_ENABLE_WARN_DEPRECATED is not set
154# CONFIG_ENABLE_MUST_CHECK is not set
155# CONFIG_ARM_UNWIND is not set
156CONFIG_CRYPTO=y
157CONFIG_CRYPTO_ANSI_CPRNG=y
diff --git a/arch/arm/configs/multi_v7_defconfig b/arch/arm/configs/multi_v7_defconfig
index e8a4c955241b..b7e6b6fba5e0 100644
--- a/arch/arm/configs/multi_v7_defconfig
+++ b/arch/arm/configs/multi_v7_defconfig
@@ -62,6 +62,17 @@ CONFIG_MACH_SPEAR1340=y
62CONFIG_ARCH_STI=y 62CONFIG_ARCH_STI=y
63CONFIG_ARCH_EXYNOS=y 63CONFIG_ARCH_EXYNOS=y
64CONFIG_EXYNOS5420_MCPM=y 64CONFIG_EXYNOS5420_MCPM=y
65CONFIG_ARCH_SHMOBILE_MULTI=y
66CONFIG_ARCH_EMEV2=y
67CONFIG_ARCH_R7S72100=y
68CONFIG_ARCH_R8A73A4=y
69CONFIG_ARCH_R8A7740=y
70CONFIG_ARCH_R8A7779=y
71CONFIG_ARCH_R8A7790=y
72CONFIG_ARCH_R8A7791=y
73CONFIG_ARCH_R8A7794=y
74CONFIG_ARCH_SH73A0=y
75CONFIG_MACH_MARZEN=y
65CONFIG_ARCH_SUNXI=y 76CONFIG_ARCH_SUNXI=y
66CONFIG_ARCH_SIRF=y 77CONFIG_ARCH_SIRF=y
67CONFIG_ARCH_TEGRA=y 78CONFIG_ARCH_TEGRA=y
@@ -84,6 +95,8 @@ CONFIG_PCI_KEYSTONE=y
84CONFIG_PCI_MSI=y 95CONFIG_PCI_MSI=y
85CONFIG_PCI_MVEBU=y 96CONFIG_PCI_MVEBU=y
86CONFIG_PCI_TEGRA=y 97CONFIG_PCI_TEGRA=y
98CONFIG_PCI_RCAR_GEN2=y
99CONFIG_PCI_RCAR_GEN2_PCIE=y
87CONFIG_PCIEPORTBUS=y 100CONFIG_PCIEPORTBUS=y
88CONFIG_SMP=y 101CONFIG_SMP=y
89CONFIG_NR_CPUS=8 102CONFIG_NR_CPUS=8
@@ -130,6 +143,7 @@ CONFIG_DEVTMPFS_MOUNT=y
130CONFIG_DMA_CMA=y 143CONFIG_DMA_CMA=y
131CONFIG_CMA_SIZE_MBYTES=64 144CONFIG_CMA_SIZE_MBYTES=64
132CONFIG_OMAP_OCP2SCP=y 145CONFIG_OMAP_OCP2SCP=y
146CONFIG_SIMPLE_PM_BUS=y
133CONFIG_MTD=y 147CONFIG_MTD=y
134CONFIG_MTD_CMDLINE_PARTS=y 148CONFIG_MTD_CMDLINE_PARTS=y
135CONFIG_MTD_BLOCK=y 149CONFIG_MTD_BLOCK=y
@@ -157,6 +171,7 @@ CONFIG_AHCI_SUNXI=y
157CONFIG_AHCI_TEGRA=y 171CONFIG_AHCI_TEGRA=y
158CONFIG_SATA_HIGHBANK=y 172CONFIG_SATA_HIGHBANK=y
159CONFIG_SATA_MV=y 173CONFIG_SATA_MV=y
174CONFIG_SATA_RCAR=y
160CONFIG_NETDEVICES=y 175CONFIG_NETDEVICES=y
161CONFIG_HIX5HD2_GMAC=y 176CONFIG_HIX5HD2_GMAC=y
162CONFIG_SUN4I_EMAC=y 177CONFIG_SUN4I_EMAC=y
@@ -167,14 +182,17 @@ CONFIG_MV643XX_ETH=y
167CONFIG_MVNETA=y 182CONFIG_MVNETA=y
168CONFIG_KS8851=y 183CONFIG_KS8851=y
169CONFIG_R8169=y 184CONFIG_R8169=y
185CONFIG_SH_ETH=y
170CONFIG_SMSC911X=y 186CONFIG_SMSC911X=y
171CONFIG_STMMAC_ETH=y 187CONFIG_STMMAC_ETH=y
172CONFIG_TI_CPSW=y 188CONFIG_TI_CPSW=y
173CONFIG_XILINX_EMACLITE=y 189CONFIG_XILINX_EMACLITE=y
174CONFIG_AT803X_PHY=y 190CONFIG_AT803X_PHY=y
175CONFIG_MARVELL_PHY=y 191CONFIG_MARVELL_PHY=y
192CONFIG_SMSC_PHY=y
176CONFIG_BROADCOM_PHY=y 193CONFIG_BROADCOM_PHY=y
177CONFIG_ICPLUS_PHY=y 194CONFIG_ICPLUS_PHY=y
195CONFIG_MICREL_PHY=y
178CONFIG_USB_PEGASUS=y 196CONFIG_USB_PEGASUS=y
179CONFIG_USB_USBNET=y 197CONFIG_USB_USBNET=y
180CONFIG_USB_NET_SMSC75XX=y 198CONFIG_USB_NET_SMSC75XX=y
@@ -192,15 +210,18 @@ CONFIG_KEYBOARD_CROS_EC=y
192CONFIG_MOUSE_PS2_ELANTECH=y 210CONFIG_MOUSE_PS2_ELANTECH=y
193CONFIG_INPUT_TOUCHSCREEN=y 211CONFIG_INPUT_TOUCHSCREEN=y
194CONFIG_TOUCHSCREEN_ATMEL_MXT=y 212CONFIG_TOUCHSCREEN_ATMEL_MXT=y
213CONFIG_TOUCHSCREEN_ST1232=m
195CONFIG_TOUCHSCREEN_STMPE=y 214CONFIG_TOUCHSCREEN_STMPE=y
196CONFIG_TOUCHSCREEN_SUN4I=y 215CONFIG_TOUCHSCREEN_SUN4I=y
197CONFIG_INPUT_MISC=y 216CONFIG_INPUT_MISC=y
198CONFIG_INPUT_MPU3050=y 217CONFIG_INPUT_MPU3050=y
199CONFIG_INPUT_AXP20X_PEK=y 218CONFIG_INPUT_AXP20X_PEK=y
219CONFIG_INPUT_ADXL34X=m
200CONFIG_SERIO_AMBAKMI=y 220CONFIG_SERIO_AMBAKMI=y
201CONFIG_SERIAL_8250=y 221CONFIG_SERIAL_8250=y
202CONFIG_SERIAL_8250_CONSOLE=y 222CONFIG_SERIAL_8250_CONSOLE=y
203CONFIG_SERIAL_8250_DW=y 223CONFIG_SERIAL_8250_DW=y
224CONFIG_SERIAL_8250_EM=y
204CONFIG_SERIAL_8250_MT6577=y 225CONFIG_SERIAL_8250_MT6577=y
205CONFIG_SERIAL_AMBA_PL011=y 226CONFIG_SERIAL_AMBA_PL011=y
206CONFIG_SERIAL_AMBA_PL011_CONSOLE=y 227CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
@@ -213,6 +234,9 @@ CONFIG_SERIAL_SIRFSOC_CONSOLE=y
213CONFIG_SERIAL_TEGRA=y 234CONFIG_SERIAL_TEGRA=y
214CONFIG_SERIAL_IMX=y 235CONFIG_SERIAL_IMX=y
215CONFIG_SERIAL_IMX_CONSOLE=y 236CONFIG_SERIAL_IMX_CONSOLE=y
237CONFIG_SERIAL_SH_SCI=y
238CONFIG_SERIAL_SH_SCI_NR_UARTS=20
239CONFIG_SERIAL_SH_SCI_CONSOLE=y
216CONFIG_SERIAL_MSM=y 240CONFIG_SERIAL_MSM=y
217CONFIG_SERIAL_MSM_CONSOLE=y 241CONFIG_SERIAL_MSM_CONSOLE=y
218CONFIG_SERIAL_VT8500=y 242CONFIG_SERIAL_VT8500=y
@@ -233,19 +257,26 @@ CONFIG_I2C_MUX_PCA954x=y
233CONFIG_I2C_MUX_PINCTRL=y 257CONFIG_I2C_MUX_PINCTRL=y
234CONFIG_I2C_CADENCE=y 258CONFIG_I2C_CADENCE=y
235CONFIG_I2C_DESIGNWARE_PLATFORM=y 259CONFIG_I2C_DESIGNWARE_PLATFORM=y
260CONFIG_I2C_GPIO=m
236CONFIG_I2C_EXYNOS5=y 261CONFIG_I2C_EXYNOS5=y
237CONFIG_I2C_MV64XXX=y 262CONFIG_I2C_MV64XXX=y
263CONFIG_I2C_RIIC=y
238CONFIG_I2C_S3C2410=y 264CONFIG_I2C_S3C2410=y
265CONFIG_I2C_SH_MOBILE=y
239CONFIG_I2C_SIRF=y 266CONFIG_I2C_SIRF=y
240CONFIG_I2C_TEGRA=y
241CONFIG_I2C_ST=y 267CONFIG_I2C_ST=y
242CONFIG_SPI=y 268CONFIG_I2C_TEGRA=y
243CONFIG_I2C_XILINX=y 269CONFIG_I2C_XILINX=y
244CONFIG_SPI_DAVINCI=y 270CONFIG_I2C_RCAR=y
271CONFIG_SPI=y
245CONFIG_SPI_CADENCE=y 272CONFIG_SPI_CADENCE=y
273CONFIG_SPI_DAVINCI=y
246CONFIG_SPI_OMAP24XX=y 274CONFIG_SPI_OMAP24XX=y
247CONFIG_SPI_ORION=y 275CONFIG_SPI_ORION=y
248CONFIG_SPI_PL022=y 276CONFIG_SPI_PL022=y
277CONFIG_SPI_RSPI=y
278CONFIG_SPI_SH_MSIOF=m
279CONFIG_SPI_SH_HSPI=y
249CONFIG_SPI_SIRF=y 280CONFIG_SPI_SIRF=y
250CONFIG_SPI_SUN4I=y 281CONFIG_SPI_SUN4I=y
251CONFIG_SPI_SUN6I=y 282CONFIG_SPI_SUN6I=y
@@ -259,12 +290,15 @@ CONFIG_PINCTRL_PALMAS=y
259CONFIG_PINCTRL_APQ8084=y 290CONFIG_PINCTRL_APQ8084=y
260CONFIG_GPIO_SYSFS=y 291CONFIG_GPIO_SYSFS=y
261CONFIG_GPIO_GENERIC_PLATFORM=y 292CONFIG_GPIO_GENERIC_PLATFORM=y
262CONFIG_GPIO_DWAPB=y
263CONFIG_GPIO_DAVINCI=y 293CONFIG_GPIO_DAVINCI=y
294CONFIG_GPIO_DWAPB=y
295CONFIG_GPIO_EM=y
296CONFIG_GPIO_RCAR=y
264CONFIG_GPIO_XILINX=y 297CONFIG_GPIO_XILINX=y
265CONFIG_GPIO_ZYNQ=y 298CONFIG_GPIO_ZYNQ=y
266CONFIG_GPIO_PCA953X=y 299CONFIG_GPIO_PCA953X=y
267CONFIG_GPIO_PCA953X_IRQ=y 300CONFIG_GPIO_PCA953X_IRQ=y
301CONFIG_GPIO_PCF857X=y
268CONFIG_GPIO_TWL4030=y 302CONFIG_GPIO_TWL4030=y
269CONFIG_GPIO_PALMAS=y 303CONFIG_GPIO_PALMAS=y
270CONFIG_GPIO_SYSCON=y 304CONFIG_GPIO_SYSCON=y
@@ -276,10 +310,12 @@ CONFIG_POWER_RESET_AS3722=y
276CONFIG_POWER_RESET_GPIO=y 310CONFIG_POWER_RESET_GPIO=y
277CONFIG_POWER_RESET_KEYSTONE=y 311CONFIG_POWER_RESET_KEYSTONE=y
278CONFIG_POWER_RESET_SUN6I=y 312CONFIG_POWER_RESET_SUN6I=y
313CONFIG_POWER_RESET_RMOBILE=y
279CONFIG_SENSORS_LM90=y 314CONFIG_SENSORS_LM90=y
280CONFIG_SENSORS_LM95245=y 315CONFIG_SENSORS_LM95245=y
281CONFIG_THERMAL=y 316CONFIG_THERMAL=y
282CONFIG_CPU_THERMAL=y 317CONFIG_CPU_THERMAL=y
318CONFIG_RCAR_THERMAL=y
283CONFIG_ARMADA_THERMAL=y 319CONFIG_ARMADA_THERMAL=y
284CONFIG_DAVINCI_WATCHDOG 320CONFIG_DAVINCI_WATCHDOG
285CONFIG_ST_THERMAL_SYSCFG=y 321CONFIG_ST_THERMAL_SYSCFG=y
@@ -290,6 +326,7 @@ CONFIG_ARM_SP805_WATCHDOG=y
290CONFIG_ORION_WATCHDOG=y 326CONFIG_ORION_WATCHDOG=y
291CONFIG_SUNXI_WATCHDOG=y 327CONFIG_SUNXI_WATCHDOG=y
292CONFIG_MESON_WATCHDOG=y 328CONFIG_MESON_WATCHDOG=y
329CONFIG_MFD_AS3711=y
293CONFIG_MFD_AS3722=y 330CONFIG_MFD_AS3722=y
294CONFIG_MFD_BCM590XX=y 331CONFIG_MFD_BCM590XX=y
295CONFIG_MFD_AXP20X=y 332CONFIG_MFD_AXP20X=y
@@ -304,13 +341,16 @@ CONFIG_MFD_TPS65090=y
304CONFIG_MFD_TPS6586X=y 341CONFIG_MFD_TPS6586X=y
305CONFIG_MFD_TPS65910=y 342CONFIG_MFD_TPS65910=y
306CONFIG_REGULATOR_AB8500=y 343CONFIG_REGULATOR_AB8500=y
344CONFIG_REGULATOR_AS3711=y
307CONFIG_REGULATOR_AS3722=y 345CONFIG_REGULATOR_AS3722=y
308CONFIG_REGULATOR_AXP20X=y 346CONFIG_REGULATOR_AXP20X=y
309CONFIG_REGULATOR_BCM590XX=y 347CONFIG_REGULATOR_BCM590XX=y
348CONFIG_REGULATOR_DA9210=y
310CONFIG_REGULATOR_GPIO=y 349CONFIG_REGULATOR_GPIO=y
311CONFIG_MFD_SYSCON=y 350CONFIG_MFD_SYSCON=y
312CONFIG_POWER_RESET_SYSCON=y 351CONFIG_POWER_RESET_SYSCON=y
313CONFIG_REGULATOR_MAX8907=y 352CONFIG_REGULATOR_MAX8907=y
353CONFIG_REGULATOR_MAX8973=y
314CONFIG_REGULATOR_MAX77686=y 354CONFIG_REGULATOR_MAX77686=y
315CONFIG_REGULATOR_PALMAS=y 355CONFIG_REGULATOR_PALMAS=y
316CONFIG_REGULATOR_S2MPS11=y 356CONFIG_REGULATOR_S2MPS11=y
@@ -324,18 +364,32 @@ CONFIG_REGULATOR_TWL4030=y
324CONFIG_REGULATOR_VEXPRESS=y 364CONFIG_REGULATOR_VEXPRESS=y
325CONFIG_MEDIA_SUPPORT=y 365CONFIG_MEDIA_SUPPORT=y
326CONFIG_MEDIA_CAMERA_SUPPORT=y 366CONFIG_MEDIA_CAMERA_SUPPORT=y
367CONFIG_MEDIA_CONTROLLER=y
368CONFIG_VIDEO_V4L2_SUBDEV_API=y
327CONFIG_MEDIA_USB_SUPPORT=y 369CONFIG_MEDIA_USB_SUPPORT=y
328CONFIG_USB_VIDEO_CLASS=y 370CONFIG_USB_VIDEO_CLASS=y
329CONFIG_USB_GSPCA=y 371CONFIG_USB_GSPCA=y
372CONFIG_V4L_PLATFORM_DRIVERS=y
373CONFIG_SOC_CAMERA=m
374CONFIG_SOC_CAMERA_PLATFORM=m
375CONFIG_VIDEO_RCAR_VIN=m
376CONFIG_V4L_MEM2MEM_DRIVERS=y
377CONFIG_VIDEO_RENESAS_VSP1=m
378# CONFIG_MEDIA_SUBDRV_AUTOSELECT is not set
379CONFIG_VIDEO_ADV7180=m
330CONFIG_DRM=y 380CONFIG_DRM=y
381CONFIG_DRM_RCAR_DU=m
331CONFIG_DRM_TEGRA=y 382CONFIG_DRM_TEGRA=y
332CONFIG_DRM_PANEL_SIMPLE=y 383CONFIG_DRM_PANEL_SIMPLE=y
333CONFIG_FB_ARMCLCD=y 384CONFIG_FB_ARMCLCD=y
334CONFIG_FB_WM8505=y 385CONFIG_FB_WM8505=y
386CONFIG_FB_SH_MOBILE_LCDC=y
335CONFIG_FB_SIMPLE=y 387CONFIG_FB_SIMPLE=y
388CONFIG_FB_SH_MOBILE_MERAM=y
336CONFIG_BACKLIGHT_LCD_SUPPORT=y 389CONFIG_BACKLIGHT_LCD_SUPPORT=y
337CONFIG_BACKLIGHT_CLASS_DEVICE=y 390CONFIG_BACKLIGHT_CLASS_DEVICE=y
338CONFIG_BACKLIGHT_PWM=y 391CONFIG_BACKLIGHT_PWM=y
392CONFIG_BACKLIGHT_AS3711=y
339CONFIG_FRAMEBUFFER_CONSOLE=y 393CONFIG_FRAMEBUFFER_CONSOLE=y
340CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y 394CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
341CONFIG_SOUND=y 395CONFIG_SOUND=y
@@ -343,6 +397,8 @@ CONFIG_SND=y
343CONFIG_SND_DYNAMIC_MINORS=y 397CONFIG_SND_DYNAMIC_MINORS=y
344CONFIG_SND_USB_AUDIO=y 398CONFIG_SND_USB_AUDIO=y
345CONFIG_SND_SOC=y 399CONFIG_SND_SOC=y
400CONFIG_SND_SOC_SH4_FSI=m
401CONFIG_SND_SOC_RCAR=m
346CONFIG_SND_SOC_TEGRA=y 402CONFIG_SND_SOC_TEGRA=y
347CONFIG_SND_SOC_TEGRA_RT5640=y 403CONFIG_SND_SOC_TEGRA_RT5640=y
348CONFIG_SND_SOC_TEGRA_WM8753=y 404CONFIG_SND_SOC_TEGRA_WM8753=y
@@ -350,6 +406,8 @@ CONFIG_SND_SOC_TEGRA_WM8903=y
350CONFIG_SND_SOC_TEGRA_TRIMSLICE=y 406CONFIG_SND_SOC_TEGRA_TRIMSLICE=y
351CONFIG_SND_SOC_TEGRA_ALC5632=y 407CONFIG_SND_SOC_TEGRA_ALC5632=y
352CONFIG_SND_SOC_TEGRA_MAX98090=y 408CONFIG_SND_SOC_TEGRA_MAX98090=y
409CONFIG_SND_SOC_AK4642=m
410CONFIG_SND_SOC_WM8978=m
353CONFIG_USB=y 411CONFIG_USB=y
354CONFIG_USB_XHCI_HCD=y 412CONFIG_USB_XHCI_HCD=y
355CONFIG_USB_XHCI_MVEBU=y 413CONFIG_USB_XHCI_MVEBU=y
@@ -362,6 +420,8 @@ CONFIG_USB_ISP1760_HCD=y
362CONFIG_USB_OHCI_HCD=y 420CONFIG_USB_OHCI_HCD=y
363CONFIG_USB_OHCI_HCD_STI=y 421CONFIG_USB_OHCI_HCD_STI=y
364CONFIG_USB_OHCI_HCD_PLATFORM=y 422CONFIG_USB_OHCI_HCD_PLATFORM=y
423CONFIG_USB_R8A66597_HCD=m
424CONFIG_USB_RENESAS_USBHS=m
365CONFIG_USB_STORAGE=y 425CONFIG_USB_STORAGE=y
366CONFIG_USB_DWC3=y 426CONFIG_USB_DWC3=y
367CONFIG_USB_CHIPIDEA=y 427CONFIG_USB_CHIPIDEA=y
@@ -374,6 +434,10 @@ CONFIG_SAMSUNG_USB3PHY=y
374CONFIG_USB_GPIO_VBUS=y 434CONFIG_USB_GPIO_VBUS=y
375CONFIG_USB_ISP1301=y 435CONFIG_USB_ISP1301=y
376CONFIG_USB_MXS_PHY=y 436CONFIG_USB_MXS_PHY=y
437CONFIG_USB_RCAR_PHY=m
438CONFIG_USB_RCAR_GEN2_PHY=m
439CONFIG_USB_GADGET=y
440CONFIG_USB_RENESAS_USBHS_UDC=m
377CONFIG_MMC=y 441CONFIG_MMC=y
378CONFIG_MMC_BLOCK_MINORS=16 442CONFIG_MMC_BLOCK_MINORS=16
379CONFIG_MMC_ARMMMCI=y 443CONFIG_MMC_ARMMMCI=y
@@ -392,12 +456,14 @@ CONFIG_MMC_SDHCI_ST=y
392CONFIG_MMC_OMAP=y 456CONFIG_MMC_OMAP=y
393CONFIG_MMC_OMAP_HS=y 457CONFIG_MMC_OMAP_HS=y
394CONFIG_MMC_MVSDIO=y 458CONFIG_MMC_MVSDIO=y
395CONFIG_MMC_SUNXI=y 459CONFIG_MMC_SDHI=y
396CONFIG_MMC_DW=y 460CONFIG_MMC_DW=y
397CONFIG_MMC_DW_IDMAC=y 461CONFIG_MMC_DW_IDMAC=y
398CONFIG_MMC_DW_PLTFM=y 462CONFIG_MMC_DW_PLTFM=y
399CONFIG_MMC_DW_EXYNOS=y 463CONFIG_MMC_DW_EXYNOS=y
400CONFIG_MMC_DW_ROCKCHIP=y 464CONFIG_MMC_DW_ROCKCHIP=y
465CONFIG_MMC_SH_MMCIF=y
466CONFIG_MMC_SUNXI=y
401CONFIG_NEW_LEDS=y 467CONFIG_NEW_LEDS=y
402CONFIG_LEDS_CLASS=y 468CONFIG_LEDS_CLASS=y
403CONFIG_LEDS_GPIO=y 469CONFIG_LEDS_GPIO=y
@@ -421,10 +487,12 @@ CONFIG_RTC_DRV_AS3722=y
421CONFIG_RTC_DRV_DS1307=y 487CONFIG_RTC_DRV_DS1307=y
422CONFIG_RTC_DRV_MAX8907=y 488CONFIG_RTC_DRV_MAX8907=y
423CONFIG_RTC_DRV_MAX77686=y 489CONFIG_RTC_DRV_MAX77686=y
490CONFIG_RTC_DRV_RS5C372=m
424CONFIG_RTC_DRV_PALMAS=y 491CONFIG_RTC_DRV_PALMAS=y
425CONFIG_RTC_DRV_TWL4030=y 492CONFIG_RTC_DRV_TWL4030=y
426CONFIG_RTC_DRV_TPS6586X=y 493CONFIG_RTC_DRV_TPS6586X=y
427CONFIG_RTC_DRV_TPS65910=y 494CONFIG_RTC_DRV_TPS65910=y
495CONFIG_RTC_DRV_S35390A=m
428CONFIG_RTC_DRV_EM3027=y 496CONFIG_RTC_DRV_EM3027=y
429CONFIG_RTC_DRV_PL031=y 497CONFIG_RTC_DRV_PL031=y
430CONFIG_RTC_DRV_VT8500=y 498CONFIG_RTC_DRV_VT8500=y
@@ -436,6 +504,9 @@ CONFIG_DMADEVICES=y
436CONFIG_DW_DMAC=y 504CONFIG_DW_DMAC=y
437CONFIG_MV_XOR=y 505CONFIG_MV_XOR=y
438CONFIG_TEGRA20_APB_DMA=y 506CONFIG_TEGRA20_APB_DMA=y
507CONFIG_SH_DMAE=y
508CONFIG_RCAR_AUDMAC_PP=m
509CONFIG_RCAR_DMAC=y
439CONFIG_STE_DMA40=y 510CONFIG_STE_DMA40=y
440CONFIG_SIRF_DMA=y 511CONFIG_SIRF_DMA=y
441CONFIG_TI_EDMA=y 512CONFIG_TI_EDMA=y
@@ -468,6 +539,7 @@ CONFIG_IIO=y
468CONFIG_XILINX_XADC=y 539CONFIG_XILINX_XADC=y
469CONFIG_AK8975=y 540CONFIG_AK8975=y
470CONFIG_PWM=y 541CONFIG_PWM=y
542CONFIG_PWM_RENESAS_TPU=y
471CONFIG_PWM_TEGRA=y 543CONFIG_PWM_TEGRA=y
472CONFIG_PWM_VT8500=y 544CONFIG_PWM_VT8500=y
473CONFIG_PHY_HIX5HD2_SATA=y 545CONFIG_PHY_HIX5HD2_SATA=y
diff --git a/arch/arm/configs/omap2plus_defconfig b/arch/arm/configs/omap2plus_defconfig
index b7386524c356..a097cffa1231 100644
--- a/arch/arm/configs/omap2plus_defconfig
+++ b/arch/arm/configs/omap2plus_defconfig
@@ -114,6 +114,7 @@ CONFIG_MTD_PHYSMAP_OF=y
114CONFIG_MTD_NAND=y 114CONFIG_MTD_NAND=y
115CONFIG_MTD_NAND_ECC_BCH=y 115CONFIG_MTD_NAND_ECC_BCH=y
116CONFIG_MTD_NAND_OMAP2=y 116CONFIG_MTD_NAND_OMAP2=y
117CONFIG_MTD_NAND_OMAP_BCH=y
117CONFIG_MTD_ONENAND=y 118CONFIG_MTD_ONENAND=y
118CONFIG_MTD_ONENAND_VERIFY_WRITE=y 119CONFIG_MTD_ONENAND_VERIFY_WRITE=y
119CONFIG_MTD_ONENAND_OMAP2=y 120CONFIG_MTD_ONENAND_OMAP2=y
@@ -248,6 +249,7 @@ CONFIG_TWL6040_CORE=y
248CONFIG_REGULATOR_PALMAS=y 249CONFIG_REGULATOR_PALMAS=y
249CONFIG_REGULATOR_PBIAS=y 250CONFIG_REGULATOR_PBIAS=y
250CONFIG_REGULATOR_TI_ABB=y 251CONFIG_REGULATOR_TI_ABB=y
252CONFIG_REGULATOR_TPS62360=m
251CONFIG_REGULATOR_TPS65023=y 253CONFIG_REGULATOR_TPS65023=y
252CONFIG_REGULATOR_TPS6507X=y 254CONFIG_REGULATOR_TPS6507X=y
253CONFIG_REGULATOR_TPS65217=y 255CONFIG_REGULATOR_TPS65217=y
@@ -374,7 +376,7 @@ CONFIG_PWM_TIEHRPWM=m
374CONFIG_PWM_TWL=m 376CONFIG_PWM_TWL=m
375CONFIG_PWM_TWL_LED=m 377CONFIG_PWM_TWL_LED=m
376CONFIG_OMAP_USB2=m 378CONFIG_OMAP_USB2=m
377CONFIG_TI_PIPE3=m 379CONFIG_TI_PIPE3=y
378CONFIG_EXT2_FS=y 380CONFIG_EXT2_FS=y
379CONFIG_EXT3_FS=y 381CONFIG_EXT3_FS=y
380# CONFIG_EXT3_FS_XATTR is not set 382# CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/mach-asm9260/Kconfig b/arch/arm/mach-asm9260/Kconfig
index 8423be76080e..52241207a82a 100644
--- a/arch/arm/mach-asm9260/Kconfig
+++ b/arch/arm/mach-asm9260/Kconfig
@@ -2,5 +2,7 @@ config MACH_ASM9260
2 bool "Alphascale ASM9260" 2 bool "Alphascale ASM9260"
3 depends on ARCH_MULTI_V5 3 depends on ARCH_MULTI_V5
4 select CPU_ARM926T 4 select CPU_ARM926T
5 select ASM9260_TIMER
6 select GENERIC_CLOCKEVENTS
5 help 7 help
6 Support for Alphascale ASM9260 based platform. 8 Support for Alphascale ASM9260 based platform.
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 5fc47569051e..485961a4de1d 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -62,6 +62,10 @@ config ARCH_R8A7740
62 select ARCH_RMOBILE 62 select ARCH_RMOBILE
63 select RENESAS_INTC_IRQPIN 63 select RENESAS_INTC_IRQPIN
64 64
65config ARCH_R8A7778
66 bool "R-Car M1A (R8A77781)"
67 select ARCH_RCAR_GEN1
68
65config ARCH_R8A7779 69config ARCH_R8A7779
66 bool "R-Car H1 (R8A77790)" 70 bool "R-Car H1 (R8A77790)"
67 select ARCH_RCAR_GEN1 71 select ARCH_RCAR_GEN1
@@ -92,13 +96,6 @@ if ARCH_SHMOBILE_LEGACY
92 96
93comment "Renesas ARM SoCs System Type" 97comment "Renesas ARM SoCs System Type"
94 98
95config ARCH_SH7372
96 bool "SH-Mobile AP4 (SH7372)"
97 select ARCH_RMOBILE
98 select ARCH_WANT_OPTIONAL_GPIOLIB
99 select ARM_CPU_SUSPEND if PM || CPU_IDLE
100 select SH_INTC
101
102config ARCH_SH73A0 99config ARCH_SH73A0
103 bool "SH-Mobile AG5 (R8A73A00)" 100 bool "SH-Mobile AG5 (R8A73A00)"
104 select ARCH_RMOBILE 101 select ARCH_RMOBILE
@@ -129,15 +126,6 @@ config ARCH_R8A7779
129 126
130comment "Renesas ARM SoCs Board Type" 127comment "Renesas ARM SoCs Board Type"
131 128
132config MACH_MACKEREL
133 bool "mackerel board"
134 depends on ARCH_SH7372
135 select ARCH_REQUIRE_GPIOLIB
136 select REGULATOR_FIXED_VOLTAGE if REGULATOR
137 select SMSC_PHY if SMSC911X
138 select SND_SOC_AK4642 if SND_SIMPLE_CARD
139 select USE_OF
140
141config MACH_ARMADILLO800EVA 129config MACH_ARMADILLO800EVA
142 bool "Armadillo-800 EVA board" 130 bool "Armadillo-800 EVA board"
143 depends on ARCH_R8A7740 131 depends on ARCH_R8A7740
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index cf8b348f943d..ba7bb7847ae3 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -6,7 +6,6 @@
6obj-y := timer.o console.o 6obj-y := timer.o console.o
7 7
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH7372) += setup-sh7372.o intc-sh7372.o pm-sh7372.o
10obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o 9obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o
11obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o 10obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
12obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o 11obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o
@@ -21,7 +20,6 @@ obj-$(CONFIG_ARCH_R7S72100) += setup-r7s72100.o
21# Clock objects 20# Clock objects
22ifndef CONFIG_COMMON_CLK 21ifndef CONFIG_COMMON_CLK
23obj-y += clock.o 22obj-y += clock.o
24obj-$(CONFIG_ARCH_SH7372) += clock-sh7372.o
25obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o 23obj-$(CONFIG_ARCH_SH73A0) += clock-sh73a0.o
26obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o 24obj-$(CONFIG_ARCH_R8A7740) += clock-r8a7740.o
27obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o 25obj-$(CONFIG_ARCH_R8A7778) += clock-r8a7778.o
@@ -50,14 +48,10 @@ obj-$(CONFIG_CPU_FREQ) += cpufreq.o
50obj-$(CONFIG_PM_RCAR) += pm-rcar.o 48obj-$(CONFIG_PM_RCAR) += pm-rcar.o
51obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o 49obj-$(CONFIG_PM_RMOBILE) += pm-rmobile.o
52 50
53# special sh7372 handling for IRQ objects and low level sleep code
54obj-$(CONFIG_ARCH_SH7372) += entry-intc.o sleep-sh7372.o
55
56# Board objects 51# Board objects
57ifdef CONFIG_ARCH_SHMOBILE_MULTI 52ifdef CONFIG_ARCH_SHMOBILE_MULTI
58obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o 53obj-$(CONFIG_MACH_MARZEN) += board-marzen-reference.o
59else 54else
60obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
61obj-$(CONFIG_MACH_BOCKW) += board-bockw.o 55obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
62obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o 56obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
63obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 57obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index d893aa467781..da9fc6d4a1da 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -5,7 +5,6 @@ loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
5loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 5loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
6loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 6loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
7loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000 7loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
8loadaddr-$(CONFIG_MACH_MACKEREL) += 0x40008000
9loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 8loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
10 9
11__ZRELADDR := $(sort $(loadaddr-y)) 10__ZRELADDR := $(sort $(loadaddr-y))
diff --git a/arch/arm/mach-shmobile/board-bockw-reference.c b/arch/arm/mach-shmobile/board-bockw-reference.c
index d649ade4a202..9a74efda3d18 100644
--- a/arch/arm/mach-shmobile/board-bockw-reference.c
+++ b/arch/arm/mach-shmobile/board-bockw-reference.c
@@ -36,7 +36,9 @@ static void __init bockw_init(void)
36 void __iomem *fpga; 36 void __iomem *fpga;
37 void __iomem *pfc; 37 void __iomem *pfc;
38 38
39#ifndef CONFIG_COMMON_CLK
39 r8a7778_clock_init(); 40 r8a7778_clock_init();
41#endif
40 r8a7778_init_irq_extpin_dt(1); 42 r8a7778_init_irq_extpin_dt(1);
41 r8a7778_add_dt_devices(); 43 r8a7778_add_dt_devices();
42 44
diff --git a/arch/arm/mach-shmobile/board-mackerel.c b/arch/arm/mach-shmobile/board-mackerel.c
deleted file mode 100644
index a1c1dfb6a67a..000000000000
--- a/arch/arm/mach-shmobile/board-mackerel.c
+++ /dev/null
@@ -1,1522 +0,0 @@
1/*
2 * mackerel board support
3 *
4 * Copyright (C) 2010 Renesas Solutions Corp.
5 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * based on ap4evb
8 * Copyright (C) 2010 Magnus Damm
9 * Copyright (C) 2008 Yoshihiro Shimoda
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20#include <linux/delay.h>
21#include <linux/kernel.h>
22#include <linux/init.h>
23#include <linux/interrupt.h>
24#include <linux/irq.h>
25#include <linux/platform_device.h>
26#include <linux/gpio.h>
27#include <linux/input.h>
28#include <linux/io.h>
29#include <linux/i2c.h>
30#include <linux/leds.h>
31#include <linux/mfd/tmio.h>
32#include <linux/mmc/host.h>
33#include <linux/mmc/sh_mmcif.h>
34#include <linux/mmc/sh_mobile_sdhi.h>
35#include <linux/mtd/mtd.h>
36#include <linux/mtd/partitions.h>
37#include <linux/mtd/physmap.h>
38#include <linux/mtd/sh_flctl.h>
39#include <linux/pinctrl/machine.h>
40#include <linux/pinctrl/pinconf-generic.h>
41#include <linux/platform_data/gpio_backlight.h>
42#include <linux/pm_clock.h>
43#include <linux/regulator/fixed.h>
44#include <linux/regulator/machine.h>
45#include <linux/smsc911x.h>
46#include <linux/sh_clk.h>
47#include <linux/tca6416_keypad.h>
48#include <linux/usb/renesas_usbhs.h>
49#include <linux/dma-mapping.h>
50
51#include <video/sh_mobile_hdmi.h>
52#include <video/sh_mobile_lcdc.h>
53#include <media/sh_mobile_ceu.h>
54#include <media/soc_camera.h>
55#include <media/soc_camera_platform.h>
56#include <sound/sh_fsi.h>
57#include <sound/simple_card.h>
58#include <asm/mach/arch.h>
59#include <asm/mach-types.h>
60
61#include "common.h"
62#include "intc.h"
63#include "irqs.h"
64#include "pm-rmobile.h"
65#include "sh-gpio.h"
66#include "sh7372.h"
67
68/*
69 * Address Interface BusWidth note
70 * ------------------------------------------------------------------
71 * 0x0000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = ON
72 * 0x0800_0000 user area -
73 * 0x1000_0000 NOR Flash ROM (MCP) 16bit SW7 : bit1 = OFF
74 * 0x1400_0000 Ether (LAN9220) 16bit
75 * 0x1600_0000 user area - cannot use with NAND
76 * 0x1800_0000 user area -
77 * 0x1A00_0000 -
78 * 0x4000_0000 LPDDR2-SDRAM (POP) 32bit
79 */
80
81/*
82 * CPU mode
83 *
84 * SW4 | Boot Area| Master | Remarks
85 * 1 | 2 | 3 | 4 | 5 | 6 | 8 | | Processor|
86 * ----+-----+-----+-----+-----+-----+-----+----------+----------+--------------
87 * ON | ON | OFF | ON | ON | OFF | OFF | External | System | External ROM
88 * ON | ON | ON | ON | ON | OFF | OFF | External | System | ROM Debug
89 * ON | ON | X | ON | OFF | OFF | OFF | Built-in | System | ROM Debug
90 * X | OFF | X | X | X | X | OFF | Built-in | System | MaskROM
91 * OFF | X | X | X | X | X | OFF | Built-in | System | MaskROM
92 * X | X | X | OFF | X | X | OFF | Built-in | System | MaskROM
93 * OFF | ON | OFF | X | X | OFF | ON | External | System | Standalone
94 * ON | OFF | OFF | X | X | OFF | ON | External | Realtime | Standalone
95*/
96
97/*
98 * NOR Flash ROM
99 *
100 * SW1 | SW2 | SW7 | NOR Flash ROM
101 * bit1 | bit1 bit2 | bit1 | Memory allocation
102 * ------+------------+------+------------------
103 * OFF | ON OFF | ON | Area 0
104 * OFF | ON OFF | OFF | Area 4
105 */
106
107/*
108 * SMSC 9220
109 *
110 * SW1 SMSC 9220
111 * -----------------------
112 * ON access disable
113 * OFF access enable
114 */
115
116/*
117 * NAND Flash ROM
118 *
119 * SW1 | SW2 | SW7 | NAND Flash ROM
120 * bit1 | bit1 bit2 | bit2 | Memory allocation
121 * ------+------------+------+------------------
122 * OFF | ON OFF | ON | FCE 0
123 * OFF | ON OFF | OFF | FCE 1
124 */
125
126/*
127 * External interrupt pin settings
128 *
129 * IRQX | pin setting | device | level
130 * ------+--------------------+--------------------+-------
131 * IRQ0 | ICR1A.IRQ0SA=0010 | SDHI2 card detect | Low
132 * IRQ6 | ICR1A.IRQ6SA=0011 | Ether(LAN9220) | High
133 * IRQ7 | ICR1A.IRQ7SA=0010 | LCD Touch Panel | Low
134 * IRQ8 | ICR2A.IRQ8SA=0010 | MMC/SD card detect | Low
135 * IRQ9 | ICR2A.IRQ9SA=0010 | KEY(TCA6408) | Low
136 * IRQ21 | ICR4A.IRQ21SA=0011 | Sensor(ADXL345) | High
137 * IRQ22 | ICR4A.IRQ22SA=0011 | Sensor(AK8975) | High
138 */
139
140/*
141 * USB
142 *
143 * USB0 : CN22 : Function
144 * USB1 : CN31 : Function/Host *1
145 *
146 * J30 (for CN31) *1
147 * ----------+---------------+-------------
148 * 1-2 short | VBUS 5V | Host
149 * open | external VBUS | Function
150 *
151 * CAUTION
152 *
153 * renesas_usbhs driver can use external interrupt mode
154 * (which come from USB-PHY) or autonomy mode (it use own interrupt)
155 * for detecting connection/disconnection when Function.
156 * USB will be power OFF while it has been disconnecting
157 * if external interrupt mode, and it is always power ON if autonomy mode,
158 *
159 * mackerel can not use external interrupt (IRQ7-PORT167) mode on "USB0",
160 * because Touchscreen is using IRQ7-PORT40.
161 * It is impossible to use IRQ7 demux on this board.
162 */
163
164/*
165 * SDHI0 (CN12)
166 *
167 * SW56 : OFF
168 *
169 */
170
171/* MMC /SDHI1 (CN7)
172 *
173 * I/O voltage : 1.8v
174 *
175 * Power voltage : 1.8v or 3.3v
176 * J22 : select power voltage *1
177 * 1-2 pin : 1.8v
178 * 2-3 pin : 3.3v
179 *
180 * *1
181 * Please change J22 depends the card to be used.
182 * MMC's OCR field set to support either voltage for the card inserted.
183 *
184 * SW1 | SW33
185 * | bit1 | bit2 | bit3 | bit4
186 * -------------+------+------+------+-------
187 * MMC0 OFF | OFF | X | ON | X (Use MMCIF)
188 * SDHI1 OFF | ON | X | OFF | X (Use MFD_SH_MOBILE_SDHI)
189 *
190 */
191
192/*
193 * SDHI2 (CN23)
194 *
195 * microSD card sloct
196 *
197 */
198
199/*
200 * FSI - AK4642
201 *
202 * it needs amixer settings for playing
203 *
204 * amixer set "Headphone Enable" on
205 */
206
207/* Fixed 3.3V and 1.8V regulators to be used by multiple devices */
208static struct regulator_consumer_supply fixed1v8_power_consumers[] =
209{
210 /*
211 * J22 on mackerel switches mmcif.0 and sdhi.1 between 1.8V and 3.3V
212 * Since we cannot support both voltages, we support the default 1.8V
213 */
214 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.1"),
215 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.1"),
216 REGULATOR_SUPPLY("vmmc", "sh_mmcif.0"),
217 REGULATOR_SUPPLY("vqmmc", "sh_mmcif.0"),
218};
219
220static struct regulator_consumer_supply fixed3v3_power_consumers[] =
221{
222 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.0"),
223 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
224 REGULATOR_SUPPLY("vmmc", "sh_mobile_sdhi.2"),
225 REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.2"),
226};
227
228/* Dummy supplies, where voltage doesn't matter */
229static struct regulator_consumer_supply dummy_supplies[] = {
230 REGULATOR_SUPPLY("vddvario", "smsc911x"),
231 REGULATOR_SUPPLY("vdd33a", "smsc911x"),
232};
233
234/* MTD */
235static struct mtd_partition nor_flash_partitions[] = {
236 {
237 .name = "loader",
238 .offset = 0x00000000,
239 .size = 512 * 1024,
240 .mask_flags = MTD_WRITEABLE,
241 },
242 {
243 .name = "bootenv",
244 .offset = MTDPART_OFS_APPEND,
245 .size = 512 * 1024,
246 .mask_flags = MTD_WRITEABLE,
247 },
248 {
249 .name = "kernel_ro",
250 .offset = MTDPART_OFS_APPEND,
251 .size = 8 * 1024 * 1024,
252 .mask_flags = MTD_WRITEABLE,
253 },
254 {
255 .name = "kernel",
256 .offset = MTDPART_OFS_APPEND,
257 .size = 8 * 1024 * 1024,
258 },
259 {
260 .name = "data",
261 .offset = MTDPART_OFS_APPEND,
262 .size = MTDPART_SIZ_FULL,
263 },
264};
265
266static struct physmap_flash_data nor_flash_data = {
267 .width = 2,
268 .parts = nor_flash_partitions,
269 .nr_parts = ARRAY_SIZE(nor_flash_partitions),
270};
271
272static struct resource nor_flash_resources[] = {
273 [0] = {
274 .start = 0x20000000, /* CS0 shadow instead of regular CS0 */
275 .end = 0x28000000 - 1, /* needed by USB MASK ROM boot */
276 .flags = IORESOURCE_MEM,
277 }
278};
279
280static struct platform_device nor_flash_device = {
281 .name = "physmap-flash",
282 .dev = {
283 .platform_data = &nor_flash_data,
284 },
285 .num_resources = ARRAY_SIZE(nor_flash_resources),
286 .resource = nor_flash_resources,
287};
288
289/* SMSC */
290static struct resource smc911x_resources[] = {
291 {
292 .start = 0x14000000,
293 .end = 0x16000000 - 1,
294 .flags = IORESOURCE_MEM,
295 }, {
296 .start = evt2irq(0x02c0) /* IRQ6A */,
297 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_LOWLEVEL,
298 },
299};
300
301static struct smsc911x_platform_config smsc911x_info = {
302 .flags = SMSC911X_USE_16BIT | SMSC911X_SAVE_MAC_ADDRESS,
303 .irq_polarity = SMSC911X_IRQ_POLARITY_ACTIVE_LOW,
304 .irq_type = SMSC911X_IRQ_TYPE_PUSH_PULL,
305};
306
307static struct platform_device smc911x_device = {
308 .name = "smsc911x",
309 .id = -1,
310 .num_resources = ARRAY_SIZE(smc911x_resources),
311 .resource = smc911x_resources,
312 .dev = {
313 .platform_data = &smsc911x_info,
314 },
315};
316
317/* MERAM */
318static struct sh_mobile_meram_info mackerel_meram_info = {
319 .addr_mode = SH_MOBILE_MERAM_MODE1,
320};
321
322static struct resource meram_resources[] = {
323 [0] = {
324 .name = "regs",
325 .start = 0xe8000000,
326 .end = 0xe807ffff,
327 .flags = IORESOURCE_MEM,
328 },
329 [1] = {
330 .name = "meram",
331 .start = 0xe8080000,
332 .end = 0xe81fffff,
333 .flags = IORESOURCE_MEM,
334 },
335};
336
337static struct platform_device meram_device = {
338 .name = "sh_mobile_meram",
339 .id = 0,
340 .num_resources = ARRAY_SIZE(meram_resources),
341 .resource = meram_resources,
342 .dev = {
343 .platform_data = &mackerel_meram_info,
344 },
345};
346
347/* LCDC and backlight */
348static struct fb_videomode mackerel_lcdc_modes[] = {
349 {
350 .name = "WVGA Panel",
351 .xres = 800,
352 .yres = 480,
353 .left_margin = 220,
354 .right_margin = 110,
355 .hsync_len = 70,
356 .upper_margin = 20,
357 .lower_margin = 5,
358 .vsync_len = 5,
359 .sync = 0,
360 },
361};
362
363static const struct sh_mobile_meram_cfg lcd_meram_cfg = {
364 .icb[0] = {
365 .meram_size = 0x40,
366 },
367 .icb[1] = {
368 .meram_size = 0x40,
369 },
370};
371
372static struct sh_mobile_lcdc_info lcdc_info = {
373 .meram_dev = &mackerel_meram_info,
374 .clock_source = LCDC_CLK_BUS,
375 .ch[0] = {
376 .chan = LCDC_CHAN_MAINLCD,
377 .fourcc = V4L2_PIX_FMT_RGB565,
378 .lcd_modes = mackerel_lcdc_modes,
379 .num_modes = ARRAY_SIZE(mackerel_lcdc_modes),
380 .interface_type = RGB24,
381 .clock_divider = 3,
382 .flags = 0,
383 .panel_cfg = {
384 .width = 152,
385 .height = 91,
386 },
387 .meram_cfg = &lcd_meram_cfg,
388 }
389};
390
391static struct resource lcdc_resources[] = {
392 [0] = {
393 .name = "LCDC",
394 .start = 0xfe940000,
395 .end = 0xfe943fff,
396 .flags = IORESOURCE_MEM,
397 },
398 [1] = {
399 .start = intcs_evt2irq(0x580),
400 .flags = IORESOURCE_IRQ,
401 },
402};
403
404static struct platform_device lcdc_device = {
405 .name = "sh_mobile_lcdc_fb",
406 .num_resources = ARRAY_SIZE(lcdc_resources),
407 .resource = lcdc_resources,
408 .dev = {
409 .platform_data = &lcdc_info,
410 .coherent_dma_mask = DMA_BIT_MASK(32),
411 },
412};
413
414static struct gpio_backlight_platform_data gpio_backlight_data = {
415 .fbdev = &lcdc_device.dev,
416 .gpio = 31,
417 .def_value = 1,
418 .name = "backlight",
419};
420
421static struct platform_device gpio_backlight_device = {
422 .name = "gpio-backlight",
423 .dev = {
424 .platform_data = &gpio_backlight_data,
425 },
426};
427
428/* HDMI */
429static struct sh_mobile_hdmi_info hdmi_info = {
430 .flags = HDMI_SND_SRC_SPDIF,
431};
432
433static struct resource hdmi_resources[] = {
434 [0] = {
435 .name = "HDMI",
436 .start = 0xe6be0000,
437 .end = 0xe6be00ff,
438 .flags = IORESOURCE_MEM,
439 },
440 [1] = {
441 /* There's also an HDMI interrupt on INTCS @ 0x18e0 */
442 .start = evt2irq(0x17e0),
443 .flags = IORESOURCE_IRQ,
444 },
445};
446
447static struct platform_device hdmi_device = {
448 .name = "sh-mobile-hdmi",
449 .num_resources = ARRAY_SIZE(hdmi_resources),
450 .resource = hdmi_resources,
451 .id = -1,
452 .dev = {
453 .platform_data = &hdmi_info,
454 },
455};
456
457static const struct sh_mobile_meram_cfg hdmi_meram_cfg = {
458 .icb[0] = {
459 .meram_size = 0x100,
460 },
461 .icb[1] = {
462 .meram_size = 0x100,
463 },
464};
465
466static struct sh_mobile_lcdc_info hdmi_lcdc_info = {
467 .meram_dev = &mackerel_meram_info,
468 .clock_source = LCDC_CLK_EXTERNAL,
469 .ch[0] = {
470 .chan = LCDC_CHAN_MAINLCD,
471 .fourcc = V4L2_PIX_FMT_RGB565,
472 .interface_type = RGB24,
473 .clock_divider = 1,
474 .flags = LCDC_FLAGS_DWPOL,
475 .meram_cfg = &hdmi_meram_cfg,
476 .tx_dev = &hdmi_device,
477 }
478};
479
480static struct resource hdmi_lcdc_resources[] = {
481 [0] = {
482 .name = "LCDC1",
483 .start = 0xfe944000,
484 .end = 0xfe947fff,
485 .flags = IORESOURCE_MEM,
486 },
487 [1] = {
488 .start = intcs_evt2irq(0x1780),
489 .flags = IORESOURCE_IRQ,
490 },
491};
492
493static struct platform_device hdmi_lcdc_device = {
494 .name = "sh_mobile_lcdc_fb",
495 .num_resources = ARRAY_SIZE(hdmi_lcdc_resources),
496 .resource = hdmi_lcdc_resources,
497 .id = 1,
498 .dev = {
499 .platform_data = &hdmi_lcdc_info,
500 .coherent_dma_mask = DMA_BIT_MASK(32),
501 },
502};
503
504static struct asoc_simple_card_info fsi2_hdmi_info = {
505 .name = "HDMI",
506 .card = "FSI2B-HDMI",
507 .codec = "sh-mobile-hdmi",
508 .platform = "sh_fsi2",
509 .daifmt = SND_SOC_DAIFMT_CBS_CFS,
510 .cpu_dai = {
511 .name = "fsib-dai",
512 },
513 .codec_dai = {
514 .name = "sh_mobile_hdmi-hifi",
515 },
516};
517
518static struct platform_device fsi_hdmi_device = {
519 .name = "asoc-simple-card",
520 .id = 1,
521 .dev = {
522 .platform_data = &fsi2_hdmi_info,
523 .coherent_dma_mask = DMA_BIT_MASK(32),
524 .dma_mask = &fsi_hdmi_device.dev.coherent_dma_mask,
525 },
526};
527
528static void __init hdmi_init_pm_clock(void)
529{
530 struct clk *hdmi_ick = clk_get(&hdmi_device.dev, "ick");
531 int ret;
532 long rate;
533
534 if (IS_ERR(hdmi_ick)) {
535 ret = PTR_ERR(hdmi_ick);
536 pr_err("Cannot get HDMI ICK: %d\n", ret);
537 goto out;
538 }
539
540 ret = clk_set_parent(&sh7372_pllc2_clk, &sh7372_dv_clki_div2_clk);
541 if (ret < 0) {
542 pr_err("Cannot set PLLC2 parent: %d, %d users\n",
543 ret, sh7372_pllc2_clk.usecount);
544 goto out;
545 }
546
547 pr_debug("PLLC2 initial frequency %lu\n",
548 clk_get_rate(&sh7372_pllc2_clk));
549
550 rate = clk_round_rate(&sh7372_pllc2_clk, 594000000);
551 if (rate <= 0) {
552 pr_err("Cannot get suitable rate: %ld\n", rate);
553 ret = -EINVAL;
554 goto out;
555 }
556
557 ret = clk_set_rate(&sh7372_pllc2_clk, rate);
558 if (ret < 0) {
559 pr_err("Cannot set rate %ld: %d\n", rate, ret);
560 goto out;
561 }
562
563 pr_debug("PLLC2 set frequency %lu\n", rate);
564
565 ret = clk_set_parent(hdmi_ick, &sh7372_pllc2_clk);
566 if (ret < 0)
567 pr_err("Cannot set HDMI parent: %d\n", ret);
568
569out:
570 if (!IS_ERR(hdmi_ick))
571 clk_put(hdmi_ick);
572}
573
574/* USBHS0 is connected to CN22 which takes a USB Mini-B plug
575 *
576 * The sh7372 SoC has IRQ7 set aside for USBHS0 hotplug,
577 * but on this particular board IRQ7 is already used by
578 * the touch screen. This leaves us with software polling.
579 */
580#define USBHS0_POLL_INTERVAL (HZ * 5)
581
582struct usbhs_private {
583 void __iomem *usbphyaddr;
584 void __iomem *usbcrcaddr;
585 struct renesas_usbhs_platform_info info;
586 struct delayed_work work;
587 struct platform_device *pdev;
588};
589
590#define usbhs_get_priv(pdev) \
591 container_of(renesas_usbhs_get_info(pdev), \
592 struct usbhs_private, info)
593
594#define usbhs_is_connected(priv) \
595 (!((1 << 7) & __raw_readw(priv->usbcrcaddr)))
596
597static int usbhs_get_vbus(struct platform_device *pdev)
598{
599 return usbhs_is_connected(usbhs_get_priv(pdev));
600}
601
602static int usbhs_phy_reset(struct platform_device *pdev)
603{
604 struct usbhs_private *priv = usbhs_get_priv(pdev);
605
606 /* init phy */
607 __raw_writew(0x8a0a, priv->usbcrcaddr);
608
609 return 0;
610}
611
612static int usbhs0_get_id(struct platform_device *pdev)
613{
614 return USBHS_GADGET;
615}
616
617static void usbhs0_work_function(struct work_struct *work)
618{
619 struct usbhs_private *priv = container_of(work, struct usbhs_private,
620 work.work);
621
622 renesas_usbhs_call_notify_hotplug(priv->pdev);
623 schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL);
624}
625
626static int usbhs0_hardware_init(struct platform_device *pdev)
627{
628 struct usbhs_private *priv = usbhs_get_priv(pdev);
629
630 priv->pdev = pdev;
631 INIT_DELAYED_WORK(&priv->work, usbhs0_work_function);
632 schedule_delayed_work(&priv->work, USBHS0_POLL_INTERVAL);
633 return 0;
634}
635
636static int usbhs0_hardware_exit(struct platform_device *pdev)
637{
638 struct usbhs_private *priv = usbhs_get_priv(pdev);
639
640 cancel_delayed_work_sync(&priv->work);
641
642 return 0;
643}
644
645static struct usbhs_private usbhs0_private = {
646 .usbcrcaddr = IOMEM(0xe605810c), /* USBCR2 */
647 .info = {
648 .platform_callback = {
649 .hardware_init = usbhs0_hardware_init,
650 .hardware_exit = usbhs0_hardware_exit,
651 .phy_reset = usbhs_phy_reset,
652 .get_id = usbhs0_get_id,
653 .get_vbus = usbhs_get_vbus,
654 },
655 .driver_param = {
656 .buswait_bwait = 4,
657 .d0_tx_id = SHDMA_SLAVE_USB0_TX,
658 .d1_rx_id = SHDMA_SLAVE_USB0_RX,
659 },
660 },
661};
662
663static struct resource usbhs0_resources[] = {
664 [0] = {
665 .name = "USBHS0",
666 .start = 0xe6890000,
667 .end = 0xe68900e6 - 1,
668 .flags = IORESOURCE_MEM,
669 },
670 [1] = {
671 .start = evt2irq(0x1ca0) /* USB0_USB0I0 */,
672 .flags = IORESOURCE_IRQ,
673 },
674};
675
676static struct platform_device usbhs0_device = {
677 .name = "renesas_usbhs",
678 .id = 0,
679 .dev = {
680 .platform_data = &usbhs0_private.info,
681 },
682 .num_resources = ARRAY_SIZE(usbhs0_resources),
683 .resource = usbhs0_resources,
684};
685
686/* USBHS1 is connected to CN31 which takes a USB Mini-AB plug
687 *
688 * Use J30 to select between Host and Function. This setting
689 * can however not be detected by software. Hotplug of USBHS1
690 * is provided via IRQ8.
691 *
692 * Current USB1 works as "USB Host".
693 * - set J30 "short"
694 *
695 * If you want to use it as "USB gadget",
696 * - J30 "open"
697 * - modify usbhs1_get_id() USBHS_HOST -> USBHS_GADGET
698 * - add .get_vbus = usbhs_get_vbus in usbhs1_private
699 * - check usbhs0_device(pio)/usbhs1_device(irq) order in mackerel_devices.
700 */
701#define IRQ8 evt2irq(0x0300)
702#define USB_PHY_MODE (1 << 4)
703#define USB_PHY_INT_EN ((1 << 3) | (1 << 2))
704#define USB_PHY_ON (1 << 1)
705#define USB_PHY_OFF (1 << 0)
706#define USB_PHY_INT_CLR (USB_PHY_ON | USB_PHY_OFF)
707
708static irqreturn_t usbhs1_interrupt(int irq, void *data)
709{
710 struct platform_device *pdev = data;
711 struct usbhs_private *priv = usbhs_get_priv(pdev);
712
713 dev_dbg(&pdev->dev, "%s\n", __func__);
714
715 renesas_usbhs_call_notify_hotplug(pdev);
716
717 /* clear status */
718 __raw_writew(__raw_readw(priv->usbphyaddr) | USB_PHY_INT_CLR,
719 priv->usbphyaddr);
720
721 return IRQ_HANDLED;
722}
723
724static int usbhs1_hardware_init(struct platform_device *pdev)
725{
726 struct usbhs_private *priv = usbhs_get_priv(pdev);
727 int ret;
728
729 /* clear interrupt status */
730 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
731
732 ret = request_irq(IRQ8, usbhs1_interrupt, IRQF_TRIGGER_HIGH,
733 dev_name(&pdev->dev), pdev);
734 if (ret) {
735 dev_err(&pdev->dev, "request_irq err\n");
736 return ret;
737 }
738
739 /* enable USB phy interrupt */
740 __raw_writew(USB_PHY_MODE | USB_PHY_INT_EN, priv->usbphyaddr);
741
742 return 0;
743}
744
745static int usbhs1_hardware_exit(struct platform_device *pdev)
746{
747 struct usbhs_private *priv = usbhs_get_priv(pdev);
748
749 /* clear interrupt status */
750 __raw_writew(USB_PHY_MODE | USB_PHY_INT_CLR, priv->usbphyaddr);
751
752 free_irq(IRQ8, pdev);
753
754 return 0;
755}
756
757static int usbhs1_get_id(struct platform_device *pdev)
758{
759 return USBHS_HOST;
760}
761
762static u32 usbhs1_pipe_cfg[] = {
763 USB_ENDPOINT_XFER_CONTROL,
764 USB_ENDPOINT_XFER_ISOC,
765 USB_ENDPOINT_XFER_ISOC,
766 USB_ENDPOINT_XFER_BULK,
767 USB_ENDPOINT_XFER_BULK,
768 USB_ENDPOINT_XFER_BULK,
769 USB_ENDPOINT_XFER_INT,
770 USB_ENDPOINT_XFER_INT,
771 USB_ENDPOINT_XFER_INT,
772 USB_ENDPOINT_XFER_BULK,
773 USB_ENDPOINT_XFER_BULK,
774 USB_ENDPOINT_XFER_BULK,
775 USB_ENDPOINT_XFER_BULK,
776 USB_ENDPOINT_XFER_BULK,
777 USB_ENDPOINT_XFER_BULK,
778 USB_ENDPOINT_XFER_BULK,
779};
780
781static struct usbhs_private usbhs1_private = {
782 .usbphyaddr = IOMEM(0xe60581e2), /* USBPHY1INTAP */
783 .usbcrcaddr = IOMEM(0xe6058130), /* USBCR4 */
784 .info = {
785 .platform_callback = {
786 .hardware_init = usbhs1_hardware_init,
787 .hardware_exit = usbhs1_hardware_exit,
788 .get_id = usbhs1_get_id,
789 .phy_reset = usbhs_phy_reset,
790 },
791 .driver_param = {
792 .buswait_bwait = 4,
793 .has_otg = 1,
794 .pipe_type = usbhs1_pipe_cfg,
795 .pipe_size = ARRAY_SIZE(usbhs1_pipe_cfg),
796 .d0_tx_id = SHDMA_SLAVE_USB1_TX,
797 .d1_rx_id = SHDMA_SLAVE_USB1_RX,
798 },
799 },
800};
801
802static struct resource usbhs1_resources[] = {
803 [0] = {
804 .name = "USBHS1",
805 .start = 0xe68b0000,
806 .end = 0xe68b00e6 - 1,
807 .flags = IORESOURCE_MEM,
808 },
809 [1] = {
810 .start = evt2irq(0x1ce0) /* USB1_USB1I0 */,
811 .flags = IORESOURCE_IRQ,
812 },
813};
814
815static struct platform_device usbhs1_device = {
816 .name = "renesas_usbhs",
817 .id = 1,
818 .dev = {
819 .platform_data = &usbhs1_private.info,
820 .dma_mask = &usbhs1_device.dev.coherent_dma_mask,
821 .coherent_dma_mask = DMA_BIT_MASK(32),
822 },
823 .num_resources = ARRAY_SIZE(usbhs1_resources),
824 .resource = usbhs1_resources,
825};
826
827/* LED */
828static struct gpio_led mackerel_leds[] = {
829 {
830 .name = "led0",
831 .gpio = 0,
832 .default_state = LEDS_GPIO_DEFSTATE_ON,
833 },
834 {
835 .name = "led1",
836 .gpio = 1,
837 .default_state = LEDS_GPIO_DEFSTATE_ON,
838 },
839 {
840 .name = "led2",
841 .gpio = 2,
842 .default_state = LEDS_GPIO_DEFSTATE_ON,
843 },
844 {
845 .name = "led3",
846 .gpio = 159,
847 .default_state = LEDS_GPIO_DEFSTATE_ON,
848 }
849};
850
851static struct gpio_led_platform_data mackerel_leds_pdata = {
852 .leds = mackerel_leds,
853 .num_leds = ARRAY_SIZE(mackerel_leds),
854};
855
856static struct platform_device leds_device = {
857 .name = "leds-gpio",
858 .id = 0,
859 .dev = {
860 .platform_data = &mackerel_leds_pdata,
861 },
862};
863
864/* FSI */
865#define IRQ_FSI evt2irq(0x1840)
866static struct sh_fsi_platform_info fsi_info = {
867 .port_a = {
868 .tx_id = SHDMA_SLAVE_FSIA_TX,
869 .rx_id = SHDMA_SLAVE_FSIA_RX,
870 },
871 .port_b = {
872 .flags = SH_FSI_CLK_CPG |
873 SH_FSI_FMT_SPDIF,
874 }
875};
876
877static struct resource fsi_resources[] = {
878 [0] = {
879 /* we need 0xFE1F0000 to access DMA
880 * instead of 0xFE3C0000 */
881 .name = "FSI",
882 .start = 0xFE1F0000,
883 .end = 0xFE1F0400 - 1,
884 .flags = IORESOURCE_MEM,
885 },
886 [1] = {
887 .start = IRQ_FSI,
888 .flags = IORESOURCE_IRQ,
889 },
890};
891
892static struct platform_device fsi_device = {
893 .name = "sh_fsi2",
894 .id = -1,
895 .num_resources = ARRAY_SIZE(fsi_resources),
896 .resource = fsi_resources,
897 .dev = {
898 .platform_data = &fsi_info,
899 },
900};
901
902static struct asoc_simple_card_info fsi2_ak4643_info = {
903 .name = "AK4643",
904 .card = "FSI2A-AK4643",
905 .codec = "ak4642-codec.0-0013",
906 .platform = "sh_fsi2",
907 .daifmt = SND_SOC_DAIFMT_LEFT_J | SND_SOC_DAIFMT_CBM_CFM,
908 .cpu_dai = {
909 .name = "fsia-dai",
910 },
911 .codec_dai = {
912 .name = "ak4642-hifi",
913 .sysclk = 11289600,
914 },
915};
916
917static struct platform_device fsi_ak4643_device = {
918 .name = "asoc-simple-card",
919 .dev = {
920 .platform_data = &fsi2_ak4643_info,
921 .coherent_dma_mask = DMA_BIT_MASK(32),
922 .dma_mask = &fsi_ak4643_device.dev.coherent_dma_mask,
923 },
924};
925
926/* FLCTL */
927static struct mtd_partition nand_partition_info[] = {
928 {
929 .name = "system",
930 .offset = 0,
931 .size = 128 * 1024 * 1024,
932 },
933 {
934 .name = "userdata",
935 .offset = MTDPART_OFS_APPEND,
936 .size = 256 * 1024 * 1024,
937 },
938 {
939 .name = "cache",
940 .offset = MTDPART_OFS_APPEND,
941 .size = 128 * 1024 * 1024,
942 },
943};
944
945static struct resource nand_flash_resources[] = {
946 [0] = {
947 .start = 0xe6a30000,
948 .end = 0xe6a3009b,
949 .flags = IORESOURCE_MEM,
950 },
951 [1] = {
952 .start = evt2irq(0x0d80), /* flstei: status error irq */
953 .flags = IORESOURCE_IRQ,
954 },
955};
956
957static struct sh_flctl_platform_data nand_flash_data = {
958 .parts = nand_partition_info,
959 .nr_parts = ARRAY_SIZE(nand_partition_info),
960 .flcmncr_val = CLK_16B_12L_4H | TYPESEL_SET
961 | SHBUSSEL | SEL_16BIT | SNAND_E,
962 .use_holden = 1,
963};
964
965static struct platform_device nand_flash_device = {
966 .name = "sh_flctl",
967 .resource = nand_flash_resources,
968 .num_resources = ARRAY_SIZE(nand_flash_resources),
969 .dev = {
970 .platform_data = &nand_flash_data,
971 },
972};
973
974/* SDHI0 */
975static struct sh_mobile_sdhi_info sdhi0_info = {
976 .dma_slave_tx = SHDMA_SLAVE_SDHI0_TX,
977 .dma_slave_rx = SHDMA_SLAVE_SDHI0_RX,
978 .tmio_flags = TMIO_MMC_USE_GPIO_CD,
979 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ,
980 .cd_gpio = 172,
981};
982
983static struct resource sdhi0_resources[] = {
984 {
985 .name = "SDHI0",
986 .start = 0xe6850000,
987 .end = 0xe68500ff,
988 .flags = IORESOURCE_MEM,
989 }, {
990 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
991 .start = evt2irq(0x0e20) /* SDHI0_SDHI0I1 */,
992 .flags = IORESOURCE_IRQ,
993 }, {
994 .name = SH_MOBILE_SDHI_IRQ_SDIO,
995 .start = evt2irq(0x0e40) /* SDHI0_SDHI0I2 */,
996 .flags = IORESOURCE_IRQ,
997 },
998};
999
1000static struct platform_device sdhi0_device = {
1001 .name = "sh_mobile_sdhi",
1002 .num_resources = ARRAY_SIZE(sdhi0_resources),
1003 .resource = sdhi0_resources,
1004 .id = 0,
1005 .dev = {
1006 .platform_data = &sdhi0_info,
1007 },
1008};
1009
1010#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1011/* SDHI1 */
1012
1013/* GPIO 41 can trigger IRQ8, but it is used by USBHS1, we have to poll */
1014static struct sh_mobile_sdhi_info sdhi1_info = {
1015 .dma_slave_tx = SHDMA_SLAVE_SDHI1_TX,
1016 .dma_slave_rx = SHDMA_SLAVE_SDHI1_RX,
1017 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
1018 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
1019 MMC_CAP_NEEDS_POLL,
1020 .cd_gpio = 41,
1021};
1022
1023static struct resource sdhi1_resources[] = {
1024 {
1025 .name = "SDHI1",
1026 .start = 0xe6860000,
1027 .end = 0xe68600ff,
1028 .flags = IORESOURCE_MEM,
1029 }, {
1030 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
1031 .start = evt2irq(0x0ea0), /* SDHI1_SDHI1I1 */
1032 .flags = IORESOURCE_IRQ,
1033 }, {
1034 .name = SH_MOBILE_SDHI_IRQ_SDIO,
1035 .start = evt2irq(0x0ec0), /* SDHI1_SDHI1I2 */
1036 .flags = IORESOURCE_IRQ,
1037 },
1038};
1039
1040static struct platform_device sdhi1_device = {
1041 .name = "sh_mobile_sdhi",
1042 .num_resources = ARRAY_SIZE(sdhi1_resources),
1043 .resource = sdhi1_resources,
1044 .id = 1,
1045 .dev = {
1046 .platform_data = &sdhi1_info,
1047 },
1048};
1049#endif
1050
1051/* SDHI2 */
1052
1053/*
1054 * The card detect pin of the top SD/MMC slot (CN23) is active low and is
1055 * connected to GPIO SCIFB_SCK of SH7372 (GPIO 162).
1056 */
1057static struct sh_mobile_sdhi_info sdhi2_info = {
1058 .dma_slave_tx = SHDMA_SLAVE_SDHI2_TX,
1059 .dma_slave_rx = SHDMA_SLAVE_SDHI2_RX,
1060 .tmio_flags = TMIO_MMC_WRPROTECT_DISABLE | TMIO_MMC_USE_GPIO_CD,
1061 .tmio_caps = MMC_CAP_SD_HIGHSPEED | MMC_CAP_SDIO_IRQ |
1062 MMC_CAP_NEEDS_POLL,
1063 .cd_gpio = 162,
1064};
1065
1066static struct resource sdhi2_resources[] = {
1067 {
1068 .name = "SDHI2",
1069 .start = 0xe6870000,
1070 .end = 0xe68700ff,
1071 .flags = IORESOURCE_MEM,
1072 }, {
1073 .name = SH_MOBILE_SDHI_IRQ_SDCARD,
1074 .start = evt2irq(0x1220), /* SDHI2_SDHI2I1 */
1075 .flags = IORESOURCE_IRQ,
1076 }, {
1077 .name = SH_MOBILE_SDHI_IRQ_SDIO,
1078 .start = evt2irq(0x1240), /* SDHI2_SDHI2I2 */
1079 .flags = IORESOURCE_IRQ,
1080 },
1081};
1082
1083static struct platform_device sdhi2_device = {
1084 .name = "sh_mobile_sdhi",
1085 .num_resources = ARRAY_SIZE(sdhi2_resources),
1086 .resource = sdhi2_resources,
1087 .id = 2,
1088 .dev = {
1089 .platform_data = &sdhi2_info,
1090 },
1091};
1092
1093/* SH_MMCIF */
1094#if IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1095static struct resource sh_mmcif_resources[] = {
1096 [0] = {
1097 .name = "MMCIF",
1098 .start = 0xE6BD0000,
1099 .end = 0xE6BD00FF,
1100 .flags = IORESOURCE_MEM,
1101 },
1102 [1] = {
1103 /* MMC ERR */
1104 .start = evt2irq(0x1ac0),
1105 .flags = IORESOURCE_IRQ,
1106 },
1107 [2] = {
1108 /* MMC NOR */
1109 .start = evt2irq(0x1ae0),
1110 .flags = IORESOURCE_IRQ,
1111 },
1112};
1113
1114static struct sh_mmcif_plat_data sh_mmcif_plat = {
1115 .sup_pclk = 0,
1116 .caps = MMC_CAP_4_BIT_DATA |
1117 MMC_CAP_8_BIT_DATA |
1118 MMC_CAP_NEEDS_POLL,
1119 .use_cd_gpio = true,
1120 /* card detect pin for SD/MMC slot (CN7) */
1121 .cd_gpio = 41,
1122 .slave_id_tx = SHDMA_SLAVE_MMCIF_TX,
1123 .slave_id_rx = SHDMA_SLAVE_MMCIF_RX,
1124};
1125
1126static struct platform_device sh_mmcif_device = {
1127 .name = "sh_mmcif",
1128 .id = 0,
1129 .dev = {
1130 .dma_mask = NULL,
1131 .coherent_dma_mask = 0xffffffff,
1132 .platform_data = &sh_mmcif_plat,
1133 },
1134 .num_resources = ARRAY_SIZE(sh_mmcif_resources),
1135 .resource = sh_mmcif_resources,
1136};
1137#endif
1138
1139static int mackerel_camera_add(struct soc_camera_device *icd);
1140static void mackerel_camera_del(struct soc_camera_device *icd);
1141
1142static int camera_set_capture(struct soc_camera_platform_info *info,
1143 int enable)
1144{
1145 return 0; /* camera sensor always enabled */
1146}
1147
1148static struct soc_camera_platform_info camera_info = {
1149 .format_name = "UYVY",
1150 .format_depth = 16,
1151 .format = {
1152 .code = MEDIA_BUS_FMT_UYVY8_2X8,
1153 .colorspace = V4L2_COLORSPACE_SMPTE170M,
1154 .field = V4L2_FIELD_NONE,
1155 .width = 640,
1156 .height = 480,
1157 },
1158 .mbus_param = V4L2_MBUS_PCLK_SAMPLE_RISING | V4L2_MBUS_MASTER |
1159 V4L2_MBUS_VSYNC_ACTIVE_HIGH | V4L2_MBUS_HSYNC_ACTIVE_HIGH |
1160 V4L2_MBUS_DATA_ACTIVE_HIGH,
1161 .mbus_type = V4L2_MBUS_PARALLEL,
1162 .set_capture = camera_set_capture,
1163};
1164
1165static struct soc_camera_link camera_link = {
1166 .bus_id = 0,
1167 .add_device = mackerel_camera_add,
1168 .del_device = mackerel_camera_del,
1169 .module_name = "soc_camera_platform",
1170 .priv = &camera_info,
1171};
1172
1173static struct platform_device *camera_device;
1174
1175static void mackerel_camera_release(struct device *dev)
1176{
1177 soc_camera_platform_release(&camera_device);
1178}
1179
1180static int mackerel_camera_add(struct soc_camera_device *icd)
1181{
1182 return soc_camera_platform_add(icd, &camera_device, &camera_link,
1183 mackerel_camera_release, 0);
1184}
1185
1186static void mackerel_camera_del(struct soc_camera_device *icd)
1187{
1188 soc_camera_platform_del(icd, camera_device, &camera_link);
1189}
1190
1191static struct sh_mobile_ceu_info sh_mobile_ceu_info = {
1192 .flags = SH_CEU_FLAG_USE_8BIT_BUS,
1193 .max_width = 8188,
1194 .max_height = 8188,
1195};
1196
1197static struct resource ceu_resources[] = {
1198 [0] = {
1199 .name = "CEU",
1200 .start = 0xfe910000,
1201 .end = 0xfe91009f,
1202 .flags = IORESOURCE_MEM,
1203 },
1204 [1] = {
1205 .start = intcs_evt2irq(0x880),
1206 .flags = IORESOURCE_IRQ,
1207 },
1208 [2] = {
1209 /* place holder for contiguous memory */
1210 },
1211};
1212
1213static struct platform_device ceu_device = {
1214 .name = "sh_mobile_ceu",
1215 .id = 0, /* "ceu0" clock */
1216 .num_resources = ARRAY_SIZE(ceu_resources),
1217 .resource = ceu_resources,
1218 .dev = {
1219 .platform_data = &sh_mobile_ceu_info,
1220 .coherent_dma_mask = 0xffffffff,
1221 },
1222};
1223
1224static struct platform_device mackerel_camera = {
1225 .name = "soc-camera-pdrv",
1226 .id = 0,
1227 .dev = {
1228 .platform_data = &camera_link,
1229 },
1230};
1231
1232static struct platform_device *mackerel_devices[] __initdata = {
1233 &nor_flash_device,
1234 &smc911x_device,
1235 &lcdc_device,
1236 &gpio_backlight_device,
1237 &usbhs0_device,
1238 &usbhs1_device,
1239 &leds_device,
1240 &fsi_device,
1241 &fsi_ak4643_device,
1242 &fsi_hdmi_device,
1243 &nand_flash_device,
1244 &sdhi0_device,
1245#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1246 &sdhi1_device,
1247#else
1248 &sh_mmcif_device,
1249#endif
1250 &sdhi2_device,
1251 &ceu_device,
1252 &mackerel_camera,
1253 &hdmi_device,
1254 &hdmi_lcdc_device,
1255 &meram_device,
1256};
1257
1258/* Keypad Initialization */
1259#define KEYPAD_BUTTON(ev_type, ev_code, act_low) \
1260{ \
1261 .type = ev_type, \
1262 .code = ev_code, \
1263 .active_low = act_low, \
1264}
1265
1266#define KEYPAD_BUTTON_LOW(event_code) KEYPAD_BUTTON(EV_KEY, event_code, 1)
1267
1268static struct tca6416_button mackerel_gpio_keys[] = {
1269 KEYPAD_BUTTON_LOW(KEY_HOME),
1270 KEYPAD_BUTTON_LOW(KEY_MENU),
1271 KEYPAD_BUTTON_LOW(KEY_BACK),
1272 KEYPAD_BUTTON_LOW(KEY_POWER),
1273};
1274
1275static struct tca6416_keys_platform_data mackerel_tca6416_keys_info = {
1276 .buttons = mackerel_gpio_keys,
1277 .nbuttons = ARRAY_SIZE(mackerel_gpio_keys),
1278 .rep = 1,
1279 .use_polling = 0,
1280 .pinmask = 0x000F,
1281};
1282
1283/* I2C */
1284#define IRQ7 evt2irq(0x02e0)
1285#define IRQ9 evt2irq(0x0320)
1286
1287static struct i2c_board_info i2c0_devices[] = {
1288 {
1289 I2C_BOARD_INFO("ak4643", 0x13),
1290 },
1291 /* Keypad */
1292 {
1293 I2C_BOARD_INFO("tca6408-keys", 0x20),
1294 .platform_data = &mackerel_tca6416_keys_info,
1295 .irq = IRQ9,
1296 },
1297 /* Touchscreen */
1298 {
1299 I2C_BOARD_INFO("st1232-ts", 0x55),
1300 .irq = IRQ7,
1301 },
1302};
1303
1304#define IRQ21 evt2irq(0x32a0)
1305
1306static struct i2c_board_info i2c1_devices[] = {
1307 /* Accelerometer */
1308 {
1309 I2C_BOARD_INFO("adxl34x", 0x53),
1310 .irq = IRQ21,
1311 },
1312};
1313
1314static unsigned long pin_pulldown_conf[] = {
1315 PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_DOWN, 0),
1316};
1317
1318static const struct pinctrl_map mackerel_pinctrl_map[] = {
1319 /* ADXL34X */
1320 PIN_MAP_MUX_GROUP_DEFAULT("1-0053", "pfc-sh7372",
1321 "intc_irq21", "intc"),
1322 /* CEU */
1323 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
1324 "ceu_data_0_7", "ceu"),
1325 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
1326 "ceu_clk_0", "ceu"),
1327 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
1328 "ceu_sync", "ceu"),
1329 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_ceu.0", "pfc-sh7372",
1330 "ceu_field", "ceu"),
1331 /* FLCTL */
1332 PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
1333 "flctl_data", "flctl"),
1334 PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
1335 "flctl_ce0", "flctl"),
1336 PIN_MAP_MUX_GROUP_DEFAULT("sh_flctl.0", "pfc-sh7372",
1337 "flctl_ctrl", "flctl"),
1338 /* FSIA (AK4643) */
1339 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
1340 "fsia_sclk_in", "fsia"),
1341 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
1342 "fsia_data_in", "fsia"),
1343 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.0", "pfc-sh7372",
1344 "fsia_data_out", "fsia"),
1345 /* FSIB (HDMI) */
1346 PIN_MAP_MUX_GROUP_DEFAULT("asoc-simple-card.1", "pfc-sh7372",
1347 "fsib_mclk_in", "fsib"),
1348 /* HDMI */
1349 PIN_MAP_MUX_GROUP_DEFAULT("sh-mobile-hdmi", "pfc-sh7372",
1350 "hdmi", "hdmi"),
1351 /* LCDC */
1352 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
1353 "lcd_data24", "lcd"),
1354 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh7372",
1355 "lcd_sync", "lcd"),
1356 /* SCIFA0 */
1357 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.0", "pfc-sh7372",
1358 "scifa0_data", "scifa0"),
1359 /* SCIFA2 (GT-720F GPS module) */
1360 PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh7372",
1361 "scifa2_data", "scifa2"),
1362 /* SDHI0 */
1363 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1364 "sdhi0_data4", "sdhi0"),
1365 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1366 "sdhi0_ctrl", "sdhi0"),
1367 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1368 "sdhi0_wp", "sdhi0"),
1369 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
1370 "intc_irq26_1", "intc"),
1371 /* SDHI1 */
1372#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1373 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1374 "sdhi1_data4", "sdhi1"),
1375 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
1376 "sdhi1_ctrl", "sdhi1"),
1377#else
1378 /* MMCIF */
1379 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1380 "mmc0_data8_0", "mmc0"),
1381 PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
1382 "mmc0_ctrl_0", "mmc0"),
1383#endif
1384 /* SDHI2 */
1385 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
1386 "sdhi2_data4", "sdhi2"),
1387 PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh7372",
1388 "sdhi2_ctrl", "sdhi2"),
1389 /* SMSC911X */
1390 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
1391 "bsc_cs5a", "bsc"),
1392 PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-sh7372",
1393 "intc_irq6_0", "intc"),
1394 /* ST1232 */
1395 PIN_MAP_MUX_GROUP_DEFAULT("0-0055", "pfc-sh7372",
1396 "intc_irq7_0", "intc"),
1397 /* TCA6416 */
1398 PIN_MAP_MUX_GROUP_DEFAULT("0-0020", "pfc-sh7372",
1399 "intc_irq9_0", "intc"),
1400 /* USBHS0 */
1401 PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
1402 "usb0_vbus", "usb0"),
1403 PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.0", "pfc-sh7372",
1404 "usb0_vbus", pin_pulldown_conf),
1405 /* USBHS1 */
1406 PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
1407 "usb1_vbus", "usb1"),
1408 PIN_MAP_CONFIGS_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
1409 "usb1_vbus", pin_pulldown_conf),
1410 PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs.1", "pfc-sh7372",
1411 "usb1_otg_id_0", "usb1"),
1412};
1413
1414#define GPIO_PORT9CR IOMEM(0xE6051009)
1415#define GPIO_PORT10CR IOMEM(0xE605100A)
1416#define SRCR4 IOMEM(0xe61580bc)
1417#define USCCR1 IOMEM(0xE6058144)
1418static void __init mackerel_init(void)
1419{
1420 static struct pm_domain_device domain_devices[] __initdata = {
1421 { "A4LC", &lcdc_device, },
1422 { "A4LC", &hdmi_lcdc_device, },
1423 { "A4LC", &meram_device, },
1424 { "A4MP", &fsi_device, },
1425 { "A3SP", &usbhs0_device, },
1426 { "A3SP", &usbhs1_device, },
1427 { "A3SP", &nand_flash_device, },
1428 { "A3SP", &sdhi0_device, },
1429#if !IS_ENABLED(CONFIG_MMC_SH_MMCIF)
1430 { "A3SP", &sdhi1_device, },
1431#else
1432 { "A3SP", &sh_mmcif_device, },
1433#endif
1434 { "A3SP", &sdhi2_device, },
1435 { "A4R", &ceu_device, },
1436 };
1437 u32 srcr4;
1438 struct clk *clk;
1439
1440 regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
1441 ARRAY_SIZE(fixed1v8_power_consumers), 1800000);
1442 regulator_register_always_on(1, "fixed-3.3V", fixed3v3_power_consumers,
1443 ARRAY_SIZE(fixed3v3_power_consumers), 3300000);
1444 regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
1445
1446 /* External clock source */
1447 clk_set_rate(&sh7372_dv_clki_clk, 27000000);
1448
1449 pinctrl_register_mappings(mackerel_pinctrl_map,
1450 ARRAY_SIZE(mackerel_pinctrl_map));
1451 sh7372_pinmux_init();
1452
1453 gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
1454
1455 /* FSI2 port A (ak4643) */
1456 gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
1457
1458 gpio_request(9, NULL);
1459 gpio_request(10, NULL);
1460 gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
1461 gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
1462
1463 intc_set_priority(IRQ_FSI, 3); /* irq priority FSI(3) > SMSC911X(2) */
1464
1465 /* FSI2 port B (HDMI) */
1466 __raw_writew(__raw_readw(USCCR1) & ~(1 << 6), USCCR1); /* use SPDIF */
1467
1468 /* set SPU2 clock to 119.6 MHz */
1469 clk = clk_get(NULL, "spu_clk");
1470 if (!IS_ERR(clk)) {
1471 clk_set_rate(clk, clk_round_rate(clk, 119600000));
1472 clk_put(clk);
1473 }
1474
1475 /* Keypad */
1476 irq_set_irq_type(IRQ9, IRQ_TYPE_LEVEL_HIGH);
1477
1478 /* Touchscreen */
1479 irq_set_irq_type(IRQ7, IRQ_TYPE_LEVEL_LOW);
1480
1481 /* Accelerometer */
1482 irq_set_irq_type(IRQ21, IRQ_TYPE_LEVEL_HIGH);
1483
1484 /* Reset HDMI, must be held at least one EXTALR (32768Hz) period */
1485 srcr4 = __raw_readl(SRCR4);
1486 __raw_writel(srcr4 | (1 << 13), SRCR4);
1487 udelay(50);
1488 __raw_writel(srcr4 & ~(1 << 13), SRCR4);
1489
1490 i2c_register_board_info(0, i2c0_devices,
1491 ARRAY_SIZE(i2c0_devices));
1492 i2c_register_board_info(1, i2c1_devices,
1493 ARRAY_SIZE(i2c1_devices));
1494
1495 sh7372_add_standard_devices();
1496
1497 platform_add_devices(mackerel_devices, ARRAY_SIZE(mackerel_devices));
1498
1499 rmobile_add_devices_to_domains(domain_devices,
1500 ARRAY_SIZE(domain_devices));
1501
1502 hdmi_init_pm_clock();
1503 sh7372_pm_init();
1504 pm_clk_add(&fsi_device.dev, "spu2");
1505 pm_clk_add(&hdmi_lcdc_device.dev, "hdmi");
1506}
1507
1508static const char *mackerel_boards_compat_dt[] __initdata = {
1509 "renesas,mackerel",
1510 NULL,
1511};
1512
1513DT_MACHINE_START(MACKEREL_DT, "mackerel")
1514 .map_io = sh7372_map_io,
1515 .init_early = sh7372_add_early_devices,
1516 .init_irq = sh7372_init_irq,
1517 .handle_irq = shmobile_handle_irq_intc,
1518 .init_machine = mackerel_init,
1519 .init_late = sh7372_pm_init_late,
1520 .init_time = sh7372_earlytimer_init,
1521 .dt_compat = mackerel_boards_compat_dt,
1522MACHINE_END
diff --git a/arch/arm/mach-shmobile/clock-sh7372.c b/arch/arm/mach-shmobile/clock-sh7372.c
deleted file mode 100644
index 3bc92f46060e..000000000000
--- a/arch/arm/mach-shmobile/clock-sh7372.c
+++ /dev/null
@@ -1,620 +0,0 @@
1/*
2 * SH7372 clock framework support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/init.h>
16#include <linux/kernel.h>
17#include <linux/io.h>
18#include <linux/sh_clk.h>
19#include <linux/clkdev.h>
20#include "clock.h"
21#include "common.h"
22
23/* SH7372 registers */
24#define FRQCRA IOMEM(0xe6150000)
25#define FRQCRB IOMEM(0xe6150004)
26#define FRQCRC IOMEM(0xe61500e0)
27#define FRQCRD IOMEM(0xe61500e4)
28#define VCLKCR1 IOMEM(0xe6150008)
29#define VCLKCR2 IOMEM(0xe615000c)
30#define VCLKCR3 IOMEM(0xe615001c)
31#define FMSICKCR IOMEM(0xe6150010)
32#define FMSOCKCR IOMEM(0xe6150014)
33#define FSIACKCR IOMEM(0xe6150018)
34#define FSIBCKCR IOMEM(0xe6150090)
35#define SUBCKCR IOMEM(0xe6150080)
36#define SPUCKCR IOMEM(0xe6150084)
37#define VOUCKCR IOMEM(0xe6150088)
38#define HDMICKCR IOMEM(0xe6150094)
39#define DSITCKCR IOMEM(0xe6150060)
40#define DSI0PCKCR IOMEM(0xe6150064)
41#define DSI1PCKCR IOMEM(0xe6150098)
42#define PLLC01CR IOMEM(0xe6150028)
43#define PLLC2CR IOMEM(0xe615002c)
44#define RMSTPCR0 IOMEM(0xe6150110)
45#define RMSTPCR1 IOMEM(0xe6150114)
46#define RMSTPCR2 IOMEM(0xe6150118)
47#define RMSTPCR3 IOMEM(0xe615011c)
48#define RMSTPCR4 IOMEM(0xe6150120)
49#define SMSTPCR0 IOMEM(0xe6150130)
50#define SMSTPCR1 IOMEM(0xe6150134)
51#define SMSTPCR2 IOMEM(0xe6150138)
52#define SMSTPCR3 IOMEM(0xe615013c)
53#define SMSTPCR4 IOMEM(0xe6150140)
54
55#define FSIDIVA 0xFE1F8000
56#define FSIDIVB 0xFE1F8008
57
58/* Platforms must set frequency on their DV_CLKI pin */
59struct clk sh7372_dv_clki_clk = {
60};
61
62/* Fixed 32 KHz root clock from EXTALR pin */
63static struct clk r_clk = {
64 .rate = 32768,
65};
66
67/*
68 * 26MHz default rate for the EXTAL1 root input clock.
69 * If needed, reset this with clk_set_rate() from the platform code.
70 */
71struct clk sh7372_extal1_clk = {
72 .rate = 26000000,
73};
74
75/*
76 * 48MHz default rate for the EXTAL2 root input clock.
77 * If needed, reset this with clk_set_rate() from the platform code.
78 */
79struct clk sh7372_extal2_clk = {
80 .rate = 48000000,
81};
82
83SH_CLK_RATIO(div2, 1, 2);
84
85SH_FIXED_RATIO_CLKg(sh7372_dv_clki_div2_clk, sh7372_dv_clki_clk, div2);
86SH_FIXED_RATIO_CLK(extal1_div2_clk, sh7372_extal1_clk, div2);
87SH_FIXED_RATIO_CLK(extal2_div2_clk, sh7372_extal2_clk, div2);
88SH_FIXED_RATIO_CLK(extal2_div4_clk, extal2_div2_clk, div2);
89
90/* PLLC0 and PLLC1 */
91static unsigned long pllc01_recalc(struct clk *clk)
92{
93 unsigned long mult = 1;
94
95 if (__raw_readl(PLLC01CR) & (1 << 14))
96 mult = (((__raw_readl(clk->enable_reg) >> 24) & 0x3f) + 1) * 2;
97
98 return clk->parent->rate * mult;
99}
100
101static struct sh_clk_ops pllc01_clk_ops = {
102 .recalc = pllc01_recalc,
103};
104
105static struct clk pllc0_clk = {
106 .ops = &pllc01_clk_ops,
107 .flags = CLK_ENABLE_ON_INIT,
108 .parent = &extal1_div2_clk,
109 .enable_reg = (void __iomem *)FRQCRC,
110};
111
112static struct clk pllc1_clk = {
113 .ops = &pllc01_clk_ops,
114 .flags = CLK_ENABLE_ON_INIT,
115 .parent = &extal1_div2_clk,
116 .enable_reg = (void __iomem *)FRQCRA,
117};
118
119/* Divide PLLC1 by two */
120SH_FIXED_RATIO_CLK(pllc1_div2_clk, pllc1_clk, div2);
121
122/* PLLC2 */
123
124/* Indices are important - they are the actual src selecting values */
125static struct clk *pllc2_parent[] = {
126 [0] = &extal1_div2_clk,
127 [1] = &extal2_div2_clk,
128 [2] = &sh7372_dv_clki_div2_clk,
129};
130
131/* Only multipliers 20 * 2 to 46 * 2 are valid, last entry for CPUFREQ_TABLE_END */
132static struct cpufreq_frequency_table pllc2_freq_table[29];
133
134static void pllc2_table_rebuild(struct clk *clk)
135{
136 int i;
137
138 /* Initialise PLLC2 frequency table */
139 for (i = 0; i < ARRAY_SIZE(pllc2_freq_table) - 2; i++) {
140 pllc2_freq_table[i].frequency = clk->parent->rate * (i + 20) * 2;
141 pllc2_freq_table[i].driver_data = i;
142 }
143
144 /* This is a special entry - switching PLL off makes it a repeater */
145 pllc2_freq_table[i].frequency = clk->parent->rate;
146 pllc2_freq_table[i].driver_data = i;
147
148 pllc2_freq_table[++i].frequency = CPUFREQ_TABLE_END;
149 pllc2_freq_table[i].driver_data = i;
150}
151
152static unsigned long pllc2_recalc(struct clk *clk)
153{
154 unsigned long mult = 1;
155
156 pllc2_table_rebuild(clk);
157
158 /*
159 * If the PLL is off, mult == 1, clk->rate will be updated in
160 * pllc2_enable().
161 */
162 if (__raw_readl(PLLC2CR) & (1 << 31))
163 mult = (((__raw_readl(PLLC2CR) >> 24) & 0x3f) + 1) * 2;
164
165 return clk->parent->rate * mult;
166}
167
168static long pllc2_round_rate(struct clk *clk, unsigned long rate)
169{
170 return clk_rate_table_round(clk, clk->freq_table, rate);
171}
172
173static int pllc2_enable(struct clk *clk)
174{
175 int i;
176
177 __raw_writel(__raw_readl(PLLC2CR) | 0x80000000, PLLC2CR);
178
179 for (i = 0; i < 100; i++)
180 if (__raw_readl(PLLC2CR) & 0x80000000) {
181 clk->rate = pllc2_recalc(clk);
182 return 0;
183 }
184
185 pr_err("%s(): timeout!\n", __func__);
186
187 return -ETIMEDOUT;
188}
189
190static void pllc2_disable(struct clk *clk)
191{
192 __raw_writel(__raw_readl(PLLC2CR) & ~0x80000000, PLLC2CR);
193}
194
195static int pllc2_set_rate(struct clk *clk, unsigned long rate)
196{
197 unsigned long value;
198 int idx;
199
200 idx = clk_rate_table_find(clk, clk->freq_table, rate);
201 if (idx < 0)
202 return idx;
203
204 if (rate == clk->parent->rate)
205 return -EINVAL;
206
207 value = __raw_readl(PLLC2CR) & ~(0x3f << 24);
208
209 __raw_writel(value | ((idx + 19) << 24), PLLC2CR);
210
211 clk->rate = clk->freq_table[idx].frequency;
212
213 return 0;
214}
215
216static int pllc2_set_parent(struct clk *clk, struct clk *parent)
217{
218 u32 value;
219 int ret, i;
220
221 if (!clk->parent_table || !clk->parent_num)
222 return -EINVAL;
223
224 /* Search the parent */
225 for (i = 0; i < clk->parent_num; i++)
226 if (clk->parent_table[i] == parent)
227 break;
228
229 if (i == clk->parent_num)
230 return -ENODEV;
231
232 ret = clk_reparent(clk, parent);
233 if (ret < 0)
234 return ret;
235
236 value = __raw_readl(PLLC2CR) & ~(3 << 6);
237
238 __raw_writel(value | (i << 6), PLLC2CR);
239
240 /* Rebiuld the frequency table */
241 pllc2_table_rebuild(clk);
242
243 return 0;
244}
245
246static struct sh_clk_ops pllc2_clk_ops = {
247 .recalc = pllc2_recalc,
248 .round_rate = pllc2_round_rate,
249 .set_rate = pllc2_set_rate,
250 .enable = pllc2_enable,
251 .disable = pllc2_disable,
252 .set_parent = pllc2_set_parent,
253};
254
255struct clk sh7372_pllc2_clk = {
256 .ops = &pllc2_clk_ops,
257 .parent = &extal1_div2_clk,
258 .freq_table = pllc2_freq_table,
259 .nr_freqs = ARRAY_SIZE(pllc2_freq_table) - 1,
260 .parent_table = pllc2_parent,
261 .parent_num = ARRAY_SIZE(pllc2_parent),
262};
263
264/* External input clock (pin name: FSIACK/FSIBCK ) */
265static struct clk fsiack_clk = {
266};
267
268static struct clk fsibck_clk = {
269};
270
271static struct clk *main_clks[] = {
272 &sh7372_dv_clki_clk,
273 &r_clk,
274 &sh7372_extal1_clk,
275 &sh7372_extal2_clk,
276 &sh7372_dv_clki_div2_clk,
277 &extal1_div2_clk,
278 &extal2_div2_clk,
279 &extal2_div4_clk,
280 &pllc0_clk,
281 &pllc1_clk,
282 &pllc1_div2_clk,
283 &sh7372_pllc2_clk,
284 &fsiack_clk,
285 &fsibck_clk,
286};
287
288static void div4_kick(struct clk *clk)
289{
290 unsigned long value;
291
292 /* set KICK bit in FRQCRB to update hardware setting */
293 value = __raw_readl(FRQCRB);
294 value |= (1 << 31);
295 __raw_writel(value, FRQCRB);
296}
297
298static int divisors[] = { 2, 3, 4, 6, 8, 12, 16, 18,
299 24, 32, 36, 48, 0, 72, 96, 0 };
300
301static struct clk_div_mult_table div4_div_mult_table = {
302 .divisors = divisors,
303 .nr_divisors = ARRAY_SIZE(divisors),
304};
305
306static struct clk_div4_table div4_table = {
307 .div_mult_table = &div4_div_mult_table,
308 .kick = div4_kick,
309};
310
311enum { DIV4_I, DIV4_ZG, DIV4_B, DIV4_M1, DIV4_CSIR,
312 DIV4_ZX, DIV4_HP,
313 DIV4_ISPB, DIV4_S, DIV4_ZB, DIV4_ZB3, DIV4_CP,
314 DIV4_DDRP, DIV4_NR };
315
316#define DIV4(_reg, _bit, _mask, _flags) \
317 SH_CLK_DIV4(&pllc1_clk, _reg, _bit, _mask, _flags)
318
319static struct clk div4_clks[DIV4_NR] = {
320 [DIV4_I] = DIV4(FRQCRA, 20, 0x6fff, CLK_ENABLE_ON_INIT),
321 [DIV4_ZG] = DIV4(FRQCRA, 16, 0x6fff, CLK_ENABLE_ON_INIT),
322 [DIV4_B] = DIV4(FRQCRA, 8, 0x6fff, CLK_ENABLE_ON_INIT),
323 [DIV4_M1] = DIV4(FRQCRA, 4, 0x6fff, CLK_ENABLE_ON_INIT),
324 [DIV4_CSIR] = DIV4(FRQCRA, 0, 0x6fff, 0),
325 [DIV4_ZX] = DIV4(FRQCRB, 12, 0x6fff, 0),
326 [DIV4_HP] = DIV4(FRQCRB, 4, 0x6fff, 0),
327 [DIV4_ISPB] = DIV4(FRQCRC, 20, 0x6fff, 0),
328 [DIV4_S] = DIV4(FRQCRC, 12, 0x6fff, 0),
329 [DIV4_ZB] = DIV4(FRQCRC, 8, 0x6fff, 0),
330 [DIV4_ZB3] = DIV4(FRQCRC, 4, 0x6fff, 0),
331 [DIV4_CP] = DIV4(FRQCRC, 0, 0x6fff, 0),
332 [DIV4_DDRP] = DIV4(FRQCRD, 0, 0x677c, 0),
333};
334
335enum { DIV6_VCK1, DIV6_VCK2, DIV6_VCK3, DIV6_FMSI, DIV6_FMSO,
336 DIV6_SUB, DIV6_SPU,
337 DIV6_VOU, DIV6_DSIT, DIV6_DSI0P, DIV6_DSI1P,
338 DIV6_NR };
339
340static struct clk div6_clks[DIV6_NR] = {
341 [DIV6_VCK1] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR1, 0),
342 [DIV6_VCK2] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR2, 0),
343 [DIV6_VCK3] = SH_CLK_DIV6(&pllc1_div2_clk, VCLKCR3, 0),
344 [DIV6_FMSI] = SH_CLK_DIV6(&pllc1_div2_clk, FMSICKCR, 0),
345 [DIV6_FMSO] = SH_CLK_DIV6(&pllc1_div2_clk, FMSOCKCR, 0),
346 [DIV6_SUB] = SH_CLK_DIV6(&sh7372_extal2_clk, SUBCKCR, 0),
347 [DIV6_SPU] = SH_CLK_DIV6(&pllc1_div2_clk, SPUCKCR, 0),
348 [DIV6_VOU] = SH_CLK_DIV6(&pllc1_div2_clk, VOUCKCR, 0),
349 [DIV6_DSIT] = SH_CLK_DIV6(&pllc1_div2_clk, DSITCKCR, 0),
350 [DIV6_DSI0P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI0PCKCR, 0),
351 [DIV6_DSI1P] = SH_CLK_DIV6(&pllc1_div2_clk, DSI1PCKCR, 0),
352};
353
354enum { DIV6_HDMI, DIV6_FSIA, DIV6_FSIB, DIV6_REPARENT_NR };
355
356/* Indices are important - they are the actual src selecting values */
357static struct clk *hdmi_parent[] = {
358 [0] = &pllc1_div2_clk,
359 [1] = &sh7372_pllc2_clk,
360 [2] = &sh7372_dv_clki_clk,
361 [3] = NULL, /* pllc2_div4 not implemented yet */
362};
363
364static struct clk *fsiackcr_parent[] = {
365 [0] = &pllc1_div2_clk,
366 [1] = &sh7372_pllc2_clk,
367 [2] = &fsiack_clk, /* external input for FSI A */
368 [3] = NULL, /* setting prohibited */
369};
370
371static struct clk *fsibckcr_parent[] = {
372 [0] = &pllc1_div2_clk,
373 [1] = &sh7372_pllc2_clk,
374 [2] = &fsibck_clk, /* external input for FSI B */
375 [3] = NULL, /* setting prohibited */
376};
377
378static struct clk div6_reparent_clks[DIV6_REPARENT_NR] = {
379 [DIV6_HDMI] = SH_CLK_DIV6_EXT(HDMICKCR, 0,
380 hdmi_parent, ARRAY_SIZE(hdmi_parent), 6, 2),
381 [DIV6_FSIA] = SH_CLK_DIV6_EXT(FSIACKCR, 0,
382 fsiackcr_parent, ARRAY_SIZE(fsiackcr_parent), 6, 2),
383 [DIV6_FSIB] = SH_CLK_DIV6_EXT(FSIBCKCR, 0,
384 fsibckcr_parent, ARRAY_SIZE(fsibckcr_parent), 6, 2),
385};
386
387/* FSI DIV */
388enum { FSIDIV_A, FSIDIV_B, FSIDIV_REPARENT_NR };
389
390static struct clk fsidivs[] = {
391 [FSIDIV_A] = SH_CLK_FSIDIV(FSIDIVA, &div6_reparent_clks[DIV6_FSIA]),
392 [FSIDIV_B] = SH_CLK_FSIDIV(FSIDIVB, &div6_reparent_clks[DIV6_FSIB]),
393};
394
395enum { MSTP001, MSTP000,
396 MSTP131, MSTP130,
397 MSTP129, MSTP128, MSTP127, MSTP126, MSTP125,
398 MSTP118, MSTP117, MSTP116, MSTP113,
399 MSTP106, MSTP101, MSTP100,
400 MSTP223,
401 MSTP218, MSTP217, MSTP216, MSTP214, MSTP208, MSTP207,
402 MSTP206, MSTP205, MSTP204, MSTP203, MSTP202, MSTP201, MSTP200,
403 MSTP328, MSTP323, MSTP322, MSTP315, MSTP314, MSTP313, MSTP312,
404 MSTP423, MSTP415, MSTP413, MSTP411, MSTP410, MSTP407, MSTP406,
405 MSTP405, MSTP404, MSTP403, MSTP400,
406 MSTP_NR };
407
408#define MSTP(_parent, _reg, _bit, _flags) \
409 SH_CLK_MSTP32(_parent, _reg, _bit, _flags)
410
411static struct clk mstp_clks[MSTP_NR] = {
412 [MSTP001] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 1, 0), /* IIC2 */
413 [MSTP000] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR0, 0, 0), /* MSIOF0 */
414 [MSTP131] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 31, 0), /* VEU3 */
415 [MSTP130] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 30, 0), /* VEU2 */
416 [MSTP129] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 29, 0), /* VEU1 */
417 [MSTP128] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 28, 0), /* VEU0 */
418 [MSTP127] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 27, 0), /* CEU */
419 [MSTP126] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 26, 0), /* CSI2 */
420 [MSTP125] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 25, 0), /* TMU0 */
421 [MSTP118] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 18, 0), /* DSITX */
422 [MSTP117] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 17, 0), /* LCDC1 */
423 [MSTP116] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 16, 0), /* IIC0 */
424 [MSTP113] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR1, 13, 0), /* MERAM */
425 [MSTP106] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 6, 0), /* JPU */
426 [MSTP101] = MSTP(&div4_clks[DIV4_M1], SMSTPCR1, 1, 0), /* VPU */
427 [MSTP100] = MSTP(&div4_clks[DIV4_B], SMSTPCR1, 0, 0), /* LCDC0 */
428 [MSTP223] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR2, 23, 0), /* SPU2 */
429 [MSTP218] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 18, 0), /* DMAC1 */
430 [MSTP217] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 17, 0), /* DMAC2 */
431 [MSTP216] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 16, 0), /* DMAC3 */
432 [MSTP214] = MSTP(&div4_clks[DIV4_HP], SMSTPCR2, 14, 0), /* USBDMAC */
433 [MSTP208] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 8, 0), /* MSIOF1 */
434 [MSTP207] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 7, 0), /* SCIFA5 */
435 [MSTP206] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 6, 0), /* SCIFB */
436 [MSTP205] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 5, 0), /* MSIOF2 */
437 [MSTP204] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 4, 0), /* SCIFA0 */
438 [MSTP203] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 3, 0), /* SCIFA1 */
439 [MSTP202] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 2, 0), /* SCIFA2 */
440 [MSTP201] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 1, 0), /* SCIFA3 */
441 [MSTP200] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR2, 0, 0), /* SCIFA4 */
442 [MSTP328] = MSTP(&div6_clks[DIV6_SPU], SMSTPCR3, 28, 0), /* FSI2 */
443 [MSTP323] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 23, 0), /* IIC1 */
444 [MSTP322] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR3, 22, 0), /* USB0 */
445 [MSTP315] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 15, 0), /* FLCTL*/
446 [MSTP314] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 14, 0), /* SDHI0 */
447 [MSTP313] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 13, 0), /* SDHI1 */
448 [MSTP312] = MSTP(&div4_clks[DIV4_HP], SMSTPCR3, 12, 0), /* MMC */
449 [MSTP423] = MSTP(&div4_clks[DIV4_B], SMSTPCR4, 23, 0), /* DSITX1 */
450 [MSTP415] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 15, 0), /* SDHI2 */
451 [MSTP413] = MSTP(&pllc1_div2_clk, SMSTPCR4, 13, 0), /* HDMI */
452 [MSTP411] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 11, 0), /* IIC3 */
453 [MSTP410] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 10, 0), /* IIC4 */
454 [MSTP407] = MSTP(&div4_clks[DIV4_HP], SMSTPCR4, 7, 0), /* USB-DMAC1 */
455 [MSTP406] = MSTP(&div6_clks[DIV6_SUB], SMSTPCR4, 6, 0), /* USB1 */
456 [MSTP405] = MSTP(&r_clk, SMSTPCR4, 5, 0), /* CMT4 */
457 [MSTP404] = MSTP(&r_clk, SMSTPCR4, 4, 0), /* CMT3 */
458 [MSTP403] = MSTP(&r_clk, SMSTPCR4, 3, 0), /* KEYSC */
459 [MSTP400] = MSTP(&r_clk, SMSTPCR4, 0, 0), /* CMT2 */
460};
461
462static struct clk_lookup lookups[] = {
463 /* main clocks */
464 CLKDEV_CON_ID("dv_clki_div2_clk", &sh7372_dv_clki_div2_clk),
465 CLKDEV_CON_ID("r_clk", &r_clk),
466 CLKDEV_CON_ID("extal1", &sh7372_extal1_clk),
467 CLKDEV_CON_ID("extal2", &sh7372_extal2_clk),
468 CLKDEV_CON_ID("extal1_div2_clk", &extal1_div2_clk),
469 CLKDEV_CON_ID("extal2_div2_clk", &extal2_div2_clk),
470 CLKDEV_CON_ID("extal2_div4_clk", &extal2_div4_clk),
471 CLKDEV_CON_ID("pllc0_clk", &pllc0_clk),
472 CLKDEV_CON_ID("pllc1_clk", &pllc1_clk),
473 CLKDEV_CON_ID("pllc1_div2_clk", &pllc1_div2_clk),
474 CLKDEV_CON_ID("pllc2_clk", &sh7372_pllc2_clk),
475 CLKDEV_CON_ID("fsiack", &fsiack_clk),
476 CLKDEV_CON_ID("fsibck", &fsibck_clk),
477
478 /* DIV4 clocks */
479 CLKDEV_CON_ID("i_clk", &div4_clks[DIV4_I]),
480 CLKDEV_CON_ID("zg_clk", &div4_clks[DIV4_ZG]),
481 CLKDEV_CON_ID("b_clk", &div4_clks[DIV4_B]),
482 CLKDEV_CON_ID("m1_clk", &div4_clks[DIV4_M1]),
483 CLKDEV_CON_ID("csir_clk", &div4_clks[DIV4_CSIR]),
484 CLKDEV_CON_ID("zx_clk", &div4_clks[DIV4_ZX]),
485 CLKDEV_CON_ID("hp_clk", &div4_clks[DIV4_HP]),
486 CLKDEV_CON_ID("ispb_clk", &div4_clks[DIV4_ISPB]),
487 CLKDEV_CON_ID("s_clk", &div4_clks[DIV4_S]),
488 CLKDEV_CON_ID("zb_clk", &div4_clks[DIV4_ZB]),
489 CLKDEV_CON_ID("zb3_clk", &div4_clks[DIV4_ZB3]),
490 CLKDEV_CON_ID("cp_clk", &div4_clks[DIV4_CP]),
491 CLKDEV_CON_ID("ddrp_clk", &div4_clks[DIV4_DDRP]),
492
493 /* DIV6 clocks */
494 CLKDEV_CON_ID("vck1_clk", &div6_clks[DIV6_VCK1]),
495 CLKDEV_CON_ID("vck2_clk", &div6_clks[DIV6_VCK2]),
496 CLKDEV_CON_ID("vck3_clk", &div6_clks[DIV6_VCK3]),
497 CLKDEV_CON_ID("fmsi_clk", &div6_clks[DIV6_FMSI]),
498 CLKDEV_CON_ID("fmso_clk", &div6_clks[DIV6_FMSO]),
499 CLKDEV_CON_ID("sub_clk", &div6_clks[DIV6_SUB]),
500 CLKDEV_CON_ID("spu_clk", &div6_clks[DIV6_SPU]),
501 CLKDEV_CON_ID("vou_clk", &div6_clks[DIV6_VOU]),
502 CLKDEV_CON_ID("hdmi_clk", &div6_reparent_clks[DIV6_HDMI]),
503
504 /* MSTP32 clocks */
505 CLKDEV_DEV_ID("i2c-sh_mobile.2", &mstp_clks[MSTP001]), /* IIC2 */
506 CLKDEV_DEV_ID("fff30000.i2c", &mstp_clks[MSTP001]), /* IIC2 */
507 CLKDEV_DEV_ID("spi_sh_msiof.0", &mstp_clks[MSTP000]), /* MSIOF0 */
508 CLKDEV_DEV_ID("uio_pdrv_genirq.4", &mstp_clks[MSTP131]), /* VEU3 */
509 CLKDEV_DEV_ID("uio_pdrv_genirq.3", &mstp_clks[MSTP130]), /* VEU2 */
510 CLKDEV_DEV_ID("uio_pdrv_genirq.2", &mstp_clks[MSTP129]), /* VEU1 */
511 CLKDEV_DEV_ID("uio_pdrv_genirq.1", &mstp_clks[MSTP128]), /* VEU0 */
512 CLKDEV_DEV_ID("sh_mobile_ceu.0", &mstp_clks[MSTP127]), /* CEU */
513 CLKDEV_DEV_ID("sh-mobile-csi2.0", &mstp_clks[MSTP126]), /* CSI2 */
514 CLKDEV_DEV_ID("sh-mipi-dsi.0", &mstp_clks[MSTP118]), /* DSITX0 */
515 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.1", &mstp_clks[MSTP117]), /* LCDC1 */
516 CLKDEV_DEV_ID("i2c-sh_mobile.0", &mstp_clks[MSTP116]), /* IIC0 */
517 CLKDEV_DEV_ID("fff20000.i2c", &mstp_clks[MSTP116]), /* IIC0 */
518 CLKDEV_DEV_ID("sh_mobile_meram.0", &mstp_clks[MSTP113]), /* MERAM */
519 CLKDEV_DEV_ID("uio_pdrv_genirq.5", &mstp_clks[MSTP106]), /* JPU */
520 CLKDEV_DEV_ID("uio_pdrv_genirq.0", &mstp_clks[MSTP101]), /* VPU */
521 CLKDEV_DEV_ID("sh_mobile_lcdc_fb.0", &mstp_clks[MSTP100]), /* LCDC0 */
522 CLKDEV_DEV_ID("uio_pdrv_genirq.6", &mstp_clks[MSTP223]), /* SPU2DSP0 */
523 CLKDEV_DEV_ID("uio_pdrv_genirq.7", &mstp_clks[MSTP223]), /* SPU2DSP1 */
524 CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]), /* DMAC1 */
525 CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]), /* DMAC2 */
526 CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]), /* DMAC3 */
527 CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]), /* USB-DMAC0 */
528 CLKDEV_DEV_ID("spi_sh_msiof.1", &mstp_clks[MSTP208]), /* MSIOF1 */
529 CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]), /* SCIFA5 */
530 CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP206]), /* SCIFB */
531 CLKDEV_DEV_ID("spi_sh_msiof.2", &mstp_clks[MSTP205]), /* MSIOF2 */
532 CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]), /* SCIFA0 */
533 CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]), /* SCIFA1 */
534 CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]), /* SCIFA2 */
535 CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]), /* SCIFA3 */
536 CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]), /* SCIFA4 */
537 CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]), /* FSI2 */
538 CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]), /* IIC1 */
539 CLKDEV_DEV_ID("e6c20000.i2c", &mstp_clks[MSTP323]), /* IIC1 */
540 CLKDEV_DEV_ID("r8a66597_hcd.0", &mstp_clks[MSTP322]), /* USB0 */
541 CLKDEV_DEV_ID("r8a66597_udc.0", &mstp_clks[MSTP322]), /* USB0 */
542 CLKDEV_DEV_ID("renesas_usbhs.0", &mstp_clks[MSTP322]), /* USB0 */
543 CLKDEV_DEV_ID("sh_flctl.0", &mstp_clks[MSTP315]), /* FLCTL */
544 CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
545 CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
546 CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
547 CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
548 CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMC */
549 CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMC */
550 CLKDEV_DEV_ID("sh-mipi-dsi.1", &mstp_clks[MSTP423]), /* DSITX1 */
551 CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]), /* SDHI2 */
552 CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]), /* SDHI2 */
553 CLKDEV_DEV_ID("sh-mobile-hdmi", &mstp_clks[MSTP413]), /* HDMI */
554 CLKDEV_DEV_ID("i2c-sh_mobile.3", &mstp_clks[MSTP411]), /* IIC3 */
555 CLKDEV_DEV_ID("e6d20000.i2c", &mstp_clks[MSTP411]), /* IIC3 */
556 CLKDEV_DEV_ID("i2c-sh_mobile.4", &mstp_clks[MSTP410]), /* IIC4 */
557 CLKDEV_DEV_ID("e6d30000.i2c", &mstp_clks[MSTP410]), /* IIC4 */
558 CLKDEV_DEV_ID("sh-dma-engine.4", &mstp_clks[MSTP407]), /* USB-DMAC1 */
559 CLKDEV_DEV_ID("r8a66597_hcd.1", &mstp_clks[MSTP406]), /* USB1 */
560 CLKDEV_DEV_ID("r8a66597_udc.1", &mstp_clks[MSTP406]), /* USB1 */
561 CLKDEV_DEV_ID("renesas_usbhs.1", &mstp_clks[MSTP406]), /* USB1 */
562 CLKDEV_DEV_ID("sh_keysc.0", &mstp_clks[MSTP403]), /* KEYSC */
563
564 /* ICK */
565 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSIT]),
566 CLKDEV_ICK_ID("dsit_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSIT]),
567 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.0", &div6_clks[DIV6_DSI0P]),
568 CLKDEV_ICK_ID("dsip_clk", "sh-mipi-dsi.1", &div6_clks[DIV6_DSI1P]),
569 CLKDEV_ICK_ID("hdmi", "sh_mobile_lcdc_fb.1",
570 &div6_reparent_clks[DIV6_HDMI]),
571 CLKDEV_ICK_ID("ick", "sh-mobile-hdmi", &div6_reparent_clks[DIV6_HDMI]),
572 CLKDEV_ICK_ID("icka", "sh_fsi2", &div6_reparent_clks[DIV6_FSIA]),
573 CLKDEV_ICK_ID("ickb", "sh_fsi2", &div6_reparent_clks[DIV6_FSIB]),
574 CLKDEV_ICK_ID("fck", "sh-tmu.0", &mstp_clks[MSTP125]), /* TMU0 */
575 CLKDEV_ICK_ID("spu2", "sh_fsi2", &mstp_clks[MSTP223]),
576 CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.4", &mstp_clks[MSTP405]), /* CMT4 */
577 CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.3", &mstp_clks[MSTP404]), /* CMT3 */
578 CLKDEV_ICK_ID("fck", "sh-cmt-32-fast.2", &mstp_clks[MSTP400]), /* CMT2 */
579 CLKDEV_ICK_ID("diva", "sh_fsi2", &fsidivs[FSIDIV_A]),
580 CLKDEV_ICK_ID("divb", "sh_fsi2", &fsidivs[FSIDIV_B]),
581 CLKDEV_ICK_ID("xcka", "sh_fsi2", &fsiack_clk),
582 CLKDEV_ICK_ID("xckb", "sh_fsi2", &fsibck_clk),
583};
584
585void __init sh7372_clock_init(void)
586{
587 int k, ret = 0;
588
589 /* make sure MSTP bits on the RT/SH4AL-DSP side are off */
590 __raw_writel(0xe4ef8087, RMSTPCR0);
591 __raw_writel(0xffffffff, RMSTPCR1);
592 __raw_writel(0x37c7f7ff, RMSTPCR2);
593 __raw_writel(0xffffffff, RMSTPCR3);
594 __raw_writel(0xffe0fffd, RMSTPCR4);
595
596 for (k = 0; !ret && (k < ARRAY_SIZE(main_clks)); k++)
597 ret = clk_register(main_clks[k]);
598
599 if (!ret)
600 ret = sh_clk_div4_register(div4_clks, DIV4_NR, &div4_table);
601
602 if (!ret)
603 ret = sh_clk_div6_register(div6_clks, DIV6_NR);
604
605 if (!ret)
606 ret = sh_clk_div6_reparent_register(div6_reparent_clks, DIV6_REPARENT_NR);
607
608 if (!ret)
609 ret = sh_clk_mstp_register(mstp_clks, MSTP_NR);
610
611 if (!ret)
612 ret = sh_clk_fsidiv_register(fsidivs, FSIDIV_REPARENT_NR);
613
614 clkdev_add_table(lookups, ARRAY_SIZE(lookups));
615
616 if (!ret)
617 shmobile_clk_init();
618 else
619 panic("failed to setup sh7372 clocks\n");
620}
diff --git a/arch/arm/mach-shmobile/clock.c b/arch/arm/mach-shmobile/clock.c
index 34f056fc3756..68c2d06d0eaa 100644
--- a/arch/arm/mach-shmobile/clock.c
+++ b/arch/arm/mach-shmobile/clock.c
@@ -45,14 +45,3 @@ int __init shmobile_clk_init(void)
45 45
46 return 0; 46 return 0;
47} 47}
48
49int __clk_get(struct clk *clk)
50{
51 return 1;
52}
53EXPORT_SYMBOL(__clk_get);
54
55void __clk_put(struct clk *clk)
56{
57}
58EXPORT_SYMBOL(__clk_put);
diff --git a/arch/arm/mach-shmobile/common.h b/arch/arm/mach-shmobile/common.h
index 309025efd4cf..8faf6e040d78 100644
--- a/arch/arm/mach-shmobile/common.h
+++ b/arch/arm/mach-shmobile/common.h
@@ -21,7 +21,6 @@ extern void shmobile_smp_scu_cpu_die(unsigned int cpu);
21extern int shmobile_smp_scu_cpu_kill(unsigned int cpu); 21extern int shmobile_smp_scu_cpu_kill(unsigned int cpu);
22struct clk; 22struct clk;
23extern int shmobile_clk_init(void); 23extern int shmobile_clk_init(void);
24extern void shmobile_handle_irq_intc(struct pt_regs *);
25extern struct platform_suspend_ops shmobile_suspend_ops; 24extern struct platform_suspend_ops shmobile_suspend_ops;
26struct cpuidle_driver; 25struct cpuidle_driver;
27extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv); 26extern void shmobile_cpuidle_set_driver(struct cpuidle_driver *drv);
diff --git a/arch/arm/mach-shmobile/entry-intc.S b/arch/arm/mach-shmobile/entry-intc.S
deleted file mode 100644
index 1a1c00ca39a2..000000000000
--- a/arch/arm/mach-shmobile/entry-intc.S
+++ /dev/null
@@ -1,54 +0,0 @@
1/*
2 * ARM Interrupt demux handler using INTC
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Renesas Solutions Corp.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#include <asm/entry-macro-multi.S>
13
14#define INTCA_BASE 0xe6980000
15#define INTFLGA_OFFS 0x00000018 /* accept pending interrupt */
16#define INTEVTA_OFFS 0x00000020 /* vector number of accepted interrupt */
17#define INTLVLA_OFFS 0x00000030 /* priority level of accepted interrupt */
18#define INTLVLB_OFFS 0x00000034 /* previous priority level */
19
20 .macro get_irqnr_preamble, base, tmp
21 ldr \base, =INTCA_BASE
22 .endm
23
24 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
25 /* The single INTFLGA read access below results in the following:
26 *
27 * 1. INTLVLB is updated with old priority value from INTLVLA
28 * 2. Highest priority interrupt is accepted
29 * 3. INTLVLA is updated to contain priority of accepted interrupt
30 * 4. Accepted interrupt vector is stored in INTFLGA and INTEVTA
31 */
32 ldr \irqnr, [\base, #INTFLGA_OFFS]
33
34 /* Restore INTLVLA with the value saved in INTLVLB.
35 * This is required to support interrupt priorities properly.
36 */
37 ldrb \tmp, [\base, #INTLVLB_OFFS]
38 strb \tmp, [\base, #INTLVLA_OFFS]
39
40 /* Handle invalid vector number case */
41 cmp \irqnr, #0
42 beq 1000f
43
44 /* Convert vector to irq number, same as the evt2irq() macro */
45 lsr \irqnr, \irqnr, #0x5
46 subs \irqnr, \irqnr, #16
47
481000:
49 .endm
50
51 .macro test_for_ipi, irqnr, irqstat, base, tmp
52 .endm
53
54 arch_irq_handler shmobile_handle_irq_intc
diff --git a/arch/arm/mach-shmobile/include/mach/clkdev.h b/arch/arm/mach-shmobile/include/mach/clkdev.h
deleted file mode 100644
index 36d0163a857a..000000000000
--- a/arch/arm/mach-shmobile/include/mach/clkdev.h
+++ /dev/null
@@ -1,7 +0,0 @@
1#ifndef __ASM_MACH_CLKDEV_H
2#define __ASM_MACH_CLKDEV_H
3
4int __clk_get(struct clk *clk);
5void __clk_put(struct clk *clk);
6
7#endif /* __ASM_MACH_CLKDEV_H */
diff --git a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt b/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
deleted file mode 100644
index 9f134dfeffdc..000000000000
--- a/arch/arm/mach-shmobile/include/mach/head-mackerel.txt
+++ /dev/null
@@ -1,93 +0,0 @@
1LIST "partner-jet-setup.txt"
2LIST "(C) Copyright 2010 Renesas Solutions Corp"
3LIST "Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>"
4
5LIST "RWT Setting"
6EW 0xE6020004, 0xA500
7EW 0xE6030004, 0xA500
8
9LIST "GPIO Setting"
10EB 0xE6051013, 0xA2
11
12LIST "CPG"
13ED 0xE61500C0, 0x00000002
14
15WAIT 1, 0xFE40009C
16
17LIST "FRQCR"
18ED 0xE6150000, 0x2D1305C3
19ED 0xE61500E0, 0x9E40358E
20ED 0xE6150004, 0x80331050
21
22WAIT 1, 0xFE40009C
23
24ED 0xE61500E4, 0x00002000
25
26WAIT 1, 0xFE40009C
27
28LIST "PLL"
29ED 0xE6150028, 0x00004000
30
31WAIT 1, 0xFE40009C
32
33ED 0xE615002C, 0x93000040
34
35WAIT 1, 0xFE40009C
36
37LIST "SUB/USBClk"
38ED 0xE6150080, 0x00000180
39
40LIST "BSC"
41ED 0xFEC10000, 0x00E0001B
42
43LIST "SBSC1"
44ED 0xFE400354, 0x01AD8000
45ED 0xFE400354, 0x01AD8001
46
47WAIT 5, 0xFE40009C
48
49ED 0xFE400008, 0xBCC90151
50ED 0xFE400040, 0x41774113
51ED 0xFE400044, 0x2712E229
52ED 0xFE400048, 0x20C18505
53ED 0xFE40004C, 0x00110209
54ED 0xFE400010, 0x00000087
55
56WAIT 30, 0xFE40009C
57
58ED 0xFE400084, 0x0000003F
59EB 0xFE500000, 0x00
60
61WAIT 5, 0xFE40009C
62
63ED 0xFE400084, 0x0000FF0A
64EB 0xFE500000, 0x00
65
66WAIT 1, 0xFE40009C
67
68ED 0xFE400084, 0x00002201
69EB 0xFE500000, 0x00
70ED 0xFE400084, 0x00000302
71EB 0xFE500000, 0x00
72EB 0xFE5C0000, 0x00
73ED 0xFE400008, 0xBCC90159
74ED 0xFE40008C, 0x88800004
75ED 0xFE400094, 0x00000004
76ED 0xFE400028, 0xA55A0032
77ED 0xFE40002C, 0xA55A000C
78ED 0xFE400020, 0xA55A2048
79ED 0xFE400008, 0xBCC90959
80
81LIST "Change CPGA setting"
82ED 0xE61500E0, 0x9E40352E
83ED 0xE6150004, 0x80331050
84
85WAIT 1, 0xFE40009C
86
87ED 0xFE400354, 0x01AD8002
88
89LIST "SCIF0 - Serial port for earlyprintk"
90EB 0xE6053098, 0xe1
91EW 0xE6C40000, 0x0000
92EB 0xE6C40004, 0x19
93EW 0xE6C40008, 0x0030
diff --git a/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h b/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h
deleted file mode 100644
index 15d3a9efdec2..000000000000
--- a/arch/arm/mach-shmobile/include/mach/mmc-mackerel.h
+++ /dev/null
@@ -1,38 +0,0 @@
1#ifndef MMC_MACKEREL_H
2#define MMC_MACKEREL_H
3
4#define PORT0CR (void __iomem *)0xe6051000
5#define PORT1CR (void __iomem *)0xe6051001
6#define PORT2CR (void __iomem *)0xe6051002
7#define PORT159CR (void __iomem *)0xe605009f
8
9#define PORTR031_000DR (void __iomem *)0xe6055000
10#define PORTL159_128DR (void __iomem *)0xe6054010
11
12static inline void mmc_init_progress(void)
13{
14 /* Initialise LEDS0-3
15 * registers: PORT0CR-PORT2CR,PORT159CR (LED0-LED3 Control)
16 * value: 0x10 - enable output
17 */
18 __raw_writeb(0x10, PORT0CR);
19 __raw_writeb(0x10, PORT1CR);
20 __raw_writeb(0x10, PORT2CR);
21 __raw_writeb(0x10, PORT159CR);
22}
23
24static inline void mmc_update_progress(int n)
25{
26 unsigned a = 0, b = 0;
27
28 if (n < 3)
29 a = 1 << n;
30 else
31 b = 1 << 31;
32
33 __raw_writel((__raw_readl(PORTR031_000DR) & ~0x7) | a,
34 PORTR031_000DR);
35 __raw_writel((__raw_readl(PORTL159_128DR) & ~(1 << 31)) | b,
36 PORTL159_128DR);
37}
38#endif /* MMC_MACKEREL_H */
diff --git a/arch/arm/mach-shmobile/include/mach/mmc.h b/arch/arm/mach-shmobile/include/mach/mmc.h
deleted file mode 100644
index e979b8fc1da2..000000000000
--- a/arch/arm/mach-shmobile/include/mach/mmc.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef MMC_H
2#define MMC_H
3
4/**************************************************
5 *
6 * board specific settings
7 *
8 **************************************************/
9
10#ifdef CONFIG_MACH_MACKEREL
11#include "mach/mmc-mackerel.h"
12#else
13#error "unsupported board."
14#endif
15
16#endif /* MMC_H */
diff --git a/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h b/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h
deleted file mode 100644
index 4a81b01f1e8f..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sdhi-sh7372.h
+++ /dev/null
@@ -1,21 +0,0 @@
1#ifndef SDHI_SH7372_H
2#define SDHI_SH7372_H
3
4#define SDGENCNTA 0xfe40009c
5
6/* The countdown of SDGENCNTA is controlled by
7 * ZB3D2CLK which runs at 149.5MHz.
8 * That is 149.5ticks/us. Approximate this as 150ticks/us.
9 */
10static void udelay(int us)
11{
12 __raw_writel(us * 150, SDGENCNTA);
13 while(__raw_readl(SDGENCNTA)) ;
14}
15
16static void msleep(int ms)
17{
18 udelay(ms * 1000);
19}
20
21#endif
diff --git a/arch/arm/mach-shmobile/include/mach/sdhi.h b/arch/arm/mach-shmobile/include/mach/sdhi.h
deleted file mode 100644
index 0ec9e69f2c3b..000000000000
--- a/arch/arm/mach-shmobile/include/mach/sdhi.h
+++ /dev/null
@@ -1,16 +0,0 @@
1#ifndef SDHI_H
2#define SDHI_H
3
4/**************************************************
5 *
6 * CPU specific settings
7 *
8 **************************************************/
9
10#ifdef CONFIG_ARCH_SH7372
11#include "mach/sdhi-sh7372.h"
12#else
13#error "unsupported CPU."
14#endif
15
16#endif /* SDHI_H */
diff --git a/arch/arm/mach-shmobile/include/mach/system.h b/arch/arm/mach-shmobile/include/mach/system.h
deleted file mode 100644
index 540eaff08f34..000000000000
--- a/arch/arm/mach-shmobile/include/mach/system.h
+++ /dev/null
@@ -1,11 +0,0 @@
1#ifndef __ASM_ARCH_SYSTEM_H
2#define __ASM_ARCH_SYSTEM_H
3
4#include <asm/system_misc.h>
5
6static inline void arch_reset(char mode, const char *cmd)
7{
8 soft_restart(0);
9}
10
11#endif
diff --git a/arch/arm/mach-shmobile/include/mach/uncompress.h b/arch/arm/mach-shmobile/include/mach/uncompress.h
deleted file mode 100644
index f1aee56781e7..000000000000
--- a/arch/arm/mach-shmobile/include/mach/uncompress.h
+++ /dev/null
@@ -1,19 +0,0 @@
1#ifndef __ASM_MACH_UNCOMPRESS_H
2#define __ASM_MACH_UNCOMPRESS_H
3
4/*
5 * This does not append a newline
6 */
7static void putc(int c)
8{
9}
10
11static inline void flush(void)
12{
13}
14
15static void arch_decomp_setup(void)
16{
17}
18
19#endif /* __ASM_MACH_UNCOMPRESS_H */
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index 727cc78ac8ec..9d9cb09c9336 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -9,10 +9,7 @@
9 * 9 *
10 **************************************************/ 10 **************************************************/
11 11
12#ifdef CONFIG_MACH_MACKEREL 12#if defined(CONFIG_MACH_KZM9G) || defined(CONFIG_MACH_KZM9G_REFERENCE)
13#define MEMORY_START 0x40000000
14#include "mach/head-mackerel.txt"
15#elif defined(CONFIG_MACH_KZM9G) || defined(CONFIG_MACH_KZM9G_REFERENCE)
16#define MEMORY_START 0x43000000 13#define MEMORY_START 0x43000000
17#include "mach/head-kzm9g.txt" 14#include "mach/head-kzm9g.txt"
18#else 15#else
diff --git a/arch/arm/mach-shmobile/intc-sh7372.c b/arch/arm/mach-shmobile/intc-sh7372.c
deleted file mode 100644
index 1ccf49cb485f..000000000000
--- a/arch/arm/mach-shmobile/intc-sh7372.c
+++ /dev/null
@@ -1,672 +0,0 @@
1/*
2 * sh7372 processor support - INTC hardware block
3 *
4 * Copyright (C) 2010 Magnus Damm
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15#include <linux/kernel.h>
16#include <linux/init.h>
17#include <linux/interrupt.h>
18#include <linux/module.h>
19#include <linux/irq.h>
20#include <linux/io.h>
21#include <asm/mach-types.h>
22#include <asm/mach/arch.h>
23#include "intc.h"
24#include "irqs.h"
25
26enum {
27 UNUSED_INTCA = 0,
28
29 /* interrupt sources INTCA */
30 DIRC,
31 CRYPT_STD,
32 IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1,
33 AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX,
34 MFI_MFIM, MFI_MFIS,
35 BBIF1, BBIF2,
36 USBHSDMAC0_USHDMI,
37 _3DG_SGX540,
38 CMT1_CMT10, CMT1_CMT11, CMT1_CMT12, CMT1_CMT13, CMT2, CMT3,
39 KEYSC_KEY,
40 SCIFA0, SCIFA1, SCIFA2, SCIFA3,
41 MSIOF2, MSIOF1,
42 SCIFA4, SCIFA5, SCIFB,
43 FLCTL_FLSTEI, FLCTL_FLTENDI, FLCTL_FLTREQ0I, FLCTL_FLTREQ1I,
44 SDHI0_SDHI0I0, SDHI0_SDHI0I1, SDHI0_SDHI0I2, SDHI0_SDHI0I3,
45 SDHI1_SDHI1I0, SDHI1_SDHI1I1, SDHI1_SDHI1I2,
46 IRREM,
47 IRDA,
48 TPU0,
49 TTI20,
50 DDM,
51 SDHI2_SDHI2I0, SDHI2_SDHI2I1, SDHI2_SDHI2I2, SDHI2_SDHI2I3,
52 RWDT0,
53 DMAC1_1_DEI0, DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3,
54 DMAC1_2_DEI4, DMAC1_2_DEI5, DMAC1_2_DADERR,
55 DMAC2_1_DEI0, DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3,
56 DMAC2_2_DEI4, DMAC2_2_DEI5, DMAC2_2_DADERR,
57 DMAC3_1_DEI0, DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3,
58 DMAC3_2_DEI4, DMAC3_2_DEI5, DMAC3_2_DADERR,
59 SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM,
60 HDMI,
61 SPU2_SPU0, SPU2_SPU1,
62 FSI, FMSI,
63 MIPI_HSI,
64 IPMMU_IPMMUD,
65 CEC_1, CEC_2,
66 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ, AP_ARM_DMAIRQ, AP_ARM_DMASIRQ,
67 MFIS2,
68 CPORTR2S,
69 CMT14, CMT15,
70 MMC_MMC_ERR, MMC_MMC_NOR,
71 IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
72 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3,
73 USB0_USB0I1, USB0_USB0I0,
74 USB1_USB1I1, USB1_USB1I0,
75 USBHSDMAC1_USHDMI,
76
77 /* interrupt groups INTCA */
78 DMAC1_1, DMAC1_2, DMAC2_1, DMAC2_2, DMAC3_1, DMAC3_2, SHWYSTAT,
79 AP_ARM1, AP_ARM2, SPU2, FLCTL, IIC1, SDHI0, SDHI1, SDHI2
80};
81
82static struct intc_vect intca_vectors[] __initdata = {
83 INTC_VECT(DIRC, 0x0560),
84 INTC_VECT(CRYPT_STD, 0x0700),
85 INTC_VECT(IIC1_ALI1, 0x0780), INTC_VECT(IIC1_TACKI1, 0x07a0),
86 INTC_VECT(IIC1_WAITI1, 0x07c0), INTC_VECT(IIC1_DTEI1, 0x07e0),
87 INTC_VECT(AP_ARM_IRQPMU, 0x0800), INTC_VECT(AP_ARM_COMMTX, 0x0840),
88 INTC_VECT(AP_ARM_COMMRX, 0x0860),
89 INTC_VECT(MFI_MFIM, 0x0900), INTC_VECT(MFI_MFIS, 0x0920),
90 INTC_VECT(BBIF1, 0x0940), INTC_VECT(BBIF2, 0x0960),
91 INTC_VECT(USBHSDMAC0_USHDMI, 0x0a00),
92 INTC_VECT(_3DG_SGX540, 0x0a60),
93 INTC_VECT(CMT1_CMT10, 0x0b00), INTC_VECT(CMT1_CMT11, 0x0b20),
94 INTC_VECT(CMT1_CMT12, 0x0b40), INTC_VECT(CMT1_CMT13, 0x0b60),
95 INTC_VECT(CMT2, 0x0b80), INTC_VECT(CMT3, 0x0ba0),
96 INTC_VECT(KEYSC_KEY, 0x0be0),
97 INTC_VECT(SCIFA0, 0x0c00), INTC_VECT(SCIFA1, 0x0c20),
98 INTC_VECT(SCIFA2, 0x0c40), INTC_VECT(SCIFA3, 0x0c60),
99 INTC_VECT(MSIOF2, 0x0c80), INTC_VECT(MSIOF1, 0x0d00),
100 INTC_VECT(SCIFA4, 0x0d20), INTC_VECT(SCIFA5, 0x0d40),
101 INTC_VECT(SCIFB, 0x0d60),
102 INTC_VECT(FLCTL_FLSTEI, 0x0d80), INTC_VECT(FLCTL_FLTENDI, 0x0da0),
103 INTC_VECT(FLCTL_FLTREQ0I, 0x0dc0), INTC_VECT(FLCTL_FLTREQ1I, 0x0de0),
104 INTC_VECT(SDHI0_SDHI0I0, 0x0e00), INTC_VECT(SDHI0_SDHI0I1, 0x0e20),
105 INTC_VECT(SDHI0_SDHI0I2, 0x0e40), INTC_VECT(SDHI0_SDHI0I3, 0x0e60),
106 INTC_VECT(SDHI1_SDHI1I0, 0x0e80), INTC_VECT(SDHI1_SDHI1I1, 0x0ea0),
107 INTC_VECT(SDHI1_SDHI1I2, 0x0ec0),
108 INTC_VECT(IRREM, 0x0f60),
109 INTC_VECT(IRDA, 0x0480),
110 INTC_VECT(TPU0, 0x04a0),
111 INTC_VECT(TTI20, 0x1100),
112 INTC_VECT(DDM, 0x1140),
113 INTC_VECT(SDHI2_SDHI2I0, 0x1200), INTC_VECT(SDHI2_SDHI2I1, 0x1220),
114 INTC_VECT(SDHI2_SDHI2I2, 0x1240), INTC_VECT(SDHI2_SDHI2I3, 0x1260),
115 INTC_VECT(RWDT0, 0x1280),
116 INTC_VECT(DMAC1_1_DEI0, 0x2000), INTC_VECT(DMAC1_1_DEI1, 0x2020),
117 INTC_VECT(DMAC1_1_DEI2, 0x2040), INTC_VECT(DMAC1_1_DEI3, 0x2060),
118 INTC_VECT(DMAC1_2_DEI4, 0x2080), INTC_VECT(DMAC1_2_DEI5, 0x20a0),
119 INTC_VECT(DMAC1_2_DADERR, 0x20c0),
120 INTC_VECT(DMAC2_1_DEI0, 0x2100), INTC_VECT(DMAC2_1_DEI1, 0x2120),
121 INTC_VECT(DMAC2_1_DEI2, 0x2140), INTC_VECT(DMAC2_1_DEI3, 0x2160),
122 INTC_VECT(DMAC2_2_DEI4, 0x2180), INTC_VECT(DMAC2_2_DEI5, 0x21a0),
123 INTC_VECT(DMAC2_2_DADERR, 0x21c0),
124 INTC_VECT(DMAC3_1_DEI0, 0x2200), INTC_VECT(DMAC3_1_DEI1, 0x2220),
125 INTC_VECT(DMAC3_1_DEI2, 0x2240), INTC_VECT(DMAC3_1_DEI3, 0x2260),
126 INTC_VECT(DMAC3_2_DEI4, 0x2280), INTC_VECT(DMAC3_2_DEI5, 0x22a0),
127 INTC_VECT(DMAC3_2_DADERR, 0x22c0),
128 INTC_VECT(SHWYSTAT_RT, 0x1300), INTC_VECT(SHWYSTAT_HS, 0x1320),
129 INTC_VECT(SHWYSTAT_COM, 0x1340),
130 INTC_VECT(HDMI, 0x17e0),
131 INTC_VECT(SPU2_SPU0, 0x1800), INTC_VECT(SPU2_SPU1, 0x1820),
132 INTC_VECT(FSI, 0x1840),
133 INTC_VECT(FMSI, 0x1860),
134 INTC_VECT(MIPI_HSI, 0x18e0),
135 INTC_VECT(IPMMU_IPMMUD, 0x1920),
136 INTC_VECT(CEC_1, 0x1940), INTC_VECT(CEC_2, 0x1960),
137 INTC_VECT(AP_ARM_CTIIRQ, 0x1980),
138 INTC_VECT(AP_ARM_DMAEXTERRIRQ, 0x19a0),
139 INTC_VECT(AP_ARM_DMAIRQ, 0x19c0),
140 INTC_VECT(AP_ARM_DMASIRQ, 0x19e0),
141 INTC_VECT(MFIS2, 0x1a00),
142 INTC_VECT(CPORTR2S, 0x1a20),
143 INTC_VECT(CMT14, 0x1a40), INTC_VECT(CMT15, 0x1a60),
144 INTC_VECT(MMC_MMC_ERR, 0x1ac0), INTC_VECT(MMC_MMC_NOR, 0x1ae0),
145 INTC_VECT(IIC4_ALI4, 0x1b00), INTC_VECT(IIC4_TACKI4, 0x1b20),
146 INTC_VECT(IIC4_WAITI4, 0x1b40), INTC_VECT(IIC4_DTEI4, 0x1b60),
147 INTC_VECT(IIC3_ALI3, 0x1b80), INTC_VECT(IIC3_TACKI3, 0x1ba0),
148 INTC_VECT(IIC3_WAITI3, 0x1bc0), INTC_VECT(IIC3_DTEI3, 0x1be0),
149 INTC_VECT(USB0_USB0I1, 0x1c80), INTC_VECT(USB0_USB0I0, 0x1ca0),
150 INTC_VECT(USB1_USB1I1, 0x1cc0), INTC_VECT(USB1_USB1I0, 0x1ce0),
151 INTC_VECT(USBHSDMAC1_USHDMI, 0x1d00),
152};
153
154static struct intc_group intca_groups[] __initdata = {
155 INTC_GROUP(DMAC1_1, DMAC1_1_DEI0,
156 DMAC1_1_DEI1, DMAC1_1_DEI2, DMAC1_1_DEI3),
157 INTC_GROUP(DMAC1_2, DMAC1_2_DEI4,
158 DMAC1_2_DEI5, DMAC1_2_DADERR),
159 INTC_GROUP(DMAC2_1, DMAC2_1_DEI0,
160 DMAC2_1_DEI1, DMAC2_1_DEI2, DMAC2_1_DEI3),
161 INTC_GROUP(DMAC2_2, DMAC2_2_DEI4,
162 DMAC2_2_DEI5, DMAC2_2_DADERR),
163 INTC_GROUP(DMAC3_1, DMAC3_1_DEI0,
164 DMAC3_1_DEI1, DMAC3_1_DEI2, DMAC3_1_DEI3),
165 INTC_GROUP(DMAC3_2, DMAC3_2_DEI4,
166 DMAC3_2_DEI5, DMAC3_2_DADERR),
167 INTC_GROUP(AP_ARM1, AP_ARM_IRQPMU, AP_ARM_COMMTX, AP_ARM_COMMRX),
168 INTC_GROUP(AP_ARM2, AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
169 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ),
170 INTC_GROUP(SPU2, SPU2_SPU0, SPU2_SPU1),
171 INTC_GROUP(FLCTL, FLCTL_FLSTEI, FLCTL_FLTENDI,
172 FLCTL_FLTREQ0I, FLCTL_FLTREQ1I),
173 INTC_GROUP(IIC1, IIC1_ALI1, IIC1_TACKI1, IIC1_WAITI1, IIC1_DTEI1),
174 INTC_GROUP(SDHI0, SDHI0_SDHI0I0, SDHI0_SDHI0I1,
175 SDHI0_SDHI0I2, SDHI0_SDHI0I3),
176 INTC_GROUP(SDHI1, SDHI1_SDHI1I0, SDHI1_SDHI1I1,
177 SDHI1_SDHI1I2),
178 INTC_GROUP(SDHI2, SDHI2_SDHI2I0, SDHI2_SDHI2I1,
179 SDHI2_SDHI2I2, SDHI2_SDHI2I3),
180 INTC_GROUP(SHWYSTAT, SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM),
181};
182
183static struct intc_mask_reg intca_mask_registers[] __initdata = {
184 { 0xe6940080, 0xe69400c0, 8, /* IMR0A / IMCR0A */
185 { DMAC2_1_DEI3, DMAC2_1_DEI2, DMAC2_1_DEI1, DMAC2_1_DEI0,
186 AP_ARM_IRQPMU, 0, AP_ARM_COMMTX, AP_ARM_COMMRX } },
187 { 0xe6940084, 0xe69400c4, 8, /* IMR1A / IMCR1A */
188 { 0, CRYPT_STD, DIRC, 0,
189 DMAC1_1_DEI3, DMAC1_1_DEI2, DMAC1_1_DEI1, DMAC1_1_DEI0 } },
190 { 0xe6940088, 0xe69400c8, 8, /* IMR2A / IMCR2A */
191 { 0, 0, 0, 0,
192 BBIF1, BBIF2, MFI_MFIS, MFI_MFIM } },
193 { 0xe694008c, 0xe69400cc, 8, /* IMR3A / IMCR3A */
194 { DMAC3_1_DEI3, DMAC3_1_DEI2, DMAC3_1_DEI1, DMAC3_1_DEI0,
195 DMAC3_2_DADERR, DMAC3_2_DEI5, DMAC3_2_DEI4, IRDA } },
196 { 0xe6940090, 0xe69400d0, 8, /* IMR4A / IMCR4A */
197 { DDM, 0, 0, 0,
198 0, 0, 0, 0 } },
199 { 0xe6940094, 0xe69400d4, 8, /* IMR5A / IMCR5A */
200 { KEYSC_KEY, DMAC1_2_DADERR, DMAC1_2_DEI5, DMAC1_2_DEI4,
201 SCIFA3, SCIFA2, SCIFA1, SCIFA0 } },
202 { 0xe6940098, 0xe69400d8, 8, /* IMR6A / IMCR6A */
203 { SCIFB, SCIFA5, SCIFA4, MSIOF1,
204 0, 0, MSIOF2, 0 } },
205 { 0xe694009c, 0xe69400dc, 8, /* IMR7A / IMCR7A */
206 { SDHI0_SDHI0I3, SDHI0_SDHI0I2, SDHI0_SDHI0I1, SDHI0_SDHI0I0,
207 FLCTL_FLTREQ1I, FLCTL_FLTREQ0I, FLCTL_FLTENDI, FLCTL_FLSTEI } },
208 { 0xe69400a0, 0xe69400e0, 8, /* IMR8A / IMCR8A */
209 { 0, SDHI1_SDHI1I2, SDHI1_SDHI1I1, SDHI1_SDHI1I0,
210 TTI20, USBHSDMAC0_USHDMI, 0, 0 } },
211 { 0xe69400a4, 0xe69400e4, 8, /* IMR9A / IMCR9A */
212 { CMT1_CMT13, CMT1_CMT12, CMT1_CMT11, CMT1_CMT10,
213 CMT2, 0, 0, _3DG_SGX540 } },
214 { 0xe69400a8, 0xe69400e8, 8, /* IMR10A / IMCR10A */
215 { 0, DMAC2_2_DADERR, DMAC2_2_DEI5, DMAC2_2_DEI4,
216 0, 0, 0, 0 } },
217 { 0xe69400ac, 0xe69400ec, 8, /* IMR11A / IMCR11A */
218 { IIC1_DTEI1, IIC1_WAITI1, IIC1_TACKI1, IIC1_ALI1,
219 0, 0, IRREM, 0 } },
220 { 0xe69400b0, 0xe69400f0, 8, /* IMR12A / IMCR12A */
221 { 0, 0, TPU0, 0,
222 0, 0, 0, 0 } },
223 { 0xe69400b4, 0xe69400f4, 8, /* IMR13A / IMCR13A */
224 { SDHI2_SDHI2I3, SDHI2_SDHI2I2, SDHI2_SDHI2I1, SDHI2_SDHI2I0,
225 0, CMT3, 0, RWDT0 } },
226 { 0xe6950080, 0xe69500c0, 8, /* IMR0A3 / IMCR0A3 */
227 { SHWYSTAT_RT, SHWYSTAT_HS, SHWYSTAT_COM, 0,
228 0, 0, 0, 0 } },
229 { 0xe6950090, 0xe69500d0, 8, /* IMR4A3 / IMCR4A3 */
230 { 0, 0, 0, 0,
231 0, 0, 0, HDMI } },
232 { 0xe6950094, 0xe69500d4, 8, /* IMR5A3 / IMCR5A3 */
233 { SPU2_SPU0, SPU2_SPU1, FSI, FMSI,
234 0, 0, 0, MIPI_HSI } },
235 { 0xe6950098, 0xe69500d8, 8, /* IMR6A3 / IMCR6A3 */
236 { 0, IPMMU_IPMMUD, CEC_1, CEC_2,
237 AP_ARM_CTIIRQ, AP_ARM_DMAEXTERRIRQ,
238 AP_ARM_DMAIRQ, AP_ARM_DMASIRQ } },
239 { 0xe695009c, 0xe69500dc, 8, /* IMR7A3 / IMCR7A3 */
240 { MFIS2, CPORTR2S, CMT14, CMT15,
241 0, 0, MMC_MMC_ERR, MMC_MMC_NOR } },
242 { 0xe69500a0, 0xe69500e0, 8, /* IMR8A3 / IMCR8A3 */
243 { IIC4_ALI4, IIC4_TACKI4, IIC4_WAITI4, IIC4_DTEI4,
244 IIC3_ALI3, IIC3_TACKI3, IIC3_WAITI3, IIC3_DTEI3 } },
245 { 0xe69500a4, 0xe69500e4, 8, /* IMR9A3 / IMCR9A3 */
246 { 0, 0, 0, 0,
247 USB0_USB0I1, USB0_USB0I0, USB1_USB1I1, USB1_USB1I0 } },
248 { 0xe69500a8, 0xe69500e8, 8, /* IMR10A3 / IMCR10A3 */
249 { USBHSDMAC1_USHDMI, 0, 0, 0,
250 0, 0, 0, 0 } },
251};
252
253static struct intc_prio_reg intca_prio_registers[] __initdata = {
254 { 0xe6940000, 0, 16, 4, /* IPRAA */ { DMAC3_1, DMAC3_2, CMT2, 0 } },
255 { 0xe6940004, 0, 16, 4, /* IPRBA */ { IRDA, 0, BBIF1, BBIF2 } },
256 { 0xe6940008, 0, 16, 4, /* IPRCA */ { 0, CRYPT_STD,
257 CMT1_CMT11, AP_ARM1 } },
258 { 0xe694000c, 0, 16, 4, /* IPRDA */ { 0, 0,
259 CMT1_CMT12, 0 } },
260 { 0xe6940010, 0, 16, 4, /* IPREA */ { DMAC1_1, MFI_MFIS,
261 MFI_MFIM, 0 } },
262 { 0xe6940014, 0, 16, 4, /* IPRFA */ { KEYSC_KEY, DMAC1_2,
263 _3DG_SGX540, CMT1_CMT10 } },
264 { 0xe6940018, 0, 16, 4, /* IPRGA */ { SCIFA0, SCIFA1,
265 SCIFA2, SCIFA3 } },
266 { 0xe694001c, 0, 16, 4, /* IPRGH */ { MSIOF2, USBHSDMAC0_USHDMI,
267 FLCTL, SDHI0 } },
268 { 0xe6940020, 0, 16, 4, /* IPRIA */ { MSIOF1, SCIFA4,
269 0/* MSU */, IIC1 } },
270 { 0xe6940024, 0, 16, 4, /* IPRJA */ { DMAC2_1, DMAC2_2,
271 0/* MSUG */, TTI20 } },
272 { 0xe6940028, 0, 16, 4, /* IPRKA */ { 0, CMT1_CMT13, IRREM, SDHI1 } },
273 { 0xe694002c, 0, 16, 4, /* IPRLA */ { TPU0, 0, 0, 0 } },
274 { 0xe6940030, 0, 16, 4, /* IPRMA */ { 0, CMT3, 0, RWDT0 } },
275 { 0xe6940034, 0, 16, 4, /* IPRNA */ { SCIFB, SCIFA5, 0, DDM } },
276 { 0xe6940038, 0, 16, 4, /* IPROA */ { 0, 0, DIRC, SDHI2 } },
277 { 0xe6950000, 0, 16, 4, /* IPRAA3 */ { SHWYSTAT, 0, 0, 0 } },
278 { 0xe6950024, 0, 16, 4, /* IPRJA3 */ { 0, 0, 0, HDMI } },
279 { 0xe6950028, 0, 16, 4, /* IPRKA3 */ { SPU2, 0, FSI, FMSI } },
280 { 0xe695002c, 0, 16, 4, /* IPRLA3 */ { 0, 0, 0, MIPI_HSI } },
281 { 0xe6950030, 0, 16, 4, /* IPRMA3 */ { IPMMU_IPMMUD, 0,
282 CEC_1, CEC_2 } },
283 { 0xe6950034, 0, 16, 4, /* IPRNA3 */ { AP_ARM2, 0, 0, 0 } },
284 { 0xe6950038, 0, 16, 4, /* IPROA3 */ { MFIS2, CPORTR2S,
285 CMT14, CMT15 } },
286 { 0xe695003c, 0, 16, 4, /* IPRPA3 */ { 0, 0,
287 MMC_MMC_ERR, MMC_MMC_NOR } },
288 { 0xe6950040, 0, 16, 4, /* IPRQA3 */ { IIC4_ALI4, IIC4_TACKI4,
289 IIC4_WAITI4, IIC4_DTEI4 } },
290 { 0xe6950044, 0, 16, 4, /* IPRRA3 */ { IIC3_ALI3, IIC3_TACKI3,
291 IIC3_WAITI3, IIC3_DTEI3 } },
292 { 0xe6950048, 0, 16, 4, /* IPRSA3 */ { 0/*ERI*/, 0/*RXI*/,
293 0/*TXI*/, 0/*TEI*/} },
294 { 0xe695004c, 0, 16, 4, /* IPRTA3 */ { USB0_USB0I1, USB0_USB0I0,
295 USB1_USB1I1, USB1_USB1I0 } },
296 { 0xe6950050, 0, 16, 4, /* IPRUA3 */ { USBHSDMAC1_USHDMI, 0, 0, 0 } },
297};
298
299static DECLARE_INTC_DESC(intca_desc, "sh7372-intca",
300 intca_vectors, intca_groups,
301 intca_mask_registers, intca_prio_registers,
302 NULL);
303
304INTC_IRQ_PINS_16(intca_irq_pins_lo, 0xe6900000,
305 INTC_VECT, "sh7372-intca-irq-lo");
306
307INTC_IRQ_PINS_16H(intca_irq_pins_hi, 0xe6900000,
308 INTC_VECT, "sh7372-intca-irq-hi");
309
310enum {
311 UNUSED_INTCS = 0,
312 ENABLED_INTCS,
313
314 /* interrupt sources INTCS */
315
316 /* IRQ0S - IRQ31S */
317 VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3,
318 RTDMAC_1_DEI0, RTDMAC_1_DEI1, RTDMAC_1_DEI2, RTDMAC_1_DEI3,
319 CEU, BEU_BEU0, BEU_BEU1, BEU_BEU2,
320 /* MFI */
321 /* BBIF2 */
322 VPU,
323 TSIF1,
324 /* 3DG */
325 _2DDMAC,
326 IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2,
327 IPMMU_IPMMUR, IPMMU_IPMMUR2,
328 RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR,
329 /* KEYSC */
330 /* TTI20 */
331 MSIOF,
332 IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0,
333 TMU_TUNI0, TMU_TUNI1, TMU_TUNI2,
334 CMT0,
335 TSIF0,
336 /* CMT2 */
337 LMB,
338 CTI,
339 /* RWDT0 */
340 ICB,
341 JPU_JPEG,
342 LCDC,
343 LCRC,
344 RTDMAC2_1_DEI0, RTDMAC2_1_DEI1, RTDMAC2_1_DEI2, RTDMAC2_1_DEI3,
345 RTDMAC2_2_DEI4, RTDMAC2_2_DEI5, RTDMAC2_2_DADERR,
346 ISP,
347 LCDC1,
348 CSIRX,
349 DSITX_DSITX0,
350 DSITX_DSITX1,
351 /* SPU2 */
352 /* FSI */
353 /* FMSI */
354 /* HDMI */
355 TMU1_TUNI0, TMU1_TUNI1, TMU1_TUNI2,
356 CMT4,
357 DSITX1_DSITX1_0,
358 DSITX1_DSITX1_1,
359 MFIS2_INTCS, /* Priority always enabled using ENABLED_INTCS */
360 CPORTS2R,
361 /* CEC */
362 JPU6E,
363
364 /* interrupt groups INTCS */
365 RTDMAC_1, RTDMAC_2, VEU, BEU, IIC0, IPMMU, IIC2,
366 RTDMAC2_1, RTDMAC2_2, TMU1, DSITX,
367};
368
369static struct intc_vect intcs_vectors[] = {
370 /* IRQ0S - IRQ31S */
371 INTCS_VECT(VEU_VEU0, 0x700), INTCS_VECT(VEU_VEU1, 0x720),
372 INTCS_VECT(VEU_VEU2, 0x740), INTCS_VECT(VEU_VEU3, 0x760),
373 INTCS_VECT(RTDMAC_1_DEI0, 0x800), INTCS_VECT(RTDMAC_1_DEI1, 0x820),
374 INTCS_VECT(RTDMAC_1_DEI2, 0x840), INTCS_VECT(RTDMAC_1_DEI3, 0x860),
375 INTCS_VECT(CEU, 0x880), INTCS_VECT(BEU_BEU0, 0x8a0),
376 INTCS_VECT(BEU_BEU1, 0x8c0), INTCS_VECT(BEU_BEU2, 0x8e0),
377 /* MFI */
378 /* BBIF2 */
379 INTCS_VECT(VPU, 0x980),
380 INTCS_VECT(TSIF1, 0x9a0),
381 /* 3DG */
382 INTCS_VECT(_2DDMAC, 0xa00),
383 INTCS_VECT(IIC2_ALI2, 0xa80), INTCS_VECT(IIC2_TACKI2, 0xaa0),
384 INTCS_VECT(IIC2_WAITI2, 0xac0), INTCS_VECT(IIC2_DTEI2, 0xae0),
385 INTCS_VECT(IPMMU_IPMMUR, 0xb00), INTCS_VECT(IPMMU_IPMMUR2, 0xb20),
386 INTCS_VECT(RTDMAC_2_DEI4, 0xb80), INTCS_VECT(RTDMAC_2_DEI5, 0xba0),
387 INTCS_VECT(RTDMAC_2_DADERR, 0xbc0),
388 /* KEYSC */
389 /* TTI20 */
390 INTCS_VECT(MSIOF, 0x0d20),
391 INTCS_VECT(IIC0_ALI0, 0xe00), INTCS_VECT(IIC0_TACKI0, 0xe20),
392 INTCS_VECT(IIC0_WAITI0, 0xe40), INTCS_VECT(IIC0_DTEI0, 0xe60),
393 INTCS_VECT(TMU_TUNI0, 0xe80), INTCS_VECT(TMU_TUNI1, 0xea0),
394 INTCS_VECT(TMU_TUNI2, 0xec0),
395 INTCS_VECT(CMT0, 0xf00),
396 INTCS_VECT(TSIF0, 0xf20),
397 /* CMT2 */
398 INTCS_VECT(LMB, 0xf60),
399 INTCS_VECT(CTI, 0x400),
400 /* RWDT0 */
401 INTCS_VECT(ICB, 0x480),
402 INTCS_VECT(JPU_JPEG, 0x560),
403 INTCS_VECT(LCDC, 0x580),
404 INTCS_VECT(LCRC, 0x5a0),
405 INTCS_VECT(RTDMAC2_1_DEI0, 0x1300), INTCS_VECT(RTDMAC2_1_DEI1, 0x1320),
406 INTCS_VECT(RTDMAC2_1_DEI2, 0x1340), INTCS_VECT(RTDMAC2_1_DEI3, 0x1360),
407 INTCS_VECT(RTDMAC2_2_DEI4, 0x1380), INTCS_VECT(RTDMAC2_2_DEI5, 0x13a0),
408 INTCS_VECT(RTDMAC2_2_DADERR, 0x13c0),
409 INTCS_VECT(ISP, 0x1720),
410 INTCS_VECT(LCDC1, 0x1780),
411 INTCS_VECT(CSIRX, 0x17a0),
412 INTCS_VECT(DSITX_DSITX0, 0x17c0),
413 INTCS_VECT(DSITX_DSITX1, 0x17e0),
414 /* SPU2 */
415 /* FSI */
416 /* FMSI */
417 /* HDMI */
418 INTCS_VECT(TMU1_TUNI0, 0x1900), INTCS_VECT(TMU1_TUNI1, 0x1920),
419 INTCS_VECT(TMU1_TUNI2, 0x1940),
420 INTCS_VECT(CMT4, 0x1980),
421 INTCS_VECT(DSITX1_DSITX1_0, 0x19a0),
422 INTCS_VECT(DSITX1_DSITX1_1, 0x19c0),
423 INTCS_VECT(MFIS2_INTCS, 0x1a00),
424 INTCS_VECT(CPORTS2R, 0x1a20),
425 /* CEC */
426 INTCS_VECT(JPU6E, 0x1a80),
427};
428
429static struct intc_group intcs_groups[] __initdata = {
430 INTC_GROUP(RTDMAC_1, RTDMAC_1_DEI0, RTDMAC_1_DEI1,
431 RTDMAC_1_DEI2, RTDMAC_1_DEI3),
432 INTC_GROUP(RTDMAC_2, RTDMAC_2_DEI4, RTDMAC_2_DEI5, RTDMAC_2_DADERR),
433 INTC_GROUP(VEU, VEU_VEU0, VEU_VEU1, VEU_VEU2, VEU_VEU3),
434 INTC_GROUP(BEU, BEU_BEU0, BEU_BEU1, BEU_BEU2),
435 INTC_GROUP(IIC0, IIC0_ALI0, IIC0_TACKI0, IIC0_WAITI0, IIC0_DTEI0),
436 INTC_GROUP(IPMMU, IPMMU_IPMMUR, IPMMU_IPMMUR2),
437 INTC_GROUP(IIC2, IIC2_ALI2, IIC2_TACKI2, IIC2_WAITI2, IIC2_DTEI2),
438 INTC_GROUP(RTDMAC2_1, RTDMAC2_1_DEI0, RTDMAC2_1_DEI1,
439 RTDMAC2_1_DEI2, RTDMAC2_1_DEI3),
440 INTC_GROUP(RTDMAC2_2, RTDMAC2_2_DEI4,
441 RTDMAC2_2_DEI5, RTDMAC2_2_DADERR),
442 INTC_GROUP(TMU1, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0),
443 INTC_GROUP(DSITX, DSITX_DSITX0, DSITX_DSITX1),
444};
445
446static struct intc_mask_reg intcs_mask_registers[] = {
447 { 0xffd20184, 0xffd201c4, 8, /* IMR1SA / IMCR1SA */
448 { BEU_BEU2, BEU_BEU1, BEU_BEU0, CEU,
449 VEU_VEU3, VEU_VEU2, VEU_VEU1, VEU_VEU0 } },
450 { 0xffd20188, 0xffd201c8, 8, /* IMR2SA / IMCR2SA */
451 { 0, 0, 0, VPU,
452 0, 0, 0, 0 } },
453 { 0xffd2018c, 0xffd201cc, 8, /* IMR3SA / IMCR3SA */
454 { 0, 0, 0, _2DDMAC,
455 0, 0, 0, ICB } },
456 { 0xffd20190, 0xffd201d0, 8, /* IMR4SA / IMCR4SA */
457 { 0, 0, 0, CTI,
458 JPU_JPEG, 0, LCRC, LCDC } },
459 { 0xffd20194, 0xffd201d4, 8, /* IMR5SA / IMCR5SA */
460 { 0, RTDMAC_2_DADERR, RTDMAC_2_DEI5, RTDMAC_2_DEI4,
461 RTDMAC_1_DEI3, RTDMAC_1_DEI2, RTDMAC_1_DEI1, RTDMAC_1_DEI0 } },
462 { 0xffd20198, 0xffd201d8, 8, /* IMR6SA / IMCR6SA */
463 { 0, 0, MSIOF, 0,
464 0, 0, 0, 0 } },
465 { 0xffd2019c, 0xffd201dc, 8, /* IMR7SA / IMCR7SA */
466 { 0, TMU_TUNI2, TMU_TUNI1, TMU_TUNI0,
467 0, 0, 0, 0 } },
468 { 0xffd201a4, 0xffd201e4, 8, /* IMR9SA / IMCR9SA */
469 { 0, 0, 0, CMT0,
470 IIC2_DTEI2, IIC2_WAITI2, IIC2_TACKI2, IIC2_ALI2 } },
471 { 0xffd201a8, 0xffd201e8, 8, /* IMR10SA / IMCR10SA */
472 { 0, 0, IPMMU_IPMMUR2, IPMMU_IPMMUR,
473 0, 0, 0, 0 } },
474 { 0xffd201ac, 0xffd201ec, 8, /* IMR11SA / IMCR11SA */
475 { IIC0_DTEI0, IIC0_WAITI0, IIC0_TACKI0, IIC0_ALI0,
476 0, TSIF1, LMB, TSIF0 } },
477 { 0xffd50180, 0xffd501c0, 8, /* IMR0SA3 / IMCR0SA3 */
478 { 0, RTDMAC2_2_DADERR, RTDMAC2_2_DEI5, RTDMAC2_2_DEI4,
479 RTDMAC2_1_DEI3, RTDMAC2_1_DEI2, RTDMAC2_1_DEI1, RTDMAC2_1_DEI0 } },
480 { 0xffd50190, 0xffd501d0, 8, /* IMR4SA3 / IMCR4SA3 */
481 { 0, ISP, 0, 0,
482 LCDC1, CSIRX, DSITX_DSITX0, DSITX_DSITX1 } },
483 { 0xffd50198, 0xffd501d8, 8, /* IMR6SA3 / IMCR6SA3 */
484 { 0, TMU1_TUNI2, TMU1_TUNI1, TMU1_TUNI0,
485 CMT4, DSITX1_DSITX1_0, DSITX1_DSITX1_1, 0 } },
486 { 0xffd5019c, 0xffd501dc, 8, /* IMR7SA3 / IMCR7SA3 */
487 { MFIS2_INTCS, CPORTS2R, 0, 0,
488 JPU6E, 0, 0, 0 } },
489};
490
491/* Priority is needed for INTCA to receive the INTCS interrupt */
492static struct intc_prio_reg intcs_prio_registers[] = {
493 { 0xffd20000, 0, 16, 4, /* IPRAS */ { CTI, 0, _2DDMAC, ICB } },
494 { 0xffd20004, 0, 16, 4, /* IPRBS */ { JPU_JPEG, LCDC, 0, LCRC } },
495 { 0xffd20010, 0, 16, 4, /* IPRES */ { RTDMAC_1, CEU, 0, VPU } },
496 { 0xffd20014, 0, 16, 4, /* IPRFS */ { 0, RTDMAC_2, 0, CMT0 } },
497 { 0xffd20018, 0, 16, 4, /* IPRGS */ { TMU_TUNI0, TMU_TUNI1,
498 TMU_TUNI2, TSIF1 } },
499 { 0xffd2001c, 0, 16, 4, /* IPRHS */ { 0, 0, VEU, BEU } },
500 { 0xffd20020, 0, 16, 4, /* IPRIS */ { 0, MSIOF, TSIF0, IIC0 } },
501 { 0xffd20028, 0, 16, 4, /* IPRKS */ { 0, 0, LMB, 0 } },
502 { 0xffd2002c, 0, 16, 4, /* IPRLS */ { IPMMU, 0, 0, 0 } },
503 { 0xffd20030, 0, 16, 4, /* IPRMS */ { IIC2, 0, 0, 0 } },
504 { 0xffd50000, 0, 16, 4, /* IPRAS3 */ { RTDMAC2_1, 0, 0, 0 } },
505 { 0xffd50004, 0, 16, 4, /* IPRBS3 */ { RTDMAC2_2, 0, 0, 0 } },
506 { 0xffd50020, 0, 16, 4, /* IPRIS3 */ { 0, ISP, 0, 0 } },
507 { 0xffd50024, 0, 16, 4, /* IPRJS3 */ { LCDC1, CSIRX, DSITX, 0 } },
508 { 0xffd50030, 0, 16, 4, /* IPRMS3 */ { TMU1, 0, 0, 0 } },
509 { 0xffd50034, 0, 16, 4, /* IPRNS3 */ { CMT4, DSITX1_DSITX1_0,
510 DSITX1_DSITX1_1, 0 } },
511 { 0xffd50038, 0, 16, 4, /* IPROS3 */ { ENABLED_INTCS, CPORTS2R,
512 0, 0 } },
513 { 0xffd5003c, 0, 16, 4, /* IPRPS3 */ { JPU6E, 0, 0, 0 } },
514};
515
516static struct resource intcs_resources[] __initdata = {
517 [0] = {
518 .start = 0xffd20000,
519 .end = 0xffd201ff,
520 .flags = IORESOURCE_MEM,
521 },
522 [1] = {
523 .start = 0xffd50000,
524 .end = 0xffd501ff,
525 .flags = IORESOURCE_MEM,
526 }
527};
528
529static struct intc_desc intcs_desc __initdata = {
530 .name = "sh7372-intcs",
531 .force_enable = ENABLED_INTCS,
532 .skip_syscore_suspend = true,
533 .resource = intcs_resources,
534 .num_resources = ARRAY_SIZE(intcs_resources),
535 .hw = INTC_HW_DESC(intcs_vectors, intcs_groups, intcs_mask_registers,
536 intcs_prio_registers, NULL, NULL),
537};
538
539static void intcs_demux(unsigned int irq, struct irq_desc *desc)
540{
541 void __iomem *reg = (void *)irq_get_handler_data(irq);
542 unsigned int evtcodeas = ioread32(reg);
543
544 generic_handle_irq(intcs_evt2irq(evtcodeas));
545}
546
547static void __iomem *intcs_ffd2;
548static void __iomem *intcs_ffd5;
549
550void __init sh7372_init_irq(void)
551{
552 void __iomem *intevtsa;
553 int n;
554
555 intcs_ffd2 = ioremap_nocache(0xffd20000, PAGE_SIZE);
556 intevtsa = intcs_ffd2 + 0x100;
557 intcs_ffd5 = ioremap_nocache(0xffd50000, PAGE_SIZE);
558
559 register_intc_controller(&intca_desc);
560 register_intc_controller(&intca_irq_pins_lo_desc);
561 register_intc_controller(&intca_irq_pins_hi_desc);
562 register_intc_controller(&intcs_desc);
563
564 /* setup dummy cascade chip for INTCS */
565 n = evt2irq(0xf80);
566 irq_alloc_desc_at(n, numa_node_id());
567 irq_set_chip_and_handler_name(n, &dummy_irq_chip,
568 handle_level_irq, "level");
569 set_irq_flags(n, IRQF_VALID); /* yuck */
570
571 /* demux using INTEVTSA */
572 irq_set_handler_data(n, (void *)intevtsa);
573 irq_set_chained_handler(n, intcs_demux);
574
575 /* unmask INTCS in INTAMASK */
576 iowrite16(0, intcs_ffd2 + 0x104);
577}
578
579static unsigned short ffd2[0x200];
580static unsigned short ffd5[0x100];
581
582void sh7372_intcs_suspend(void)
583{
584 int k;
585
586 for (k = 0x00; k <= 0x30; k += 4)
587 ffd2[k] = __raw_readw(intcs_ffd2 + k);
588
589 for (k = 0x80; k <= 0xb0; k += 4)
590 ffd2[k] = __raw_readb(intcs_ffd2 + k);
591
592 for (k = 0x180; k <= 0x188; k += 4)
593 ffd2[k] = __raw_readb(intcs_ffd2 + k);
594
595 for (k = 0x00; k <= 0x3c; k += 4)
596 ffd5[k] = __raw_readw(intcs_ffd5 + k);
597
598 for (k = 0x80; k <= 0x9c; k += 4)
599 ffd5[k] = __raw_readb(intcs_ffd5 + k);
600}
601
602void sh7372_intcs_resume(void)
603{
604 int k;
605
606 for (k = 0x00; k <= 0x30; k += 4)
607 __raw_writew(ffd2[k], intcs_ffd2 + k);
608
609 for (k = 0x80; k <= 0xb0; k += 4)
610 __raw_writeb(ffd2[k], intcs_ffd2 + k);
611
612 for (k = 0x180; k <= 0x188; k += 4)
613 __raw_writeb(ffd2[k], intcs_ffd2 + k);
614
615 for (k = 0x00; k <= 0x3c; k += 4)
616 __raw_writew(ffd5[k], intcs_ffd5 + k);
617
618 for (k = 0x80; k <= 0x9c; k += 4)
619 __raw_writeb(ffd5[k], intcs_ffd5 + k);
620}
621
622#define E694_BASE IOMEM(0xe6940000)
623#define E695_BASE IOMEM(0xe6950000)
624
625static unsigned short e694[0x200];
626static unsigned short e695[0x200];
627
628void sh7372_intca_suspend(void)
629{
630 int k;
631
632 for (k = 0x00; k <= 0x38; k += 4)
633 e694[k] = __raw_readw(E694_BASE + k);
634
635 for (k = 0x80; k <= 0xb4; k += 4)
636 e694[k] = __raw_readb(E694_BASE + k);
637
638 for (k = 0x180; k <= 0x1b4; k += 4)
639 e694[k] = __raw_readb(E694_BASE + k);
640
641 for (k = 0x00; k <= 0x50; k += 4)
642 e695[k] = __raw_readw(E695_BASE + k);
643
644 for (k = 0x80; k <= 0xa8; k += 4)
645 e695[k] = __raw_readb(E695_BASE + k);
646
647 for (k = 0x180; k <= 0x1a8; k += 4)
648 e695[k] = __raw_readb(E695_BASE + k);
649}
650
651void sh7372_intca_resume(void)
652{
653 int k;
654
655 for (k = 0x00; k <= 0x38; k += 4)
656 __raw_writew(e694[k], E694_BASE + k);
657
658 for (k = 0x80; k <= 0xb4; k += 4)
659 __raw_writeb(e694[k], E694_BASE + k);
660
661 for (k = 0x180; k <= 0x1b4; k += 4)
662 __raw_writeb(e694[k], E694_BASE + k);
663
664 for (k = 0x00; k <= 0x50; k += 4)
665 __raw_writew(e695[k], E695_BASE + k);
666
667 for (k = 0x80; k <= 0xa8; k += 4)
668 __raw_writeb(e695[k], E695_BASE + k);
669
670 for (k = 0x180; k <= 0x1a8; k += 4)
671 __raw_writeb(e695[k], E695_BASE + k);
672}
diff --git a/arch/arm/mach-shmobile/pm-sh7372.c b/arch/arm/mach-shmobile/pm-sh7372.c
deleted file mode 100644
index c0293ae4b013..000000000000
--- a/arch/arm/mach-shmobile/pm-sh7372.c
+++ /dev/null
@@ -1,549 +0,0 @@
1/*
2 * sh7372 Power management support
3 *
4 * Copyright (C) 2011 Magnus Damm
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#include <linux/pm.h>
12#include <linux/suspend.h>
13#include <linux/cpuidle.h>
14#include <linux/module.h>
15#include <linux/list.h>
16#include <linux/err.h>
17#include <linux/slab.h>
18#include <linux/pm_clock.h>
19#include <linux/platform_device.h>
20#include <linux/delay.h>
21#include <linux/irq.h>
22#include <linux/bitrev.h>
23#include <linux/console.h>
24
25#include <asm/cpuidle.h>
26#include <asm/io.h>
27#include <asm/tlbflush.h>
28#include <asm/suspend.h>
29
30#include "common.h"
31#include "pm-rmobile.h"
32#include "sh7372.h"
33
34/* DBG */
35#define DBGREG1 IOMEM(0xe6100020)
36#define DBGREG9 IOMEM(0xe6100040)
37
38/* CPGA */
39#define SYSTBCR IOMEM(0xe6150024)
40#define MSTPSR0 IOMEM(0xe6150030)
41#define MSTPSR1 IOMEM(0xe6150038)
42#define MSTPSR2 IOMEM(0xe6150040)
43#define MSTPSR3 IOMEM(0xe6150048)
44#define MSTPSR4 IOMEM(0xe615004c)
45#define PLLC01STPCR IOMEM(0xe61500c8)
46
47/* SYSC */
48#define SYSC_BASE IOMEM(0xe6180000)
49
50#define SBAR IOMEM(0xe6180020)
51#define WUPRMSK IOMEM(0xe6180028)
52#define WUPSMSK IOMEM(0xe618002c)
53#define WUPSMSK2 IOMEM(0xe6180048)
54#define WUPSFAC IOMEM(0xe6180098)
55#define IRQCR IOMEM(0xe618022c)
56#define IRQCR2 IOMEM(0xe6180238)
57#define IRQCR3 IOMEM(0xe6180244)
58#define IRQCR4 IOMEM(0xe6180248)
59#define PDNSEL IOMEM(0xe6180254)
60
61/* INTC */
62#define ICR1A IOMEM(0xe6900000)
63#define ICR2A IOMEM(0xe6900004)
64#define ICR3A IOMEM(0xe6900008)
65#define ICR4A IOMEM(0xe690000c)
66#define INTMSK00A IOMEM(0xe6900040)
67#define INTMSK10A IOMEM(0xe6900044)
68#define INTMSK20A IOMEM(0xe6900048)
69#define INTMSK30A IOMEM(0xe690004c)
70
71/* MFIS */
72/* FIXME: pointing where? */
73#define SMFRAM 0xe6a70000
74
75/* AP-System Core */
76#define APARMBAREA IOMEM(0xe6f10020)
77
78#ifdef CONFIG_PM
79
80#define PM_DOMAIN_ON_OFF_LATENCY_NS 250000
81
82static int sh7372_a4r_pd_suspend(void)
83{
84 sh7372_intcs_suspend();
85 __raw_writel(0x300fffff, WUPRMSK); /* avoid wakeup */
86 return 0;
87}
88
89static bool a4s_suspend_ready;
90
91static int sh7372_a4s_pd_suspend(void)
92{
93 /*
94 * The A4S domain contains the CPU core and therefore it should
95 * only be turned off if the CPU is not in use. This may happen
96 * during system suspend, when SYSC is going to be used for generating
97 * resume signals and a4s_suspend_ready is set to let
98 * sh7372_enter_suspend() know that it can turn A4S off.
99 */
100 a4s_suspend_ready = true;
101 return -EBUSY;
102}
103
104static void sh7372_a4s_pd_resume(void)
105{
106 a4s_suspend_ready = false;
107}
108
109static int sh7372_a3sp_pd_suspend(void)
110{
111 /*
112 * Serial consoles make use of SCIF hardware located in A3SP,
113 * keep such power domain on if "no_console_suspend" is set.
114 */
115 return console_suspend_enabled ? 0 : -EBUSY;
116}
117
118static struct rmobile_pm_domain sh7372_pm_domains[] = {
119 {
120 .genpd.name = "A4LC",
121 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
122 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
123 .base = SYSC_BASE,
124 .bit_shift = 1,
125 },
126 {
127 .genpd.name = "A4MP",
128 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
129 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
130 .base = SYSC_BASE,
131 .bit_shift = 2,
132 },
133 {
134 .genpd.name = "D4",
135 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
136 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
137 .base = SYSC_BASE,
138 .bit_shift = 3,
139 },
140 {
141 .genpd.name = "A4R",
142 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
143 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
144 .base = SYSC_BASE,
145 .bit_shift = 5,
146 .suspend = sh7372_a4r_pd_suspend,
147 .resume = sh7372_intcs_resume,
148 },
149 {
150 .genpd.name = "A3RV",
151 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
152 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
153 .base = SYSC_BASE,
154 .bit_shift = 6,
155 },
156 {
157 .genpd.name = "A3RI",
158 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
159 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
160 .base = SYSC_BASE,
161 .bit_shift = 8,
162 },
163 {
164 .genpd.name = "A4S",
165 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
166 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
167 .base = SYSC_BASE,
168 .bit_shift = 10,
169 .gov = &pm_domain_always_on_gov,
170 .no_debug = true,
171 .suspend = sh7372_a4s_pd_suspend,
172 .resume = sh7372_a4s_pd_resume,
173 },
174 {
175 .genpd.name = "A3SP",
176 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
177 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
178 .base = SYSC_BASE,
179 .bit_shift = 11,
180 .gov = &pm_domain_always_on_gov,
181 .no_debug = true,
182 .suspend = sh7372_a3sp_pd_suspend,
183 },
184 {
185 .genpd.name = "A3SG",
186 .genpd.power_on_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
187 .genpd.power_off_latency_ns = PM_DOMAIN_ON_OFF_LATENCY_NS,
188 .base = SYSC_BASE,
189 .bit_shift = 13,
190 },
191};
192
193void __init sh7372_init_pm_domains(void)
194{
195 rmobile_init_domains(sh7372_pm_domains, ARRAY_SIZE(sh7372_pm_domains));
196 pm_genpd_add_subdomain_names("A4LC", "A3RV");
197 pm_genpd_add_subdomain_names("A4R", "A4LC");
198 pm_genpd_add_subdomain_names("A4S", "A3SG");
199 pm_genpd_add_subdomain_names("A4S", "A3SP");
200}
201
202#endif /* CONFIG_PM */
203
204#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
205static void sh7372_set_reset_vector(unsigned long address)
206{
207 /* set reset vector, translate 4k */
208 __raw_writel(address, SBAR);
209 __raw_writel(0, APARMBAREA);
210}
211
212static void sh7372_enter_sysc(int pllc0_on, unsigned long sleep_mode)
213{
214 if (pllc0_on)
215 __raw_writel(0, PLLC01STPCR);
216 else
217 __raw_writel(1 << 28, PLLC01STPCR);
218
219 __raw_readl(WUPSFAC); /* read wakeup int. factor before sleep */
220 cpu_suspend(sleep_mode, sh7372_do_idle_sysc);
221 __raw_readl(WUPSFAC); /* read wakeup int. factor after wakeup */
222
223 /* disable reset vector translation */
224 __raw_writel(0, SBAR);
225}
226
227static int sh7372_sysc_valid(unsigned long *mskp, unsigned long *msk2p)
228{
229 unsigned long mstpsr0, mstpsr1, mstpsr2, mstpsr3, mstpsr4;
230 unsigned long msk, msk2;
231
232 /* check active clocks to determine potential wakeup sources */
233
234 mstpsr0 = __raw_readl(MSTPSR0);
235 if ((mstpsr0 & 0x00000003) != 0x00000003) {
236 pr_debug("sh7372 mstpsr0 0x%08lx\n", mstpsr0);
237 return 0;
238 }
239
240 mstpsr1 = __raw_readl(MSTPSR1);
241 if ((mstpsr1 & 0xff079b7f) != 0xff079b7f) {
242 pr_debug("sh7372 mstpsr1 0x%08lx\n", mstpsr1);
243 return 0;
244 }
245
246 mstpsr2 = __raw_readl(MSTPSR2);
247 if ((mstpsr2 & 0x000741ff) != 0x000741ff) {
248 pr_debug("sh7372 mstpsr2 0x%08lx\n", mstpsr2);
249 return 0;
250 }
251
252 mstpsr3 = __raw_readl(MSTPSR3);
253 if ((mstpsr3 & 0x1a60f010) != 0x1a60f010) {
254 pr_debug("sh7372 mstpsr3 0x%08lx\n", mstpsr3);
255 return 0;
256 }
257
258 mstpsr4 = __raw_readl(MSTPSR4);
259 if ((mstpsr4 & 0x00008cf0) != 0x00008cf0) {
260 pr_debug("sh7372 mstpsr4 0x%08lx\n", mstpsr4);
261 return 0;
262 }
263
264 msk = 0;
265 msk2 = 0;
266
267 /* make bitmaps of limited number of wakeup sources */
268
269 if ((mstpsr2 & (1 << 23)) == 0) /* SPU2 */
270 msk |= 1 << 31;
271
272 if ((mstpsr2 & (1 << 12)) == 0) /* MFI_MFIM */
273 msk |= 1 << 21;
274
275 if ((mstpsr4 & (1 << 3)) == 0) /* KEYSC */
276 msk |= 1 << 2;
277
278 if ((mstpsr1 & (1 << 24)) == 0) /* CMT0 */
279 msk |= 1 << 1;
280
281 if ((mstpsr3 & (1 << 29)) == 0) /* CMT1 */
282 msk |= 1 << 1;
283
284 if ((mstpsr4 & (1 << 0)) == 0) /* CMT2 */
285 msk |= 1 << 1;
286
287 if ((mstpsr2 & (1 << 13)) == 0) /* MFI_MFIS */
288 msk2 |= 1 << 17;
289
290 *mskp = msk;
291 *msk2p = msk2;
292
293 return 1;
294}
295
296static void sh7372_icr_to_irqcr(unsigned long icr, u16 *irqcr1p, u16 *irqcr2p)
297{
298 u16 tmp, irqcr1, irqcr2;
299 int k;
300
301 irqcr1 = 0;
302 irqcr2 = 0;
303
304 /* convert INTCA ICR register layout to SYSC IRQCR+IRQCR2 */
305 for (k = 0; k <= 7; k++) {
306 tmp = (icr >> ((7 - k) * 4)) & 0xf;
307 irqcr1 |= (tmp & 0x03) << (k * 2);
308 irqcr2 |= (tmp >> 2) << (k * 2);
309 }
310
311 *irqcr1p = irqcr1;
312 *irqcr2p = irqcr2;
313}
314
315static void sh7372_setup_sysc(unsigned long msk, unsigned long msk2)
316{
317 u16 irqcrx_low, irqcrx_high, irqcry_low, irqcry_high;
318 unsigned long tmp;
319
320 /* read IRQ0A -> IRQ15A mask */
321 tmp = bitrev8(__raw_readb(INTMSK00A));
322 tmp |= bitrev8(__raw_readb(INTMSK10A)) << 8;
323
324 /* setup WUPSMSK from clocks and external IRQ mask */
325 msk = (~msk & 0xc030000f) | (tmp << 4);
326 __raw_writel(msk, WUPSMSK);
327
328 /* propage level/edge trigger for external IRQ 0->15 */
329 sh7372_icr_to_irqcr(__raw_readl(ICR1A), &irqcrx_low, &irqcry_low);
330 sh7372_icr_to_irqcr(__raw_readl(ICR2A), &irqcrx_high, &irqcry_high);
331 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR);
332 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR2);
333
334 /* read IRQ16A -> IRQ31A mask */
335 tmp = bitrev8(__raw_readb(INTMSK20A));
336 tmp |= bitrev8(__raw_readb(INTMSK30A)) << 8;
337
338 /* setup WUPSMSK2 from clocks and external IRQ mask */
339 msk2 = (~msk2 & 0x00030000) | tmp;
340 __raw_writel(msk2, WUPSMSK2);
341
342 /* propage level/edge trigger for external IRQ 16->31 */
343 sh7372_icr_to_irqcr(__raw_readl(ICR3A), &irqcrx_low, &irqcry_low);
344 sh7372_icr_to_irqcr(__raw_readl(ICR4A), &irqcrx_high, &irqcry_high);
345 __raw_writel((irqcrx_high << 16) | irqcrx_low, IRQCR3);
346 __raw_writel((irqcry_high << 16) | irqcry_low, IRQCR4);
347}
348
349static void sh7372_enter_a3sm_common(int pllc0_on)
350{
351 /* use INTCA together with SYSC for wakeup */
352 sh7372_setup_sysc(1 << 0, 0);
353 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
354 sh7372_enter_sysc(pllc0_on, 1 << 12);
355}
356
357static void sh7372_enter_a4s_common(int pllc0_on)
358{
359 sh7372_intca_suspend();
360 sh7372_set_reset_vector(SMFRAM);
361 sh7372_enter_sysc(pllc0_on, 1 << 10);
362 sh7372_intca_resume();
363}
364
365static void sh7372_pm_setup_smfram(void)
366{
367 /* pass physical address of cpu_resume() to assembly resume code */
368 sh7372_cpu_resume = virt_to_phys(cpu_resume);
369
370 memcpy((void *)SMFRAM, sh7372_resume_core_standby_sysc, 0x100);
371}
372#else
373static inline void sh7372_pm_setup_smfram(void) {}
374#endif /* CONFIG_SUSPEND || CONFIG_CPU_IDLE */
375
376#ifdef CONFIG_CPU_IDLE
377static int sh7372_do_idle_core_standby(unsigned long unused)
378{
379 cpu_do_idle(); /* WFI when SYSTBCR == 0x10 -> Core Standby */
380 return 0;
381}
382
383static int sh7372_enter_core_standby(struct cpuidle_device *dev,
384 struct cpuidle_driver *drv, int index)
385{
386 sh7372_set_reset_vector(__pa(sh7372_resume_core_standby_sysc));
387
388 /* enter sleep mode with SYSTBCR to 0x10 */
389 __raw_writel(0x10, SYSTBCR);
390 cpu_suspend(0, sh7372_do_idle_core_standby);
391 __raw_writel(0, SYSTBCR);
392
393 /* disable reset vector translation */
394 __raw_writel(0, SBAR);
395
396 return 1;
397}
398
399static int sh7372_enter_a3sm_pll_on(struct cpuidle_device *dev,
400 struct cpuidle_driver *drv, int index)
401{
402 sh7372_enter_a3sm_common(1);
403 return 2;
404}
405
406static int sh7372_enter_a3sm_pll_off(struct cpuidle_device *dev,
407 struct cpuidle_driver *drv, int index)
408{
409 sh7372_enter_a3sm_common(0);
410 return 3;
411}
412
413static int sh7372_enter_a4s(struct cpuidle_device *dev,
414 struct cpuidle_driver *drv, int index)
415{
416 unsigned long msk, msk2;
417
418 if (!sh7372_sysc_valid(&msk, &msk2))
419 return sh7372_enter_a3sm_pll_off(dev, drv, index);
420
421 sh7372_setup_sysc(msk, msk2);
422 sh7372_enter_a4s_common(0);
423 return 4;
424}
425
426static struct cpuidle_driver sh7372_cpuidle_driver = {
427 .name = "sh7372_cpuidle",
428 .owner = THIS_MODULE,
429 .state_count = 5,
430 .safe_state_index = 0, /* C1 */
431 .states[0] = ARM_CPUIDLE_WFI_STATE,
432 .states[1] = {
433 .name = "C2",
434 .desc = "Core Standby Mode",
435 .exit_latency = 10,
436 .target_residency = 20 + 10,
437 .enter = sh7372_enter_core_standby,
438 },
439 .states[2] = {
440 .name = "C3",
441 .desc = "A3SM PLL ON",
442 .exit_latency = 20,
443 .target_residency = 30 + 20,
444 .enter = sh7372_enter_a3sm_pll_on,
445 },
446 .states[3] = {
447 .name = "C4",
448 .desc = "A3SM PLL OFF",
449 .exit_latency = 120,
450 .target_residency = 30 + 120,
451 .enter = sh7372_enter_a3sm_pll_off,
452 },
453 .states[4] = {
454 .name = "C5",
455 .desc = "A4S PLL OFF",
456 .exit_latency = 240,
457 .target_residency = 30 + 240,
458 .enter = sh7372_enter_a4s,
459 .disabled = true,
460 },
461};
462
463static void __init sh7372_cpuidle_init(void)
464{
465 shmobile_cpuidle_set_driver(&sh7372_cpuidle_driver);
466}
467#else
468static void __init sh7372_cpuidle_init(void) {}
469#endif
470
471#ifdef CONFIG_SUSPEND
472static int sh7372_enter_suspend(suspend_state_t suspend_state)
473{
474 unsigned long msk, msk2;
475
476 /* check active clocks to determine potential wakeup sources */
477 if (sh7372_sysc_valid(&msk, &msk2) && a4s_suspend_ready) {
478 /* convert INTC mask/sense to SYSC mask/sense */
479 sh7372_setup_sysc(msk, msk2);
480
481 /* enter A4S sleep with PLLC0 off */
482 pr_debug("entering A4S\n");
483 sh7372_enter_a4s_common(0);
484 return 0;
485 }
486
487 /* default to enter A3SM sleep with PLLC0 off */
488 pr_debug("entering A3SM\n");
489 sh7372_enter_a3sm_common(0);
490 return 0;
491}
492
493/**
494 * sh7372_pm_notifier_fn - SH7372 PM notifier routine.
495 * @notifier: Unused.
496 * @pm_event: Event being handled.
497 * @unused: Unused.
498 */
499static int sh7372_pm_notifier_fn(struct notifier_block *notifier,
500 unsigned long pm_event, void *unused)
501{
502 switch (pm_event) {
503 case PM_SUSPEND_PREPARE:
504 /*
505 * This is necessary, because the A4R domain has to be "on"
506 * when suspend_device_irqs() and resume_device_irqs() are
507 * executed during system suspend and resume, respectively, so
508 * that those functions don't crash while accessing the INTCS.
509 */
510 pm_genpd_name_poweron("A4R");
511 break;
512 case PM_POST_SUSPEND:
513 pm_genpd_poweroff_unused();
514 break;
515 }
516
517 return NOTIFY_DONE;
518}
519
520static void sh7372_suspend_init(void)
521{
522 shmobile_suspend_ops.enter = sh7372_enter_suspend;
523 pm_notifier(sh7372_pm_notifier_fn, 0);
524}
525#else
526static void sh7372_suspend_init(void) {}
527#endif
528
529void __init sh7372_pm_init(void)
530{
531 /* enable DBG hardware block to kick SYSC */
532 __raw_writel(0x0000a500, DBGREG9);
533 __raw_writel(0x0000a501, DBGREG9);
534 __raw_writel(0x00000000, DBGREG1);
535
536 /* do not convert A3SM, A3SP, A3SG, A4R power down into A4S */
537 __raw_writel(0, PDNSEL);
538
539 sh7372_pm_setup_smfram();
540
541 sh7372_suspend_init();
542 sh7372_cpuidle_init();
543}
544
545void __init sh7372_pm_init_late(void)
546{
547 shmobile_init_late();
548 pm_genpd_name_attach_cpuidle("A4S", 4);
549}
diff --git a/arch/arm/mach-shmobile/setup-r8a7778.c b/arch/arm/mach-shmobile/setup-r8a7778.c
index cef8895a9b82..c49aa094fe17 100644
--- a/arch/arm/mach-shmobile/setup-r8a7778.c
+++ b/arch/arm/mach-shmobile/setup-r8a7778.c
@@ -15,6 +15,7 @@
15 * GNU General Public License for more details. 15 * GNU General Public License for more details.
16 */ 16 */
17 17
18#include <linux/clk/shmobile.h>
18#include <linux/kernel.h> 19#include <linux/kernel.h>
19#include <linux/io.h> 20#include <linux/io.h>
20#include <linux/irqchip/arm-gic.h> 21#include <linux/irqchip/arm-gic.h>
@@ -41,6 +42,21 @@
41#include "irqs.h" 42#include "irqs.h"
42#include "r8a7778.h" 43#include "r8a7778.h"
43 44
45#define MODEMR 0xffcc0020
46
47#ifdef CONFIG_COMMON_CLK
48static void __init r8a7778_timer_init(void)
49{
50 u32 mode;
51 void __iomem *modemr = ioremap_nocache(MODEMR, 4);
52
53 BUG_ON(!modemr);
54 mode = ioread32(modemr);
55 iounmap(modemr);
56 r8a7778_clocks_init(mode);
57}
58#endif
59
44/* SCIF */ 60/* SCIF */
45#define R8A7778_SCIF(index, baseaddr, irq) \ 61#define R8A7778_SCIF(index, baseaddr, irq) \
46static struct plat_sci_port scif##index##_platform_data = { \ 62static struct plat_sci_port scif##index##_platform_data = { \
@@ -608,6 +624,9 @@ DT_MACHINE_START(R8A7778_DT, "Generic R8A7778 (Flattened Device Tree)")
608 .init_early = shmobile_init_delay, 624 .init_early = shmobile_init_delay,
609 .init_irq = r8a7778_init_irq_dt, 625 .init_irq = r8a7778_init_irq_dt,
610 .init_late = shmobile_init_late, 626 .init_late = shmobile_init_late,
627#ifdef CONFIG_COMMON_CLK
628 .init_time = r8a7778_timer_init,
629#endif
611 .dt_compat = r8a7778_compat_dt, 630 .dt_compat = r8a7778_compat_dt,
612MACHINE_END 631MACHINE_END
613 632
diff --git a/arch/arm/mach-shmobile/setup-sh7372.c b/arch/arm/mach-shmobile/setup-sh7372.c
deleted file mode 100644
index 458a2cfad417..000000000000
--- a/arch/arm/mach-shmobile/setup-sh7372.c
+++ /dev/null
@@ -1,1016 +0,0 @@
1/*
2 * sh7372 processor support
3 *
4 * Copyright (C) 2010 Magnus Damm
5 * Copyright (C) 2008 Yoshihiro Shimoda
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; version 2 of the License.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16#include <linux/kernel.h>
17#include <linux/init.h>
18#include <linux/interrupt.h>
19#include <linux/irq.h>
20#include <linux/platform_device.h>
21#include <linux/of_platform.h>
22#include <linux/uio_driver.h>
23#include <linux/delay.h>
24#include <linux/input.h>
25#include <linux/io.h>
26#include <linux/serial_sci.h>
27#include <linux/sh_dma.h>
28#include <linux/sh_timer.h>
29#include <linux/pm_domain.h>
30#include <linux/dma-mapping.h>
31#include <linux/platform_data/sh_ipmmu.h>
32
33#include <asm/mach/map.h>
34#include <asm/mach-types.h>
35#include <asm/mach/arch.h>
36#include <asm/mach/time.h>
37
38#include "common.h"
39#include "dma-register.h"
40#include "intc.h"
41#include "irqs.h"
42#include "pm-rmobile.h"
43#include "sh7372.h"
44
45static struct map_desc sh7372_io_desc[] __initdata = {
46 /* create a 1:1 identity mapping for 0xe6xxxxxx
47 * used by CPGA, INTC and PFC.
48 */
49 {
50 .virtual = 0xe6000000,
51 .pfn = __phys_to_pfn(0xe6000000),
52 .length = 256 << 20,
53 .type = MT_DEVICE_NONSHARED
54 },
55};
56
57void __init sh7372_map_io(void)
58{
59 debug_ll_io_init();
60 iotable_init(sh7372_io_desc, ARRAY_SIZE(sh7372_io_desc));
61}
62
63/* PFC */
64static struct resource sh7372_pfc_resources[] = {
65 [0] = {
66 .start = 0xe6050000,
67 .end = 0xe6057fff,
68 .flags = IORESOURCE_MEM,
69 },
70 [1] = {
71 .start = 0xe605800c,
72 .end = 0xe6058027,
73 .flags = IORESOURCE_MEM,
74 }
75};
76
77static struct platform_device sh7372_pfc_device = {
78 .name = "pfc-sh7372",
79 .id = -1,
80 .resource = sh7372_pfc_resources,
81 .num_resources = ARRAY_SIZE(sh7372_pfc_resources),
82};
83
84void __init sh7372_pinmux_init(void)
85{
86 platform_device_register(&sh7372_pfc_device);
87}
88
89/* SCIF */
90#define SH7372_SCIF(scif_type, index, baseaddr, irq) \
91static struct plat_sci_port scif##index##_platform_data = { \
92 .type = scif_type, \
93 .flags = UPF_BOOT_AUTOCONF, \
94 .scscr = SCSCR_RE | SCSCR_TE, \
95}; \
96 \
97static struct resource scif##index##_resources[] = { \
98 DEFINE_RES_MEM(baseaddr, 0x100), \
99 DEFINE_RES_IRQ(irq), \
100}; \
101 \
102static struct platform_device scif##index##_device = { \
103 .name = "sh-sci", \
104 .id = index, \
105 .resource = scif##index##_resources, \
106 .num_resources = ARRAY_SIZE(scif##index##_resources), \
107 .dev = { \
108 .platform_data = &scif##index##_platform_data, \
109 }, \
110}
111
112SH7372_SCIF(PORT_SCIFA, 0, 0xe6c40000, evt2irq(0x0c00));
113SH7372_SCIF(PORT_SCIFA, 1, 0xe6c50000, evt2irq(0x0c20));
114SH7372_SCIF(PORT_SCIFA, 2, 0xe6c60000, evt2irq(0x0c40));
115SH7372_SCIF(PORT_SCIFA, 3, 0xe6c70000, evt2irq(0x0c60));
116SH7372_SCIF(PORT_SCIFA, 4, 0xe6c80000, evt2irq(0x0d20));
117SH7372_SCIF(PORT_SCIFA, 5, 0xe6cb0000, evt2irq(0x0d40));
118SH7372_SCIF(PORT_SCIFB, 6, 0xe6c30000, evt2irq(0x0d60));
119
120/* CMT */
121static struct sh_timer_config cmt2_platform_data = {
122 .channels_mask = 0x20,
123};
124
125static struct resource cmt2_resources[] = {
126 DEFINE_RES_MEM(0xe6130000, 0x50),
127 DEFINE_RES_IRQ(evt2irq(0x0b80)),
128};
129
130static struct platform_device cmt2_device = {
131 .name = "sh-cmt-32-fast",
132 .id = 2,
133 .dev = {
134 .platform_data = &cmt2_platform_data,
135 },
136 .resource = cmt2_resources,
137 .num_resources = ARRAY_SIZE(cmt2_resources),
138};
139
140/* TMU */
141static struct sh_timer_config tmu0_platform_data = {
142 .channels_mask = 7,
143};
144
145static struct resource tmu0_resources[] = {
146 DEFINE_RES_MEM(0xfff60000, 0x2c),
147 DEFINE_RES_IRQ(intcs_evt2irq(0xe80)),
148 DEFINE_RES_IRQ(intcs_evt2irq(0xea0)),
149 DEFINE_RES_IRQ(intcs_evt2irq(0xec0)),
150};
151
152static struct platform_device tmu0_device = {
153 .name = "sh-tmu",
154 .id = 0,
155 .dev = {
156 .platform_data = &tmu0_platform_data,
157 },
158 .resource = tmu0_resources,
159 .num_resources = ARRAY_SIZE(tmu0_resources),
160};
161
162/* I2C */
163static struct resource iic0_resources[] = {
164 [0] = {
165 .name = "IIC0",
166 .start = 0xFFF20000,
167 .end = 0xFFF20425 - 1,
168 .flags = IORESOURCE_MEM,
169 },
170 [1] = {
171 .start = intcs_evt2irq(0xe00), /* IIC0_ALI0 */
172 .end = intcs_evt2irq(0xe60), /* IIC0_DTEI0 */
173 .flags = IORESOURCE_IRQ,
174 },
175};
176
177static struct platform_device iic0_device = {
178 .name = "i2c-sh_mobile",
179 .id = 0, /* "i2c0" clock */
180 .num_resources = ARRAY_SIZE(iic0_resources),
181 .resource = iic0_resources,
182};
183
184static struct resource iic1_resources[] = {
185 [0] = {
186 .name = "IIC1",
187 .start = 0xE6C20000,
188 .end = 0xE6C20425 - 1,
189 .flags = IORESOURCE_MEM,
190 },
191 [1] = {
192 .start = evt2irq(0x780), /* IIC1_ALI1 */
193 .end = evt2irq(0x7e0), /* IIC1_DTEI1 */
194 .flags = IORESOURCE_IRQ,
195 },
196};
197
198static struct platform_device iic1_device = {
199 .name = "i2c-sh_mobile",
200 .id = 1, /* "i2c1" clock */
201 .num_resources = ARRAY_SIZE(iic1_resources),
202 .resource = iic1_resources,
203};
204
205/* DMA */
206static const struct sh_dmae_slave_config sh7372_dmae_slaves[] = {
207 {
208 .slave_id = SHDMA_SLAVE_SCIF0_TX,
209 .addr = 0xe6c40020,
210 .chcr = CHCR_TX(XMIT_SZ_8BIT),
211 .mid_rid = 0x21,
212 }, {
213 .slave_id = SHDMA_SLAVE_SCIF0_RX,
214 .addr = 0xe6c40024,
215 .chcr = CHCR_RX(XMIT_SZ_8BIT),
216 .mid_rid = 0x22,
217 }, {
218 .slave_id = SHDMA_SLAVE_SCIF1_TX,
219 .addr = 0xe6c50020,
220 .chcr = CHCR_TX(XMIT_SZ_8BIT),
221 .mid_rid = 0x25,
222 }, {
223 .slave_id = SHDMA_SLAVE_SCIF1_RX,
224 .addr = 0xe6c50024,
225 .chcr = CHCR_RX(XMIT_SZ_8BIT),
226 .mid_rid = 0x26,
227 }, {
228 .slave_id = SHDMA_SLAVE_SCIF2_TX,
229 .addr = 0xe6c60020,
230 .chcr = CHCR_TX(XMIT_SZ_8BIT),
231 .mid_rid = 0x29,
232 }, {
233 .slave_id = SHDMA_SLAVE_SCIF2_RX,
234 .addr = 0xe6c60024,
235 .chcr = CHCR_RX(XMIT_SZ_8BIT),
236 .mid_rid = 0x2a,
237 }, {
238 .slave_id = SHDMA_SLAVE_SCIF3_TX,
239 .addr = 0xe6c70020,
240 .chcr = CHCR_TX(XMIT_SZ_8BIT),
241 .mid_rid = 0x2d,
242 }, {
243 .slave_id = SHDMA_SLAVE_SCIF3_RX,
244 .addr = 0xe6c70024,
245 .chcr = CHCR_RX(XMIT_SZ_8BIT),
246 .mid_rid = 0x2e,
247 }, {
248 .slave_id = SHDMA_SLAVE_SCIF4_TX,
249 .addr = 0xe6c80020,
250 .chcr = CHCR_TX(XMIT_SZ_8BIT),
251 .mid_rid = 0x39,
252 }, {
253 .slave_id = SHDMA_SLAVE_SCIF4_RX,
254 .addr = 0xe6c80024,
255 .chcr = CHCR_RX(XMIT_SZ_8BIT),
256 .mid_rid = 0x3a,
257 }, {
258 .slave_id = SHDMA_SLAVE_SCIF5_TX,
259 .addr = 0xe6cb0020,
260 .chcr = CHCR_TX(XMIT_SZ_8BIT),
261 .mid_rid = 0x35,
262 }, {
263 .slave_id = SHDMA_SLAVE_SCIF5_RX,
264 .addr = 0xe6cb0024,
265 .chcr = CHCR_RX(XMIT_SZ_8BIT),
266 .mid_rid = 0x36,
267 }, {
268 .slave_id = SHDMA_SLAVE_SCIF6_TX,
269 .addr = 0xe6c30040,
270 .chcr = CHCR_TX(XMIT_SZ_8BIT),
271 .mid_rid = 0x3d,
272 }, {
273 .slave_id = SHDMA_SLAVE_SCIF6_RX,
274 .addr = 0xe6c30060,
275 .chcr = CHCR_RX(XMIT_SZ_8BIT),
276 .mid_rid = 0x3e,
277 }, {
278 .slave_id = SHDMA_SLAVE_FLCTL0_TX,
279 .addr = 0xe6a30050,
280 .chcr = CHCR_TX(XMIT_SZ_32BIT),
281 .mid_rid = 0x83,
282 }, {
283 .slave_id = SHDMA_SLAVE_FLCTL0_RX,
284 .addr = 0xe6a30050,
285 .chcr = CHCR_RX(XMIT_SZ_32BIT),
286 .mid_rid = 0x83,
287 }, {
288 .slave_id = SHDMA_SLAVE_FLCTL1_TX,
289 .addr = 0xe6a30060,
290 .chcr = CHCR_TX(XMIT_SZ_32BIT),
291 .mid_rid = 0x87,
292 }, {
293 .slave_id = SHDMA_SLAVE_FLCTL1_RX,
294 .addr = 0xe6a30060,
295 .chcr = CHCR_RX(XMIT_SZ_32BIT),
296 .mid_rid = 0x87,
297 }, {
298 .slave_id = SHDMA_SLAVE_SDHI0_TX,
299 .addr = 0xe6850030,
300 .chcr = CHCR_TX(XMIT_SZ_16BIT),
301 .mid_rid = 0xc1,
302 }, {
303 .slave_id = SHDMA_SLAVE_SDHI0_RX,
304 .addr = 0xe6850030,
305 .chcr = CHCR_RX(XMIT_SZ_16BIT),
306 .mid_rid = 0xc2,
307 }, {
308 .slave_id = SHDMA_SLAVE_SDHI1_TX,
309 .addr = 0xe6860030,
310 .chcr = CHCR_TX(XMIT_SZ_16BIT),
311 .mid_rid = 0xc9,
312 }, {
313 .slave_id = SHDMA_SLAVE_SDHI1_RX,
314 .addr = 0xe6860030,
315 .chcr = CHCR_RX(XMIT_SZ_16BIT),
316 .mid_rid = 0xca,
317 }, {
318 .slave_id = SHDMA_SLAVE_SDHI2_TX,
319 .addr = 0xe6870030,
320 .chcr = CHCR_TX(XMIT_SZ_16BIT),
321 .mid_rid = 0xcd,
322 }, {
323 .slave_id = SHDMA_SLAVE_SDHI2_RX,
324 .addr = 0xe6870030,
325 .chcr = CHCR_RX(XMIT_SZ_16BIT),
326 .mid_rid = 0xce,
327 }, {
328 .slave_id = SHDMA_SLAVE_FSIA_TX,
329 .addr = 0xfe1f0024,
330 .chcr = CHCR_TX(XMIT_SZ_32BIT),
331 .mid_rid = 0xb1,
332 }, {
333 .slave_id = SHDMA_SLAVE_FSIA_RX,
334 .addr = 0xfe1f0020,
335 .chcr = CHCR_RX(XMIT_SZ_32BIT),
336 .mid_rid = 0xb2,
337 }, {
338 .slave_id = SHDMA_SLAVE_MMCIF_TX,
339 .addr = 0xe6bd0034,
340 .chcr = CHCR_TX(XMIT_SZ_32BIT),
341 .mid_rid = 0xd1,
342 }, {
343 .slave_id = SHDMA_SLAVE_MMCIF_RX,
344 .addr = 0xe6bd0034,
345 .chcr = CHCR_RX(XMIT_SZ_32BIT),
346 .mid_rid = 0xd2,
347 },
348};
349
350#define SH7372_CHCLR (0x220 - 0x20)
351
352static const struct sh_dmae_channel sh7372_dmae_channels[] = {
353 {
354 .offset = 0,
355 .dmars = 0,
356 .dmars_bit = 0,
357 .chclr_offset = SH7372_CHCLR + 0,
358 }, {
359 .offset = 0x10,
360 .dmars = 0,
361 .dmars_bit = 8,
362 .chclr_offset = SH7372_CHCLR + 0x10,
363 }, {
364 .offset = 0x20,
365 .dmars = 4,
366 .dmars_bit = 0,
367 .chclr_offset = SH7372_CHCLR + 0x20,
368 }, {
369 .offset = 0x30,
370 .dmars = 4,
371 .dmars_bit = 8,
372 .chclr_offset = SH7372_CHCLR + 0x30,
373 }, {
374 .offset = 0x50,
375 .dmars = 8,
376 .dmars_bit = 0,
377 .chclr_offset = SH7372_CHCLR + 0x50,
378 }, {
379 .offset = 0x60,
380 .dmars = 8,
381 .dmars_bit = 8,
382 .chclr_offset = SH7372_CHCLR + 0x60,
383 }
384};
385
386static struct sh_dmae_pdata dma_platform_data = {
387 .slave = sh7372_dmae_slaves,
388 .slave_num = ARRAY_SIZE(sh7372_dmae_slaves),
389 .channel = sh7372_dmae_channels,
390 .channel_num = ARRAY_SIZE(sh7372_dmae_channels),
391 .ts_low_shift = TS_LOW_SHIFT,
392 .ts_low_mask = TS_LOW_BIT << TS_LOW_SHIFT,
393 .ts_high_shift = TS_HI_SHIFT,
394 .ts_high_mask = TS_HI_BIT << TS_HI_SHIFT,
395 .ts_shift = dma_ts_shift,
396 .ts_shift_num = ARRAY_SIZE(dma_ts_shift),
397 .dmaor_init = DMAOR_DME,
398 .chclr_present = 1,
399};
400
401/* Resource order important! */
402static struct resource sh7372_dmae0_resources[] = {
403 {
404 /* Channel registers and DMAOR */
405 .start = 0xfe008020,
406 .end = 0xfe00828f,
407 .flags = IORESOURCE_MEM,
408 },
409 {
410 /* DMARSx */
411 .start = 0xfe009000,
412 .end = 0xfe00900b,
413 .flags = IORESOURCE_MEM,
414 },
415 {
416 .name = "error_irq",
417 .start = evt2irq(0x20c0),
418 .end = evt2irq(0x20c0),
419 .flags = IORESOURCE_IRQ,
420 },
421 {
422 /* IRQ for channels 0-5 */
423 .start = evt2irq(0x2000),
424 .end = evt2irq(0x20a0),
425 .flags = IORESOURCE_IRQ,
426 },
427};
428
429/* Resource order important! */
430static struct resource sh7372_dmae1_resources[] = {
431 {
432 /* Channel registers and DMAOR */
433 .start = 0xfe018020,
434 .end = 0xfe01828f,
435 .flags = IORESOURCE_MEM,
436 },
437 {
438 /* DMARSx */
439 .start = 0xfe019000,
440 .end = 0xfe01900b,
441 .flags = IORESOURCE_MEM,
442 },
443 {
444 .name = "error_irq",
445 .start = evt2irq(0x21c0),
446 .end = evt2irq(0x21c0),
447 .flags = IORESOURCE_IRQ,
448 },
449 {
450 /* IRQ for channels 0-5 */
451 .start = evt2irq(0x2100),
452 .end = evt2irq(0x21a0),
453 .flags = IORESOURCE_IRQ,
454 },
455};
456
457/* Resource order important! */
458static struct resource sh7372_dmae2_resources[] = {
459 {
460 /* Channel registers and DMAOR */
461 .start = 0xfe028020,
462 .end = 0xfe02828f,
463 .flags = IORESOURCE_MEM,
464 },
465 {
466 /* DMARSx */
467 .start = 0xfe029000,
468 .end = 0xfe02900b,
469 .flags = IORESOURCE_MEM,
470 },
471 {
472 .name = "error_irq",
473 .start = evt2irq(0x22c0),
474 .end = evt2irq(0x22c0),
475 .flags = IORESOURCE_IRQ,
476 },
477 {
478 /* IRQ for channels 0-5 */
479 .start = evt2irq(0x2200),
480 .end = evt2irq(0x22a0),
481 .flags = IORESOURCE_IRQ,
482 },
483};
484
485static struct platform_device dma0_device = {
486 .name = "sh-dma-engine",
487 .id = 0,
488 .resource = sh7372_dmae0_resources,
489 .num_resources = ARRAY_SIZE(sh7372_dmae0_resources),
490 .dev = {
491 .platform_data = &dma_platform_data,
492 },
493};
494
495static struct platform_device dma1_device = {
496 .name = "sh-dma-engine",
497 .id = 1,
498 .resource = sh7372_dmae1_resources,
499 .num_resources = ARRAY_SIZE(sh7372_dmae1_resources),
500 .dev = {
501 .platform_data = &dma_platform_data,
502 },
503};
504
505static struct platform_device dma2_device = {
506 .name = "sh-dma-engine",
507 .id = 2,
508 .resource = sh7372_dmae2_resources,
509 .num_resources = ARRAY_SIZE(sh7372_dmae2_resources),
510 .dev = {
511 .platform_data = &dma_platform_data,
512 },
513};
514
515/*
516 * USB-DMAC
517 */
518static const struct sh_dmae_channel sh7372_usb_dmae_channels[] = {
519 {
520 .offset = 0,
521 }, {
522 .offset = 0x20,
523 },
524};
525
526/* USB DMAC0 */
527static const struct sh_dmae_slave_config sh7372_usb_dmae0_slaves[] = {
528 {
529 .slave_id = SHDMA_SLAVE_USB0_TX,
530 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
531 }, {
532 .slave_id = SHDMA_SLAVE_USB0_RX,
533 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
534 },
535};
536
537static struct sh_dmae_pdata usb_dma0_platform_data = {
538 .slave = sh7372_usb_dmae0_slaves,
539 .slave_num = ARRAY_SIZE(sh7372_usb_dmae0_slaves),
540 .channel = sh7372_usb_dmae_channels,
541 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
542 .ts_low_shift = USBTS_LOW_SHIFT,
543 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
544 .ts_high_shift = USBTS_HI_SHIFT,
545 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
546 .ts_shift = dma_usbts_shift,
547 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
548 .dmaor_init = DMAOR_DME,
549 .chcr_offset = 0x14,
550 .chcr_ie_bit = 1 << 5,
551 .dmaor_is_32bit = 1,
552 .needs_tend_set = 1,
553 .no_dmars = 1,
554 .slave_only = 1,
555};
556
557static struct resource sh7372_usb_dmae0_resources[] = {
558 {
559 /* Channel registers and DMAOR */
560 .start = 0xe68a0020,
561 .end = 0xe68a0064 - 1,
562 .flags = IORESOURCE_MEM,
563 },
564 {
565 /* VCR/SWR/DMICR */
566 .start = 0xe68a0000,
567 .end = 0xe68a0014 - 1,
568 .flags = IORESOURCE_MEM,
569 },
570 {
571 /* IRQ for channels */
572 .start = evt2irq(0x0a00),
573 .end = evt2irq(0x0a00),
574 .flags = IORESOURCE_IRQ,
575 },
576};
577
578static struct platform_device usb_dma0_device = {
579 .name = "sh-dma-engine",
580 .id = 3,
581 .resource = sh7372_usb_dmae0_resources,
582 .num_resources = ARRAY_SIZE(sh7372_usb_dmae0_resources),
583 .dev = {
584 .platform_data = &usb_dma0_platform_data,
585 },
586};
587
588/* USB DMAC1 */
589static const struct sh_dmae_slave_config sh7372_usb_dmae1_slaves[] = {
590 {
591 .slave_id = SHDMA_SLAVE_USB1_TX,
592 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
593 }, {
594 .slave_id = SHDMA_SLAVE_USB1_RX,
595 .chcr = USBTS_INDEX2VAL(USBTS_XMIT_SZ_8BYTE),
596 },
597};
598
599static struct sh_dmae_pdata usb_dma1_platform_data = {
600 .slave = sh7372_usb_dmae1_slaves,
601 .slave_num = ARRAY_SIZE(sh7372_usb_dmae1_slaves),
602 .channel = sh7372_usb_dmae_channels,
603 .channel_num = ARRAY_SIZE(sh7372_usb_dmae_channels),
604 .ts_low_shift = USBTS_LOW_SHIFT,
605 .ts_low_mask = USBTS_LOW_BIT << USBTS_LOW_SHIFT,
606 .ts_high_shift = USBTS_HI_SHIFT,
607 .ts_high_mask = USBTS_HI_BIT << USBTS_HI_SHIFT,
608 .ts_shift = dma_usbts_shift,
609 .ts_shift_num = ARRAY_SIZE(dma_usbts_shift),
610 .dmaor_init = DMAOR_DME,
611 .chcr_offset = 0x14,
612 .chcr_ie_bit = 1 << 5,
613 .dmaor_is_32bit = 1,
614 .needs_tend_set = 1,
615 .no_dmars = 1,
616 .slave_only = 1,
617};
618
619static struct resource sh7372_usb_dmae1_resources[] = {
620 {
621 /* Channel registers and DMAOR */
622 .start = 0xe68c0020,
623 .end = 0xe68c0064 - 1,
624 .flags = IORESOURCE_MEM,
625 },
626 {
627 /* VCR/SWR/DMICR */
628 .start = 0xe68c0000,
629 .end = 0xe68c0014 - 1,
630 .flags = IORESOURCE_MEM,
631 },
632 {
633 /* IRQ for channels */
634 .start = evt2irq(0x1d00),
635 .end = evt2irq(0x1d00),
636 .flags = IORESOURCE_IRQ,
637 },
638};
639
640static struct platform_device usb_dma1_device = {
641 .name = "sh-dma-engine",
642 .id = 4,
643 .resource = sh7372_usb_dmae1_resources,
644 .num_resources = ARRAY_SIZE(sh7372_usb_dmae1_resources),
645 .dev = {
646 .platform_data = &usb_dma1_platform_data,
647 },
648};
649
650/* VPU */
651static struct uio_info vpu_platform_data = {
652 .name = "VPU5HG",
653 .version = "0",
654 .irq = intcs_evt2irq(0x980),
655};
656
657static struct resource vpu_resources[] = {
658 [0] = {
659 .name = "VPU",
660 .start = 0xfe900000,
661 .end = 0xfe900157,
662 .flags = IORESOURCE_MEM,
663 },
664};
665
666static struct platform_device vpu_device = {
667 .name = "uio_pdrv_genirq",
668 .id = 0,
669 .dev = {
670 .platform_data = &vpu_platform_data,
671 },
672 .resource = vpu_resources,
673 .num_resources = ARRAY_SIZE(vpu_resources),
674};
675
676/* VEU0 */
677static struct uio_info veu0_platform_data = {
678 .name = "VEU0",
679 .version = "0",
680 .irq = intcs_evt2irq(0x700),
681};
682
683static struct resource veu0_resources[] = {
684 [0] = {
685 .name = "VEU0",
686 .start = 0xfe920000,
687 .end = 0xfe9200cb,
688 .flags = IORESOURCE_MEM,
689 },
690};
691
692static struct platform_device veu0_device = {
693 .name = "uio_pdrv_genirq",
694 .id = 1,
695 .dev = {
696 .platform_data = &veu0_platform_data,
697 },
698 .resource = veu0_resources,
699 .num_resources = ARRAY_SIZE(veu0_resources),
700};
701
702/* VEU1 */
703static struct uio_info veu1_platform_data = {
704 .name = "VEU1",
705 .version = "0",
706 .irq = intcs_evt2irq(0x720),
707};
708
709static struct resource veu1_resources[] = {
710 [0] = {
711 .name = "VEU1",
712 .start = 0xfe924000,
713 .end = 0xfe9240cb,
714 .flags = IORESOURCE_MEM,
715 },
716};
717
718static struct platform_device veu1_device = {
719 .name = "uio_pdrv_genirq",
720 .id = 2,
721 .dev = {
722 .platform_data = &veu1_platform_data,
723 },
724 .resource = veu1_resources,
725 .num_resources = ARRAY_SIZE(veu1_resources),
726};
727
728/* VEU2 */
729static struct uio_info veu2_platform_data = {
730 .name = "VEU2",
731 .version = "0",
732 .irq = intcs_evt2irq(0x740),
733};
734
735static struct resource veu2_resources[] = {
736 [0] = {
737 .name = "VEU2",
738 .start = 0xfe928000,
739 .end = 0xfe928307,
740 .flags = IORESOURCE_MEM,
741 },
742};
743
744static struct platform_device veu2_device = {
745 .name = "uio_pdrv_genirq",
746 .id = 3,
747 .dev = {
748 .platform_data = &veu2_platform_data,
749 },
750 .resource = veu2_resources,
751 .num_resources = ARRAY_SIZE(veu2_resources),
752};
753
754/* VEU3 */
755static struct uio_info veu3_platform_data = {
756 .name = "VEU3",
757 .version = "0",
758 .irq = intcs_evt2irq(0x760),
759};
760
761static struct resource veu3_resources[] = {
762 [0] = {
763 .name = "VEU3",
764 .start = 0xfe92c000,
765 .end = 0xfe92c307,
766 .flags = IORESOURCE_MEM,
767 },
768};
769
770static struct platform_device veu3_device = {
771 .name = "uio_pdrv_genirq",
772 .id = 4,
773 .dev = {
774 .platform_data = &veu3_platform_data,
775 },
776 .resource = veu3_resources,
777 .num_resources = ARRAY_SIZE(veu3_resources),
778};
779
780/* JPU */
781static struct uio_info jpu_platform_data = {
782 .name = "JPU",
783 .version = "0",
784 .irq = intcs_evt2irq(0x560),
785};
786
787static struct resource jpu_resources[] = {
788 [0] = {
789 .name = "JPU",
790 .start = 0xfe980000,
791 .end = 0xfe9902d3,
792 .flags = IORESOURCE_MEM,
793 },
794};
795
796static struct platform_device jpu_device = {
797 .name = "uio_pdrv_genirq",
798 .id = 5,
799 .dev = {
800 .platform_data = &jpu_platform_data,
801 },
802 .resource = jpu_resources,
803 .num_resources = ARRAY_SIZE(jpu_resources),
804};
805
806/* SPU2DSP0 */
807static struct uio_info spu0_platform_data = {
808 .name = "SPU2DSP0",
809 .version = "0",
810 .irq = evt2irq(0x1800),
811};
812
813static struct resource spu0_resources[] = {
814 [0] = {
815 .name = "SPU2DSP0",
816 .start = 0xfe200000,
817 .end = 0xfe2fffff,
818 .flags = IORESOURCE_MEM,
819 },
820};
821
822static struct platform_device spu0_device = {
823 .name = "uio_pdrv_genirq",
824 .id = 6,
825 .dev = {
826 .platform_data = &spu0_platform_data,
827 },
828 .resource = spu0_resources,
829 .num_resources = ARRAY_SIZE(spu0_resources),
830};
831
832/* SPU2DSP1 */
833static struct uio_info spu1_platform_data = {
834 .name = "SPU2DSP1",
835 .version = "0",
836 .irq = evt2irq(0x1820),
837};
838
839static struct resource spu1_resources[] = {
840 [0] = {
841 .name = "SPU2DSP1",
842 .start = 0xfe300000,
843 .end = 0xfe3fffff,
844 .flags = IORESOURCE_MEM,
845 },
846};
847
848static struct platform_device spu1_device = {
849 .name = "uio_pdrv_genirq",
850 .id = 7,
851 .dev = {
852 .platform_data = &spu1_platform_data,
853 },
854 .resource = spu1_resources,
855 .num_resources = ARRAY_SIZE(spu1_resources),
856};
857
858/* IPMMUI (an IPMMU module for ICB/LMB) */
859static struct resource ipmmu_resources[] = {
860 [0] = {
861 .name = "IPMMUI",
862 .start = 0xfe951000,
863 .end = 0xfe9510ff,
864 .flags = IORESOURCE_MEM,
865 },
866};
867
868static const char * const ipmmu_dev_names[] = {
869 "sh_mobile_lcdc_fb.0",
870 "sh_mobile_lcdc_fb.1",
871 "sh_mobile_ceu.0",
872 "uio_pdrv_genirq.0",
873 "uio_pdrv_genirq.1",
874 "uio_pdrv_genirq.2",
875 "uio_pdrv_genirq.3",
876 "uio_pdrv_genirq.4",
877 "uio_pdrv_genirq.5",
878};
879
880static struct shmobile_ipmmu_platform_data ipmmu_platform_data = {
881 .dev_names = ipmmu_dev_names,
882 .num_dev_names = ARRAY_SIZE(ipmmu_dev_names),
883};
884
885static struct platform_device ipmmu_device = {
886 .name = "ipmmu",
887 .id = -1,
888 .dev = {
889 .platform_data = &ipmmu_platform_data,
890 },
891 .resource = ipmmu_resources,
892 .num_resources = ARRAY_SIZE(ipmmu_resources),
893};
894
895static struct platform_device *sh7372_early_devices[] __initdata = {
896 &scif0_device,
897 &scif1_device,
898 &scif2_device,
899 &scif3_device,
900 &scif4_device,
901 &scif5_device,
902 &scif6_device,
903 &cmt2_device,
904 &tmu0_device,
905 &ipmmu_device,
906};
907
908static struct platform_device *sh7372_late_devices[] __initdata = {
909 &iic0_device,
910 &iic1_device,
911 &dma0_device,
912 &dma1_device,
913 &dma2_device,
914 &usb_dma0_device,
915 &usb_dma1_device,
916 &vpu_device,
917 &veu0_device,
918 &veu1_device,
919 &veu2_device,
920 &veu3_device,
921 &jpu_device,
922 &spu0_device,
923 &spu1_device,
924};
925
926void __init sh7372_add_standard_devices(void)
927{
928 static struct pm_domain_device domain_devices[] __initdata = {
929 { "A3RV", &vpu_device, },
930 { "A4MP", &spu0_device, },
931 { "A4MP", &spu1_device, },
932 { "A3SP", &scif0_device, },
933 { "A3SP", &scif1_device, },
934 { "A3SP", &scif2_device, },
935 { "A3SP", &scif3_device, },
936 { "A3SP", &scif4_device, },
937 { "A3SP", &scif5_device, },
938 { "A3SP", &scif6_device, },
939 { "A3SP", &iic1_device, },
940 { "A3SP", &dma0_device, },
941 { "A3SP", &dma1_device, },
942 { "A3SP", &dma2_device, },
943 { "A3SP", &usb_dma0_device, },
944 { "A3SP", &usb_dma1_device, },
945 { "A4R", &iic0_device, },
946 { "A4R", &veu0_device, },
947 { "A4R", &veu1_device, },
948 { "A4R", &veu2_device, },
949 { "A4R", &veu3_device, },
950 { "A4R", &jpu_device, },
951 { "A4R", &tmu0_device, },
952 };
953
954 sh7372_init_pm_domains();
955
956 platform_add_devices(sh7372_early_devices,
957 ARRAY_SIZE(sh7372_early_devices));
958
959 platform_add_devices(sh7372_late_devices,
960 ARRAY_SIZE(sh7372_late_devices));
961
962 rmobile_add_devices_to_domains(domain_devices,
963 ARRAY_SIZE(domain_devices));
964}
965
966void __init sh7372_earlytimer_init(void)
967{
968 sh7372_clock_init();
969 shmobile_earlytimer_init();
970}
971
972void __init sh7372_add_early_devices(void)
973{
974 early_platform_add_devices(sh7372_early_devices,
975 ARRAY_SIZE(sh7372_early_devices));
976
977 /* setup early console here as well */
978 shmobile_setup_console();
979}
980
981#ifdef CONFIG_USE_OF
982
983void __init sh7372_add_early_devices_dt(void)
984{
985 shmobile_init_delay();
986
987 sh7372_add_early_devices();
988}
989
990void __init sh7372_add_standard_devices_dt(void)
991{
992 /* clocks are setup late during boot in the case of DT */
993 sh7372_clock_init();
994
995 platform_add_devices(sh7372_early_devices,
996 ARRAY_SIZE(sh7372_early_devices));
997
998 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
999}
1000
1001static const char *sh7372_boards_compat_dt[] __initdata = {
1002 "renesas,sh7372",
1003 NULL,
1004};
1005
1006DT_MACHINE_START(SH7372_DT, "Generic SH7372 (Flattened Device Tree)")
1007 .map_io = sh7372_map_io,
1008 .init_early = sh7372_add_early_devices_dt,
1009 .init_irq = sh7372_init_irq,
1010 .handle_irq = shmobile_handle_irq_intc,
1011 .init_machine = sh7372_add_standard_devices_dt,
1012 .init_late = shmobile_init_late,
1013 .dt_compat = sh7372_boards_compat_dt,
1014MACHINE_END
1015
1016#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/sh7372.h b/arch/arm/mach-shmobile/sh7372.h
deleted file mode 100644
index 4ad960d5075b..000000000000
--- a/arch/arm/mach-shmobile/sh7372.h
+++ /dev/null
@@ -1,84 +0,0 @@
1/*
2 * Copyright (C) 2010 Renesas Solutions Corp.
3 *
4 * Kuninori Morimoto <morimoto.kuninori@renesas.com>
5 *
6 * This file is subject to the terms and conditions of the GNU General Public
7 * License. See the file "COPYING" in the main directory of this archive
8 * for more details.
9 */
10
11#ifndef __ASM_SH7372_H__
12#define __ASM_SH7372_H__
13
14/* DMA slave IDs */
15enum {
16 SHDMA_SLAVE_INVALID,
17 SHDMA_SLAVE_SCIF0_TX,
18 SHDMA_SLAVE_SCIF0_RX,
19 SHDMA_SLAVE_SCIF1_TX,
20 SHDMA_SLAVE_SCIF1_RX,
21 SHDMA_SLAVE_SCIF2_TX,
22 SHDMA_SLAVE_SCIF2_RX,
23 SHDMA_SLAVE_SCIF3_TX,
24 SHDMA_SLAVE_SCIF3_RX,
25 SHDMA_SLAVE_SCIF4_TX,
26 SHDMA_SLAVE_SCIF4_RX,
27 SHDMA_SLAVE_SCIF5_TX,
28 SHDMA_SLAVE_SCIF5_RX,
29 SHDMA_SLAVE_SCIF6_TX,
30 SHDMA_SLAVE_SCIF6_RX,
31 SHDMA_SLAVE_FLCTL0_TX,
32 SHDMA_SLAVE_FLCTL0_RX,
33 SHDMA_SLAVE_FLCTL1_TX,
34 SHDMA_SLAVE_FLCTL1_RX,
35 SHDMA_SLAVE_SDHI0_RX,
36 SHDMA_SLAVE_SDHI0_TX,
37 SHDMA_SLAVE_SDHI1_RX,
38 SHDMA_SLAVE_SDHI1_TX,
39 SHDMA_SLAVE_SDHI2_RX,
40 SHDMA_SLAVE_SDHI2_TX,
41 SHDMA_SLAVE_FSIA_RX,
42 SHDMA_SLAVE_FSIA_TX,
43 SHDMA_SLAVE_MMCIF_RX,
44 SHDMA_SLAVE_MMCIF_TX,
45 SHDMA_SLAVE_USB0_TX,
46 SHDMA_SLAVE_USB0_RX,
47 SHDMA_SLAVE_USB1_TX,
48 SHDMA_SLAVE_USB1_RX,
49};
50
51extern struct clk sh7372_extal1_clk;
52extern struct clk sh7372_extal2_clk;
53extern struct clk sh7372_dv_clki_clk;
54extern struct clk sh7372_dv_clki_div2_clk;
55extern struct clk sh7372_pllc2_clk;
56
57extern void sh7372_init_irq(void);
58extern void sh7372_map_io(void);
59extern void sh7372_earlytimer_init(void);
60extern void sh7372_add_early_devices(void);
61extern void sh7372_add_standard_devices(void);
62extern void sh7372_add_early_devices_dt(void);
63extern void sh7372_add_standard_devices_dt(void);
64extern void sh7372_clock_init(void);
65extern void sh7372_pinmux_init(void);
66extern void sh7372_pm_init(void);
67extern void sh7372_resume_core_standby_sysc(void);
68extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
69extern void sh7372_intcs_suspend(void);
70extern void sh7372_intcs_resume(void);
71extern void sh7372_intca_suspend(void);
72extern void sh7372_intca_resume(void);
73
74extern unsigned long sh7372_cpu_resume;
75
76#ifdef CONFIG_PM
77extern void __init sh7372_init_pm_domains(void);
78#else
79static inline void sh7372_init_pm_domains(void) {}
80#endif
81
82extern void __init sh7372_pm_init_late(void);
83
84#endif /* __ASM_SH7372_H__ */
diff --git a/arch/arm/mach-shmobile/sleep-sh7372.S b/arch/arm/mach-shmobile/sleep-sh7372.S
deleted file mode 100644
index 146b8de16432..000000000000
--- a/arch/arm/mach-shmobile/sleep-sh7372.S
+++ /dev/null
@@ -1,98 +0,0 @@
1/*
2 * sh7372 lowlevel sleep code for "Core Standby Mode"
3 *
4 * Copyright (C) 2011 Magnus Damm
5 *
6 * In "Core Standby Mode" the ARM core is off, but L2 cache is still on
7 *
8 * Based on mach-omap2/sleep34xx.S
9 *
10 * (C) Copyright 2007 Texas Instruments
11 * Karthik Dasu <karthik-dp@ti.com>
12 *
13 * (C) Copyright 2004 Texas Instruments, <www.ti.com>
14 * Richard Woodruff <r-woodruff2@ti.com>
15 *
16 * This program is free software; you can redistribute it and/or
17 * modify it under the terms of the GNU General Public License as
18 * published by the Free Software Foundation; either version 2 of
19 * the License, or (at your option) any later version.
20 *
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
24 * GNU General Public License for more details.
25 */
26
27#include <linux/linkage.h>
28#include <linux/init.h>
29#include <asm/memory.h>
30#include <asm/assembler.h>
31
32#if defined(CONFIG_SUSPEND) || defined(CONFIG_CPU_IDLE)
33 .align 12
34 .text
35 .global sh7372_resume_core_standby_sysc
36sh7372_resume_core_standby_sysc:
37 ldr pc, 1f
38
39 .align 2
40 .globl sh7372_cpu_resume
41sh7372_cpu_resume:
421: .space 4
43
44#define SPDCR 0xe6180008
45
46 /* A3SM & A4S power down */
47 .global sh7372_do_idle_sysc
48sh7372_do_idle_sysc:
49 mov r8, r0 /* sleep mode passed in r0 */
50
51 /*
52 * Clear the SCTLR.C bit to prevent further data cache
53 * allocation. Clearing SCTLR.C would make all the data accesses
54 * strongly ordered and would not hit the cache.
55 */
56 mrc p15, 0, r0, c1, c0, 0
57 bic r0, r0, #(1 << 2) @ Disable the C bit
58 mcr p15, 0, r0, c1, c0, 0
59 isb
60
61 /*
62 * Clean and invalidate data cache again.
63 */
64 ldr r1, kernel_flush
65 blx r1
66
67 /* disable L2 cache in the aux control register */
68 mrc p15, 0, r10, c1, c0, 1
69 bic r10, r10, #2
70 mcr p15, 0, r10, c1, c0, 1
71 isb
72
73 /*
74 * The kernel doesn't interwork: v7_flush_dcache_all in particluar will
75 * always return in Thumb state when CONFIG_THUMB2_KERNEL is enabled.
76 * This sequence switches back to ARM. Note that .align may insert a
77 * nop: bx pc needs to be word-aligned in order to work.
78 */
79 THUMB( .thumb )
80 THUMB( .align )
81 THUMB( bx pc )
82 THUMB( nop )
83 .arm
84
85 /* Data memory barrier and Data sync barrier */
86 dsb
87 dmb
88
89 /* SYSC power down */
90 ldr r0, =SPDCR
91 str r8, [r0]
921:
93 b 1b
94
95 .align 2
96kernel_flush:
97 .word v7_flush_dcache_all
98#endif
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 9fc280e24ef4..01f792fcb220 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -124,19 +124,12 @@ static int r8a7779_cpu_kill(unsigned int cpu)
124 124
125 return 0; 125 return 0;
126} 126}
127
128static int r8a7779_cpu_disable(unsigned int cpu)
129{
130 /* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
131 return cpu == 0 ? -EPERM : 0;
132}
133#endif /* CONFIG_HOTPLUG_CPU */ 127#endif /* CONFIG_HOTPLUG_CPU */
134 128
135struct smp_operations r8a7779_smp_ops __initdata = { 129struct smp_operations r8a7779_smp_ops __initdata = {
136 .smp_prepare_cpus = r8a7779_smp_prepare_cpus, 130 .smp_prepare_cpus = r8a7779_smp_prepare_cpus,
137 .smp_boot_secondary = r8a7779_boot_secondary, 131 .smp_boot_secondary = r8a7779_boot_secondary,
138#ifdef CONFIG_HOTPLUG_CPU 132#ifdef CONFIG_HOTPLUG_CPU
139 .cpu_disable = r8a7779_cpu_disable,
140 .cpu_die = shmobile_smp_scu_cpu_die, 133 .cpu_die = shmobile_smp_scu_cpu_die,
141 .cpu_kill = r8a7779_cpu_kill, 134 .cpu_kill = r8a7779_cpu_kill,
142#endif 135#endif
diff --git a/arch/arm/tools/mach-types b/arch/arm/tools/mach-types
index a10297da122b..2ed1b8a922ed 100644
--- a/arch/arm/tools/mach-types
+++ b/arch/arm/tools/mach-types
@@ -526,7 +526,6 @@ ag5evm MACH_AG5EVM AG5EVM 3189
526ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206 526ics_if_voip MACH_ICS_IF_VOIP ICS_IF_VOIP 3206
527wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207 527wlf_cragg_6410 MACH_WLF_CRAGG_6410 WLF_CRAGG_6410 3207
528trimslice MACH_TRIMSLICE TRIMSLICE 3209 528trimslice MACH_TRIMSLICE TRIMSLICE 3209
529mackerel MACH_MACKEREL MACKEREL 3211
530kaen MACH_KAEN KAEN 3217 529kaen MACH_KAEN KAEN 3217
531nokia_rm680 MACH_NOKIA_RM680 NOKIA_RM680 3220 530nokia_rm680 MACH_NOKIA_RM680 NOKIA_RM680 3220
532msm8960_sim MACH_MSM8960_SIM MSM8960_SIM 3230 531msm8960_sim MACH_MSM8960_SIM MSM8960_SIM 3230
diff --git a/arch/arm64/boot/dts/arm/foundation-v8.dts b/arch/arm64/boot/dts/arm/foundation-v8.dts
index 27f32962e55c..4eac8dcea423 100644
--- a/arch/arm64/boot/dts/arm/foundation-v8.dts
+++ b/arch/arm64/boot/dts/arm/foundation-v8.dts
@@ -34,6 +34,7 @@
34 reg = <0x0 0x0>; 34 reg = <0x0 0x0>;
35 enable-method = "spin-table"; 35 enable-method = "spin-table";
36 cpu-release-addr = <0x0 0x8000fff8>; 36 cpu-release-addr = <0x0 0x8000fff8>;
37 next-level-cache = <&L2_0>;
37 }; 38 };
38 cpu@1 { 39 cpu@1 {
39 device_type = "cpu"; 40 device_type = "cpu";
@@ -41,6 +42,7 @@
41 reg = <0x0 0x1>; 42 reg = <0x0 0x1>;
42 enable-method = "spin-table"; 43 enable-method = "spin-table";
43 cpu-release-addr = <0x0 0x8000fff8>; 44 cpu-release-addr = <0x0 0x8000fff8>;
45 next-level-cache = <&L2_0>;
44 }; 46 };
45 cpu@2 { 47 cpu@2 {
46 device_type = "cpu"; 48 device_type = "cpu";
@@ -48,6 +50,7 @@
48 reg = <0x0 0x2>; 50 reg = <0x0 0x2>;
49 enable-method = "spin-table"; 51 enable-method = "spin-table";
50 cpu-release-addr = <0x0 0x8000fff8>; 52 cpu-release-addr = <0x0 0x8000fff8>;
53 next-level-cache = <&L2_0>;
51 }; 54 };
52 cpu@3 { 55 cpu@3 {
53 device_type = "cpu"; 56 device_type = "cpu";
@@ -55,6 +58,11 @@
55 reg = <0x0 0x3>; 58 reg = <0x0 0x3>;
56 enable-method = "spin-table"; 59 enable-method = "spin-table";
57 cpu-release-addr = <0x0 0x8000fff8>; 60 cpu-release-addr = <0x0 0x8000fff8>;
61 next-level-cache = <&L2_0>;
62 };
63
64 L2_0: l2-cache0 {
65 compatible = "cache";
58 }; 66 };
59 }; 67 };
60 68
diff --git a/arch/arm64/boot/dts/arm/juno.dts b/arch/arm64/boot/dts/arm/juno.dts
index d429129ecb3d..133ee59de2d7 100644
--- a/arch/arm64/boot/dts/arm/juno.dts
+++ b/arch/arm64/boot/dts/arm/juno.dts
@@ -39,6 +39,7 @@
39 reg = <0x0 0x0>; 39 reg = <0x0 0x0>;
40 device_type = "cpu"; 40 device_type = "cpu";
41 enable-method = "psci"; 41 enable-method = "psci";
42 next-level-cache = <&A57_L2>;
42 }; 43 };
43 44
44 A57_1: cpu@1 { 45 A57_1: cpu@1 {
@@ -46,6 +47,7 @@
46 reg = <0x0 0x1>; 47 reg = <0x0 0x1>;
47 device_type = "cpu"; 48 device_type = "cpu";
48 enable-method = "psci"; 49 enable-method = "psci";
50 next-level-cache = <&A57_L2>;
49 }; 51 };
50 52
51 A53_0: cpu@100 { 53 A53_0: cpu@100 {
@@ -53,6 +55,7 @@
53 reg = <0x0 0x100>; 55 reg = <0x0 0x100>;
54 device_type = "cpu"; 56 device_type = "cpu";
55 enable-method = "psci"; 57 enable-method = "psci";
58 next-level-cache = <&A53_L2>;
56 }; 59 };
57 60
58 A53_1: cpu@101 { 61 A53_1: cpu@101 {
@@ -60,6 +63,7 @@
60 reg = <0x0 0x101>; 63 reg = <0x0 0x101>;
61 device_type = "cpu"; 64 device_type = "cpu";
62 enable-method = "psci"; 65 enable-method = "psci";
66 next-level-cache = <&A53_L2>;
63 }; 67 };
64 68
65 A53_2: cpu@102 { 69 A53_2: cpu@102 {
@@ -67,6 +71,7 @@
67 reg = <0x0 0x102>; 71 reg = <0x0 0x102>;
68 device_type = "cpu"; 72 device_type = "cpu";
69 enable-method = "psci"; 73 enable-method = "psci";
74 next-level-cache = <&A53_L2>;
70 }; 75 };
71 76
72 A53_3: cpu@103 { 77 A53_3: cpu@103 {
@@ -74,6 +79,15 @@
74 reg = <0x0 0x103>; 79 reg = <0x0 0x103>;
75 device_type = "cpu"; 80 device_type = "cpu";
76 enable-method = "psci"; 81 enable-method = "psci";
82 next-level-cache = <&A53_L2>;
83 };
84
85 A57_L2: l2-cache0 {
86 compatible = "cache";
87 };
88
89 A53_L2: l2-cache1 {
90 compatible = "cache";
77 }; 91 };
78 }; 92 };
79 93
diff --git a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
index efc59b3baf63..20addabbd127 100644
--- a/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
+++ b/arch/arm64/boot/dts/arm/rtsm_ve-aemv8a.dts
@@ -37,6 +37,7 @@
37 reg = <0x0 0x0>; 37 reg = <0x0 0x0>;
38 enable-method = "spin-table"; 38 enable-method = "spin-table";
39 cpu-release-addr = <0x0 0x8000fff8>; 39 cpu-release-addr = <0x0 0x8000fff8>;
40 next-level-cache = <&L2_0>;
40 }; 41 };
41 cpu@1 { 42 cpu@1 {
42 device_type = "cpu"; 43 device_type = "cpu";
@@ -44,6 +45,7 @@
44 reg = <0x0 0x1>; 45 reg = <0x0 0x1>;
45 enable-method = "spin-table"; 46 enable-method = "spin-table";
46 cpu-release-addr = <0x0 0x8000fff8>; 47 cpu-release-addr = <0x0 0x8000fff8>;
48 next-level-cache = <&L2_0>;
47 }; 49 };
48 cpu@2 { 50 cpu@2 {
49 device_type = "cpu"; 51 device_type = "cpu";
@@ -51,6 +53,7 @@
51 reg = <0x0 0x2>; 53 reg = <0x0 0x2>;
52 enable-method = "spin-table"; 54 enable-method = "spin-table";
53 cpu-release-addr = <0x0 0x8000fff8>; 55 cpu-release-addr = <0x0 0x8000fff8>;
56 next-level-cache = <&L2_0>;
54 }; 57 };
55 cpu@3 { 58 cpu@3 {
56 device_type = "cpu"; 59 device_type = "cpu";
@@ -58,6 +61,11 @@
58 reg = <0x0 0x3>; 61 reg = <0x0 0x3>;
59 enable-method = "spin-table"; 62 enable-method = "spin-table";
60 cpu-release-addr = <0x0 0x8000fff8>; 63 cpu-release-addr = <0x0 0x8000fff8>;
64 next-level-cache = <&L2_0>;
65 };
66
67 L2_0: l2-cache0 {
68 compatible = "cache";
61 }; 69 };
62 }; 70 };
63 71
diff --git a/arch/arm64/crypto/Makefile b/arch/arm64/crypto/Makefile
index 5720608c50b1..abb79b3cfcfe 100644
--- a/arch/arm64/crypto/Makefile
+++ b/arch/arm64/crypto/Makefile
@@ -29,7 +29,7 @@ aes-ce-blk-y := aes-glue-ce.o aes-ce.o
29obj-$(CONFIG_CRYPTO_AES_ARM64_NEON_BLK) += aes-neon-blk.o 29obj-$(CONFIG_CRYPTO_AES_ARM64_NEON_BLK) += aes-neon-blk.o
30aes-neon-blk-y := aes-glue-neon.o aes-neon.o 30aes-neon-blk-y := aes-glue-neon.o aes-neon.o
31 31
32AFLAGS_aes-ce.o := -DINTERLEAVE=2 -DINTERLEAVE_INLINE 32AFLAGS_aes-ce.o := -DINTERLEAVE=4
33AFLAGS_aes-neon.o := -DINTERLEAVE=4 33AFLAGS_aes-neon.o := -DINTERLEAVE=4
34 34
35CFLAGS_aes-glue-ce.o := -DUSE_V8_CRYPTO_EXTENSIONS 35CFLAGS_aes-glue-ce.o := -DUSE_V8_CRYPTO_EXTENSIONS
diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 5901480bfdca..750bac4e637e 100644
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -20,6 +20,9 @@
20#error "Only include this from assembly code" 20#error "Only include this from assembly code"
21#endif 21#endif
22 22
23#ifndef __ASM_ASSEMBLER_H
24#define __ASM_ASSEMBLER_H
25
23#include <asm/ptrace.h> 26#include <asm/ptrace.h>
24#include <asm/thread_info.h> 27#include <asm/thread_info.h>
25 28
@@ -155,3 +158,5 @@ lr .req x30 // link register
155#endif 158#endif
156 orr \rd, \lbits, \hbits, lsl #32 159 orr \rd, \lbits, \hbits, lsl #32
157 .endm 160 .endm
161
162#endif /* __ASM_ASSEMBLER_H */
diff --git a/arch/arm64/include/asm/cpuidle.h b/arch/arm64/include/asm/cpuidle.h
index 0710654631e7..c60643f14cda 100644
--- a/arch/arm64/include/asm/cpuidle.h
+++ b/arch/arm64/include/asm/cpuidle.h
@@ -1,6 +1,8 @@
1#ifndef __ASM_CPUIDLE_H 1#ifndef __ASM_CPUIDLE_H
2#define __ASM_CPUIDLE_H 2#define __ASM_CPUIDLE_H
3 3
4#include <asm/proc-fns.h>
5
4#ifdef CONFIG_CPU_IDLE 6#ifdef CONFIG_CPU_IDLE
5extern int cpu_init_idle(unsigned int cpu); 7extern int cpu_init_idle(unsigned int cpu);
6extern int cpu_suspend(unsigned long arg); 8extern int cpu_suspend(unsigned long arg);
diff --git a/arch/arm64/include/asm/insn.h b/arch/arm64/include/asm/insn.h
index e2ff32a93b5c..d2f49423c5dc 100644
--- a/arch/arm64/include/asm/insn.h
+++ b/arch/arm64/include/asm/insn.h
@@ -264,8 +264,10 @@ __AARCH64_INSN_FUNCS(ands, 0x7F200000, 0x6A000000)
264__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000) 264__AARCH64_INSN_FUNCS(bics, 0x7F200000, 0x6A200000)
265__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000) 265__AARCH64_INSN_FUNCS(b, 0xFC000000, 0x14000000)
266__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000) 266__AARCH64_INSN_FUNCS(bl, 0xFC000000, 0x94000000)
267__AARCH64_INSN_FUNCS(cbz, 0xFE000000, 0x34000000) 267__AARCH64_INSN_FUNCS(cbz, 0x7F000000, 0x34000000)
268__AARCH64_INSN_FUNCS(cbnz, 0xFE000000, 0x35000000) 268__AARCH64_INSN_FUNCS(cbnz, 0x7F000000, 0x35000000)
269__AARCH64_INSN_FUNCS(tbz, 0x7F000000, 0x36000000)
270__AARCH64_INSN_FUNCS(tbnz, 0x7F000000, 0x37000000)
269__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000) 271__AARCH64_INSN_FUNCS(bcond, 0xFF000010, 0x54000000)
270__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001) 272__AARCH64_INSN_FUNCS(svc, 0xFFE0001F, 0xD4000001)
271__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002) 273__AARCH64_INSN_FUNCS(hvc, 0xFFE0001F, 0xD4000002)
diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
index 16449c535e50..800ec0e87ed9 100644
--- a/arch/arm64/include/asm/pgtable.h
+++ b/arch/arm64/include/asm/pgtable.h
@@ -460,7 +460,7 @@ static inline pud_t *pud_offset(pgd_t *pgd, unsigned long addr)
460static inline pte_t pte_modify(pte_t pte, pgprot_t newprot) 460static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
461{ 461{
462 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY | 462 const pteval_t mask = PTE_USER | PTE_PXN | PTE_UXN | PTE_RDONLY |
463 PTE_PROT_NONE | PTE_VALID | PTE_WRITE; 463 PTE_PROT_NONE | PTE_WRITE | PTE_TYPE_MASK;
464 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask); 464 pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
465 return pte; 465 return pte;
466} 466}
diff --git a/arch/arm64/include/asm/processor.h b/arch/arm64/include/asm/processor.h
index f9be30ea1cbd..20e9591a60cf 100644
--- a/arch/arm64/include/asm/processor.h
+++ b/arch/arm64/include/asm/processor.h
@@ -45,7 +45,8 @@
45#define STACK_TOP STACK_TOP_MAX 45#define STACK_TOP STACK_TOP_MAX
46#endif /* CONFIG_COMPAT */ 46#endif /* CONFIG_COMPAT */
47 47
48#define ARCH_LOW_ADDRESS_LIMIT PHYS_MASK 48extern phys_addr_t arm64_dma_phys_limit;
49#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
49#endif /* __KERNEL__ */ 50#endif /* __KERNEL__ */
50 51
51struct debug_info { 52struct debug_info {
diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
index 73f0ce570fb3..4abe9b945f77 100644
--- a/arch/arm64/include/asm/tlbflush.h
+++ b/arch/arm64/include/asm/tlbflush.h
@@ -24,11 +24,6 @@
24#include <linux/sched.h> 24#include <linux/sched.h>
25#include <asm/cputype.h> 25#include <asm/cputype.h>
26 26
27extern void __cpu_flush_user_tlb_range(unsigned long, unsigned long, struct vm_area_struct *);
28extern void __cpu_flush_kern_tlb_range(unsigned long, unsigned long);
29
30extern struct cpu_tlb_fns cpu_tlb;
31
32/* 27/*
33 * TLB Management 28 * TLB Management
34 * ============== 29 * ==============
diff --git a/arch/arm64/kernel/Makefile b/arch/arm64/kernel/Makefile
index bef04afd6031..5ee07eee80c2 100644
--- a/arch/arm64/kernel/Makefile
+++ b/arch/arm64/kernel/Makefile
@@ -15,8 +15,9 @@ CFLAGS_REMOVE_return_address.o = -pg
15arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \ 15arm64-obj-y := cputable.o debug-monitors.o entry.o irq.o fpsimd.o \
16 entry-fpsimd.o process.o ptrace.o setup.o signal.o \ 16 entry-fpsimd.o process.o ptrace.o setup.o signal.o \
17 sys.o stacktrace.o time.o traps.o io.o vdso.o \ 17 sys.o stacktrace.o time.o traps.o io.o vdso.o \
18 hyp-stub.o psci.o cpu_ops.o insn.o return_address.o \ 18 hyp-stub.o psci.o psci-call.o cpu_ops.o insn.o \
19 cpuinfo.o cpu_errata.o alternative.o cacheinfo.o 19 return_address.o cpuinfo.o cpu_errata.o \
20 alternative.o cacheinfo.o
20 21
21arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \ 22arm64-obj-$(CONFIG_COMPAT) += sys32.o kuser32.o signal32.o \
22 sys_compat.o entry32.o \ 23 sys_compat.o entry32.o \
diff --git a/arch/arm64/kernel/ftrace.c b/arch/arm64/kernel/ftrace.c
index cf8556ae09d0..c851be795080 100644
--- a/arch/arm64/kernel/ftrace.c
+++ b/arch/arm64/kernel/ftrace.c
@@ -156,7 +156,7 @@ static int ftrace_modify_graph_caller(bool enable)
156 156
157 branch = aarch64_insn_gen_branch_imm(pc, 157 branch = aarch64_insn_gen_branch_imm(pc,
158 (unsigned long)ftrace_graph_caller, 158 (unsigned long)ftrace_graph_caller,
159 AARCH64_INSN_BRANCH_LINK); 159 AARCH64_INSN_BRANCH_NOLINK);
160 nop = aarch64_insn_gen_nop(); 160 nop = aarch64_insn_gen_nop();
161 161
162 if (enable) 162 if (enable)
diff --git a/arch/arm64/kernel/insn.c b/arch/arm64/kernel/insn.c
index 27d4864577e5..c8eca88f12e6 100644
--- a/arch/arm64/kernel/insn.c
+++ b/arch/arm64/kernel/insn.c
@@ -87,8 +87,10 @@ static void __kprobes *patch_map(void *addr, int fixmap)
87 87
88 if (module && IS_ENABLED(CONFIG_DEBUG_SET_MODULE_RONX)) 88 if (module && IS_ENABLED(CONFIG_DEBUG_SET_MODULE_RONX))
89 page = vmalloc_to_page(addr); 89 page = vmalloc_to_page(addr);
90 else 90 else if (!module && IS_ENABLED(CONFIG_DEBUG_RODATA))
91 page = virt_to_page(addr); 91 page = virt_to_page(addr);
92 else
93 return addr;
92 94
93 BUG_ON(!page); 95 BUG_ON(!page);
94 set_fixmap(fixmap, page_to_phys(page)); 96 set_fixmap(fixmap, page_to_phys(page));
diff --git a/arch/arm64/kernel/psci-call.S b/arch/arm64/kernel/psci-call.S
new file mode 100644
index 000000000000..cf83e61cd3b5
--- /dev/null
+++ b/arch/arm64/kernel/psci-call.S
@@ -0,0 +1,28 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2015 ARM Limited
12 *
13 * Author: Will Deacon <will.deacon@arm.com>
14 */
15
16#include <linux/linkage.h>
17
18/* int __invoke_psci_fn_hvc(u64 function_id, u64 arg0, u64 arg1, u64 arg2) */
19ENTRY(__invoke_psci_fn_hvc)
20 hvc #0
21 ret
22ENDPROC(__invoke_psci_fn_hvc)
23
24/* int __invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1, u64 arg2) */
25ENTRY(__invoke_psci_fn_smc)
26 smc #0
27 ret
28ENDPROC(__invoke_psci_fn_smc)
diff --git a/arch/arm64/kernel/psci.c b/arch/arm64/kernel/psci.c
index 3425f311c49e..9b8a70ae64a1 100644
--- a/arch/arm64/kernel/psci.c
+++ b/arch/arm64/kernel/psci.c
@@ -57,6 +57,9 @@ static struct psci_operations psci_ops;
57static int (*invoke_psci_fn)(u64, u64, u64, u64); 57static int (*invoke_psci_fn)(u64, u64, u64, u64);
58typedef int (*psci_initcall_t)(const struct device_node *); 58typedef int (*psci_initcall_t)(const struct device_node *);
59 59
60asmlinkage int __invoke_psci_fn_hvc(u64, u64, u64, u64);
61asmlinkage int __invoke_psci_fn_smc(u64, u64, u64, u64);
62
60enum psci_function { 63enum psci_function {
61 PSCI_FN_CPU_SUSPEND, 64 PSCI_FN_CPU_SUSPEND,
62 PSCI_FN_CPU_ON, 65 PSCI_FN_CPU_ON,
@@ -109,40 +112,6 @@ static void psci_power_state_unpack(u32 power_state,
109 PSCI_0_2_POWER_STATE_AFFL_SHIFT; 112 PSCI_0_2_POWER_STATE_AFFL_SHIFT;
110} 113}
111 114
112/*
113 * The following two functions are invoked via the invoke_psci_fn pointer
114 * and will not be inlined, allowing us to piggyback on the AAPCS.
115 */
116static noinline int __invoke_psci_fn_hvc(u64 function_id, u64 arg0, u64 arg1,
117 u64 arg2)
118{
119 asm volatile(
120 __asmeq("%0", "x0")
121 __asmeq("%1", "x1")
122 __asmeq("%2", "x2")
123 __asmeq("%3", "x3")
124 "hvc #0\n"
125 : "+r" (function_id)
126 : "r" (arg0), "r" (arg1), "r" (arg2));
127
128 return function_id;
129}
130
131static noinline int __invoke_psci_fn_smc(u64 function_id, u64 arg0, u64 arg1,
132 u64 arg2)
133{
134 asm volatile(
135 __asmeq("%0", "x0")
136 __asmeq("%1", "x1")
137 __asmeq("%2", "x2")
138 __asmeq("%3", "x3")
139 "smc #0\n"
140 : "+r" (function_id)
141 : "r" (arg0), "r" (arg1), "r" (arg2));
142
143 return function_id;
144}
145
146static int psci_get_version(void) 115static int psci_get_version(void)
147{ 116{
148 int err; 117 int err;
diff --git a/arch/arm64/kernel/signal32.c b/arch/arm64/kernel/signal32.c
index c20a300e2213..d26fcd4cd6e6 100644
--- a/arch/arm64/kernel/signal32.c
+++ b/arch/arm64/kernel/signal32.c
@@ -154,8 +154,7 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from)
154 case __SI_TIMER: 154 case __SI_TIMER:
155 err |= __put_user(from->si_tid, &to->si_tid); 155 err |= __put_user(from->si_tid, &to->si_tid);
156 err |= __put_user(from->si_overrun, &to->si_overrun); 156 err |= __put_user(from->si_overrun, &to->si_overrun);
157 err |= __put_user((compat_uptr_t)(unsigned long)from->si_ptr, 157 err |= __put_user(from->si_int, &to->si_int);
158 &to->si_ptr);
159 break; 158 break;
160 case __SI_POLL: 159 case __SI_POLL:
161 err |= __put_user(from->si_band, &to->si_band); 160 err |= __put_user(from->si_band, &to->si_band);
@@ -184,7 +183,7 @@ int copy_siginfo_to_user32(compat_siginfo_t __user *to, const siginfo_t *from)
184 case __SI_MESGQ: /* But this is */ 183 case __SI_MESGQ: /* But this is */
185 err |= __put_user(from->si_pid, &to->si_pid); 184 err |= __put_user(from->si_pid, &to->si_pid);
186 err |= __put_user(from->si_uid, &to->si_uid); 185 err |= __put_user(from->si_uid, &to->si_uid);
187 err |= __put_user((compat_uptr_t)(unsigned long)from->si_ptr, &to->si_ptr); 186 err |= __put_user(from->si_int, &to->si_int);
188 break; 187 break;
189 case __SI_SYS: 188 case __SI_SYS:
190 err |= __put_user((compat_uptr_t)(unsigned long) 189 err |= __put_user((compat_uptr_t)(unsigned long)
diff --git a/arch/arm64/kernel/vdso/gettimeofday.S b/arch/arm64/kernel/vdso/gettimeofday.S
index fe652ffd34c2..efa79e8d4196 100644
--- a/arch/arm64/kernel/vdso/gettimeofday.S
+++ b/arch/arm64/kernel/vdso/gettimeofday.S
@@ -174,8 +174,6 @@ ENDPROC(__kernel_clock_gettime)
174/* int __kernel_clock_getres(clockid_t clock_id, struct timespec *res); */ 174/* int __kernel_clock_getres(clockid_t clock_id, struct timespec *res); */
175ENTRY(__kernel_clock_getres) 175ENTRY(__kernel_clock_getres)
176 .cfi_startproc 176 .cfi_startproc
177 cbz w1, 3f
178
179 cmp w0, #CLOCK_REALTIME 177 cmp w0, #CLOCK_REALTIME
180 ccmp w0, #CLOCK_MONOTONIC, #0x4, ne 178 ccmp w0, #CLOCK_MONOTONIC, #0x4, ne
181 b.ne 1f 179 b.ne 1f
@@ -188,6 +186,7 @@ ENTRY(__kernel_clock_getres)
188 b.ne 4f 186 b.ne 4f
189 ldr x2, 6f 187 ldr x2, 6f
1902: 1882:
189 cbz w1, 3f
191 stp xzr, x2, [x1] 190 stp xzr, x2, [x1]
192 191
1933: /* res == NULL. */ 1923: /* res == NULL. */
diff --git a/arch/arm64/mm/dma-mapping.c b/arch/arm64/mm/dma-mapping.c
index 0a24b9b8c698..58e0c2bdde04 100644
--- a/arch/arm64/mm/dma-mapping.c
+++ b/arch/arm64/mm/dma-mapping.c
@@ -348,8 +348,6 @@ static struct dma_map_ops swiotlb_dma_ops = {
348 .mapping_error = swiotlb_dma_mapping_error, 348 .mapping_error = swiotlb_dma_mapping_error,
349}; 349};
350 350
351extern int swiotlb_late_init_with_default_size(size_t default_size);
352
353static int __init atomic_pool_init(void) 351static int __init atomic_pool_init(void)
354{ 352{
355 pgprot_t prot = __pgprot(PROT_NORMAL_NC); 353 pgprot_t prot = __pgprot(PROT_NORMAL_NC);
@@ -411,21 +409,13 @@ out:
411 return -ENOMEM; 409 return -ENOMEM;
412} 410}
413 411
414static int __init swiotlb_late_init(void) 412static int __init arm64_dma_init(void)
415{ 413{
416 size_t swiotlb_size = min(SZ_64M, MAX_ORDER_NR_PAGES << PAGE_SHIFT); 414 int ret;
417 415
418 dma_ops = &swiotlb_dma_ops; 416 dma_ops = &swiotlb_dma_ops;
419 417
420 return swiotlb_late_init_with_default_size(swiotlb_size); 418 ret = atomic_pool_init();
421}
422
423static int __init arm64_dma_init(void)
424{
425 int ret = 0;
426
427 ret |= swiotlb_late_init();
428 ret |= atomic_pool_init();
429 419
430 return ret; 420 return ret;
431} 421}
diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index 71145f952070..ae85da6307bb 100644
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -33,6 +33,7 @@
33#include <linux/dma-mapping.h> 33#include <linux/dma-mapping.h>
34#include <linux/dma-contiguous.h> 34#include <linux/dma-contiguous.h>
35#include <linux/efi.h> 35#include <linux/efi.h>
36#include <linux/swiotlb.h>
36 37
37#include <asm/fixmap.h> 38#include <asm/fixmap.h>
38#include <asm/memory.h> 39#include <asm/memory.h>
@@ -45,6 +46,7 @@
45#include "mm.h" 46#include "mm.h"
46 47
47phys_addr_t memstart_addr __read_mostly = 0; 48phys_addr_t memstart_addr __read_mostly = 0;
49phys_addr_t arm64_dma_phys_limit __read_mostly;
48 50
49#ifdef CONFIG_BLK_DEV_INITRD 51#ifdef CONFIG_BLK_DEV_INITRD
50static int __init early_initrd(char *p) 52static int __init early_initrd(char *p)
@@ -85,7 +87,7 @@ static void __init zone_sizes_init(unsigned long min, unsigned long max)
85 87
86 /* 4GB maximum for 32-bit only capable devices */ 88 /* 4GB maximum for 32-bit only capable devices */
87 if (IS_ENABLED(CONFIG_ZONE_DMA)) { 89 if (IS_ENABLED(CONFIG_ZONE_DMA)) {
88 max_dma = PFN_DOWN(max_zone_dma_phys()); 90 max_dma = PFN_DOWN(arm64_dma_phys_limit);
89 zone_size[ZONE_DMA] = max_dma - min; 91 zone_size[ZONE_DMA] = max_dma - min;
90 } 92 }
91 zone_size[ZONE_NORMAL] = max - max_dma; 93 zone_size[ZONE_NORMAL] = max - max_dma;
@@ -156,8 +158,6 @@ early_param("mem", early_mem);
156 158
157void __init arm64_memblock_init(void) 159void __init arm64_memblock_init(void)
158{ 160{
159 phys_addr_t dma_phys_limit = 0;
160
161 memblock_enforce_memory_limit(memory_limit); 161 memblock_enforce_memory_limit(memory_limit);
162 162
163 /* 163 /*
@@ -174,8 +174,10 @@ void __init arm64_memblock_init(void)
174 174
175 /* 4GB maximum for 32-bit only capable devices */ 175 /* 4GB maximum for 32-bit only capable devices */
176 if (IS_ENABLED(CONFIG_ZONE_DMA)) 176 if (IS_ENABLED(CONFIG_ZONE_DMA))
177 dma_phys_limit = max_zone_dma_phys(); 177 arm64_dma_phys_limit = max_zone_dma_phys();
178 dma_contiguous_reserve(dma_phys_limit); 178 else
179 arm64_dma_phys_limit = PHYS_MASK + 1;
180 dma_contiguous_reserve(arm64_dma_phys_limit);
179 181
180 memblock_allow_resize(); 182 memblock_allow_resize();
181 memblock_dump_all(); 183 memblock_dump_all();
@@ -276,6 +278,8 @@ static void __init free_unused_memmap(void)
276 */ 278 */
277void __init mem_init(void) 279void __init mem_init(void)
278{ 280{
281 swiotlb_init(1);
282
279 set_max_mapnr(pfn_to_page(max_pfn) - mem_map); 283 set_max_mapnr(pfn_to_page(max_pfn) - mem_map);
280 284
281#ifndef CONFIG_SPARSEMEM_VMEMMAP 285#ifndef CONFIG_SPARSEMEM_VMEMMAP
diff --git a/arch/frv/include/asm/pgtable.h b/arch/frv/include/asm/pgtable.h
index 93bcf2abd1a1..07d7a7ef8bd5 100644
--- a/arch/frv/include/asm/pgtable.h
+++ b/arch/frv/include/asm/pgtable.h
@@ -123,12 +123,14 @@ extern unsigned long empty_zero_page;
123#define PGDIR_MASK (~(PGDIR_SIZE - 1)) 123#define PGDIR_MASK (~(PGDIR_SIZE - 1))
124#define PTRS_PER_PGD 64 124#define PTRS_PER_PGD 64
125 125
126#define __PAGETABLE_PUD_FOLDED
126#define PUD_SHIFT 26 127#define PUD_SHIFT 26
127#define PTRS_PER_PUD 1 128#define PTRS_PER_PUD 1
128#define PUD_SIZE (1UL << PUD_SHIFT) 129#define PUD_SIZE (1UL << PUD_SHIFT)
129#define PUD_MASK (~(PUD_SIZE - 1)) 130#define PUD_MASK (~(PUD_SIZE - 1))
130#define PUE_SIZE 256 131#define PUE_SIZE 256
131 132
133#define __PAGETABLE_PMD_FOLDED
132#define PMD_SHIFT 26 134#define PMD_SHIFT 26
133#define PMD_SIZE (1UL << PMD_SHIFT) 135#define PMD_SIZE (1UL << PMD_SHIFT)
134#define PMD_MASK (~(PMD_SIZE - 1)) 136#define PMD_MASK (~(PMD_SIZE - 1))
diff --git a/arch/m32r/include/asm/pgtable-2level.h b/arch/m32r/include/asm/pgtable-2level.h
index 8fd8ee70266a..421e6ba3a173 100644
--- a/arch/m32r/include/asm/pgtable-2level.h
+++ b/arch/m32r/include/asm/pgtable-2level.h
@@ -13,6 +13,7 @@
13 * the M32R is two-level, so we don't really have any 13 * the M32R is two-level, so we don't really have any
14 * PMD directory physically. 14 * PMD directory physically.
15 */ 15 */
16#define __PAGETABLE_PMD_FOLDED
16#define PMD_SHIFT 22 17#define PMD_SHIFT 22
17#define PTRS_PER_PMD 1 18#define PTRS_PER_PMD 1
18 19
diff --git a/arch/m68k/include/asm/pgtable_mm.h b/arch/m68k/include/asm/pgtable_mm.h
index 28a145bfbb71..35ed4a9981ae 100644
--- a/arch/m68k/include/asm/pgtable_mm.h
+++ b/arch/m68k/include/asm/pgtable_mm.h
@@ -54,10 +54,12 @@
54 */ 54 */
55#ifdef CONFIG_SUN3 55#ifdef CONFIG_SUN3
56#define PTRS_PER_PTE 16 56#define PTRS_PER_PTE 16
57#define __PAGETABLE_PMD_FOLDED
57#define PTRS_PER_PMD 1 58#define PTRS_PER_PMD 1
58#define PTRS_PER_PGD 2048 59#define PTRS_PER_PGD 2048
59#elif defined(CONFIG_COLDFIRE) 60#elif defined(CONFIG_COLDFIRE)
60#define PTRS_PER_PTE 512 61#define PTRS_PER_PTE 512
62#define __PAGETABLE_PMD_FOLDED
61#define PTRS_PER_PMD 1 63#define PTRS_PER_PMD 1
62#define PTRS_PER_PGD 1024 64#define PTRS_PER_PGD 1024
63#else 65#else
diff --git a/arch/metag/include/asm/processor.h b/arch/metag/include/asm/processor.h
index 881071c07942..13272fd5a5ba 100644
--- a/arch/metag/include/asm/processor.h
+++ b/arch/metag/include/asm/processor.h
@@ -149,8 +149,8 @@ extern void exit_thread(void);
149 149
150unsigned long get_wchan(struct task_struct *p); 150unsigned long get_wchan(struct task_struct *p);
151 151
152#define KSTK_EIP(tsk) ((tsk)->thread.kernel_context->CurrPC) 152#define KSTK_EIP(tsk) (task_pt_regs(tsk)->ctx.CurrPC)
153#define KSTK_ESP(tsk) ((tsk)->thread.kernel_context->AX[0].U0) 153#define KSTK_ESP(tsk) (task_pt_regs(tsk)->ctx.AX[0].U0)
154 154
155#define user_stack_pointer(regs) ((regs)->ctx.AX[0].U0) 155#define user_stack_pointer(regs) ((regs)->ctx.AX[0].U0)
156 156
diff --git a/arch/mn10300/include/asm/pgtable.h b/arch/mn10300/include/asm/pgtable.h
index afab728ab65e..96d3f9deb59c 100644
--- a/arch/mn10300/include/asm/pgtable.h
+++ b/arch/mn10300/include/asm/pgtable.h
@@ -56,7 +56,9 @@ extern void paging_init(void);
56#define PGDIR_SHIFT 22 56#define PGDIR_SHIFT 22
57#define PTRS_PER_PGD 1024 57#define PTRS_PER_PGD 1024
58#define PTRS_PER_PUD 1 /* we don't really have any PUD physically */ 58#define PTRS_PER_PUD 1 /* we don't really have any PUD physically */
59#define __PAGETABLE_PUD_FOLDED
59#define PTRS_PER_PMD 1 /* we don't really have any PMD physically */ 60#define PTRS_PER_PMD 1 /* we don't really have any PMD physically */
61#define __PAGETABLE_PMD_FOLDED
60#define PTRS_PER_PTE 1024 62#define PTRS_PER_PTE 1024
61 63
62#define PGD_SIZE PAGE_SIZE 64#define PGD_SIZE PAGE_SIZE
diff --git a/arch/parisc/include/asm/pgtable.h b/arch/parisc/include/asm/pgtable.h
index 8c966b2270aa..15207b9362bf 100644
--- a/arch/parisc/include/asm/pgtable.h
+++ b/arch/parisc/include/asm/pgtable.h
@@ -96,6 +96,7 @@ extern void purge_tlb_entries(struct mm_struct *, unsigned long);
96#if PT_NLEVELS == 3 96#if PT_NLEVELS == 3
97#define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY) 97#define BITS_PER_PMD (PAGE_SHIFT + PMD_ORDER - BITS_PER_PMD_ENTRY)
98#else 98#else
99#define __PAGETABLE_PMD_FOLDED
99#define BITS_PER_PMD 0 100#define BITS_PER_PMD 0
100#endif 101#endif
101#define PTRS_PER_PMD (1UL << BITS_PER_PMD) 102#define PTRS_PER_PMD (1UL << BITS_PER_PMD)
diff --git a/arch/s390/include/asm/pgtable.h b/arch/s390/include/asm/pgtable.h
index fbb5ee3ae57c..e08ec38f8c6e 100644
--- a/arch/s390/include/asm/pgtable.h
+++ b/arch/s390/include/asm/pgtable.h
@@ -91,7 +91,9 @@ extern unsigned long zero_page_mask;
91 */ 91 */
92#define PTRS_PER_PTE 256 92#define PTRS_PER_PTE 256
93#ifndef CONFIG_64BIT 93#ifndef CONFIG_64BIT
94#define __PAGETABLE_PUD_FOLDED
94#define PTRS_PER_PMD 1 95#define PTRS_PER_PMD 1
96#define __PAGETABLE_PMD_FOLDED
95#define PTRS_PER_PUD 1 97#define PTRS_PER_PUD 1
96#else /* CONFIG_64BIT */ 98#else /* CONFIG_64BIT */
97#define PTRS_PER_PMD 2048 99#define PTRS_PER_PMD 2048
diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c
index b5c8ff5e9dfc..2346c95c6ab1 100644
--- a/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@ -1396,6 +1396,12 @@ void cpu_init(void)
1396 1396
1397 wait_for_master_cpu(cpu); 1397 wait_for_master_cpu(cpu);
1398 1398
1399 /*
1400 * Initialize the CR4 shadow before doing anything that could
1401 * try to read it.
1402 */
1403 cr4_init_shadow();
1404
1399 show_ucode_info_early(); 1405 show_ucode_info_early();
1400 1406
1401 printk(KERN_INFO "Initializing CPU#%d\n", cpu); 1407 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index 94d7dcb12145..50163fa9034f 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -565,8 +565,8 @@ static const struct _tlb_table intel_tlb_table[] = {
565 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" }, 565 { 0xb2, TLB_INST_4K, 64, " TLB_INST 4KByte pages, 4-way set associative" },
566 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" }, 566 { 0xb3, TLB_DATA_4K, 128, " TLB_DATA 4 KByte pages, 4-way set associative" },
567 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" }, 567 { 0xb4, TLB_DATA_4K, 256, " TLB_DATA 4 KByte pages, 4-way associative" },
568 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set ssociative" }, 568 { 0xb5, TLB_INST_4K, 64, " TLB_INST 4 KByte pages, 8-way set associative" },
569 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set ssociative" }, 569 { 0xb6, TLB_INST_4K, 128, " TLB_INST 4 KByte pages, 8-way set associative" },
570 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" }, 570 { 0xba, TLB_DATA_4K, 64, " TLB_DATA 4 KByte pages, 4-way associative" },
571 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" }, 571 { 0xc0, TLB_DATA_4K_4M, 8, " TLB_DATA 4 KByte and 4 MByte pages, 4-way associative" },
572 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" }, 572 { 0xc1, STLB_4K_2M, 1024, " STLB 4 KByte and 2 MByte pages, 8-way associative" },
diff --git a/arch/x86/kernel/entry_32.S b/arch/x86/kernel/entry_32.S
index 000d4199b03e..31e2d5bf3e38 100644
--- a/arch/x86/kernel/entry_32.S
+++ b/arch/x86/kernel/entry_32.S
@@ -982,6 +982,9 @@ ENTRY(xen_hypervisor_callback)
982ENTRY(xen_do_upcall) 982ENTRY(xen_do_upcall)
9831: mov %esp, %eax 9831: mov %esp, %eax
984 call xen_evtchn_do_upcall 984 call xen_evtchn_do_upcall
985#ifndef CONFIG_PREEMPT
986 call xen_maybe_preempt_hcall
987#endif
985 jmp ret_from_intr 988 jmp ret_from_intr
986 CFI_ENDPROC 989 CFI_ENDPROC
987ENDPROC(xen_hypervisor_callback) 990ENDPROC(xen_hypervisor_callback)
diff --git a/arch/x86/kernel/entry_64.S b/arch/x86/kernel/entry_64.S
index db13655c3a2a..10074ad9ebf8 100644
--- a/arch/x86/kernel/entry_64.S
+++ b/arch/x86/kernel/entry_64.S
@@ -1208,6 +1208,9 @@ ENTRY(xen_do_hypervisor_callback) # do_hypervisor_callback(struct *pt_regs)
1208 popq %rsp 1208 popq %rsp
1209 CFI_DEF_CFA_REGISTER rsp 1209 CFI_DEF_CFA_REGISTER rsp
1210 decl PER_CPU_VAR(irq_count) 1210 decl PER_CPU_VAR(irq_count)
1211#ifndef CONFIG_PREEMPT
1212 call xen_maybe_preempt_hcall
1213#endif
1211 jmp error_exit 1214 jmp error_exit
1212 CFI_ENDPROC 1215 CFI_ENDPROC
1213END(xen_do_hypervisor_callback) 1216END(xen_do_hypervisor_callback)
diff --git a/arch/x86/kernel/kprobes/core.c b/arch/x86/kernel/kprobes/core.c
index 6a1146ea4d4d..4e3d5a9621fe 100644
--- a/arch/x86/kernel/kprobes/core.c
+++ b/arch/x86/kernel/kprobes/core.c
@@ -223,27 +223,48 @@ static unsigned long
223__recover_probed_insn(kprobe_opcode_t *buf, unsigned long addr) 223__recover_probed_insn(kprobe_opcode_t *buf, unsigned long addr)
224{ 224{
225 struct kprobe *kp; 225 struct kprobe *kp;
226 unsigned long faddr;
226 227
227 kp = get_kprobe((void *)addr); 228 kp = get_kprobe((void *)addr);
228 /* There is no probe, return original address */ 229 faddr = ftrace_location(addr);
229 if (!kp) 230 /*
231 * Addresses inside the ftrace location are refused by
232 * arch_check_ftrace_location(). Something went terribly wrong
233 * if such an address is checked here.
234 */
235 if (WARN_ON(faddr && faddr != addr))
236 return 0UL;
237 /*
238 * Use the current code if it is not modified by Kprobe
239 * and it cannot be modified by ftrace.
240 */
241 if (!kp && !faddr)
230 return addr; 242 return addr;
231 243
232 /* 244 /*
233 * Basically, kp->ainsn.insn has an original instruction. 245 * Basically, kp->ainsn.insn has an original instruction.
234 * However, RIP-relative instruction can not do single-stepping 246 * However, RIP-relative instruction can not do single-stepping
235 * at different place, __copy_instruction() tweaks the displacement of 247 * at different place, __copy_instruction() tweaks the displacement of
236 * that instruction. In that case, we can't recover the instruction 248 * that instruction. In that case, we can't recover the instruction
237 * from the kp->ainsn.insn. 249 * from the kp->ainsn.insn.
238 * 250 *
239 * On the other hand, kp->opcode has a copy of the first byte of 251 * On the other hand, in case on normal Kprobe, kp->opcode has a copy
240 * the probed instruction, which is overwritten by int3. And 252 * of the first byte of the probed instruction, which is overwritten
241 * the instruction at kp->addr is not modified by kprobes except 253 * by int3. And the instruction at kp->addr is not modified by kprobes
242 * for the first byte, we can recover the original instruction 254 * except for the first byte, we can recover the original instruction
243 * from it and kp->opcode. 255 * from it and kp->opcode.
256 *
257 * In case of Kprobes using ftrace, we do not have a copy of
258 * the original instruction. In fact, the ftrace location might
259 * be modified at anytime and even could be in an inconsistent state.
260 * Fortunately, we know that the original code is the ideal 5-byte
261 * long NOP.
244 */ 262 */
245 memcpy(buf, kp->addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t)); 263 memcpy(buf, (void *)addr, MAX_INSN_SIZE * sizeof(kprobe_opcode_t));
246 buf[0] = kp->opcode; 264 if (faddr)
265 memcpy(buf, ideal_nops[NOP_ATOMIC5], 5);
266 else
267 buf[0] = kp->opcode;
247 return (unsigned long)buf; 268 return (unsigned long)buf;
248} 269}
249 270
@@ -251,6 +272,7 @@ __recover_probed_insn(kprobe_opcode_t *buf, unsigned long addr)
251 * Recover the probed instruction at addr for further analysis. 272 * Recover the probed instruction at addr for further analysis.
252 * Caller must lock kprobes by kprobe_mutex, or disable preemption 273 * Caller must lock kprobes by kprobe_mutex, or disable preemption
253 * for preventing to release referencing kprobes. 274 * for preventing to release referencing kprobes.
275 * Returns zero if the instruction can not get recovered.
254 */ 276 */
255unsigned long recover_probed_instruction(kprobe_opcode_t *buf, unsigned long addr) 277unsigned long recover_probed_instruction(kprobe_opcode_t *buf, unsigned long addr)
256{ 278{
@@ -285,6 +307,8 @@ static int can_probe(unsigned long paddr)
285 * normally used, we just go through if there is no kprobe. 307 * normally used, we just go through if there is no kprobe.
286 */ 308 */
287 __addr = recover_probed_instruction(buf, addr); 309 __addr = recover_probed_instruction(buf, addr);
310 if (!__addr)
311 return 0;
288 kernel_insn_init(&insn, (void *)__addr, MAX_INSN_SIZE); 312 kernel_insn_init(&insn, (void *)__addr, MAX_INSN_SIZE);
289 insn_get_length(&insn); 313 insn_get_length(&insn);
290 314
@@ -333,6 +357,8 @@ int __copy_instruction(u8 *dest, u8 *src)
333 unsigned long recovered_insn = 357 unsigned long recovered_insn =
334 recover_probed_instruction(buf, (unsigned long)src); 358 recover_probed_instruction(buf, (unsigned long)src);
335 359
360 if (!recovered_insn)
361 return 0;
336 kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE); 362 kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE);
337 insn_get_length(&insn); 363 insn_get_length(&insn);
338 /* Another subsystem puts a breakpoint, failed to recover */ 364 /* Another subsystem puts a breakpoint, failed to recover */
diff --git a/arch/x86/kernel/kprobes/opt.c b/arch/x86/kernel/kprobes/opt.c
index 0dd8d089c315..7b3b9d15c47a 100644
--- a/arch/x86/kernel/kprobes/opt.c
+++ b/arch/x86/kernel/kprobes/opt.c
@@ -259,6 +259,8 @@ static int can_optimize(unsigned long paddr)
259 */ 259 */
260 return 0; 260 return 0;
261 recovered_insn = recover_probed_instruction(buf, addr); 261 recovered_insn = recover_probed_instruction(buf, addr);
262 if (!recovered_insn)
263 return 0;
262 kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE); 264 kernel_insn_init(&insn, (void *)recovered_insn, MAX_INSN_SIZE);
263 insn_get_length(&insn); 265 insn_get_length(&insn);
264 /* Another subsystem puts a breakpoint */ 266 /* Another subsystem puts a breakpoint */
diff --git a/arch/x86/lguest/Kconfig b/arch/x86/lguest/Kconfig
index 4a0890f815c4..08f41caada45 100644
--- a/arch/x86/lguest/Kconfig
+++ b/arch/x86/lguest/Kconfig
@@ -1,6 +1,6 @@
1config LGUEST_GUEST 1config LGUEST_GUEST
2 bool "Lguest guest support" 2 bool "Lguest guest support"
3 depends on X86_32 && PARAVIRT 3 depends on X86_32 && PARAVIRT && PCI
4 select TTY 4 select TTY
5 select VIRTUALIZATION 5 select VIRTUALIZATION
6 select VIRTIO 6 select VIRTIO
@@ -8,7 +8,7 @@ config LGUEST_GUEST
8 help 8 help
9 Lguest is a tiny in-kernel hypervisor. Selecting this will 9 Lguest is a tiny in-kernel hypervisor. Selecting this will
10 allow your kernel to boot under lguest. This option will increase 10 allow your kernel to boot under lguest. This option will increase
11 your kernel size by about 6k. If in doubt, say N. 11 your kernel size by about 10k. If in doubt, say N.
12 12
13 If you say Y here, make sure you say Y (or M) to the virtio block 13 If you say Y here, make sure you say Y (or M) to the virtio block
14 and net drivers which lguest needs. 14 and net drivers which lguest needs.
diff --git a/arch/x86/platform/intel-mid/intel-mid.c b/arch/x86/platform/intel-mid/intel-mid.c
index 1bbedc4b0f88..3005f0c89f2e 100644
--- a/arch/x86/platform/intel-mid/intel-mid.c
+++ b/arch/x86/platform/intel-mid/intel-mid.c
@@ -130,7 +130,7 @@ static void intel_mid_arch_setup(void)
130 intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip](); 130 intel_mid_ops = get_intel_mid_ops[__intel_mid_cpu_chip]();
131 else { 131 else {
132 intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL](); 132 intel_mid_ops = get_intel_mid_ops[INTEL_MID_CPU_CHIP_PENWELL]();
133 pr_info("ARCH: Uknown SoC, assuming PENWELL!\n"); 133 pr_info("ARCH: Unknown SoC, assuming PENWELL!\n");
134 } 134 }
135 135
136out: 136out:
diff --git a/arch/x86/xen/enlighten.c b/arch/x86/xen/enlighten.c
index bd8b8459c3d0..5240f563076d 100644
--- a/arch/x86/xen/enlighten.c
+++ b/arch/x86/xen/enlighten.c
@@ -1070,6 +1070,23 @@ static inline void xen_write_cr8(unsigned long val)
1070 BUG_ON(val); 1070 BUG_ON(val);
1071} 1071}
1072#endif 1072#endif
1073
1074static u64 xen_read_msr_safe(unsigned int msr, int *err)
1075{
1076 u64 val;
1077
1078 val = native_read_msr_safe(msr, err);
1079 switch (msr) {
1080 case MSR_IA32_APICBASE:
1081#ifdef CONFIG_X86_X2APIC
1082 if (!(cpuid_ecx(1) & (1 << (X86_FEATURE_X2APIC & 31))))
1083#endif
1084 val &= ~X2APIC_ENABLE;
1085 break;
1086 }
1087 return val;
1088}
1089
1073static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high) 1090static int xen_write_msr_safe(unsigned int msr, unsigned low, unsigned high)
1074{ 1091{
1075 int ret; 1092 int ret;
@@ -1240,7 +1257,7 @@ static const struct pv_cpu_ops xen_cpu_ops __initconst = {
1240 1257
1241 .wbinvd = native_wbinvd, 1258 .wbinvd = native_wbinvd,
1242 1259
1243 .read_msr = native_read_msr_safe, 1260 .read_msr = xen_read_msr_safe,
1244 .write_msr = xen_write_msr_safe, 1261 .write_msr = xen_write_msr_safe,
1245 1262
1246 .read_tsc = native_read_tsc, 1263 .read_tsc = native_read_tsc,
@@ -1741,6 +1758,7 @@ asmlinkage __visible void __init xen_start_kernel(void)
1741#ifdef CONFIG_X86_32 1758#ifdef CONFIG_X86_32
1742 i386_start_kernel(); 1759 i386_start_kernel();
1743#else 1760#else
1761 cr4_init_shadow(); /* 32b kernel does this in i386_start_kernel() */
1744 x86_64_start_reservations((char *)__pa_symbol(&boot_params)); 1762 x86_64_start_reservations((char *)__pa_symbol(&boot_params));
1745#endif 1763#endif
1746} 1764}
diff --git a/drivers/block/nvme-core.c b/drivers/block/nvme-core.c
index b64bccbb78c9..ceb32dd52a6c 100644
--- a/drivers/block/nvme-core.c
+++ b/drivers/block/nvme-core.c
@@ -482,6 +482,7 @@ static int nvme_error_status(u16 status)
482 } 482 }
483} 483}
484 484
485#ifdef CONFIG_BLK_DEV_INTEGRITY
485static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi) 486static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
486{ 487{
487 if (be32_to_cpu(pi->ref_tag) == v) 488 if (be32_to_cpu(pi->ref_tag) == v)
@@ -538,6 +539,58 @@ static void nvme_dif_remap(struct request *req,
538 kunmap_atomic(pmap); 539 kunmap_atomic(pmap);
539} 540}
540 541
542static int nvme_noop_verify(struct blk_integrity_iter *iter)
543{
544 return 0;
545}
546
547static int nvme_noop_generate(struct blk_integrity_iter *iter)
548{
549 return 0;
550}
551
552struct blk_integrity nvme_meta_noop = {
553 .name = "NVME_META_NOOP",
554 .generate_fn = nvme_noop_generate,
555 .verify_fn = nvme_noop_verify,
556};
557
558static void nvme_init_integrity(struct nvme_ns *ns)
559{
560 struct blk_integrity integrity;
561
562 switch (ns->pi_type) {
563 case NVME_NS_DPS_PI_TYPE3:
564 integrity = t10_pi_type3_crc;
565 break;
566 case NVME_NS_DPS_PI_TYPE1:
567 case NVME_NS_DPS_PI_TYPE2:
568 integrity = t10_pi_type1_crc;
569 break;
570 default:
571 integrity = nvme_meta_noop;
572 break;
573 }
574 integrity.tuple_size = ns->ms;
575 blk_integrity_register(ns->disk, &integrity);
576 blk_queue_max_integrity_segments(ns->queue, 1);
577}
578#else /* CONFIG_BLK_DEV_INTEGRITY */
579static void nvme_dif_remap(struct request *req,
580 void (*dif_swap)(u32 p, u32 v, struct t10_pi_tuple *pi))
581{
582}
583static void nvme_dif_prep(u32 p, u32 v, struct t10_pi_tuple *pi)
584{
585}
586static void nvme_dif_complete(u32 p, u32 v, struct t10_pi_tuple *pi)
587{
588}
589static void nvme_init_integrity(struct nvme_ns *ns)
590{
591}
592#endif
593
541static void req_completion(struct nvme_queue *nvmeq, void *ctx, 594static void req_completion(struct nvme_queue *nvmeq, void *ctx,
542 struct nvme_completion *cqe) 595 struct nvme_completion *cqe)
543{ 596{
@@ -1959,43 +2012,6 @@ static void nvme_config_discard(struct nvme_ns *ns)
1959 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue); 2012 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1960} 2013}
1961 2014
1962static int nvme_noop_verify(struct blk_integrity_iter *iter)
1963{
1964 return 0;
1965}
1966
1967static int nvme_noop_generate(struct blk_integrity_iter *iter)
1968{
1969 return 0;
1970}
1971
1972struct blk_integrity nvme_meta_noop = {
1973 .name = "NVME_META_NOOP",
1974 .generate_fn = nvme_noop_generate,
1975 .verify_fn = nvme_noop_verify,
1976};
1977
1978static void nvme_init_integrity(struct nvme_ns *ns)
1979{
1980 struct blk_integrity integrity;
1981
1982 switch (ns->pi_type) {
1983 case NVME_NS_DPS_PI_TYPE3:
1984 integrity = t10_pi_type3_crc;
1985 break;
1986 case NVME_NS_DPS_PI_TYPE1:
1987 case NVME_NS_DPS_PI_TYPE2:
1988 integrity = t10_pi_type1_crc;
1989 break;
1990 default:
1991 integrity = nvme_meta_noop;
1992 break;
1993 }
1994 integrity.tuple_size = ns->ms;
1995 blk_integrity_register(ns->disk, &integrity);
1996 blk_queue_max_integrity_segments(ns->queue, 1);
1997}
1998
1999static int nvme_revalidate_disk(struct gendisk *disk) 2015static int nvme_revalidate_disk(struct gendisk *disk)
2000{ 2016{
2001 struct nvme_ns *ns = disk->private_data; 2017 struct nvme_ns *ns = disk->private_data;
@@ -2036,7 +2052,8 @@ static int nvme_revalidate_disk(struct gendisk *disk)
2036 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ? 2052 pi_type = ns->ms == sizeof(struct t10_pi_tuple) ?
2037 id->dps & NVME_NS_DPS_PI_MASK : 0; 2053 id->dps & NVME_NS_DPS_PI_MASK : 0;
2038 2054
2039 if (disk->integrity && (ns->pi_type != pi_type || ns->ms != old_ms || 2055 if (blk_get_integrity(disk) && (ns->pi_type != pi_type ||
2056 ns->ms != old_ms ||
2040 bs != queue_logical_block_size(disk->queue) || 2057 bs != queue_logical_block_size(disk->queue) ||
2041 (ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT))) 2058 (ns->ms && id->flbas & NVME_NS_FLBAS_META_EXT)))
2042 blk_integrity_unregister(disk); 2059 blk_integrity_unregister(disk);
@@ -2044,11 +2061,11 @@ static int nvme_revalidate_disk(struct gendisk *disk)
2044 ns->pi_type = pi_type; 2061 ns->pi_type = pi_type;
2045 blk_queue_logical_block_size(ns->queue, bs); 2062 blk_queue_logical_block_size(ns->queue, bs);
2046 2063
2047 if (ns->ms && !disk->integrity && (disk->flags & GENHD_FL_UP) && 2064 if (ns->ms && !blk_get_integrity(disk) && (disk->flags & GENHD_FL_UP) &&
2048 !(id->flbas & NVME_NS_FLBAS_META_EXT)) 2065 !(id->flbas & NVME_NS_FLBAS_META_EXT))
2049 nvme_init_integrity(ns); 2066 nvme_init_integrity(ns);
2050 2067
2051 if (id->ncap == 0 || (ns->ms && !disk->integrity)) 2068 if (id->ncap == 0 || (ns->ms && !blk_get_integrity(disk)))
2052 set_capacity(disk, 0); 2069 set_capacity(disk, 0);
2053 else 2070 else
2054 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9)); 2071 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
@@ -2652,7 +2669,7 @@ static void nvme_dev_remove(struct nvme_dev *dev)
2652 2669
2653 list_for_each_entry(ns, &dev->namespaces, list) { 2670 list_for_each_entry(ns, &dev->namespaces, list) {
2654 if (ns->disk->flags & GENHD_FL_UP) { 2671 if (ns->disk->flags & GENHD_FL_UP) {
2655 if (ns->disk->integrity) 2672 if (blk_get_integrity(ns->disk))
2656 blk_integrity_unregister(ns->disk); 2673 blk_integrity_unregister(ns->disk);
2657 del_gendisk(ns->disk); 2674 del_gendisk(ns->disk);
2658 } 2675 }
diff --git a/drivers/block/zram/zram_drv.c b/drivers/block/zram/zram_drv.c
index 8e233edd7a09..871bd3550cb0 100644
--- a/drivers/block/zram/zram_drv.c
+++ b/drivers/block/zram/zram_drv.c
@@ -528,7 +528,7 @@ out_cleanup:
528static inline void update_used_max(struct zram *zram, 528static inline void update_used_max(struct zram *zram,
529 const unsigned long pages) 529 const unsigned long pages)
530{ 530{
531 int old_max, cur_max; 531 unsigned long old_max, cur_max;
532 532
533 old_max = atomic_long_read(&zram->stats.max_used_pages); 533 old_max = atomic_long_read(&zram->stats.max_used_pages);
534 534
diff --git a/drivers/clk/shmobile/Makefile b/drivers/clk/shmobile/Makefile
index 0689d7fb2666..97c71c885e4f 100644
--- a/drivers/clk/shmobile/Makefile
+++ b/drivers/clk/shmobile/Makefile
@@ -2,6 +2,7 @@ obj-$(CONFIG_ARCH_EMEV2) += clk-emev2.o
2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o 2obj-$(CONFIG_ARCH_R7S72100) += clk-rz.o
3obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o 3obj-$(CONFIG_ARCH_R8A73A4) += clk-r8a73a4.o
4obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o 4obj-$(CONFIG_ARCH_R8A7740) += clk-r8a7740.o
5obj-$(CONFIG_ARCH_R8A7778) += clk-r8a7778.o
5obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o 6obj-$(CONFIG_ARCH_R8A7779) += clk-r8a7779.o
6obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o 7obj-$(CONFIG_ARCH_R8A7790) += clk-rcar-gen2.o
7obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o 8obj-$(CONFIG_ARCH_R8A7791) += clk-rcar-gen2.o
diff --git a/drivers/clk/shmobile/clk-r8a7778.c b/drivers/clk/shmobile/clk-r8a7778.c
new file mode 100644
index 000000000000..cb33b57274bf
--- /dev/null
+++ b/drivers/clk/shmobile/clk-r8a7778.c
@@ -0,0 +1,143 @@
1/*
2 * r8a7778 Core CPG Clocks
3 *
4 * Copyright (C) 2014 Ulrich Hecht
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/shmobile.h>
14#include <linux/of_address.h>
15
16struct r8a7778_cpg {
17 struct clk_onecell_data data;
18 spinlock_t lock;
19 void __iomem *reg;
20};
21
22/* PLL multipliers per bits 11, 12, and 18 of MODEMR */
23struct {
24 unsigned long plla_mult;
25 unsigned long pllb_mult;
26} r8a7778_rates[] __initdata = {
27 [0] = { 21, 21 },
28 [1] = { 24, 24 },
29 [2] = { 28, 28 },
30 [3] = { 32, 32 },
31 [5] = { 24, 21 },
32 [6] = { 28, 21 },
33 [7] = { 32, 24 },
34};
35
36/* Clock dividers per bits 1 and 2 of MODEMR */
37struct {
38 const char *name;
39 unsigned int div[4];
40} r8a7778_divs[6] __initdata = {
41 { "b", { 12, 12, 16, 18 } },
42 { "out", { 12, 12, 16, 18 } },
43 { "p", { 16, 12, 16, 12 } },
44 { "s", { 4, 3, 4, 3 } },
45 { "s1", { 8, 6, 8, 6 } },
46};
47
48static u32 cpg_mode_rates __initdata;
49static u32 cpg_mode_divs __initdata;
50
51static struct clk * __init
52r8a7778_cpg_register_clock(struct device_node *np, struct r8a7778_cpg *cpg,
53 const char *name)
54{
55 if (!strcmp(name, "plla")) {
56 return clk_register_fixed_factor(NULL, "plla",
57 of_clk_get_parent_name(np, 0), 0,
58 r8a7778_rates[cpg_mode_rates].plla_mult, 1);
59 } else if (!strcmp(name, "pllb")) {
60 return clk_register_fixed_factor(NULL, "pllb",
61 of_clk_get_parent_name(np, 0), 0,
62 r8a7778_rates[cpg_mode_rates].pllb_mult, 1);
63 } else {
64 unsigned int i;
65
66 for (i = 0; i < ARRAY_SIZE(r8a7778_divs); i++) {
67 if (!strcmp(name, r8a7778_divs[i].name)) {
68 return clk_register_fixed_factor(NULL,
69 r8a7778_divs[i].name,
70 "plla", 0, 1,
71 r8a7778_divs[i].div[cpg_mode_divs]);
72 }
73 }
74 }
75
76 return ERR_PTR(-EINVAL);
77}
78
79
80static void __init r8a7778_cpg_clocks_init(struct device_node *np)
81{
82 struct r8a7778_cpg *cpg;
83 struct clk **clks;
84 unsigned int i;
85 int num_clks;
86
87 num_clks = of_property_count_strings(np, "clock-output-names");
88 if (num_clks < 0) {
89 pr_err("%s: failed to count clocks\n", __func__);
90 return;
91 }
92
93 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
94 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
95 if (cpg == NULL || clks == NULL) {
96 /* We're leaking memory on purpose, there's no point in cleaning
97 * up as the system won't boot anyway.
98 */
99 return;
100 }
101
102 spin_lock_init(&cpg->lock);
103
104 cpg->data.clks = clks;
105 cpg->data.clk_num = num_clks;
106
107 cpg->reg = of_iomap(np, 0);
108 if (WARN_ON(cpg->reg == NULL))
109 return;
110
111 for (i = 0; i < num_clks; ++i) {
112 const char *name;
113 struct clk *clk;
114
115 of_property_read_string_index(np, "clock-output-names", i,
116 &name);
117
118 clk = r8a7778_cpg_register_clock(np, cpg, name);
119 if (IS_ERR(clk))
120 pr_err("%s: failed to register %s %s clock (%ld)\n",
121 __func__, np->name, name, PTR_ERR(clk));
122 else
123 cpg->data.clks[i] = clk;
124 }
125
126 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
127}
128
129CLK_OF_DECLARE(r8a7778_cpg_clks, "renesas,r8a7778-cpg-clocks",
130 r8a7778_cpg_clocks_init);
131
132void __init r8a7778_clocks_init(u32 mode)
133{
134 BUG_ON(!(mode & BIT(19)));
135
136 cpg_mode_rates = (!!(mode & BIT(18)) << 2) |
137 (!!(mode & BIT(12)) << 1) |
138 (!!(mode & BIT(11)));
139 cpg_mode_divs = (!!(mode & BIT(2)) << 1) |
140 (!!(mode & BIT(1)));
141
142 of_clk_init(NULL);
143}
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index 1c2506f68122..68161f7a07d6 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -63,6 +63,11 @@ config VT8500_TIMER
63config CADENCE_TTC_TIMER 63config CADENCE_TTC_TIMER
64 bool 64 bool
65 65
66config ASM9260_TIMER
67 bool
68 select CLKSRC_MMIO
69 select CLKSRC_OF
70
66config CLKSRC_NOMADIK_MTU 71config CLKSRC_NOMADIK_MTU
67 bool 72 bool
68 depends on (ARCH_NOMADIK || ARCH_U8500) 73 depends on (ARCH_NOMADIK || ARCH_U8500)
@@ -245,15 +250,4 @@ config CLKSRC_PXA
245 help 250 help
246 This enables OST0 support available on PXA and SA-11x0 251 This enables OST0 support available on PXA and SA-11x0
247 platforms. 252 platforms.
248
249config ASM9260_TIMER
250 bool "Alphascale ASM9260 timer driver"
251 depends on GENERIC_CLOCKEVENTS
252 select CLKSRC_MMIO
253 select CLKSRC_OF
254 default y if MACH_ASM9260
255 help
256 This enables build of a clocksource and clockevent driver for
257 the 32-bit System Timer hardware available on a Alphascale ASM9260.
258
259endmenu 253endmenu
diff --git a/drivers/clocksource/mtk_timer.c b/drivers/clocksource/mtk_timer.c
index 32a3d25795d3..68ab42356d0e 100644
--- a/drivers/clocksource/mtk_timer.c
+++ b/drivers/clocksource/mtk_timer.c
@@ -224,6 +224,8 @@ static void __init mtk_timer_init(struct device_node *node)
224 } 224 }
225 rate = clk_get_rate(clk); 225 rate = clk_get_rate(clk);
226 226
227 mtk_timer_global_reset(evt);
228
227 if (request_irq(evt->dev.irq, mtk_timer_interrupt, 229 if (request_irq(evt->dev.irq, mtk_timer_interrupt,
228 IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) { 230 IRQF_TIMER | IRQF_IRQPOLL, "mtk_timer", evt)) {
229 pr_warn("failed to setup irq %d\n", evt->dev.irq); 231 pr_warn("failed to setup irq %d\n", evt->dev.irq);
@@ -232,8 +234,6 @@ static void __init mtk_timer_init(struct device_node *node)
232 234
233 evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); 235 evt->ticks_per_jiffy = DIV_ROUND_UP(rate, HZ);
234 236
235 mtk_timer_global_reset(evt);
236
237 /* Configure clock source */ 237 /* Configure clock source */
238 mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN); 238 mtk_timer_setup(evt, GPT_CLK_SRC, TIMER_CTRL_OP_FREERUN);
239 clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC), 239 clocksource_mmio_init(evt->gpt_base + TIMER_CNT_REG(GPT_CLK_SRC),
@@ -241,10 +241,11 @@ static void __init mtk_timer_init(struct device_node *node)
241 241
242 /* Configure clock event */ 242 /* Configure clock event */
243 mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT); 243 mtk_timer_setup(evt, GPT_CLK_EVT, TIMER_CTRL_OP_REPEAT);
244 mtk_timer_enable_irq(evt, GPT_CLK_EVT);
245
246 clockevents_config_and_register(&evt->dev, rate, 0x3, 244 clockevents_config_and_register(&evt->dev, rate, 0x3,
247 0xffffffff); 245 0xffffffff);
246
247 mtk_timer_enable_irq(evt, GPT_CLK_EVT);
248
248 return; 249 return;
249 250
250err_clk_disable: 251err_clk_disable:
diff --git a/drivers/clocksource/pxa_timer.c b/drivers/clocksource/pxa_timer.c
index 941f3f344e08..d9438af2bbd6 100644
--- a/drivers/clocksource/pxa_timer.c
+++ b/drivers/clocksource/pxa_timer.c
@@ -163,7 +163,7 @@ static struct irqaction pxa_ost0_irq = {
163 .dev_id = &ckevt_pxa_osmr0, 163 .dev_id = &ckevt_pxa_osmr0,
164}; 164};
165 165
166static void pxa_timer_common_init(int irq, unsigned long clock_tick_rate) 166static void __init pxa_timer_common_init(int irq, unsigned long clock_tick_rate)
167{ 167{
168 timer_writel(0, OIER); 168 timer_writel(0, OIER);
169 timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR); 169 timer_writel(OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3, OSSR);
diff --git a/drivers/gpio/gpio-tps65912.c b/drivers/gpio/gpio-tps65912.c
index 472fb5b8779f..9cdbc0c9cb2d 100644
--- a/drivers/gpio/gpio-tps65912.c
+++ b/drivers/gpio/gpio-tps65912.c
@@ -26,9 +26,12 @@ struct tps65912_gpio_data {
26 struct gpio_chip gpio_chip; 26 struct gpio_chip gpio_chip;
27}; 27};
28 28
29#define to_tgd(gc) container_of(gc, struct tps65912_gpio_data, gpio_chip)
30
29static int tps65912_gpio_get(struct gpio_chip *gc, unsigned offset) 31static int tps65912_gpio_get(struct gpio_chip *gc, unsigned offset)
30{ 32{
31 struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio); 33 struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc);
34 struct tps65912 *tps65912 = tps65912_gpio->tps65912;
32 int val; 35 int val;
33 36
34 val = tps65912_reg_read(tps65912, TPS65912_GPIO1 + offset); 37 val = tps65912_reg_read(tps65912, TPS65912_GPIO1 + offset);
@@ -42,7 +45,8 @@ static int tps65912_gpio_get(struct gpio_chip *gc, unsigned offset)
42static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset, 45static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset,
43 int value) 46 int value)
44{ 47{
45 struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio); 48 struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc);
49 struct tps65912 *tps65912 = tps65912_gpio->tps65912;
46 50
47 if (value) 51 if (value)
48 tps65912_set_bits(tps65912, TPS65912_GPIO1 + offset, 52 tps65912_set_bits(tps65912, TPS65912_GPIO1 + offset,
@@ -55,7 +59,8 @@ static void tps65912_gpio_set(struct gpio_chip *gc, unsigned offset,
55static int tps65912_gpio_output(struct gpio_chip *gc, unsigned offset, 59static int tps65912_gpio_output(struct gpio_chip *gc, unsigned offset,
56 int value) 60 int value)
57{ 61{
58 struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio); 62 struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc);
63 struct tps65912 *tps65912 = tps65912_gpio->tps65912;
59 64
60 /* Set the initial value */ 65 /* Set the initial value */
61 tps65912_gpio_set(gc, offset, value); 66 tps65912_gpio_set(gc, offset, value);
@@ -66,7 +71,8 @@ static int tps65912_gpio_output(struct gpio_chip *gc, unsigned offset,
66 71
67static int tps65912_gpio_input(struct gpio_chip *gc, unsigned offset) 72static int tps65912_gpio_input(struct gpio_chip *gc, unsigned offset)
68{ 73{
69 struct tps65912 *tps65912 = container_of(gc, struct tps65912, gpio); 74 struct tps65912_gpio_data *tps65912_gpio = to_tgd(gc);
75 struct tps65912 *tps65912 = tps65912_gpio->tps65912;
70 76
71 return tps65912_clear_bits(tps65912, TPS65912_GPIO1 + offset, 77 return tps65912_clear_bits(tps65912, TPS65912_GPIO1 + offset,
72 GPIO_CFG_MASK); 78 GPIO_CFG_MASK);
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index 8cad8e400b44..4650bf830d6b 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -46,12 +46,13 @@ static int of_gpiochip_find_and_xlate(struct gpio_chip *gc, void *data)
46 46
47 ret = gc->of_xlate(gc, &gg_data->gpiospec, gg_data->flags); 47 ret = gc->of_xlate(gc, &gg_data->gpiospec, gg_data->flags);
48 if (ret < 0) { 48 if (ret < 0) {
49 /* We've found the gpio chip, but the translation failed. 49 /* We've found a gpio chip, but the translation failed.
50 * Return true to stop looking and return the translation 50 * Store translation error in out_gpio.
51 * error via out_gpio 51 * Return false to keep looking, as more than one gpio chip
52 * could be registered per of-node.
52 */ 53 */
53 gg_data->out_gpio = ERR_PTR(ret); 54 gg_data->out_gpio = ERR_PTR(ret);
54 return true; 55 return false;
55 } 56 }
56 57
57 gg_data->out_gpio = gpiochip_get_desc(gc, ret); 58 gg_data->out_gpio = gpiochip_get_desc(gc, ret);
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
index b3589d0e39b9..910ff8ab9c9c 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
@@ -62,12 +62,18 @@ enum KFD_MQD_TYPE get_mqd_type_from_queue_type(enum kfd_queue_type type)
62 return KFD_MQD_TYPE_CP; 62 return KFD_MQD_TYPE_CP;
63} 63}
64 64
65static inline unsigned int get_first_pipe(struct device_queue_manager *dqm) 65unsigned int get_first_pipe(struct device_queue_manager *dqm)
66{ 66{
67 BUG_ON(!dqm); 67 BUG_ON(!dqm || !dqm->dev);
68 return dqm->dev->shared_resources.first_compute_pipe; 68 return dqm->dev->shared_resources.first_compute_pipe;
69} 69}
70 70
71unsigned int get_pipes_num(struct device_queue_manager *dqm)
72{
73 BUG_ON(!dqm || !dqm->dev);
74 return dqm->dev->shared_resources.compute_pipe_count;
75}
76
71static inline unsigned int get_pipes_num_cpsch(void) 77static inline unsigned int get_pipes_num_cpsch(void)
72{ 78{
73 return PIPE_PER_ME_CP_SCHEDULING; 79 return PIPE_PER_ME_CP_SCHEDULING;
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
index d64f86cda34f..488f51d19427 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.h
@@ -163,6 +163,8 @@ void program_sh_mem_settings(struct device_queue_manager *dqm,
163 struct qcm_process_device *qpd); 163 struct qcm_process_device *qpd);
164int init_pipelines(struct device_queue_manager *dqm, 164int init_pipelines(struct device_queue_manager *dqm,
165 unsigned int pipes_num, unsigned int first_pipe); 165 unsigned int pipes_num, unsigned int first_pipe);
166unsigned int get_first_pipe(struct device_queue_manager *dqm);
167unsigned int get_pipes_num(struct device_queue_manager *dqm);
166 168
167extern inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd) 169extern inline unsigned int get_sh_mem_bases_32(struct kfd_process_device *pdd)
168{ 170{
@@ -175,10 +177,4 @@ get_sh_mem_bases_nybble_64(struct kfd_process_device *pdd)
175 return (pdd->lds_base >> 60) & 0x0E; 177 return (pdd->lds_base >> 60) & 0x0E;
176} 178}
177 179
178extern inline unsigned int get_pipes_num(struct device_queue_manager *dqm)
179{
180 BUG_ON(!dqm || !dqm->dev);
181 return dqm->dev->shared_resources.compute_pipe_count;
182}
183
184#endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */ 180#endif /* KFD_DEVICE_QUEUE_MANAGER_H_ */
diff --git a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
index 6b072466e2a6..5469efe0523e 100644
--- a/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
+++ b/drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager_cik.c
@@ -131,5 +131,5 @@ static int register_process_cik(struct device_queue_manager *dqm,
131 131
132static int initialize_cpsch_cik(struct device_queue_manager *dqm) 132static int initialize_cpsch_cik(struct device_queue_manager *dqm)
133{ 133{
134 return init_pipelines(dqm, get_pipes_num(dqm), 0); 134 return init_pipelines(dqm, get_pipes_num(dqm), get_first_pipe(dqm));
135} 135}
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
index 0409b907de5d..b3e3068c6ec0 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_crtc.c
@@ -153,7 +153,7 @@ static int atmel_hlcdc_crtc_mode_set(struct drm_crtc *c,
153 (adj->crtc_hdisplay - 1) | 153 (adj->crtc_hdisplay - 1) |
154 ((adj->crtc_vdisplay - 1) << 16)); 154 ((adj->crtc_vdisplay - 1) << 16));
155 155
156 cfg = ATMEL_HLCDC_CLKPOL; 156 cfg = 0;
157 157
158 prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); 158 prate = clk_get_rate(crtc->dc->hlcdc->sys_clk);
159 mode_rate = mode->crtc_clock * 1000; 159 mode_rate = mode->crtc_clock * 1000;
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
index 7320a6c6613f..c1cb17493e0d 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_dc.c
@@ -311,8 +311,6 @@ static int atmel_hlcdc_dc_load(struct drm_device *dev)
311 311
312 pm_runtime_enable(dev->dev); 312 pm_runtime_enable(dev->dev);
313 313
314 pm_runtime_put_sync(dev->dev);
315
316 ret = atmel_hlcdc_dc_modeset_init(dev); 314 ret = atmel_hlcdc_dc_modeset_init(dev);
317 if (ret < 0) { 315 if (ret < 0) {
318 dev_err(dev->dev, "failed to initialize mode setting\n"); 316 dev_err(dev->dev, "failed to initialize mode setting\n");
diff --git a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
index 063d2a7b941f..e79bd9ba474b 100644
--- a/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
+++ b/drivers/gpu/drm/atmel-hlcdc/atmel_hlcdc_layer.c
@@ -311,7 +311,8 @@ int atmel_hlcdc_layer_disable(struct atmel_hlcdc_layer *layer)
311 311
312 /* Disable the layer */ 312 /* Disable the layer */
313 regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR, 313 regmap_write(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_CHDR,
314 ATMEL_HLCDC_LAYER_RST); 314 ATMEL_HLCDC_LAYER_RST | ATMEL_HLCDC_LAYER_A2Q |
315 ATMEL_HLCDC_LAYER_UPDATE);
315 316
316 /* Clear all pending interrupts */ 317 /* Clear all pending interrupts */
317 regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR, &isr); 318 regmap_read(regmap, desc->regs_offset + ATMEL_HLCDC_LAYER_ISR, &isr);
diff --git a/drivers/gpu/drm/drm_crtc.c b/drivers/gpu/drm/drm_crtc.c
index 6b00173d1be4..6b6b07ff720b 100644
--- a/drivers/gpu/drm/drm_crtc.c
+++ b/drivers/gpu/drm/drm_crtc.c
@@ -2127,7 +2127,6 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
2127 DRM_DEBUG_KMS("[CONNECTOR:%d:?]\n", out_resp->connector_id); 2127 DRM_DEBUG_KMS("[CONNECTOR:%d:?]\n", out_resp->connector_id);
2128 2128
2129 mutex_lock(&dev->mode_config.mutex); 2129 mutex_lock(&dev->mode_config.mutex);
2130 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2131 2130
2132 connector = drm_connector_find(dev, out_resp->connector_id); 2131 connector = drm_connector_find(dev, out_resp->connector_id);
2133 if (!connector) { 2132 if (!connector) {
@@ -2157,6 +2156,8 @@ int drm_mode_getconnector(struct drm_device *dev, void *data,
2157 out_resp->mm_height = connector->display_info.height_mm; 2156 out_resp->mm_height = connector->display_info.height_mm;
2158 out_resp->subpixel = connector->display_info.subpixel_order; 2157 out_resp->subpixel = connector->display_info.subpixel_order;
2159 out_resp->connection = connector->status; 2158 out_resp->connection = connector->status;
2159
2160 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
2160 encoder = drm_connector_get_encoder(connector); 2161 encoder = drm_connector_get_encoder(connector);
2161 if (encoder) 2162 if (encoder)
2162 out_resp->encoder_id = encoder->base.id; 2163 out_resp->encoder_id = encoder->base.id;
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f2a825e39646..8727086cf48c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2114,6 +2114,9 @@ void i915_gem_track_fb(struct drm_i915_gem_object *old,
2114 * number comparisons on buffer last_read|write_seqno. It also allows an 2114 * number comparisons on buffer last_read|write_seqno. It also allows an
2115 * emission time to be associated with the request for tracking how far ahead 2115 * emission time to be associated with the request for tracking how far ahead
2116 * of the GPU the submission is. 2116 * of the GPU the submission is.
2117 *
2118 * The requests are reference counted, so upon creation they should have an
2119 * initial reference taken using kref_init
2117 */ 2120 */
2118struct drm_i915_gem_request { 2121struct drm_i915_gem_request {
2119 struct kref ref; 2122 struct kref ref;
@@ -2137,7 +2140,16 @@ struct drm_i915_gem_request {
2137 /** Position in the ringbuffer of the end of the whole request */ 2140 /** Position in the ringbuffer of the end of the whole request */
2138 u32 tail; 2141 u32 tail;
2139 2142
2140 /** Context related to this request */ 2143 /**
2144 * Context related to this request
2145 * Contexts are refcounted, so when this request is associated with a
2146 * context, we must increment the context's refcount, to guarantee that
2147 * it persists while any request is linked to it. Requests themselves
2148 * are also refcounted, so the request will only be freed when the last
2149 * reference to it is dismissed, and the code in
2150 * i915_gem_request_free() will then decrement the refcount on the
2151 * context.
2152 */
2141 struct intel_context *ctx; 2153 struct intel_context *ctx;
2142 2154
2143 /** Batch buffer related to this request if any */ 2155 /** Batch buffer related to this request if any */
@@ -2374,6 +2386,7 @@ struct drm_i915_cmd_table {
2374 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00) 2386 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2375#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \ 2387#define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2376 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \ 2388 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2389 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2377 (INTEL_DEVID(dev) & 0xf) == 0xe)) 2390 (INTEL_DEVID(dev) & 0xf) == 0xe))
2378#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \ 2391#define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2379 (INTEL_DEVID(dev) & 0x00F0) == 0x0020) 2392 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index c26d36cc4b31..e5daad5f75fb 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2659,8 +2659,7 @@ static void i915_gem_reset_ring_cleanup(struct drm_i915_private *dev_priv,
2659 if (submit_req->ctx != ring->default_context) 2659 if (submit_req->ctx != ring->default_context)
2660 intel_lr_context_unpin(ring, submit_req->ctx); 2660 intel_lr_context_unpin(ring, submit_req->ctx);
2661 2661
2662 i915_gem_context_unreference(submit_req->ctx); 2662 i915_gem_request_unreference(submit_req);
2663 kfree(submit_req);
2664 } 2663 }
2665 2664
2666 /* 2665 /*
diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index a2045848bd1a..9c6f93ec886b 100644
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -485,10 +485,8 @@ i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
485 stolen_offset, gtt_offset, size); 485 stolen_offset, gtt_offset, size);
486 486
487 /* KISS and expect everything to be page-aligned */ 487 /* KISS and expect everything to be page-aligned */
488 BUG_ON(stolen_offset & 4095); 488 if (WARN_ON(size == 0) || WARN_ON(size & 4095) ||
489 BUG_ON(size & 4095); 489 WARN_ON(stolen_offset & 4095))
490
491 if (WARN_ON(size == 0))
492 return NULL; 490 return NULL;
493 491
494 stolen = kzalloc(sizeof(*stolen), GFP_KERNEL); 492 stolen = kzalloc(sizeof(*stolen), GFP_KERNEL);
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c
index 7a24bd1a51f6..6377b22269ad 100644
--- a/drivers/gpu/drm/i915/i915_gem_tiling.c
+++ b/drivers/gpu/drm/i915/i915_gem_tiling.c
@@ -335,9 +335,10 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
335 return -EINVAL; 335 return -EINVAL;
336 } 336 }
337 337
338 mutex_lock(&dev->struct_mutex);
338 if (i915_gem_obj_is_pinned(obj) || obj->framebuffer_references) { 339 if (i915_gem_obj_is_pinned(obj) || obj->framebuffer_references) {
339 drm_gem_object_unreference_unlocked(&obj->base); 340 ret = -EBUSY;
340 return -EBUSY; 341 goto err;
341 } 342 }
342 343
343 if (args->tiling_mode == I915_TILING_NONE) { 344 if (args->tiling_mode == I915_TILING_NONE) {
@@ -369,7 +370,6 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
369 } 370 }
370 } 371 }
371 372
372 mutex_lock(&dev->struct_mutex);
373 if (args->tiling_mode != obj->tiling_mode || 373 if (args->tiling_mode != obj->tiling_mode ||
374 args->stride != obj->stride) { 374 args->stride != obj->stride) {
375 /* We need to rebind the object if its current allocation 375 /* We need to rebind the object if its current allocation
@@ -424,6 +424,7 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
424 obj->bit_17 = NULL; 424 obj->bit_17 = NULL;
425 } 425 }
426 426
427err:
427 drm_gem_object_unreference(&obj->base); 428 drm_gem_object_unreference(&obj->base);
428 mutex_unlock(&dev->struct_mutex); 429 mutex_unlock(&dev->struct_mutex);
429 430
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4145d95902f5..ede5bbbd8a08 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1892,6 +1892,9 @@ static irqreturn_t valleyview_irq_handler(int irq, void *arg)
1892 u32 iir, gt_iir, pm_iir; 1892 u32 iir, gt_iir, pm_iir;
1893 irqreturn_t ret = IRQ_NONE; 1893 irqreturn_t ret = IRQ_NONE;
1894 1894
1895 if (!intel_irqs_enabled(dev_priv))
1896 return IRQ_NONE;
1897
1895 while (true) { 1898 while (true) {
1896 /* Find, clear, then process each source of interrupt */ 1899 /* Find, clear, then process each source of interrupt */
1897 1900
@@ -1936,6 +1939,9 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1936 u32 master_ctl, iir; 1939 u32 master_ctl, iir;
1937 irqreturn_t ret = IRQ_NONE; 1940 irqreturn_t ret = IRQ_NONE;
1938 1941
1942 if (!intel_irqs_enabled(dev_priv))
1943 return IRQ_NONE;
1944
1939 for (;;) { 1945 for (;;) {
1940 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; 1946 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1941 iir = I915_READ(VLV_IIR); 1947 iir = I915_READ(VLV_IIR);
@@ -2208,6 +2214,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
2208 u32 de_iir, gt_iir, de_ier, sde_ier = 0; 2214 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
2209 irqreturn_t ret = IRQ_NONE; 2215 irqreturn_t ret = IRQ_NONE;
2210 2216
2217 if (!intel_irqs_enabled(dev_priv))
2218 return IRQ_NONE;
2219
2211 /* We get interrupts on unclaimed registers, so check for this before we 2220 /* We get interrupts on unclaimed registers, so check for this before we
2212 * do any I915_{READ,WRITE}. */ 2221 * do any I915_{READ,WRITE}. */
2213 intel_uncore_check_errors(dev); 2222 intel_uncore_check_errors(dev);
@@ -2279,6 +2288,9 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
2279 enum pipe pipe; 2288 enum pipe pipe;
2280 u32 aux_mask = GEN8_AUX_CHANNEL_A; 2289 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2281 2290
2291 if (!intel_irqs_enabled(dev_priv))
2292 return IRQ_NONE;
2293
2282 if (IS_GEN9(dev)) 2294 if (IS_GEN9(dev))
2283 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | 2295 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2284 GEN9_AUX_CHANNEL_D; 2296 GEN9_AUX_CHANNEL_D;
@@ -3771,6 +3783,9 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg)
3771 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 3783 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3772 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3784 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3773 3785
3786 if (!intel_irqs_enabled(dev_priv))
3787 return IRQ_NONE;
3788
3774 iir = I915_READ16(IIR); 3789 iir = I915_READ16(IIR);
3775 if (iir == 0) 3790 if (iir == 0)
3776 return IRQ_NONE; 3791 return IRQ_NONE;
@@ -3951,6 +3966,9 @@ static irqreturn_t i915_irq_handler(int irq, void *arg)
3951 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 3966 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3952 int pipe, ret = IRQ_NONE; 3967 int pipe, ret = IRQ_NONE;
3953 3968
3969 if (!intel_irqs_enabled(dev_priv))
3970 return IRQ_NONE;
3971
3954 iir = I915_READ(IIR); 3972 iir = I915_READ(IIR);
3955 do { 3973 do {
3956 bool irq_received = (iir & ~flip_mask) != 0; 3974 bool irq_received = (iir & ~flip_mask) != 0;
@@ -4171,6 +4189,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg)
4171 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT | 4189 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4172 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT; 4190 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
4173 4191
4192 if (!intel_irqs_enabled(dev_priv))
4193 return IRQ_NONE;
4194
4174 iir = I915_READ(IIR); 4195 iir = I915_READ(IIR);
4175 4196
4176 for (;;) { 4197 for (;;) {
@@ -4520,6 +4541,7 @@ void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
4520{ 4541{
4521 dev_priv->dev->driver->irq_uninstall(dev_priv->dev); 4542 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
4522 dev_priv->pm.irqs_enabled = false; 4543 dev_priv->pm.irqs_enabled = false;
4544 synchronize_irq(dev_priv->dev->irq);
4523} 4545}
4524 4546
4525/** 4547/**
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3d220a67f865..e730789b53b7 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2371,13 +2371,19 @@ intel_alloc_plane_obj(struct intel_crtc *crtc,
2371 struct drm_device *dev = crtc->base.dev; 2371 struct drm_device *dev = crtc->base.dev;
2372 struct drm_i915_gem_object *obj = NULL; 2372 struct drm_i915_gem_object *obj = NULL;
2373 struct drm_mode_fb_cmd2 mode_cmd = { 0 }; 2373 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2374 u32 base = plane_config->base; 2374 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2375 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2376 PAGE_SIZE);
2377
2378 size_aligned -= base_aligned;
2375 2379
2376 if (plane_config->size == 0) 2380 if (plane_config->size == 0)
2377 return false; 2381 return false;
2378 2382
2379 obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, 2383 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2380 plane_config->size); 2384 base_aligned,
2385 base_aligned,
2386 size_aligned);
2381 if (!obj) 2387 if (!obj)
2382 return false; 2388 return false;
2383 2389
@@ -2725,10 +2731,19 @@ static void skylake_update_primary_plane(struct drm_crtc *crtc,
2725 case DRM_FORMAT_XRGB8888: 2731 case DRM_FORMAT_XRGB8888:
2726 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; 2732 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2727 break; 2733 break;
2734 case DRM_FORMAT_ARGB8888:
2735 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2736 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2737 break;
2728 case DRM_FORMAT_XBGR8888: 2738 case DRM_FORMAT_XBGR8888:
2729 plane_ctl |= PLANE_CTL_ORDER_RGBX; 2739 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2730 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888; 2740 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2731 break; 2741 break;
2742 case DRM_FORMAT_ABGR8888:
2743 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2744 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2745 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2746 break;
2732 case DRM_FORMAT_XRGB2101010: 2747 case DRM_FORMAT_XRGB2101010:
2733 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010; 2748 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2734 break; 2749 break;
@@ -6627,7 +6642,7 @@ i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6627 aligned_height = intel_fb_align_height(dev, fb->height, 6642 aligned_height = intel_fb_align_height(dev, fb->height,
6628 plane_config->tiling); 6643 plane_config->tiling);
6629 6644
6630 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height); 6645 plane_config->size = fb->pitches[0] * aligned_height;
6631 6646
6632 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 6647 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6633 pipe_name(pipe), plane, fb->width, fb->height, 6648 pipe_name(pipe), plane, fb->width, fb->height,
@@ -7664,7 +7679,7 @@ skylake_get_initial_plane_config(struct intel_crtc *crtc,
7664 aligned_height = intel_fb_align_height(dev, fb->height, 7679 aligned_height = intel_fb_align_height(dev, fb->height,
7665 plane_config->tiling); 7680 plane_config->tiling);
7666 7681
7667 plane_config->size = ALIGN(fb->pitches[0] * aligned_height, PAGE_SIZE); 7682 plane_config->size = fb->pitches[0] * aligned_height;
7668 7683
7669 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 7684 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7670 pipe_name(pipe), fb->width, fb->height, 7685 pipe_name(pipe), fb->width, fb->height,
@@ -7755,7 +7770,7 @@ ironlake_get_initial_plane_config(struct intel_crtc *crtc,
7755 aligned_height = intel_fb_align_height(dev, fb->height, 7770 aligned_height = intel_fb_align_height(dev, fb->height,
7756 plane_config->tiling); 7771 plane_config->tiling);
7757 7772
7758 plane_config->size = PAGE_ALIGN(fb->pitches[0] * aligned_height); 7773 plane_config->size = fb->pitches[0] * aligned_height;
7759 7774
7760 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", 7775 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7761 pipe_name(pipe), fb->width, fb->height, 7776 pipe_name(pipe), fb->width, fb->height,
@@ -8698,6 +8713,7 @@ retry:
8698 old->release_fb->funcs->destroy(old->release_fb); 8713 old->release_fb->funcs->destroy(old->release_fb);
8699 goto fail; 8714 goto fail;
8700 } 8715 }
8716 crtc->primary->crtc = crtc;
8701 8717
8702 /* let the connector get through one full cycle before testing */ 8718 /* let the connector get through one full cycle before testing */
8703 intel_wait_for_vblank(dev, intel_crtc->pipe); 8719 intel_wait_for_vblank(dev, intel_crtc->pipe);
@@ -12182,9 +12198,6 @@ intel_check_cursor_plane(struct drm_plane *plane,
12182 return -ENOMEM; 12198 return -ENOMEM;
12183 } 12199 }
12184 12200
12185 if (fb == crtc->cursor->fb)
12186 return 0;
12187
12188 /* we only need to pin inside GTT if cursor is non-phy */ 12201 /* we only need to pin inside GTT if cursor is non-phy */
12189 mutex_lock(&dev->struct_mutex); 12202 mutex_lock(&dev->struct_mutex);
12190 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) { 12203 if (!INTEL_INFO(dev)->cursor_needs_physical && obj->tiling_mode) {
@@ -13096,6 +13109,9 @@ static struct intel_quirk intel_quirks[] = {
13096 13109
13097 /* HP Chromebook 14 (Celeron 2955U) */ 13110 /* HP Chromebook 14 (Celeron 2955U) */
13098 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, 13111 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
13112
13113 /* Dell Chromebook 11 */
13114 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
13099}; 13115};
13100 13116
13101static void intel_init_quirks(struct drm_device *dev) 13117static void intel_init_quirks(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 0f358c5999ec..e8d3da9f3373 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -503,18 +503,19 @@ static int execlists_context_queue(struct intel_engine_cs *ring,
503 * If there isn't a request associated with this submission, 503 * If there isn't a request associated with this submission,
504 * create one as a temporary holder. 504 * create one as a temporary holder.
505 */ 505 */
506 WARN(1, "execlist context submission without request");
507 request = kzalloc(sizeof(*request), GFP_KERNEL); 506 request = kzalloc(sizeof(*request), GFP_KERNEL);
508 if (request == NULL) 507 if (request == NULL)
509 return -ENOMEM; 508 return -ENOMEM;
510 request->ring = ring; 509 request->ring = ring;
511 request->ctx = to; 510 request->ctx = to;
511 kref_init(&request->ref);
512 request->uniq = dev_priv->request_uniq++;
513 i915_gem_context_reference(request->ctx);
512 } else { 514 } else {
515 i915_gem_request_reference(request);
513 WARN_ON(to != request->ctx); 516 WARN_ON(to != request->ctx);
514 } 517 }
515 request->tail = tail; 518 request->tail = tail;
516 i915_gem_request_reference(request);
517 i915_gem_context_reference(request->ctx);
518 519
519 intel_runtime_pm_get(dev_priv); 520 intel_runtime_pm_get(dev_priv);
520 521
@@ -731,7 +732,6 @@ void intel_execlists_retire_requests(struct intel_engine_cs *ring)
731 if (ctx_obj && (ctx != ring->default_context)) 732 if (ctx_obj && (ctx != ring->default_context))
732 intel_lr_context_unpin(ring, ctx); 733 intel_lr_context_unpin(ring, ctx);
733 intel_runtime_pm_put(dev_priv); 734 intel_runtime_pm_put(dev_priv);
734 i915_gem_context_unreference(ctx);
735 list_del(&req->execlist_link); 735 list_del(&req->execlist_link);
736 i915_gem_request_unreference(req); 736 i915_gem_request_unreference(req);
737 } 737 }
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 5bf825dfaa09..8d74de82456e 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -178,6 +178,13 @@ radeon_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
178 switch (msg->request & ~DP_AUX_I2C_MOT) { 178 switch (msg->request & ~DP_AUX_I2C_MOT) {
179 case DP_AUX_NATIVE_WRITE: 179 case DP_AUX_NATIVE_WRITE:
180 case DP_AUX_I2C_WRITE: 180 case DP_AUX_I2C_WRITE:
181 /* The atom implementation only supports writes with a max payload of
182 * 12 bytes since it uses 4 bits for the total count (header + payload)
183 * in the parameter space. The atom interface supports 16 byte
184 * payloads for reads. The hw itself supports up to 16 bytes of payload.
185 */
186 if (WARN_ON_ONCE(msg->size > 12))
187 return -E2BIG;
181 /* tx_size needs to be 4 even for bare address packets since the atom 188 /* tx_size needs to be 4 even for bare address packets since the atom
182 * table needs the info in tx_buf[3]. 189 * table needs the info in tx_buf[3].
183 */ 190 */
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 7c9df1eac065..7fe7b749e182 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -731,7 +731,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
731 dig_connector = radeon_connector->con_priv; 731 dig_connector = radeon_connector->con_priv;
732 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) || 732 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
733 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) { 733 (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
734 if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 734 if (radeon_audio != 0 &&
735 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
736 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
735 return ATOM_ENCODER_MODE_DP_AUDIO; 737 return ATOM_ENCODER_MODE_DP_AUDIO;
736 return ATOM_ENCODER_MODE_DP; 738 return ATOM_ENCODER_MODE_DP;
737 } else if (radeon_audio != 0) { 739 } else if (radeon_audio != 0) {
@@ -747,7 +749,9 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
747 } 749 }
748 break; 750 break;
749 case DRM_MODE_CONNECTOR_eDP: 751 case DRM_MODE_CONNECTOR_eDP:
750 if (radeon_audio != 0 && ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev)) 752 if (radeon_audio != 0 &&
753 drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
754 ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
751 return ATOM_ENCODER_MODE_DP_AUDIO; 755 return ATOM_ENCODER_MODE_DP_AUDIO;
752 return ATOM_ENCODER_MODE_DP; 756 return ATOM_ENCODER_MODE_DP;
753 case DRM_MODE_CONNECTOR_DVIA: 757 case DRM_MODE_CONNECTOR_DVIA:
@@ -1720,8 +1724,10 @@ radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1720 } 1724 }
1721 1725
1722 encoder_mode = atombios_get_encoder_mode(encoder); 1726 encoder_mode = atombios_get_encoder_mode(encoder);
1723 if (radeon_audio != 0 && 1727 if (connector && (radeon_audio != 0) &&
1724 (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode))) 1728 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1729 (ENCODER_MODE_IS_DP(encoder_mode) &&
1730 drm_detect_monitor_audio(radeon_connector_edid(connector)))))
1725 radeon_audio_dpms(encoder, mode); 1731 radeon_audio_dpms(encoder, mode);
1726} 1732}
1727 1733
@@ -2136,6 +2142,7 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2136 struct drm_device *dev = encoder->dev; 2142 struct drm_device *dev = encoder->dev;
2137 struct radeon_device *rdev = dev->dev_private; 2143 struct radeon_device *rdev = dev->dev_private;
2138 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); 2144 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2145 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2139 int encoder_mode; 2146 int encoder_mode;
2140 2147
2141 radeon_encoder->pixel_clock = adjusted_mode->clock; 2148 radeon_encoder->pixel_clock = adjusted_mode->clock;
@@ -2164,8 +2171,10 @@ radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2164 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA: 2171 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2165 /* handled in dpms */ 2172 /* handled in dpms */
2166 encoder_mode = atombios_get_encoder_mode(encoder); 2173 encoder_mode = atombios_get_encoder_mode(encoder);
2167 if (radeon_audio != 0 && 2174 if (connector && (radeon_audio != 0) &&
2168 (encoder_mode == ATOM_ENCODER_MODE_HDMI || ENCODER_MODE_IS_DP(encoder_mode))) 2175 ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2176 (ENCODER_MODE_IS_DP(encoder_mode) &&
2177 drm_detect_monitor_audio(radeon_connector_edid(connector)))))
2169 radeon_audio_mode_set(encoder, adjusted_mode); 2178 radeon_audio_mode_set(encoder, adjusted_mode);
2170 break; 2179 break;
2171 case ENCODER_OBJECT_ID_INTERNAL_DDI: 2180 case ENCODER_OBJECT_ID_INTERNAL_DDI:
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e6a4ba236c70..0c993da9c8fb 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3613,6 +3613,8 @@ static void cik_gpu_init(struct radeon_device *rdev)
3613 } 3613 }
3614 3614
3615 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 3615 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3616 WREG32(SRBM_INT_CNTL, 0x1);
3617 WREG32(SRBM_INT_ACK, 0x1);
3616 3618
3617 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN); 3619 WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
3618 3620
@@ -7230,6 +7232,8 @@ static void cik_disable_interrupt_state(struct radeon_device *rdev)
7230 WREG32(CP_ME2_PIPE3_INT_CNTL, 0); 7232 WREG32(CP_ME2_PIPE3_INT_CNTL, 0);
7231 /* grbm */ 7233 /* grbm */
7232 WREG32(GRBM_INT_CNTL, 0); 7234 WREG32(GRBM_INT_CNTL, 0);
7235 /* SRBM */
7236 WREG32(SRBM_INT_CNTL, 0);
7233 /* vline/vblank, etc. */ 7237 /* vline/vblank, etc. */
7234 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 7238 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
7235 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 7239 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -8046,6 +8050,10 @@ restart_ih:
8046 break; 8050 break;
8047 } 8051 }
8048 break; 8052 break;
8053 case 96:
8054 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
8055 WREG32(SRBM_INT_ACK, 0x1);
8056 break;
8049 case 124: /* UVD */ 8057 case 124: /* UVD */
8050 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 8058 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
8051 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 8059 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 03003f8a6de6..c648e1996dab 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -482,6 +482,10 @@
482#define SOFT_RESET_ORB (1 << 23) 482#define SOFT_RESET_ORB (1 << 23)
483#define SOFT_RESET_VCE (1 << 24) 483#define SOFT_RESET_VCE (1 << 24)
484 484
485#define SRBM_READ_ERROR 0xE98
486#define SRBM_INT_CNTL 0xEA0
487#define SRBM_INT_ACK 0xEA8
488
485#define VM_L2_CNTL 0x1400 489#define VM_L2_CNTL 0x1400
486#define ENABLE_L2_CACHE (1 << 0) 490#define ENABLE_L2_CACHE (1 << 0)
487#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 491#define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 78600f534c80..4c0e24b3bb90 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -3253,6 +3253,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
3253 } 3253 }
3254 3254
3255 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 3255 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3256 WREG32(SRBM_INT_CNTL, 0x1);
3257 WREG32(SRBM_INT_ACK, 0x1);
3256 3258
3257 evergreen_fix_pci_max_read_req_size(rdev); 3259 evergreen_fix_pci_max_read_req_size(rdev);
3258 3260
@@ -4324,6 +4326,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
4324 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; 4326 tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE;
4325 WREG32(DMA_CNTL, tmp); 4327 WREG32(DMA_CNTL, tmp);
4326 WREG32(GRBM_INT_CNTL, 0); 4328 WREG32(GRBM_INT_CNTL, 0);
4329 WREG32(SRBM_INT_CNTL, 0);
4327 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 4330 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
4328 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 4331 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
4329 if (rdev->num_crtc >= 4) { 4332 if (rdev->num_crtc >= 4) {
@@ -5066,6 +5069,10 @@ restart_ih:
5066 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); 5069 DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data);
5067 break; 5070 break;
5068 } 5071 }
5072 case 96:
5073 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
5074 WREG32(SRBM_INT_ACK, 0x1);
5075 break;
5069 case 124: /* UVD */ 5076 case 124: /* UVD */
5070 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 5077 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
5071 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 5078 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h
index ee83d2a88750..a8d1d5240fcb 100644
--- a/drivers/gpu/drm/radeon/evergreend.h
+++ b/drivers/gpu/drm/radeon/evergreend.h
@@ -1191,6 +1191,10 @@
1191#define SOFT_RESET_REGBB (1 << 22) 1191#define SOFT_RESET_REGBB (1 << 22)
1192#define SOFT_RESET_ORB (1 << 23) 1192#define SOFT_RESET_ORB (1 << 23)
1193 1193
1194#define SRBM_READ_ERROR 0xE98
1195#define SRBM_INT_CNTL 0xEA0
1196#define SRBM_INT_ACK 0xEA8
1197
1194/* display watermarks */ 1198/* display watermarks */
1195#define DC_LB_MEMORY_SPLIT 0x6b0c 1199#define DC_LB_MEMORY_SPLIT 0x6b0c
1196#define PRIORITY_A_CNT 0x6b18 1200#define PRIORITY_A_CNT 0x6b18
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 24242a7f0ac3..dab00812abaa 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -962,6 +962,8 @@ static void cayman_gpu_init(struct radeon_device *rdev)
962 } 962 }
963 963
964 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 964 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
965 WREG32(SRBM_INT_CNTL, 0x1);
966 WREG32(SRBM_INT_ACK, 0x1);
965 967
966 evergreen_fix_pci_max_read_req_size(rdev); 968 evergreen_fix_pci_max_read_req_size(rdev);
967 969
@@ -1086,12 +1088,12 @@ static void cayman_gpu_init(struct radeon_device *rdev)
1086 1088
1087 if ((rdev->config.cayman.max_backends_per_se == 1) && 1089 if ((rdev->config.cayman.max_backends_per_se == 1) &&
1088 (rdev->flags & RADEON_IS_IGP)) { 1090 (rdev->flags & RADEON_IS_IGP)) {
1089 if ((disabled_rb_mask & 3) == 1) { 1091 if ((disabled_rb_mask & 3) == 2) {
1090 /* RB0 disabled, RB1 enabled */
1091 tmp = 0x11111111;
1092 } else {
1093 /* RB1 disabled, RB0 enabled */ 1092 /* RB1 disabled, RB0 enabled */
1094 tmp = 0x00000000; 1093 tmp = 0x00000000;
1094 } else {
1095 /* RB0 disabled, RB1 enabled */
1096 tmp = 0x11111111;
1095 } 1097 }
1096 } else { 1098 } else {
1097 tmp = gb_addr_config & NUM_PIPES_MASK; 1099 tmp = gb_addr_config & NUM_PIPES_MASK;
diff --git a/drivers/gpu/drm/radeon/nid.h b/drivers/gpu/drm/radeon/nid.h
index ad7125486894..6b44580440d0 100644
--- a/drivers/gpu/drm/radeon/nid.h
+++ b/drivers/gpu/drm/radeon/nid.h
@@ -82,6 +82,10 @@
82#define SOFT_RESET_REGBB (1 << 22) 82#define SOFT_RESET_REGBB (1 << 22)
83#define SOFT_RESET_ORB (1 << 23) 83#define SOFT_RESET_ORB (1 << 23)
84 84
85#define SRBM_READ_ERROR 0xE98
86#define SRBM_INT_CNTL 0xEA0
87#define SRBM_INT_ACK 0xEA8
88
85#define SRBM_STATUS2 0x0EC4 89#define SRBM_STATUS2 0x0EC4
86#define DMA_BUSY (1 << 5) 90#define DMA_BUSY (1 << 5)
87#define DMA1_BUSY (1 << 6) 91#define DMA1_BUSY (1 << 6)
diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c
index 843b65f46ece..fa2154493cf1 100644
--- a/drivers/gpu/drm/radeon/r600_dpm.c
+++ b/drivers/gpu/drm/radeon/r600_dpm.c
@@ -188,7 +188,7 @@ u32 r600_dpm_get_vrefresh(struct radeon_device *rdev)
188 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { 188 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
189 radeon_crtc = to_radeon_crtc(crtc); 189 radeon_crtc = to_radeon_crtc(crtc);
190 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) { 190 if (crtc->enabled && radeon_crtc->enabled && radeon_crtc->hw_mode.clock) {
191 vrefresh = radeon_crtc->hw_mode.vrefresh; 191 vrefresh = drm_mode_vrefresh(&radeon_crtc->hw_mode);
192 break; 192 break;
193 } 193 }
194 } 194 }
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index c830863bc98a..a579ed379f20 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -715,6 +715,7 @@ int radeon_cs_packet_parse(struct radeon_cs_parser *p,
715 struct radeon_cs_chunk *ib_chunk = p->chunk_ib; 715 struct radeon_cs_chunk *ib_chunk = p->chunk_ib;
716 struct radeon_device *rdev = p->rdev; 716 struct radeon_device *rdev = p->rdev;
717 uint32_t header; 717 uint32_t header;
718 int ret = 0, i;
718 719
719 if (idx >= ib_chunk->length_dw) { 720 if (idx >= ib_chunk->length_dw) {
720 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", 721 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
@@ -743,14 +744,25 @@ int radeon_cs_packet_parse(struct radeon_cs_parser *p,
743 break; 744 break;
744 default: 745 default:
745 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx); 746 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
746 return -EINVAL; 747 ret = -EINVAL;
748 goto dump_ib;
747 } 749 }
748 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) { 750 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
749 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", 751 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
750 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw); 752 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
751 return -EINVAL; 753 ret = -EINVAL;
754 goto dump_ib;
752 } 755 }
753 return 0; 756 return 0;
757
758dump_ib:
759 for (i = 0; i < ib_chunk->length_dw; i++) {
760 if (i == idx)
761 printk("\t0x%08x <---\n", radeon_get_ib_value(p, i));
762 else
763 printk("\t0x%08x\n", radeon_get_ib_value(p, i));
764 }
765 return ret;
754} 766}
755 767
756/** 768/**
diff --git a/drivers/gpu/drm/radeon/radeon_encoders.c b/drivers/gpu/drm/radeon/radeon_encoders.c
index 6b670b0bc47b..3a297037cc17 100644
--- a/drivers/gpu/drm/radeon/radeon_encoders.c
+++ b/drivers/gpu/drm/radeon/radeon_encoders.c
@@ -179,9 +179,12 @@ static void radeon_encoder_add_backlight(struct radeon_encoder *radeon_encoder,
179 (rdev->pdev->subsystem_vendor == 0x1734) && 179 (rdev->pdev->subsystem_vendor == 0x1734) &&
180 (rdev->pdev->subsystem_device == 0x1107)) 180 (rdev->pdev->subsystem_device == 0x1107))
181 use_bl = false; 181 use_bl = false;
182/* Older PPC macs use on-GPU backlight controller */
183#ifndef CONFIG_PPC_PMAC
182 /* disable native backlight control on older asics */ 184 /* disable native backlight control on older asics */
183 else if (rdev->family < CHIP_R600) 185 else if (rdev->family < CHIP_R600)
184 use_bl = false; 186 use_bl = false;
187#endif
185 else 188 else
186 use_bl = true; 189 use_bl = true;
187 } 190 }
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 9f758d39420d..33cf4108386d 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -852,6 +852,12 @@ static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
852 single_display = false; 852 single_display = false;
853 } 853 }
854 854
855 /* 120hz tends to be problematic even if they are under the
856 * vblank limit.
857 */
858 if (single_display && (r600_dpm_get_vrefresh(rdev) >= 120))
859 single_display = false;
860
855 /* certain older asics have a separare 3D performance state, 861 /* certain older asics have a separare 3D performance state,
856 * so try that first if the user selected performance 862 * so try that first if the user selected performance
857 */ 863 */
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 73107fe9e46f..bcf516a8a2f1 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3162,6 +3162,8 @@ static void si_gpu_init(struct radeon_device *rdev)
3162 } 3162 }
3163 3163
3164 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); 3164 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
3165 WREG32(SRBM_INT_CNTL, 1);
3166 WREG32(SRBM_INT_ACK, 1);
3165 3167
3166 evergreen_fix_pci_max_read_req_size(rdev); 3168 evergreen_fix_pci_max_read_req_size(rdev);
3167 3169
@@ -4699,12 +4701,6 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4699 switch (pkt.type) { 4701 switch (pkt.type) {
4700 case RADEON_PACKET_TYPE0: 4702 case RADEON_PACKET_TYPE0:
4701 dev_err(rdev->dev, "Packet0 not allowed!\n"); 4703 dev_err(rdev->dev, "Packet0 not allowed!\n");
4702 for (i = 0; i < ib->length_dw; i++) {
4703 if (i == idx)
4704 printk("\t0x%08x <---\n", ib->ptr[i]);
4705 else
4706 printk("\t0x%08x\n", ib->ptr[i]);
4707 }
4708 ret = -EINVAL; 4704 ret = -EINVAL;
4709 break; 4705 break;
4710 case RADEON_PACKET_TYPE2: 4706 case RADEON_PACKET_TYPE2:
@@ -4736,8 +4732,15 @@ int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib)
4736 ret = -EINVAL; 4732 ret = -EINVAL;
4737 break; 4733 break;
4738 } 4734 }
4739 if (ret) 4735 if (ret) {
4736 for (i = 0; i < ib->length_dw; i++) {
4737 if (i == idx)
4738 printk("\t0x%08x <---\n", ib->ptr[i]);
4739 else
4740 printk("\t0x%08x\n", ib->ptr[i]);
4741 }
4740 break; 4742 break;
4743 }
4741 } while (idx < ib->length_dw); 4744 } while (idx < ib->length_dw);
4742 4745
4743 return ret; 4746 return ret;
@@ -5910,6 +5913,7 @@ static void si_disable_interrupt_state(struct radeon_device *rdev)
5910 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE; 5913 tmp = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET) & ~TRAP_ENABLE;
5911 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp); 5914 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, tmp);
5912 WREG32(GRBM_INT_CNTL, 0); 5915 WREG32(GRBM_INT_CNTL, 0);
5916 WREG32(SRBM_INT_CNTL, 0);
5913 if (rdev->num_crtc >= 2) { 5917 if (rdev->num_crtc >= 2) {
5914 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 5918 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
5915 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 5919 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
@@ -6609,6 +6613,10 @@ restart_ih:
6609 break; 6613 break;
6610 } 6614 }
6611 break; 6615 break;
6616 case 96:
6617 DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR));
6618 WREG32(SRBM_INT_ACK, 0x1);
6619 break;
6612 case 124: /* UVD */ 6620 case 124: /* UVD */
6613 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); 6621 DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data);
6614 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); 6622 radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX);
diff --git a/drivers/gpu/drm/radeon/sid.h b/drivers/gpu/drm/radeon/sid.h
index cbd91d226f3c..c27118cab16a 100644
--- a/drivers/gpu/drm/radeon/sid.h
+++ b/drivers/gpu/drm/radeon/sid.h
@@ -358,6 +358,10 @@
358#define CC_SYS_RB_BACKEND_DISABLE 0xe80 358#define CC_SYS_RB_BACKEND_DISABLE 0xe80
359#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 359#define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84
360 360
361#define SRBM_READ_ERROR 0xE98
362#define SRBM_INT_CNTL 0xEA0
363#define SRBM_INT_ACK 0xEA8
364
361#define SRBM_STATUS2 0x0EC4 365#define SRBM_STATUS2 0x0EC4
362#define DMA_BUSY (1 << 5) 366#define DMA_BUSY (1 << 5)
363#define DMA1_BUSY (1 << 6) 367#define DMA1_BUSY (1 << 6)
diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c
index 3aaa84ae2681..1a52522f5da7 100644
--- a/drivers/gpu/drm/tegra/dc.c
+++ b/drivers/gpu/drm/tegra/dc.c
@@ -997,8 +997,10 @@ static void tegra_crtc_reset(struct drm_crtc *crtc)
997 crtc->state = NULL; 997 crtc->state = NULL;
998 998
999 state = kzalloc(sizeof(*state), GFP_KERNEL); 999 state = kzalloc(sizeof(*state), GFP_KERNEL);
1000 if (state) 1000 if (state) {
1001 crtc->state = &state->base; 1001 crtc->state = &state->base;
1002 crtc->state->crtc = crtc;
1003 }
1002} 1004}
1003 1005
1004static struct drm_crtc_state * 1006static struct drm_crtc_state *
@@ -1012,6 +1014,7 @@ tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
1012 return NULL; 1014 return NULL;
1013 1015
1014 copy->base.mode_changed = false; 1016 copy->base.mode_changed = false;
1017 copy->base.active_changed = false;
1015 copy->base.planes_changed = false; 1018 copy->base.planes_changed = false;
1016 copy->base.event = NULL; 1019 copy->base.event = NULL;
1017 1020
@@ -1227,9 +1230,6 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
1227 /* program display mode */ 1230 /* program display mode */
1228 tegra_dc_set_timings(dc, mode); 1231 tegra_dc_set_timings(dc, mode);
1229 1232
1230 if (dc->soc->supports_border_color)
1231 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1232
1233 /* interlacing isn't supported yet, so disable it */ 1233 /* interlacing isn't supported yet, so disable it */
1234 if (dc->soc->supports_interlacing) { 1234 if (dc->soc->supports_interlacing) {
1235 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); 1235 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
@@ -1252,42 +1252,7 @@ static void tegra_crtc_mode_set_nofb(struct drm_crtc *crtc)
1252 1252
1253static void tegra_crtc_prepare(struct drm_crtc *crtc) 1253static void tegra_crtc_prepare(struct drm_crtc *crtc)
1254{ 1254{
1255 struct tegra_dc *dc = to_tegra_dc(crtc);
1256 unsigned int syncpt;
1257 unsigned long value;
1258
1259 drm_crtc_vblank_off(crtc); 1255 drm_crtc_vblank_off(crtc);
1260
1261 if (dc->pipe)
1262 syncpt = SYNCPT_VBLANK1;
1263 else
1264 syncpt = SYNCPT_VBLANK0;
1265
1266 /* initialize display controller */
1267 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1268 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1269
1270 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1271 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1272
1273 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1274 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1275 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1276
1277 /* initialize timer */
1278 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1279 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1280 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1281
1282 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1283 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1284 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1285
1286 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1287 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1288
1289 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1290 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1291} 1256}
1292 1257
1293static void tegra_crtc_commit(struct drm_crtc *crtc) 1258static void tegra_crtc_commit(struct drm_crtc *crtc)
@@ -1664,6 +1629,8 @@ static int tegra_dc_init(struct host1x_client *client)
1664 struct tegra_drm *tegra = drm->dev_private; 1629 struct tegra_drm *tegra = drm->dev_private;
1665 struct drm_plane *primary = NULL; 1630 struct drm_plane *primary = NULL;
1666 struct drm_plane *cursor = NULL; 1631 struct drm_plane *cursor = NULL;
1632 unsigned int syncpt;
1633 u32 value;
1667 int err; 1634 int err;
1668 1635
1669 if (tegra->domain) { 1636 if (tegra->domain) {
@@ -1730,6 +1697,40 @@ static int tegra_dc_init(struct host1x_client *client)
1730 goto cleanup; 1697 goto cleanup;
1731 } 1698 }
1732 1699
1700 /* initialize display controller */
1701 if (dc->pipe)
1702 syncpt = SYNCPT_VBLANK1;
1703 else
1704 syncpt = SYNCPT_VBLANK0;
1705
1706 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1707 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
1708
1709 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
1710 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
1711
1712 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
1713 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
1714 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
1715
1716 /* initialize timer */
1717 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
1718 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
1719 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
1720
1721 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
1722 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
1723 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1724
1725 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1726 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
1727
1728 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
1729 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
1730
1731 if (dc->soc->supports_border_color)
1732 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR);
1733
1733 return 0; 1734 return 0;
1734 1735
1735cleanup: 1736cleanup:
diff --git a/drivers/gpu/drm/tegra/hdmi.c b/drivers/gpu/drm/tegra/hdmi.c
index 7e06657ae58b..7eaaee74a039 100644
--- a/drivers/gpu/drm/tegra/hdmi.c
+++ b/drivers/gpu/drm/tegra/hdmi.c
@@ -851,6 +851,14 @@ static void tegra_hdmi_encoder_mode_set(struct drm_encoder *encoder,
851 h_back_porch = mode->htotal - mode->hsync_end; 851 h_back_porch = mode->htotal - mode->hsync_end;
852 h_front_porch = mode->hsync_start - mode->hdisplay; 852 h_front_porch = mode->hsync_start - mode->hdisplay;
853 853
854 err = clk_set_rate(hdmi->clk, pclk);
855 if (err < 0) {
856 dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
857 err);
858 }
859
860 DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
861
854 /* power up sequence */ 862 /* power up sequence */
855 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0); 863 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
856 value &= ~SOR_PLL_PDBG; 864 value &= ~SOR_PLL_PDBG;
diff --git a/drivers/hid/hid-core.c b/drivers/hid/hid-core.c
index db4fb6e1cc5b..7c669c328c4c 100644
--- a/drivers/hid/hid-core.c
+++ b/drivers/hid/hid-core.c
@@ -1872,6 +1872,7 @@ static const struct hid_device_id hid_have_special_driver[] = {
1872 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_SIDEWINDER_GV) }, 1872 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_SIDEWINDER_GV) },
1873 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE4K) }, 1873 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE4K) },
1874 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE4K_JP) }, 1874 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE4K_JP) },
1875 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE7K) },
1875 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_LK6K) }, 1876 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_LK6K) },
1876 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_USB) }, 1877 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_USB) },
1877 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_3K) }, 1878 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_DIGITAL_MEDIA_3K) },
@@ -1926,6 +1927,7 @@ static const struct hid_device_id hid_have_special_driver[] = {
1926#endif 1927#endif
1927#if IS_ENABLED(CONFIG_HID_SAITEK) 1928#if IS_ENABLED(CONFIG_HID_SAITEK)
1928 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_PS1000) }, 1929 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_PS1000) },
1930 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7_OLD) },
1929 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7) }, 1931 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7) },
1930 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_MMO7) }, 1932 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_MMO7) },
1931 { HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT9) }, 1933 { HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT9) },
diff --git a/drivers/hid/hid-ids.h b/drivers/hid/hid-ids.h
index 46edb4d3ed28..204312bfab2c 100644
--- a/drivers/hid/hid-ids.h
+++ b/drivers/hid/hid-ids.h
@@ -654,6 +654,7 @@
654#define USB_DEVICE_ID_MS_LK6K 0x00f9 654#define USB_DEVICE_ID_MS_LK6K 0x00f9
655#define USB_DEVICE_ID_MS_PRESENTER_8K_BT 0x0701 655#define USB_DEVICE_ID_MS_PRESENTER_8K_BT 0x0701
656#define USB_DEVICE_ID_MS_PRESENTER_8K_USB 0x0713 656#define USB_DEVICE_ID_MS_PRESENTER_8K_USB 0x0713
657#define USB_DEVICE_ID_MS_NE7K 0x071d
657#define USB_DEVICE_ID_MS_DIGITAL_MEDIA_3K 0x0730 658#define USB_DEVICE_ID_MS_DIGITAL_MEDIA_3K 0x0730
658#define USB_DEVICE_ID_MS_COMFORT_MOUSE_4500 0x076c 659#define USB_DEVICE_ID_MS_COMFORT_MOUSE_4500 0x076c
659#define USB_DEVICE_ID_MS_SURFACE_PRO_2 0x0799 660#define USB_DEVICE_ID_MS_SURFACE_PRO_2 0x0799
@@ -802,6 +803,7 @@
802#define USB_VENDOR_ID_SAITEK 0x06a3 803#define USB_VENDOR_ID_SAITEK 0x06a3
803#define USB_DEVICE_ID_SAITEK_RUMBLEPAD 0xff17 804#define USB_DEVICE_ID_SAITEK_RUMBLEPAD 0xff17
804#define USB_DEVICE_ID_SAITEK_PS1000 0x0621 805#define USB_DEVICE_ID_SAITEK_PS1000 0x0621
806#define USB_DEVICE_ID_SAITEK_RAT7_OLD 0x0ccb
805#define USB_DEVICE_ID_SAITEK_RAT7 0x0cd7 807#define USB_DEVICE_ID_SAITEK_RAT7 0x0cd7
806#define USB_DEVICE_ID_SAITEK_MMO7 0x0cd0 808#define USB_DEVICE_ID_SAITEK_MMO7 0x0cd0
807 809
diff --git a/drivers/hid/hid-microsoft.c b/drivers/hid/hid-microsoft.c
index fbaea6eb882e..af935eb198c9 100644
--- a/drivers/hid/hid-microsoft.c
+++ b/drivers/hid/hid-microsoft.c
@@ -264,6 +264,8 @@ static const struct hid_device_id ms_devices[] = {
264 .driver_data = MS_ERGONOMY }, 264 .driver_data = MS_ERGONOMY },
265 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE4K_JP), 265 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE4K_JP),
266 .driver_data = MS_ERGONOMY }, 266 .driver_data = MS_ERGONOMY },
267 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_NE7K),
268 .driver_data = MS_ERGONOMY },
267 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_LK6K), 269 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_LK6K),
268 .driver_data = MS_ERGONOMY | MS_RDESC }, 270 .driver_data = MS_ERGONOMY | MS_RDESC },
269 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_USB), 271 { HID_USB_DEVICE(USB_VENDOR_ID_MICROSOFT, USB_DEVICE_ID_MS_PRESENTER_8K_USB),
diff --git a/drivers/hid/hid-saitek.c b/drivers/hid/hid-saitek.c
index 5632c54eadf0..a014f21275d8 100644
--- a/drivers/hid/hid-saitek.c
+++ b/drivers/hid/hid-saitek.c
@@ -177,6 +177,8 @@ static int saitek_event(struct hid_device *hdev, struct hid_field *field,
177static const struct hid_device_id saitek_devices[] = { 177static const struct hid_device_id saitek_devices[] = {
178 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_PS1000), 178 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_PS1000),
179 .driver_data = SAITEK_FIX_PS1000 }, 179 .driver_data = SAITEK_FIX_PS1000 },
180 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7_OLD),
181 .driver_data = SAITEK_RELEASE_MODE_RAT7 },
180 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7), 182 { HID_USB_DEVICE(USB_VENDOR_ID_SAITEK, USB_DEVICE_ID_SAITEK_RAT7),
181 .driver_data = SAITEK_RELEASE_MODE_RAT7 }, 183 .driver_data = SAITEK_RELEASE_MODE_RAT7 },
182 { HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT9), 184 { HID_USB_DEVICE(USB_VENDOR_ID_MADCATZ, USB_DEVICE_ID_MADCATZ_RAT9),
diff --git a/drivers/hid/hid-sensor-hub.c b/drivers/hid/hid-sensor-hub.c
index 6a58b6c723aa..e54ce1097e2c 100644
--- a/drivers/hid/hid-sensor-hub.c
+++ b/drivers/hid/hid-sensor-hub.c
@@ -135,8 +135,9 @@ static struct hid_sensor_hub_callbacks *sensor_hub_get_callback(
135{ 135{
136 struct hid_sensor_hub_callbacks_list *callback; 136 struct hid_sensor_hub_callbacks_list *callback;
137 struct sensor_hub_data *pdata = hid_get_drvdata(hdev); 137 struct sensor_hub_data *pdata = hid_get_drvdata(hdev);
138 unsigned long flags;
138 139
139 spin_lock(&pdata->dyn_callback_lock); 140 spin_lock_irqsave(&pdata->dyn_callback_lock, flags);
140 list_for_each_entry(callback, &pdata->dyn_callback_list, list) 141 list_for_each_entry(callback, &pdata->dyn_callback_list, list)
141 if (callback->usage_id == usage_id && 142 if (callback->usage_id == usage_id &&
142 (collection_index >= 143 (collection_index >=
@@ -145,10 +146,11 @@ static struct hid_sensor_hub_callbacks *sensor_hub_get_callback(
145 callback->hsdev->end_collection_index)) { 146 callback->hsdev->end_collection_index)) {
146 *priv = callback->priv; 147 *priv = callback->priv;
147 *hsdev = callback->hsdev; 148 *hsdev = callback->hsdev;
148 spin_unlock(&pdata->dyn_callback_lock); 149 spin_unlock_irqrestore(&pdata->dyn_callback_lock,
150 flags);
149 return callback->usage_callback; 151 return callback->usage_callback;
150 } 152 }
151 spin_unlock(&pdata->dyn_callback_lock); 153 spin_unlock_irqrestore(&pdata->dyn_callback_lock, flags);
152 154
153 return NULL; 155 return NULL;
154} 156}
diff --git a/drivers/hid/hid-sony.c b/drivers/hid/hid-sony.c
index 31e9d2561106..1896c019e302 100644
--- a/drivers/hid/hid-sony.c
+++ b/drivers/hid/hid-sony.c
@@ -804,7 +804,7 @@ union sixaxis_output_report_01 {
804#define DS4_REPORT_0x81_SIZE 7 804#define DS4_REPORT_0x81_SIZE 7
805#define SIXAXIS_REPORT_0xF2_SIZE 18 805#define SIXAXIS_REPORT_0xF2_SIZE 18
806 806
807static spinlock_t sony_dev_list_lock; 807static DEFINE_SPINLOCK(sony_dev_list_lock);
808static LIST_HEAD(sony_device_list); 808static LIST_HEAD(sony_device_list);
809static DEFINE_IDA(sony_device_id_allocator); 809static DEFINE_IDA(sony_device_id_allocator);
810 810
@@ -1944,6 +1944,8 @@ static int sony_probe(struct hid_device *hdev, const struct hid_device_id *id)
1944 return -ENOMEM; 1944 return -ENOMEM;
1945 } 1945 }
1946 1946
1947 spin_lock_init(&sc->lock);
1948
1947 sc->quirks = quirks; 1949 sc->quirks = quirks;
1948 hid_set_drvdata(hdev, sc); 1950 hid_set_drvdata(hdev, sc);
1949 sc->hdev = hdev; 1951 sc->hdev = hdev;
@@ -2147,8 +2149,8 @@ static void __exit sony_exit(void)
2147{ 2149{
2148 dbg_hid("Sony:%s\n", __func__); 2150 dbg_hid("Sony:%s\n", __func__);
2149 2151
2150 ida_destroy(&sony_device_id_allocator);
2151 hid_unregister_driver(&sony_driver); 2152 hid_unregister_driver(&sony_driver);
2153 ida_destroy(&sony_device_id_allocator);
2152} 2154}
2153module_init(sony_init); 2155module_init(sony_init);
2154module_exit(sony_exit); 2156module_exit(sony_exit);
diff --git a/drivers/hid/i2c-hid/i2c-hid.c b/drivers/hid/i2c-hid/i2c-hid.c
index d43e967e7533..36053f33d6d9 100644
--- a/drivers/hid/i2c-hid/i2c-hid.c
+++ b/drivers/hid/i2c-hid/i2c-hid.c
@@ -370,7 +370,10 @@ static int i2c_hid_hwreset(struct i2c_client *client)
370static void i2c_hid_get_input(struct i2c_hid *ihid) 370static void i2c_hid_get_input(struct i2c_hid *ihid)
371{ 371{
372 int ret, ret_size; 372 int ret, ret_size;
373 int size = ihid->bufsize; 373 int size = le16_to_cpu(ihid->hdesc.wMaxInputLength);
374
375 if (size > ihid->bufsize)
376 size = ihid->bufsize;
374 377
375 ret = i2c_master_recv(ihid->client, ihid->inbuf, size); 378 ret = i2c_master_recv(ihid->client, ihid->inbuf, size);
376 if (ret != size) { 379 if (ret != size) {
@@ -785,7 +788,7 @@ static int i2c_hid_init_irq(struct i2c_client *client)
785 dev_dbg(&client->dev, "Requesting IRQ: %d\n", client->irq); 788 dev_dbg(&client->dev, "Requesting IRQ: %d\n", client->irq);
786 789
787 ret = request_threaded_irq(client->irq, NULL, i2c_hid_irq, 790 ret = request_threaded_irq(client->irq, NULL, i2c_hid_irq,
788 IRQF_TRIGGER_FALLING | IRQF_ONESHOT, 791 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
789 client->name, ihid); 792 client->name, ihid);
790 if (ret < 0) { 793 if (ret < 0) {
791 dev_warn(&client->dev, 794 dev_warn(&client->dev,
diff --git a/drivers/hid/wacom_wac.c b/drivers/hid/wacom_wac.c
index 1a6507999a65..046351cf17f3 100644
--- a/drivers/hid/wacom_wac.c
+++ b/drivers/hid/wacom_wac.c
@@ -778,6 +778,11 @@ static int wacom_intuos_irq(struct wacom_wac *wacom)
778 input_report_abs(input, ABS_X, be16_to_cpup((__be16 *)&data[4])); 778 input_report_abs(input, ABS_X, be16_to_cpup((__be16 *)&data[4]));
779 input_report_abs(input, ABS_Y, be16_to_cpup((__be16 *)&data[6])); 779 input_report_abs(input, ABS_Y, be16_to_cpup((__be16 *)&data[6]));
780 input_report_abs(input, ABS_Z, be16_to_cpup((__be16 *)&data[8])); 780 input_report_abs(input, ABS_Z, be16_to_cpup((__be16 *)&data[8]));
781 if ((data[2] & 0x07) | data[4] | data[5] | data[6] | data[7] | data[8] | data[9]) {
782 input_report_abs(input, ABS_MISC, PAD_DEVICE_ID);
783 } else {
784 input_report_abs(input, ABS_MISC, 0);
785 }
781 } else if (features->type == CINTIQ_HYBRID) { 786 } else if (features->type == CINTIQ_HYBRID) {
782 /* 787 /*
783 * Do not send hardware buttons under Android. They 788 * Do not send hardware buttons under Android. They
@@ -2725,9 +2730,9 @@ static const struct wacom_features wacom_features_0xF6 =
2725 .oVid = USB_VENDOR_ID_WACOM, .oPid = 0xf8, .touch_max = 10, 2730 .oVid = USB_VENDOR_ID_WACOM, .oPid = 0xf8, .touch_max = 10,
2726 .check_for_hid_type = true, .hid_type = HID_TYPE_USBNONE }; 2731 .check_for_hid_type = true, .hid_type = HID_TYPE_USBNONE };
2727static const struct wacom_features wacom_features_0x32A = 2732static const struct wacom_features wacom_features_0x32A =
2728 { "Wacom Cintiq 27QHD", 119740, 67520, 2047, 2733 { "Wacom Cintiq 27QHD", 119740, 67520, 2047, 63,
2729 63, WACOM_27QHD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, 2734 WACOM_27QHD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES,
2730 WACOM_27QHD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES }; 2735 WACOM_CINTIQ_OFFSET, WACOM_CINTIQ_OFFSET };
2731static const struct wacom_features wacom_features_0x32B = 2736static const struct wacom_features wacom_features_0x32B =
2732 { "Wacom Cintiq 27QHD touch", 119740, 67520, 2047, 63, 2737 { "Wacom Cintiq 27QHD touch", 119740, 67520, 2047, 63,
2733 WACOM_27QHD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, 2738 WACOM_27QHD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES,
diff --git a/drivers/hwmon/ads7828.c b/drivers/hwmon/ads7828.c
index bce4e9ff21bf..6c99ee7bafa3 100644
--- a/drivers/hwmon/ads7828.c
+++ b/drivers/hwmon/ads7828.c
@@ -147,6 +147,9 @@ static int ads7828_probe(struct i2c_client *client,
147 &ads2830_regmap_config); 147 &ads2830_regmap_config);
148 } 148 }
149 149
150 if (IS_ERR(data->regmap))
151 return PTR_ERR(data->regmap);
152
150 data->cmd_byte = ext_vref ? ADS7828_CMD_PD1 : ADS7828_CMD_PD3; 153 data->cmd_byte = ext_vref ? ADS7828_CMD_PD1 : ADS7828_CMD_PD3;
151 if (!diff_input) 154 if (!diff_input)
152 data->cmd_byte |= ADS7828_CMD_SD_SE; 155 data->cmd_byte |= ADS7828_CMD_SD_SE;
diff --git a/drivers/md/md.c b/drivers/md/md.c
index c8d2bac4e28b..cadf9cc02b25 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -2555,7 +2555,7 @@ state_store(struct md_rdev *rdev, const char *buf, size_t len)
2555 return err ? err : len; 2555 return err ? err : len;
2556} 2556}
2557static struct rdev_sysfs_entry rdev_state = 2557static struct rdev_sysfs_entry rdev_state =
2558__ATTR(state, S_IRUGO|S_IWUSR, state_show, state_store); 2558__ATTR_PREALLOC(state, S_IRUGO|S_IWUSR, state_show, state_store);
2559 2559
2560static ssize_t 2560static ssize_t
2561errors_show(struct md_rdev *rdev, char *page) 2561errors_show(struct md_rdev *rdev, char *page)
@@ -3638,7 +3638,8 @@ resync_start_store(struct mddev *mddev, const char *buf, size_t len)
3638 return err ?: len; 3638 return err ?: len;
3639} 3639}
3640static struct md_sysfs_entry md_resync_start = 3640static struct md_sysfs_entry md_resync_start =
3641__ATTR(resync_start, S_IRUGO|S_IWUSR, resync_start_show, resync_start_store); 3641__ATTR_PREALLOC(resync_start, S_IRUGO|S_IWUSR,
3642 resync_start_show, resync_start_store);
3642 3643
3643/* 3644/*
3644 * The array state can be: 3645 * The array state can be:
@@ -3851,7 +3852,7 @@ array_state_store(struct mddev *mddev, const char *buf, size_t len)
3851 return err ?: len; 3852 return err ?: len;
3852} 3853}
3853static struct md_sysfs_entry md_array_state = 3854static struct md_sysfs_entry md_array_state =
3854__ATTR(array_state, S_IRUGO|S_IWUSR, array_state_show, array_state_store); 3855__ATTR_PREALLOC(array_state, S_IRUGO|S_IWUSR, array_state_show, array_state_store);
3855 3856
3856static ssize_t 3857static ssize_t
3857max_corrected_read_errors_show(struct mddev *mddev, char *page) { 3858max_corrected_read_errors_show(struct mddev *mddev, char *page) {
@@ -4101,7 +4102,7 @@ out_unlock:
4101} 4102}
4102 4103
4103static struct md_sysfs_entry md_metadata = 4104static struct md_sysfs_entry md_metadata =
4104__ATTR(metadata_version, S_IRUGO|S_IWUSR, metadata_show, metadata_store); 4105__ATTR_PREALLOC(metadata_version, S_IRUGO|S_IWUSR, metadata_show, metadata_store);
4105 4106
4106static ssize_t 4107static ssize_t
4107action_show(struct mddev *mddev, char *page) 4108action_show(struct mddev *mddev, char *page)
@@ -4189,7 +4190,7 @@ action_store(struct mddev *mddev, const char *page, size_t len)
4189} 4190}
4190 4191
4191static struct md_sysfs_entry md_scan_mode = 4192static struct md_sysfs_entry md_scan_mode =
4192__ATTR(sync_action, S_IRUGO|S_IWUSR, action_show, action_store); 4193__ATTR_PREALLOC(sync_action, S_IRUGO|S_IWUSR, action_show, action_store);
4193 4194
4194static ssize_t 4195static ssize_t
4195last_sync_action_show(struct mddev *mddev, char *page) 4196last_sync_action_show(struct mddev *mddev, char *page)
@@ -4335,7 +4336,8 @@ sync_completed_show(struct mddev *mddev, char *page)
4335 return sprintf(page, "%llu / %llu\n", resync, max_sectors); 4336 return sprintf(page, "%llu / %llu\n", resync, max_sectors);
4336} 4337}
4337 4338
4338static struct md_sysfs_entry md_sync_completed = __ATTR_RO(sync_completed); 4339static struct md_sysfs_entry md_sync_completed =
4340 __ATTR_PREALLOC(sync_completed, S_IRUGO, sync_completed_show, NULL);
4339 4341
4340static ssize_t 4342static ssize_t
4341min_sync_show(struct mddev *mddev, char *page) 4343min_sync_show(struct mddev *mddev, char *page)
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index 4153da5d4011..d34e238afa54 100644
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
@@ -560,7 +560,7 @@ static int read_balance(struct r1conf *conf, struct r1bio *r1_bio, int *max_sect
560 if (test_bit(WriteMostly, &rdev->flags)) { 560 if (test_bit(WriteMostly, &rdev->flags)) {
561 /* Don't balance among write-mostly, just 561 /* Don't balance among write-mostly, just
562 * use the first as a last resort */ 562 * use the first as a last resort */
563 if (best_disk < 0) { 563 if (best_dist_disk < 0) {
564 if (is_badblock(rdev, this_sector, sectors, 564 if (is_badblock(rdev, this_sector, sectors,
565 &first_bad, &bad_sectors)) { 565 &first_bad, &bad_sectors)) {
566 if (first_bad < this_sector) 566 if (first_bad < this_sector)
@@ -569,7 +569,8 @@ static int read_balance(struct r1conf *conf, struct r1bio *r1_bio, int *max_sect
569 best_good_sectors = first_bad - this_sector; 569 best_good_sectors = first_bad - this_sector;
570 } else 570 } else
571 best_good_sectors = sectors; 571 best_good_sectors = sectors;
572 best_disk = disk; 572 best_dist_disk = disk;
573 best_pending_disk = disk;
573 } 574 }
574 continue; 575 continue;
575 } 576 }
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index e75d48c0421a..cd2f96b2c572 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -5121,12 +5121,17 @@ static inline sector_t sync_request(struct mddev *mddev, sector_t sector_nr, int
5121 schedule_timeout_uninterruptible(1); 5121 schedule_timeout_uninterruptible(1);
5122 } 5122 }
5123 /* Need to check if array will still be degraded after recovery/resync 5123 /* Need to check if array will still be degraded after recovery/resync
5124 * We don't need to check the 'failed' flag as when that gets set, 5124 * Note in case of > 1 drive failures it's possible we're rebuilding
5125 * recovery aborts. 5125 * one drive while leaving another faulty drive in array.
5126 */ 5126 */
5127 for (i = 0; i < conf->raid_disks; i++) 5127 rcu_read_lock();
5128 if (conf->disks[i].rdev == NULL) 5128 for (i = 0; i < conf->raid_disks; i++) {
5129 struct md_rdev *rdev = ACCESS_ONCE(conf->disks[i].rdev);
5130
5131 if (rdev == NULL || test_bit(Faulty, &rdev->flags))
5129 still_degraded = 1; 5132 still_degraded = 1;
5133 }
5134 rcu_read_unlock();
5130 5135
5131 bitmap_start_sync(mddev->bitmap, sector_nr, &sync_blocks, still_degraded); 5136 bitmap_start_sync(mddev->bitmap, sector_nr, &sync_blocks, still_degraded);
5132 5137
diff --git a/drivers/rtc/rtc-ds1685.c b/drivers/rtc/rtc-ds1685.c
index 8c3bfcb115b7..803869c7d7c2 100644
--- a/drivers/rtc/rtc-ds1685.c
+++ b/drivers/rtc/rtc-ds1685.c
@@ -399,21 +399,21 @@ ds1685_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *alrm)
399 * of this RTC chip. We check for it anyways in case support is 399 * of this RTC chip. We check for it anyways in case support is
400 * added in the future. 400 * added in the future.
401 */ 401 */
402 if (unlikely((seconds >= 0xc0) && (seconds <= 0xff))) 402 if (unlikely(seconds >= 0xc0))
403 alrm->time.tm_sec = -1; 403 alrm->time.tm_sec = -1;
404 else 404 else
405 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds, 405 alrm->time.tm_sec = ds1685_rtc_bcd2bin(rtc, seconds,
406 RTC_SECS_BCD_MASK, 406 RTC_SECS_BCD_MASK,
407 RTC_SECS_BIN_MASK); 407 RTC_SECS_BIN_MASK);
408 408
409 if (unlikely((minutes >= 0xc0) && (minutes <= 0xff))) 409 if (unlikely(minutes >= 0xc0))
410 alrm->time.tm_min = -1; 410 alrm->time.tm_min = -1;
411 else 411 else
412 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes, 412 alrm->time.tm_min = ds1685_rtc_bcd2bin(rtc, minutes,
413 RTC_MINS_BCD_MASK, 413 RTC_MINS_BCD_MASK,
414 RTC_MINS_BIN_MASK); 414 RTC_MINS_BIN_MASK);
415 415
416 if (unlikely((hours >= 0xc0) && (hours <= 0xff))) 416 if (unlikely(hours >= 0xc0))
417 alrm->time.tm_hour = -1; 417 alrm->time.tm_hour = -1;
418 else 418 else
419 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours, 419 alrm->time.tm_hour = ds1685_rtc_bcd2bin(rtc, hours,
@@ -472,13 +472,13 @@ ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
472 * field, and we only support four fields. We put the support 472 * field, and we only support four fields. We put the support
473 * here anyways for the future. 473 * here anyways for the future.
474 */ 474 */
475 if (unlikely((seconds >= 0xc0) && (seconds <= 0xff))) 475 if (unlikely(seconds >= 0xc0))
476 seconds = 0xff; 476 seconds = 0xff;
477 477
478 if (unlikely((minutes >= 0xc0) && (minutes <= 0xff))) 478 if (unlikely(minutes >= 0xc0))
479 minutes = 0xff; 479 minutes = 0xff;
480 480
481 if (unlikely((hours >= 0xc0) && (hours <= 0xff))) 481 if (unlikely(hours >= 0xc0))
482 hours = 0xff; 482 hours = 0xff;
483 483
484 alrm->time.tm_mon = -1; 484 alrm->time.tm_mon = -1;
@@ -528,7 +528,6 @@ ds1685_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alrm)
528/* ----------------------------------------------------------------------- */ 528/* ----------------------------------------------------------------------- */
529/* /dev/rtcX Interface functions */ 529/* /dev/rtcX Interface functions */
530 530
531#ifdef CONFIG_RTC_INTF_DEV
532/** 531/**
533 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off. 532 * ds1685_rtc_alarm_irq_enable - replaces ioctl() RTC_AIE on/off.
534 * @dev: pointer to device structure. 533 * @dev: pointer to device structure.
@@ -557,7 +556,6 @@ ds1685_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
557 556
558 return 0; 557 return 0;
559} 558}
560#endif
561/* ----------------------------------------------------------------------- */ 559/* ----------------------------------------------------------------------- */
562 560
563 561
@@ -1612,7 +1610,7 @@ ds1685_rtc_sysfs_time_regs_show(struct device *dev,
1612 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false); 1610 ds1685_rtc_sysfs_time_regs_lookup(attr->attr.name, false);
1613 1611
1614 /* Make sure we actually matched something. */ 1612 /* Make sure we actually matched something. */
1615 if (!bcd_reg_info && !bin_reg_info) 1613 if (!bcd_reg_info || !bin_reg_info)
1616 return -EINVAL; 1614 return -EINVAL;
1617 1615
1618 /* bcd_reg_info->reg == bin_reg_info->reg. */ 1616 /* bcd_reg_info->reg == bin_reg_info->reg. */
@@ -1650,7 +1648,7 @@ ds1685_rtc_sysfs_time_regs_store(struct device *dev,
1650 return -EINVAL; 1648 return -EINVAL;
1651 1649
1652 /* Make sure we actually matched something. */ 1650 /* Make sure we actually matched something. */
1653 if (!bcd_reg_info && !bin_reg_info) 1651 if (!bcd_reg_info || !bin_reg_info)
1654 return -EINVAL; 1652 return -EINVAL;
1655 1653
1656 /* Check for a valid range. */ 1654 /* Check for a valid range. */
diff --git a/drivers/sh/pm_runtime.c b/drivers/sh/pm_runtime.c
index f3ee439d6f0e..cd4c293f0dd0 100644
--- a/drivers/sh/pm_runtime.c
+++ b/drivers/sh/pm_runtime.c
@@ -81,7 +81,9 @@ static int __init sh_pm_runtime_init(void)
81 if (!of_machine_is_compatible("renesas,emev2") && 81 if (!of_machine_is_compatible("renesas,emev2") &&
82 !of_machine_is_compatible("renesas,r7s72100") && 82 !of_machine_is_compatible("renesas,r7s72100") &&
83 !of_machine_is_compatible("renesas,r8a73a4") && 83 !of_machine_is_compatible("renesas,r8a73a4") &&
84#ifndef CONFIG_PM_GENERIC_DOMAINS_OF
84 !of_machine_is_compatible("renesas,r8a7740") && 85 !of_machine_is_compatible("renesas,r8a7740") &&
86#endif
85 !of_machine_is_compatible("renesas,r8a7778") && 87 !of_machine_is_compatible("renesas,r8a7778") &&
86 !of_machine_is_compatible("renesas,r8a7779") && 88 !of_machine_is_compatible("renesas,r8a7779") &&
87 !of_machine_is_compatible("renesas,r8a7790") && 89 !of_machine_is_compatible("renesas,r8a7790") &&
diff --git a/drivers/thermal/int340x_thermal/int3400_thermal.c b/drivers/thermal/int340x_thermal/int3400_thermal.c
index 25d244cbbe8f..031018e7a65b 100644
--- a/drivers/thermal/int340x_thermal/int3400_thermal.c
+++ b/drivers/thermal/int340x_thermal/int3400_thermal.c
@@ -262,13 +262,12 @@ static int int3400_thermal_probe(struct platform_device *pdev)
262 result = acpi_parse_art(priv->adev->handle, &priv->art_count, 262 result = acpi_parse_art(priv->adev->handle, &priv->art_count,
263 &priv->arts, true); 263 &priv->arts, true);
264 if (result) 264 if (result)
265 goto free_priv; 265 dev_dbg(&pdev->dev, "_ART table parsing error\n");
266
267 266
268 result = acpi_parse_trt(priv->adev->handle, &priv->trt_count, 267 result = acpi_parse_trt(priv->adev->handle, &priv->trt_count,
269 &priv->trts, true); 268 &priv->trts, true);
270 if (result) 269 if (result)
271 goto free_art; 270 dev_dbg(&pdev->dev, "_TRT table parsing error\n");
272 271
273 platform_set_drvdata(pdev, priv); 272 platform_set_drvdata(pdev, priv);
274 273
@@ -281,7 +280,7 @@ static int int3400_thermal_probe(struct platform_device *pdev)
281 &int3400_thermal_params, 0, 0); 280 &int3400_thermal_params, 0, 0);
282 if (IS_ERR(priv->thermal)) { 281 if (IS_ERR(priv->thermal)) {
283 result = PTR_ERR(priv->thermal); 282 result = PTR_ERR(priv->thermal);
284 goto free_trt; 283 goto free_art_trt;
285 } 284 }
286 285
287 priv->rel_misc_dev_res = acpi_thermal_rel_misc_device_add( 286 priv->rel_misc_dev_res = acpi_thermal_rel_misc_device_add(
@@ -295,9 +294,8 @@ static int int3400_thermal_probe(struct platform_device *pdev)
295 294
296free_zone: 295free_zone:
297 thermal_zone_device_unregister(priv->thermal); 296 thermal_zone_device_unregister(priv->thermal);
298free_trt: 297free_art_trt:
299 kfree(priv->trts); 298 kfree(priv->trts);
300free_art:
301 kfree(priv->arts); 299 kfree(priv->arts);
302free_priv: 300free_priv:
303 kfree(priv); 301 kfree(priv);
diff --git a/drivers/thermal/intel_powerclamp.c b/drivers/thermal/intel_powerclamp.c
index 6ceebd659dd4..12623bc02f46 100644
--- a/drivers/thermal/intel_powerclamp.c
+++ b/drivers/thermal/intel_powerclamp.c
@@ -688,6 +688,7 @@ static const struct x86_cpu_id intel_powerclamp_ids[] = {
688 { X86_VENDOR_INTEL, 6, 0x45}, 688 { X86_VENDOR_INTEL, 6, 0x45},
689 { X86_VENDOR_INTEL, 6, 0x46}, 689 { X86_VENDOR_INTEL, 6, 0x46},
690 { X86_VENDOR_INTEL, 6, 0x4c}, 690 { X86_VENDOR_INTEL, 6, 0x4c},
691 { X86_VENDOR_INTEL, 6, 0x4d},
691 { X86_VENDOR_INTEL, 6, 0x56}, 692 { X86_VENDOR_INTEL, 6, 0x56},
692 {} 693 {}
693}; 694};
diff --git a/drivers/thermal/rcar_thermal.c b/drivers/thermal/rcar_thermal.c
index 2580a4872f90..fe4e767018c4 100644
--- a/drivers/thermal/rcar_thermal.c
+++ b/drivers/thermal/rcar_thermal.c
@@ -387,21 +387,9 @@ static int rcar_thermal_probe(struct platform_device *pdev)
387 387
388 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 388 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
389 if (irq) { 389 if (irq) {
390 int ret;
391
392 /* 390 /*
393 * platform has IRQ support. 391 * platform has IRQ support.
394 * Then, driver uses common registers 392 * Then, driver uses common registers
395 */
396
397 ret = devm_request_irq(dev, irq->start, rcar_thermal_irq, 0,
398 dev_name(dev), common);
399 if (ret) {
400 dev_err(dev, "irq request failed\n ");
401 return ret;
402 }
403
404 /*
405 * rcar_has_irq_support() will be enabled 393 * rcar_has_irq_support() will be enabled
406 */ 394 */
407 res = platform_get_resource(pdev, IORESOURCE_MEM, mres++); 395 res = platform_get_resource(pdev, IORESOURCE_MEM, mres++);
@@ -456,8 +444,16 @@ static int rcar_thermal_probe(struct platform_device *pdev)
456 } 444 }
457 445
458 /* enable temperature comparation */ 446 /* enable temperature comparation */
459 if (irq) 447 if (irq) {
448 ret = devm_request_irq(dev, irq->start, rcar_thermal_irq, 0,
449 dev_name(dev), common);
450 if (ret) {
451 dev_err(dev, "irq request failed\n ");
452 goto error_unregister;
453 }
454
460 rcar_thermal_common_write(common, ENR, enr_bits); 455 rcar_thermal_common_write(common, ENR, enr_bits);
456 }
461 457
462 platform_set_drvdata(pdev, common); 458 platform_set_drvdata(pdev, common);
463 459
@@ -467,9 +463,9 @@ static int rcar_thermal_probe(struct platform_device *pdev)
467 463
468error_unregister: 464error_unregister:
469 rcar_thermal_for_each_priv(priv, common) { 465 rcar_thermal_for_each_priv(priv, common) {
470 thermal_zone_device_unregister(priv->zone);
471 if (rcar_has_irq_support(priv)) 466 if (rcar_has_irq_support(priv))
472 rcar_thermal_irq_disable(priv); 467 rcar_thermal_irq_disable(priv);
468 thermal_zone_device_unregister(priv->zone);
473 } 469 }
474 470
475 pm_runtime_put(dev); 471 pm_runtime_put(dev);
@@ -485,9 +481,9 @@ static int rcar_thermal_remove(struct platform_device *pdev)
485 struct rcar_thermal_priv *priv; 481 struct rcar_thermal_priv *priv;
486 482
487 rcar_thermal_for_each_priv(priv, common) { 483 rcar_thermal_for_each_priv(priv, common) {
488 thermal_zone_device_unregister(priv->zone);
489 if (rcar_has_irq_support(priv)) 484 if (rcar_has_irq_support(priv))
490 rcar_thermal_irq_disable(priv); 485 rcar_thermal_irq_disable(priv);
486 thermal_zone_device_unregister(priv->zone);
491 } 487 }
492 488
493 pm_runtime_put(dev); 489 pm_runtime_put(dev);
diff --git a/drivers/thermal/samsung/exynos_tmu.c b/drivers/thermal/samsung/exynos_tmu.c
index 933cd80a6bc5..1fc54ab911d2 100644
--- a/drivers/thermal/samsung/exynos_tmu.c
+++ b/drivers/thermal/samsung/exynos_tmu.c
@@ -918,34 +918,16 @@ static irqreturn_t exynos_tmu_irq(int irq, void *id)
918} 918}
919 919
920static const struct of_device_id exynos_tmu_match[] = { 920static const struct of_device_id exynos_tmu_match[] = {
921 { 921 { .compatible = "samsung,exynos3250-tmu", },
922 .compatible = "samsung,exynos3250-tmu", 922 { .compatible = "samsung,exynos4210-tmu", },
923 }, 923 { .compatible = "samsung,exynos4412-tmu", },
924 { 924 { .compatible = "samsung,exynos5250-tmu", },
925 .compatible = "samsung,exynos4210-tmu", 925 { .compatible = "samsung,exynos5260-tmu", },
926 }, 926 { .compatible = "samsung,exynos5420-tmu", },
927 { 927 { .compatible = "samsung,exynos5420-tmu-ext-triminfo", },
928 .compatible = "samsung,exynos4412-tmu", 928 { .compatible = "samsung,exynos5440-tmu", },
929 }, 929 { .compatible = "samsung,exynos7-tmu", },
930 { 930 { /* sentinel */ },
931 .compatible = "samsung,exynos5250-tmu",
932 },
933 {
934 .compatible = "samsung,exynos5260-tmu",
935 },
936 {
937 .compatible = "samsung,exynos5420-tmu",
938 },
939 {
940 .compatible = "samsung,exynos5420-tmu-ext-triminfo",
941 },
942 {
943 .compatible = "samsung,exynos5440-tmu",
944 },
945 {
946 .compatible = "samsung,exynos7-tmu",
947 },
948 {},
949}; 931};
950MODULE_DEVICE_TABLE(of, exynos_tmu_match); 932MODULE_DEVICE_TABLE(of, exynos_tmu_match);
951 933
diff --git a/drivers/thermal/ti-soc-thermal/ti-bandgap.c b/drivers/thermal/ti-soc-thermal/ti-bandgap.c
index 634b6ce0e63a..62a5d449c388 100644
--- a/drivers/thermal/ti-soc-thermal/ti-bandgap.c
+++ b/drivers/thermal/ti-soc-thermal/ti-bandgap.c
@@ -1402,7 +1402,7 @@ int ti_bandgap_remove(struct platform_device *pdev)
1402 return 0; 1402 return 0;
1403} 1403}
1404 1404
1405#ifdef CONFIG_PM 1405#ifdef CONFIG_PM_SLEEP
1406static int ti_bandgap_save_ctxt(struct ti_bandgap *bgp) 1406static int ti_bandgap_save_ctxt(struct ti_bandgap *bgp)
1407{ 1407{
1408 int i; 1408 int i;
diff --git a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
index 3fb054a10f6a..a38c1756442a 100644
--- a/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
+++ b/drivers/thermal/ti-soc-thermal/ti-thermal-common.c
@@ -429,7 +429,7 @@ int ti_thermal_unregister_cpu_cooling(struct ti_bandgap *bgp, int id)
429 429
430 data = ti_bandgap_get_sensor_data(bgp, id); 430 data = ti_bandgap_get_sensor_data(bgp, id);
431 431
432 if (data && data->cool_dev) 432 if (data)
433 cpufreq_cooling_unregister(data->cool_dev); 433 cpufreq_cooling_unregister(data->cool_dev);
434 434
435 return 0; 435 return 0;
diff --git a/drivers/xen/Makefile b/drivers/xen/Makefile
index 2140398a2a8c..2ccd3592d41f 100644
--- a/drivers/xen/Makefile
+++ b/drivers/xen/Makefile
@@ -2,7 +2,7 @@ ifeq ($(filter y, $(CONFIG_ARM) $(CONFIG_ARM64)),)
2obj-$(CONFIG_HOTPLUG_CPU) += cpu_hotplug.o 2obj-$(CONFIG_HOTPLUG_CPU) += cpu_hotplug.o
3endif 3endif
4obj-$(CONFIG_X86) += fallback.o 4obj-$(CONFIG_X86) += fallback.o
5obj-y += grant-table.o features.o balloon.o manage.o 5obj-y += grant-table.o features.o balloon.o manage.o preempt.o
6obj-y += events/ 6obj-y += events/
7obj-y += xenbus/ 7obj-y += xenbus/
8 8
diff --git a/drivers/xen/preempt.c b/drivers/xen/preempt.c
new file mode 100644
index 000000000000..a1800c150839
--- /dev/null
+++ b/drivers/xen/preempt.c
@@ -0,0 +1,44 @@
1/*
2 * Preemptible hypercalls
3 *
4 * Copyright (C) 2014 Citrix Systems R&D ltd.
5 *
6 * This source code is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
10 */
11
12#include <linux/sched.h>
13#include <xen/xen-ops.h>
14
15#ifndef CONFIG_PREEMPT
16
17/*
18 * Some hypercalls issued by the toolstack can take many 10s of
19 * seconds. Allow tasks running hypercalls via the privcmd driver to
20 * be voluntarily preempted even if full kernel preemption is
21 * disabled.
22 *
23 * Such preemptible hypercalls are bracketed by
24 * xen_preemptible_hcall_begin() and xen_preemptible_hcall_end()
25 * calls.
26 */
27
28DEFINE_PER_CPU(bool, xen_in_preemptible_hcall);
29EXPORT_SYMBOL_GPL(xen_in_preemptible_hcall);
30
31asmlinkage __visible void xen_maybe_preempt_hcall(void)
32{
33 if (unlikely(__this_cpu_read(xen_in_preemptible_hcall)
34 && should_resched())) {
35 /*
36 * Clear flag as we may be rescheduled on a different
37 * cpu.
38 */
39 __this_cpu_write(xen_in_preemptible_hcall, false);
40 _cond_resched();
41 __this_cpu_write(xen_in_preemptible_hcall, true);
42 }
43}
44#endif /* CONFIG_PREEMPT */
diff --git a/drivers/xen/privcmd.c b/drivers/xen/privcmd.c
index 569a13b9e856..59ac71c4a043 100644
--- a/drivers/xen/privcmd.c
+++ b/drivers/xen/privcmd.c
@@ -56,10 +56,12 @@ static long privcmd_ioctl_hypercall(void __user *udata)
56 if (copy_from_user(&hypercall, udata, sizeof(hypercall))) 56 if (copy_from_user(&hypercall, udata, sizeof(hypercall)))
57 return -EFAULT; 57 return -EFAULT;
58 58
59 xen_preemptible_hcall_begin();
59 ret = privcmd_call(hypercall.op, 60 ret = privcmd_call(hypercall.op,
60 hypercall.arg[0], hypercall.arg[1], 61 hypercall.arg[0], hypercall.arg[1],
61 hypercall.arg[2], hypercall.arg[3], 62 hypercall.arg[2], hypercall.arg[3],
62 hypercall.arg[4]); 63 hypercall.arg[4]);
64 xen_preemptible_hcall_end();
63 65
64 return ret; 66 return ret;
65} 67}
diff --git a/drivers/xen/xen-scsiback.c b/drivers/xen/xen-scsiback.c
index 61653a03a8f5..9faca6a60bb0 100644
--- a/drivers/xen/xen-scsiback.c
+++ b/drivers/xen/xen-scsiback.c
@@ -709,12 +709,11 @@ static int prepare_pending_reqs(struct vscsibk_info *info,
709static int scsiback_do_cmd_fn(struct vscsibk_info *info) 709static int scsiback_do_cmd_fn(struct vscsibk_info *info)
710{ 710{
711 struct vscsiif_back_ring *ring = &info->ring; 711 struct vscsiif_back_ring *ring = &info->ring;
712 struct vscsiif_request *ring_req; 712 struct vscsiif_request ring_req;
713 struct vscsibk_pend *pending_req; 713 struct vscsibk_pend *pending_req;
714 RING_IDX rc, rp; 714 RING_IDX rc, rp;
715 int err, more_to_do; 715 int err, more_to_do;
716 uint32_t result; 716 uint32_t result;
717 uint8_t act;
718 717
719 rc = ring->req_cons; 718 rc = ring->req_cons;
720 rp = ring->sring->req_prod; 719 rp = ring->sring->req_prod;
@@ -735,11 +734,10 @@ static int scsiback_do_cmd_fn(struct vscsibk_info *info)
735 if (!pending_req) 734 if (!pending_req)
736 return 1; 735 return 1;
737 736
738 ring_req = RING_GET_REQUEST(ring, rc); 737 ring_req = *RING_GET_REQUEST(ring, rc);
739 ring->req_cons = ++rc; 738 ring->req_cons = ++rc;
740 739
741 act = ring_req->act; 740 err = prepare_pending_reqs(info, &ring_req, pending_req);
742 err = prepare_pending_reqs(info, ring_req, pending_req);
743 if (err) { 741 if (err) {
744 switch (err) { 742 switch (err) {
745 case -ENODEV: 743 case -ENODEV:
@@ -755,9 +753,9 @@ static int scsiback_do_cmd_fn(struct vscsibk_info *info)
755 return 1; 753 return 1;
756 } 754 }
757 755
758 switch (act) { 756 switch (ring_req.act) {
759 case VSCSIIF_ACT_SCSI_CDB: 757 case VSCSIIF_ACT_SCSI_CDB:
760 if (scsiback_gnttab_data_map(ring_req, pending_req)) { 758 if (scsiback_gnttab_data_map(&ring_req, pending_req)) {
761 scsiback_fast_flush_area(pending_req); 759 scsiback_fast_flush_area(pending_req);
762 scsiback_do_resp_with_sense(NULL, 760 scsiback_do_resp_with_sense(NULL,
763 DRIVER_ERROR << 24, 0, pending_req); 761 DRIVER_ERROR << 24, 0, pending_req);
@@ -768,7 +766,7 @@ static int scsiback_do_cmd_fn(struct vscsibk_info *info)
768 break; 766 break;
769 case VSCSIIF_ACT_SCSI_ABORT: 767 case VSCSIIF_ACT_SCSI_ABORT:
770 scsiback_device_action(pending_req, TMR_ABORT_TASK, 768 scsiback_device_action(pending_req, TMR_ABORT_TASK,
771 ring_req->ref_rqid); 769 ring_req.ref_rqid);
772 break; 770 break;
773 case VSCSIIF_ACT_SCSI_RESET: 771 case VSCSIIF_ACT_SCSI_RESET:
774 scsiback_device_action(pending_req, TMR_LUN_RESET, 0); 772 scsiback_device_action(pending_req, TMR_LUN_RESET, 0);
diff --git a/fs/btrfs/volumes.c b/fs/btrfs/volumes.c
index cd4d1315aaa9..8222f6f74147 100644
--- a/fs/btrfs/volumes.c
+++ b/fs/btrfs/volumes.c
@@ -4903,10 +4903,17 @@ static void sort_parity_stripes(struct btrfs_bio *bbio, int num_stripes)
4903static struct btrfs_bio *alloc_btrfs_bio(int total_stripes, int real_stripes) 4903static struct btrfs_bio *alloc_btrfs_bio(int total_stripes, int real_stripes)
4904{ 4904{
4905 struct btrfs_bio *bbio = kzalloc( 4905 struct btrfs_bio *bbio = kzalloc(
4906 /* the size of the btrfs_bio */
4906 sizeof(struct btrfs_bio) + 4907 sizeof(struct btrfs_bio) +
4908 /* plus the variable array for the stripes */
4907 sizeof(struct btrfs_bio_stripe) * (total_stripes) + 4909 sizeof(struct btrfs_bio_stripe) * (total_stripes) +
4910 /* plus the variable array for the tgt dev */
4908 sizeof(int) * (real_stripes) + 4911 sizeof(int) * (real_stripes) +
4909 sizeof(u64) * (real_stripes), 4912 /*
4913 * plus the raid_map, which includes both the tgt dev
4914 * and the stripes
4915 */
4916 sizeof(u64) * (total_stripes),
4910 GFP_NOFS); 4917 GFP_NOFS);
4911 if (!bbio) 4918 if (!bbio)
4912 return NULL; 4919 return NULL;
diff --git a/fs/nilfs2/btree.c b/fs/nilfs2/btree.c
index b2e3ff347620..ecdbae19a766 100644
--- a/fs/nilfs2/btree.c
+++ b/fs/nilfs2/btree.c
@@ -31,6 +31,8 @@
31#include "alloc.h" 31#include "alloc.h"
32#include "dat.h" 32#include "dat.h"
33 33
34static void __nilfs_btree_init(struct nilfs_bmap *bmap);
35
34static struct nilfs_btree_path *nilfs_btree_alloc_path(void) 36static struct nilfs_btree_path *nilfs_btree_alloc_path(void)
35{ 37{
36 struct nilfs_btree_path *path; 38 struct nilfs_btree_path *path;
@@ -368,6 +370,34 @@ static int nilfs_btree_node_broken(const struct nilfs_btree_node *node,
368 return ret; 370 return ret;
369} 371}
370 372
373/**
374 * nilfs_btree_root_broken - verify consistency of btree root node
375 * @node: btree root node to be examined
376 * @ino: inode number
377 *
378 * Return Value: If node is broken, 1 is returned. Otherwise, 0 is returned.
379 */
380static int nilfs_btree_root_broken(const struct nilfs_btree_node *node,
381 unsigned long ino)
382{
383 int level, flags, nchildren;
384 int ret = 0;
385
386 level = nilfs_btree_node_get_level(node);
387 flags = nilfs_btree_node_get_flags(node);
388 nchildren = nilfs_btree_node_get_nchildren(node);
389
390 if (unlikely(level < NILFS_BTREE_LEVEL_NODE_MIN ||
391 level > NILFS_BTREE_LEVEL_MAX ||
392 nchildren < 0 ||
393 nchildren > NILFS_BTREE_ROOT_NCHILDREN_MAX)) {
394 pr_crit("NILFS: bad btree root (inode number=%lu): level = %d, flags = 0x%x, nchildren = %d\n",
395 ino, level, flags, nchildren);
396 ret = 1;
397 }
398 return ret;
399}
400
371int nilfs_btree_broken_node_block(struct buffer_head *bh) 401int nilfs_btree_broken_node_block(struct buffer_head *bh)
372{ 402{
373 int ret; 403 int ret;
@@ -1713,7 +1743,7 @@ nilfs_btree_commit_convert_and_insert(struct nilfs_bmap *btree,
1713 1743
1714 /* convert and insert */ 1744 /* convert and insert */
1715 dat = NILFS_BMAP_USE_VBN(btree) ? nilfs_bmap_get_dat(btree) : NULL; 1745 dat = NILFS_BMAP_USE_VBN(btree) ? nilfs_bmap_get_dat(btree) : NULL;
1716 nilfs_btree_init(btree); 1746 __nilfs_btree_init(btree);
1717 if (nreq != NULL) { 1747 if (nreq != NULL) {
1718 nilfs_bmap_commit_alloc_ptr(btree, dreq, dat); 1748 nilfs_bmap_commit_alloc_ptr(btree, dreq, dat);
1719 nilfs_bmap_commit_alloc_ptr(btree, nreq, dat); 1749 nilfs_bmap_commit_alloc_ptr(btree, nreq, dat);
@@ -2294,12 +2324,23 @@ static const struct nilfs_bmap_operations nilfs_btree_ops_gc = {
2294 .bop_gather_data = NULL, 2324 .bop_gather_data = NULL,
2295}; 2325};
2296 2326
2297int nilfs_btree_init(struct nilfs_bmap *bmap) 2327static void __nilfs_btree_init(struct nilfs_bmap *bmap)
2298{ 2328{
2299 bmap->b_ops = &nilfs_btree_ops; 2329 bmap->b_ops = &nilfs_btree_ops;
2300 bmap->b_nchildren_per_block = 2330 bmap->b_nchildren_per_block =
2301 NILFS_BTREE_NODE_NCHILDREN_MAX(nilfs_btree_node_size(bmap)); 2331 NILFS_BTREE_NODE_NCHILDREN_MAX(nilfs_btree_node_size(bmap));
2302 return 0; 2332}
2333
2334int nilfs_btree_init(struct nilfs_bmap *bmap)
2335{
2336 int ret = 0;
2337
2338 __nilfs_btree_init(bmap);
2339
2340 if (nilfs_btree_root_broken(nilfs_btree_get_root(bmap),
2341 bmap->b_inode->i_ino))
2342 ret = -EIO;
2343 return ret;
2303} 2344}
2304 2345
2305void nilfs_btree_init_gc(struct nilfs_bmap *bmap) 2346void nilfs_btree_init_gc(struct nilfs_bmap *bmap)
diff --git a/fs/xfs/xfs_file.c b/fs/xfs/xfs_file.c
index ce615d12fb44..a2e1cb8a568b 100644
--- a/fs/xfs/xfs_file.c
+++ b/fs/xfs/xfs_file.c
@@ -397,7 +397,8 @@ STATIC int /* error (positive) */
397xfs_zero_last_block( 397xfs_zero_last_block(
398 struct xfs_inode *ip, 398 struct xfs_inode *ip,
399 xfs_fsize_t offset, 399 xfs_fsize_t offset,
400 xfs_fsize_t isize) 400 xfs_fsize_t isize,
401 bool *did_zeroing)
401{ 402{
402 struct xfs_mount *mp = ip->i_mount; 403 struct xfs_mount *mp = ip->i_mount;
403 xfs_fileoff_t last_fsb = XFS_B_TO_FSBT(mp, isize); 404 xfs_fileoff_t last_fsb = XFS_B_TO_FSBT(mp, isize);
@@ -425,6 +426,7 @@ xfs_zero_last_block(
425 zero_len = mp->m_sb.sb_blocksize - zero_offset; 426 zero_len = mp->m_sb.sb_blocksize - zero_offset;
426 if (isize + zero_len > offset) 427 if (isize + zero_len > offset)
427 zero_len = offset - isize; 428 zero_len = offset - isize;
429 *did_zeroing = true;
428 return xfs_iozero(ip, isize, zero_len); 430 return xfs_iozero(ip, isize, zero_len);
429} 431}
430 432
@@ -443,7 +445,8 @@ int /* error (positive) */
443xfs_zero_eof( 445xfs_zero_eof(
444 struct xfs_inode *ip, 446 struct xfs_inode *ip,
445 xfs_off_t offset, /* starting I/O offset */ 447 xfs_off_t offset, /* starting I/O offset */
446 xfs_fsize_t isize) /* current inode size */ 448 xfs_fsize_t isize, /* current inode size */
449 bool *did_zeroing)
447{ 450{
448 struct xfs_mount *mp = ip->i_mount; 451 struct xfs_mount *mp = ip->i_mount;
449 xfs_fileoff_t start_zero_fsb; 452 xfs_fileoff_t start_zero_fsb;
@@ -465,7 +468,7 @@ xfs_zero_eof(
465 * We only zero a part of that block so it is handled specially. 468 * We only zero a part of that block so it is handled specially.
466 */ 469 */
467 if (XFS_B_FSB_OFFSET(mp, isize) != 0) { 470 if (XFS_B_FSB_OFFSET(mp, isize) != 0) {
468 error = xfs_zero_last_block(ip, offset, isize); 471 error = xfs_zero_last_block(ip, offset, isize, did_zeroing);
469 if (error) 472 if (error)
470 return error; 473 return error;
471 } 474 }
@@ -525,6 +528,7 @@ xfs_zero_eof(
525 if (error) 528 if (error)
526 return error; 529 return error;
527 530
531 *did_zeroing = true;
528 start_zero_fsb = imap.br_startoff + imap.br_blockcount; 532 start_zero_fsb = imap.br_startoff + imap.br_blockcount;
529 ASSERT(start_zero_fsb <= (end_zero_fsb + 1)); 533 ASSERT(start_zero_fsb <= (end_zero_fsb + 1));
530 } 534 }
@@ -567,13 +571,15 @@ restart:
567 * having to redo all checks before. 571 * having to redo all checks before.
568 */ 572 */
569 if (*pos > i_size_read(inode)) { 573 if (*pos > i_size_read(inode)) {
574 bool zero = false;
575
570 if (*iolock == XFS_IOLOCK_SHARED) { 576 if (*iolock == XFS_IOLOCK_SHARED) {
571 xfs_rw_iunlock(ip, *iolock); 577 xfs_rw_iunlock(ip, *iolock);
572 *iolock = XFS_IOLOCK_EXCL; 578 *iolock = XFS_IOLOCK_EXCL;
573 xfs_rw_ilock(ip, *iolock); 579 xfs_rw_ilock(ip, *iolock);
574 goto restart; 580 goto restart;
575 } 581 }
576 error = xfs_zero_eof(ip, *pos, i_size_read(inode)); 582 error = xfs_zero_eof(ip, *pos, i_size_read(inode), &zero);
577 if (error) 583 if (error)
578 return error; 584 return error;
579 } 585 }
diff --git a/fs/xfs/xfs_inode.c b/fs/xfs/xfs_inode.c
index daafa1f6d260..6163767aa856 100644
--- a/fs/xfs/xfs_inode.c
+++ b/fs/xfs/xfs_inode.c
@@ -2867,6 +2867,10 @@ xfs_rename(
2867 * Handle RENAME_EXCHANGE flags 2867 * Handle RENAME_EXCHANGE flags
2868 */ 2868 */
2869 if (flags & RENAME_EXCHANGE) { 2869 if (flags & RENAME_EXCHANGE) {
2870 if (target_ip == NULL) {
2871 error = -EINVAL;
2872 goto error_return;
2873 }
2870 error = xfs_cross_rename(tp, src_dp, src_name, src_ip, 2874 error = xfs_cross_rename(tp, src_dp, src_name, src_ip,
2871 target_dp, target_name, target_ip, 2875 target_dp, target_name, target_ip,
2872 &free_list, &first_block, spaceres); 2876 &free_list, &first_block, spaceres);
diff --git a/fs/xfs/xfs_inode.h b/fs/xfs/xfs_inode.h
index 86cd6b39bed7..a1cd55f3f351 100644
--- a/fs/xfs/xfs_inode.h
+++ b/fs/xfs/xfs_inode.h
@@ -384,10 +384,11 @@ enum xfs_prealloc_flags {
384 XFS_PREALLOC_INVISIBLE = (1 << 4), 384 XFS_PREALLOC_INVISIBLE = (1 << 4),
385}; 385};
386 386
387int xfs_update_prealloc_flags(struct xfs_inode *, 387int xfs_update_prealloc_flags(struct xfs_inode *ip,
388 enum xfs_prealloc_flags); 388 enum xfs_prealloc_flags flags);
389int xfs_zero_eof(struct xfs_inode *, xfs_off_t, xfs_fsize_t); 389int xfs_zero_eof(struct xfs_inode *ip, xfs_off_t offset,
390int xfs_iozero(struct xfs_inode *, loff_t, size_t); 390 xfs_fsize_t isize, bool *did_zeroing);
391int xfs_iozero(struct xfs_inode *ip, loff_t pos, size_t count);
391 392
392 393
393#define IHOLD(ip) \ 394#define IHOLD(ip) \
diff --git a/fs/xfs/xfs_iops.c b/fs/xfs/xfs_iops.c
index d919ad7b16bf..e53a90331422 100644
--- a/fs/xfs/xfs_iops.c
+++ b/fs/xfs/xfs_iops.c
@@ -751,6 +751,7 @@ xfs_setattr_size(
751 int error; 751 int error;
752 uint lock_flags = 0; 752 uint lock_flags = 0;
753 uint commit_flags = 0; 753 uint commit_flags = 0;
754 bool did_zeroing = false;
754 755
755 trace_xfs_setattr(ip); 756 trace_xfs_setattr(ip);
756 757
@@ -794,20 +795,16 @@ xfs_setattr_size(
794 return error; 795 return error;
795 796
796 /* 797 /*
797 * Now we can make the changes. Before we join the inode to the 798 * File data changes must be complete before we start the transaction to
798 * transaction, take care of the part of the truncation that must be 799 * modify the inode. This needs to be done before joining the inode to
799 * done without the inode lock. This needs to be done before joining 800 * the transaction because the inode cannot be unlocked once it is a
800 * the inode to the transaction, because the inode cannot be unlocked 801 * part of the transaction.
801 * once it is a part of the transaction. 802 *
803 * Start with zeroing any data block beyond EOF that we may expose on
804 * file extension.
802 */ 805 */
803 if (newsize > oldsize) { 806 if (newsize > oldsize) {
804 /* 807 error = xfs_zero_eof(ip, newsize, oldsize, &did_zeroing);
805 * Do the first part of growing a file: zero any data in the
806 * last block that is beyond the old EOF. We need to do this
807 * before the inode is joined to the transaction to modify
808 * i_size.
809 */
810 error = xfs_zero_eof(ip, newsize, oldsize);
811 if (error) 808 if (error)
812 return error; 809 return error;
813 } 810 }
@@ -817,23 +814,18 @@ xfs_setattr_size(
817 * any previous writes that are beyond the on disk EOF and the new 814 * any previous writes that are beyond the on disk EOF and the new
818 * EOF that have not been written out need to be written here. If we 815 * EOF that have not been written out need to be written here. If we
819 * do not write the data out, we expose ourselves to the null files 816 * do not write the data out, we expose ourselves to the null files
820 * problem. 817 * problem. Note that this includes any block zeroing we did above;
821 * 818 * otherwise those blocks may not be zeroed after a crash.
822 * Only flush from the on disk size to the smaller of the in memory
823 * file size or the new size as that's the range we really care about
824 * here and prevents waiting for other data not within the range we
825 * care about here.
826 */ 819 */
827 if (oldsize != ip->i_d.di_size && newsize > ip->i_d.di_size) { 820 if (newsize > ip->i_d.di_size &&
821 (oldsize != ip->i_d.di_size || did_zeroing)) {
828 error = filemap_write_and_wait_range(VFS_I(ip)->i_mapping, 822 error = filemap_write_and_wait_range(VFS_I(ip)->i_mapping,
829 ip->i_d.di_size, newsize); 823 ip->i_d.di_size, newsize);
830 if (error) 824 if (error)
831 return error; 825 return error;
832 } 826 }
833 827
834 /* 828 /* Now wait for all direct I/O to complete. */
835 * Wait for all direct I/O to complete.
836 */
837 inode_dio_wait(inode); 829 inode_dio_wait(inode);
838 830
839 /* 831 /*
diff --git a/fs/xfs/xfs_pnfs.c b/fs/xfs/xfs_pnfs.c
index 4b33ef112400..365dd57ea760 100644
--- a/fs/xfs/xfs_pnfs.c
+++ b/fs/xfs/xfs_pnfs.c
@@ -300,8 +300,10 @@ xfs_fs_commit_blocks(
300 300
301 tp = xfs_trans_alloc(mp, XFS_TRANS_SETATTR_NOT_SIZE); 301 tp = xfs_trans_alloc(mp, XFS_TRANS_SETATTR_NOT_SIZE);
302 error = xfs_trans_reserve(tp, &M_RES(mp)->tr_ichange, 0, 0); 302 error = xfs_trans_reserve(tp, &M_RES(mp)->tr_ichange, 0, 0);
303 if (error) 303 if (error) {
304 xfs_trans_cancel(tp, 0);
304 goto out_drop_iolock; 305 goto out_drop_iolock;
306 }
305 307
306 xfs_ilock(ip, XFS_ILOCK_EXCL); 308 xfs_ilock(ip, XFS_ILOCK_EXCL);
307 xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL); 309 xfs_trans_ijoin(tp, ip, XFS_ILOCK_EXCL);
diff --git a/fs/xfs/xfs_qm.c b/fs/xfs/xfs_qm.c
index 53cc2aaf8d2b..fbbb9e62e274 100644
--- a/fs/xfs/xfs_qm.c
+++ b/fs/xfs/xfs_qm.c
@@ -836,6 +836,11 @@ xfs_qm_reset_dqcounts(
836 */ 836 */
837 xfs_dqcheck(mp, ddq, id+j, type, XFS_QMOPT_DQREPAIR, 837 xfs_dqcheck(mp, ddq, id+j, type, XFS_QMOPT_DQREPAIR,
838 "xfs_quotacheck"); 838 "xfs_quotacheck");
839 /*
840 * Reset type in case we are reusing group quota file for
841 * project quotas or vice versa
842 */
843 ddq->d_flags = type;
839 ddq->d_bcount = 0; 844 ddq->d_bcount = 0;
840 ddq->d_icount = 0; 845 ddq->d_icount = 0;
841 ddq->d_rtbcount = 0; 846 ddq->d_rtbcount = 0;
diff --git a/include/drm/i915_pciids.h b/include/drm/i915_pciids.h
index 180ad0e6de21..d016dc57f007 100644
--- a/include/drm/i915_pciids.h
+++ b/include/drm/i915_pciids.h
@@ -214,9 +214,9 @@
214 INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info) 214 INTEL_VGA_DEVICE((((gt) - 1) << 4) | (id), info)
215 215
216#define _INTEL_BDW_M_IDS(gt, info) \ 216#define _INTEL_BDW_M_IDS(gt, info) \
217 _INTEL_BDW_M(gt, 0x1602, info), /* ULT */ \ 217 _INTEL_BDW_M(gt, 0x1602, info), /* Halo */ \
218 _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \ 218 _INTEL_BDW_M(gt, 0x1606, info), /* ULT */ \
219 _INTEL_BDW_M(gt, 0x160B, info), /* Iris */ \ 219 _INTEL_BDW_M(gt, 0x160B, info), /* ULT */ \
220 _INTEL_BDW_M(gt, 0x160E, info) /* ULX */ 220 _INTEL_BDW_M(gt, 0x160E, info) /* ULX */
221 221
222#define _INTEL_BDW_D_IDS(gt, info) \ 222#define _INTEL_BDW_D_IDS(gt, info) \
diff --git a/include/dt-bindings/clock/r8a7778-clock.h b/include/dt-bindings/clock/r8a7778-clock.h
new file mode 100644
index 000000000000..f6b07c5399de
--- /dev/null
+++ b/include/dt-bindings/clock/r8a7778-clock.h
@@ -0,0 +1,71 @@
1/*
2 * Copyright (C) 2014 Ulrich Hecht
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef __DT_BINDINGS_CLOCK_R8A7778_H__
11#define __DT_BINDINGS_CLOCK_R8A7778_H__
12
13/* CPG */
14#define R8A7778_CLK_PLLA 0
15#define R8A7778_CLK_PLLB 1
16#define R8A7778_CLK_B 2
17#define R8A7778_CLK_OUT 3
18#define R8A7778_CLK_P 4
19#define R8A7778_CLK_S 5
20#define R8A7778_CLK_S1 6
21
22/* MSTP0 */
23#define R8A7778_CLK_I2C0 30
24#define R8A7778_CLK_I2C1 29
25#define R8A7778_CLK_I2C2 28
26#define R8A7778_CLK_I2C3 27
27#define R8A7778_CLK_SCIF0 26
28#define R8A7778_CLK_SCIF1 25
29#define R8A7778_CLK_SCIF2 24
30#define R8A7778_CLK_SCIF3 23
31#define R8A7778_CLK_SCIF4 22
32#define R8A7778_CLK_SCIF5 21
33#define R8A7778_CLK_TMU0 16
34#define R8A7778_CLK_TMU1 15
35#define R8A7778_CLK_TMU2 14
36#define R8A7778_CLK_SSI0 12
37#define R8A7778_CLK_SSI1 11
38#define R8A7778_CLK_SSI2 10
39#define R8A7778_CLK_SSI3 9
40#define R8A7778_CLK_SRU 8
41#define R8A7778_CLK_HSPI 7
42
43/* MSTP1 */
44#define R8A7778_CLK_ETHER 14
45#define R8A7778_CLK_VIN0 10
46#define R8A7778_CLK_VIN1 9
47#define R8A7778_CLK_USB 0
48
49/* MSTP3 */
50#define R8A7778_CLK_MMC 31
51#define R8A7778_CLK_SDHI0 23
52#define R8A7778_CLK_SDHI1 22
53#define R8A7778_CLK_SDHI2 21
54#define R8A7778_CLK_SSI4 11
55#define R8A7778_CLK_SSI5 10
56#define R8A7778_CLK_SSI6 9
57#define R8A7778_CLK_SSI7 8
58#define R8A7778_CLK_SSI8 7
59
60/* MSTP5 */
61#define R8A7778_CLK_SRU_SRC0 31
62#define R8A7778_CLK_SRU_SRC1 30
63#define R8A7778_CLK_SRU_SRC2 29
64#define R8A7778_CLK_SRU_SRC3 28
65#define R8A7778_CLK_SRU_SRC4 27
66#define R8A7778_CLK_SRU_SRC5 26
67#define R8A7778_CLK_SRU_SRC6 25
68#define R8A7778_CLK_SRU_SRC7 24
69#define R8A7778_CLK_SRU_SRC8 23
70
71#endif /* __DT_BINDINGS_CLOCK_R8A7778_H__ */
diff --git a/include/linux/clk/shmobile.h b/include/linux/clk/shmobile.h
index 9f8a14041dd5..63a8159c4e64 100644
--- a/include/linux/clk/shmobile.h
+++ b/include/linux/clk/shmobile.h
@@ -16,6 +16,7 @@
16 16
17#include <linux/types.h> 17#include <linux/types.h>
18 18
19void r8a7778_clocks_init(u32 mode);
19void r8a7779_clocks_init(u32 mode); 20void r8a7779_clocks_init(u32 mode);
20void rcar_gen2_clocks_init(u32 mode); 21void rcar_gen2_clocks_init(u32 mode);
21 22
diff --git a/include/linux/hid-sensor-hub.h b/include/linux/hid-sensor-hub.h
index 51f7ccadf923..4173a8fdad9e 100644
--- a/include/linux/hid-sensor-hub.h
+++ b/include/linux/hid-sensor-hub.h
@@ -33,6 +33,8 @@
33 * @units: Measurment unit for this attribute. 33 * @units: Measurment unit for this attribute.
34 * @unit_expo: Exponent used in the data. 34 * @unit_expo: Exponent used in the data.
35 * @size: Size in bytes for data size. 35 * @size: Size in bytes for data size.
36 * @logical_minimum: Logical minimum value for this attribute.
37 * @logical_maximum: Logical maximum value for this attribute.
36 */ 38 */
37struct hid_sensor_hub_attribute_info { 39struct hid_sensor_hub_attribute_info {
38 u32 usage_id; 40 u32 usage_id;
@@ -146,6 +148,7 @@ int sensor_hub_input_get_attribute_info(struct hid_sensor_hub_device *hsdev,
146 148
147/** 149/**
148* sensor_hub_input_attr_get_raw_value() - Synchronous read request 150* sensor_hub_input_attr_get_raw_value() - Synchronous read request
151* @hsdev: Hub device instance.
149* @usage_id: Attribute usage id of parent physical device as per spec 152* @usage_id: Attribute usage id of parent physical device as per spec
150* @attr_usage_id: Attribute usage id as per spec 153* @attr_usage_id: Attribute usage id as per spec
151* @report_id: Report id to look for 154* @report_id: Report id to look for
@@ -160,6 +163,7 @@ int sensor_hub_input_attr_get_raw_value(struct hid_sensor_hub_device *hsdev,
160 u32 attr_usage_id, u32 report_id); 163 u32 attr_usage_id, u32 report_id);
161/** 164/**
162* sensor_hub_set_feature() - Feature set request 165* sensor_hub_set_feature() - Feature set request
166* @hsdev: Hub device instance.
163* @report_id: Report id to look for 167* @report_id: Report id to look for
164* @field_index: Field index inside a report 168* @field_index: Field index inside a report
165* @value: Value to set 169* @value: Value to set
@@ -172,6 +176,7 @@ int sensor_hub_set_feature(struct hid_sensor_hub_device *hsdev, u32 report_id,
172 176
173/** 177/**
174* sensor_hub_get_feature() - Feature get request 178* sensor_hub_get_feature() - Feature get request
179* @hsdev: Hub device instance.
175* @report_id: Report id to look for 180* @report_id: Report id to look for
176* @field_index: Field index inside a report 181* @field_index: Field index inside a report
177* @value: Place holder for return value 182* @value: Place holder for return value
diff --git a/include/linux/thermal.h b/include/linux/thermal.h
index fc52e307efab..5eac316490ea 100644
--- a/include/linux/thermal.h
+++ b/include/linux/thermal.h
@@ -314,6 +314,8 @@ void thermal_zone_of_sensor_unregister(struct device *dev,
314} 314}
315 315
316#endif 316#endif
317
318#if IS_ENABLED(CONFIG_THERMAL)
317struct thermal_zone_device *thermal_zone_device_register(const char *, int, int, 319struct thermal_zone_device *thermal_zone_device_register(const char *, int, int,
318 void *, struct thermal_zone_device_ops *, 320 void *, struct thermal_zone_device_ops *,
319 const struct thermal_zone_params *, int, int); 321 const struct thermal_zone_params *, int, int);
@@ -340,8 +342,58 @@ struct thermal_instance *get_thermal_instance(struct thermal_zone_device *,
340 struct thermal_cooling_device *, int); 342 struct thermal_cooling_device *, int);
341void thermal_cdev_update(struct thermal_cooling_device *); 343void thermal_cdev_update(struct thermal_cooling_device *);
342void thermal_notify_framework(struct thermal_zone_device *, int); 344void thermal_notify_framework(struct thermal_zone_device *, int);
343 345#else
344#ifdef CONFIG_NET 346static inline struct thermal_zone_device *thermal_zone_device_register(
347 const char *type, int trips, int mask, void *devdata,
348 struct thermal_zone_device_ops *ops,
349 const struct thermal_zone_params *tzp,
350 int passive_delay, int polling_delay)
351{ return ERR_PTR(-ENODEV); }
352static inline void thermal_zone_device_unregister(
353 struct thermal_zone_device *tz)
354{ }
355static inline int thermal_zone_bind_cooling_device(
356 struct thermal_zone_device *tz, int trip,
357 struct thermal_cooling_device *cdev,
358 unsigned long upper, unsigned long lower)
359{ return -ENODEV; }
360static inline int thermal_zone_unbind_cooling_device(
361 struct thermal_zone_device *tz, int trip,
362 struct thermal_cooling_device *cdev)
363{ return -ENODEV; }
364static inline void thermal_zone_device_update(struct thermal_zone_device *tz)
365{ }
366static inline struct thermal_cooling_device *
367thermal_cooling_device_register(char *type, void *devdata,
368 const struct thermal_cooling_device_ops *ops)
369{ return ERR_PTR(-ENODEV); }
370static inline struct thermal_cooling_device *
371thermal_of_cooling_device_register(struct device_node *np,
372 char *type, void *devdata, const struct thermal_cooling_device_ops *ops)
373{ return ERR_PTR(-ENODEV); }
374static inline void thermal_cooling_device_unregister(
375 struct thermal_cooling_device *cdev)
376{ }
377static inline struct thermal_zone_device *thermal_zone_get_zone_by_name(
378 const char *name)
379{ return ERR_PTR(-ENODEV); }
380static inline int thermal_zone_get_temp(
381 struct thermal_zone_device *tz, unsigned long *temp)
382{ return -ENODEV; }
383static inline int get_tz_trend(struct thermal_zone_device *tz, int trip)
384{ return -ENODEV; }
385static inline struct thermal_instance *
386get_thermal_instance(struct thermal_zone_device *tz,
387 struct thermal_cooling_device *cdev, int trip)
388{ return ERR_PTR(-ENODEV); }
389static inline void thermal_cdev_update(struct thermal_cooling_device *cdev)
390{ }
391static inline void thermal_notify_framework(struct thermal_zone_device *tz,
392 int trip)
393{ }
394#endif /* CONFIG_THERMAL */
395
396#if defined(CONFIG_NET) && IS_ENABLED(CONFIG_THERMAL)
345extern int thermal_generate_netlink_event(struct thermal_zone_device *tz, 397extern int thermal_generate_netlink_event(struct thermal_zone_device *tz,
346 enum events event); 398 enum events event);
347#else 399#else
diff --git a/include/xen/xen-ops.h b/include/xen/xen-ops.h
index 7491ee5d8164..83338210ee04 100644
--- a/include/xen/xen-ops.h
+++ b/include/xen/xen-ops.h
@@ -46,4 +46,30 @@ static inline efi_system_table_t __init *xen_efi_probe(void)
46} 46}
47#endif 47#endif
48 48
49#ifdef CONFIG_PREEMPT
50
51static inline void xen_preemptible_hcall_begin(void)
52{
53}
54
55static inline void xen_preemptible_hcall_end(void)
56{
57}
58
59#else
60
61DECLARE_PER_CPU(bool, xen_in_preemptible_hcall);
62
63static inline void xen_preemptible_hcall_begin(void)
64{
65 __this_cpu_write(xen_in_preemptible_hcall, true);
66}
67
68static inline void xen_preemptible_hcall_end(void)
69{
70 __this_cpu_write(xen_in_preemptible_hcall, false);
71}
72
73#endif /* CONFIG_PREEMPT */
74
49#endif /* INCLUDE_XEN_OPS_H */ 75#endif /* INCLUDE_XEN_OPS_H */
diff --git a/kernel/livepatch/core.c b/kernel/livepatch/core.c
index ff7f47d026ac..782172f073c5 100644
--- a/kernel/livepatch/core.c
+++ b/kernel/livepatch/core.c
@@ -314,12 +314,12 @@ static void notrace klp_ftrace_handler(unsigned long ip,
314 rcu_read_lock(); 314 rcu_read_lock();
315 func = list_first_or_null_rcu(&ops->func_stack, struct klp_func, 315 func = list_first_or_null_rcu(&ops->func_stack, struct klp_func,
316 stack_node); 316 stack_node);
317 rcu_read_unlock();
318
319 if (WARN_ON_ONCE(!func)) 317 if (WARN_ON_ONCE(!func))
320 return; 318 goto unlock;
321 319
322 klp_arch_set_pc(regs, (unsigned long)func->new_func); 320 klp_arch_set_pc(regs, (unsigned long)func->new_func);
321unlock:
322 rcu_read_unlock();
323} 323}
324 324
325static int klp_disable_func(struct klp_func *func) 325static int klp_disable_func(struct klp_func *func)
@@ -731,7 +731,7 @@ static int klp_init_func(struct klp_object *obj, struct klp_func *func)
731 func->state = KLP_DISABLED; 731 func->state = KLP_DISABLED;
732 732
733 return kobject_init_and_add(&func->kobj, &klp_ktype_func, 733 return kobject_init_and_add(&func->kobj, &klp_ktype_func,
734 obj->kobj, func->old_name); 734 obj->kobj, "%s", func->old_name);
735} 735}
736 736
737/* parts of the initialization that is done only when the object is loaded */ 737/* parts of the initialization that is done only when the object is loaded */
@@ -807,7 +807,7 @@ static int klp_init_patch(struct klp_patch *patch)
807 patch->state = KLP_DISABLED; 807 patch->state = KLP_DISABLED;
808 808
809 ret = kobject_init_and_add(&patch->kobj, &klp_ktype_patch, 809 ret = kobject_init_and_add(&patch->kobj, &klp_ktype_patch,
810 klp_root_kobj, patch->mod->name); 810 klp_root_kobj, "%s", patch->mod->name);
811 if (ret) 811 if (ret)
812 goto unlock; 812 goto unlock;
813 813
diff --git a/kernel/locking/rtmutex.c b/kernel/locking/rtmutex.c
index e16e5542bf13..6357265a31ad 100644
--- a/kernel/locking/rtmutex.c
+++ b/kernel/locking/rtmutex.c
@@ -1193,6 +1193,7 @@ rt_mutex_slowlock(struct rt_mutex *lock, int state,
1193 ret = __rt_mutex_slowlock(lock, state, timeout, &waiter); 1193 ret = __rt_mutex_slowlock(lock, state, timeout, &waiter);
1194 1194
1195 if (unlikely(ret)) { 1195 if (unlikely(ret)) {
1196 __set_current_state(TASK_RUNNING);
1196 if (rt_mutex_has_waiters(lock)) 1197 if (rt_mutex_has_waiters(lock))
1197 remove_waiter(lock, &waiter); 1198 remove_waiter(lock, &waiter);
1198 rt_mutex_handle_deadlock(ret, chwalk, &waiter); 1199 rt_mutex_handle_deadlock(ret, chwalk, &waiter);
diff --git a/kernel/sys.c b/kernel/sys.c
index 667b2e62fad2..a03d9cd23ed7 100644
--- a/kernel/sys.c
+++ b/kernel/sys.c
@@ -1108,6 +1108,7 @@ DECLARE_RWSEM(uts_sem);
1108/* 1108/*
1109 * Work around broken programs that cannot handle "Linux 3.0". 1109 * Work around broken programs that cannot handle "Linux 3.0".
1110 * Instead we map 3.x to 2.6.40+x, so e.g. 3.0 would be 2.6.40 1110 * Instead we map 3.x to 2.6.40+x, so e.g. 3.0 would be 2.6.40
1111 * And we map 4.x to 2.6.60+x, so 4.0 would be 2.6.60.
1111 */ 1112 */
1112static int override_release(char __user *release, size_t len) 1113static int override_release(char __user *release, size_t len)
1113{ 1114{
@@ -1127,7 +1128,7 @@ static int override_release(char __user *release, size_t len)
1127 break; 1128 break;
1128 rest++; 1129 rest++;
1129 } 1130 }
1130 v = ((LINUX_VERSION_CODE >> 8) & 0xff) + 40; 1131 v = ((LINUX_VERSION_CODE >> 8) & 0xff) + 60;
1131 copy = clamp_t(size_t, len, 1, sizeof(buf)); 1132 copy = clamp_t(size_t, len, 1, sizeof(buf));
1132 copy = scnprintf(buf, copy, "2.6.%u%s", v, rest); 1133 copy = scnprintf(buf, copy, "2.6.%u%s", v, rest);
1133 ret = copy_to_user(release, buf, copy + 1); 1134 ret = copy_to_user(release, buf, copy + 1);
diff --git a/mm/memcontrol.c b/mm/memcontrol.c
index d18d3a6e7337..9fe07692eaad 100644
--- a/mm/memcontrol.c
+++ b/mm/memcontrol.c
@@ -5247,7 +5247,7 @@ static int memory_low_show(struct seq_file *m, void *v)
5247 unsigned long low = ACCESS_ONCE(memcg->low); 5247 unsigned long low = ACCESS_ONCE(memcg->low);
5248 5248
5249 if (low == PAGE_COUNTER_MAX) 5249 if (low == PAGE_COUNTER_MAX)
5250 seq_puts(m, "infinity\n"); 5250 seq_puts(m, "max\n");
5251 else 5251 else
5252 seq_printf(m, "%llu\n", (u64)low * PAGE_SIZE); 5252 seq_printf(m, "%llu\n", (u64)low * PAGE_SIZE);
5253 5253
@@ -5262,7 +5262,7 @@ static ssize_t memory_low_write(struct kernfs_open_file *of,
5262 int err; 5262 int err;
5263 5263
5264 buf = strstrip(buf); 5264 buf = strstrip(buf);
5265 err = page_counter_memparse(buf, "infinity", &low); 5265 err = page_counter_memparse(buf, "max", &low);
5266 if (err) 5266 if (err)
5267 return err; 5267 return err;
5268 5268
@@ -5277,7 +5277,7 @@ static int memory_high_show(struct seq_file *m, void *v)
5277 unsigned long high = ACCESS_ONCE(memcg->high); 5277 unsigned long high = ACCESS_ONCE(memcg->high);
5278 5278
5279 if (high == PAGE_COUNTER_MAX) 5279 if (high == PAGE_COUNTER_MAX)
5280 seq_puts(m, "infinity\n"); 5280 seq_puts(m, "max\n");
5281 else 5281 else
5282 seq_printf(m, "%llu\n", (u64)high * PAGE_SIZE); 5282 seq_printf(m, "%llu\n", (u64)high * PAGE_SIZE);
5283 5283
@@ -5292,7 +5292,7 @@ static ssize_t memory_high_write(struct kernfs_open_file *of,
5292 int err; 5292 int err;
5293 5293
5294 buf = strstrip(buf); 5294 buf = strstrip(buf);
5295 err = page_counter_memparse(buf, "infinity", &high); 5295 err = page_counter_memparse(buf, "max", &high);
5296 if (err) 5296 if (err)
5297 return err; 5297 return err;
5298 5298
@@ -5307,7 +5307,7 @@ static int memory_max_show(struct seq_file *m, void *v)
5307 unsigned long max = ACCESS_ONCE(memcg->memory.limit); 5307 unsigned long max = ACCESS_ONCE(memcg->memory.limit);
5308 5308
5309 if (max == PAGE_COUNTER_MAX) 5309 if (max == PAGE_COUNTER_MAX)
5310 seq_puts(m, "infinity\n"); 5310 seq_puts(m, "max\n");
5311 else 5311 else
5312 seq_printf(m, "%llu\n", (u64)max * PAGE_SIZE); 5312 seq_printf(m, "%llu\n", (u64)max * PAGE_SIZE);
5313 5313
@@ -5322,7 +5322,7 @@ static ssize_t memory_max_write(struct kernfs_open_file *of,
5322 int err; 5322 int err;
5323 5323
5324 buf = strstrip(buf); 5324 buf = strstrip(buf);
5325 err = page_counter_memparse(buf, "infinity", &max); 5325 err = page_counter_memparse(buf, "max", &max);
5326 if (err) 5326 if (err)
5327 return err; 5327 return err;
5328 5328
@@ -5426,7 +5426,7 @@ bool mem_cgroup_low(struct mem_cgroup *root, struct mem_cgroup *memcg)
5426 if (memcg == root_mem_cgroup) 5426 if (memcg == root_mem_cgroup)
5427 return false; 5427 return false;
5428 5428
5429 if (page_counter_read(&memcg->memory) > memcg->low) 5429 if (page_counter_read(&memcg->memory) >= memcg->low)
5430 return false; 5430 return false;
5431 5431
5432 while (memcg != root) { 5432 while (memcg != root) {
@@ -5435,7 +5435,7 @@ bool mem_cgroup_low(struct mem_cgroup *root, struct mem_cgroup *memcg)
5435 if (memcg == root_mem_cgroup) 5435 if (memcg == root_mem_cgroup)
5436 break; 5436 break;
5437 5437
5438 if (page_counter_read(&memcg->memory) > memcg->low) 5438 if (page_counter_read(&memcg->memory) >= memcg->low)
5439 return false; 5439 return false;
5440 } 5440 }
5441 return true; 5441 return true;
diff --git a/mm/nommu.c b/mm/nommu.c
index 7296360fc057..3e67e7538ecf 100644
--- a/mm/nommu.c
+++ b/mm/nommu.c
@@ -1213,11 +1213,9 @@ static int do_mmap_private(struct vm_area_struct *vma,
1213 if (sysctl_nr_trim_pages && total - point >= sysctl_nr_trim_pages) { 1213 if (sysctl_nr_trim_pages && total - point >= sysctl_nr_trim_pages) {
1214 total = point; 1214 total = point;
1215 kdebug("try to alloc exact %lu pages", total); 1215 kdebug("try to alloc exact %lu pages", total);
1216 base = alloc_pages_exact(len, GFP_KERNEL);
1217 } else {
1218 base = (void *)__get_free_pages(GFP_KERNEL, order);
1219 } 1216 }
1220 1217
1218 base = alloc_pages_exact(total << PAGE_SHIFT, GFP_KERNEL);
1221 if (!base) 1219 if (!base)
1222 goto enomem; 1220 goto enomem;
1223 1221
diff --git a/mm/page_alloc.c b/mm/page_alloc.c
index a47f0b229a1a..7abfa70cdc1a 100644
--- a/mm/page_alloc.c
+++ b/mm/page_alloc.c
@@ -2353,8 +2353,15 @@ __alloc_pages_may_oom(gfp_t gfp_mask, unsigned int order,
2353 if (ac->high_zoneidx < ZONE_NORMAL) 2353 if (ac->high_zoneidx < ZONE_NORMAL)
2354 goto out; 2354 goto out;
2355 /* The OOM killer does not compensate for light reclaim */ 2355 /* The OOM killer does not compensate for light reclaim */
2356 if (!(gfp_mask & __GFP_FS)) 2356 if (!(gfp_mask & __GFP_FS)) {
2357 /*
2358 * XXX: Page reclaim didn't yield anything,
2359 * and the OOM killer can't be invoked, but
2360 * keep looping as per should_alloc_retry().
2361 */
2362 *did_some_progress = 1;
2357 goto out; 2363 goto out;
2364 }
2358 /* 2365 /*
2359 * GFP_THISNODE contains __GFP_NORETRY and we never hit this. 2366 * GFP_THISNODE contains __GFP_NORETRY and we never hit this.
2360 * Sanity check for bare calls of __GFP_THISNODE, not real OOM. 2367 * Sanity check for bare calls of __GFP_THISNODE, not real OOM.
diff --git a/mm/shmem.c b/mm/shmem.c
index 2f17cb5f00a4..cf2d0ca010bc 100644
--- a/mm/shmem.c
+++ b/mm/shmem.c
@@ -1455,6 +1455,9 @@ static struct inode *shmem_get_inode(struct super_block *sb, const struct inode
1455 1455
1456bool shmem_mapping(struct address_space *mapping) 1456bool shmem_mapping(struct address_space *mapping)
1457{ 1457{
1458 if (!mapping->host)
1459 return false;
1460
1458 return mapping->host->i_sb->s_op == &shmem_ops; 1461 return mapping->host->i_sb->s_op == &shmem_ops;
1459} 1462}
1460 1463
diff --git a/scripts/gdb/linux/__init__.py b/scripts/gdb/linux/__init__.py
new file mode 100644
index 000000000000..4680fb176337
--- /dev/null
+++ b/scripts/gdb/linux/__init__.py
@@ -0,0 +1 @@
# nothing to do for the initialization of this package
diff --git a/sound/core/pcm_native.c b/sound/core/pcm_native.c
index b03a638b420c..279e24f61305 100644
--- a/sound/core/pcm_native.c
+++ b/sound/core/pcm_native.c
@@ -1552,6 +1552,8 @@ static int snd_pcm_do_drain_init(struct snd_pcm_substream *substream, int state)
1552 if (! snd_pcm_playback_empty(substream)) { 1552 if (! snd_pcm_playback_empty(substream)) {
1553 snd_pcm_do_start(substream, SNDRV_PCM_STATE_DRAINING); 1553 snd_pcm_do_start(substream, SNDRV_PCM_STATE_DRAINING);
1554 snd_pcm_post_start(substream, SNDRV_PCM_STATE_DRAINING); 1554 snd_pcm_post_start(substream, SNDRV_PCM_STATE_DRAINING);
1555 } else {
1556 runtime->status->state = SNDRV_PCM_STATE_SETUP;
1555 } 1557 }
1556 break; 1558 break;
1557 case SNDRV_PCM_STATE_RUNNING: 1559 case SNDRV_PCM_STATE_RUNNING:
diff --git a/sound/firewire/amdtp.c b/sound/firewire/amdtp.c
index 0d580186ef1a..5cc356db5351 100644
--- a/sound/firewire/amdtp.c
+++ b/sound/firewire/amdtp.c
@@ -33,7 +33,7 @@
33 */ 33 */
34#define MAX_MIDI_RX_BLOCKS 8 34#define MAX_MIDI_RX_BLOCKS 8
35 35
36#define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 µs */ 36#define TRANSFER_DELAY_TICKS 0x2e00 /* 479.17 microseconds */
37 37
38/* isochronous header parameters */ 38/* isochronous header parameters */
39#define ISO_DATA_LENGTH_SHIFT 16 39#define ISO_DATA_LENGTH_SHIFT 16
@@ -78,7 +78,7 @@ static void pcm_period_tasklet(unsigned long data);
78int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit, 78int amdtp_stream_init(struct amdtp_stream *s, struct fw_unit *unit,
79 enum amdtp_stream_direction dir, enum cip_flags flags) 79 enum amdtp_stream_direction dir, enum cip_flags flags)
80{ 80{
81 s->unit = fw_unit_get(unit); 81 s->unit = unit;
82 s->direction = dir; 82 s->direction = dir;
83 s->flags = flags; 83 s->flags = flags;
84 s->context = ERR_PTR(-1); 84 s->context = ERR_PTR(-1);
@@ -102,7 +102,6 @@ void amdtp_stream_destroy(struct amdtp_stream *s)
102{ 102{
103 WARN_ON(amdtp_stream_running(s)); 103 WARN_ON(amdtp_stream_running(s));
104 mutex_destroy(&s->mutex); 104 mutex_destroy(&s->mutex);
105 fw_unit_put(s->unit);
106} 105}
107EXPORT_SYMBOL(amdtp_stream_destroy); 106EXPORT_SYMBOL(amdtp_stream_destroy);
108 107
diff --git a/sound/firewire/bebob/bebob.c b/sound/firewire/bebob/bebob.c
index fc19c99654aa..611b7dae7ee5 100644
--- a/sound/firewire/bebob/bebob.c
+++ b/sound/firewire/bebob/bebob.c
@@ -116,11 +116,22 @@ end:
116 return err; 116 return err;
117} 117}
118 118
119/*
120 * This module releases the FireWire unit data after all ALSA character devices
121 * are released by applications. This is for releasing stream data or finishing
122 * transactions safely. Thus at returning from .remove(), this module still keep
123 * references for the unit.
124 */
119static void 125static void
120bebob_card_free(struct snd_card *card) 126bebob_card_free(struct snd_card *card)
121{ 127{
122 struct snd_bebob *bebob = card->private_data; 128 struct snd_bebob *bebob = card->private_data;
123 129
130 snd_bebob_stream_destroy_duplex(bebob);
131 fw_unit_put(bebob->unit);
132
133 kfree(bebob->maudio_special_quirk);
134
124 if (bebob->card_index >= 0) { 135 if (bebob->card_index >= 0) {
125 mutex_lock(&devices_mutex); 136 mutex_lock(&devices_mutex);
126 clear_bit(bebob->card_index, devices_used); 137 clear_bit(bebob->card_index, devices_used);
@@ -205,7 +216,7 @@ bebob_probe(struct fw_unit *unit,
205 card->private_free = bebob_card_free; 216 card->private_free = bebob_card_free;
206 217
207 bebob->card = card; 218 bebob->card = card;
208 bebob->unit = unit; 219 bebob->unit = fw_unit_get(unit);
209 bebob->spec = spec; 220 bebob->spec = spec;
210 mutex_init(&bebob->mutex); 221 mutex_init(&bebob->mutex);
211 spin_lock_init(&bebob->lock); 222 spin_lock_init(&bebob->lock);
@@ -306,10 +317,11 @@ static void bebob_remove(struct fw_unit *unit)
306 if (bebob == NULL) 317 if (bebob == NULL)
307 return; 318 return;
308 319
309 kfree(bebob->maudio_special_quirk); 320 /* Awake bus-reset waiters. */
321 if (!completion_done(&bebob->bus_reset))
322 complete_all(&bebob->bus_reset);
310 323
311 snd_bebob_stream_destroy_duplex(bebob); 324 /* No need to wait for releasing card object in this context. */
312 snd_card_disconnect(bebob->card);
313 snd_card_free_when_closed(bebob->card); 325 snd_card_free_when_closed(bebob->card);
314} 326}
315 327
diff --git a/sound/firewire/bebob/bebob_stream.c b/sound/firewire/bebob/bebob_stream.c
index 0ebcabfdc7ce..98e4fc8121a1 100644
--- a/sound/firewire/bebob/bebob_stream.c
+++ b/sound/firewire/bebob/bebob_stream.c
@@ -410,8 +410,6 @@ break_both_connections(struct snd_bebob *bebob)
410static void 410static void
411destroy_both_connections(struct snd_bebob *bebob) 411destroy_both_connections(struct snd_bebob *bebob)
412{ 412{
413 break_both_connections(bebob);
414
415 cmp_connection_destroy(&bebob->in_conn); 413 cmp_connection_destroy(&bebob->in_conn);
416 cmp_connection_destroy(&bebob->out_conn); 414 cmp_connection_destroy(&bebob->out_conn);
417} 415}
@@ -712,22 +710,16 @@ void snd_bebob_stream_update_duplex(struct snd_bebob *bebob)
712 mutex_unlock(&bebob->mutex); 710 mutex_unlock(&bebob->mutex);
713} 711}
714 712
713/*
714 * This function should be called before starting streams or after stopping
715 * streams.
716 */
715void snd_bebob_stream_destroy_duplex(struct snd_bebob *bebob) 717void snd_bebob_stream_destroy_duplex(struct snd_bebob *bebob)
716{ 718{
717 mutex_lock(&bebob->mutex);
718
719 amdtp_stream_pcm_abort(&bebob->rx_stream);
720 amdtp_stream_pcm_abort(&bebob->tx_stream);
721
722 amdtp_stream_stop(&bebob->rx_stream);
723 amdtp_stream_stop(&bebob->tx_stream);
724
725 amdtp_stream_destroy(&bebob->rx_stream); 719 amdtp_stream_destroy(&bebob->rx_stream);
726 amdtp_stream_destroy(&bebob->tx_stream); 720 amdtp_stream_destroy(&bebob->tx_stream);
727 721
728 destroy_both_connections(bebob); 722 destroy_both_connections(bebob);
729
730 mutex_unlock(&bebob->mutex);
731} 723}
732 724
733/* 725/*
diff --git a/sound/firewire/dice/dice-stream.c b/sound/firewire/dice/dice-stream.c
index fa9cf761b610..07dbd01d7a6b 100644
--- a/sound/firewire/dice/dice-stream.c
+++ b/sound/firewire/dice/dice-stream.c
@@ -311,14 +311,21 @@ end:
311 return err; 311 return err;
312} 312}
313 313
314/*
315 * This function should be called before starting streams or after stopping
316 * streams.
317 */
314static void destroy_stream(struct snd_dice *dice, struct amdtp_stream *stream) 318static void destroy_stream(struct snd_dice *dice, struct amdtp_stream *stream)
315{ 319{
316 amdtp_stream_destroy(stream); 320 struct fw_iso_resources *resources;
317 321
318 if (stream == &dice->tx_stream) 322 if (stream == &dice->tx_stream)
319 fw_iso_resources_destroy(&dice->tx_resources); 323 resources = &dice->tx_resources;
320 else 324 else
321 fw_iso_resources_destroy(&dice->rx_resources); 325 resources = &dice->rx_resources;
326
327 amdtp_stream_destroy(stream);
328 fw_iso_resources_destroy(resources);
322} 329}
323 330
324int snd_dice_stream_init_duplex(struct snd_dice *dice) 331int snd_dice_stream_init_duplex(struct snd_dice *dice)
@@ -332,6 +339,8 @@ int snd_dice_stream_init_duplex(struct snd_dice *dice)
332 goto end; 339 goto end;
333 340
334 err = init_stream(dice, &dice->rx_stream); 341 err = init_stream(dice, &dice->rx_stream);
342 if (err < 0)
343 destroy_stream(dice, &dice->tx_stream);
335end: 344end:
336 return err; 345 return err;
337} 346}
@@ -340,10 +349,7 @@ void snd_dice_stream_destroy_duplex(struct snd_dice *dice)
340{ 349{
341 snd_dice_transaction_clear_enable(dice); 350 snd_dice_transaction_clear_enable(dice);
342 351
343 stop_stream(dice, &dice->tx_stream);
344 destroy_stream(dice, &dice->tx_stream); 352 destroy_stream(dice, &dice->tx_stream);
345
346 stop_stream(dice, &dice->rx_stream);
347 destroy_stream(dice, &dice->rx_stream); 353 destroy_stream(dice, &dice->rx_stream);
348 354
349 dice->substreams_counter = 0; 355 dice->substreams_counter = 0;
diff --git a/sound/firewire/dice/dice.c b/sound/firewire/dice/dice.c
index 90d8f40ff727..70a111d7f428 100644
--- a/sound/firewire/dice/dice.c
+++ b/sound/firewire/dice/dice.c
@@ -226,11 +226,20 @@ static void dice_card_strings(struct snd_dice *dice)
226 strcpy(card->mixername, "DICE"); 226 strcpy(card->mixername, "DICE");
227} 227}
228 228
229/*
230 * This module releases the FireWire unit data after all ALSA character devices
231 * are released by applications. This is for releasing stream data or finishing
232 * transactions safely. Thus at returning from .remove(), this module still keep
233 * references for the unit.
234 */
229static void dice_card_free(struct snd_card *card) 235static void dice_card_free(struct snd_card *card)
230{ 236{
231 struct snd_dice *dice = card->private_data; 237 struct snd_dice *dice = card->private_data;
232 238
239 snd_dice_stream_destroy_duplex(dice);
233 snd_dice_transaction_destroy(dice); 240 snd_dice_transaction_destroy(dice);
241 fw_unit_put(dice->unit);
242
234 mutex_destroy(&dice->mutex); 243 mutex_destroy(&dice->mutex);
235} 244}
236 245
@@ -251,7 +260,7 @@ static int dice_probe(struct fw_unit *unit, const struct ieee1394_device_id *id)
251 260
252 dice = card->private_data; 261 dice = card->private_data;
253 dice->card = card; 262 dice->card = card;
254 dice->unit = unit; 263 dice->unit = fw_unit_get(unit);
255 card->private_free = dice_card_free; 264 card->private_free = dice_card_free;
256 265
257 spin_lock_init(&dice->lock); 266 spin_lock_init(&dice->lock);
@@ -305,10 +314,7 @@ static void dice_remove(struct fw_unit *unit)
305{ 314{
306 struct snd_dice *dice = dev_get_drvdata(&unit->device); 315 struct snd_dice *dice = dev_get_drvdata(&unit->device);
307 316
308 snd_card_disconnect(dice->card); 317 /* No need to wait for releasing card object in this context. */
309
310 snd_dice_stream_destroy_duplex(dice);
311
312 snd_card_free_when_closed(dice->card); 318 snd_card_free_when_closed(dice->card);
313} 319}
314 320
diff --git a/sound/firewire/fireworks/fireworks.c b/sound/firewire/fireworks/fireworks.c
index 3e2ed8e82cbc..2682e7e3e5c9 100644
--- a/sound/firewire/fireworks/fireworks.c
+++ b/sound/firewire/fireworks/fireworks.c
@@ -173,11 +173,23 @@ end:
173 return err; 173 return err;
174} 174}
175 175
176/*
177 * This module releases the FireWire unit data after all ALSA character devices
178 * are released by applications. This is for releasing stream data or finishing
179 * transactions safely. Thus at returning from .remove(), this module still keep
180 * references for the unit.
181 */
176static void 182static void
177efw_card_free(struct snd_card *card) 183efw_card_free(struct snd_card *card)
178{ 184{
179 struct snd_efw *efw = card->private_data; 185 struct snd_efw *efw = card->private_data;
180 186
187 snd_efw_stream_destroy_duplex(efw);
188 snd_efw_transaction_remove_instance(efw);
189 fw_unit_put(efw->unit);
190
191 kfree(efw->resp_buf);
192
181 if (efw->card_index >= 0) { 193 if (efw->card_index >= 0) {
182 mutex_lock(&devices_mutex); 194 mutex_lock(&devices_mutex);
183 clear_bit(efw->card_index, devices_used); 195 clear_bit(efw->card_index, devices_used);
@@ -185,7 +197,6 @@ efw_card_free(struct snd_card *card)
185 } 197 }
186 198
187 mutex_destroy(&efw->mutex); 199 mutex_destroy(&efw->mutex);
188 kfree(efw->resp_buf);
189} 200}
190 201
191static int 202static int
@@ -218,7 +229,7 @@ efw_probe(struct fw_unit *unit,
218 card->private_free = efw_card_free; 229 card->private_free = efw_card_free;
219 230
220 efw->card = card; 231 efw->card = card;
221 efw->unit = unit; 232 efw->unit = fw_unit_get(unit);
222 mutex_init(&efw->mutex); 233 mutex_init(&efw->mutex);
223 spin_lock_init(&efw->lock); 234 spin_lock_init(&efw->lock);
224 init_waitqueue_head(&efw->hwdep_wait); 235 init_waitqueue_head(&efw->hwdep_wait);
@@ -289,10 +300,7 @@ static void efw_remove(struct fw_unit *unit)
289{ 300{
290 struct snd_efw *efw = dev_get_drvdata(&unit->device); 301 struct snd_efw *efw = dev_get_drvdata(&unit->device);
291 302
292 snd_efw_stream_destroy_duplex(efw); 303 /* No need to wait for releasing card object in this context. */
293 snd_efw_transaction_remove_instance(efw);
294
295 snd_card_disconnect(efw->card);
296 snd_card_free_when_closed(efw->card); 304 snd_card_free_when_closed(efw->card);
297} 305}
298 306
diff --git a/sound/firewire/fireworks/fireworks_stream.c b/sound/firewire/fireworks/fireworks_stream.c
index 4f440e163667..c55db1bddc80 100644
--- a/sound/firewire/fireworks/fireworks_stream.c
+++ b/sound/firewire/fireworks/fireworks_stream.c
@@ -100,17 +100,22 @@ end:
100 return err; 100 return err;
101} 101}
102 102
103/*
104 * This function should be called before starting the stream or after stopping
105 * the streams.
106 */
103static void 107static void
104destroy_stream(struct snd_efw *efw, struct amdtp_stream *stream) 108destroy_stream(struct snd_efw *efw, struct amdtp_stream *stream)
105{ 109{
106 stop_stream(efw, stream); 110 struct cmp_connection *conn;
107
108 amdtp_stream_destroy(stream);
109 111
110 if (stream == &efw->tx_stream) 112 if (stream == &efw->tx_stream)
111 cmp_connection_destroy(&efw->out_conn); 113 conn = &efw->out_conn;
112 else 114 else
113 cmp_connection_destroy(&efw->in_conn); 115 conn = &efw->in_conn;
116
117 amdtp_stream_destroy(stream);
118 cmp_connection_destroy(&efw->out_conn);
114} 119}
115 120
116static int 121static int
@@ -319,12 +324,8 @@ void snd_efw_stream_update_duplex(struct snd_efw *efw)
319 324
320void snd_efw_stream_destroy_duplex(struct snd_efw *efw) 325void snd_efw_stream_destroy_duplex(struct snd_efw *efw)
321{ 326{
322 mutex_lock(&efw->mutex);
323
324 destroy_stream(efw, &efw->rx_stream); 327 destroy_stream(efw, &efw->rx_stream);
325 destroy_stream(efw, &efw->tx_stream); 328 destroy_stream(efw, &efw->tx_stream);
326
327 mutex_unlock(&efw->mutex);
328} 329}
329 330
330void snd_efw_stream_lock_changed(struct snd_efw *efw) 331void snd_efw_stream_lock_changed(struct snd_efw *efw)
diff --git a/sound/firewire/oxfw/oxfw-stream.c b/sound/firewire/oxfw/oxfw-stream.c
index bda845afb470..29ccb3637164 100644
--- a/sound/firewire/oxfw/oxfw-stream.c
+++ b/sound/firewire/oxfw/oxfw-stream.c
@@ -337,6 +337,10 @@ void snd_oxfw_stream_stop_simplex(struct snd_oxfw *oxfw,
337 stop_stream(oxfw, stream); 337 stop_stream(oxfw, stream);
338} 338}
339 339
340/*
341 * This function should be called before starting the stream or after stopping
342 * the streams.
343 */
340void snd_oxfw_stream_destroy_simplex(struct snd_oxfw *oxfw, 344void snd_oxfw_stream_destroy_simplex(struct snd_oxfw *oxfw,
341 struct amdtp_stream *stream) 345 struct amdtp_stream *stream)
342{ 346{
@@ -347,8 +351,6 @@ void snd_oxfw_stream_destroy_simplex(struct snd_oxfw *oxfw,
347 else 351 else
348 conn = &oxfw->in_conn; 352 conn = &oxfw->in_conn;
349 353
350 stop_stream(oxfw, stream);
351
352 amdtp_stream_destroy(stream); 354 amdtp_stream_destroy(stream);
353 cmp_connection_destroy(conn); 355 cmp_connection_destroy(conn);
354} 356}
diff --git a/sound/firewire/oxfw/oxfw.c b/sound/firewire/oxfw/oxfw.c
index 60e5cad0531a..8c6ce019f437 100644
--- a/sound/firewire/oxfw/oxfw.c
+++ b/sound/firewire/oxfw/oxfw.c
@@ -104,11 +104,23 @@ end:
104 return err; 104 return err;
105} 105}
106 106
107/*
108 * This module releases the FireWire unit data after all ALSA character devices
109 * are released by applications. This is for releasing stream data or finishing
110 * transactions safely. Thus at returning from .remove(), this module still keep
111 * references for the unit.
112 */
107static void oxfw_card_free(struct snd_card *card) 113static void oxfw_card_free(struct snd_card *card)
108{ 114{
109 struct snd_oxfw *oxfw = card->private_data; 115 struct snd_oxfw *oxfw = card->private_data;
110 unsigned int i; 116 unsigned int i;
111 117
118 snd_oxfw_stream_destroy_simplex(oxfw, &oxfw->rx_stream);
119 if (oxfw->has_output)
120 snd_oxfw_stream_destroy_simplex(oxfw, &oxfw->tx_stream);
121
122 fw_unit_put(oxfw->unit);
123
112 for (i = 0; i < SND_OXFW_STREAM_FORMAT_ENTRIES; i++) { 124 for (i = 0; i < SND_OXFW_STREAM_FORMAT_ENTRIES; i++) {
113 kfree(oxfw->tx_stream_formats[i]); 125 kfree(oxfw->tx_stream_formats[i]);
114 kfree(oxfw->rx_stream_formats[i]); 126 kfree(oxfw->rx_stream_formats[i]);
@@ -136,7 +148,7 @@ static int oxfw_probe(struct fw_unit *unit,
136 oxfw = card->private_data; 148 oxfw = card->private_data;
137 oxfw->card = card; 149 oxfw->card = card;
138 mutex_init(&oxfw->mutex); 150 mutex_init(&oxfw->mutex);
139 oxfw->unit = unit; 151 oxfw->unit = fw_unit_get(unit);
140 oxfw->device_info = (const struct device_info *)id->driver_data; 152 oxfw->device_info = (const struct device_info *)id->driver_data;
141 spin_lock_init(&oxfw->lock); 153 spin_lock_init(&oxfw->lock);
142 init_waitqueue_head(&oxfw->hwdep_wait); 154 init_waitqueue_head(&oxfw->hwdep_wait);
@@ -212,12 +224,7 @@ static void oxfw_remove(struct fw_unit *unit)
212{ 224{
213 struct snd_oxfw *oxfw = dev_get_drvdata(&unit->device); 225 struct snd_oxfw *oxfw = dev_get_drvdata(&unit->device);
214 226
215 snd_card_disconnect(oxfw->card); 227 /* No need to wait for releasing card object in this context. */
216
217 snd_oxfw_stream_destroy_simplex(oxfw, &oxfw->rx_stream);
218 if (oxfw->has_output)
219 snd_oxfw_stream_destroy_simplex(oxfw, &oxfw->tx_stream);
220
221 snd_card_free_when_closed(oxfw->card); 228 snd_card_free_when_closed(oxfw->card);
222} 229}
223 230
diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c
index dfcb5e929f9f..a2ce773bdc62 100644
--- a/sound/pci/hda/hda_controller.c
+++ b/sound/pci/hda/hda_controller.c
@@ -961,7 +961,6 @@ static int azx_alloc_cmd_io(struct azx *chip)
961 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n"); 961 dev_err(chip->card->dev, "cannot allocate CORB/RIRB\n");
962 return err; 962 return err;
963} 963}
964EXPORT_SYMBOL_GPL(azx_alloc_cmd_io);
965 964
966static void azx_init_cmd_io(struct azx *chip) 965static void azx_init_cmd_io(struct azx *chip)
967{ 966{
@@ -1026,7 +1025,6 @@ static void azx_init_cmd_io(struct azx *chip)
1026 azx_writeb(chip, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN); 1025 azx_writeb(chip, RIRBCTL, AZX_RBCTL_DMA_EN | AZX_RBCTL_IRQ_EN);
1027 spin_unlock_irq(&chip->reg_lock); 1026 spin_unlock_irq(&chip->reg_lock);
1028} 1027}
1029EXPORT_SYMBOL_GPL(azx_init_cmd_io);
1030 1028
1031static void azx_free_cmd_io(struct azx *chip) 1029static void azx_free_cmd_io(struct azx *chip)
1032{ 1030{
@@ -1036,7 +1034,6 @@ static void azx_free_cmd_io(struct azx *chip)
1036 azx_writeb(chip, CORBCTL, 0); 1034 azx_writeb(chip, CORBCTL, 0);
1037 spin_unlock_irq(&chip->reg_lock); 1035 spin_unlock_irq(&chip->reg_lock);
1038} 1036}
1039EXPORT_SYMBOL_GPL(azx_free_cmd_io);
1040 1037
1041static unsigned int azx_command_addr(u32 cmd) 1038static unsigned int azx_command_addr(u32 cmd)
1042{ 1039{
@@ -1316,7 +1313,6 @@ static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
1316 else 1313 else
1317 return azx_corb_send_cmd(bus, val); 1314 return azx_corb_send_cmd(bus, val);
1318} 1315}
1319EXPORT_SYMBOL_GPL(azx_send_cmd);
1320 1316
1321/* get a response */ 1317/* get a response */
1322static unsigned int azx_get_response(struct hda_bus *bus, 1318static unsigned int azx_get_response(struct hda_bus *bus,
@@ -1330,7 +1326,6 @@ static unsigned int azx_get_response(struct hda_bus *bus,
1330 else 1326 else
1331 return azx_rirb_get_response(bus, addr); 1327 return azx_rirb_get_response(bus, addr);
1332} 1328}
1333EXPORT_SYMBOL_GPL(azx_get_response);
1334 1329
1335#ifdef CONFIG_SND_HDA_DSP_LOADER 1330#ifdef CONFIG_SND_HDA_DSP_LOADER
1336/* 1331/*
diff --git a/sound/pci/hda/hda_intel.c b/sound/pci/hda/hda_intel.c
index 36d2f20db7a4..4ca3d5d02436 100644
--- a/sound/pci/hda/hda_intel.c
+++ b/sound/pci/hda/hda_intel.c
@@ -1966,7 +1966,7 @@ static const struct pci_device_id azx_ids[] = {
1966 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM }, 1966 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1967 /* Panther Point */ 1967 /* Panther Point */
1968 { PCI_DEVICE(0x8086, 0x1e20), 1968 { PCI_DEVICE(0x8086, 0x1e20),
1969 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1969 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH_NOPM },
1970 /* Lynx Point */ 1970 /* Lynx Point */
1971 { PCI_DEVICE(0x8086, 0x8c20), 1971 { PCI_DEVICE(0x8086, 0x8c20),
1972 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH }, 1972 .driver_data = AZX_DRIVER_PCH | AZX_DCAPS_INTEL_PCH },
diff --git a/sound/pci/hda/patch_sigmatel.c b/sound/pci/hda/patch_sigmatel.c
index 6d36c5b78805..87eff3173ce9 100644
--- a/sound/pci/hda/patch_sigmatel.c
+++ b/sound/pci/hda/patch_sigmatel.c
@@ -79,6 +79,7 @@ enum {
79 STAC_ALIENWARE_M17X, 79 STAC_ALIENWARE_M17X,
80 STAC_92HD89XX_HP_FRONT_JACK, 80 STAC_92HD89XX_HP_FRONT_JACK,
81 STAC_92HD89XX_HP_Z1_G2_RIGHT_MIC_JACK, 81 STAC_92HD89XX_HP_Z1_G2_RIGHT_MIC_JACK,
82 STAC_92HD73XX_ASUS_MOBO,
82 STAC_92HD73XX_MODELS 83 STAC_92HD73XX_MODELS
83}; 84};
84 85
@@ -1911,7 +1912,18 @@ static const struct hda_fixup stac92hd73xx_fixups[] = {
1911 [STAC_92HD89XX_HP_Z1_G2_RIGHT_MIC_JACK] = { 1912 [STAC_92HD89XX_HP_Z1_G2_RIGHT_MIC_JACK] = {
1912 .type = HDA_FIXUP_PINS, 1913 .type = HDA_FIXUP_PINS,
1913 .v.pins = stac92hd89xx_hp_z1_g2_right_mic_jack_pin_configs, 1914 .v.pins = stac92hd89xx_hp_z1_g2_right_mic_jack_pin_configs,
1914 } 1915 },
1916 [STAC_92HD73XX_ASUS_MOBO] = {
1917 .type = HDA_FIXUP_PINS,
1918 .v.pins = (const struct hda_pintbl[]) {
1919 /* enable 5.1 and SPDIF out */
1920 { 0x0c, 0x01014411 },
1921 { 0x0d, 0x01014410 },
1922 { 0x0e, 0x01014412 },
1923 { 0x22, 0x014b1180 },
1924 { }
1925 }
1926 },
1915}; 1927};
1916 1928
1917static const struct hda_model_fixup stac92hd73xx_models[] = { 1929static const struct hda_model_fixup stac92hd73xx_models[] = {
@@ -1923,6 +1935,7 @@ static const struct hda_model_fixup stac92hd73xx_models[] = {
1923 { .id = STAC_DELL_M6_BOTH, .name = "dell-m6" }, 1935 { .id = STAC_DELL_M6_BOTH, .name = "dell-m6" },
1924 { .id = STAC_DELL_EQ, .name = "dell-eq" }, 1936 { .id = STAC_DELL_EQ, .name = "dell-eq" },
1925 { .id = STAC_ALIENWARE_M17X, .name = "alienware" }, 1937 { .id = STAC_ALIENWARE_M17X, .name = "alienware" },
1938 { .id = STAC_92HD73XX_ASUS_MOBO, .name = "asus-mobo" },
1926 {} 1939 {}
1927}; 1940};
1928 1941
@@ -1975,6 +1988,8 @@ static const struct snd_pci_quirk stac92hd73xx_fixup_tbl[] = {
1975 "HP Z1 G2", STAC_92HD89XX_HP_Z1_G2_RIGHT_MIC_JACK), 1988 "HP Z1 G2", STAC_92HD89XX_HP_Z1_G2_RIGHT_MIC_JACK),
1976 SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2b17, 1989 SND_PCI_QUIRK(PCI_VENDOR_ID_HP, 0x2b17,
1977 "unknown HP", STAC_92HD89XX_HP_FRONT_JACK), 1990 "unknown HP", STAC_92HD89XX_HP_FRONT_JACK),
1991 SND_PCI_QUIRK(PCI_VENDOR_ID_ASUSTEK, 0x83f8, "ASUS AT4NM10",
1992 STAC_92HD73XX_ASUS_MOBO),
1978 {} /* terminator */ 1993 {} /* terminator */
1979}; 1994};
1980 1995
diff --git a/tools/perf/bench/mem-memcpy.c b/tools/perf/bench/mem-memcpy.c
index 6c14afe8c1b1..db1d3a29d97f 100644
--- a/tools/perf/bench/mem-memcpy.c
+++ b/tools/perf/bench/mem-memcpy.c
@@ -289,7 +289,7 @@ static u64 do_memcpy_cycle(const struct routine *r, size_t len, bool prefault)
289 memcpy_t fn = r->fn.memcpy; 289 memcpy_t fn = r->fn.memcpy;
290 int i; 290 int i;
291 291
292 memcpy_alloc_mem(&src, &dst, len); 292 memcpy_alloc_mem(&dst, &src, len);
293 293
294 if (prefault) 294 if (prefault)
295 fn(dst, src, len); 295 fn(dst, src, len);
@@ -312,7 +312,7 @@ static double do_memcpy_gettimeofday(const struct routine *r, size_t len,
312 void *src = NULL, *dst = NULL; 312 void *src = NULL, *dst = NULL;
313 int i; 313 int i;
314 314
315 memcpy_alloc_mem(&src, &dst, len); 315 memcpy_alloc_mem(&dst, &src, len);
316 316
317 if (prefault) 317 if (prefault)
318 fn(dst, src, len); 318 fn(dst, src, len);
diff --git a/tools/perf/config/Makefile.arch b/tools/perf/config/Makefile.arch
index ff95a68741d1..ac8721ffa6c8 100644
--- a/tools/perf/config/Makefile.arch
+++ b/tools/perf/config/Makefile.arch
@@ -21,6 +21,10 @@ ifeq ($(RAW_ARCH),x86_64)
21 endif 21 endif
22endif 22endif
23 23
24ifeq ($(RAW_ARCH),sparc64)
25 ARCH ?= sparc
26endif
27
24ARCH ?= $(RAW_ARCH) 28ARCH ?= $(RAW_ARCH)
25 29
26LP64 := $(shell echo __LP64__ | ${CC} ${CFLAGS} -E -x c - | tail -n 1) 30LP64 := $(shell echo __LP64__ | ${CC} ${CFLAGS} -E -x c - | tail -n 1)
diff --git a/tools/perf/config/feature-checks/Makefile b/tools/perf/config/feature-checks/Makefile
index 42ac05aaf8ac..b32ff3372514 100644
--- a/tools/perf/config/feature-checks/Makefile
+++ b/tools/perf/config/feature-checks/Makefile
@@ -49,7 +49,7 @@ test-hello.bin:
49 $(BUILD) 49 $(BUILD)
50 50
51test-pthread-attr-setaffinity-np.bin: 51test-pthread-attr-setaffinity-np.bin:
52 $(BUILD) -Werror -lpthread 52 $(BUILD) -D_GNU_SOURCE -Werror -lpthread
53 53
54test-stackprotector-all.bin: 54test-stackprotector-all.bin:
55 $(BUILD) -Werror -fstack-protector-all 55 $(BUILD) -Werror -fstack-protector-all
diff --git a/tools/perf/config/feature-checks/test-pthread-attr-setaffinity-np.c b/tools/perf/config/feature-checks/test-pthread-attr-setaffinity-np.c
index 0a0d3ecb4e8a..2b81b72eca23 100644
--- a/tools/perf/config/feature-checks/test-pthread-attr-setaffinity-np.c
+++ b/tools/perf/config/feature-checks/test-pthread-attr-setaffinity-np.c
@@ -5,10 +5,11 @@ int main(void)
5{ 5{
6 int ret = 0; 6 int ret = 0;
7 pthread_attr_t thread_attr; 7 pthread_attr_t thread_attr;
8 cpu_set_t cs;
8 9
9 pthread_attr_init(&thread_attr); 10 pthread_attr_init(&thread_attr);
10 /* don't care abt exact args, just the API itself in libpthread */ 11 /* don't care abt exact args, just the API itself in libpthread */
11 ret = pthread_attr_setaffinity_np(&thread_attr, 0, NULL); 12 ret = pthread_attr_setaffinity_np(&thread_attr, sizeof(cs), &cs);
12 13
13 return ret; 14 return ret;
14} 15}
diff --git a/tools/perf/util/cloexec.c b/tools/perf/util/cloexec.c
index 47b78b3f0325..6da965bdbc2c 100644
--- a/tools/perf/util/cloexec.c
+++ b/tools/perf/util/cloexec.c
@@ -25,6 +25,10 @@ static int perf_flag_probe(void)
25 if (cpu < 0) 25 if (cpu < 0)
26 cpu = 0; 26 cpu = 0;
27 27
28 /*
29 * Using -1 for the pid is a workaround to avoid gratuitous jump label
30 * changes.
31 */
28 while (1) { 32 while (1) {
29 /* check cloexec flag */ 33 /* check cloexec flag */
30 fd = sys_perf_event_open(&attr, pid, cpu, -1, 34 fd = sys_perf_event_open(&attr, pid, cpu, -1,
@@ -47,16 +51,24 @@ static int perf_flag_probe(void)
47 err, strerror_r(err, sbuf, sizeof(sbuf))); 51 err, strerror_r(err, sbuf, sizeof(sbuf)));
48 52
49 /* not supported, confirm error related to PERF_FLAG_FD_CLOEXEC */ 53 /* not supported, confirm error related to PERF_FLAG_FD_CLOEXEC */
50 fd = sys_perf_event_open(&attr, pid, cpu, -1, 0); 54 while (1) {
55 fd = sys_perf_event_open(&attr, pid, cpu, -1, 0);
56 if (fd < 0 && pid == -1 && errno == EACCES) {
57 pid = 0;
58 continue;
59 }
60 break;
61 }
51 err = errno; 62 err = errno;
52 63
64 if (fd >= 0)
65 close(fd);
66
53 if (WARN_ONCE(fd < 0 && err != EBUSY, 67 if (WARN_ONCE(fd < 0 && err != EBUSY,
54 "perf_event_open(..., 0) failed unexpectedly with error %d (%s)\n", 68 "perf_event_open(..., 0) failed unexpectedly with error %d (%s)\n",
55 err, strerror_r(err, sbuf, sizeof(sbuf)))) 69 err, strerror_r(err, sbuf, sizeof(sbuf))))
56 return -1; 70 return -1;
57 71
58 close(fd);
59
60 return 0; 72 return 0;
61} 73}
62 74
diff --git a/tools/perf/util/evlist.h b/tools/perf/util/evlist.h
index c94a9e03ecf1..e99a67632831 100644
--- a/tools/perf/util/evlist.h
+++ b/tools/perf/util/evlist.h
@@ -28,7 +28,7 @@ struct perf_mmap {
28 int mask; 28 int mask;
29 int refcnt; 29 int refcnt;
30 unsigned int prev; 30 unsigned int prev;
31 char event_copy[PERF_SAMPLE_MAX_SIZE]; 31 char event_copy[PERF_SAMPLE_MAX_SIZE] __attribute__((aligned(8)));
32}; 32};
33 33
34struct perf_evlist { 34struct perf_evlist {
diff --git a/tools/perf/util/symbol-elf.c b/tools/perf/util/symbol-elf.c
index b24f9d8727a8..33b7a2aef713 100644
--- a/tools/perf/util/symbol-elf.c
+++ b/tools/perf/util/symbol-elf.c
@@ -11,6 +11,11 @@
11#include <symbol/kallsyms.h> 11#include <symbol/kallsyms.h>
12#include "debug.h" 12#include "debug.h"
13 13
14#ifndef EM_AARCH64
15#define EM_AARCH64 183 /* ARM 64 bit */
16#endif
17
18
14#ifdef HAVE_CPLUS_DEMANGLE_SUPPORT 19#ifdef HAVE_CPLUS_DEMANGLE_SUPPORT
15extern char *cplus_demangle(const char *, int); 20extern char *cplus_demangle(const char *, int);
16 21
diff --git a/tools/thermal/tmon/.gitignore b/tools/thermal/tmon/.gitignore
new file mode 100644
index 000000000000..06e96be65276
--- /dev/null
+++ b/tools/thermal/tmon/.gitignore
@@ -0,0 +1 @@
/tmon
diff --git a/tools/thermal/tmon/Makefile b/tools/thermal/tmon/Makefile
index e775adcbd29f..0788621c8d76 100644
--- a/tools/thermal/tmon/Makefile
+++ b/tools/thermal/tmon/Makefile
@@ -2,8 +2,8 @@ VERSION = 1.0
2 2
3BINDIR=usr/bin 3BINDIR=usr/bin
4WARNFLAGS=-Wall -Wshadow -W -Wformat -Wimplicit-function-declaration -Wimplicit-int 4WARNFLAGS=-Wall -Wshadow -W -Wformat -Wimplicit-function-declaration -Wimplicit-int
5CFLAGS= -O1 ${WARNFLAGS} -fstack-protector 5CFLAGS+= -O1 ${WARNFLAGS} -fstack-protector
6CC=gcc 6CC=$(CROSS_COMPILE)gcc
7 7
8CFLAGS+=-D VERSION=\"$(VERSION)\" 8CFLAGS+=-D VERSION=\"$(VERSION)\"
9LDFLAGS+= 9LDFLAGS+=
@@ -16,12 +16,21 @@ INSTALL_CONFIGFILE=install -m 644 -p
16CONFIG_FILE= 16CONFIG_FILE=
17CONFIG_PATH= 17CONFIG_PATH=
18 18
19# Static builds might require -ltinfo, for instance
20ifneq ($(findstring -static, $(LDFLAGS)),)
21STATIC := --static
22endif
23
24TMON_LIBS=-lm -lpthread
25TMON_LIBS += $(shell pkg-config --libs $(STATIC) panelw ncursesw 2> /dev/null || \
26 pkg-config --libs $(STATIC) panel ncurses 2> /dev/null || \
27 echo -lpanel -lncurses)
19 28
20OBJS = tmon.o tui.o sysfs.o pid.o 29OBJS = tmon.o tui.o sysfs.o pid.o
21OBJS += 30OBJS +=
22 31
23tmon: $(OBJS) Makefile tmon.h 32tmon: $(OBJS) Makefile tmon.h
24 $(CC) ${CFLAGS} $(LDFLAGS) $(OBJS) -o $(TARGET) -lm -lpanel -lncursesw -ltinfo -lpthread 33 $(CC) $(CFLAGS) $(LDFLAGS) $(OBJS) -o $(TARGET) $(TMON_LIBS)
25 34
26valgrind: tmon 35valgrind: tmon
27 sudo valgrind -v --track-origins=yes --tool=memcheck --leak-check=yes --show-reachable=yes --num-callers=20 --track-fds=yes ./$(TARGET) 1> /dev/null 36 sudo valgrind -v --track-origins=yes --tool=memcheck --leak-check=yes --show-reachable=yes --num-callers=20 --track-fds=yes ./$(TARGET) 1> /dev/null
diff --git a/tools/thermal/tmon/tmon.8 b/tools/thermal/tmon/tmon.8
index 0be727cb9892..02d5179803aa 100644
--- a/tools/thermal/tmon/tmon.8
+++ b/tools/thermal/tmon/tmon.8
@@ -55,6 +55,8 @@ The \fB-l --log\fP option write data to /var/tmp/tmon.log
55.PP 55.PP
56The \fB-t --time-interval\fP option sets the polling interval in seconds 56The \fB-t --time-interval\fP option sets the polling interval in seconds
57.PP 57.PP
58The \fB-T --target-temp\fP option sets the initial target temperature
59.PP
58The \fB-v --version\fP option shows the version of \fBtmon \fP 60The \fB-v --version\fP option shows the version of \fBtmon \fP
59.PP 61.PP
60The \fB-z --zone\fP option sets the target therma zone instance to be controlled 62The \fB-z --zone\fP option sets the target therma zone instance to be controlled
diff --git a/tools/thermal/tmon/tmon.c b/tools/thermal/tmon/tmon.c
index 09b7c3218334..9aa19652e8e8 100644
--- a/tools/thermal/tmon/tmon.c
+++ b/tools/thermal/tmon/tmon.c
@@ -64,6 +64,7 @@ void usage()
64 printf(" -h, --help show this help message\n"); 64 printf(" -h, --help show this help message\n");
65 printf(" -l, --log log data to /var/tmp/tmon.log\n"); 65 printf(" -l, --log log data to /var/tmp/tmon.log\n");
66 printf(" -t, --time-interval sampling time interval, > 1 sec.\n"); 66 printf(" -t, --time-interval sampling time interval, > 1 sec.\n");
67 printf(" -T, --target-temp initial target temperature\n");
67 printf(" -v, --version show version\n"); 68 printf(" -v, --version show version\n");
68 printf(" -z, --zone target thermal zone id\n"); 69 printf(" -z, --zone target thermal zone id\n");
69 70
@@ -219,6 +220,7 @@ static struct option opts[] = {
219 { "control", 1, NULL, 'c' }, 220 { "control", 1, NULL, 'c' },
220 { "daemon", 0, NULL, 'd' }, 221 { "daemon", 0, NULL, 'd' },
221 { "time-interval", 1, NULL, 't' }, 222 { "time-interval", 1, NULL, 't' },
223 { "target-temp", 1, NULL, 'T' },
222 { "log", 0, NULL, 'l' }, 224 { "log", 0, NULL, 'l' },
223 { "help", 0, NULL, 'h' }, 225 { "help", 0, NULL, 'h' },
224 { "version", 0, NULL, 'v' }, 226 { "version", 0, NULL, 'v' },
@@ -231,7 +233,7 @@ int main(int argc, char **argv)
231{ 233{
232 int err = 0; 234 int err = 0;
233 int id2 = 0, c; 235 int id2 = 0, c;
234 double yk = 0.0; /* controller output */ 236 double yk = 0.0, temp; /* controller output */
235 int target_tz_index; 237 int target_tz_index;
236 238
237 if (geteuid() != 0) { 239 if (geteuid() != 0) {
@@ -239,7 +241,7 @@ int main(int argc, char **argv)
239 exit(EXIT_FAILURE); 241 exit(EXIT_FAILURE);
240 } 242 }
241 243
242 while ((c = getopt_long(argc, argv, "c:dlht:vgz:", opts, &id2)) != -1) { 244 while ((c = getopt_long(argc, argv, "c:dlht:T:vgz:", opts, &id2)) != -1) {
243 switch (c) { 245 switch (c) {
244 case 'c': 246 case 'c':
245 no_control = 0; 247 no_control = 0;
@@ -254,6 +256,14 @@ int main(int argc, char **argv)
254 if (ticktime < 1) 256 if (ticktime < 1)
255 ticktime = 1; 257 ticktime = 1;
256 break; 258 break;
259 case 'T':
260 temp = strtod(optarg, NULL);
261 if (temp < 0) {
262 fprintf(stderr, "error: temperature must be positive\n");
263 return 1;
264 }
265 target_temp_user = temp;
266 break;
257 case 'l': 267 case 'l':
258 printf("Logging data to /var/tmp/tmon.log\n"); 268 printf("Logging data to /var/tmp/tmon.log\n");
259 logging = 1; 269 logging = 1;
diff --git a/tools/thermal/tmon/tui.c b/tools/thermal/tmon/tui.c
index 89f8ef0e15c8..b5d1c6b22dd3 100644
--- a/tools/thermal/tmon/tui.c
+++ b/tools/thermal/tmon/tui.c
@@ -30,6 +30,18 @@
30 30
31#include "tmon.h" 31#include "tmon.h"
32 32
33#define min(x, y) ({ \
34 typeof(x) _min1 = (x); \
35 typeof(y) _min2 = (y); \
36 (void) (&_min1 == &_min2); \
37 _min1 < _min2 ? _min1 : _min2; })
38
39#define max(x, y) ({ \
40 typeof(x) _max1 = (x); \
41 typeof(y) _max2 = (y); \
42 (void) (&_max1 == &_max2); \
43 _max1 > _max2 ? _max1 : _max2; })
44
33static PANEL *data_panel; 45static PANEL *data_panel;
34static PANEL *dialogue_panel; 46static PANEL *dialogue_panel;
35static PANEL *top; 47static PANEL *top;
@@ -98,6 +110,18 @@ void write_status_bar(int x, char *line)
98 wrefresh(status_bar_window); 110 wrefresh(status_bar_window);
99} 111}
100 112
113/* wrap at 5 */
114#define DIAG_DEV_ROWS 5
115/*
116 * list cooling devices + "set temp" entry; wraps after 5 rows, if they fit
117 */
118static int diag_dev_rows(void)
119{
120 int entries = ptdata.nr_cooling_dev + 1;
121 int rows = max(DIAG_DEV_ROWS, (entries + 1) / 2);
122 return min(rows, entries);
123}
124
101void setup_windows(void) 125void setup_windows(void)
102{ 126{
103 int y_begin = 1; 127 int y_begin = 1;
@@ -122,7 +146,7 @@ void setup_windows(void)
122 * dialogue window is a pop-up, when needed it lays on top of cdev win 146 * dialogue window is a pop-up, when needed it lays on top of cdev win
123 */ 147 */
124 148
125 dialogue_window = subwin(stdscr, ptdata.nr_cooling_dev+5, maxx-50, 149 dialogue_window = subwin(stdscr, diag_dev_rows() + 5, maxx-50,
126 DIAG_Y, DIAG_X); 150 DIAG_Y, DIAG_X);
127 151
128 thermal_data_window = subwin(stdscr, ptdata.nr_tz_sensor * 152 thermal_data_window = subwin(stdscr, ptdata.nr_tz_sensor *
@@ -258,21 +282,26 @@ void show_cooling_device(void)
258} 282}
259 283
260const char DIAG_TITLE[] = "[ TUNABLES ]"; 284const char DIAG_TITLE[] = "[ TUNABLES ]";
261#define DIAG_DEV_ROWS 5
262void show_dialogue(void) 285void show_dialogue(void)
263{ 286{
264 int j, x = 0, y = 0; 287 int j, x = 0, y = 0;
288 int rows, cols;
265 WINDOW *w = dialogue_window; 289 WINDOW *w = dialogue_window;
266 290
267 if (tui_disabled || !w) 291 if (tui_disabled || !w)
268 return; 292 return;
269 293
294 getmaxyx(w, rows, cols);
295
296 /* Silence compiler 'unused' warnings */
297 (void)cols;
298
270 werase(w); 299 werase(w);
271 box(w, 0, 0); 300 box(w, 0, 0);
272 mvwprintw(w, 0, maxx/4, DIAG_TITLE); 301 mvwprintw(w, 0, maxx/4, DIAG_TITLE);
273 /* list all the available tunables */ 302 /* list all the available tunables */
274 for (j = 0; j <= ptdata.nr_cooling_dev; j++) { 303 for (j = 0; j <= ptdata.nr_cooling_dev; j++) {
275 y = j % DIAG_DEV_ROWS; 304 y = j % diag_dev_rows();
276 if (y == 0 && j != 0) 305 if (y == 0 && j != 0)
277 x += 20; 306 x += 20;
278 if (j == ptdata.nr_cooling_dev) 307 if (j == ptdata.nr_cooling_dev)
@@ -283,12 +312,10 @@ void show_dialogue(void)
283 ptdata.cdi[j].type, ptdata.cdi[j].instance); 312 ptdata.cdi[j].type, ptdata.cdi[j].instance);
284 } 313 }
285 wattron(w, A_BOLD); 314 wattron(w, A_BOLD);
286 mvwprintw(w, DIAG_DEV_ROWS+1, 1, "Enter Choice [A-Z]?"); 315 mvwprintw(w, diag_dev_rows()+1, 1, "Enter Choice [A-Z]?");
287 wattroff(w, A_BOLD); 316 wattroff(w, A_BOLD);
288 /* y size of dialogue win is nr cdev + 5, so print legend 317 /* print legend at the bottom line */
289 * at the bottom line 318 mvwprintw(w, rows - 2, 1,
290 */
291 mvwprintw(w, ptdata.nr_cooling_dev+3, 1,
292 "Legend: A=Active, P=Passive, C=Critical"); 319 "Legend: A=Active, P=Passive, C=Critical");
293 320
294 wrefresh(dialogue_window); 321 wrefresh(dialogue_window);
@@ -437,7 +464,7 @@ static void handle_input_choice(int ch)
437 snprintf(buf, sizeof(buf), "New Value for %.10s-%2d: ", 464 snprintf(buf, sizeof(buf), "New Value for %.10s-%2d: ",
438 ptdata.cdi[cdev_id].type, 465 ptdata.cdi[cdev_id].type,
439 ptdata.cdi[cdev_id].instance); 466 ptdata.cdi[cdev_id].instance);
440 write_dialogue_win(buf, DIAG_DEV_ROWS+2, 2); 467 write_dialogue_win(buf, diag_dev_rows() + 2, 2);
441 handle_input_val(cdev_id); 468 handle_input_val(cdev_id);
442 } else { 469 } else {
443 snprintf(buf, sizeof(buf), "Invalid selection %d", ch); 470 snprintf(buf, sizeof(buf), "Invalid selection %d", ch);