2 files changed, 13 insertions, 0 deletions

diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index fcd8036af910..6d7ba37e2257 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -319,6 +319,15 @@ static int omap3_noncore_dpll_program(struct clk_hw_omap *clk, u16 freqsel)
 
         /* Set DPLL multiplier, divider */
         v = omap2_clk_readl(clk, dd->mult_div1_reg);
+
+        /* Handle Duty Cycle Correction */
+        if (dd->dcc_mask) {
+                if (dd->last_rounded_rate >= dd->dcc_rate)
+                        v |= dd->dcc_mask; /* Enable DCC */
+                else
+                        v &= ~dd->dcc_mask; /* Disable DCC */
+        }
+
         v &= ~(dd->mult_mask | dd->div1_mask);
         v |= dd->last_rounded_m << __ffs(dd->mult_mask);
         v |= (dd->last_rounded_n - 1) << __ffs(dd->div1_mask);
diff --git a/include/linux/clk/ti.h b/include/linux/clk/ti.h
index 4231c41bed51..e8d8a35034a5 100644
--- a/include/linux/clk/ti.h
+++ b/include/linux/clk/ti.h
@@ -41,6 +41,8 @@
  * @idlest_reg: register containing the DPLL idle status bitfield
  * @autoidle_mask: mask of the DPLL autoidle mode bitfield in @autoidle_reg
  * @freqsel_mask: mask of the DPLL jitter correction bitfield in @control_reg
+ * @dcc_mask: mask of the DPLL DCC correction bitfield @mult_div1_reg
+ * @dcc_rate: rate atleast which DCC @dcc_mask must be set
  * @idlest_mask: mask of the DPLL idle status bitfield in @idlest_reg
  * @lpmode_mask: mask of the DPLL low-power mode bitfield in @control_reg
  * @m4xen_mask: mask of the DPLL M4X multiplier bitfield in @control_reg
@@ -86,6 +88,8 @@ struct dpll_data {
         u32                     idlest_mask;
         u32                     dco_mask;
         u32                     sddiv_mask;
+        u32                     dcc_mask;
+        unsigned long           dcc_rate;
         u32                     lpmode_mask;
         u32                     m4xen_mask;
         u8                      auto_recal_bit;