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-rw-r--r--drivers/pci/pcie/aer/aerdrv_errprint.c11
-rw-r--r--drivers/pci/quirks.c34
-rw-r--r--drivers/vfio/pci/vfio_pci_config.c2
-rw-r--r--include/ras/ras_event.h48
-rw-r--r--include/uapi/linux/pci_regs.h2
5 files changed, 68 insertions, 29 deletions
diff --git a/drivers/pci/pcie/aer/aerdrv_errprint.c b/drivers/pci/pcie/aer/aerdrv_errprint.c
index 35d06e177917..c6849d9e86ce 100644
--- a/drivers/pci/pcie/aer/aerdrv_errprint.c
+++ b/drivers/pci/pcie/aer/aerdrv_errprint.c
@@ -89,15 +89,17 @@ static const char *aer_correctable_error_string[] = {
89 NULL, 89 NULL,
90 "Replay Timer Timeout", /* Bit Position 12 */ 90 "Replay Timer Timeout", /* Bit Position 12 */
91 "Advisory Non-Fatal", /* Bit Position 13 */ 91 "Advisory Non-Fatal", /* Bit Position 13 */
92 "Corrected Internal Error", /* Bit Position 14 */
93 "Header Log Overflow", /* Bit Position 15 */
92}; 94};
93 95
94static const char *aer_uncorrectable_error_string[] = { 96static const char *aer_uncorrectable_error_string[] = {
95 NULL, 97 "Undefined", /* Bit Position 0 */
96 NULL, 98 NULL,
97 NULL, 99 NULL,
98 NULL, 100 NULL,
99 "Data Link Protocol", /* Bit Position 4 */ 101 "Data Link Protocol", /* Bit Position 4 */
100 NULL, 102 "Surprise Down Error", /* Bit Position 5 */
101 NULL, 103 NULL,
102 NULL, 104 NULL,
103 NULL, 105 NULL,
@@ -113,6 +115,11 @@ static const char *aer_uncorrectable_error_string[] = {
113 "Malformed TLP", /* Bit Position 18 */ 115 "Malformed TLP", /* Bit Position 18 */
114 "ECRC", /* Bit Position 19 */ 116 "ECRC", /* Bit Position 19 */
115 "Unsupported Request", /* Bit Position 20 */ 117 "Unsupported Request", /* Bit Position 20 */
118 "ACS Violation", /* Bit Position 21 */
119 "Uncorrectable Internal Error", /* Bit Position 22 */
120 "MC Blocked TLP", /* Bit Position 23 */
121 "AtomicOp Egress Blocked", /* Bit Position 24 */
122 "TLP Prefix Blocked Error", /* Bit Position 25 */
116}; 123};
117 124
118static const char *aer_agent_string[] = { 125static const char *aer_agent_string[] = {
diff --git a/drivers/pci/quirks.c b/drivers/pci/quirks.c
index 95239e0cfee6..b6c65009e858 100644
--- a/drivers/pci/quirks.c
+++ b/drivers/pci/quirks.c
@@ -3635,14 +3635,16 @@ static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
3635 return acs_flags & ~flags ? 0 : 1; 3635 return acs_flags & ~flags ? 0 : 1;
3636} 3636}
3637 3637
3638static int pci_quirk_solarflare_acs(struct pci_dev *dev, u16 acs_flags) 3638static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
3639{ 3639{
3640 /* 3640 /*
3641 * SV, TB, and UF are not relevant to multifunction endpoints. 3641 * SV, TB, and UF are not relevant to multifunction endpoints.
3642 * 3642 *
3643 * Solarflare indicates that peer-to-peer between functions is not 3643 * Multifunction devices are only required to implement RR, CR, and DT
3644 * possible, therefore RR, CR, and DT are not implemented. Mask 3644 * in their ACS capability if they support peer-to-peer transactions.
3645 * these out as if they were clear in the ACS capabilities register. 3645 * Devices matching this quirk have been verified by the vendor to not
3646 * perform peer-to-peer with other functions, allowing us to mask out
3647 * these bits as if they were unimplemented in the ACS capability.
3646 */ 3648 */
3647 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 3649 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
3648 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 3650 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
@@ -3661,8 +3663,28 @@ static const struct pci_dev_acs_enabled {
3661 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 3663 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
3662 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 3664 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
3663 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 3665 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
3664 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_solarflare_acs }, 3666 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
3665 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_solarflare_acs }, 3667 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
3668 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
3669 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
3670 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
3671 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
3672 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
3673 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
3674 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
3675 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
3676 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
3677 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
3678 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
3679 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
3680 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
3681 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
3682 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
3683 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
3684 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
3685 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
3686 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
3687 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
3666 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 3688 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
3667 { 0 } 3689 { 0 }
3668}; 3690};
diff --git a/drivers/vfio/pci/vfio_pci_config.c b/drivers/vfio/pci/vfio_pci_config.c
index e50790e91f76..1de3f94aa7de 100644
--- a/drivers/vfio/pci/vfio_pci_config.c
+++ b/drivers/vfio/pci/vfio_pci_config.c
@@ -727,7 +727,7 @@ static int __init init_pci_ext_cap_err_perm(struct perm_bits *perm)
727 p_setd(perm, 0, ALL_VIRT, NO_WRITE); 727 p_setd(perm, 0, ALL_VIRT, NO_WRITE);
728 728
729 /* Writable bits mask */ 729 /* Writable bits mask */
730 mask = PCI_ERR_UNC_TRAIN | /* Training */ 730 mask = PCI_ERR_UNC_UND | /* Undefined */
731 PCI_ERR_UNC_DLP | /* Data Link Protocol */ 731 PCI_ERR_UNC_DLP | /* Data Link Protocol */
732 PCI_ERR_UNC_SURPDN | /* Surprise Down */ 732 PCI_ERR_UNC_SURPDN | /* Surprise Down */
733 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */ 733 PCI_ERR_UNC_POISON_TLP | /* Poisoned TLP */
diff --git a/include/ras/ras_event.h b/include/ras/ras_event.h
index 47da53c27ffa..79abb9c71772 100644
--- a/include/ras/ras_event.h
+++ b/include/ras/ras_event.h
@@ -8,6 +8,7 @@
8#include <linux/tracepoint.h> 8#include <linux/tracepoint.h>
9#include <linux/edac.h> 9#include <linux/edac.h>
10#include <linux/ktime.h> 10#include <linux/ktime.h>
11#include <linux/pci.h>
11#include <linux/aer.h> 12#include <linux/aer.h>
12#include <linux/cper.h> 13#include <linux/cper.h>
13 14
@@ -173,25 +174,34 @@ TRACE_EVENT(mc_event,
173 * u8 severity - error severity 0:NONFATAL 1:FATAL 2:CORRECTED 174 * u8 severity - error severity 0:NONFATAL 1:FATAL 2:CORRECTED
174 */ 175 */
175 176
176#define aer_correctable_errors \ 177#define aer_correctable_errors \
177 {BIT(0), "Receiver Error"}, \ 178 {PCI_ERR_COR_RCVR, "Receiver Error"}, \
178 {BIT(6), "Bad TLP"}, \ 179 {PCI_ERR_COR_BAD_TLP, "Bad TLP"}, \
179 {BIT(7), "Bad DLLP"}, \ 180 {PCI_ERR_COR_BAD_DLLP, "Bad DLLP"}, \
180 {BIT(8), "RELAY_NUM Rollover"}, \ 181 {PCI_ERR_COR_REP_ROLL, "RELAY_NUM Rollover"}, \
181 {BIT(12), "Replay Timer Timeout"}, \ 182 {PCI_ERR_COR_REP_TIMER, "Replay Timer Timeout"}, \
182 {BIT(13), "Advisory Non-Fatal"} 183 {PCI_ERR_COR_ADV_NFAT, "Advisory Non-Fatal Error"}, \
183 184 {PCI_ERR_COR_INTERNAL, "Corrected Internal Error"}, \
184#define aer_uncorrectable_errors \ 185 {PCI_ERR_COR_LOG_OVER, "Header Log Overflow"}
185 {BIT(4), "Data Link Protocol"}, \ 186
186 {BIT(12), "Poisoned TLP"}, \ 187#define aer_uncorrectable_errors \
187 {BIT(13), "Flow Control Protocol"}, \ 188 {PCI_ERR_UNC_UND, "Undefined"}, \
188 {BIT(14), "Completion Timeout"}, \ 189 {PCI_ERR_UNC_DLP, "Data Link Protocol Error"}, \
189 {BIT(15), "Completer Abort"}, \ 190 {PCI_ERR_UNC_SURPDN, "Surprise Down Error"}, \
190 {BIT(16), "Unexpected Completion"}, \ 191 {PCI_ERR_UNC_POISON_TLP,"Poisoned TLP"}, \
191 {BIT(17), "Receiver Overflow"}, \ 192 {PCI_ERR_UNC_FCP, "Flow Control Protocol Error"}, \
192 {BIT(18), "Malformed TLP"}, \ 193 {PCI_ERR_UNC_COMP_TIME, "Completion Timeout"}, \
193 {BIT(19), "ECRC"}, \ 194 {PCI_ERR_UNC_COMP_ABORT,"Completer Abort"}, \
194 {BIT(20), "Unsupported Request"} 195 {PCI_ERR_UNC_UNX_COMP, "Unexpected Completion"}, \
196 {PCI_ERR_UNC_RX_OVER, "Receiver Overflow"}, \
197 {PCI_ERR_UNC_MALF_TLP, "Malformed TLP"}, \
198 {PCI_ERR_UNC_ECRC, "ECRC Error"}, \
199 {PCI_ERR_UNC_UNSUP, "Unsupported Request Error"}, \
200 {PCI_ERR_UNC_ACSV, "ACS Violation"}, \
201 {PCI_ERR_UNC_INTN, "Uncorrectable Internal Error"},\
202 {PCI_ERR_UNC_MCBTLP, "MC Blocked TLP"}, \
203 {PCI_ERR_UNC_ATOMEG, "AtomicOp Egress Blocked"}, \
204 {PCI_ERR_UNC_TLPPRE, "TLP Prefix Blocked Error"}
195 205
196TRACE_EVENT(aer_event, 206TRACE_EVENT(aer_event,
197 TP_PROTO(const char *dev_name, 207 TP_PROTO(const char *dev_name,
diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h
index 57d6e56a086a..4a1d0cc38ff2 100644
--- a/include/uapi/linux/pci_regs.h
+++ b/include/uapi/linux/pci_regs.h
@@ -631,7 +631,7 @@
631 631
632/* Advanced Error Reporting */ 632/* Advanced Error Reporting */
633#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */ 633#define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
634#define PCI_ERR_UNC_TRAIN 0x00000001 /* Training */ 634#define PCI_ERR_UNC_UND 0x00000001 /* Undefined */
635#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */ 635#define PCI_ERR_UNC_DLP 0x00000010 /* Data Link Protocol */
636#define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */ 636#define PCI_ERR_UNC_SURPDN 0x00000020 /* Surprise Down */
637#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */ 637#define PCI_ERR_UNC_POISON_TLP 0x00001000 /* Poisoned TLP */