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-rw-r--r--arch/arm/mach-exynos/mct.c57
1 files changed, 36 insertions, 21 deletions
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index ffd1323ed7db..1061db4118aa 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -65,9 +65,22 @@ enum {
65 MCT_INT_PPI 65 MCT_INT_PPI
66}; 66};
67 67
68enum {
69 MCT_G0_IRQ,
70 MCT_G1_IRQ,
71 MCT_G2_IRQ,
72 MCT_G3_IRQ,
73 MCT_L0_IRQ,
74 MCT_L1_IRQ,
75 MCT_L2_IRQ,
76 MCT_L3_IRQ,
77 MCT_NR_IRQS,
78};
79
68static void __iomem *reg_base; 80static void __iomem *reg_base;
69static unsigned long clk_rate; 81static unsigned long clk_rate;
70static unsigned int mct_int_type; 82static unsigned int mct_int_type;
83static int mct_irqs[MCT_NR_IRQS];
71 84
72struct mct_clock_event_device { 85struct mct_clock_event_device {
73 struct clock_event_device *evt; 86 struct clock_event_device *evt;
@@ -282,11 +295,7 @@ static void exynos4_clockevent_init(void)
282 mct_comp_device.cpumask = cpumask_of(0); 295 mct_comp_device.cpumask = cpumask_of(0);
283 clockevents_config_and_register(&mct_comp_device, clk_rate, 296 clockevents_config_and_register(&mct_comp_device, clk_rate,
284 0xf, 0xffffffff); 297 0xf, 0xffffffff);
285 298 setup_irq(mct_irqs[MCT_G0_IRQ], &mct_comp_event_irq);
286 if (soc_is_exynos5250())
287 setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
288 else
289 setup_irq(EXYNOS4_IRQ_MCT_G0, &mct_comp_event_irq);
290} 299}
291 300
292#ifdef CONFIG_LOCAL_TIMERS 301#ifdef CONFIG_LOCAL_TIMERS
@@ -410,7 +419,6 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
410{ 419{
411 struct mct_clock_event_device *mevt; 420 struct mct_clock_event_device *mevt;
412 unsigned int cpu = smp_processor_id(); 421 unsigned int cpu = smp_processor_id();
413 int mct_lx_irq;
414 422
415 mevt = this_cpu_ptr(&percpu_mct_tick); 423 mevt = this_cpu_ptr(&percpu_mct_tick);
416 mevt->evt = evt; 424 mevt->evt = evt;
@@ -431,21 +439,17 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
431 439
432 if (mct_int_type == MCT_INT_SPI) { 440 if (mct_int_type == MCT_INT_SPI) {
433 if (cpu == 0) { 441 if (cpu == 0) {
434 mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L0 :
435 EXYNOS5_IRQ_MCT_L0;
436 mct_tick0_event_irq.dev_id = mevt; 442 mct_tick0_event_irq.dev_id = mevt;
437 evt->irq = mct_lx_irq; 443 evt->irq = mct_irqs[MCT_L0_IRQ];
438 setup_irq(mct_lx_irq, &mct_tick0_event_irq); 444 setup_irq(evt->irq, &mct_tick0_event_irq);
439 } else { 445 } else {
440 mct_lx_irq = soc_is_exynos4210() ? EXYNOS4_IRQ_MCT_L1 :
441 EXYNOS5_IRQ_MCT_L1;
442 mct_tick1_event_irq.dev_id = mevt; 446 mct_tick1_event_irq.dev_id = mevt;
443 evt->irq = mct_lx_irq; 447 evt->irq = mct_irqs[MCT_L1_IRQ];
444 setup_irq(mct_lx_irq, &mct_tick1_event_irq); 448 setup_irq(evt->irq, &mct_tick1_event_irq);
445 irq_set_affinity(mct_lx_irq, cpumask_of(1)); 449 irq_set_affinity(evt->irq, cpumask_of(1));
446 } 450 }
447 } else { 451 } else {
448 enable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 0); 452 enable_percpu_irq(mct_irqs[MCT_L0_IRQ], 0);
449 } 453 }
450 454
451 return 0; 455 return 0;
@@ -461,7 +465,7 @@ static void exynos4_local_timer_stop(struct clock_event_device *evt)
461 else 465 else
462 remove_irq(evt->irq, &mct_tick1_event_irq); 466 remove_irq(evt->irq, &mct_tick1_event_irq);
463 else 467 else
464 disable_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER); 468 disable_percpu_irq(mct_irqs[MCT_L0_IRQ]);
465} 469}
466 470
467static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = { 471static struct local_timer_ops exynos4_mct_tick_ops __cpuinitdata = {
@@ -483,11 +487,11 @@ static void __init exynos4_timer_resources(void)
483 if (mct_int_type == MCT_INT_PPI) { 487 if (mct_int_type == MCT_INT_PPI) {
484 int err; 488 int err;
485 489
486 err = request_percpu_irq(EXYNOS_IRQ_MCT_LOCALTIMER, 490 err = request_percpu_irq(mct_irqs[MCT_L0_IRQ],
487 exynos4_mct_tick_isr, "MCT", 491 exynos4_mct_tick_isr, "MCT",
488 &percpu_mct_tick); 492 &percpu_mct_tick);
489 WARN(err, "MCT: can't request IRQ %d (%d)\n", 493 WARN(err, "MCT: can't request IRQ %d (%d)\n",
490 EXYNOS_IRQ_MCT_LOCALTIMER, err); 494 mct_irqs[MCT_L0_IRQ], err);
491 } 495 }
492 496
493 local_timer_register(&exynos4_mct_tick_ops); 497 local_timer_register(&exynos4_mct_tick_ops);
@@ -501,10 +505,21 @@ void __init exynos4_timer_init(void)
501 return; 505 return;
502 } 506 }
503 507
504 if ((soc_is_exynos4210()) || (soc_is_exynos5250())) 508 if (soc_is_exynos4210()) {
509 mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
510 mct_irqs[MCT_L0_IRQ] = EXYNOS4_IRQ_MCT_L0;
511 mct_irqs[MCT_L1_IRQ] = EXYNOS4_IRQ_MCT_L1;
505 mct_int_type = MCT_INT_SPI; 512 mct_int_type = MCT_INT_SPI;
506 else 513 } else if (soc_is_exynos5250()) {
514 mct_irqs[MCT_G0_IRQ] = EXYNOS5_IRQ_MCT_G0;
515 mct_irqs[MCT_L0_IRQ] = EXYNOS5_IRQ_MCT_L0;
516 mct_irqs[MCT_L1_IRQ] = EXYNOS5_IRQ_MCT_L1;
517 mct_int_type = MCT_INT_SPI;
518 } else {
519 mct_irqs[MCT_G0_IRQ] = EXYNOS4_IRQ_MCT_G0;
520 mct_irqs[MCT_L0_IRQ] = EXYNOS_IRQ_MCT_LOCALTIMER;
507 mct_int_type = MCT_INT_PPI; 521 mct_int_type = MCT_INT_PPI;
522 }
508 523
509 exynos4_timer_resources(); 524 exynos4_timer_resources();
510 exynos4_clocksource_init(); 525 exynos4_clocksource_init();