diff options
-rw-r--r-- | arch/arm/mach-s3c2440/mach-osiris.c | 18 | ||||
-rw-r--r-- | include/asm-arm/arch-s3c2410/osiris-cpld.h | 14 | ||||
-rw-r--r-- | include/asm-arm/arch-s3c2410/osiris-map.h | 19 |
3 files changed, 33 insertions, 18 deletions
diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c index 4d6c7a574c1a..4525bb0f8513 100644 --- a/arch/arm/mach-s3c2440/mach-osiris.c +++ b/arch/arm/mach-s3c2440/mach-osiris.c | |||
@@ -65,6 +65,11 @@ static struct map_desc osiris_iodesc[] __initdata = { | |||
65 | /* CPLD control registers */ | 65 | /* CPLD control registers */ |
66 | 66 | ||
67 | { | 67 | { |
68 | .virtual = (u32)OSIRIS_VA_CTRL0, | ||
69 | .pfn = __phys_to_pfn(OSIRIS_PA_CTRL0), | ||
70 | .length = SZ_16K, | ||
71 | .type = MT_DEVICE, | ||
72 | }, { | ||
68 | .virtual = (u32)OSIRIS_VA_CTRL1, | 73 | .virtual = (u32)OSIRIS_VA_CTRL1, |
69 | .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1), | 74 | .pfn = __phys_to_pfn(OSIRIS_PA_CTRL1), |
70 | .length = SZ_16K, | 75 | .length = SZ_16K, |
@@ -74,6 +79,11 @@ static struct map_desc osiris_iodesc[] __initdata = { | |||
74 | .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2), | 79 | .pfn = __phys_to_pfn(OSIRIS_PA_CTRL2), |
75 | .length = SZ_16K, | 80 | .length = SZ_16K, |
76 | .type = MT_DEVICE, | 81 | .type = MT_DEVICE, |
82 | }, { | ||
83 | .virtual = (u32)OSIRIS_VA_IDREG, | ||
84 | .pfn = __phys_to_pfn(OSIRIS_PA_IDREG), | ||
85 | .length = SZ_16K, | ||
86 | .type = MT_DEVICE, | ||
77 | }, | 87 | }, |
78 | }; | 88 | }; |
79 | 89 | ||
@@ -195,13 +205,13 @@ static void osiris_nand_select(struct s3c2410_nand_set *set, int slot) | |||
195 | pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n", | 205 | pr_debug("osiris_nand: selecting slot %d (set %p,%p)\n", |
196 | slot, set, set->nr_map); | 206 | slot, set, set->nr_map); |
197 | 207 | ||
198 | tmp = __raw_readb(OSIRIS_VA_CTRL1); | 208 | tmp = __raw_readb(OSIRIS_VA_CTRL0); |
199 | tmp &= ~OSIRIS_CTRL1_NANDSEL; | 209 | tmp &= ~OSIRIS_CTRL0_NANDSEL; |
200 | tmp |= slot; | 210 | tmp |= slot; |
201 | 211 | ||
202 | pr_debug("osiris_nand: ctrl1 now %02x\n", tmp); | 212 | pr_debug("osiris_nand: ctrl0 now %02x\n", tmp); |
203 | 213 | ||
204 | __raw_writeb(tmp, OSIRIS_VA_CTRL1); | 214 | __raw_writeb(tmp, OSIRIS_VA_CTRL0); |
205 | } | 215 | } |
206 | 216 | ||
207 | static struct s3c2410_platform_nand osiris_nand_info = { | 217 | static struct s3c2410_platform_nand osiris_nand_info = { |
diff --git a/include/asm-arm/arch-s3c2410/osiris-cpld.h b/include/asm-arm/arch-s3c2410/osiris-cpld.h index 3b6498468d62..a3253e979efe 100644 --- a/include/asm-arm/arch-s3c2410/osiris-cpld.h +++ b/include/asm-arm/arch-s3c2410/osiris-cpld.h | |||
@@ -14,12 +14,14 @@ | |||
14 | #ifndef __ASM_ARCH_OSIRISCPLD_H | 14 | #ifndef __ASM_ARCH_OSIRISCPLD_H |
15 | #define __ASM_ARCH_OSIRISCPLD_H | 15 | #define __ASM_ARCH_OSIRISCPLD_H |
16 | 16 | ||
17 | /* CTRL1 - NAND WP control */ | 17 | /* CTRL0 - NAND WP control */ |
18 | 18 | ||
19 | #define OSIRIS_CTRL1_NANDSEL (0x3) | 19 | #define OSIRIS_CTRL0_NANDSEL (0x3) |
20 | #define OSIRIS_CTRL1_BOOT_INT (1<<3) | 20 | #define OSIRIS_CTRL0_BOOT_INT (1<<3) |
21 | #define OSIRIS_CTRL1_PCMCIA (1<<4) | 21 | #define OSIRIS_CTRL0_PCMCIA (1<<4) |
22 | #define OSIRIS_CTRL1_PCMCIA_nWAIT (1<<6) | 22 | #define OSIRIS_CTRL0_PCMCIA_nWAIT (1<<6) |
23 | #define OSIRIS_CTRL1_PCMCIA_nIOIS16 (1<<7) | 23 | #define OSIRIS_CTRL0_PCMCIA_nIOIS16 (1<<7) |
24 | |||
25 | #define OSIRIS_ID_REVMASK (0x7) | ||
24 | 26 | ||
25 | #endif /* __ASM_ARCH_OSIRISCPLD_H */ | 27 | #endif /* __ASM_ARCH_OSIRISCPLD_H */ |
diff --git a/include/asm-arm/arch-s3c2410/osiris-map.h b/include/asm-arm/arch-s3c2410/osiris-map.h index a14164dfa525..b5c74d2b9aaa 100644 --- a/include/asm-arm/arch-s3c2410/osiris-map.h +++ b/include/asm-arm/arch-s3c2410/osiris-map.h | |||
@@ -24,16 +24,19 @@ | |||
24 | 24 | ||
25 | /* we put the CPLD registers next, to get them out of the way */ | 25 | /* we put the CPLD registers next, to get them out of the way */ |
26 | 26 | ||
27 | #define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00000000) | 27 | #define OSIRIS_VA_CTRL0 OSIRIS_IOADDR(0x00000000) |
28 | #define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD) | 28 | #define OSIRIS_PA_CTRL0 (OSIRIS_PA_CPLD) |
29 | 29 | ||
30 | #define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00100000) | 30 | #define OSIRIS_VA_CTRL1 OSIRIS_IOADDR(0x00100000) |
31 | #define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (1<<23)) | 31 | #define OSIRIS_PA_CTRL1 (OSIRIS_PA_CPLD + (1<<23)) |
32 | 32 | ||
33 | #define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00200000) | 33 | #define OSIRIS_VA_CTRL2 OSIRIS_IOADDR(0x00200000) |
34 | #define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) | 34 | #define OSIRIS_PA_CTRL2 (OSIRIS_PA_CPLD + (2<<23)) |
35 | 35 | ||
36 | #define OSIRIS_VA_CTRL4 OSIRIS_IOADDR(0x00300000) | 36 | #define OSIRIS_VA_CTRL3 OSIRIS_IOADDR(0x00300000) |
37 | #define OSIRIS_PA_CTRL4 (OSIRIS_PA_CPLD + (3<<23)) | 37 | #define OSIRIS_PA_CTRL3 (OSIRIS_PA_CPLD + (2<<23)) |
38 | |||
39 | #define OSIRIS_VA_IDREG OSIRIS_IOADDR(0x00700000) | ||
40 | #define OSIRIS_PA_IDREG (OSIRIS_PA_CPLD + (7<<23)) | ||
38 | 41 | ||
39 | #endif /* __ASM_ARCH_OSIRISMAP_H */ | 42 | #endif /* __ASM_ARCH_OSIRISMAP_H */ |