aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--drivers/gpu/drm/radeon/r600_cs.c94
-rw-r--r--drivers/gpu/drm/radeon/r600d.h17
-rw-r--r--drivers/gpu/drm/radeon/radeon_drv.c3
-rw-r--r--drivers/gpu/drm/radeon/reg_srcs/r6008
4 files changed, 101 insertions, 21 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index 3dab49cb1d4a..1bec5b8bba18 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -47,13 +47,17 @@ struct r600_cs_track {
47 u32 npipes; 47 u32 npipes;
48 /* value we track */ 48 /* value we track */
49 u32 sq_config; 49 u32 sq_config;
50 u32 log_nsamples;
50 u32 nsamples; 51 u32 nsamples;
51 u32 cb_color_base_last[8]; 52 u32 cb_color_base_last[8];
52 struct radeon_bo *cb_color_bo[8]; 53 struct radeon_bo *cb_color_bo[8];
53 u64 cb_color_bo_mc[8]; 54 u64 cb_color_bo_mc[8];
54 u32 cb_color_bo_offset[8]; 55 u64 cb_color_bo_offset[8];
55 struct radeon_bo *cb_color_frag_bo[8]; /* unused */ 56 struct radeon_bo *cb_color_frag_bo[8];
56 struct radeon_bo *cb_color_tile_bo[8]; /* unused */ 57 u64 cb_color_frag_offset[8];
58 struct radeon_bo *cb_color_tile_bo[8];
59 u64 cb_color_tile_offset[8];
60 u32 cb_color_mask[8];
57 u32 cb_color_info[8]; 61 u32 cb_color_info[8];
58 u32 cb_color_view[8]; 62 u32 cb_color_view[8];
59 u32 cb_color_size_idx[8]; /* unused */ 63 u32 cb_color_size_idx[8]; /* unused */
@@ -349,10 +353,6 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
349 unsigned array_mode; 353 unsigned array_mode;
350 u32 format; 354 u32 format;
351 355
352 if (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
353 dev_warn(p->dev, "FMASK or CMASK buffer are not supported by this kernel\n");
354 return -EINVAL;
355 }
356 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i]; 356 size = radeon_bo_size(track->cb_color_bo[i]) - track->cb_color_bo_offset[i];
357 format = G_0280A0_FORMAT(track->cb_color_info[i]); 357 format = G_0280A0_FORMAT(track->cb_color_info[i]);
358 if (!r600_fmt_is_valid_color(format)) { 358 if (!r600_fmt_is_valid_color(format)) {
@@ -441,7 +441,7 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
441 * broken userspace. 441 * broken userspace.
442 */ 442 */
443 } else { 443 } else {
444 dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big (%d %d) (%d %d %d)\n", 444 dev_warn(p->dev, "%s offset[%d] %d %llu %d %lu too big (%d %d) (%d %d %d)\n",
445 __func__, i, array_mode, 445 __func__, i, array_mode,
446 track->cb_color_bo_offset[i], tmp, 446 track->cb_color_bo_offset[i], tmp,
447 radeon_bo_size(track->cb_color_bo[i]), 447 radeon_bo_size(track->cb_color_bo[i]),
@@ -458,6 +458,51 @@ static int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i)
458 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) | 458 tmp = S_028060_PITCH_TILE_MAX((pitch / 8) - 1) |
459 S_028060_SLICE_TILE_MAX(slice_tile_max - 1); 459 S_028060_SLICE_TILE_MAX(slice_tile_max - 1);
460 ib[track->cb_color_size_idx[i]] = tmp; 460 ib[track->cb_color_size_idx[i]] = tmp;
461
462 /* FMASK/CMASK */
463 switch (G_0280A0_TILE_MODE(track->cb_color_info[i])) {
464 case V_0280A0_TILE_DISABLE:
465 break;
466 case V_0280A0_FRAG_ENABLE:
467 if (track->nsamples > 1) {
468 uint32_t tile_max = G_028100_FMASK_TILE_MAX(track->cb_color_mask[i]);
469 /* the tile size is 8x8, but the size is in units of bits.
470 * for bytes, do just * 8. */
471 uint32_t bytes = track->nsamples * track->log_nsamples * 8 * (tile_max + 1);
472
473 if (bytes + track->cb_color_frag_offset[i] >
474 radeon_bo_size(track->cb_color_frag_bo[i])) {
475 dev_warn(p->dev, "%s FMASK_TILE_MAX too large "
476 "(tile_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
477 __func__, tile_max, bytes,
478 track->cb_color_frag_offset[i],
479 radeon_bo_size(track->cb_color_frag_bo[i]));
480 return -EINVAL;
481 }
482 }
483 /* fall through */
484 case V_0280A0_CLEAR_ENABLE:
485 {
486 uint32_t block_max = G_028100_CMASK_BLOCK_MAX(track->cb_color_mask[i]);
487 /* One block = 128x128 pixels, one 8x8 tile has 4 bits..
488 * (128*128) / (8*8) / 2 = 128 bytes per block. */
489 uint32_t bytes = (block_max + 1) * 128;
490
491 if (bytes + track->cb_color_tile_offset[i] >
492 radeon_bo_size(track->cb_color_tile_bo[i])) {
493 dev_warn(p->dev, "%s CMASK_BLOCK_MAX too large "
494 "(block_max=%u, bytes=%u, offset=%llu, bo_size=%lu)\n",
495 __func__, block_max, bytes,
496 track->cb_color_tile_offset[i],
497 radeon_bo_size(track->cb_color_tile_bo[i]));
498 return -EINVAL;
499 }
500 break;
501 }
502 default:
503 dev_warn(p->dev, "%s invalid tile mode\n", __func__);
504 return -EINVAL;
505 }
461 return 0; 506 return 0;
462} 507}
463 508
@@ -1231,6 +1276,7 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1231 break; 1276 break;
1232 case R_028C04_PA_SC_AA_CONFIG: 1277 case R_028C04_PA_SC_AA_CONFIG:
1233 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx)); 1278 tmp = G_028C04_MSAA_NUM_SAMPLES(radeon_get_ib_value(p, idx));
1279 track->log_nsamples = tmp;
1234 track->nsamples = 1 << tmp; 1280 track->nsamples = 1 << tmp;
1235 track->cb_dirty = true; 1281 track->cb_dirty = true;
1236 break; 1282 break;
@@ -1312,16 +1358,21 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1312 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1358 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1313 return -EINVAL; 1359 return -EINVAL;
1314 } 1360 }
1315 ib[idx] = track->cb_color_base_last[tmp];
1316 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp]; 1361 track->cb_color_frag_bo[tmp] = track->cb_color_bo[tmp];
1362 track->cb_color_frag_offset[tmp] = track->cb_color_bo_offset[tmp];
1363 ib[idx] = track->cb_color_base_last[tmp];
1317 } else { 1364 } else {
1318 r = r600_cs_packet_next_reloc(p, &reloc); 1365 r = r600_cs_packet_next_reloc(p, &reloc);
1319 if (r) { 1366 if (r) {
1320 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1367 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1321 return -EINVAL; 1368 return -EINVAL;
1322 } 1369 }
1323 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1324 track->cb_color_frag_bo[tmp] = reloc->robj; 1370 track->cb_color_frag_bo[tmp] = reloc->robj;
1371 track->cb_color_frag_offset[tmp] = (u64)ib[idx] << 8;
1372 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1373 }
1374 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1375 track->cb_dirty = true;
1325 } 1376 }
1326 break; 1377 break;
1327 case R_0280C0_CB_COLOR0_TILE: 1378 case R_0280C0_CB_COLOR0_TILE:
@@ -1338,16 +1389,35 @@ static int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx)
1338 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg); 1389 dev_err(p->dev, "Broken old userspace ? no cb_color0_base supplied before trying to write 0x%08X\n", reg);
1339 return -EINVAL; 1390 return -EINVAL;
1340 } 1391 }
1341 ib[idx] = track->cb_color_base_last[tmp];
1342 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp]; 1392 track->cb_color_tile_bo[tmp] = track->cb_color_bo[tmp];
1393 track->cb_color_tile_offset[tmp] = track->cb_color_bo_offset[tmp];
1394 ib[idx] = track->cb_color_base_last[tmp];
1343 } else { 1395 } else {
1344 r = r600_cs_packet_next_reloc(p, &reloc); 1396 r = r600_cs_packet_next_reloc(p, &reloc);
1345 if (r) { 1397 if (r) {
1346 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg); 1398 dev_err(p->dev, "bad SET_CONTEXT_REG 0x%04X\n", reg);
1347 return -EINVAL; 1399 return -EINVAL;
1348 } 1400 }
1349 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1350 track->cb_color_tile_bo[tmp] = reloc->robj; 1401 track->cb_color_tile_bo[tmp] = reloc->robj;
1402 track->cb_color_tile_offset[tmp] = (u64)ib[idx] << 8;
1403 ib[idx] += (u32)((reloc->lobj.gpu_offset >> 8) & 0xffffffff);
1404 }
1405 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1406 track->cb_dirty = true;
1407 }
1408 break;
1409 case R_028100_CB_COLOR0_MASK:
1410 case R_028104_CB_COLOR1_MASK:
1411 case R_028108_CB_COLOR2_MASK:
1412 case R_02810C_CB_COLOR3_MASK:
1413 case R_028110_CB_COLOR4_MASK:
1414 case R_028114_CB_COLOR5_MASK:
1415 case R_028118_CB_COLOR6_MASK:
1416 case R_02811C_CB_COLOR7_MASK:
1417 tmp = (reg - R_028100_CB_COLOR0_MASK) / 4;
1418 track->cb_color_mask[tmp] = ib[idx];
1419 if (G_0280A0_TILE_MODE(track->cb_color_info[tmp])) {
1420 track->cb_dirty = true;
1351 } 1421 }
1352 break; 1422 break;
1353 case CB_COLOR0_BASE: 1423 case CB_COLOR0_BASE:
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index fd328f4c3ea8..bdb69a63062f 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -92,6 +92,20 @@
92#define R_028094_CB_COLOR5_VIEW 0x028094 92#define R_028094_CB_COLOR5_VIEW 0x028094
93#define R_028098_CB_COLOR6_VIEW 0x028098 93#define R_028098_CB_COLOR6_VIEW 0x028098
94#define R_02809C_CB_COLOR7_VIEW 0x02809C 94#define R_02809C_CB_COLOR7_VIEW 0x02809C
95#define R_028100_CB_COLOR0_MASK 0x028100
96#define S_028100_CMASK_BLOCK_MAX(x) (((x) & 0xFFF) << 0)
97#define G_028100_CMASK_BLOCK_MAX(x) (((x) >> 0) & 0xFFF)
98#define C_028100_CMASK_BLOCK_MAX 0xFFFFF000
99#define S_028100_FMASK_TILE_MAX(x) (((x) & 0xFFFFF) << 12)
100#define G_028100_FMASK_TILE_MAX(x) (((x) >> 12) & 0xFFFFF)
101#define C_028100_FMASK_TILE_MAX 0x00000FFF
102#define R_028104_CB_COLOR1_MASK 0x028104
103#define R_028108_CB_COLOR2_MASK 0x028108
104#define R_02810C_CB_COLOR3_MASK 0x02810C
105#define R_028110_CB_COLOR4_MASK 0x028110
106#define R_028114_CB_COLOR5_MASK 0x028114
107#define R_028118_CB_COLOR6_MASK 0x028118
108#define R_02811C_CB_COLOR7_MASK 0x02811C
95#define CB_COLOR0_INFO 0x280a0 109#define CB_COLOR0_INFO 0x280a0
96# define CB_FORMAT(x) ((x) << 2) 110# define CB_FORMAT(x) ((x) << 2)
97# define CB_ARRAY_MODE(x) ((x) << 8) 111# define CB_ARRAY_MODE(x) ((x) << 8)
@@ -1400,6 +1414,9 @@
1400#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18) 1414#define S_0280A0_TILE_MODE(x) (((x) & 0x3) << 18)
1401#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3) 1415#define G_0280A0_TILE_MODE(x) (((x) >> 18) & 0x3)
1402#define C_0280A0_TILE_MODE 0xFFF3FFFF 1416#define C_0280A0_TILE_MODE 0xFFF3FFFF
1417#define V_0280A0_TILE_DISABLE 0
1418#define V_0280A0_CLEAR_ENABLE 1
1419#define V_0280A0_FRAG_ENABLE 2
1403#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20) 1420#define S_0280A0_BLEND_CLAMP(x) (((x) & 0x1) << 20)
1404#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1) 1421#define G_0280A0_BLEND_CLAMP(x) (((x) >> 20) & 0x1)
1405#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF 1422#define C_0280A0_BLEND_CLAMP 0xFFEFFFFF
diff --git a/drivers/gpu/drm/radeon/radeon_drv.c b/drivers/gpu/drm/radeon/radeon_drv.c
index d7269f48d37c..27d22d709c90 100644
--- a/drivers/gpu/drm/radeon/radeon_drv.c
+++ b/drivers/gpu/drm/radeon/radeon_drv.c
@@ -62,9 +62,10 @@
62 * 2.18.0 - r600-eg: allow "invalid" DB formats 62 * 2.18.0 - r600-eg: allow "invalid" DB formats
63 * 2.19.0 - r600-eg: MSAA textures 63 * 2.19.0 - r600-eg: MSAA textures
64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query 64 * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
65 * 2.21.0 - r600-r700: FMASK and CMASK
65 */ 66 */
66#define KMS_DRIVER_MAJOR 2 67#define KMS_DRIVER_MAJOR 2
67#define KMS_DRIVER_MINOR 20 68#define KMS_DRIVER_MINOR 21
68#define KMS_DRIVER_PATCHLEVEL 0 69#define KMS_DRIVER_PATCHLEVEL 0
69int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags); 70int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
70int radeon_driver_unload_kms(struct drm_device *dev); 71int radeon_driver_unload_kms(struct drm_device *dev);
diff --git a/drivers/gpu/drm/radeon/reg_srcs/r600 b/drivers/gpu/drm/radeon/reg_srcs/r600
index 5e659b034d9a..f93e45d869f4 100644
--- a/drivers/gpu/drm/radeon/reg_srcs/r600
+++ b/drivers/gpu/drm/radeon/reg_srcs/r600
@@ -744,14 +744,6 @@ r600 0x9400
7440x00028C38 CB_CLRCMP_DST 7440x00028C38 CB_CLRCMP_DST
7450x00028C3C CB_CLRCMP_MSK 7450x00028C3C CB_CLRCMP_MSK
7460x00028C34 CB_CLRCMP_SRC 7460x00028C34 CB_CLRCMP_SRC
7470x00028100 CB_COLOR0_MASK
7480x00028104 CB_COLOR1_MASK
7490x00028108 CB_COLOR2_MASK
7500x0002810C CB_COLOR3_MASK
7510x00028110 CB_COLOR4_MASK
7520x00028114 CB_COLOR5_MASK
7530x00028118 CB_COLOR6_MASK
7540x0002811C CB_COLOR7_MASK
7550x00028808 CB_COLOR_CONTROL 7470x00028808 CB_COLOR_CONTROL
7560x0002842C CB_FOG_BLUE 7480x0002842C CB_FOG_BLUE
7570x00028428 CB_FOG_GREEN 7490x00028428 CB_FOG_GREEN
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-28 10:58:41 -0500