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-rw-r--r--Documentation/devicetree/bindings/arm/shmobile.txt2
-rw-r--r--arch/arm/boot/dts/Makefile6
-rw-r--r--arch/arm/boot/dts/emev2-kzm9d.dts13
-rw-r--r--arch/arm/boot/dts/emev2.dtsi10
-rw-r--r--arch/arm/boot/dts/r8a7740.dtsi79
-rw-r--r--arch/arm/boot/dts/r8a7790.dtsi102
-rw-r--r--arch/arm/boot/dts/r8a7791-henninger.dts11
-rw-r--r--arch/arm/boot/dts/r8a7791-koelsch.dts50
-rw-r--r--arch/arm/boot/dts/r8a7791.dtsi122
-rw-r--r--arch/arm/boot/dts/r8a7794-alt.dts13
-rw-r--r--arch/arm/boot/dts/r8a7794.dtsi157
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g-reference.dts366
-rw-r--r--arch/arm/boot/dts/sh73a0-kzm9g.dts378
-rw-r--r--arch/arm/boot/dts/sh73a0.dtsi245
-rw-r--r--arch/arm/mach-shmobile/Kconfig19
-rw-r--r--arch/arm/mach-shmobile/Makefile5
-rw-r--r--arch/arm/mach-shmobile/Makefile.boot1
-rw-r--r--arch/arm/mach-shmobile/board-kzm9g-reference.c62
-rw-r--r--arch/arm/mach-shmobile/include/mach/zboot.h2
-rw-r--r--arch/arm/mach-shmobile/setup-sh73a0.c19
-rw-r--r--arch/arm/mach-shmobile/sh73a0.h1
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7790.c4
-rw-r--r--arch/arm/mach-shmobile/smp-r8a7791.c2
-rw-r--r--arch/arm/mach-shmobile/smp-sh73a0.c2
-rw-r--r--include/dt-bindings/clock/r8a7790-clock.h3
-rw-r--r--include/dt-bindings/clock/r8a7791-clock.h3
-rw-r--r--include/dt-bindings/clock/sh73a0-clock.h3
27 files changed, 1164 insertions, 516 deletions
diff --git a/Documentation/devicetree/bindings/arm/shmobile.txt b/Documentation/devicetree/bindings/arm/shmobile.txt
index 2f8043ee438d..c4f19b2e7dd9 100644
--- a/Documentation/devicetree/bindings/arm/shmobile.txt
+++ b/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -53,8 +53,6 @@ Boards:
53 compatible = "renesas,kzm9d", "renesas,emev2" 53 compatible = "renesas,kzm9d", "renesas,emev2"
54 - Kyoto Microcomputer Co. KZM-A9-GT 54 - Kyoto Microcomputer Co. KZM-A9-GT
55 compatible = "renesas,kzm9g", "renesas,sh73a0" 55 compatible = "renesas,kzm9g", "renesas,sh73a0"
56 - Kyoto Microcomputer Co. KZM-A9-GT - Reference Device Tree Implementation
57 compatible = "renesas,kzm9g-reference", "renesas,sh73a0"
58 - Lager (RTP0RC7790SEB00010S) 56 - Lager (RTP0RC7790SEB00010S)
59 compatible = "renesas,lager", "renesas,r8a7790" 57 compatible = "renesas,lager", "renesas,r8a7790"
60 - Marzen 58 - Marzen
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 5d258e00c5e7..7f098c992198 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -468,8 +468,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_LEGACY) += \
468 r8a7778-bockw.dtb \ 468 r8a7778-bockw.dtb \
469 r8a7778-bockw-reference.dtb \ 469 r8a7778-bockw-reference.dtb \
470 r8a7779-marzen.dtb \ 470 r8a7779-marzen.dtb \
471 sh73a0-kzm9g.dtb \ 471 sh73a0-kzm9g.dtb
472 sh73a0-kzm9g-reference.dtb
473dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \ 472dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
474 emev2-kzm9d.dtb \ 473 emev2-kzm9d.dtb \
475 r7s72100-genmai.dtb \ 474 r7s72100-genmai.dtb \
@@ -480,7 +479,8 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
480 r8a7790-lager.dtb \ 479 r8a7790-lager.dtb \
481 r8a7791-henninger.dtb \ 480 r8a7791-henninger.dtb \
482 r8a7791-koelsch.dtb \ 481 r8a7791-koelsch.dtb \
483 r8a7794-alt.dtb 482 r8a7794-alt.dtb \
483 sh73a0-kzm9g.dtb
484dtb-$(CONFIG_ARCH_SOCFPGA) += \ 484dtb-$(CONFIG_ARCH_SOCFPGA) += \
485 socfpga_arria5_socdk.dtb \ 485 socfpga_arria5_socdk.dtb \
486 socfpga_arria10_socdk.dtb \ 486 socfpga_arria10_socdk.dtb \
diff --git a/arch/arm/boot/dts/emev2-kzm9d.dts b/arch/arm/boot/dts/emev2-kzm9d.dts
index 667d323e80a3..19446273e4a7 100644
--- a/arch/arm/boot/dts/emev2-kzm9d.dts
+++ b/arch/arm/boot/dts/emev2-kzm9d.dts
@@ -94,3 +94,16 @@
94 vdd33a-supply = <&reg_3p3v>; 94 vdd33a-supply = <&reg_3p3v>;
95 }; 95 };
96}; 96};
97
98&pfc {
99 uart1_pins: uart@e1030000 {
100 renesas,groups = "uart1_ctrl", "uart1_data";
101 renesas,function = "uart1";
102 };
103};
104
105&uart1 {
106 pinctrl-0 = <&uart1_pins>;
107 pinctrl-names = "default";
108 status = "okay";
109};
diff --git a/arch/arm/boot/dts/emev2.dtsi b/arch/arm/boot/dts/emev2.dtsi
index cc7bfe0ba40a..bb45694d91bc 100644
--- a/arch/arm/boot/dts/emev2.dtsi
+++ b/arch/arm/boot/dts/emev2.dtsi
@@ -169,12 +169,18 @@
169 clock-names = "sclk"; 169 clock-names = "sclk";
170 }; 170 };
171 171
172 pfc: pfc@e0140200 {
173 compatible = "renesas,pfc-emev2";
174 reg = <0xe0140200 0x100>;
175 };
176
172 gpio0: gpio@e0050000 { 177 gpio0: gpio@e0050000 {
173 compatible = "renesas,em-gio"; 178 compatible = "renesas,em-gio";
174 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>; 179 reg = <0xe0050000 0x2c>, <0xe0050040 0x20>;
175 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>, 180 interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>,
176 <0 68 IRQ_TYPE_LEVEL_HIGH>; 181 <0 68 IRQ_TYPE_LEVEL_HIGH>;
177 gpio-controller; 182 gpio-controller;
183 gpio-ranges = <&pfc 0 0 32>;
178 #gpio-cells = <2>; 184 #gpio-cells = <2>;
179 ngpios = <32>; 185 ngpios = <32>;
180 interrupt-controller; 186 interrupt-controller;
@@ -186,6 +192,7 @@
186 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>, 192 interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>,
187 <0 70 IRQ_TYPE_LEVEL_HIGH>; 193 <0 70 IRQ_TYPE_LEVEL_HIGH>;
188 gpio-controller; 194 gpio-controller;
195 gpio-ranges = <&pfc 0 32 32>;
189 #gpio-cells = <2>; 196 #gpio-cells = <2>;
190 ngpios = <32>; 197 ngpios = <32>;
191 interrupt-controller; 198 interrupt-controller;
@@ -197,6 +204,7 @@
197 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>, 204 interrupts = <0 71 IRQ_TYPE_LEVEL_HIGH>,
198 <0 72 IRQ_TYPE_LEVEL_HIGH>; 205 <0 72 IRQ_TYPE_LEVEL_HIGH>;
199 gpio-controller; 206 gpio-controller;
207 gpio-ranges = <&pfc 0 64 32>;
200 #gpio-cells = <2>; 208 #gpio-cells = <2>;
201 ngpios = <32>; 209 ngpios = <32>;
202 interrupt-controller; 210 interrupt-controller;
@@ -208,6 +216,7 @@
208 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>, 216 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>,
209 <0 74 IRQ_TYPE_LEVEL_HIGH>; 217 <0 74 IRQ_TYPE_LEVEL_HIGH>;
210 gpio-controller; 218 gpio-controller;
219 gpio-ranges = <&pfc 0 96 32>;
211 #gpio-cells = <2>; 220 #gpio-cells = <2>;
212 ngpios = <32>; 221 ngpios = <32>;
213 interrupt-controller; 222 interrupt-controller;
@@ -219,6 +228,7 @@
219 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>, 228 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>,
220 <0 76 IRQ_TYPE_LEVEL_HIGH>; 229 <0 76 IRQ_TYPE_LEVEL_HIGH>;
221 gpio-controller; 230 gpio-controller;
231 gpio-ranges = <&pfc 0 128 31>;
222 #gpio-cells = <2>; 232 #gpio-cells = <2>;
223 ngpios = <31>; 233 ngpios = <31>;
224 interrupt-controller; 234 interrupt-controller;
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi
index 8a092605d641..83c1c3ca1b8f 100644
--- a/arch/arm/boot/dts/r8a7740.dtsi
+++ b/arch/arm/boot/dts/r8a7740.dtsi
@@ -431,6 +431,18 @@
431 clock-frequency = <27000000>; 431 clock-frequency = <27000000>;
432 clock-output-names = "dv"; 432 clock-output-names = "dv";
433 }; 433 };
434 fmsick_clk: fmsick_clk {
435 compatible = "fixed-clock";
436 #clock-cells = <0>;
437 clock-frequency = <0>;
438 clock-output-names = "fmsick";
439 };
440 fmsock_clk: fmsock_clk {
441 compatible = "fixed-clock";
442 #clock-cells = <0>;
443 clock-frequency = <0>;
444 clock-output-names = "fmsock";
445 };
434 fsiack_clk: fsiack_clk { 446 fsiack_clk: fsiack_clk {
435 compatible = "fixed-clock"; 447 compatible = "fixed-clock";
436 #clock-cells = <0>; 448 #clock-cells = <0>;
@@ -459,13 +471,78 @@
459 }; 471 };
460 472
461 /* Variable factor clocks (DIV6) */ 473 /* Variable factor clocks (DIV6) */
474 vclk1_clk: vclk1_clk@e6150008 {
475 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
476 reg = <0xe6150008 4>;
477 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
478 <&cpg_clocks R8A7740_CLK_USB24S>,
479 <&extal1_div2_clk>, <&extalr_clk>, <0>,
480 <0>;
481 #clock-cells = <0>;
482 clock-output-names = "vclk1";
483 };
484 vclk2_clk: vclk2_clk@e615000c {
485 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
486 reg = <0xe615000c 4>;
487 clocks = <&pllc1_div2_clk>, <0>, <&dv_clk>,
488 <&cpg_clocks R8A7740_CLK_USB24S>,
489 <&extal1_div2_clk>, <&extalr_clk>, <0>,
490 <0>;
491 #clock-cells = <0>;
492 clock-output-names = "vclk2";
493 };
494 fmsi_clk: fmsi_clk@e6150010 {
495 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
496 reg = <0xe6150010 4>;
497 clocks = <&pllc1_div2_clk>, <&fmsick_clk>, <0>, <0>;
498 #clock-cells = <0>;
499 clock-output-names = "fmsi";
500 };
501 fmso_clk: fmso_clk@e6150014 {
502 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
503 reg = <0xe6150014 4>;
504 clocks = <&pllc1_div2_clk>, <&fmsock_clk>, <0>, <0>;
505 #clock-cells = <0>;
506 clock-output-names = "fmso";
507 };
508 fsia_clk: fsia_clk@e6150018 {
509 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
510 reg = <0xe6150018 4>;
511 clocks = <&pllc1_div2_clk>, <&fsiack_clk>, <0>, <0>;
512 #clock-cells = <0>;
513 clock-output-names = "fsia";
514 };
462 sub_clk: sub_clk@e6150080 { 515 sub_clk: sub_clk@e6150080 {
463 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock"; 516 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
464 reg = <0xe6150080 4>; 517 reg = <0xe6150080 4>;
465 clocks = <&pllc1_div2_clk>; 518 clocks = <&pllc1_div2_clk>,
519 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
466 #clock-cells = <0>; 520 #clock-cells = <0>;
467 clock-output-names = "sub"; 521 clock-output-names = "sub";
468 }; 522 };
523 spu_clk: spu_clk@e6150084 {
524 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
525 reg = <0xe6150084 4>;
526 clocks = <&pllc1_div2_clk>,
527 <&cpg_clocks R8A7740_CLK_USB24S>, <0>, <0>;
528 #clock-cells = <0>;
529 clock-output-names = "spu";
530 };
531 vou_clk: vou_clk@e6150088 {
532 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
533 reg = <0xe6150088 4>;
534 clocks = <&pllc1_div2_clk>, <&extal1_clk>, <&dv_clk>,
535 <0>;
536 #clock-cells = <0>;
537 clock-output-names = "vou";
538 };
539 stpro_clk: stpro_clk@e615009c {
540 compatible = "renesas,r8a7740-div6-clock", "renesas,cpg-div6-clock";
541 reg = <0xe615009c 4>;
542 clocks = <&cpg_clocks R8A7740_CLK_PLLC0>;
543 #clock-cells = <0>;
544 clock-output-names = "stpro";
545 };
469 546
470 /* Fixed factor clocks */ 547 /* Fixed factor clocks */
471 pllc1_div2_clk: pllc1_div2_clk { 548 pllc1_div2_clk: pllc1_div2_clk {
diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 4b38fc920114..c6c0a0c8f1be 100644
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -792,6 +792,26 @@
792 }; 792 };
793 }; 793 };
794 794
795 can0: can@e6e80000 {
796 compatible = "renesas,can-r8a7790";
797 reg = <0 0xe6e80000 0 0x1000>;
798 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
799 clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
800 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
801 clock-names = "clkp1", "clkp2", "can_clk";
802 status = "disabled";
803 };
804
805 can1: can@e6e88000 {
806 compatible = "renesas,can-r8a7790";
807 reg = <0 0xe6e88000 0 0x1000>;
808 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
810 <&cpg_clocks R8A7790_CLK_RCAN>, <&can_clk>;
811 clock-names = "clkp1", "clkp2", "can_clk";
812 status = "disabled";
813 };
814
795 clocks { 815 clocks {
796 #address-cells = <2>; 816 #address-cells = <2>;
797 #size-cells = <2>; 817 #size-cells = <2>;
@@ -838,16 +858,34 @@
838 clock-output-names = "audio_clk_c"; 858 clock-output-names = "audio_clk_c";
839 }; 859 };
840 860
861 /* External USB clock - can be overridden by the board */
862 usb_extal_clk: usb_extal_clk {
863 compatible = "fixed-clock";
864 #clock-cells = <0>;
865 clock-frequency = <48000000>;
866 clock-output-names = "usb_extal";
867 };
868
869 /* External CAN clock */
870 can_clk: can_clk {
871 compatible = "fixed-clock";
872 #clock-cells = <0>;
873 /* This value must be overridden by the board. */
874 clock-frequency = <0>;
875 clock-output-names = "can_clk";
876 status = "disabled";
877 };
878
841 /* Special CPG clocks */ 879 /* Special CPG clocks */
842 cpg_clocks: cpg_clocks@e6150000 { 880 cpg_clocks: cpg_clocks@e6150000 {
843 compatible = "renesas,r8a7790-cpg-clocks", 881 compatible = "renesas,r8a7790-cpg-clocks",
844 "renesas,rcar-gen2-cpg-clocks"; 882 "renesas,rcar-gen2-cpg-clocks";
845 reg = <0 0xe6150000 0 0x1000>; 883 reg = <0 0xe6150000 0 0x1000>;
846 clocks = <&extal_clk>; 884 clocks = <&extal_clk &usb_extal_clk>;
847 #clock-cells = <1>; 885 #clock-cells = <1>;
848 clock-output-names = "main", "pll0", "pll1", "pll3", 886 clock-output-names = "main", "pll0", "pll1", "pll3",
849 "lb", "qspi", "sdh", "sd0", "sd1", 887 "lb", "qspi", "sdh", "sd0", "sd1",
850 "z"; 888 "z", "rcan", "adsp";
851 }; 889 };
852 890
853 /* Variable factor clocks */ 891 /* Variable factor clocks */
@@ -1121,13 +1159,16 @@
1121 mstp5_clks: mstp5_clks@e6150144 { 1159 mstp5_clks: mstp5_clks@e6150144 {
1122 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1160 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
1123 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1161 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1124 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; 1162 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
1163 <&extal_clk>, <&p_clk>;
1125 #clock-cells = <1>; 1164 #clock-cells = <1>;
1126 clock-indices = < 1165 clock-indices = <
1127 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1 1166 R8A7790_CLK_AUDIO_DMAC0 R8A7790_CLK_AUDIO_DMAC1
1128 R8A7790_CLK_THERMAL R8A7790_CLK_PWM 1167 R8A7790_CLK_ADSP_MOD R8A7790_CLK_THERMAL
1168 R8A7790_CLK_PWM
1129 >; 1169 >;
1130 clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; 1170 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1171 "thermal", "pwm";
1131 }; 1172 };
1132 mstp7_clks: mstp7_clks@e615014c { 1173 mstp7_clks: mstp7_clks@e615014c {
1133 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; 1174 compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1465,4 +1506,55 @@
1465 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; }; 1506 ssi9: ssi@9 { interrupts = <0 379 IRQ_TYPE_LEVEL_HIGH>; };
1466 }; 1507 };
1467 }; 1508 };
1509
1510 ipmmu_sy0: mmu@e6280000 {
1511 compatible = "renesas,ipmmu-vmsa";
1512 reg = <0 0xe6280000 0 0x1000>;
1513 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1514 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1515 #iommu-cells = <1>;
1516 status = "disabled";
1517 };
1518
1519 ipmmu_sy1: mmu@e6290000 {
1520 compatible = "renesas,ipmmu-vmsa";
1521 reg = <0 0xe6290000 0 0x1000>;
1522 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1523 #iommu-cells = <1>;
1524 status = "disabled";
1525 };
1526
1527 ipmmu_ds: mmu@e6740000 {
1528 compatible = "renesas,ipmmu-vmsa";
1529 reg = <0 0xe6740000 0 0x1000>;
1530 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1531 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1532 #iommu-cells = <1>;
1533 status = "disabled";
1534 };
1535
1536 ipmmu_mp: mmu@ec680000 {
1537 compatible = "renesas,ipmmu-vmsa";
1538 reg = <0 0xec680000 0 0x1000>;
1539 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1540 #iommu-cells = <1>;
1541 status = "disabled";
1542 };
1543
1544 ipmmu_mx: mmu@fe951000 {
1545 compatible = "renesas,ipmmu-vmsa";
1546 reg = <0 0xfe951000 0 0x1000>;
1547 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1548 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1549 #iommu-cells = <1>;
1550 status = "disabled";
1551 };
1552
1553 ipmmu_rt: mmu@ffc80000 {
1554 compatible = "renesas,ipmmu-vmsa";
1555 reg = <0 0xffc80000 0 0x1000>;
1556 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1557 #iommu-cells = <1>;
1558 status = "disabled";
1559 };
1468}; 1560};
diff --git a/arch/arm/boot/dts/r8a7791-henninger.dts b/arch/arm/boot/dts/r8a7791-henninger.dts
index d2ebf11f9881..e33e4047b0b0 100644
--- a/arch/arm/boot/dts/r8a7791-henninger.dts
+++ b/arch/arm/boot/dts/r8a7791-henninger.dts
@@ -141,6 +141,11 @@
141 renesas,groups = "vin0_data8", "vin0_clk"; 141 renesas,groups = "vin0_data8", "vin0_clk";
142 renesas,function = "vin0"; 142 renesas,function = "vin0";
143 }; 143 };
144
145 can0_pins: can0 {
146 renesas,groups = "can0_data";
147 renesas,function = "can0";
148 };
144}; 149};
145 150
146&scif0 { 151&scif0 {
@@ -307,3 +312,9 @@
307 }; 312 };
308 }; 313 };
309}; 314};
315
316&can0 {
317 pinctrl-0 = <&can0_pins>;
318 pinctrl-names = "default";
319 status = "okay";
320};
diff --git a/arch/arm/boot/dts/r8a7791-koelsch.dts b/arch/arm/boot/dts/r8a7791-koelsch.dts
index a3c27807f6c5..624bb2c30513 100644
--- a/arch/arm/boot/dts/r8a7791-koelsch.dts
+++ b/arch/arm/boot/dts/r8a7791-koelsch.dts
@@ -258,6 +258,17 @@
258 system-clock-frequency = <11289600>; 258 system-clock-frequency = <11289600>;
259 }; 259 };
260 }; 260 };
261
262 hdmi-out {
263 compatible = "hdmi-connector";
264 type = "a";
265
266 port {
267 hdmi_con: endpoint {
268 remote-endpoint = <&adv7511_out>;
269 };
270 };
271 };
261}; 272};
262 273
263&du { 274&du {
@@ -266,6 +277,11 @@
266 status = "okay"; 277 status = "okay";
267 278
268 ports { 279 ports {
280 port@0 {
281 endpoint {
282 remote-endpoint = <&adv7511_in>;
283 };
284 };
269 port@1 { 285 port@1 {
270 lvds_connector: endpoint { 286 lvds_connector: endpoint {
271 }; 287 };
@@ -284,7 +300,7 @@
284 }; 300 };
285 301
286 du_pins: du { 302 du_pins: du {
287 renesas,groups = "du_rgb666", "du_sync", "du_clk_out_0"; 303 renesas,groups = "du_rgb666", "du_sync", "du_disp", "du_clk_out_0";
288 renesas,function = "du"; 304 renesas,function = "du";
289 }; 305 };
290 306
@@ -506,6 +522,38 @@
506 }; 522 };
507 }; 523 };
508 524
525 hdmi@39 {
526 compatible = "adi,adv7511w";
527 reg = <0x39>;
528 interrupt-parent = <&gpio3>;
529 interrupts = <29 IRQ_TYPE_EDGE_FALLING>;
530
531 adi,input-depth = <8>;
532 adi,input-colorspace = "rgb";
533 adi,input-clock = "1x";
534 adi,input-style = <1>;
535 adi,input-justification = "evenly";
536
537 ports {
538 #address-cells = <1>;
539 #size-cells = <0>;
540
541 port@0 {
542 reg = <0>;
543 adv7511_in: endpoint {
544 remote-endpoint = <&du_out_rgb>;
545 };
546 };
547
548 port@1 {
549 reg = <1>;
550 adv7511_out: endpoint {
551 remote-endpoint = <&hdmi_con>;
552 };
553 };
554 };
555 };
556
509 eeprom@50 { 557 eeprom@50 {
510 compatible = "renesas,24c02"; 558 compatible = "renesas,24c02";
511 reg = <0x50>; 559 reg = <0x50>;
diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index e35812a0d8d4..1e593a2b55fa 100644
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -816,6 +816,26 @@
816 }; 816 };
817 }; 817 };
818 818
819 can0: can@e6e80000 {
820 compatible = "renesas,can-r8a7791";
821 reg = <0 0xe6e80000 0 0x1000>;
822 interrupts = <0 186 IRQ_TYPE_LEVEL_HIGH>;
823 clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
824 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
825 clock-names = "clkp1", "clkp2", "can_clk";
826 status = "disabled";
827 };
828
829 can1: can@e6e88000 {
830 compatible = "renesas,can-r8a7791";
831 reg = <0 0xe6e88000 0 0x1000>;
832 interrupts = <0 187 IRQ_TYPE_LEVEL_HIGH>;
833 clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
834 <&cpg_clocks R8A7791_CLK_RCAN>, <&can_clk>;
835 clock-names = "clkp1", "clkp2", "can_clk";
836 status = "disabled";
837 };
838
819 clocks { 839 clocks {
820 #address-cells = <2>; 840 #address-cells = <2>;
821 #size-cells = <2>; 841 #size-cells = <2>;
@@ -862,31 +882,50 @@
862 status = "disabled"; 882 status = "disabled";
863 }; 883 };
864 884
885 /* External USB clock - can be overridden by the board */
886 usb_extal_clk: usb_extal_clk {
887 compatible = "fixed-clock";
888 #clock-cells = <0>;
889 clock-frequency = <48000000>;
890 clock-output-names = "usb_extal";
891 };
892
893 /* External CAN clock */
894 can_clk: can_clk {
895 compatible = "fixed-clock";
896 #clock-cells = <0>;
897 /* This value must be overridden by the board. */
898 clock-frequency = <0>;
899 clock-output-names = "can_clk";
900 status = "disabled";
901 };
902
865 /* Special CPG clocks */ 903 /* Special CPG clocks */
866 cpg_clocks: cpg_clocks@e6150000 { 904 cpg_clocks: cpg_clocks@e6150000 {
867 compatible = "renesas,r8a7791-cpg-clocks", 905 compatible = "renesas,r8a7791-cpg-clocks",
868 "renesas,rcar-gen2-cpg-clocks"; 906 "renesas,rcar-gen2-cpg-clocks";
869 reg = <0 0xe6150000 0 0x1000>; 907 reg = <0 0xe6150000 0 0x1000>;
870 clocks = <&extal_clk>; 908 clocks = <&extal_clk &usb_extal_clk>;
871 #clock-cells = <1>; 909 #clock-cells = <1>;
872 clock-output-names = "main", "pll0", "pll1", "pll3", 910 clock-output-names = "main", "pll0", "pll1", "pll3",
873 "lb", "qspi", "sdh", "sd0", "z"; 911 "lb", "qspi", "sdh", "sd0", "z",
912 "rcan", "adsp";
874 }; 913 };
875 914
876 /* Variable factor clocks */ 915 /* Variable factor clocks */
877 sd1_clk: sd2_clk@e6150078 { 916 sd2_clk: sd2_clk@e6150078 {
878 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 917 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
879 reg = <0 0xe6150078 0 4>; 918 reg = <0 0xe6150078 0 4>;
880 clocks = <&pll1_div2_clk>; 919 clocks = <&pll1_div2_clk>;
881 #clock-cells = <0>; 920 #clock-cells = <0>;
882 clock-output-names = "sd1"; 921 clock-output-names = "sd2";
883 }; 922 };
884 sd2_clk: sd3_clk@e615026c { 923 sd3_clk: sd3_clk@e615026c {
885 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 924 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
886 reg = <0 0xe615026c 0 4>; 925 reg = <0 0xe615026c 0 4>;
887 clocks = <&pll1_div2_clk>; 926 clocks = <&pll1_div2_clk>;
888 #clock-cells = <0>; 927 #clock-cells = <0>;
889 clock-output-names = "sd2"; 928 clock-output-names = "sd3";
890 }; 929 };
891 mmc0_clk: mmc0_clk@e6150240 { 930 mmc0_clk: mmc0_clk@e6150240 {
892 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock"; 931 compatible = "renesas,r8a7791-div6-clock", "renesas,cpg-div6-clock";
@@ -1107,7 +1146,7 @@
1107 mstp3_clks: mstp3_clks@e615013c { 1146 mstp3_clks: mstp3_clks@e615013c {
1108 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1147 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1109 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 1148 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
1110 clocks = <&cp_clk>, <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7791_CLK_SD0>, 1149 clocks = <&cp_clk>, <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7791_CLK_SD0>,
1111 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, 1150 <&mmc0_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
1112 <&hp_clk>, <&hp_clk>; 1151 <&hp_clk>, <&hp_clk>;
1113 #clock-cells = <1>; 1152 #clock-cells = <1>;
@@ -1125,13 +1164,16 @@
1125 mstp5_clks: mstp5_clks@e6150144 { 1164 mstp5_clks: mstp5_clks@e6150144 {
1126 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1165 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
1127 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>; 1166 reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
1128 clocks = <&hp_clk>, <&hp_clk>, <&extal_clk>, <&p_clk>; 1167 clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7791_CLK_ADSP>,
1168 <&extal_clk>, <&p_clk>;
1129 #clock-cells = <1>; 1169 #clock-cells = <1>;
1130 clock-indices = < 1170 clock-indices = <
1131 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1 1171 R8A7791_CLK_AUDIO_DMAC0 R8A7791_CLK_AUDIO_DMAC1
1132 R8A7791_CLK_THERMAL R8A7791_CLK_PWM 1172 R8A7791_CLK_ADSP_MOD R8A7791_CLK_THERMAL
1173 R8A7791_CLK_PWM
1133 >; 1174 >;
1134 clock-output-names = "audmac0", "audmac1", "thermal", "pwm"; 1175 clock-output-names = "audmac0", "audmac1", "adsp_mod",
1176 "thermal", "pwm";
1135 }; 1177 };
1136 mstp7_clks: mstp7_clks@e615014c { 1178 mstp7_clks: mstp7_clks@e615014c {
1137 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks"; 1179 compatible = "renesas,r8a7791-mstp-clocks", "renesas,cpg-mstp-clocks";
@@ -1384,6 +1426,66 @@
1384 status = "disabled"; 1426 status = "disabled";
1385 }; 1427 };
1386 1428
1429 ipmmu_sy0: mmu@e6280000 {
1430 compatible = "renesas,ipmmu-vmsa";
1431 reg = <0 0xe6280000 0 0x1000>;
1432 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
1433 <0 224 IRQ_TYPE_LEVEL_HIGH>;
1434 #iommu-cells = <1>;
1435 status = "disabled";
1436 };
1437
1438 ipmmu_sy1: mmu@e6290000 {
1439 compatible = "renesas,ipmmu-vmsa";
1440 reg = <0 0xe6290000 0 0x1000>;
1441 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
1442 #iommu-cells = <1>;
1443 status = "disabled";
1444 };
1445
1446 ipmmu_ds: mmu@e6740000 {
1447 compatible = "renesas,ipmmu-vmsa";
1448 reg = <0 0xe6740000 0 0x1000>;
1449 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
1450 <0 199 IRQ_TYPE_LEVEL_HIGH>;
1451 #iommu-cells = <1>;
1452 status = "disabled";
1453 };
1454
1455 ipmmu_mp: mmu@ec680000 {
1456 compatible = "renesas,ipmmu-vmsa";
1457 reg = <0 0xec680000 0 0x1000>;
1458 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
1459 #iommu-cells = <1>;
1460 status = "disabled";
1461 };
1462
1463 ipmmu_mx: mmu@fe951000 {
1464 compatible = "renesas,ipmmu-vmsa";
1465 reg = <0 0xfe951000 0 0x1000>;
1466 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
1467 <0 221 IRQ_TYPE_LEVEL_HIGH>;
1468 #iommu-cells = <1>;
1469 status = "disabled";
1470 };
1471
1472 ipmmu_rt: mmu@ffc80000 {
1473 compatible = "renesas,ipmmu-vmsa";
1474 reg = <0 0xffc80000 0 0x1000>;
1475 interrupts = <0 307 IRQ_TYPE_LEVEL_HIGH>;
1476 #iommu-cells = <1>;
1477 status = "disabled";
1478 };
1479
1480 ipmmu_gp: mmu@e62a0000 {
1481 compatible = "renesas,ipmmu-vmsa";
1482 reg = <0 0xe62a0000 0 0x1000>;
1483 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
1484 <0 261 IRQ_TYPE_LEVEL_HIGH>;
1485 #iommu-cells = <1>;
1486 status = "disabled";
1487 };
1488
1387 rcar_sound: rcar_sound@ec500000 { 1489 rcar_sound: rcar_sound@ec500000 {
1388 /* 1490 /*
1389 * #sound-dai-cells is required 1491 * #sound-dai-cells is required
diff --git a/arch/arm/boot/dts/r8a7794-alt.dts b/arch/arm/boot/dts/r8a7794-alt.dts
index 0d848e605071..25bf434433b1 100644
--- a/arch/arm/boot/dts/r8a7794-alt.dts
+++ b/arch/arm/boot/dts/r8a7794-alt.dts
@@ -43,6 +43,19 @@
43 status = "okay"; 43 status = "okay";
44}; 44};
45 45
46&ether {
47 phy-handle = <&phy1>;
48 renesas,ether-link-active-low;
49 status = "okay";
50
51 phy1: ethernet-phy@1 {
52 reg = <1>;
53 interrupt-parent = <&irqc0>;
54 interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
55 micrel,led-mode = <1>;
56 };
57};
58
46&scif2 { 59&scif2 {
47 status = "okay"; 60 status = "okay";
48}; 61};
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi
index 8f78da5ef10b..7a3ffa51a8bf 100644
--- a/arch/arm/boot/dts/r8a7794.dtsi
+++ b/arch/arm/boot/dts/r8a7794.dtsi
@@ -107,6 +107,66 @@
107 <0 17 IRQ_TYPE_LEVEL_HIGH>; 107 <0 17 IRQ_TYPE_LEVEL_HIGH>;
108 }; 108 };
109 109
110 dmac0: dma-controller@e6700000 {
111 compatible = "renesas,rcar-dmac";
112 reg = <0 0xe6700000 0 0x20000>;
113 interrupts = <0 197 IRQ_TYPE_LEVEL_HIGH
114 0 200 IRQ_TYPE_LEVEL_HIGH
115 0 201 IRQ_TYPE_LEVEL_HIGH
116 0 202 IRQ_TYPE_LEVEL_HIGH
117 0 203 IRQ_TYPE_LEVEL_HIGH
118 0 204 IRQ_TYPE_LEVEL_HIGH
119 0 205 IRQ_TYPE_LEVEL_HIGH
120 0 206 IRQ_TYPE_LEVEL_HIGH
121 0 207 IRQ_TYPE_LEVEL_HIGH
122 0 208 IRQ_TYPE_LEVEL_HIGH
123 0 209 IRQ_TYPE_LEVEL_HIGH
124 0 210 IRQ_TYPE_LEVEL_HIGH
125 0 211 IRQ_TYPE_LEVEL_HIGH
126 0 212 IRQ_TYPE_LEVEL_HIGH
127 0 213 IRQ_TYPE_LEVEL_HIGH
128 0 214 IRQ_TYPE_LEVEL_HIGH>;
129 interrupt-names = "error",
130 "ch0", "ch1", "ch2", "ch3",
131 "ch4", "ch5", "ch6", "ch7",
132 "ch8", "ch9", "ch10", "ch11",
133 "ch12", "ch13", "ch14";
134 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC0>;
135 clock-names = "fck";
136 #dma-cells = <1>;
137 dma-channels = <15>;
138 };
139
140 dmac1: dma-controller@e6720000 {
141 compatible = "renesas,rcar-dmac";
142 reg = <0 0xe6720000 0 0x20000>;
143 interrupts = <0 220 IRQ_TYPE_LEVEL_HIGH
144 0 216 IRQ_TYPE_LEVEL_HIGH
145 0 217 IRQ_TYPE_LEVEL_HIGH
146 0 218 IRQ_TYPE_LEVEL_HIGH
147 0 219 IRQ_TYPE_LEVEL_HIGH
148 0 308 IRQ_TYPE_LEVEL_HIGH
149 0 309 IRQ_TYPE_LEVEL_HIGH
150 0 310 IRQ_TYPE_LEVEL_HIGH
151 0 311 IRQ_TYPE_LEVEL_HIGH
152 0 312 IRQ_TYPE_LEVEL_HIGH
153 0 313 IRQ_TYPE_LEVEL_HIGH
154 0 314 IRQ_TYPE_LEVEL_HIGH
155 0 315 IRQ_TYPE_LEVEL_HIGH
156 0 316 IRQ_TYPE_LEVEL_HIGH
157 0 317 IRQ_TYPE_LEVEL_HIGH
158 0 318 IRQ_TYPE_LEVEL_HIGH>;
159 interrupt-names = "error",
160 "ch0", "ch1", "ch2", "ch3",
161 "ch4", "ch5", "ch6", "ch7",
162 "ch8", "ch9", "ch10", "ch11",
163 "ch12", "ch13", "ch14";
164 clocks = <&mstp2_clks R8A7794_CLK_SYS_DMAC1>;
165 clock-names = "fck";
166 #dma-cells = <1>;
167 dma-channels = <15>;
168 };
169
110 scifa0: serial@e6c40000 { 170 scifa0: serial@e6c40000 {
111 compatible = "renesas,scifa-r8a7794", "renesas,scifa"; 171 compatible = "renesas,scifa-r8a7794", "renesas,scifa";
112 reg = <0 0xe6c40000 0 64>; 172 reg = <0 0xe6c40000 0 64>;
@@ -269,6 +329,41 @@
269 status = "disabled"; 329 status = "disabled";
270 }; 330 };
271 331
332 ether: ethernet@ee700000 {
333 compatible = "renesas,ether-r8a7794";
334 reg = <0 0xee700000 0 0x400>;
335 interrupts = <0 162 IRQ_TYPE_LEVEL_HIGH>;
336 clocks = <&mstp8_clks R8A7794_CLK_ETHER>;
337 phy-mode = "rmii";
338 #address-cells = <1>;
339 #size-cells = <0>;
340 status = "disabled";
341 };
342
343 sdhi0: sd@ee100000 {
344 compatible = "renesas,sdhi-r8a7794";
345 reg = <0 0xee100000 0 0x200>;
346 interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>;
347 clocks = <&mstp3_clks R8A7794_CLK_SDHI0>;
348 status = "disabled";
349 };
350
351 sdhi1: sd@ee140000 {
352 compatible = "renesas,sdhi-r8a7794";
353 reg = <0 0xee140000 0 0x100>;
354 interrupts = <0 167 IRQ_TYPE_LEVEL_HIGH>;
355 clocks = <&mstp3_clks R8A7794_CLK_SDHI1>;
356 status = "disabled";
357 };
358
359 sdhi2: sd@ee160000 {
360 compatible = "renesas,sdhi-r8a7794";
361 reg = <0 0xee160000 0 0x100>;
362 interrupts = <0 168 IRQ_TYPE_LEVEL_HIGH>;
363 clocks = <&mstp3_clks R8A7794_CLK_SDHI2>;
364 status = "disabled";
365 };
366
272 clocks { 367 clocks {
273 #address-cells = <2>; 368 #address-cells = <2>;
274 #size-cells = <2>; 369 #size-cells = <2>;
@@ -294,19 +389,19 @@
294 "lb", "qspi", "sdh", "sd0", "z"; 389 "lb", "qspi", "sdh", "sd0", "z";
295 }; 390 };
296 /* Variable factor clocks */ 391 /* Variable factor clocks */
297 sd1_clk: sd2_clk@e6150078 { 392 sd2_clk: sd2_clk@e6150078 {
298 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 393 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
299 reg = <0 0xe6150078 0 4>; 394 reg = <0 0xe6150078 0 4>;
300 clocks = <&pll1_div2_clk>; 395 clocks = <&pll1_div2_clk>;
301 #clock-cells = <0>; 396 #clock-cells = <0>;
302 clock-output-names = "sd1"; 397 clock-output-names = "sd2";
303 }; 398 };
304 sd2_clk: sd3_clk@e615007c { 399 sd3_clk: sd3_clk@e615026c {
305 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 400 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
306 reg = <0 0xe615007c 0 4>; 401 reg = <0 0xe615026c 0 4>;
307 clocks = <&pll1_div2_clk>; 402 clocks = <&pll1_div2_clk>;
308 #clock-cells = <0>; 403 #clock-cells = <0>;
309 clock-output-names = "sd2"; 404 clock-output-names = "sd3";
310 }; 405 };
311 mmc0_clk: mmc0_clk@e6150240 { 406 mmc0_clk: mmc0_clk@e6150240 {
312 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock"; 407 compatible = "renesas,r8a7794-div6-clock", "renesas,cpg-div6-clock";
@@ -518,7 +613,7 @@
518 mstp3_clks: mstp3_clks@e615013c { 613 mstp3_clks: mstp3_clks@e615013c {
519 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; 614 compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
520 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; 615 reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
521 clocks = <&sd2_clk>, <&sd1_clk>, <&cpg_clocks R8A7794_CLK_SD0>, 616 clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
522 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; 617 <&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
523 #clock-cells = <1>; 618 #clock-cells = <1>;
524 clock-indices = < 619 clock-indices = <
@@ -585,4 +680,54 @@
585 clock-output-names = "scifa3", "scifa4", "scifa5"; 680 clock-output-names = "scifa3", "scifa4", "scifa5";
586 }; 681 };
587 }; 682 };
683
684 ipmmu_sy0: mmu@e6280000 {
685 compatible = "renesas,ipmmu-vmsa";
686 reg = <0 0xe6280000 0 0x1000>;
687 interrupts = <0 223 IRQ_TYPE_LEVEL_HIGH>,
688 <0 224 IRQ_TYPE_LEVEL_HIGH>;
689 #iommu-cells = <1>;
690 status = "disabled";
691 };
692
693 ipmmu_sy1: mmu@e6290000 {
694 compatible = "renesas,ipmmu-vmsa";
695 reg = <0 0xe6290000 0 0x1000>;
696 interrupts = <0 225 IRQ_TYPE_LEVEL_HIGH>;
697 #iommu-cells = <1>;
698 status = "disabled";
699 };
700
701 ipmmu_ds: mmu@e6740000 {
702 compatible = "renesas,ipmmu-vmsa";
703 reg = <0 0xe6740000 0 0x1000>;
704 interrupts = <0 198 IRQ_TYPE_LEVEL_HIGH>,
705 <0 199 IRQ_TYPE_LEVEL_HIGH>;
706 #iommu-cells = <1>;
707 };
708
709 ipmmu_mp: mmu@ec680000 {
710 compatible = "renesas,ipmmu-vmsa";
711 reg = <0 0xec680000 0 0x1000>;
712 interrupts = <0 226 IRQ_TYPE_LEVEL_HIGH>;
713 #iommu-cells = <1>;
714 status = "disabled";
715 };
716
717 ipmmu_mx: mmu@fe951000 {
718 compatible = "renesas,ipmmu-vmsa";
719 reg = <0 0xfe951000 0 0x1000>;
720 interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>,
721 <0 221 IRQ_TYPE_LEVEL_HIGH>;
722 #iommu-cells = <1>;
723 };
724
725 ipmmu_gp: mmu@e62a0000 {
726 compatible = "renesas,ipmmu-vmsa";
727 reg = <0 0xe62a0000 0 0x1000>;
728 interrupts = <0 260 IRQ_TYPE_LEVEL_HIGH>,
729 <0 261 IRQ_TYPE_LEVEL_HIGH>;
730 #iommu-cells = <1>;
731 status = "disabled";
732 };
588}; 733};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts b/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
deleted file mode 100644
index 6d32c87632d4..000000000000
--- a/arch/arm/boot/dts/sh73a0-kzm9g-reference.dts
+++ /dev/null
@@ -1,366 +0,0 @@
1/*
2 * Device Tree Source for the KZM-A9-GT board
3 *
4 * Copyright (C) 2012 Horms Solutions Ltd.
5 *
6 * Based on sh73a0-kzm9g.dts
7 * Copyright (C) 2012 Renesas Solutions Corp.
8 *
9 * This file is licensed under the terms of the GNU General Public License
10 * version 2. This program is licensed "as is" without any warranty of any
11 * kind, whether express or implied.
12 */
13
14/dts-v1/;
15#include "sh73a0.dtsi"
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include <dt-bindings/interrupt-controller/irq.h>
19
20/ {
21 model = "KZM-A9-GT";
22 compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
23
24 aliases {
25 serial4 = &scifa4;
26 };
27
28 cpus {
29 cpu@0 {
30 cpu0-supply = <&vdd_dvfs>;
31 operating-points = <
32 /* kHz uV */
33 1196000 1315000
34 598000 1175000
35 398667 1065000
36 >;
37 voltage-tolerance = <1>; /* 1% */
38 };
39 };
40
41 chosen {
42 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
43 stdout-path = &scifa4;
44 };
45
46 memory {
47 device_type = "memory";
48 reg = <0x41000000 0x1e800000>;
49 };
50
51 reg_1p8v: regulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "fixed-1.8V";
54 regulator-min-microvolt = <1800000>;
55 regulator-max-microvolt = <1800000>;
56 regulator-always-on;
57 regulator-boot-on;
58 };
59
60 reg_3p3v: regulator@1 {
61 compatible = "regulator-fixed";
62 regulator-name = "fixed-3.3V";
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 regulator-always-on;
66 regulator-boot-on;
67 };
68
69 vmmc_sdhi0: regulator@2 {
70 compatible = "regulator-fixed";
71 regulator-name = "SDHI0 Vcc";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
75 enable-active-high;
76 };
77
78 vmmc_sdhi2: regulator@3 {
79 compatible = "regulator-fixed";
80 regulator-name = "SDHI2 Vcc";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86
87 lan9220@10000000 {
88 compatible = "smsc,lan9220", "smsc,lan9115";
89 reg = <0x10000000 0x100>;
90 phy-mode = "mii";
91 interrupt-parent = <&irqpin0>;
92 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
93 reg-io-width = <4>;
94 smsc,irq-push-pull;
95 smsc,save-mac-address;
96 vddvario-supply = <&reg_1p8v>;
97 vdd33a-supply = <&reg_3p3v>;
98 };
99
100 leds {
101 compatible = "gpio-leds";
102 led1 {
103 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
104 label = "LED1";
105 };
106 led2 {
107 gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
108 label = "LED2";
109 };
110 led3 {
111 gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
112 label = "LED3";
113 };
114 led4 {
115 gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
116 label = "LED4";
117 };
118 };
119
120 keyboard {
121 compatible = "gpio-keys";
122
123 back-key {
124 gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
125 linux,code = <KEY_BACK>;
126 label = "SW3";
127 };
128
129 right-key {
130 gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
131 linux,code = <KEY_RIGHT>;
132 label = "SW2-R";
133 };
134
135 left-key {
136 gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
137 linux,code = <KEY_LEFT>;
138 label = "SW2-L";
139 };
140
141 enter-key {
142 gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
143 linux,code = <KEY_ENTER>;
144 label = "SW2-P";
145 };
146
147 up-key {
148 gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
149 linux,code = <KEY_UP>;
150 label = "SW2-U";
151 };
152
153 down-key {
154 gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
155 linux,code = <KEY_DOWN>;
156 label = "SW2-D";
157 };
158
159 home-key {
160 gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
161 linux,code = <KEY_HOME>;
162 label = "SW1";
163 };
164 };
165
166 sound {
167 compatible = "simple-audio-card";
168 simple-audio-card,format = "left_j";
169 simple-audio-card,cpu {
170 sound-dai = <&sh_fsi2 0>;
171 };
172 simple-audio-card,codec {
173 sound-dai = <&ak4648>;
174 bitclock-master;
175 frame-master;
176 system-clock-frequency = <11289600>;
177 };
178 };
179};
180
181&cmt1 {
182 status = "okay";
183};
184
185&extal2_clk {
186 clock-frequency = <48000000>;
187};
188
189&i2c0 {
190 status = "okay";
191 as3711@40 {
192 compatible = "ams,as3711";
193 reg = <0x40>;
194
195 regulators {
196 vdd_dvfs: sd1 {
197 regulator-name = "1.315V CPU";
198 regulator-min-microvolt = <1050000>;
199 regulator-max-microvolt = <1350000>;
200 regulator-always-on;
201 regulator-boot-on;
202 };
203 sd2 {
204 regulator-name = "1.8V";
205 regulator-min-microvolt = <1800000>;
206 regulator-max-microvolt = <1800000>;
207 regulator-always-on;
208 regulator-boot-on;
209 };
210 sd4 {
211 regulator-name = "1.215V";
212 regulator-min-microvolt = <1215000>;
213 regulator-max-microvolt = <1235000>;
214 regulator-always-on;
215 regulator-boot-on;
216 };
217 ldo2 {
218 regulator-name = "2.8V CPU";
219 regulator-min-microvolt = <2800000>;
220 regulator-max-microvolt = <2800000>;
221 regulator-always-on;
222 regulator-boot-on;
223 };
224 ldo3 {
225 regulator-name = "3.0V CPU";
226 regulator-min-microvolt = <3000000>;
227 regulator-max-microvolt = <3000000>;
228 regulator-always-on;
229 regulator-boot-on;
230 };
231 ldo4 {
232 regulator-name = "2.8V";
233 regulator-min-microvolt = <2800000>;
234 regulator-max-microvolt = <2800000>;
235 regulator-always-on;
236 regulator-boot-on;
237 };
238 ldo5 {
239 regulator-name = "2.8V #2";
240 regulator-min-microvolt = <2800000>;
241 regulator-max-microvolt = <2800000>;
242 regulator-always-on;
243 regulator-boot-on;
244 };
245 ldo7 {
246 regulator-name = "1.15V CPU";
247 regulator-min-microvolt = <1150000>;
248 regulator-max-microvolt = <1150000>;
249 regulator-always-on;
250 regulator-boot-on;
251 };
252 ldo8 {
253 regulator-name = "1.15V CPU #2";
254 regulator-min-microvolt = <1150000>;
255 regulator-max-microvolt = <1150000>;
256 regulator-always-on;
257 regulator-boot-on;
258 };
259 };
260 };
261
262 ak4648: ak4648@12 {
263 #sound-dai-cells = <0>;
264 compatible = "asahi-kasei,ak4648";
265 reg = <0x12>;
266 };
267};
268
269&i2c3 {
270 pinctrl-0 = <&i2c3_pins>;
271 pinctrl-names = "default";
272 status = "okay";
273
274 pcf8575: gpio@20 {
275 compatible = "nxp,pcf8575";
276 reg = <0x20>;
277 interrupt-parent = <&irqpin2>;
278 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
279 gpio-controller;
280 #gpio-cells = <2>;
281 interrupt-controller;
282 #interrupt-cells = <2>;
283 };
284};
285
286&mmcif {
287 pinctrl-0 = <&mmcif_pins>;
288 pinctrl-names = "default";
289
290 bus-width = <8>;
291 vmmc-supply = <&reg_1p8v>;
292 status = "okay";
293};
294
295&pfc {
296 i2c3_pins: i2c3 {
297 renesas,groups = "i2c3_1";
298 renesas,function = "i2c3";
299 };
300
301 mmcif_pins: mmc {
302 mux {
303 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
304 renesas,function = "mmc0";
305 };
306 cfg {
307 renesas,groups = "mmc0_data8_0";
308 renesas,pins = "PORT279";
309 bias-pull-up;
310 };
311 };
312
313 scifa4_pins: serial4 {
314 renesas,groups = "scifa4_data", "scifa4_ctrl";
315 renesas,function = "scifa4";
316 };
317
318 sdhi0_pins: sd0 {
319 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
320 renesas,function = "sdhi0";
321 };
322
323 sdhi2_pins: sd2 {
324 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
325 renesas,function = "sdhi2";
326 };
327
328 fsia_pins: sounda {
329 renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
330 "fsia_data_in", "fsia_data_out";
331 renesas,function = "fsia";
332 };
333};
334
335&scifa4 {
336 pinctrl-0 = <&scifa4_pins>;
337 pinctrl-names = "default";
338
339 status = "okay";
340};
341
342&sdhi0 {
343 pinctrl-0 = <&sdhi0_pins>;
344 pinctrl-names = "default";
345
346 vmmc-supply = <&vmmc_sdhi0>;
347 bus-width = <4>;
348 status = "okay";
349};
350
351&sdhi2 {
352 pinctrl-0 = <&sdhi2_pins>;
353 pinctrl-names = "default";
354
355 vmmc-supply = <&vmmc_sdhi2>;
356 bus-width = <4>;
357 broken-cd;
358 status = "okay";
359};
360
361&sh_fsi2 {
362 pinctrl-0 = <&fsia_pins>;
363 pinctrl-names = "default";
364
365 status = "okay";
366};
diff --git a/arch/arm/boot/dts/sh73a0-kzm9g.dts b/arch/arm/boot/dts/sh73a0-kzm9g.dts
index 27c5f426d172..022ba505f573 100644
--- a/arch/arm/boot/dts/sh73a0-kzm9g.dts
+++ b/arch/arm/boot/dts/sh73a0-kzm9g.dts
@@ -1,6 +1,9 @@
1/* 1/*
2 * Device Tree Source for the KZM-A9-GT board 2 * Device Tree Source for the KZM-A9-GT board
3 * 3 *
4 * Copyright (C) 2012 Horms Solutions Ltd.
5 *
6 * Based on sh73a0-kzm9g.dts
4 * Copyright (C) 2012 Renesas Solutions Corp. 7 * Copyright (C) 2012 Renesas Solutions Corp.
5 * 8 *
6 * This file is licensed under the terms of the GNU General Public License 9 * This file is licensed under the terms of the GNU General Public License
@@ -10,17 +13,388 @@
10 13
11/dts-v1/; 14/dts-v1/;
12#include "sh73a0.dtsi" 15#include "sh73a0.dtsi"
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/input/input.h>
18#include <dt-bindings/interrupt-controller/irq.h>
13 19
14/ { 20/ {
15 model = "KZM-A9-GT"; 21 model = "KZM-A9-GT";
16 compatible = "renesas,kzm9g", "renesas,sh73a0"; 22 compatible = "renesas,kzm9g", "renesas,sh73a0";
17 23
24 aliases {
25 serial4 = &scifa4;
26 };
27
28 cpus {
29 cpu@0 {
30 cpu0-supply = <&vdd_dvfs>;
31 operating-points = <
32 /* kHz uV */
33 1196000 1315000
34 598000 1175000
35 398667 1065000
36 >;
37 voltage-tolerance = <1>; /* 1% */
38 };
39 };
40
18 chosen { 41 chosen {
19 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200 rw"; 42 bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel rw";
43 stdout-path = &scifa4;
20 }; 44 };
21 45
22 memory { 46 memory {
23 device_type = "memory"; 47 device_type = "memory";
24 reg = <0x41000000 0x1e800000>; 48 reg = <0x40000000 0x20000000>;
49 };
50
51 reg_1p8v: regulator@0 {
52 compatible = "regulator-fixed";
53 regulator-name = "fixed-1.8V";
54 regulator-min-microvolt = <1800000>;
55 regulator-max-microvolt = <1800000>;
56 regulator-always-on;
57 regulator-boot-on;
58 };
59
60 reg_3p3v: regulator@1 {
61 compatible = "regulator-fixed";
62 regulator-name = "fixed-3.3V";
63 regulator-min-microvolt = <3300000>;
64 regulator-max-microvolt = <3300000>;
65 regulator-always-on;
66 regulator-boot-on;
67 };
68
69 vmmc_sdhi0: regulator@2 {
70 compatible = "regulator-fixed";
71 regulator-name = "SDHI0 Vcc";
72 regulator-min-microvolt = <3300000>;
73 regulator-max-microvolt = <3300000>;
74 gpio = <&pfc 15 GPIO_ACTIVE_HIGH>;
75 enable-active-high;
76 };
77
78 vmmc_sdhi2: regulator@3 {
79 compatible = "regulator-fixed";
80 regulator-name = "SDHI2 Vcc";
81 regulator-min-microvolt = <3300000>;
82 regulator-max-microvolt = <3300000>;
83 gpio = <&pfc 14 GPIO_ACTIVE_HIGH>;
84 enable-active-high;
85 };
86
87 leds {
88 compatible = "gpio-leds";
89 led1 {
90 gpios = <&pfc 20 GPIO_ACTIVE_LOW>;
91 label = "LED1";
92 };
93 led2 {
94 gpios = <&pfc 21 GPIO_ACTIVE_LOW>;
95 label = "LED2";
96 };
97 led3 {
98 gpios = <&pfc 22 GPIO_ACTIVE_LOW>;
99 label = "LED3";
100 };
101 led4 {
102 gpios = <&pfc 23 GPIO_ACTIVE_LOW>;
103 label = "LED4";
104 };
105 };
106
107 keyboard {
108 compatible = "gpio-keys";
109
110 back-key {
111 gpios = <&pcf8575 8 GPIO_ACTIVE_LOW>;
112 linux,code = <KEY_BACK>;
113 label = "SW3";
114 };
115
116 right-key {
117 gpios = <&pcf8575 9 GPIO_ACTIVE_LOW>;
118 linux,code = <KEY_RIGHT>;
119 label = "SW2-R";
120 };
121
122 left-key {
123 gpios = <&pcf8575 10 GPIO_ACTIVE_LOW>;
124 linux,code = <KEY_LEFT>;
125 label = "SW2-L";
126 };
127
128 enter-key {
129 gpios = <&pcf8575 11 GPIO_ACTIVE_LOW>;
130 linux,code = <KEY_ENTER>;
131 label = "SW2-P";
132 };
133
134 up-key {
135 gpios = <&pcf8575 12 GPIO_ACTIVE_LOW>;
136 linux,code = <KEY_UP>;
137 label = "SW2-U";
138 };
139
140 down-key {
141 gpios = <&pcf8575 13 GPIO_ACTIVE_LOW>;
142 linux,code = <KEY_DOWN>;
143 label = "SW2-D";
144 };
145
146 home-key {
147 gpios = <&pcf8575 14 GPIO_ACTIVE_LOW>;
148 linux,code = <KEY_HOME>;
149 label = "SW1";
150 };
151 };
152
153 sound {
154 compatible = "simple-audio-card";
155 simple-audio-card,format = "left_j";
156 simple-audio-card,cpu {
157 sound-dai = <&sh_fsi2 0>;
158 };
159 simple-audio-card,codec {
160 sound-dai = <&ak4648>;
161 bitclock-master;
162 frame-master;
163 system-clock-frequency = <11289600>;
164 };
165 };
166};
167
168&bsc {
169 ethernet@10000000 {
170 compatible = "smsc,lan9220", "smsc,lan9115";
171 reg = <0x10000000 0x100>;
172 phy-mode = "mii";
173 interrupt-parent = <&irqpin0>;
174 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
175 reg-io-width = <4>;
176 smsc,irq-push-pull;
177 smsc,save-mac-address;
178 vddvario-supply = <&reg_1p8v>;
179 vdd33a-supply = <&reg_3p3v>;
180 };
181};
182
183&cmt1 {
184 status = "okay";
185};
186
187&extal2_clk {
188 clock-frequency = <48000000>;
189};
190
191&i2c0 {
192 status = "okay";
193
194 compass@c {
195 compatible = "asahi-kasei,ak8975";
196 reg = <0x0c>;
197 interrupt-parent = <&irqpin3>;
198 interrupts = <4 IRQ_TYPE_EDGE_FALLING>;
199 };
200
201 ak4648: codec@12 {
202 compatible = "asahi-kasei,ak4648";
203 reg = <0x12>;
204 #sound-dai-cells = <0>;
205 };
206
207 accelerometer@1d {
208 compatible = "adi,adxl34x";
209 reg = <0x1d>;
210 interrupt-parent = <&irqpin3>;
211 interrupts = <2 IRQ_TYPE_LEVEL_HIGH>,
212 <3 IRQ_TYPE_LEVEL_HIGH>;
25 }; 213 };
214
215 rtc@32 {
216 compatible = "ricoh,r2025sd";
217 reg = <0x32>;
218 };
219
220 as3711@40 {
221 compatible = "ams,as3711";
222 reg = <0x40>;
223
224 regulators {
225 vdd_dvfs: sd1 {
226 regulator-name = "1.315V CPU";
227 regulator-min-microvolt = <1050000>;
228 regulator-max-microvolt = <1350000>;
229 regulator-always-on;
230 regulator-boot-on;
231 };
232 sd2 {
233 regulator-name = "1.8V";
234 regulator-min-microvolt = <1800000>;
235 regulator-max-microvolt = <1800000>;
236 regulator-always-on;
237 regulator-boot-on;
238 };
239 sd4 {
240 regulator-name = "1.215V";
241 regulator-min-microvolt = <1215000>;
242 regulator-max-microvolt = <1235000>;
243 regulator-always-on;
244 regulator-boot-on;
245 };
246 ldo2 {
247 regulator-name = "2.8V CPU";
248 regulator-min-microvolt = <2800000>;
249 regulator-max-microvolt = <2800000>;
250 regulator-always-on;
251 regulator-boot-on;
252 };
253 ldo3 {
254 regulator-name = "3.0V CPU";
255 regulator-min-microvolt = <3000000>;
256 regulator-max-microvolt = <3000000>;
257 regulator-always-on;
258 regulator-boot-on;
259 };
260 ldo4 {
261 regulator-name = "2.8V";
262 regulator-min-microvolt = <2800000>;
263 regulator-max-microvolt = <2800000>;
264 regulator-always-on;
265 regulator-boot-on;
266 };
267 ldo5 {
268 regulator-name = "2.8V #2";
269 regulator-min-microvolt = <2800000>;
270 regulator-max-microvolt = <2800000>;
271 regulator-always-on;
272 regulator-boot-on;
273 };
274 ldo7 {
275 regulator-name = "1.15V CPU";
276 regulator-min-microvolt = <1150000>;
277 regulator-max-microvolt = <1150000>;
278 regulator-always-on;
279 regulator-boot-on;
280 };
281 ldo8 {
282 regulator-name = "1.15V CPU #2";
283 regulator-min-microvolt = <1150000>;
284 regulator-max-microvolt = <1150000>;
285 regulator-always-on;
286 regulator-boot-on;
287 };
288 };
289 };
290};
291
292&i2c1 {
293 status = "okay";
294
295 touchscreen@55 {
296 compatible = "sitronix,st1232";
297 reg = <0x55>;
298 interrupt-parent = <&irqpin1>;
299 interrupts = <0 IRQ_TYPE_EDGE_FALLING>;
300 };
301};
302
303&i2c3 {
304 pinctrl-0 = <&i2c3_pins>;
305 pinctrl-names = "default";
306 status = "okay";
307
308 pcf8575: gpio@20 {
309 compatible = "nxp,pcf8575";
310 reg = <0x20>;
311 interrupt-parent = <&irqpin2>;
312 interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
313 gpio-controller;
314 #gpio-cells = <2>;
315 interrupt-controller;
316 #interrupt-cells = <2>;
317 };
318};
319
320&mmcif {
321 pinctrl-0 = <&mmcif_pins>;
322 pinctrl-names = "default";
323
324 bus-width = <8>;
325 vmmc-supply = <&reg_1p8v>;
326 status = "okay";
327};
328
329&pfc {
330 i2c3_pins: i2c3 {
331 renesas,groups = "i2c3_1";
332 renesas,function = "i2c3";
333 };
334
335 mmcif_pins: mmc {
336 mux {
337 renesas,groups = "mmc0_data8_0", "mmc0_ctrl_0";
338 renesas,function = "mmc0";
339 };
340 cfg {
341 renesas,groups = "mmc0_data8_0";
342 renesas,pins = "PORT279";
343 bias-pull-up;
344 };
345 };
346
347 scifa4_pins: serial4 {
348 renesas,groups = "scifa4_data", "scifa4_ctrl";
349 renesas,function = "scifa4";
350 };
351
352 sdhi0_pins: sd0 {
353 renesas,groups = "sdhi0_data4", "sdhi0_ctrl", "sdhi0_cd", "sdhi0_wp";
354 renesas,function = "sdhi0";
355 };
356
357 sdhi2_pins: sd2 {
358 renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
359 renesas,function = "sdhi2";
360 };
361
362 fsia_pins: sounda {
363 renesas,groups = "fsia_mclk_in", "fsia_sclk_in",
364 "fsia_data_in", "fsia_data_out";
365 renesas,function = "fsia";
366 };
367};
368
369&scifa4 {
370 pinctrl-0 = <&scifa4_pins>;
371 pinctrl-names = "default";
372
373 status = "okay";
374};
375
376&sdhi0 {
377 pinctrl-0 = <&sdhi0_pins>;
378 pinctrl-names = "default";
379
380 vmmc-supply = <&vmmc_sdhi0>;
381 bus-width = <4>;
382 status = "okay";
383};
384
385&sdhi2 {
386 pinctrl-0 = <&sdhi2_pins>;
387 pinctrl-names = "default";
388
389 vmmc-supply = <&vmmc_sdhi2>;
390 bus-width = <4>;
391 broken-cd;
392 status = "okay";
393};
394
395&sh_fsi2 {
396 pinctrl-0 = <&fsia_pins>;
397 pinctrl-names = "default";
398
399 status = "okay";
26}; 400};
diff --git a/arch/arm/boot/dts/sh73a0.dtsi b/arch/arm/boot/dts/sh73a0.dtsi
index 2dfd5b44255d..45b539ce4d35 100644
--- a/arch/arm/boot/dts/sh73a0.dtsi
+++ b/arch/arm/boot/dts/sh73a0.dtsi
@@ -11,6 +11,7 @@
11/include/ "skeleton.dtsi" 11/include/ "skeleton.dtsi"
12 12
13#include <dt-bindings/clock/sh73a0-clock.h> 13#include <dt-bindings/clock/sh73a0-clock.h>
14#include <dt-bindings/interrupt-controller/arm-gic.h>
14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/interrupt-controller/irq.h>
15 16
16/ { 17/ {
@@ -26,15 +27,24 @@
26 compatible = "arm,cortex-a9"; 27 compatible = "arm,cortex-a9";
27 reg = <0>; 28 reg = <0>;
28 clock-frequency = <1196000000>; 29 clock-frequency = <1196000000>;
30 power-domains = <&pd_a2sl>;
29 }; 31 };
30 cpu@1 { 32 cpu@1 {
31 device_type = "cpu"; 33 device_type = "cpu";
32 compatible = "arm,cortex-a9"; 34 compatible = "arm,cortex-a9";
33 reg = <1>; 35 reg = <1>;
34 clock-frequency = <1196000000>; 36 clock-frequency = <1196000000>;
37 power-domains = <&pd_a2sl>;
35 }; 38 };
36 }; 39 };
37 40
41 timer@f0000600 {
42 compatible = "arm,cortex-a9-twd-timer";
43 reg = <0xf0000600 0x20>;
44 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
45 clocks = <&twd_clk>;
46 };
47
38 gic: interrupt-controller@f0001000 { 48 gic: interrupt-controller@f0001000 {
39 compatible = "arm,cortex-a9-gic"; 49 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>; 50 #interrupt-cells = <3>;
@@ -49,6 +59,7 @@
49 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>, 59 interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>,
50 <0 38 IRQ_TYPE_LEVEL_HIGH>; 60 <0 38 IRQ_TYPE_LEVEL_HIGH>;
51 interrupt-names = "sec", "temp"; 61 interrupt-names = "sec", "temp";
62 power-domains = <&pd_a4bc1>;
52 }; 63 };
53 64
54 sbsc1: memory-controller@fe400000 { 65 sbsc1: memory-controller@fe400000 {
@@ -57,6 +68,7 @@
57 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>, 68 interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>,
58 <0 36 IRQ_TYPE_LEVEL_HIGH>; 69 <0 36 IRQ_TYPE_LEVEL_HIGH>;
59 interrupt-names = "sec", "temp"; 70 interrupt-names = "sec", "temp";
71 power-domains = <&pd_a4bc0>;
60 }; 72 };
61 73
62 pmu { 74 pmu {
@@ -69,11 +81,12 @@
69 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48"; 81 compatible = "renesas,cmt-48-sh73a0", "renesas,cmt-48";
70 reg = <0xe6138000 0x200>; 82 reg = <0xe6138000 0x200>;
71 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>; 83 interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
84 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
85 clock-names = "fck";
86 power-domains = <&pd_c5>;
72 87
73 renesas,channels-mask = <0x3f>; 88 renesas,channels-mask = <0x3f>;
74 89
75 clocks = <&mstp3_clks SH73A0_CLK_CMT1>;
76 clock-names = "fck";
77 status = "disabled"; 90 status = "disabled";
78 }; 91 };
79 92
@@ -94,6 +107,9 @@
94 0 6 IRQ_TYPE_LEVEL_HIGH 107 0 6 IRQ_TYPE_LEVEL_HIGH
95 0 7 IRQ_TYPE_LEVEL_HIGH 108 0 7 IRQ_TYPE_LEVEL_HIGH
96 0 8 IRQ_TYPE_LEVEL_HIGH>; 109 0 8 IRQ_TYPE_LEVEL_HIGH>;
110 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
111 power-domains = <&pd_a4s>;
112 control-parent;
97 }; 113 };
98 114
99 irqpin1: irqpin@e6900004 { 115 irqpin1: irqpin@e6900004 {
@@ -113,6 +129,8 @@
113 0 14 IRQ_TYPE_LEVEL_HIGH 129 0 14 IRQ_TYPE_LEVEL_HIGH
114 0 15 IRQ_TYPE_LEVEL_HIGH 130 0 15 IRQ_TYPE_LEVEL_HIGH
115 0 16 IRQ_TYPE_LEVEL_HIGH>; 131 0 16 IRQ_TYPE_LEVEL_HIGH>;
132 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
133 power-domains = <&pd_a4s>;
116 control-parent; 134 control-parent;
117 }; 135 };
118 136
@@ -133,6 +151,9 @@
133 0 22 IRQ_TYPE_LEVEL_HIGH 151 0 22 IRQ_TYPE_LEVEL_HIGH
134 0 23 IRQ_TYPE_LEVEL_HIGH 152 0 23 IRQ_TYPE_LEVEL_HIGH
135 0 24 IRQ_TYPE_LEVEL_HIGH>; 153 0 24 IRQ_TYPE_LEVEL_HIGH>;
154 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
155 power-domains = <&pd_a4s>;
156 control-parent;
136 }; 157 };
137 158
138 irqpin3: irqpin@e690000c { 159 irqpin3: irqpin@e690000c {
@@ -152,6 +173,9 @@
152 0 30 IRQ_TYPE_LEVEL_HIGH 173 0 30 IRQ_TYPE_LEVEL_HIGH
153 0 31 IRQ_TYPE_LEVEL_HIGH 174 0 31 IRQ_TYPE_LEVEL_HIGH
154 0 32 IRQ_TYPE_LEVEL_HIGH>; 175 0 32 IRQ_TYPE_LEVEL_HIGH>;
176 clocks = <&mstp5_clks SH73A0_CLK_INTCA0>;
177 power-domains = <&pd_a4s>;
178 control-parent;
155 }; 179 };
156 180
157 i2c0: i2c@e6820000 { 181 i2c0: i2c@e6820000 {
@@ -164,6 +188,7 @@
164 0 169 IRQ_TYPE_LEVEL_HIGH 188 0 169 IRQ_TYPE_LEVEL_HIGH
165 0 170 IRQ_TYPE_LEVEL_HIGH>; 189 0 170 IRQ_TYPE_LEVEL_HIGH>;
166 clocks = <&mstp1_clks SH73A0_CLK_IIC0>; 190 clocks = <&mstp1_clks SH73A0_CLK_IIC0>;
191 power-domains = <&pd_a3sp>;
167 status = "disabled"; 192 status = "disabled";
168 }; 193 };
169 194
@@ -177,6 +202,7 @@
177 0 53 IRQ_TYPE_LEVEL_HIGH 202 0 53 IRQ_TYPE_LEVEL_HIGH
178 0 54 IRQ_TYPE_LEVEL_HIGH>; 203 0 54 IRQ_TYPE_LEVEL_HIGH>;
179 clocks = <&mstp3_clks SH73A0_CLK_IIC1>; 204 clocks = <&mstp3_clks SH73A0_CLK_IIC1>;
205 power-domains = <&pd_a3sp>;
180 status = "disabled"; 206 status = "disabled";
181 }; 207 };
182 208
@@ -190,6 +216,7 @@
190 0 173 IRQ_TYPE_LEVEL_HIGH 216 0 173 IRQ_TYPE_LEVEL_HIGH
191 0 174 IRQ_TYPE_LEVEL_HIGH>; 217 0 174 IRQ_TYPE_LEVEL_HIGH>;
192 clocks = <&mstp0_clks SH73A0_CLK_IIC2>; 218 clocks = <&mstp0_clks SH73A0_CLK_IIC2>;
219 power-domains = <&pd_a3sp>;
193 status = "disabled"; 220 status = "disabled";
194 }; 221 };
195 222
@@ -203,6 +230,7 @@
203 0 185 IRQ_TYPE_LEVEL_HIGH 230 0 185 IRQ_TYPE_LEVEL_HIGH
204 0 186 IRQ_TYPE_LEVEL_HIGH>; 231 0 186 IRQ_TYPE_LEVEL_HIGH>;
205 clocks = <&mstp4_clks SH73A0_CLK_IIC3>; 232 clocks = <&mstp4_clks SH73A0_CLK_IIC3>;
233 power-domains = <&pd_a3sp>;
206 status = "disabled"; 234 status = "disabled";
207 }; 235 };
208 236
@@ -216,6 +244,7 @@
216 0 189 IRQ_TYPE_LEVEL_HIGH 244 0 189 IRQ_TYPE_LEVEL_HIGH
217 0 190 IRQ_TYPE_LEVEL_HIGH>; 245 0 190 IRQ_TYPE_LEVEL_HIGH>;
218 clocks = <&mstp4_clks SH73A0_CLK_IIC4>; 246 clocks = <&mstp4_clks SH73A0_CLK_IIC4>;
247 power-domains = <&pd_c5>;
219 status = "disabled"; 248 status = "disabled";
220 }; 249 };
221 250
@@ -225,6 +254,7 @@
225 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH 254 interrupts = <0 140 IRQ_TYPE_LEVEL_HIGH
226 0 141 IRQ_TYPE_LEVEL_HIGH>; 255 0 141 IRQ_TYPE_LEVEL_HIGH>;
227 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>; 256 clocks = <&mstp3_clks SH73A0_CLK_MMCIF0>;
257 power-domains = <&pd_a3sp>;
228 reg-io-width = <4>; 258 reg-io-width = <4>;
229 status = "disabled"; 259 status = "disabled";
230 }; 260 };
@@ -236,6 +266,7 @@
236 0 84 IRQ_TYPE_LEVEL_HIGH 266 0 84 IRQ_TYPE_LEVEL_HIGH
237 0 85 IRQ_TYPE_LEVEL_HIGH>; 267 0 85 IRQ_TYPE_LEVEL_HIGH>;
238 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>; 268 clocks = <&mstp3_clks SH73A0_CLK_SDHI0>;
269 power-domains = <&pd_a3sp>;
239 cap-sd-highspeed; 270 cap-sd-highspeed;
240 status = "disabled"; 271 status = "disabled";
241 }; 272 };
@@ -247,6 +278,7 @@
247 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH 278 interrupts = <0 88 IRQ_TYPE_LEVEL_HIGH
248 0 89 IRQ_TYPE_LEVEL_HIGH>; 279 0 89 IRQ_TYPE_LEVEL_HIGH>;
249 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>; 280 clocks = <&mstp3_clks SH73A0_CLK_SDHI1>;
281 power-domains = <&pd_a3sp>;
250 toshiba,mmc-wrprotect-disable; 282 toshiba,mmc-wrprotect-disable;
251 cap-sd-highspeed; 283 cap-sd-highspeed;
252 status = "disabled"; 284 status = "disabled";
@@ -258,6 +290,7 @@
258 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH 290 interrupts = <0 104 IRQ_TYPE_LEVEL_HIGH
259 0 105 IRQ_TYPE_LEVEL_HIGH>; 291 0 105 IRQ_TYPE_LEVEL_HIGH>;
260 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>; 292 clocks = <&mstp3_clks SH73A0_CLK_SDHI2>;
293 power-domains = <&pd_a3sp>;
261 toshiba,mmc-wrprotect-disable; 294 toshiba,mmc-wrprotect-disable;
262 cap-sd-highspeed; 295 cap-sd-highspeed;
263 status = "disabled"; 296 status = "disabled";
@@ -269,6 +302,7 @@
269 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>; 302 interrupts = <0 72 IRQ_TYPE_LEVEL_HIGH>;
270 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>; 303 clocks = <&mstp2_clks SH73A0_CLK_SCIFA0>;
271 clock-names = "sci_ick"; 304 clock-names = "sci_ick";
305 power-domains = <&pd_a3sp>;
272 status = "disabled"; 306 status = "disabled";
273 }; 307 };
274 308
@@ -278,6 +312,7 @@
278 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>; 312 interrupts = <0 73 IRQ_TYPE_LEVEL_HIGH>;
279 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>; 313 clocks = <&mstp2_clks SH73A0_CLK_SCIFA1>;
280 clock-names = "sci_ick"; 314 clock-names = "sci_ick";
315 power-domains = <&pd_a3sp>;
281 status = "disabled"; 316 status = "disabled";
282 }; 317 };
283 318
@@ -287,6 +322,7 @@
287 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>; 322 interrupts = <0 74 IRQ_TYPE_LEVEL_HIGH>;
288 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>; 323 clocks = <&mstp2_clks SH73A0_CLK_SCIFA2>;
289 clock-names = "sci_ick"; 324 clock-names = "sci_ick";
325 power-domains = <&pd_a3sp>;
290 status = "disabled"; 326 status = "disabled";
291 }; 327 };
292 328
@@ -296,6 +332,7 @@
296 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>; 332 interrupts = <0 75 IRQ_TYPE_LEVEL_HIGH>;
297 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>; 333 clocks = <&mstp2_clks SH73A0_CLK_SCIFA3>;
298 clock-names = "sci_ick"; 334 clock-names = "sci_ick";
335 power-domains = <&pd_a3sp>;
299 status = "disabled"; 336 status = "disabled";
300 }; 337 };
301 338
@@ -305,6 +342,7 @@
305 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>; 342 interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
306 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>; 343 clocks = <&mstp2_clks SH73A0_CLK_SCIFA4>;
307 clock-names = "sci_ick"; 344 clock-names = "sci_ick";
345 power-domains = <&pd_a3sp>;
308 status = "disabled"; 346 status = "disabled";
309 }; 347 };
310 348
@@ -314,6 +352,7 @@
314 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>; 352 interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
315 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>; 353 clocks = <&mstp2_clks SH73A0_CLK_SCIFA5>;
316 clock-names = "sci_ick"; 354 clock-names = "sci_ick";
355 power-domains = <&pd_a3sp>;
317 status = "disabled"; 356 status = "disabled";
318 }; 357 };
319 358
@@ -323,6 +362,7 @@
323 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>; 362 interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
324 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>; 363 clocks = <&mstp3_clks SH73A0_CLK_SCIFA6>;
325 clock-names = "sci_ick"; 364 clock-names = "sci_ick";
365 power-domains = <&pd_a3sp>;
326 status = "disabled"; 366 status = "disabled";
327 }; 367 };
328 368
@@ -332,6 +372,7 @@
332 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>; 372 interrupts = <0 143 IRQ_TYPE_LEVEL_HIGH>;
333 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>; 373 clocks = <&mstp2_clks SH73A0_CLK_SCIFA7>;
334 clock-names = "sci_ick"; 374 clock-names = "sci_ick";
375 power-domains = <&pd_a3sp>;
335 status = "disabled"; 376 status = "disabled";
336 }; 377 };
337 378
@@ -341,6 +382,7 @@
341 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>; 382 interrupts = <0 80 IRQ_TYPE_LEVEL_HIGH>;
342 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>; 383 clocks = <&mstp2_clks SH73A0_CLK_SCIFB>;
343 clock-names = "sci_ick"; 384 clock-names = "sci_ick";
385 power-domains = <&pd_a3sp>;
344 status = "disabled"; 386 status = "disabled";
345 }; 387 };
346 388
@@ -359,6 +401,117 @@
359 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>, 401 <&irqpin2 4 0>, <&irqpin2 5 0>, <&irqpin2 6 0>, <&irqpin2 7 0>,
360 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>, 402 <&irqpin3 0 0>, <&irqpin3 1 0>, <&irqpin3 2 0>, <&irqpin3 3 0>,
361 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>; 403 <&irqpin3 4 0>, <&irqpin3 5 0>, <&irqpin3 6 0>, <&irqpin3 7 0>;
404 power-domains = <&pd_c5>;
405 };
406
407 sysc: system-controller@e6180000 {
408 compatible = "renesas,sysc-sh73a0", "renesas,sysc-rmobile";
409 reg = <0xe6180000 0x8000>, <0xe6188000 0x8000>;
410
411 pm-domains {
412 pd_c5: c5 {
413 #address-cells = <1>;
414 #size-cells = <0>;
415 #power-domain-cells = <0>;
416
417 pd_c4: c4@0 {
418 reg = <0>;
419 #power-domain-cells = <0>;
420 };
421
422 pd_d4: d4@1 {
423 reg = <1>;
424 #power-domain-cells = <0>;
425 };
426
427 pd_a4bc0: a4bc0@4 {
428 reg = <4>;
429 #power-domain-cells = <0>;
430 };
431
432 pd_a4bc1: a4bc1@5 {
433 reg = <5>;
434 #power-domain-cells = <0>;
435 };
436
437 pd_a4lc0: a4lc0@6 {
438 reg = <6>;
439 #power-domain-cells = <0>;
440 };
441
442 pd_a4lc1: a4lc1@7 {
443 reg = <7>;
444 #power-domain-cells = <0>;
445 };
446
447 pd_a4mp: a4mp@8 {
448 reg = <8>;
449 #address-cells = <1>;
450 #size-cells = <0>;
451 #power-domain-cells = <0>;
452
453 pd_a3mp: a3mp@9 {
454 reg = <9>;
455 #power-domain-cells = <0>;
456 };
457
458 pd_a3vc: a3vc@10 {
459 reg = <10>;
460 #power-domain-cells = <0>;
461 };
462 };
463
464 pd_a4rm: a4rm@12 {
465 reg = <12>;
466 #address-cells = <1>;
467 #size-cells = <0>;
468 #power-domain-cells = <0>;
469
470 pd_a3r: a3r@13 {
471 reg = <13>;
472 #address-cells = <1>;
473 #size-cells = <0>;
474 #power-domain-cells = <0>;
475
476 pd_a2rv: a2rv@14 {
477 reg = <14>;
478 #address-cells = <1>;
479 #size-cells = <0>;
480 #power-domain-cells = <0>;
481 };
482 };
483 };
484
485 pd_a4s: a4s@16 {
486 reg = <16>;
487 #address-cells = <1>;
488 #size-cells = <0>;
489 #power-domain-cells = <0>;
490
491 pd_a3sp: a3sp@17 {
492 reg = <17>;
493 #power-domain-cells = <0>;
494 };
495
496 pd_a3sg: a3sg@18 {
497 reg = <18>;
498 #power-domain-cells = <0>;
499 };
500
501 pd_a3sm: a3sm@19 {
502 reg = <19>;
503 #address-cells = <1>;
504 #size-cells = <0>;
505 #power-domain-cells = <0>;
506
507 pd_a2sl: a2sl@20 {
508 reg = <20>;
509 #power-domain-cells = <0>;
510 };
511 };
512 };
513 };
514 };
362 }; 515 };
363 516
364 sh_fsi2: sound@ec230000 { 517 sh_fsi2: sound@ec230000 {
@@ -366,9 +519,22 @@
366 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2"; 519 compatible = "renesas,fsi2-sh73a0", "renesas,sh_fsi2";
367 reg = <0xec230000 0x400>; 520 reg = <0xec230000 0x400>;
368 interrupts = <0 146 0x4>; 521 interrupts = <0 146 0x4>;
522 power-domains = <&pd_a4mp>;
369 status = "disabled"; 523 status = "disabled";
370 }; 524 };
371 525
526 bsc: bus@fec10000 {
527 compatible = "renesas,bsc-sh73a0", "renesas,bsc",
528 "simple-pm-bus";
529 #address-cells = <1>;
530 #size-cells = <1>;
531 ranges = <0 0 0x20000000>;
532 reg = <0xfec10000 0x400>;
533 interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
534 clocks = <&zb_clk>;
535 power-domains = <&pd_a4s>;
536 };
537
372 clocks { 538 clocks {
373 #address-cells = <1>; 539 #address-cells = <1>;
374 #size-cells = <1>; 540 #size-cells = <1>;
@@ -426,133 +592,159 @@
426 vclk1_clk: vclk1_clk@e6150008 { 592 vclk1_clk: vclk1_clk@e6150008 {
427 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 593 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
428 reg = <0xe6150008 4>; 594 reg = <0xe6150008 4>;
429 clocks = <&pll1_div2_clk>; 595 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
596 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
597 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
598 <0>;
430 #clock-cells = <0>; 599 #clock-cells = <0>;
431 clock-output-names = "vclk1"; 600 clock-output-names = "vclk1";
432 }; 601 };
433 vclk2_clk: vclk2_clk@e615000c { 602 vclk2_clk: vclk2_clk@e615000c {
434 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 603 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
435 reg = <0xe615000c 4>; 604 reg = <0xe615000c 4>;
436 clocks = <&pll1_div2_clk>; 605 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
606 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
607 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
608 <0>;
437 #clock-cells = <0>; 609 #clock-cells = <0>;
438 clock-output-names = "vclk2"; 610 clock-output-names = "vclk2";
439 }; 611 };
440 vclk3_clk: vclk3_clk@e615001c { 612 vclk3_clk: vclk3_clk@e615001c {
441 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 613 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
442 reg = <0xe615001c 4>; 614 reg = <0xe615001c 4>;
443 clocks = <&pll1_div2_clk>; 615 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
616 <&extcki_clk>, <&extal2_clk>, <&main_div2_clk>,
617 <&extalr_clk>, <&cpg_clocks SH73A0_CLK_MAIN>,
618 <0>;
444 #clock-cells = <0>; 619 #clock-cells = <0>;
445 clock-output-names = "vclk3"; 620 clock-output-names = "vclk3";
446 }; 621 };
447 zb_clk: zb_clk@e6150010 { 622 zb_clk: zb_clk@e6150010 {
448 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 623 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
449 reg = <0xe6150010 4>; 624 reg = <0xe6150010 4>;
450 clocks = <&pll1_div2_clk>; 625 clocks = <&pll1_div2_clk>, <0>,
626 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
451 #clock-cells = <0>; 627 #clock-cells = <0>;
452 clock-output-names = "zb"; 628 clock-output-names = "zb";
453 }; 629 };
454 flctl_clk: flctl_clk@e6150014 { 630 flctl_clk: flctl_clk@e6150014 {
455 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 631 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
456 reg = <0xe6150014 4>; 632 reg = <0xe6150014 4>;
457 clocks = <&pll1_div2_clk>; 633 clocks = <&pll1_div2_clk>, <0>,
634 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
458 #clock-cells = <0>; 635 #clock-cells = <0>;
459 clock-output-names = "flctlck"; 636 clock-output-names = "flctlck";
460 }; 637 };
461 sdhi0_clk: sdhi0_clk@e6150074 { 638 sdhi0_clk: sdhi0_clk@e6150074 {
462 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 639 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
463 reg = <0xe6150074 4>; 640 reg = <0xe6150074 4>;
464 clocks = <&pll1_div2_clk>; 641 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
642 <&pll1_div13_clk>, <0>;
465 #clock-cells = <0>; 643 #clock-cells = <0>;
466 clock-output-names = "sdhi0ck"; 644 clock-output-names = "sdhi0ck";
467 }; 645 };
468 sdhi1_clk: sdhi1_clk@e6150078 { 646 sdhi1_clk: sdhi1_clk@e6150078 {
469 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 647 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
470 reg = <0xe6150078 4>; 648 reg = <0xe6150078 4>;
471 clocks = <&pll1_div2_clk>; 649 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
650 <&pll1_div13_clk>, <0>;
472 #clock-cells = <0>; 651 #clock-cells = <0>;
473 clock-output-names = "sdhi1ck"; 652 clock-output-names = "sdhi1ck";
474 }; 653 };
475 sdhi2_clk: sdhi2_clk@e615007c { 654 sdhi2_clk: sdhi2_clk@e615007c {
476 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 655 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
477 reg = <0xe615007c 4>; 656 reg = <0xe615007c 4>;
478 clocks = <&pll1_div2_clk>; 657 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
658 <&pll1_div13_clk>, <0>;
479 #clock-cells = <0>; 659 #clock-cells = <0>;
480 clock-output-names = "sdhi2ck"; 660 clock-output-names = "sdhi2ck";
481 }; 661 };
482 fsia_clk: fsia_clk@e6150018 { 662 fsia_clk: fsia_clk@e6150018 {
483 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 663 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
484 reg = <0xe6150018 4>; 664 reg = <0xe6150018 4>;
485 clocks = <&pll1_div2_clk>; 665 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
666 <&fsiack_clk>, <&fsiack_clk>;
486 #clock-cells = <0>; 667 #clock-cells = <0>;
487 clock-output-names = "fsia"; 668 clock-output-names = "fsia";
488 }; 669 };
489 fsib_clk: fsib_clk@e6150090 { 670 fsib_clk: fsib_clk@e6150090 {
490 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 671 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
491 reg = <0xe6150090 4>; 672 reg = <0xe6150090 4>;
492 clocks = <&pll1_div2_clk>; 673 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
674 <&fsibck_clk>, <&fsibck_clk>;
493 #clock-cells = <0>; 675 #clock-cells = <0>;
494 clock-output-names = "fsib"; 676 clock-output-names = "fsib";
495 }; 677 };
496 sub_clk: sub_clk@e6150080 { 678 sub_clk: sub_clk@e6150080 {
497 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 679 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
498 reg = <0xe6150080 4>; 680 reg = <0xe6150080 4>;
499 clocks = <&extal2_clk>; 681 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
682 <&extal2_clk>, <&extal2_clk>;
500 #clock-cells = <0>; 683 #clock-cells = <0>;
501 clock-output-names = "sub"; 684 clock-output-names = "sub";
502 }; 685 };
503 spua_clk: spua_clk@e6150084 { 686 spua_clk: spua_clk@e6150084 {
504 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 687 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
505 reg = <0xe6150084 4>; 688 reg = <0xe6150084 4>;
506 clocks = <&pll1_div2_clk>; 689 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
690 <&extal2_clk>, <&extal2_clk>;
507 #clock-cells = <0>; 691 #clock-cells = <0>;
508 clock-output-names = "spua"; 692 clock-output-names = "spua";
509 }; 693 };
510 spuv_clk: spuv_clk@e6150094 { 694 spuv_clk: spuv_clk@e6150094 {
511 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 695 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
512 reg = <0xe6150094 4>; 696 reg = <0xe6150094 4>;
513 clocks = <&pll1_div2_clk>; 697 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
698 <&extal2_clk>, <&extal2_clk>;
514 #clock-cells = <0>; 699 #clock-cells = <0>;
515 clock-output-names = "spuv"; 700 clock-output-names = "spuv";
516 }; 701 };
517 msu_clk: msu_clk@e6150088 { 702 msu_clk: msu_clk@e6150088 {
518 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 703 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
519 reg = <0xe6150088 4>; 704 reg = <0xe6150088 4>;
520 clocks = <&pll1_div2_clk>; 705 clocks = <&pll1_div2_clk>, <0>,
706 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
521 #clock-cells = <0>; 707 #clock-cells = <0>;
522 clock-output-names = "msu"; 708 clock-output-names = "msu";
523 }; 709 };
524 hsi_clk: hsi_clk@e615008c { 710 hsi_clk: hsi_clk@e615008c {
525 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 711 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
526 reg = <0xe615008c 4>; 712 reg = <0xe615008c 4>;
527 clocks = <&pll1_div2_clk>; 713 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
714 <&pll1_div7_clk>, <0>;
528 #clock-cells = <0>; 715 #clock-cells = <0>;
529 clock-output-names = "hsi"; 716 clock-output-names = "hsi";
530 }; 717 };
531 mfg1_clk: mfg1_clk@e6150098 { 718 mfg1_clk: mfg1_clk@e6150098 {
532 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 719 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
533 reg = <0xe6150098 4>; 720 reg = <0xe6150098 4>;
534 clocks = <&pll1_div2_clk>; 721 clocks = <&pll1_div2_clk>, <0>,
722 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
535 #clock-cells = <0>; 723 #clock-cells = <0>;
536 clock-output-names = "mfg1"; 724 clock-output-names = "mfg1";
537 }; 725 };
538 mfg2_clk: mfg2_clk@e615009c { 726 mfg2_clk: mfg2_clk@e615009c {
539 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 727 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
540 reg = <0xe615009c 4>; 728 reg = <0xe615009c 4>;
541 clocks = <&pll1_div2_clk>; 729 clocks = <&pll1_div2_clk>, <0>,
730 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
542 #clock-cells = <0>; 731 #clock-cells = <0>;
543 clock-output-names = "mfg2"; 732 clock-output-names = "mfg2";
544 }; 733 };
545 dsit_clk: dsit_clk@e6150060 { 734 dsit_clk: dsit_clk@e6150060 {
546 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 735 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
547 reg = <0xe6150060 4>; 736 reg = <0xe6150060 4>;
548 clocks = <&pll1_div2_clk>; 737 clocks = <&pll1_div2_clk>, <0>,
738 <&cpg_clocks SH73A0_CLK_PLL2>, <0>;
549 #clock-cells = <0>; 739 #clock-cells = <0>;
550 clock-output-names = "dsit"; 740 clock-output-names = "dsit";
551 }; 741 };
552 dsi0p_clk: dsi0p_clk@e6150064 { 742 dsi0p_clk: dsi0p_clk@e6150064 {
553 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock"; 743 compatible = "renesas,sh73a0-div6-clock", "renesas,cpg-div6-clock";
554 reg = <0xe6150064 4>; 744 reg = <0xe6150064 4>;
555 clocks = <&pll1_div2_clk>; 745 clocks = <&pll1_div2_clk>, <&cpg_clocks SH73A0_CLK_PLL2>,
746 <&cpg_clocks SH73A0_CLK_MAIN>, <&extal2_clk>,
747 <&extcki_clk>, <0>, <0>, <0>;
556 #clock-cells = <0>; 748 #clock-cells = <0>;
557 clock-output-names = "dsi0pck"; 749 clock-output-names = "dsi0pck";
558 }; 750 };
@@ -695,5 +887,16 @@
695 clock-output-names = 887 clock-output-names =
696 "iic3", "iic4", "keysc"; 888 "iic3", "iic4", "keysc";
697 }; 889 };
890 mstp5_clks: mstp5_clks@e6150144 {
891 compatible = "renesas,sh73a0-mstp-clocks", "renesas,cpg-mstp-clocks";
892 reg = <0xe6150144 4>, <0xe615003c 4>;
893 clocks = <&cpg_clocks SH73A0_CLK_HP>;
894 #clock-cells = <1>;
895 clock-indices = <
896 SH73A0_CLK_INTCA0
897 >;
898 clock-output-names =
899 "intca0";
900 };
698 }; 901 };
699}; 902};
diff --git a/arch/arm/mach-shmobile/Kconfig b/arch/arm/mach-shmobile/Kconfig
index 485961a4de1d..c2952f58e768 100644
--- a/arch/arm/mach-shmobile/Kconfig
+++ b/arch/arm/mach-shmobile/Kconfig
@@ -82,6 +82,11 @@ config ARCH_R8A7794
82 bool "R-Car E2 (R8A77940)" 82 bool "R-Car E2 (R8A77940)"
83 select ARCH_RCAR_GEN2 83 select ARCH_RCAR_GEN2
84 84
85config ARCH_SH73A0
86 bool "SH-Mobile AG5 (R8A73A00)"
87 select ARCH_RMOBILE
88 select RENESAS_INTC_IRQPIN
89
85comment "Renesas ARM SoCs Board Type" 90comment "Renesas ARM SoCs Board Type"
86 91
87config MACH_MARZEN 92config MACH_MARZEN
@@ -172,20 +177,6 @@ config MACH_KZM9G
172 select SND_SOC_AK4642 if SND_SIMPLE_CARD 177 select SND_SOC_AK4642 if SND_SIMPLE_CARD
173 select USE_OF 178 select USE_OF
174 179
175config MACH_KZM9G_REFERENCE
176 bool "KZM-A9-GT board - Reference Device Tree Implementation"
177 depends on ARCH_SH73A0
178 select ARCH_REQUIRE_GPIOLIB
179 select REGULATOR_FIXED_VOLTAGE if REGULATOR
180 select SND_SOC_AK4642 if SND_SIMPLE_CARD
181 select USE_OF
182 ---help---
183 Use reference implementation of KZM-A9-GT board support
184 which makes as greater use of device tree at the expense
185 of not supporting a number of devices.
186
187 This is intended to aid developers
188
189comment "Renesas ARM SoCs System Configuration" 180comment "Renesas ARM SoCs System Configuration"
190 181
191config CPU_HAS_INTEVT 182config CPU_HAS_INTEVT
diff --git a/arch/arm/mach-shmobile/Makefile b/arch/arm/mach-shmobile/Makefile
index ba7bb7847ae3..d3aca07b51a8 100644
--- a/arch/arm/mach-shmobile/Makefile
+++ b/arch/arm/mach-shmobile/Makefile
@@ -6,7 +6,7 @@
6obj-y := timer.o console.o 6obj-y := timer.o console.o
7 7
8# CPU objects 8# CPU objects
9obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o intc-sh73a0.o pm-sh73a0.o 9obj-$(CONFIG_ARCH_SH73A0) += setup-sh73a0.o pm-sh73a0.o
10obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o 10obj-$(CONFIG_ARCH_R8A73A4) += setup-r8a73a4.o
11obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o 11obj-$(CONFIG_ARCH_R8A7740) += setup-r8a7740.o pm-r8a7740.o
12obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o 12obj-$(CONFIG_ARCH_R8A7778) += setup-r8a7778.o
@@ -56,8 +56,7 @@ obj-$(CONFIG_MACH_BOCKW) += board-bockw.o
56obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o 56obj-$(CONFIG_MACH_BOCKW_REFERENCE) += board-bockw-reference.o
57obj-$(CONFIG_MACH_MARZEN) += board-marzen.o 57obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
58obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o 58obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
59obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o 59obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o intc-sh73a0.o
60obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
61endif 60endif
62 61
63# Framework support 62# Framework support
diff --git a/arch/arm/mach-shmobile/Makefile.boot b/arch/arm/mach-shmobile/Makefile.boot
index da9fc6d4a1da..e1ef19cef89c 100644
--- a/arch/arm/mach-shmobile/Makefile.boot
+++ b/arch/arm/mach-shmobile/Makefile.boot
@@ -4,7 +4,6 @@ loadaddr-$(CONFIG_MACH_ARMADILLO800EVA) += 0x40008000
4loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000 4loadaddr-$(CONFIG_MACH_BOCKW) += 0x60008000
5loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000 5loadaddr-$(CONFIG_MACH_BOCKW_REFERENCE) += 0x60008000
6loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000 6loadaddr-$(CONFIG_MACH_KZM9G) += 0x41008000
7loadaddr-$(CONFIG_MACH_KZM9G_REFERENCE) += 0x41008000
8loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000 7loadaddr-$(CONFIG_MACH_MARZEN) += 0x60008000
9 8
10__ZRELADDR := $(sort $(loadaddr-y)) 9__ZRELADDR := $(sort $(loadaddr-y))
diff --git a/arch/arm/mach-shmobile/board-kzm9g-reference.c b/arch/arm/mach-shmobile/board-kzm9g-reference.c
deleted file mode 100644
index 2e82e44ab852..000000000000
--- a/arch/arm/mach-shmobile/board-kzm9g-reference.c
+++ /dev/null
@@ -1,62 +0,0 @@
1/*
2 * KZM-A9-GT board support - Reference Device Tree Implementation
3 *
4 * Copyright (C) 2012 Horms Solutions Ltd.
5 *
6 * Based on board-kzm9g.c
7 * Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; version 2 of the License.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 */
18
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/irq.h>
22#include <linux/input.h>
23#include <linux/of_platform.h>
24
25#include <asm/hardware/cache-l2x0.h>
26#include <asm/mach-types.h>
27#include <asm/mach/arch.h>
28
29#include "common.h"
30#include "sh73a0.h"
31
32static void __init kzm_init(void)
33{
34 sh73a0_add_standard_devices_dt();
35
36#ifdef CONFIG_CACHE_L2X0
37 /* Shared attribute override enable, 64K*8way */
38 l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
39#endif
40}
41
42#define RESCNT2 IOMEM(0xe6188020)
43static void kzm9g_restart(enum reboot_mode mode, const char *cmd)
44{
45 /* Do soft power on reset */
46 writel((1 << 31), RESCNT2);
47}
48
49static const char *kzm9g_boards_compat_dt[] __initdata = {
50 "renesas,kzm9g-reference",
51 NULL,
52};
53
54DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
55 .smp = smp_ops(sh73a0_smp_ops),
56 .map_io = sh73a0_map_io,
57 .init_early = shmobile_init_delay,
58 .init_machine = kzm_init,
59 .init_late = shmobile_init_late,
60 .restart = kzm9g_restart,
61 .dt_compat = kzm9g_boards_compat_dt,
62MACHINE_END
diff --git a/arch/arm/mach-shmobile/include/mach/zboot.h b/arch/arm/mach-shmobile/include/mach/zboot.h
index 9d9cb09c9336..175ee05465da 100644
--- a/arch/arm/mach-shmobile/include/mach/zboot.h
+++ b/arch/arm/mach-shmobile/include/mach/zboot.h
@@ -9,7 +9,7 @@
9 * 9 *
10 **************************************************/ 10 **************************************************/
11 11
12#if defined(CONFIG_MACH_KZM9G) || defined(CONFIG_MACH_KZM9G_REFERENCE) 12#ifdef CONFIG_MACH_KZM9G
13#define MEMORY_START 0x43000000 13#define MEMORY_START 0x43000000
14#include "mach/head-kzm9g.txt" 14#include "mach/head-kzm9g.txt"
15#else 15#else
diff --git a/arch/arm/mach-shmobile/setup-sh73a0.c b/arch/arm/mach-shmobile/setup-sh73a0.c
index faea74a2151b..fb2ab7590af8 100644
--- a/arch/arm/mach-shmobile/setup-sh73a0.c
+++ b/arch/arm/mach-shmobile/setup-sh73a0.c
@@ -30,6 +30,7 @@
30#include <linux/platform_data/sh_ipmmu.h> 30#include <linux/platform_data/sh_ipmmu.h>
31#include <linux/platform_data/irq-renesas-intc-irqpin.h> 31#include <linux/platform_data/irq-renesas-intc-irqpin.h>
32 32
33#include <asm/hardware/cache-l2x0.h>
33#include <asm/mach-types.h> 34#include <asm/mach-types.h>
34#include <asm/mach/map.h> 35#include <asm/mach/map.h>
35#include <asm/mach/arch.h> 36#include <asm/mach/arch.h>
@@ -784,22 +785,15 @@ void __init sh73a0_add_early_devices(void)
784 785
785#ifdef CONFIG_USE_OF 786#ifdef CONFIG_USE_OF
786 787
787void __init sh73a0_add_standard_devices_dt(void) 788static void __init sh73a0_generic_init(void)
788{ 789{
789 /* clocks are setup late during boot in the case of DT */ 790#ifdef CONFIG_CACHE_L2X0
790#ifndef CONFIG_COMMON_CLK 791 /* Shared attribute override enable, 64K*8way */
791 sh73a0_clock_init(); 792 l2x0_init(IOMEM(0xf0100000), 0x00400000, 0xc20f0fff);
792#endif 793#endif
793 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); 794 of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
794} 795}
795 796
796#define RESCNT2 IOMEM(0xe6188020)
797static void sh73a0_restart(enum reboot_mode mode, const char *cmd)
798{
799 /* Do soft power on reset */
800 writel((1 << 31), RESCNT2);
801}
802
803static const char *sh73a0_boards_compat_dt[] __initdata = { 797static const char *sh73a0_boards_compat_dt[] __initdata = {
804 "renesas,sh73a0", 798 "renesas,sh73a0",
805 NULL, 799 NULL,
@@ -809,9 +803,8 @@ DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
809 .smp = smp_ops(sh73a0_smp_ops), 803 .smp = smp_ops(sh73a0_smp_ops),
810 .map_io = sh73a0_map_io, 804 .map_io = sh73a0_map_io,
811 .init_early = shmobile_init_delay, 805 .init_early = shmobile_init_delay,
812 .init_machine = sh73a0_add_standard_devices_dt, 806 .init_machine = sh73a0_generic_init,
813 .init_late = shmobile_init_late, 807 .init_late = shmobile_init_late,
814 .restart = sh73a0_restart,
815 .dt_compat = sh73a0_boards_compat_dt, 808 .dt_compat = sh73a0_boards_compat_dt,
816MACHINE_END 809MACHINE_END
817#endif /* CONFIG_USE_OF */ 810#endif /* CONFIG_USE_OF */
diff --git a/arch/arm/mach-shmobile/sh73a0.h b/arch/arm/mach-shmobile/sh73a0.h
index f037c64b14fc..5a80f18b4fa0 100644
--- a/arch/arm/mach-shmobile/sh73a0.h
+++ b/arch/arm/mach-shmobile/sh73a0.h
@@ -77,7 +77,6 @@ extern void sh73a0_map_io(void);
77extern void sh73a0_earlytimer_init(void); 77extern void sh73a0_earlytimer_init(void);
78extern void sh73a0_add_early_devices(void); 78extern void sh73a0_add_early_devices(void);
79extern void sh73a0_add_standard_devices(void); 79extern void sh73a0_add_standard_devices(void);
80extern void sh73a0_add_standard_devices_dt(void);
81extern void sh73a0_clock_init(void); 80extern void sh73a0_clock_init(void);
82extern void sh73a0_pinmux_init(void); 81extern void sh73a0_pinmux_init(void);
83extern void sh73a0_pm_init(void); 82extern void sh73a0_pm_init(void);
diff --git a/arch/arm/mach-shmobile/smp-r8a7790.c b/arch/arm/mach-shmobile/smp-r8a7790.c
index 9c3da1345b8b..a5bef873d37e 100644
--- a/arch/arm/mach-shmobile/smp-r8a7790.c
+++ b/arch/arm/mach-shmobile/smp-r8a7790.c
@@ -37,11 +37,11 @@ static struct rcar_sysc_ch r8a7790_ca7_scu = {
37 37
38static struct rcar_apmu_config r8a7790_apmu_config[] = { 38static struct rcar_apmu_config r8a7790_apmu_config[] = {
39 { 39 {
40 .iomem = DEFINE_RES_MEM(0xe6152000, 0x88), 40 .iomem = DEFINE_RES_MEM(0xe6152000, 0x188),
41 .cpus = { 0, 1, 2, 3 }, 41 .cpus = { 0, 1, 2, 3 },
42 }, 42 },
43 { 43 {
44 .iomem = DEFINE_RES_MEM(0xe6151000, 0x88), 44 .iomem = DEFINE_RES_MEM(0xe6151000, 0x188),
45 .cpus = { 0x100, 0x0101, 0x102, 0x103 }, 45 .cpus = { 0x100, 0x0101, 0x102, 0x103 },
46 } 46 }
47}; 47};
diff --git a/arch/arm/mach-shmobile/smp-r8a7791.c b/arch/arm/mach-shmobile/smp-r8a7791.c
index 7e49e0a52e32..de1d92dc1323 100644
--- a/arch/arm/mach-shmobile/smp-r8a7791.c
+++ b/arch/arm/mach-shmobile/smp-r8a7791.c
@@ -27,7 +27,7 @@
27 27
28static struct rcar_apmu_config r8a7791_apmu_config[] = { 28static struct rcar_apmu_config r8a7791_apmu_config[] = {
29 { 29 {
30 .iomem = DEFINE_RES_MEM(0xe6152000, 0x88), 30 .iomem = DEFINE_RES_MEM(0xe6152000, 0x188),
31 .cpus = { 0, 1 }, 31 .cpus = { 0, 1 },
32 } 32 }
33}; 33};
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index c16dbfe9836c..2106d6b76a06 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -33,7 +33,7 @@
33 33
34#define SH73A0_SCU_BASE 0xf0000000 34#define SH73A0_SCU_BASE 0xf0000000
35 35
36#ifdef CONFIG_HAVE_ARM_TWD 36#if defined(CONFIG_HAVE_ARM_TWD) && !defined(CONFIG_ARCH_MULTIPLATFORM)
37static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29); 37static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
38void __init sh73a0_register_twd(void) 38void __init sh73a0_register_twd(void)
39{ 39{
diff --git a/include/dt-bindings/clock/r8a7790-clock.h b/include/dt-bindings/clock/r8a7790-clock.h
index 91940271cf83..3f2c6b198d4a 100644
--- a/include/dt-bindings/clock/r8a7790-clock.h
+++ b/include/dt-bindings/clock/r8a7790-clock.h
@@ -21,6 +21,8 @@
21#define R8A7790_CLK_SD0 7 21#define R8A7790_CLK_SD0 7
22#define R8A7790_CLK_SD1 8 22#define R8A7790_CLK_SD1 8
23#define R8A7790_CLK_Z 9 23#define R8A7790_CLK_Z 9
24#define R8A7790_CLK_RCAN 10
25#define R8A7790_CLK_ADSP 11
24 26
25/* MSTP0 */ 27/* MSTP0 */
26#define R8A7790_CLK_MSIOF0 0 28#define R8A7790_CLK_MSIOF0 0
@@ -80,6 +82,7 @@
80/* MSTP5 */ 82/* MSTP5 */
81#define R8A7790_CLK_AUDIO_DMAC1 1 83#define R8A7790_CLK_AUDIO_DMAC1 1
82#define R8A7790_CLK_AUDIO_DMAC0 2 84#define R8A7790_CLK_AUDIO_DMAC0 2
85#define R8A7790_CLK_ADSP_MOD 6
83#define R8A7790_CLK_THERMAL 22 86#define R8A7790_CLK_THERMAL 22
84#define R8A7790_CLK_PWM 23 87#define R8A7790_CLK_PWM 23
85 88
diff --git a/include/dt-bindings/clock/r8a7791-clock.h b/include/dt-bindings/clock/r8a7791-clock.h
index f096f3f6c16a..8fc5dc8faeea 100644
--- a/include/dt-bindings/clock/r8a7791-clock.h
+++ b/include/dt-bindings/clock/r8a7791-clock.h
@@ -20,6 +20,8 @@
20#define R8A7791_CLK_SDH 6 20#define R8A7791_CLK_SDH 6
21#define R8A7791_CLK_SD0 7 21#define R8A7791_CLK_SD0 7
22#define R8A7791_CLK_Z 8 22#define R8A7791_CLK_Z 8
23#define R8A7791_CLK_RCAN 9
24#define R8A7791_CLK_ADSP 10
23 25
24/* MSTP0 */ 26/* MSTP0 */
25#define R8A7791_CLK_MSIOF0 0 27#define R8A7791_CLK_MSIOF0 0
@@ -71,6 +73,7 @@
71/* MSTP5 */ 73/* MSTP5 */
72#define R8A7791_CLK_AUDIO_DMAC1 1 74#define R8A7791_CLK_AUDIO_DMAC1 1
73#define R8A7791_CLK_AUDIO_DMAC0 2 75#define R8A7791_CLK_AUDIO_DMAC0 2
76#define R8A7791_CLK_ADSP_MOD 6
74#define R8A7791_CLK_THERMAL 22 77#define R8A7791_CLK_THERMAL 22
75#define R8A7791_CLK_PWM 23 78#define R8A7791_CLK_PWM 23
76 79
diff --git a/include/dt-bindings/clock/sh73a0-clock.h b/include/dt-bindings/clock/sh73a0-clock.h
index 1dd3eb2b7d90..53369568c24c 100644
--- a/include/dt-bindings/clock/sh73a0-clock.h
+++ b/include/dt-bindings/clock/sh73a0-clock.h
@@ -76,4 +76,7 @@
76#define SH73A0_CLK_IIC4 10 76#define SH73A0_CLK_IIC4 10
77#define SH73A0_CLK_KEYSC 3 77#define SH73A0_CLK_KEYSC 3
78 78
79/* MSTP5 */
80#define SH73A0_CLK_INTCA0 8
81
79#endif 82#endif
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-23 11:27:32 -0400