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-rw-r--r--arch/sh/Kconfig7
-rw-r--r--arch/sh/Kconfig.debug1
-rw-r--r--arch/sh/include/asm/processor.h2
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h4
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7757.h243
-rw-r--r--arch/sh/kernel/cpu/sh4/probe.c11
-rw-r--r--arch/sh/kernel/cpu/sh4a/Makefile3
-rw-r--r--arch/sh/kernel/cpu/sh4a/clock-sh7757.c130
-rw-r--r--arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c2019
-rw-r--r--arch/sh/kernel/cpu/sh4a/setup-sh7757.c513
-rw-r--r--arch/sh/kernel/setup.c2
-rw-r--r--arch/sh/mm/Kconfig7
-rw-r--r--drivers/serial/sh-sci.c3
-rw-r--r--drivers/serial/sh-sci.h17
14 files changed, 2954 insertions, 8 deletions
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index c4a955d25451..d17570c61dfd 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -396,6 +396,13 @@ config CPU_SUBTYPE_SH7724
396 help 396 help
397 Select SH7724 if you have an SH-MobileR2R CPU. 397 Select SH7724 if you have an SH-MobileR2R CPU.
398 398
399config CPU_SUBTYPE_SH7757
400 bool "Support SH7757 processor"
401 select CPU_SH4A
402 select CPU_SHX2
403 help
404 Select SH7757 if you have a SH4A SH7757 CPU.
405
399config CPU_SUBTYPE_SH7763 406config CPU_SUBTYPE_SH7763
400 bool "Support SH7763 processor" 407 bool "Support SH7763 processor"
401 select CPU_SH4A 408 select CPU_SH4A
diff --git a/arch/sh/Kconfig.debug b/arch/sh/Kconfig.debug
index 741d20fab2e1..55907af1dc25 100644
--- a/arch/sh/Kconfig.debug
+++ b/arch/sh/Kconfig.debug
@@ -38,6 +38,7 @@ config EARLY_SCIF_CONSOLE_PORT
38 default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \ 38 default "0xffe00000" if CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7763 || \
39 CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \ 39 CPU_SUBTYPE_SH7722 || CPU_SUBTYPE_SH7366 || \
40 CPU_SUBTYPE_SH7343 40 CPU_SUBTYPE_SH7343
41 default "0xfe4c0000" if CPU_SUBTYPE_SH7757
41 default "0xffeb0000" if CPU_SUBTYPE_SH7785 42 default "0xffeb0000" if CPU_SUBTYPE_SH7785
42 default "0xffeb0000" if CPU_SUBTYPE_SH7786 43 default "0xffeb0000" if CPU_SUBTYPE_SH7786
43 default "0xfffe8000" if CPU_SUBTYPE_SH7203 44 default "0xfffe8000" if CPU_SUBTYPE_SH7203
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index ff7daaf9a620..9d87868bc53d 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -32,7 +32,7 @@ enum cpu_type {
32 32
33 /* SH-4A types */ 33 /* SH-4A types */
34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786, 34 CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
35 CPU_SH7723, CPU_SH7724, CPU_SHX3, 35 CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
36 36
37 /* SH4AL-DSP types */ 37 /* SH4AL-DSP types */
38 CPU_SH7343, CPU_SH7722, CPU_SH7366, 38 CPU_SH7343, CPU_SH7722, CPU_SH7366,
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index ccf1d999db6d..e1e90960ee9a 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -22,6 +22,10 @@
22#define MSTPCR0 0xa4150030 22#define MSTPCR0 0xa4150030
23#define MSTPCR1 0xa4150034 23#define MSTPCR1 0xa4150034
24#define MSTPCR2 0xa4150038 24#define MSTPCR2 0xa4150038
25#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
26#define FRQCR 0xffc80000
27#define OSCCR 0xffc80018
28#define PLLCR 0xffc80024
25#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 29#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
26 defined(CONFIG_CPU_SUBTYPE_SH7780) 30 defined(CONFIG_CPU_SUBTYPE_SH7780)
27#define FRQCR 0xffc80000 31#define FRQCR 0xffc80000
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7757.h b/arch/sh/include/cpu-sh4/cpu/sh7757.h
new file mode 100644
index 000000000000..f4d267efad71
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7757.h
@@ -0,0 +1,243 @@
1#ifndef __ASM_SH7757_H__
2#define __ASM_SH7757_H__
3
4enum {
5 /* PTA */
6 GPIO_PTA7, GPIO_PTA6, GPIO_PTA5, GPIO_PTA4,
7 GPIO_PTA3, GPIO_PTA2, GPIO_PTA1, GPIO_PTA0,
8
9 /* PTB */
10 GPIO_PTB7, GPIO_PTB6, GPIO_PTB5, GPIO_PTB4,
11 GPIO_PTB3, GPIO_PTB2, GPIO_PTB1, GPIO_PTB0,
12
13 /* PTC */
14 GPIO_PTC7, GPIO_PTC6, GPIO_PTC5, GPIO_PTC4,
15 GPIO_PTC3, GPIO_PTC2, GPIO_PTC1, GPIO_PTC0,
16
17 /* PTD */
18 GPIO_PTD7, GPIO_PTD6, GPIO_PTD5, GPIO_PTD4,
19 GPIO_PTD3, GPIO_PTD2, GPIO_PTD1, GPIO_PTD0,
20
21 /* PTE */
22 GPIO_PTE7, GPIO_PTE6, GPIO_PTE5, GPIO_PTE4,
23 GPIO_PTE3, GPIO_PTE2, GPIO_PTE1, GPIO_PTE0,
24
25 /* PTF */
26 GPIO_PTF7, GPIO_PTF6, GPIO_PTF5, GPIO_PTF4,
27 GPIO_PTF3, GPIO_PTF2, GPIO_PTF1, GPIO_PTF0,
28
29 /* PTG */
30 GPIO_PTG7, GPIO_PTG6, GPIO_PTG5, GPIO_PTG4,
31 GPIO_PTG3, GPIO_PTG2, GPIO_PTG1, GPIO_PTG0,
32
33 /* PTH */
34 GPIO_PTH7, GPIO_PTH6, GPIO_PTH5, GPIO_PTH4,
35 GPIO_PTH3, GPIO_PTH2, GPIO_PTH1, GPIO_PTH0,
36
37 /* PTI */
38 GPIO_PTI7, GPIO_PTI6, GPIO_PTI5, GPIO_PTI4,
39 GPIO_PTI3, GPIO_PTI2, GPIO_PTI1, GPIO_PTI0,
40
41 /* PTJ */
42 GPIO_PTJ7, GPIO_PTJ6, GPIO_PTJ5, GPIO_PTJ4,
43 GPIO_PTJ3, GPIO_PTJ2, GPIO_PTJ1, GPIO_PTJ0,
44
45 /* PTK */
46 GPIO_PTK7, GPIO_PTK6, GPIO_PTK5, GPIO_PTK4,
47 GPIO_PTK3, GPIO_PTK2, GPIO_PTK1, GPIO_PTK0,
48
49 /* PTL */
50 GPIO_PTL7, GPIO_PTL6, GPIO_PTL5, GPIO_PTL4,
51 GPIO_PTL3, GPIO_PTL2, GPIO_PTL1, GPIO_PTL0,
52
53 /* PTM */
54 GPIO_PTM6, GPIO_PTM5, GPIO_PTM4,
55 GPIO_PTM3, GPIO_PTM2, GPIO_PTM1, GPIO_PTM0,
56
57 /* PTN */
58 GPIO_PTN7, GPIO_PTN6, GPIO_PTN5, GPIO_PTN4,
59 GPIO_PTN3, GPIO_PTN2, GPIO_PTN1, GPIO_PTN0,
60
61 /* PTO */
62 GPIO_PTO7, GPIO_PTO6, GPIO_PTO5, GPIO_PTO4,
63 GPIO_PTO3, GPIO_PTO2, GPIO_PTO1, GPIO_PTO0,
64
65 /* PTP */
66 GPIO_PTP6, GPIO_PTP5, GPIO_PTP4,
67 GPIO_PTP3, GPIO_PTP2, GPIO_PTP1, GPIO_PTP0,
68
69 /* PTQ */
70 GPIO_PTQ6, GPIO_PTQ5, GPIO_PTQ4,
71 GPIO_PTQ3, GPIO_PTQ2, GPIO_PTQ1, GPIO_PTQ0,
72
73 /* PTR */
74 GPIO_PTR7, GPIO_PTR6, GPIO_PTR5, GPIO_PTR4,
75 GPIO_PTR3, GPIO_PTR2, GPIO_PTR1, GPIO_PTR0,
76
77 /* PTS */
78 GPIO_PTS7, GPIO_PTS6, GPIO_PTS5, GPIO_PTS4,
79 GPIO_PTS3, GPIO_PTS2, GPIO_PTS1, GPIO_PTS0,
80
81 /* PTT */
82 GPIO_PTT5, GPIO_PTT4,
83 GPIO_PTT3, GPIO_PTT2, GPIO_PTT1, GPIO_PTT0,
84
85 /* PTU */
86 GPIO_PTU7, GPIO_PTU6, GPIO_PTU5, GPIO_PTU4,
87 GPIO_PTU3, GPIO_PTU2, GPIO_PTU1, GPIO_PTU0,
88
89 /* PTV */
90 GPIO_PTV7, GPIO_PTV6, GPIO_PTV5, GPIO_PTV4,
91 GPIO_PTV3, GPIO_PTV2, GPIO_PTV1, GPIO_PTV0,
92
93 /* PTW */
94 GPIO_PTW7, GPIO_PTW6, GPIO_PTW5, GPIO_PTW4,
95 GPIO_PTW3, GPIO_PTW2, GPIO_PTW1, GPIO_PTW0,
96
97 /* PTX */
98 GPIO_PTX7, GPIO_PTX6, GPIO_PTX5, GPIO_PTX4,
99 GPIO_PTX3, GPIO_PTX2, GPIO_PTX1, GPIO_PTX0,
100
101 /* PTY */
102 GPIO_PTY7, GPIO_PTY6, GPIO_PTY5, GPIO_PTY4,
103 GPIO_PTY3, GPIO_PTY2, GPIO_PTY1, GPIO_PTY0,
104
105 /* PTZ */
106 GPIO_PTZ7, GPIO_PTZ6, GPIO_PTZ5, GPIO_PTZ4,
107 GPIO_PTZ3, GPIO_PTZ2, GPIO_PTZ1, GPIO_PTZ0,
108
109
110 /* PTA (mobule: LBSC, CPG, LPC) */
111 GPIO_FN_BS, GPIO_FN_RDWR, GPIO_FN_WE1, GPIO_FN_RDY,
112 GPIO_FN_MD10, GPIO_FN_MD9, GPIO_FN_MD8,
113 GPIO_FN_LGPIO7, GPIO_FN_LGPIO6, GPIO_FN_LGPIO5, GPIO_FN_LGPIO4,
114 GPIO_FN_LGPIO3, GPIO_FN_LGPIO2, GPIO_FN_LGPIO1, GPIO_FN_LGPIO0,
115
116 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
117 GPIO_FN_D15, GPIO_FN_D14, GPIO_FN_D13, GPIO_FN_D12,
118 GPIO_FN_D11, GPIO_FN_D10, GPIO_FN_D9, GPIO_FN_D8,
119 GPIO_FN_ET0_MDC, GPIO_FN_ET0_MDIO,
120 GPIO_FN_ET1_MDC, GPIO_FN_ET1_MDIO,
121 GPIO_FN_SIM_D, GPIO_FN_SIM_CLK, GPIO_FN_SIM_RST,
122 GPIO_FN_WPSZ1, GPIO_FN_WPSZ0, GPIO_FN_FWID, GPIO_FN_FLSHSZ,
123 GPIO_FN_LPC_SPIEN, GPIO_FN_BASEL,
124
125 /* PTC (mobule: SD) */
126 GPIO_FN_SD_WP, GPIO_FN_SD_CD, GPIO_FN_SD_CLK, GPIO_FN_SD_CMD,
127 GPIO_FN_SD_D3, GPIO_FN_SD_D2, GPIO_FN_SD_D1, GPIO_FN_SD_D0,
128
129 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
130 GPIO_FN_IRQ7, GPIO_FN_IRQ6, GPIO_FN_IRQ5, GPIO_FN_IRQ4,
131 GPIO_FN_IRQ3, GPIO_FN_IRQ2, GPIO_FN_IRQ1, GPIO_FN_IRQ0,
132 GPIO_FN_MD6, GPIO_FN_MD5, GPIO_FN_MD3, GPIO_FN_MD2,
133 GPIO_FN_MD1, GPIO_FN_MD0, GPIO_FN_ADTRG1, GPIO_FN_ADTRG0,
134
135 /* PTE (mobule: EtherC) */
136 GPIO_FN_ET0_CRS_DV, GPIO_FN_ET0_TXD1,
137 GPIO_FN_ET0_TXD0, GPIO_FN_ET0_TX_EN,
138 GPIO_FN_ET0_REF_CLK, GPIO_FN_ET0_RXD1,
139 GPIO_FN_ET0_RXD0, GPIO_FN_ET0_RX_ER,
140
141 /* PTF (mobule: EtherC) */
142 GPIO_FN_ET1_CRS_DV, GPIO_FN_ET1_TXD1,
143 GPIO_FN_ET1_TXD0, GPIO_FN_ET1_TX_EN,
144 GPIO_FN_ET1_REF_CLK, GPIO_FN_ET1_RXD1,
145 GPIO_FN_ET1_RXD0, GPIO_FN_ET1_RX_ER,
146
147 /* PTG (mobule: SYSTEM, PWMX, LPC) */
148 GPIO_FN_STATUS0, GPIO_FN_STATUS1,
149 GPIO_FN_PWX0, GPIO_FN_PWX1, GPIO_FN_PWX2, GPIO_FN_PWX3,
150 GPIO_FN_SERIRQ, GPIO_FN_CLKRUN, GPIO_FN_LPCPD, GPIO_FN_LDRQ,
151
152 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
153 GPIO_FN_TCLK, GPIO_FN_RXD4, GPIO_FN_TXD4,
154 GPIO_FN_SP1_MOSI, GPIO_FN_SP1_MISO,
155 GPIO_FN_SP1_SCK, GPIO_FN_SP1_SCK_FB,
156 GPIO_FN_SP1_SS0, GPIO_FN_SP1_SS1,
157 GPIO_FN_SP0_SS1,
158
159 /* PTI (mobule: INTC) */
160 GPIO_FN_IRQ15, GPIO_FN_IRQ14, GPIO_FN_IRQ13, GPIO_FN_IRQ12,
161 GPIO_FN_IRQ11, GPIO_FN_IRQ10, GPIO_FN_IRQ9, GPIO_FN_IRQ8,
162
163 /* PTJ (mobule: SCIF234, SERMUX) */
164 GPIO_FN_RXD3, GPIO_FN_TXD3, GPIO_FN_RXD2, GPIO_FN_TXD2,
165 GPIO_FN_COM1_TXD, GPIO_FN_COM1_RXD,
166 GPIO_FN_COM1_RTS, GPIO_FN_COM1_CTS,
167
168 /* PTK (mobule: SERMUX) */
169 GPIO_FN_COM2_TXD, GPIO_FN_COM2_RXD,
170 GPIO_FN_COM2_RTS, GPIO_FN_COM2_CTS,
171 GPIO_FN_COM2_DTR, GPIO_FN_COM2_DSR,
172 GPIO_FN_COM2_DCD, GPIO_FN_COM2_RI,
173
174 /* PTL (mobule: SERMUX) */
175 GPIO_FN_RAC_TXD, GPIO_FN_RAC_RXD,
176 GPIO_FN_RAC_RTS, GPIO_FN_RAC_CTS,
177 GPIO_FN_RAC_DTR, GPIO_FN_RAC_DSR,
178 GPIO_FN_RAC_DCD, GPIO_FN_RAC_RI,
179
180 /* PTM (mobule: IIC, LPC) */
181 GPIO_FN_SDA6, GPIO_FN_SCL6, GPIO_FN_SDA7, GPIO_FN_SCL7,
182 GPIO_FN_WP, GPIO_FN_FMS0, GPIO_FN_FMS1,
183
184 /* PTN (mobule: SCIF234, EVC) */
185 GPIO_FN_SCK2, GPIO_FN_RTS4, GPIO_FN_RTS3, GPIO_FN_RTS2,
186 GPIO_FN_CTS4, GPIO_FN_CTS3, GPIO_FN_CTS2,
187 GPIO_FN_EVENT7, GPIO_FN_EVENT6, GPIO_FN_EVENT5, GPIO_FN_EVENT4,
188 GPIO_FN_EVENT3, GPIO_FN_EVENT2, GPIO_FN_EVENT1, GPIO_FN_EVENT0,
189
190 /* PTO (mobule: SGPIO) */
191 GPIO_FN_SGPIO0_CLK, GPIO_FN_SGPIO0_LOAD,
192 GPIO_FN_SGPIO0_DI, GPIO_FN_SGPIO0_DO,
193 GPIO_FN_SGPIO1_CLK, GPIO_FN_SGPIO1_LOAD,
194 GPIO_FN_SGPIO1_DI, GPIO_FN_SGPIO1_DO,
195
196 /* PTP (mobule: JMC, SCIF234) */
197 GPIO_FN_JMCTCK, GPIO_FN_JMCTMS, GPIO_FN_JMCTDO, GPIO_FN_JMCTDI,
198 GPIO_FN_JMCRST, GPIO_FN_SCK4, GPIO_FN_SCK3,
199
200 /* PTQ (mobule: LPC) */
201 GPIO_FN_LAD3, GPIO_FN_LAD2, GPIO_FN_LAD1, GPIO_FN_LAD0,
202 GPIO_FN_LFRAME, GPIO_FN_LRESET, GPIO_FN_LCLK,
203
204 /* PTR (mobule: GRA, IIC) */
205 GPIO_FN_DDC3, GPIO_FN_DDC2,
206 GPIO_FN_SDA8, GPIO_FN_SCL8, GPIO_FN_SDA2, GPIO_FN_SCL2,
207 GPIO_FN_SDA1, GPIO_FN_SCL1, GPIO_FN_SDA0, GPIO_FN_SCL0,
208
209 /* PTS (mobule: GRA, IIC) */
210 GPIO_FN_DDC1, GPIO_FN_DDC0,
211 GPIO_FN_SDA9, GPIO_FN_SCL9, GPIO_FN_SDA5, GPIO_FN_SCL5,
212 GPIO_FN_SDA4, GPIO_FN_SCL4, GPIO_FN_SDA3, GPIO_FN_SCL3,
213
214 /* PTT (mobule: SYSTEM, PWMX) */
215 GPIO_FN_AUDSYNC, GPIO_FN_AUDCK,
216 GPIO_FN_AUDATA3, GPIO_FN_AUDATA2,
217 GPIO_FN_AUDATA1, GPIO_FN_AUDATA0,
218 GPIO_FN_PWX7, GPIO_FN_PWX6, GPIO_FN_PWX5, GPIO_FN_PWX4,
219
220 /* PTU (mobule: LBSC, DMAC) */
221 GPIO_FN_CS6, GPIO_FN_CS5, GPIO_FN_CS4, GPIO_FN_CS0,
222 GPIO_FN_RD, GPIO_FN_WE0, GPIO_FN_A25, GPIO_FN_A24,
223 GPIO_FN_DREQ0, GPIO_FN_DACK0,
224
225 /* PTV (mobule: LBSC, DMAC) */
226 GPIO_FN_A23, GPIO_FN_A22, GPIO_FN_A21, GPIO_FN_A20,
227 GPIO_FN_A19, GPIO_FN_A18, GPIO_FN_A17, GPIO_FN_A16,
228 GPIO_FN_TEND0, GPIO_FN_DREQ1, GPIO_FN_DACK1, GPIO_FN_TEND1,
229
230 /* PTW (mobule: LBSC) */
231 GPIO_FN_A15, GPIO_FN_A14, GPIO_FN_A13, GPIO_FN_A12,
232 GPIO_FN_A11, GPIO_FN_A10, GPIO_FN_A9, GPIO_FN_A8,
233
234 /* PTX (mobule: LBSC) */
235 GPIO_FN_A7, GPIO_FN_A6, GPIO_FN_A5, GPIO_FN_A4,
236 GPIO_FN_A3, GPIO_FN_A2, GPIO_FN_A1, GPIO_FN_A0,
237
238 /* PTY (mobule: LBSC) */
239 GPIO_FN_D7, GPIO_FN_D6, GPIO_FN_D5, GPIO_FN_D4,
240 GPIO_FN_D3, GPIO_FN_D2, GPIO_FN_D1, GPIO_FN_D0,
241};
242
243#endif /* __ASM_SH7757_H__ */
diff --git a/arch/sh/kernel/cpu/sh4/probe.c b/arch/sh/kernel/cpu/sh4/probe.c
index 6c78d0a9c857..10e6795b56aa 100644
--- a/arch/sh/kernel/cpu/sh4/probe.c
+++ b/arch/sh/kernel/cpu/sh4/probe.c
@@ -139,8 +139,15 @@ int __init detect_cpu_and_cache_system(void)
139 } 139 }
140 break; 140 break;
141 case 0x300b: 141 case 0x300b:
142 boot_cpu_data.type = CPU_SH7724; 142 switch (prr) {
143 boot_cpu_data.flags |= CPU_HAS_L2_CACHE; 143 case 0x20:
144 boot_cpu_data.type = CPU_SH7723;
145 boot_cpu_data.flags |= CPU_HAS_L2_CACHE;
146 break;
147 case 0x50:
148 boot_cpu_data.type = CPU_SH7757;
149 break;
150 }
144 break; 151 break;
145 case 0x4000: /* 1st cut */ 152 case 0x4000: /* 1st cut */
146 case 0x4001: /* 2nd cut */ 153 case 0x4001: /* 2nd cut */
diff --git a/arch/sh/kernel/cpu/sh4a/Makefile b/arch/sh/kernel/cpu/sh4a/Makefile
index 12cddf4c721d..490d5dc9e372 100644
--- a/arch/sh/kernel/cpu/sh4a/Makefile
+++ b/arch/sh/kernel/cpu/sh4a/Makefile
@@ -3,6 +3,7 @@
3# 3#
4 4
5# CPU subtype setup 5# CPU subtype setup
6obj-$(CONFIG_CPU_SUBTYPE_SH7757) += setup-sh7757.o
6obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o 7obj-$(CONFIG_CPU_SUBTYPE_SH7763) += setup-sh7763.o
7obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o 8obj-$(CONFIG_CPU_SUBTYPE_SH7770) += setup-sh7770.o
8obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o 9obj-$(CONFIG_CPU_SUBTYPE_SH7780) += setup-sh7780.o
@@ -19,6 +20,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SHX3) += setup-shx3.o
19smp-$(CONFIG_CPU_SHX3) := smp-shx3.o 20smp-$(CONFIG_CPU_SHX3) := smp-shx3.o
20 21
21# Primary on-chip clocks (common) 22# Primary on-chip clocks (common)
23clock-$(CONFIG_CPU_SUBTYPE_SH7757) := clock-sh7757.o
22clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o 24clock-$(CONFIG_CPU_SUBTYPE_SH7763) := clock-sh7763.o
23clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o 25clock-$(CONFIG_CPU_SUBTYPE_SH7770) := clock-sh7770.o
24clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o 26clock-$(CONFIG_CPU_SUBTYPE_SH7780) := clock-sh7780.o
@@ -35,6 +37,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3) := clock-shx3.o
35pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o 37pinmux-$(CONFIG_CPU_SUBTYPE_SH7722) := pinmux-sh7722.o
36pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o 38pinmux-$(CONFIG_CPU_SUBTYPE_SH7723) := pinmux-sh7723.o
37pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o 39pinmux-$(CONFIG_CPU_SUBTYPE_SH7724) := pinmux-sh7724.o
40pinmux-$(CONFIG_CPU_SUBTYPE_SH7757) := pinmux-sh7757.o
38pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o 41pinmux-$(CONFIG_CPU_SUBTYPE_SH7785) := pinmux-sh7785.o
39pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o 42pinmux-$(CONFIG_CPU_SUBTYPE_SH7786) := pinmux-sh7786.o
40 43
diff --git a/arch/sh/kernel/cpu/sh4a/clock-sh7757.c b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
new file mode 100644
index 000000000000..ddc235ca9664
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/clock-sh7757.c
@@ -0,0 +1,130 @@
1/*
2 * arch/sh/kernel/cpu/sh4/clock-sh7757.c
3 *
4 * SH7757 support for the clock framework
5 *
6 * Copyright (C) 2009 Renesas Solutions Corp.
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/init.h>
13#include <linux/kernel.h>
14#include <linux/io.h>
15#include <asm/clock.h>
16#include <asm/freq.h>
17
18static int ifc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
19 16, 1, 1, 32, 1, 1, 1, 1 };
20static int sfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
21 16, 1, 1, 32, 1, 1, 1, 1 };
22static int bfc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
23 16, 1, 1, 32, 1, 1, 1, 1 };
24static int p1fc_divisors[] = { 2, 1, 4, 1, 1, 8, 1, 1,
25 16, 1, 1, 32, 1, 1, 1, 1 };
26
27static void master_clk_init(struct clk *clk)
28{
29 clk->rate = CONFIG_SH_PCLK_FREQ * 16;
30}
31
32static struct clk_ops sh7757_master_clk_ops = {
33 .init = master_clk_init,
34};
35
36static void module_clk_recalc(struct clk *clk)
37{
38 int idx = ctrl_inl(FRQCR) & 0x0000000f;
39 clk->rate = clk->parent->rate / p1fc_divisors[idx];
40}
41
42static struct clk_ops sh7757_module_clk_ops = {
43 .recalc = module_clk_recalc,
44};
45
46static void bus_clk_recalc(struct clk *clk)
47{
48 int idx = (ctrl_inl(FRQCR) >> 8) & 0x0000000f;
49 clk->rate = clk->parent->rate / bfc_divisors[idx];
50}
51
52static struct clk_ops sh7757_bus_clk_ops = {
53 .recalc = bus_clk_recalc,
54};
55
56static void cpu_clk_recalc(struct clk *clk)
57{
58 int idx = (ctrl_inl(FRQCR) >> 20) & 0x0000000f;
59 clk->rate = clk->parent->rate / ifc_divisors[idx];
60}
61
62static struct clk_ops sh7757_cpu_clk_ops = {
63 .recalc = cpu_clk_recalc,
64};
65
66static struct clk_ops *sh7757_clk_ops[] = {
67 &sh7757_master_clk_ops,
68 &sh7757_module_clk_ops,
69 &sh7757_bus_clk_ops,
70 &sh7757_cpu_clk_ops,
71};
72
73void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
74{
75 if (idx < ARRAY_SIZE(sh7757_clk_ops))
76 *ops = sh7757_clk_ops[idx];
77}
78
79static void shyway_clk_recalc(struct clk *clk)
80{
81 int idx = (ctrl_inl(FRQCR) >> 12) & 0x0000000f;
82 clk->rate = clk->parent->rate / sfc_divisors[idx];
83}
84
85static struct clk_ops sh7757_shyway_clk_ops = {
86 .recalc = shyway_clk_recalc,
87};
88
89static struct clk sh7757_shyway_clk = {
90 .name = "shyway_clk",
91 .flags = CLK_ENABLE_ON_INIT,
92 .ops = &sh7757_shyway_clk_ops,
93};
94
95/*
96 * Additional sh7757-specific on-chip clocks that aren't already part of the
97 * clock framework
98 */
99static struct clk *sh7757_onchip_clocks[] = {
100 &sh7757_shyway_clk,
101};
102
103static int __init sh7757_clk_init(void)
104{
105 struct clk *clk = clk_get(NULL, "master_clk");
106 int i;
107
108 for (i = 0; i < ARRAY_SIZE(sh7757_onchip_clocks); i++) {
109 struct clk *clkp = sh7757_onchip_clocks[i];
110
111 clkp->parent = clk;
112 clk_register(clkp);
113 clk_enable(clkp);
114 }
115
116 /*
117 * Now that we have the rest of the clocks registered, we need to
118 * force the parent clock to propagate so that these clocks will
119 * automatically figure out their rate. We cheat by handing the
120 * parent clock its current rate and forcing child propagation.
121 */
122 clk_set_rate(clk, clk_get_rate(clk));
123
124 clk_put(clk);
125
126 return 0;
127}
128
129arch_initcall(sh7757_clk_init);
130
diff --git a/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
new file mode 100644
index 000000000000..ed23b155c097
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
@@ -0,0 +1,2019 @@
1/*
2 * SH7757 (A0 step) Pinmux
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * Author : Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
7 *
8 * Based on SH7757 Pinmux
9 * Copyright (C) 2008 Magnus Damm
10 *
11 * This file is subject to the terms and conditions of the GNU General Public
12 * License. See the file "COPYING" in the main directory of this archive
13 * for more details.
14 */
15
16#include <linux/init.h>
17#include <linux/kernel.h>
18#include <linux/gpio.h>
19#include <cpu/sh7757.h>
20
21enum {
22 PINMUX_RESERVED = 0,
23
24 PINMUX_DATA_BEGIN,
25 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
26 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA,
27 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
28 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA,
29 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
30 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA,
31 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
32 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA,
33 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
34 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA,
35 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
36 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA,
37 PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
38 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA,
39 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
40 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA,
41 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
42 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA,
43 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
44 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA,
45 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
46 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA,
47 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
48 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA,
49 PTM6_DATA, PTM5_DATA, PTM4_DATA,
50 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA,
51 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
52 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA,
53 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
54 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA,
55 PTP6_DATA, PTP5_DATA, PTP4_DATA,
56 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA,
57 PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
58 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA,
59 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
60 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA,
61 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
62 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA,
63 PTT5_DATA, PTT4_DATA,
64 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA,
65 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
66 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA,
67 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
68 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA,
69 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
70 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA,
71 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
72 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA,
73 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
74 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA,
75 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
76 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA,
77 PINMUX_DATA_END,
78
79 PINMUX_INPUT_BEGIN,
80 PTA7_IN, PTA6_IN, PTA5_IN, PTA4_IN,
81 PTA3_IN, PTA2_IN, PTA1_IN, PTA0_IN,
82 PTB7_IN, PTB6_IN, PTB5_IN, PTB4_IN,
83 PTB3_IN, PTB2_IN, PTB1_IN, PTB0_IN,
84 PTC7_IN, PTC6_IN, PTC5_IN, PTC4_IN,
85 PTC3_IN, PTC2_IN, PTC1_IN, PTC0_IN,
86 PTD7_IN, PTD6_IN, PTD5_IN, PTD4_IN,
87 PTD3_IN, PTD2_IN, PTD1_IN, PTD0_IN,
88 PTE7_IN, PTE6_IN, PTE5_IN, PTE4_IN,
89 PTE3_IN, PTE2_IN, PTE1_IN, PTE0_IN,
90 PTF7_IN, PTF6_IN, PTF5_IN, PTF4_IN,
91 PTF3_IN, PTF2_IN, PTF1_IN, PTF0_IN,
92 PTG7_IN, PTG6_IN, PTG5_IN, PTG4_IN,
93 PTG3_IN, PTG2_IN, PTG1_IN, PTG0_IN,
94 PTH7_IN, PTH6_IN, PTH5_IN, PTH4_IN,
95 PTH3_IN, PTH2_IN, PTH1_IN, PTH0_IN,
96 PTI7_IN, PTI6_IN, PTI5_IN, PTI4_IN,
97 PTI3_IN, PTI2_IN, PTI1_IN, PTI0_IN,
98 PTJ7_IN, PTJ6_IN, PTJ5_IN, PTJ4_IN,
99 PTJ3_IN, PTJ2_IN, PTJ1_IN, PTJ0_IN,
100 PTK7_IN, PTK6_IN, PTK5_IN, PTK4_IN,
101 PTK3_IN, PTK2_IN, PTK1_IN, PTK0_IN,
102 PTL7_IN, PTL6_IN, PTL5_IN, PTL4_IN,
103 PTL3_IN, PTL2_IN, PTL1_IN, PTL0_IN,
104 PTM6_IN, PTM5_IN, PTM4_IN,
105 PTM3_IN, PTM2_IN, PTM1_IN, PTM0_IN,
106 PTN7_IN, PTN6_IN, PTN5_IN, PTN4_IN,
107 PTN3_IN, PTN2_IN, PTN1_IN, PTN0_IN,
108 PTO7_IN, PTO6_IN, PTO5_IN, PTO4_IN,
109 PTO3_IN, PTO2_IN, PTO1_IN, PTO0_IN,
110 PTP6_IN, PTP5_IN, PTP4_IN,
111 PTP3_IN, PTP2_IN, PTP1_IN, PTP0_IN,
112 PTQ6_IN, PTQ5_IN, PTQ4_IN,
113 PTQ3_IN, PTQ2_IN, PTQ1_IN, PTQ0_IN,
114 PTR7_IN, PTR6_IN, PTR5_IN, PTR4_IN,
115 PTR3_IN, PTR2_IN, PTR1_IN, PTR0_IN,
116 PTS7_IN, PTS6_IN, PTS5_IN, PTS4_IN,
117 PTS3_IN, PTS2_IN, PTS1_IN, PTS0_IN,
118 PTT5_IN, PTT4_IN,
119 PTT3_IN, PTT2_IN, PTT1_IN, PTT0_IN,
120 PTU7_IN, PTU6_IN, PTU5_IN, PTU4_IN,
121 PTU3_IN, PTU2_IN, PTU1_IN, PTU0_IN,
122 PTV7_IN, PTV6_IN, PTV5_IN, PTV4_IN,
123 PTV3_IN, PTV2_IN, PTV1_IN, PTV0_IN,
124 PTW7_IN, PTW6_IN, PTW5_IN, PTW4_IN,
125 PTW3_IN, PTW2_IN, PTW1_IN, PTW0_IN,
126 PTX7_IN, PTX6_IN, PTX5_IN, PTX4_IN,
127 PTX3_IN, PTX2_IN, PTX1_IN, PTX0_IN,
128 PTY7_IN, PTY6_IN, PTY5_IN, PTY4_IN,
129 PTY3_IN, PTY2_IN, PTY1_IN, PTY0_IN,
130 PTZ7_IN, PTZ6_IN, PTZ5_IN, PTZ4_IN,
131 PTZ3_IN, PTZ2_IN, PTZ1_IN, PTZ0_IN,
132 PINMUX_INPUT_END,
133
134 PINMUX_INPUT_PULLUP_BEGIN,
135 PTU7_IN_PU, PTU6_IN_PU, PTU5_IN_PU, PTU4_IN_PU,
136 PTU3_IN_PU, PTU2_IN_PU, PTU1_IN_PU, PTU0_IN_PU,
137 PTV7_IN_PU, PTV6_IN_PU, PTV5_IN_PU, PTV4_IN_PU,
138 PTV3_IN_PU, PTV2_IN_PU, PTV1_IN_PU, PTV0_IN_PU,
139 PTW7_IN_PU, PTW6_IN_PU, PTW5_IN_PU, PTW4_IN_PU,
140 PTW3_IN_PU, PTW2_IN_PU, PTW1_IN_PU, PTW0_IN_PU,
141 PTX7_IN_PU, PTX6_IN_PU, PTX5_IN_PU, PTX4_IN_PU,
142 PTX3_IN_PU, PTX2_IN_PU, PTX1_IN_PU, PTX0_IN_PU,
143 PTY7_IN_PU, PTY6_IN_PU, PTY5_IN_PU, PTY4_IN_PU,
144 PTY3_IN_PU, PTY2_IN_PU, PTY1_IN_PU, PTY0_IN_PU,
145 PINMUX_INPUT_PULLUP_END,
146
147 PINMUX_OUTPUT_BEGIN,
148 PTA7_OUT, PTA6_OUT, PTA5_OUT, PTA4_OUT,
149 PTA3_OUT, PTA2_OUT, PTA1_OUT, PTA0_OUT,
150 PTB7_OUT, PTB6_OUT, PTB5_OUT, PTB4_OUT,
151 PTB3_OUT, PTB2_OUT, PTB1_OUT, PTB0_OUT,
152 PTC7_OUT, PTC6_OUT, PTC5_OUT, PTC4_OUT,
153 PTC3_OUT, PTC2_OUT, PTC1_OUT, PTC0_OUT,
154 PTD7_OUT, PTD6_OUT, PTD5_OUT, PTD4_OUT,
155 PTD3_OUT, PTD2_OUT, PTD1_OUT, PTD0_OUT,
156 PTE7_OUT, PTE6_OUT, PTE5_OUT, PTE4_OUT,
157 PTE3_OUT, PTE2_OUT, PTE1_OUT, PTE0_OUT,
158 PTF7_OUT, PTF6_OUT, PTF5_OUT, PTF4_OUT,
159 PTF3_OUT, PTF2_OUT, PTF1_OUT, PTF0_OUT,
160 PTG7_OUT, PTG6_OUT, PTG5_OUT, PTG4_OUT,
161 PTG3_OUT, PTG2_OUT, PTG1_OUT, PTG0_OUT,
162 PTH7_OUT, PTH6_OUT, PTH5_OUT, PTH4_OUT,
163 PTH3_OUT, PTH2_OUT, PTH1_OUT, PTH0_OUT,
164 PTI7_OUT, PTI6_OUT, PTI5_OUT, PTI4_OUT,
165 PTI3_OUT, PTI2_OUT, PTI1_OUT, PTI0_OUT,
166 PTJ7_OUT, PTJ6_OUT, PTJ5_OUT, PTJ4_OUT,
167 PTJ3_OUT, PTJ2_OUT, PTJ1_OUT, PTJ0_OUT,
168 PTK7_OUT, PTK6_OUT, PTK5_OUT, PTK4_OUT,
169 PTK3_OUT, PTK2_OUT, PTK1_OUT, PTK0_OUT,
170 PTL7_OUT, PTL6_OUT, PTL5_OUT, PTL4_OUT,
171 PTL3_OUT, PTL2_OUT, PTL1_OUT, PTL0_OUT,
172 PTM6_OUT, PTM5_OUT, PTM4_OUT,
173 PTM3_OUT, PTM2_OUT, PTM1_OUT, PTM0_OUT,
174 PTN7_OUT, PTN6_OUT, PTN5_OUT, PTN4_OUT,
175 PTN3_OUT, PTN2_OUT, PTN1_OUT, PTN0_OUT,
176 PTO7_OUT, PTO6_OUT, PTO5_OUT, PTO4_OUT,
177 PTO3_OUT, PTO2_OUT, PTO1_OUT, PTO0_OUT,
178 PTP6_OUT, PTP5_OUT, PTP4_OUT,
179 PTP3_OUT, PTP2_OUT, PTP1_OUT, PTP0_OUT,
180 PTQ6_OUT, PTQ5_OUT, PTQ4_OUT,
181 PTQ3_OUT, PTQ2_OUT, PTQ1_OUT, PTQ0_OUT,
182 PTR7_OUT, PTR6_OUT, PTR5_OUT, PTR4_OUT,
183 PTR3_OUT, PTR2_OUT, PTR1_OUT, PTR0_OUT,
184 PTS7_OUT, PTS6_OUT, PTS5_OUT, PTS4_OUT,
185 PTS3_OUT, PTS2_OUT, PTS1_OUT, PTS0_OUT,
186 PTT5_OUT, PTT4_OUT,
187 PTT3_OUT, PTT2_OUT, PTT1_OUT, PTT0_OUT,
188 PTU7_OUT, PTU6_OUT, PTU5_OUT, PTU4_OUT,
189 PTU3_OUT, PTU2_OUT, PTU1_OUT, PTU0_OUT,
190 PTV7_OUT, PTV6_OUT, PTV5_OUT, PTV4_OUT,
191 PTV3_OUT, PTV2_OUT, PTV1_OUT, PTV0_OUT,
192 PTW7_OUT, PTW6_OUT, PTW5_OUT, PTW4_OUT,
193 PTW3_OUT, PTW2_OUT, PTW1_OUT, PTW0_OUT,
194 PTX7_OUT, PTX6_OUT, PTX5_OUT, PTX4_OUT,
195 PTX3_OUT, PTX2_OUT, PTX1_OUT, PTX0_OUT,
196 PTY7_OUT, PTY6_OUT, PTY5_OUT, PTY4_OUT,
197 PTY3_OUT, PTY2_OUT, PTY1_OUT, PTY0_OUT,
198 PTZ7_OUT, PTZ6_OUT, PTZ5_OUT, PTZ4_OUT,
199 PTZ3_OUT, PTZ2_OUT, PTZ1_OUT, PTZ0_OUT,
200 PINMUX_OUTPUT_END,
201
202 PINMUX_FUNCTION_BEGIN,
203 PTA7_FN, PTA6_FN, PTA5_FN, PTA4_FN,
204 PTA3_FN, PTA2_FN, PTA1_FN, PTA0_FN,
205 PTB7_FN, PTB6_FN, PTB5_FN, PTB4_FN,
206 PTB3_FN, PTB2_FN, PTB1_FN, PTB0_FN,
207 PTC7_FN, PTC6_FN, PTC5_FN, PTC4_FN,
208 PTC3_FN, PTC2_FN, PTC1_FN, PTC0_FN,
209 PTD7_FN, PTD6_FN, PTD5_FN, PTD4_FN,
210 PTD3_FN, PTD2_FN, PTD1_FN, PTD0_FN,
211 PTE7_FN, PTE6_FN, PTE5_FN, PTE4_FN,
212 PTE3_FN, PTE2_FN, PTE1_FN, PTE0_FN,
213 PTF7_FN, PTF6_FN, PTF5_FN, PTF4_FN,
214 PTF3_FN, PTF2_FN, PTF1_FN, PTF0_FN,
215 PTG7_FN, PTG6_FN, PTG5_FN, PTG4_FN,
216 PTG3_FN, PTG2_FN, PTG1_FN, PTG0_FN,
217 PTH7_FN, PTH6_FN, PTH5_FN, PTH4_FN,
218 PTH3_FN, PTH2_FN, PTH1_FN, PTH0_FN,
219 PTI7_FN, PTI6_FN, PTI5_FN, PTI4_FN,
220 PTI3_FN, PTI2_FN, PTI1_FN, PTI0_FN,
221 PTJ7_FN, PTJ6_FN, PTJ5_FN, PTJ4_FN,
222 PTJ3_FN, PTJ2_FN, PTJ1_FN, PTJ0_FN,
223 PTK7_FN, PTK6_FN, PTK5_FN, PTK4_FN,
224 PTK3_FN, PTK2_FN, PTK1_FN, PTK0_FN,
225 PTL7_FN, PTL6_FN, PTL5_FN, PTL4_FN,
226 PTL3_FN, PTL2_FN, PTL1_FN, PTL0_FN,
227 PTM6_FN, PTM5_FN, PTM4_FN,
228 PTM3_FN, PTM2_FN, PTM1_FN, PTM0_FN,
229 PTN7_FN, PTN6_FN, PTN5_FN, PTN4_FN,
230 PTN3_FN, PTN2_FN, PTN1_FN, PTN0_FN,
231 PTO7_FN, PTO6_FN, PTO5_FN, PTO4_FN,
232 PTO3_FN, PTO2_FN, PTO1_FN, PTO0_FN,
233 PTP6_FN, PTP5_FN, PTP4_FN,
234 PTP3_FN, PTP2_FN, PTP1_FN, PTP0_FN,
235 PTQ6_FN, PTQ5_FN, PTQ4_FN,
236 PTQ3_FN, PTQ2_FN, PTQ1_FN, PTQ0_FN,
237 PTR7_FN, PTR6_FN, PTR5_FN, PTR4_FN,
238 PTR3_FN, PTR2_FN, PTR1_FN, PTR0_FN,
239 PTS7_FN, PTS6_FN, PTS5_FN, PTS4_FN,
240 PTS3_FN, PTS2_FN, PTS1_FN, PTS0_FN,
241 PTT5_FN, PTT4_FN,
242 PTT3_FN, PTT2_FN, PTT1_FN, PTT0_FN,
243 PTU7_FN, PTU6_FN, PTU5_FN, PTU4_FN,
244 PTU3_FN, PTU2_FN, PTU1_FN, PTU0_FN,
245 PTV7_FN, PTV6_FN, PTV5_FN, PTV4_FN,
246 PTV3_FN, PTV2_FN, PTV1_FN, PTV0_FN,
247 PTW7_FN, PTW6_FN, PTW5_FN, PTW4_FN,
248 PTW3_FN, PTW2_FN, PTW1_FN, PTW0_FN,
249 PTX7_FN, PTX6_FN, PTX5_FN, PTX4_FN,
250 PTX3_FN, PTX2_FN, PTX1_FN, PTX0_FN,
251 PTY7_FN, PTY6_FN, PTY5_FN, PTY4_FN,
252 PTY3_FN, PTY2_FN, PTY1_FN, PTY0_FN,
253 PTZ7_FN, PTZ6_FN, PTZ5_FN, PTZ4_FN,
254 PTZ3_FN, PTZ2_FN, PTZ1_FN, PTZ0_FN,
255
256 PS0_15_FN1, PS0_15_FN3,
257 PS0_14_FN1, PS0_14_FN3,
258 PS0_13_FN1, PS0_13_FN3,
259 PS0_12_FN1, PS0_12_FN3,
260 PS0_7_FN1, PS0_7_FN2,
261 PS0_6_FN1, PS0_6_FN2,
262 PS0_5_FN1, PS0_5_FN2,
263 PS0_4_FN1, PS0_4_FN2,
264 PS0_3_FN1, PS0_3_FN2,
265 PS0_2_FN1, PS0_2_FN2,
266 PS0_1_FN1, PS0_1_FN2,
267
268 PS1_7_FN1, PS1_7_FN3,
269 PS1_6_FN1, PS1_6_FN3,
270
271 PS2_13_FN1, PS2_13_FN3,
272 PS2_12_FN1, PS2_12_FN3,
273 PS2_1_FN1, PS2_1_FN2,
274 PS2_0_FN1, PS2_0_FN2,
275
276 PS4_15_FN1, PS4_15_FN2,
277 PS4_14_FN1, PS4_14_FN2,
278 PS4_13_FN1, PS4_13_FN2,
279 PS4_12_FN1, PS4_12_FN2,
280 PS4_11_FN1, PS4_11_FN2,
281 PS4_10_FN1, PS4_10_FN2,
282 PS4_9_FN1, PS4_9_FN2,
283 PS4_3_FN1, PS4_3_FN2,
284 PS4_2_FN1, PS4_2_FN2,
285 PS4_1_FN1, PS4_1_FN2,
286 PS4_0_FN1, PS4_0_FN2,
287
288 PS5_9_FN1, PS5_9_FN2,
289 PS5_8_FN1, PS5_8_FN2,
290 PS5_7_FN1, PS5_7_FN2,
291 PS5_6_FN1, PS5_6_FN2,
292 PS5_5_FN1, PS5_5_FN2,
293 PS5_4_FN1, PS5_4_FN2,
294
295 /* AN15 to 8 : EVENT15 to 8 */
296 PS6_7_FN_AN, PS6_7_FN_EV,
297 PS6_6_FN_AN, PS6_6_FN_EV,
298 PS6_5_FN_AN, PS6_5_FN_EV,
299 PS6_4_FN_AN, PS6_4_FN_EV,
300 PS6_3_FN_AN, PS6_3_FN_EV,
301 PS6_2_FN_AN, PS6_2_FN_EV,
302 PS6_1_FN_AN, PS6_1_FN_EV,
303 PS6_0_FN_AN, PS6_0_FN_EV,
304
305 PINMUX_FUNCTION_END,
306
307 PINMUX_MARK_BEGIN,
308 /* PTA (mobule: LBSC, CPG, LPC) */
309 BS_MARK, RDWR_MARK, WE1_MARK, RDY_MARK,
310 MD10_MARK, MD9_MARK, MD8_MARK,
311 LGPIO7_MARK, LGPIO6_MARK, LGPIO5_MARK, LGPIO4_MARK,
312 LGPIO3_MARK, LGPIO2_MARK, LGPIO1_MARK, LGPIO0_MARK,
313
314 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
315 D15_MARK, D14_MARK, D13_MARK, D12_MARK,
316 D11_MARK, D10_MARK, D9_MARK, D8_MARK,
317 ET0_MDC_MARK, ET0_MDIO_MARK, ET1_MDC_MARK, ET1_MDIO_MARK,
318 SIM_D_MARK, SIM_CLK_MARK, SIM_RST_MARK,
319 WPSZ1_MARK, WPSZ0_MARK, FWID_MARK, FLSHSZ_MARK,
320 LPC_SPIEN_MARK, BASEL_MARK,
321
322 /* PTC (mobule: SD) */
323 SD_WP_MARK, SD_CD_MARK, SD_CLK_MARK, SD_CMD_MARK,
324 SD_D3_MARK, SD_D2_MARK, SD_D1_MARK, SD_D0_MARK,
325
326 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
327 IRQ7_MARK, IRQ6_MARK, IRQ5_MARK, IRQ4_MARK,
328 IRQ3_MARK, IRQ2_MARK, IRQ1_MARK, IRQ0_MARK,
329 MD6_MARK, MD5_MARK, MD3_MARK, MD2_MARK,
330 MD1_MARK, MD0_MARK, ADTRG1_MARK, ADTRG0_MARK,
331
332 /* PTE (mobule: EtherC) */
333 ET0_CRS_DV_MARK, ET0_TXD1_MARK,
334 ET0_TXD0_MARK, ET0_TX_EN_MARK,
335 ET0_REF_CLK_MARK, ET0_RXD1_MARK,
336 ET0_RXD0_MARK, ET0_RX_ER_MARK,
337
338 /* PTF (mobule: EtherC) */
339 ET1_CRS_DV_MARK, ET1_TXD1_MARK,
340 ET1_TXD0_MARK, ET1_TX_EN_MARK,
341 ET1_REF_CLK_MARK, ET1_RXD1_MARK,
342 ET1_RXD0_MARK, ET1_RX_ER_MARK,
343
344 /* PTG (mobule: SYSTEM, PWMX, LPC) */
345 STATUS0_MARK, STATUS1_MARK,
346 PWX0_MARK, PWX1_MARK, PWX2_MARK, PWX3_MARK,
347 SERIRQ_MARK, CLKRUN_MARK, LPCPD_MARK, LDRQ_MARK,
348
349 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
350 TCLK_MARK, RXD4_MARK, TXD4_MARK,
351 SP1_MOSI_MARK, SP1_MISO_MARK, SP1_SCK_MARK, SP1_SCK_FB_MARK,
352 SP1_SS0_MARK, SP1_SS1_MARK, SP0_SS1_MARK,
353
354 /* PTI (mobule: INTC) */
355 IRQ15_MARK, IRQ14_MARK, IRQ13_MARK, IRQ12_MARK,
356 IRQ11_MARK, IRQ10_MARK, IRQ9_MARK, IRQ8_MARK,
357
358 /* PTJ (mobule: SCIF234, SERMUX) */
359 RXD3_MARK, TXD3_MARK, RXD2_MARK, TXD2_MARK,
360 COM1_TXD_MARK, COM1_RXD_MARK, COM1_RTS_MARK, COM1_CTS_MARK,
361
362 /* PTK (mobule: SERMUX) */
363 COM2_TXD_MARK, COM2_RXD_MARK, COM2_RTS_MARK, COM2_CTS_MARK,
364 COM2_DTR_MARK, COM2_DSR_MARK, COM2_DCD_MARK, COM2_RI_MARK,
365
366 /* PTL (mobule: SERMUX) */
367 RAC_TXD_MARK, RAC_RXD_MARK, RAC_RTS_MARK, RAC_CTS_MARK,
368 RAC_DTR_MARK, RAC_DSR_MARK, RAC_DCD_MARK, RAC_RI_MARK,
369
370 /* PTM (mobule: IIC, LPC) */
371 SDA6_MARK, SCL6_MARK, SDA7_MARK, SCL7_MARK,
372 WP_MARK, FMS0_MARK, FMS1_MARK,
373
374 /* PTN (mobule: SCIF234, EVC) */
375 SCK2_MARK, RTS4_MARK, RTS3_MARK, RTS2_MARK,
376 CTS4_MARK, CTS3_MARK, CTS2_MARK,
377 EVENT7_MARK, EVENT6_MARK, EVENT5_MARK, EVENT4_MARK,
378 EVENT3_MARK, EVENT2_MARK, EVENT1_MARK, EVENT0_MARK,
379
380 /* PTO (mobule: SGPIO) */
381 SGPIO0_CLK_MARK, SGPIO0_LOAD_MARK,
382 SGPIO0_DI_MARK, SGPIO0_DO_MARK,
383 SGPIO1_CLK_MARK, SGPIO1_LOAD_MARK,
384 SGPIO1_DI_MARK, SGPIO1_DO_MARK,
385
386 /* PTP (mobule: JMC, SCIF234) */
387 JMCTCK_MARK, JMCTMS_MARK, JMCTDO_MARK, JMCTDI_MARK,
388 JMCRST_MARK, SCK4_MARK, SCK3_MARK,
389
390 /* PTQ (mobule: LPC) */
391 LAD3_MARK, LAD2_MARK, LAD1_MARK, LAD0_MARK,
392 LFRAME_MARK, LRESET_MARK, LCLK_MARK,
393
394 /* PTR (mobule: GRA, IIC) */
395 DDC3_MARK, DDC2_MARK,
396 SDA8_MARK, SCL8_MARK, SDA2_MARK, SCL2_MARK,
397 SDA1_MARK, SCL1_MARK, SDA0_MARK, SCL0_MARK,
398
399 /* PTS (mobule: GRA, IIC) */
400 DDC1_MARK, DDC0_MARK,
401 SDA9_MARK, SCL9_MARK, SDA5_MARK, SCL5_MARK,
402 SDA4_MARK, SCL4_MARK, SDA3_MARK, SCL3_MARK,
403
404 /* PTT (mobule: SYSTEM, PWMX) */
405 AUDSYNC_MARK, AUDCK_MARK,
406 AUDATA3_MARK, AUDATA2_MARK,
407 AUDATA1_MARK, AUDATA0_MARK,
408 PWX7_MARK, PWX6_MARK, PWX5_MARK, PWX4_MARK,
409
410 /* PTU (mobule: LBSC, DMAC) */
411 CS6_MARK, CS5_MARK, CS4_MARK, CS0_MARK,
412 RD_MARK, WE0_MARK, A25_MARK, A24_MARK,
413 DREQ0_MARK, DACK0_MARK,
414
415 /* PTV (mobule: LBSC, DMAC) */
416 A23_MARK, A22_MARK, A21_MARK, A20_MARK,
417 A19_MARK, A18_MARK, A17_MARK, A16_MARK,
418 TEND0_MARK, DREQ1_MARK, DACK1_MARK, TEND1_MARK,
419
420 /* PTW (mobule: LBSC) */
421 A15_MARK, A14_MARK, A13_MARK, A12_MARK,
422 A11_MARK, A10_MARK, A9_MARK, A8_MARK,
423
424 /* PTX (mobule: LBSC) */
425 A7_MARK, A6_MARK, A5_MARK, A4_MARK,
426 A3_MARK, A2_MARK, A1_MARK, A0_MARK,
427
428 /* PTY (mobule: LBSC) */
429 D7_MARK, D6_MARK, D5_MARK, D4_MARK,
430 D3_MARK, D2_MARK, D1_MARK, D0_MARK,
431 PINMUX_MARK_END,
432};
433
434static pinmux_enum_t pinmux_data[] = {
435 /* PTA GPIO */
436 PINMUX_DATA(PTA7_DATA, PTA7_IN, PTA7_OUT),
437 PINMUX_DATA(PTA6_DATA, PTA6_IN, PTA6_OUT),
438 PINMUX_DATA(PTA5_DATA, PTA5_IN, PTA5_OUT),
439 PINMUX_DATA(PTA4_DATA, PTA4_IN, PTA4_OUT),
440 PINMUX_DATA(PTA3_DATA, PTA3_IN, PTA3_OUT),
441 PINMUX_DATA(PTA2_DATA, PTA2_IN, PTA2_OUT),
442 PINMUX_DATA(PTA1_DATA, PTA1_IN, PTA1_OUT),
443 PINMUX_DATA(PTA0_DATA, PTA0_IN, PTA0_OUT),
444
445 /* PTB GPIO */
446 PINMUX_DATA(PTB7_DATA, PTB7_IN, PTB7_OUT),
447 PINMUX_DATA(PTB6_DATA, PTB6_IN, PTB6_OUT),
448 PINMUX_DATA(PTB5_DATA, PTB5_IN, PTB5_OUT),
449 PINMUX_DATA(PTB4_DATA, PTB4_IN, PTB4_OUT),
450 PINMUX_DATA(PTB3_DATA, PTB3_IN, PTB3_OUT),
451 PINMUX_DATA(PTB2_DATA, PTB2_IN, PTB2_OUT),
452 PINMUX_DATA(PTB1_DATA, PTB1_IN, PTB1_OUT),
453 PINMUX_DATA(PTB0_DATA, PTB0_IN, PTB0_OUT),
454
455 /* PTC GPIO */
456 PINMUX_DATA(PTC7_DATA, PTC7_IN, PTC7_OUT),
457 PINMUX_DATA(PTC6_DATA, PTC6_IN, PTC6_OUT),
458 PINMUX_DATA(PTC5_DATA, PTC5_IN, PTC5_OUT),
459 PINMUX_DATA(PTC4_DATA, PTC4_IN, PTC4_OUT),
460 PINMUX_DATA(PTC3_DATA, PTC3_IN, PTC3_OUT),
461 PINMUX_DATA(PTC2_DATA, PTC2_IN, PTC2_OUT),
462 PINMUX_DATA(PTC1_DATA, PTC1_IN, PTC1_OUT),
463 PINMUX_DATA(PTC0_DATA, PTC0_IN, PTC0_OUT),
464
465 /* PTD GPIO */
466 PINMUX_DATA(PTD7_DATA, PTD7_IN, PTD7_OUT),
467 PINMUX_DATA(PTD6_DATA, PTD6_IN, PTD6_OUT),
468 PINMUX_DATA(PTD5_DATA, PTD5_IN, PTD5_OUT),
469 PINMUX_DATA(PTD4_DATA, PTD4_IN, PTD4_OUT),
470 PINMUX_DATA(PTD3_DATA, PTD3_IN, PTD3_OUT),
471 PINMUX_DATA(PTD2_DATA, PTD2_IN, PTD2_OUT),
472 PINMUX_DATA(PTD1_DATA, PTD1_IN, PTD1_OUT),
473 PINMUX_DATA(PTD0_DATA, PTD0_IN, PTD0_OUT),
474
475 /* PTE GPIO */
476 PINMUX_DATA(PTE5_DATA, PTE5_IN, PTE5_OUT),
477 PINMUX_DATA(PTE4_DATA, PTE4_IN, PTE4_OUT),
478 PINMUX_DATA(PTE3_DATA, PTE3_IN, PTE3_OUT),
479 PINMUX_DATA(PTE2_DATA, PTE2_IN, PTE2_OUT),
480 PINMUX_DATA(PTE1_DATA, PTE1_IN, PTE1_OUT),
481 PINMUX_DATA(PTE0_DATA, PTE0_IN, PTE0_OUT),
482
483 /* PTF GPIO */
484 PINMUX_DATA(PTF7_DATA, PTF7_IN, PTF7_OUT),
485 PINMUX_DATA(PTF6_DATA, PTF6_IN, PTF6_OUT),
486 PINMUX_DATA(PTF5_DATA, PTF5_IN, PTF5_OUT),
487 PINMUX_DATA(PTF4_DATA, PTF4_IN, PTF4_OUT),
488 PINMUX_DATA(PTF3_DATA, PTF3_IN, PTF3_OUT),
489 PINMUX_DATA(PTF2_DATA, PTF2_IN, PTF2_OUT),
490 PINMUX_DATA(PTF1_DATA, PTF1_IN, PTF1_OUT),
491 PINMUX_DATA(PTF0_DATA, PTF0_IN, PTF0_OUT),
492
493 /* PTG GPIO */
494 PINMUX_DATA(PTG7_DATA, PTG7_IN, PTG7_OUT),
495 PINMUX_DATA(PTG6_DATA, PTG6_IN, PTG6_OUT),
496 PINMUX_DATA(PTG5_DATA, PTG5_IN, PTG5_OUT),
497 PINMUX_DATA(PTG4_DATA, PTG4_IN, PTG4_OUT),
498 PINMUX_DATA(PTG3_DATA, PTG3_IN, PTG3_OUT),
499 PINMUX_DATA(PTG2_DATA, PTG2_IN, PTG2_OUT),
500 PINMUX_DATA(PTG1_DATA, PTG1_IN, PTG1_OUT),
501 PINMUX_DATA(PTG0_DATA, PTG0_IN, PTG0_OUT),
502
503 /* PTH GPIO */
504 PINMUX_DATA(PTH7_DATA, PTH7_IN, PTH7_OUT),
505 PINMUX_DATA(PTH6_DATA, PTH6_IN, PTH6_OUT),
506 PINMUX_DATA(PTH5_DATA, PTH5_IN, PTH5_OUT),
507 PINMUX_DATA(PTH4_DATA, PTH4_IN, PTH4_OUT),
508 PINMUX_DATA(PTH3_DATA, PTH3_IN, PTH3_OUT),
509 PINMUX_DATA(PTH2_DATA, PTH2_IN, PTH2_OUT),
510 PINMUX_DATA(PTH1_DATA, PTH1_IN, PTH1_OUT),
511 PINMUX_DATA(PTH0_DATA, PTH0_IN, PTH0_OUT),
512
513 /* PTI GPIO */
514 PINMUX_DATA(PTI7_DATA, PTI7_IN, PTI7_OUT),
515 PINMUX_DATA(PTI6_DATA, PTI6_IN, PTI6_OUT),
516 PINMUX_DATA(PTI5_DATA, PTI5_IN, PTI5_OUT),
517 PINMUX_DATA(PTI4_DATA, PTI4_IN, PTI4_OUT),
518 PINMUX_DATA(PTI3_DATA, PTI3_IN, PTI3_OUT),
519 PINMUX_DATA(PTI2_DATA, PTI2_IN, PTI2_OUT),
520 PINMUX_DATA(PTI1_DATA, PTI1_IN, PTI1_OUT),
521 PINMUX_DATA(PTI0_DATA, PTI0_IN, PTI0_OUT),
522
523 /* PTJ GPIO */
524 PINMUX_DATA(PTJ7_DATA, PTJ7_IN, PTJ7_OUT),
525 PINMUX_DATA(PTJ6_DATA, PTJ6_IN, PTJ6_OUT),
526 PINMUX_DATA(PTJ5_DATA, PTJ5_IN, PTJ5_OUT),
527 PINMUX_DATA(PTJ4_DATA, PTJ4_IN, PTJ4_OUT),
528 PINMUX_DATA(PTJ3_DATA, PTJ3_IN, PTJ3_OUT),
529 PINMUX_DATA(PTJ2_DATA, PTJ2_IN, PTJ2_OUT),
530 PINMUX_DATA(PTJ1_DATA, PTJ1_IN, PTJ1_OUT),
531 PINMUX_DATA(PTJ0_DATA, PTJ0_IN, PTJ0_OUT),
532
533 /* PTK GPIO */
534 PINMUX_DATA(PTK7_DATA, PTK7_IN, PTK7_OUT),
535 PINMUX_DATA(PTK6_DATA, PTK6_IN, PTK6_OUT),
536 PINMUX_DATA(PTK5_DATA, PTK5_IN, PTK5_OUT),
537 PINMUX_DATA(PTK4_DATA, PTK4_IN, PTK4_OUT),
538 PINMUX_DATA(PTK3_DATA, PTK3_IN, PTK3_OUT),
539 PINMUX_DATA(PTK2_DATA, PTK2_IN, PTK2_OUT),
540 PINMUX_DATA(PTK1_DATA, PTK1_IN, PTK1_OUT),
541 PINMUX_DATA(PTK0_DATA, PTK0_IN, PTK0_OUT),
542
543 /* PTL GPIO */
544 PINMUX_DATA(PTL7_DATA, PTL7_IN, PTL7_OUT),
545 PINMUX_DATA(PTL6_DATA, PTL6_IN, PTL6_OUT),
546 PINMUX_DATA(PTL5_DATA, PTL5_IN, PTL5_OUT),
547 PINMUX_DATA(PTL4_DATA, PTL4_IN, PTL4_OUT),
548 PINMUX_DATA(PTL3_DATA, PTL3_IN, PTL3_OUT),
549 PINMUX_DATA(PTL2_DATA, PTL2_IN, PTL2_OUT),
550 PINMUX_DATA(PTL1_DATA, PTL1_IN, PTL1_OUT),
551 PINMUX_DATA(PTL0_DATA, PTL0_IN, PTL0_OUT),
552
553 /* PTM GPIO */
554 PINMUX_DATA(PTM6_DATA, PTM6_IN, PTM6_OUT),
555 PINMUX_DATA(PTM5_DATA, PTM5_IN, PTM5_OUT),
556 PINMUX_DATA(PTM4_DATA, PTM4_IN, PTM4_OUT),
557 PINMUX_DATA(PTM3_DATA, PTM3_IN, PTM3_OUT),
558 PINMUX_DATA(PTM2_DATA, PTM2_IN, PTM2_OUT),
559 PINMUX_DATA(PTM1_DATA, PTM1_IN, PTM1_OUT),
560 PINMUX_DATA(PTM0_DATA, PTM0_IN, PTM0_OUT),
561
562 /* PTN GPIO */
563 PINMUX_DATA(PTN7_DATA, PTN7_IN, PTN7_OUT),
564 PINMUX_DATA(PTN6_DATA, PTN6_IN, PTN6_OUT),
565 PINMUX_DATA(PTN5_DATA, PTN5_IN, PTN5_OUT),
566 PINMUX_DATA(PTN4_DATA, PTN4_IN, PTN4_OUT),
567 PINMUX_DATA(PTN3_DATA, PTN3_IN, PTN3_OUT),
568 PINMUX_DATA(PTN2_DATA, PTN2_IN, PTN2_OUT),
569 PINMUX_DATA(PTN1_DATA, PTN1_IN, PTN1_OUT),
570 PINMUX_DATA(PTN0_DATA, PTN0_IN, PTN0_OUT),
571
572 /* PTO GPIO */
573 PINMUX_DATA(PTO7_DATA, PTO7_IN, PTO7_OUT),
574 PINMUX_DATA(PTO6_DATA, PTO6_IN, PTO6_OUT),
575 PINMUX_DATA(PTO5_DATA, PTO5_IN, PTO5_OUT),
576 PINMUX_DATA(PTO4_DATA, PTO4_IN, PTO4_OUT),
577 PINMUX_DATA(PTO3_DATA, PTO3_IN, PTO3_OUT),
578 PINMUX_DATA(PTO2_DATA, PTO2_IN, PTO2_OUT),
579 PINMUX_DATA(PTO1_DATA, PTO1_IN, PTO1_OUT),
580 PINMUX_DATA(PTO0_DATA, PTO0_IN, PTO0_OUT),
581
582 /* PTQ GPIO */
583 PINMUX_DATA(PTQ6_DATA, PTQ6_IN, PTQ6_OUT),
584 PINMUX_DATA(PTQ5_DATA, PTQ5_IN, PTQ5_OUT),
585 PINMUX_DATA(PTQ4_DATA, PTQ4_IN, PTQ4_OUT),
586 PINMUX_DATA(PTQ3_DATA, PTQ3_IN, PTQ3_OUT),
587 PINMUX_DATA(PTQ2_DATA, PTQ2_IN, PTQ2_OUT),
588 PINMUX_DATA(PTQ1_DATA, PTQ1_IN, PTQ1_OUT),
589 PINMUX_DATA(PTQ0_DATA, PTQ0_IN, PTQ0_OUT),
590
591 /* PTR GPIO */
592 PINMUX_DATA(PTR7_DATA, PTR7_IN, PTR7_OUT),
593 PINMUX_DATA(PTR6_DATA, PTR6_IN, PTR6_OUT),
594 PINMUX_DATA(PTR5_DATA, PTR5_IN, PTR5_OUT),
595 PINMUX_DATA(PTR4_DATA, PTR4_IN, PTR4_OUT),
596 PINMUX_DATA(PTR3_DATA, PTR3_IN, PTR3_OUT),
597 PINMUX_DATA(PTR2_DATA, PTR2_IN, PTR2_OUT),
598 PINMUX_DATA(PTR1_DATA, PTR1_IN, PTR1_OUT),
599 PINMUX_DATA(PTR0_DATA, PTR0_IN, PTR0_OUT),
600
601 /* PTS GPIO */
602 PINMUX_DATA(PTS7_DATA, PTS7_IN, PTS7_OUT),
603 PINMUX_DATA(PTS6_DATA, PTS6_IN, PTS6_OUT),
604 PINMUX_DATA(PTS5_DATA, PTS5_IN, PTS5_OUT),
605 PINMUX_DATA(PTS4_DATA, PTS4_IN, PTS4_OUT),
606 PINMUX_DATA(PTS3_DATA, PTS3_IN, PTS3_OUT),
607 PINMUX_DATA(PTS2_DATA, PTS2_IN, PTS2_OUT),
608 PINMUX_DATA(PTS1_DATA, PTS1_IN, PTS1_OUT),
609 PINMUX_DATA(PTS0_DATA, PTS0_IN, PTS0_OUT),
610
611 /* PTT GPIO */
612 PINMUX_DATA(PTT5_DATA, PTT5_IN, PTT5_OUT),
613 PINMUX_DATA(PTT4_DATA, PTT4_IN, PTT4_OUT),
614 PINMUX_DATA(PTT3_DATA, PTT3_IN, PTT3_OUT),
615 PINMUX_DATA(PTT2_DATA, PTT2_IN, PTT2_OUT),
616 PINMUX_DATA(PTT1_DATA, PTT1_IN, PTT1_OUT),
617 PINMUX_DATA(PTT0_DATA, PTT0_IN, PTT0_OUT),
618
619 /* PTU GPIO */
620 PINMUX_DATA(PTU7_DATA, PTU7_IN, PTU7_OUT),
621 PINMUX_DATA(PTU6_DATA, PTU6_IN, PTU6_OUT),
622 PINMUX_DATA(PTU5_DATA, PTU5_IN, PTU5_OUT),
623 PINMUX_DATA(PTU4_DATA, PTU4_IN, PTU4_OUT),
624 PINMUX_DATA(PTU3_DATA, PTU3_IN, PTU3_OUT),
625 PINMUX_DATA(PTU2_DATA, PTU2_IN, PTU2_OUT),
626 PINMUX_DATA(PTU1_DATA, PTU1_IN, PTU1_OUT),
627 PINMUX_DATA(PTU0_DATA, PTU0_IN, PTU0_OUT),
628
629 /* PTV GPIO */
630 PINMUX_DATA(PTV7_DATA, PTV7_IN, PTV7_OUT),
631 PINMUX_DATA(PTV6_DATA, PTV6_IN, PTV6_OUT),
632 PINMUX_DATA(PTV5_DATA, PTV5_IN, PTV5_OUT),
633 PINMUX_DATA(PTV4_DATA, PTV4_IN, PTV4_OUT),
634 PINMUX_DATA(PTV3_DATA, PTV3_IN, PTV3_OUT),
635 PINMUX_DATA(PTV2_DATA, PTV2_IN, PTV2_OUT),
636 PINMUX_DATA(PTV1_DATA, PTV1_IN, PTV1_OUT),
637 PINMUX_DATA(PTV0_DATA, PTV0_IN, PTV0_OUT),
638
639 /* PTW GPIO */
640 PINMUX_DATA(PTW7_DATA, PTW7_IN, PTW7_OUT),
641 PINMUX_DATA(PTW6_DATA, PTW6_IN, PTW6_OUT),
642 PINMUX_DATA(PTW5_DATA, PTW5_IN, PTW5_OUT),
643 PINMUX_DATA(PTW4_DATA, PTW4_IN, PTW4_OUT),
644 PINMUX_DATA(PTW3_DATA, PTW3_IN, PTW3_OUT),
645 PINMUX_DATA(PTW2_DATA, PTW2_IN, PTW2_OUT),
646 PINMUX_DATA(PTW1_DATA, PTW1_IN, PTW1_OUT),
647 PINMUX_DATA(PTW0_DATA, PTW0_IN, PTW0_OUT),
648
649 /* PTX GPIO */
650 PINMUX_DATA(PTX7_DATA, PTX7_IN, PTX7_OUT),
651 PINMUX_DATA(PTX6_DATA, PTX6_IN, PTX6_OUT),
652 PINMUX_DATA(PTX5_DATA, PTX5_IN, PTX5_OUT),
653 PINMUX_DATA(PTX4_DATA, PTX4_IN, PTX4_OUT),
654 PINMUX_DATA(PTX3_DATA, PTX3_IN, PTX3_OUT),
655 PINMUX_DATA(PTX2_DATA, PTX2_IN, PTX2_OUT),
656 PINMUX_DATA(PTX1_DATA, PTX1_IN, PTX1_OUT),
657 PINMUX_DATA(PTX0_DATA, PTX0_IN, PTX0_OUT),
658
659 /* PTY GPIO */
660 PINMUX_DATA(PTY7_DATA, PTY7_IN, PTY7_OUT),
661 PINMUX_DATA(PTY6_DATA, PTY6_IN, PTY6_OUT),
662 PINMUX_DATA(PTY5_DATA, PTY5_IN, PTY5_OUT),
663 PINMUX_DATA(PTY4_DATA, PTY4_IN, PTY4_OUT),
664 PINMUX_DATA(PTY3_DATA, PTY3_IN, PTY3_OUT),
665 PINMUX_DATA(PTY2_DATA, PTY2_IN, PTY2_OUT),
666 PINMUX_DATA(PTY1_DATA, PTY1_IN, PTY1_OUT),
667 PINMUX_DATA(PTY0_DATA, PTY0_IN, PTY0_OUT),
668
669 /* PTZ GPIO */
670 PINMUX_DATA(PTZ7_DATA, PTZ7_IN, PTZ7_OUT),
671 PINMUX_DATA(PTZ6_DATA, PTZ6_IN, PTZ6_OUT),
672 PINMUX_DATA(PTZ5_DATA, PTZ5_IN, PTZ5_OUT),
673 PINMUX_DATA(PTZ4_DATA, PTZ4_IN, PTZ4_OUT),
674 PINMUX_DATA(PTZ3_DATA, PTZ3_IN, PTZ3_OUT),
675 PINMUX_DATA(PTZ2_DATA, PTZ2_IN, PTZ2_OUT),
676 PINMUX_DATA(PTZ1_DATA, PTZ1_IN, PTZ1_OUT),
677 PINMUX_DATA(PTZ0_DATA, PTZ0_IN, PTZ0_OUT),
678
679 /* PTA FN */
680 PINMUX_DATA(BS_MARK, PS0_15_FN1, PTA7_FN),
681 PINMUX_DATA(LGPIO7_MARK, PS0_15_FN3, PTA7_FN),
682 PINMUX_DATA(RDWR_MARK, PS0_14_FN1, PTA6_FN),
683 PINMUX_DATA(LGPIO6_MARK, PS0_14_FN3, PTA6_FN),
684 PINMUX_DATA(WE1_MARK, PS0_13_FN1, PTA5_FN),
685 PINMUX_DATA(LGPIO5_MARK, PS0_13_FN3, PTA5_FN),
686 PINMUX_DATA(RDY_MARK, PS0_12_FN1, PTA4_FN),
687 PINMUX_DATA(LGPIO4_MARK, PS0_12_FN3, PTA4_FN),
688 PINMUX_DATA(LGPIO3_MARK, PTA3_FN),
689 PINMUX_DATA(LGPIO2_MARK, PTA2_FN),
690 PINMUX_DATA(LGPIO1_MARK, PTA1_FN),
691 PINMUX_DATA(LGPIO0_MARK, PTA0_FN),
692
693 /* PTB FN */
694 PINMUX_DATA(D15_MARK, PS0_7_FN1, PTB7_FN),
695 PINMUX_DATA(ET0_MDC_MARK, PS0_7_FN2, PTB7_FN),
696 PINMUX_DATA(D14_MARK, PS0_6_FN1, PTB6_FN),
697 PINMUX_DATA(ET0_MDIO_MARK, PS0_6_FN2, PTB6_FN),
698 PINMUX_DATA(D13_MARK, PS0_5_FN1, PTB5_FN),
699 PINMUX_DATA(ET1_MDC_MARK, PS0_5_FN2, PTB5_FN),
700 PINMUX_DATA(D12_MARK, PS0_4_FN1, PTB4_FN),
701 PINMUX_DATA(ET1_MDIO_MARK, PS0_4_FN2, PTB4_FN),
702 PINMUX_DATA(D11_MARK, PS0_3_FN1, PTB3_FN),
703 PINMUX_DATA(SIM_D_MARK, PS0_3_FN2, PTB3_FN),
704 PINMUX_DATA(D10_MARK, PS0_2_FN1, PTB2_FN),
705 PINMUX_DATA(SIM_CLK_MARK, PS0_2_FN2, PTB2_FN),
706 PINMUX_DATA(D9_MARK, PS0_1_FN1, PTB1_FN),
707 PINMUX_DATA(SIM_RST_MARK, PS0_1_FN2, PTB1_FN),
708 PINMUX_DATA(D8_MARK, PTB0_FN),
709
710 /* PTC FN */
711 PINMUX_DATA(SD_WP_MARK, PTC7_FN),
712 PINMUX_DATA(SD_CD_MARK, PTC6_FN),
713 PINMUX_DATA(SD_CLK_MARK, PTC5_FN),
714 PINMUX_DATA(SD_CMD_MARK, PTC4_FN),
715 PINMUX_DATA(SD_D3_MARK, PTC3_FN),
716 PINMUX_DATA(SD_D2_MARK, PTC2_FN),
717 PINMUX_DATA(SD_D1_MARK, PTC1_FN),
718 PINMUX_DATA(SD_D0_MARK, PTC0_FN),
719
720 /* PTD FN */
721 PINMUX_DATA(IRQ7_MARK, PS1_7_FN1, PTD7_FN),
722 PINMUX_DATA(ADTRG1_MARK, PS1_7_FN3, PTD7_FN),
723 PINMUX_DATA(IRQ6_MARK, PS1_6_FN1, PTD6_FN),
724 PINMUX_DATA(ADTRG0_MARK, PS1_6_FN3, PTD6_FN),
725 PINMUX_DATA(IRQ5_MARK, PTD5_FN),
726 PINMUX_DATA(IRQ4_MARK, PTD4_FN),
727 PINMUX_DATA(IRQ3_MARK, PTD3_FN),
728 PINMUX_DATA(IRQ2_MARK, PTD2_FN),
729 PINMUX_DATA(IRQ1_MARK, PTD1_FN),
730 PINMUX_DATA(IRQ0_MARK, PTD0_FN),
731
732 /* PTE FN */
733 PINMUX_DATA(ET0_CRS_DV_MARK, PTE7_FN),
734 PINMUX_DATA(ET0_TXD1_MARK, PTE6_FN),
735 PINMUX_DATA(ET0_TXD0_MARK, PTE5_FN),
736 PINMUX_DATA(ET0_TX_EN_MARK, PTE4_FN),
737 PINMUX_DATA(ET0_REF_CLK_MARK, PTE3_FN),
738 PINMUX_DATA(ET0_RXD1_MARK, PTE2_FN),
739 PINMUX_DATA(ET0_RXD0_MARK, PTE1_FN),
740 PINMUX_DATA(ET0_RX_ER_MARK, PTE0_FN),
741
742 /* PTF FN */
743 PINMUX_DATA(ET1_CRS_DV_MARK, PTF7_FN),
744 PINMUX_DATA(ET1_TXD1_MARK, PTF6_FN),
745 PINMUX_DATA(ET1_TXD0_MARK, PTF5_FN),
746 PINMUX_DATA(ET1_TX_EN_MARK, PTF4_FN),
747 PINMUX_DATA(ET1_REF_CLK_MARK, PTF3_FN),
748 PINMUX_DATA(ET1_RXD1_MARK, PTF2_FN),
749 PINMUX_DATA(ET1_RXD0_MARK, PTF1_FN),
750 PINMUX_DATA(ET1_RX_ER_MARK, PTF0_FN),
751
752 /* PTG FN */
753 PINMUX_DATA(PWX0_MARK, PTG7_FN),
754 PINMUX_DATA(PWX1_MARK, PTG6_FN),
755 PINMUX_DATA(STATUS0_MARK, PS2_13_FN1, PTG5_FN),
756 PINMUX_DATA(PWX2_MARK, PS2_13_FN3, PTG5_FN),
757 PINMUX_DATA(STATUS1_MARK, PS2_12_FN1, PTG4_FN),
758 PINMUX_DATA(PWX3_MARK, PS2_12_FN3, PTG4_FN),
759 PINMUX_DATA(SERIRQ_MARK, PTG3_FN),
760 PINMUX_DATA(CLKRUN_MARK, PTG2_FN),
761 PINMUX_DATA(LPCPD_MARK, PTG1_FN),
762 PINMUX_DATA(LDRQ_MARK, PTG0_FN),
763
764 /* PTH FN */
765 PINMUX_DATA(SP1_MOSI_MARK, PTH7_FN),
766 PINMUX_DATA(SP1_MISO_MARK, PTH6_FN),
767 PINMUX_DATA(SP1_SCK_MARK, PTH5_FN),
768 PINMUX_DATA(SP1_SCK_FB_MARK, PTH4_FN),
769 PINMUX_DATA(SP1_SS0_MARK, PTH3_FN),
770 PINMUX_DATA(TCLK_MARK, PTH2_FN),
771 PINMUX_DATA(RXD4_MARK, PS2_1_FN1, PTH1_FN),
772 PINMUX_DATA(SP1_SS1_MARK, PS2_1_FN2, PTH1_FN),
773 PINMUX_DATA(TXD4_MARK, PS2_0_FN1, PTH0_FN),
774 PINMUX_DATA(SP0_SS1_MARK, PS2_0_FN2, PTH0_FN),
775
776 /* PTI FN */
777 PINMUX_DATA(IRQ15_MARK, PTI7_FN),
778 PINMUX_DATA(IRQ14_MARK, PTI6_FN),
779 PINMUX_DATA(IRQ13_MARK, PTI5_FN),
780 PINMUX_DATA(IRQ12_MARK, PTI4_FN),
781 PINMUX_DATA(IRQ11_MARK, PTI3_FN),
782 PINMUX_DATA(IRQ10_MARK, PTI2_FN),
783 PINMUX_DATA(IRQ9_MARK, PTI1_FN),
784 PINMUX_DATA(IRQ8_MARK, PTI0_FN),
785
786 /* PTJ FN */
787 PINMUX_DATA(RXD3_MARK, PTJ7_FN),
788 PINMUX_DATA(TXD3_MARK, PTJ6_FN),
789 PINMUX_DATA(RXD2_MARK, PTJ5_FN),
790 PINMUX_DATA(TXD2_MARK, PTJ4_FN),
791 PINMUX_DATA(COM1_TXD_MARK, PTJ3_FN),
792 PINMUX_DATA(COM1_RXD_MARK, PTJ2_FN),
793 PINMUX_DATA(COM1_RTS_MARK, PTJ1_FN),
794 PINMUX_DATA(COM1_CTS_MARK, PTJ0_FN),
795
796 /* PTK FN */
797 PINMUX_DATA(COM2_TXD_MARK, PTK7_FN),
798 PINMUX_DATA(COM2_RXD_MARK, PTK6_FN),
799 PINMUX_DATA(COM2_RTS_MARK, PTK5_FN),
800 PINMUX_DATA(COM2_CTS_MARK, PTK4_FN),
801 PINMUX_DATA(COM2_DTR_MARK, PTK3_FN),
802 PINMUX_DATA(COM2_DSR_MARK, PTK2_FN),
803 PINMUX_DATA(COM2_DCD_MARK, PTK1_FN),
804 PINMUX_DATA(COM2_RI_MARK, PTK0_FN),
805
806 /* PTL FN */
807 PINMUX_DATA(RAC_TXD_MARK, PTL7_FN),
808 PINMUX_DATA(RAC_RXD_MARK, PTL6_FN),
809 PINMUX_DATA(RAC_RTS_MARK, PTL5_FN),
810 PINMUX_DATA(RAC_CTS_MARK, PTL4_FN),
811 PINMUX_DATA(RAC_DTR_MARK, PTL3_FN),
812 PINMUX_DATA(RAC_DSR_MARK, PTL2_FN),
813 PINMUX_DATA(RAC_DCD_MARK, PTL1_FN),
814 PINMUX_DATA(RAC_RI_MARK, PTL0_FN),
815
816 /* PTM FN */
817 PINMUX_DATA(WP_MARK, PTM6_FN),
818 PINMUX_DATA(FMS0_MARK, PTM5_FN),
819 PINMUX_DATA(FMS1_MARK, PTM4_FN),
820 PINMUX_DATA(SDA6_MARK, PTM3_FN),
821 PINMUX_DATA(SCL6_MARK, PTM2_FN),
822 PINMUX_DATA(SDA7_MARK, PTM1_FN),
823 PINMUX_DATA(SCL7_MARK, PTM0_FN),
824
825 /* PTN FN */
826 PINMUX_DATA(SCK2_MARK, PS4_15_FN1, PTN7_FN),
827 PINMUX_DATA(EVENT7_MARK, PS4_15_FN2, PTN7_FN),
828 PINMUX_DATA(RTS4_MARK, PS4_14_FN1, PTN6_FN),
829 PINMUX_DATA(EVENT6_MARK, PS4_14_FN2, PTN6_FN),
830 PINMUX_DATA(RTS3_MARK, PS4_13_FN1, PTN5_FN),
831 PINMUX_DATA(EVENT5_MARK, PS4_13_FN2, PTN5_FN),
832 PINMUX_DATA(RTS2_MARK, PS4_12_FN1, PTN4_FN),
833 PINMUX_DATA(EVENT4_MARK, PS4_12_FN2, PTN4_FN),
834 PINMUX_DATA(CTS4_MARK, PS4_11_FN1, PTN3_FN),
835 PINMUX_DATA(EVENT3_MARK, PS4_11_FN2, PTN3_FN),
836 PINMUX_DATA(CTS3_MARK, PS4_10_FN1, PTN2_FN),
837 PINMUX_DATA(EVENT2_MARK, PS4_10_FN2, PTN2_FN),
838 PINMUX_DATA(CTS2_MARK, PS4_9_FN1, PTN1_FN),
839 PINMUX_DATA(EVENT1_MARK, PS4_9_FN2, PTN1_FN),
840 PINMUX_DATA(EVENT0_MARK, PTN0_FN),
841
842 /* PTO FN */
843 PINMUX_DATA(SGPIO0_CLK_MARK, PTO7_FN),
844 PINMUX_DATA(SGPIO0_LOAD_MARK, PTO6_FN),
845 PINMUX_DATA(SGPIO0_DI_MARK, PTO5_FN),
846 PINMUX_DATA(SGPIO0_DO_MARK, PTO4_FN),
847 PINMUX_DATA(SGPIO1_CLK_MARK, PTO3_FN),
848 PINMUX_DATA(SGPIO1_LOAD_MARK, PTO2_FN),
849 PINMUX_DATA(SGPIO1_DI_MARK, PTO1_FN),
850 PINMUX_DATA(SGPIO1_DO_MARK, PTO0_FN),
851
852 /* PTP FN */
853 PINMUX_DATA(JMCTCK_MARK, PTP6_FN),
854 PINMUX_DATA(JMCTMS_MARK, PTP5_FN),
855 PINMUX_DATA(JMCTDO_MARK, PTP4_FN),
856 PINMUX_DATA(JMCTDI_MARK, PTP3_FN),
857 PINMUX_DATA(JMCRST_MARK, PTP2_FN),
858 PINMUX_DATA(SCK4_MARK, PTP1_FN),
859 PINMUX_DATA(SCK3_MARK, PTP0_FN),
860
861 /* PTQ FN */
862 PINMUX_DATA(LAD3_MARK, PTQ6_FN),
863 PINMUX_DATA(LAD2_MARK, PTQ5_FN),
864 PINMUX_DATA(LAD1_MARK, PTQ4_FN),
865 PINMUX_DATA(LAD0_MARK, PTQ3_FN),
866 PINMUX_DATA(LFRAME_MARK, PTQ2_FN),
867 PINMUX_DATA(SCK4_MARK, PTQ1_FN),
868 PINMUX_DATA(SCK3_MARK, PTQ0_FN),
869
870 /* PTR FN */
871 PINMUX_DATA(SDA8_MARK, PTR7_FN), /* DDC3? */
872 PINMUX_DATA(SCL8_MARK, PTR6_FN), /* DDC2? */
873 PINMUX_DATA(SDA2_MARK, PTR5_FN),
874 PINMUX_DATA(SCL2_MARK, PTR4_FN),
875 PINMUX_DATA(SDA1_MARK, PTR3_FN),
876 PINMUX_DATA(SCL1_MARK, PTR2_FN),
877 PINMUX_DATA(SDA0_MARK, PTR1_FN),
878 PINMUX_DATA(SCL0_MARK, PTR0_FN),
879
880 /* PTS FN */
881 PINMUX_DATA(SDA9_MARK, PTS7_FN), /* DDC1? */
882 PINMUX_DATA(SCL9_MARK, PTS6_FN), /* DDC0? */
883 PINMUX_DATA(SDA5_MARK, PTS5_FN),
884 PINMUX_DATA(SCL5_MARK, PTS4_FN),
885 PINMUX_DATA(SDA4_MARK, PTS3_FN),
886 PINMUX_DATA(SCL4_MARK, PTS2_FN),
887 PINMUX_DATA(SDA3_MARK, PTS1_FN),
888 PINMUX_DATA(SCL3_MARK, PTS0_FN),
889
890 /* PTT FN */
891 PINMUX_DATA(AUDSYNC_MARK, PTS5_FN),
892 PINMUX_DATA(AUDCK_MARK, PTS4_FN),
893 PINMUX_DATA(AUDATA3_MARK, PS4_3_FN1, PTS3_FN),
894 PINMUX_DATA(PWX7_MARK, PS4_3_FN2, PTS3_FN),
895 PINMUX_DATA(AUDATA2_MARK, PS4_2_FN1, PTS2_FN),
896 PINMUX_DATA(PWX6_MARK, PS4_2_FN2, PTS2_FN),
897 PINMUX_DATA(AUDATA1_MARK, PS4_1_FN1, PTS1_FN),
898 PINMUX_DATA(PWX5_MARK, PS4_1_FN2, PTS1_FN),
899 PINMUX_DATA(AUDATA0_MARK, PS4_0_FN1, PTS0_FN),
900 PINMUX_DATA(PWX4_MARK, PS4_0_FN2, PTS0_FN),
901
902 /* PTU FN */
903 PINMUX_DATA(CS6_MARK, PTU7_FN),
904 PINMUX_DATA(CS5_MARK, PTU6_FN),
905 PINMUX_DATA(CS4_MARK, PTU5_FN),
906 PINMUX_DATA(CS0_MARK, PTU4_FN),
907 PINMUX_DATA(RD_MARK, PTU3_FN),
908 PINMUX_DATA(WE0_MARK, PTU2_FN),
909 PINMUX_DATA(A25_MARK, PS5_9_FN1, PTU1_FN),
910 PINMUX_DATA(DREQ0_MARK, PS5_9_FN2, PTU1_FN),
911 PINMUX_DATA(A24_MARK, PS5_8_FN1, PTU0_FN),
912 PINMUX_DATA(DACK0_MARK, PS5_8_FN2, PTU0_FN),
913
914 /* PTV FN */
915 PINMUX_DATA(A23_MARK, PS5_7_FN1, PTV7_FN),
916 PINMUX_DATA(TEND0_MARK, PS5_7_FN2, PTV7_FN),
917 PINMUX_DATA(A22_MARK, PS5_6_FN1, PTV6_FN),
918 PINMUX_DATA(DREQ1_MARK, PS5_6_FN2, PTV6_FN),
919 PINMUX_DATA(A21_MARK, PS5_5_FN1, PTV5_FN),
920 PINMUX_DATA(DACK1_MARK, PS5_5_FN2, PTV5_FN),
921 PINMUX_DATA(A20_MARK, PS5_4_FN1, PTV4_FN),
922 PINMUX_DATA(TEND1_MARK, PS5_4_FN2, PTV4_FN),
923 PINMUX_DATA(A19_MARK, PTV3_FN),
924 PINMUX_DATA(A18_MARK, PTV2_FN),
925 PINMUX_DATA(A17_MARK, PTV1_FN),
926 PINMUX_DATA(A16_MARK, PTV0_FN),
927
928 /* PTW FN */
929 PINMUX_DATA(A15_MARK, PTW7_FN),
930 PINMUX_DATA(A14_MARK, PTW6_FN),
931 PINMUX_DATA(A13_MARK, PTW5_FN),
932 PINMUX_DATA(A12_MARK, PTW4_FN),
933 PINMUX_DATA(A11_MARK, PTW3_FN),
934 PINMUX_DATA(A10_MARK, PTW2_FN),
935 PINMUX_DATA(A9_MARK, PTW1_FN),
936 PINMUX_DATA(A8_MARK, PTW0_FN),
937
938 /* PTX FN */
939 PINMUX_DATA(A7_MARK, PTX7_FN),
940 PINMUX_DATA(A6_MARK, PTX6_FN),
941 PINMUX_DATA(A5_MARK, PTX5_FN),
942 PINMUX_DATA(A4_MARK, PTX4_FN),
943 PINMUX_DATA(A3_MARK, PTX3_FN),
944 PINMUX_DATA(A2_MARK, PTX2_FN),
945 PINMUX_DATA(A1_MARK, PTX1_FN),
946 PINMUX_DATA(A0_MARK, PTX0_FN),
947
948 /* PTY FN */
949 PINMUX_DATA(D7_MARK, PTY7_FN),
950 PINMUX_DATA(D6_MARK, PTY6_FN),
951 PINMUX_DATA(D5_MARK, PTY5_FN),
952 PINMUX_DATA(D4_MARK, PTY4_FN),
953 PINMUX_DATA(D3_MARK, PTY3_FN),
954 PINMUX_DATA(D2_MARK, PTY2_FN),
955 PINMUX_DATA(D1_MARK, PTY1_FN),
956 PINMUX_DATA(D0_MARK, PTY0_FN),
957};
958
959static struct pinmux_gpio pinmux_gpios[] = {
960 /* PTA */
961 PINMUX_GPIO(GPIO_PTA7, PTA7_DATA),
962 PINMUX_GPIO(GPIO_PTA6, PTA6_DATA),
963 PINMUX_GPIO(GPIO_PTA5, PTA5_DATA),
964 PINMUX_GPIO(GPIO_PTA4, PTA4_DATA),
965 PINMUX_GPIO(GPIO_PTA3, PTA3_DATA),
966 PINMUX_GPIO(GPIO_PTA2, PTA2_DATA),
967 PINMUX_GPIO(GPIO_PTA1, PTA1_DATA),
968 PINMUX_GPIO(GPIO_PTA0, PTA0_DATA),
969
970 /* PTB */
971 PINMUX_GPIO(GPIO_PTB7, PTB7_DATA),
972 PINMUX_GPIO(GPIO_PTB6, PTB6_DATA),
973 PINMUX_GPIO(GPIO_PTB5, PTB5_DATA),
974 PINMUX_GPIO(GPIO_PTB4, PTB4_DATA),
975 PINMUX_GPIO(GPIO_PTB3, PTB3_DATA),
976 PINMUX_GPIO(GPIO_PTB2, PTB2_DATA),
977 PINMUX_GPIO(GPIO_PTB1, PTB1_DATA),
978 PINMUX_GPIO(GPIO_PTB0, PTB0_DATA),
979
980 /* PTC */
981 PINMUX_GPIO(GPIO_PTC7, PTC7_DATA),
982 PINMUX_GPIO(GPIO_PTC6, PTC6_DATA),
983 PINMUX_GPIO(GPIO_PTC5, PTC5_DATA),
984 PINMUX_GPIO(GPIO_PTC4, PTC4_DATA),
985 PINMUX_GPIO(GPIO_PTC3, PTC3_DATA),
986 PINMUX_GPIO(GPIO_PTC2, PTC2_DATA),
987 PINMUX_GPIO(GPIO_PTC1, PTC1_DATA),
988 PINMUX_GPIO(GPIO_PTC0, PTC0_DATA),
989
990 /* PTD */
991 PINMUX_GPIO(GPIO_PTD7, PTD7_DATA),
992 PINMUX_GPIO(GPIO_PTD6, PTD6_DATA),
993 PINMUX_GPIO(GPIO_PTD5, PTD5_DATA),
994 PINMUX_GPIO(GPIO_PTD4, PTD4_DATA),
995 PINMUX_GPIO(GPIO_PTD3, PTD3_DATA),
996 PINMUX_GPIO(GPIO_PTD2, PTD2_DATA),
997 PINMUX_GPIO(GPIO_PTD1, PTD1_DATA),
998 PINMUX_GPIO(GPIO_PTD0, PTD0_DATA),
999
1000 /* PTE */
1001 PINMUX_GPIO(GPIO_PTE7, PTE7_DATA),
1002 PINMUX_GPIO(GPIO_PTE6, PTE6_DATA),
1003 PINMUX_GPIO(GPIO_PTE5, PTE5_DATA),
1004 PINMUX_GPIO(GPIO_PTE4, PTE4_DATA),
1005 PINMUX_GPIO(GPIO_PTE3, PTE3_DATA),
1006 PINMUX_GPIO(GPIO_PTE2, PTE2_DATA),
1007 PINMUX_GPIO(GPIO_PTE1, PTE1_DATA),
1008 PINMUX_GPIO(GPIO_PTE0, PTE0_DATA),
1009
1010 /* PTF */
1011 PINMUX_GPIO(GPIO_PTF7, PTF7_DATA),
1012 PINMUX_GPIO(GPIO_PTF6, PTF6_DATA),
1013 PINMUX_GPIO(GPIO_PTF5, PTF5_DATA),
1014 PINMUX_GPIO(GPIO_PTF4, PTF4_DATA),
1015 PINMUX_GPIO(GPIO_PTF3, PTF3_DATA),
1016 PINMUX_GPIO(GPIO_PTF2, PTF2_DATA),
1017 PINMUX_GPIO(GPIO_PTF1, PTF1_DATA),
1018 PINMUX_GPIO(GPIO_PTF0, PTF0_DATA),
1019
1020 /* PTG */
1021 PINMUX_GPIO(GPIO_PTG7, PTG7_DATA),
1022 PINMUX_GPIO(GPIO_PTG6, PTG6_DATA),
1023 PINMUX_GPIO(GPIO_PTG5, PTG5_DATA),
1024 PINMUX_GPIO(GPIO_PTG4, PTG4_DATA),
1025 PINMUX_GPIO(GPIO_PTG3, PTG3_DATA),
1026 PINMUX_GPIO(GPIO_PTG2, PTG2_DATA),
1027 PINMUX_GPIO(GPIO_PTG1, PTG1_DATA),
1028 PINMUX_GPIO(GPIO_PTG0, PTG0_DATA),
1029
1030 /* PTH */
1031 PINMUX_GPIO(GPIO_PTH7, PTH7_DATA),
1032 PINMUX_GPIO(GPIO_PTH6, PTH6_DATA),
1033 PINMUX_GPIO(GPIO_PTH5, PTH5_DATA),
1034 PINMUX_GPIO(GPIO_PTH4, PTH4_DATA),
1035 PINMUX_GPIO(GPIO_PTH3, PTH3_DATA),
1036 PINMUX_GPIO(GPIO_PTH2, PTH2_DATA),
1037 PINMUX_GPIO(GPIO_PTH1, PTH1_DATA),
1038 PINMUX_GPIO(GPIO_PTH0, PTH0_DATA),
1039
1040 /* PTI */
1041 PINMUX_GPIO(GPIO_PTI7, PTI7_DATA),
1042 PINMUX_GPIO(GPIO_PTI6, PTI6_DATA),
1043 PINMUX_GPIO(GPIO_PTI5, PTI5_DATA),
1044 PINMUX_GPIO(GPIO_PTI4, PTI4_DATA),
1045 PINMUX_GPIO(GPIO_PTI3, PTI3_DATA),
1046 PINMUX_GPIO(GPIO_PTI2, PTI2_DATA),
1047 PINMUX_GPIO(GPIO_PTI1, PTI1_DATA),
1048 PINMUX_GPIO(GPIO_PTI0, PTI0_DATA),
1049
1050 /* PTJ */
1051 PINMUX_GPIO(GPIO_PTJ7, PTJ7_DATA),
1052 PINMUX_GPIO(GPIO_PTJ6, PTJ6_DATA),
1053 PINMUX_GPIO(GPIO_PTJ5, PTJ5_DATA),
1054 PINMUX_GPIO(GPIO_PTJ4, PTJ4_DATA),
1055 PINMUX_GPIO(GPIO_PTJ3, PTJ3_DATA),
1056 PINMUX_GPIO(GPIO_PTJ2, PTJ2_DATA),
1057 PINMUX_GPIO(GPIO_PTJ1, PTJ1_DATA),
1058 PINMUX_GPIO(GPIO_PTJ0, PTJ0_DATA),
1059
1060 /* PTK */
1061 PINMUX_GPIO(GPIO_PTK7, PTK7_DATA),
1062 PINMUX_GPIO(GPIO_PTK6, PTK6_DATA),
1063 PINMUX_GPIO(GPIO_PTK5, PTK5_DATA),
1064 PINMUX_GPIO(GPIO_PTK4, PTK4_DATA),
1065 PINMUX_GPIO(GPIO_PTK3, PTK3_DATA),
1066 PINMUX_GPIO(GPIO_PTK2, PTK2_DATA),
1067 PINMUX_GPIO(GPIO_PTK1, PTK1_DATA),
1068 PINMUX_GPIO(GPIO_PTK0, PTK0_DATA),
1069
1070 /* PTL */
1071 PINMUX_GPIO(GPIO_PTL7, PTL7_DATA),
1072 PINMUX_GPIO(GPIO_PTL6, PTL6_DATA),
1073 PINMUX_GPIO(GPIO_PTL5, PTL5_DATA),
1074 PINMUX_GPIO(GPIO_PTL4, PTL4_DATA),
1075 PINMUX_GPIO(GPIO_PTL3, PTL3_DATA),
1076 PINMUX_GPIO(GPIO_PTL2, PTL2_DATA),
1077 PINMUX_GPIO(GPIO_PTL1, PTL1_DATA),
1078 PINMUX_GPIO(GPIO_PTL0, PTL0_DATA),
1079
1080 /* PTM */
1081 PINMUX_GPIO(GPIO_PTM6, PTM6_DATA),
1082 PINMUX_GPIO(GPIO_PTM5, PTM5_DATA),
1083 PINMUX_GPIO(GPIO_PTM4, PTM4_DATA),
1084 PINMUX_GPIO(GPIO_PTM3, PTM3_DATA),
1085 PINMUX_GPIO(GPIO_PTM2, PTM2_DATA),
1086 PINMUX_GPIO(GPIO_PTM1, PTM1_DATA),
1087 PINMUX_GPIO(GPIO_PTM0, PTM0_DATA),
1088
1089 /* PTN */
1090 PINMUX_GPIO(GPIO_PTN7, PTN7_DATA),
1091 PINMUX_GPIO(GPIO_PTN6, PTN6_DATA),
1092 PINMUX_GPIO(GPIO_PTN5, PTN5_DATA),
1093 PINMUX_GPIO(GPIO_PTN4, PTN4_DATA),
1094 PINMUX_GPIO(GPIO_PTN3, PTN3_DATA),
1095 PINMUX_GPIO(GPIO_PTN2, PTN2_DATA),
1096 PINMUX_GPIO(GPIO_PTN1, PTN1_DATA),
1097 PINMUX_GPIO(GPIO_PTN0, PTN0_DATA),
1098
1099 /* PTO */
1100 PINMUX_GPIO(GPIO_PTO7, PTO7_DATA),
1101 PINMUX_GPIO(GPIO_PTO6, PTO6_DATA),
1102 PINMUX_GPIO(GPIO_PTO5, PTO5_DATA),
1103 PINMUX_GPIO(GPIO_PTO4, PTO4_DATA),
1104 PINMUX_GPIO(GPIO_PTO3, PTO3_DATA),
1105 PINMUX_GPIO(GPIO_PTO2, PTO2_DATA),
1106 PINMUX_GPIO(GPIO_PTO1, PTO1_DATA),
1107 PINMUX_GPIO(GPIO_PTO0, PTO0_DATA),
1108
1109 /* PTP */
1110 PINMUX_GPIO(GPIO_PTP6, PTP6_DATA),
1111 PINMUX_GPIO(GPIO_PTP5, PTP5_DATA),
1112 PINMUX_GPIO(GPIO_PTP4, PTP4_DATA),
1113 PINMUX_GPIO(GPIO_PTP3, PTP3_DATA),
1114 PINMUX_GPIO(GPIO_PTP2, PTP2_DATA),
1115 PINMUX_GPIO(GPIO_PTP1, PTP1_DATA),
1116 PINMUX_GPIO(GPIO_PTP0, PTP0_DATA),
1117
1118 /* PTQ */
1119 PINMUX_GPIO(GPIO_PTQ6, PTQ6_DATA),
1120 PINMUX_GPIO(GPIO_PTQ5, PTQ5_DATA),
1121 PINMUX_GPIO(GPIO_PTQ4, PTQ4_DATA),
1122 PINMUX_GPIO(GPIO_PTQ3, PTQ3_DATA),
1123 PINMUX_GPIO(GPIO_PTQ2, PTQ2_DATA),
1124 PINMUX_GPIO(GPIO_PTQ1, PTQ1_DATA),
1125 PINMUX_GPIO(GPIO_PTQ0, PTQ0_DATA),
1126
1127 /* PTR */
1128 PINMUX_GPIO(GPIO_PTR7, PTR7_DATA),
1129 PINMUX_GPIO(GPIO_PTR6, PTR6_DATA),
1130 PINMUX_GPIO(GPIO_PTR5, PTR5_DATA),
1131 PINMUX_GPIO(GPIO_PTR4, PTR4_DATA),
1132 PINMUX_GPIO(GPIO_PTR3, PTR3_DATA),
1133 PINMUX_GPIO(GPIO_PTR2, PTR2_DATA),
1134 PINMUX_GPIO(GPIO_PTR1, PTR1_DATA),
1135 PINMUX_GPIO(GPIO_PTR0, PTR0_DATA),
1136
1137 /* PTS */
1138 PINMUX_GPIO(GPIO_PTS7, PTS7_DATA),
1139 PINMUX_GPIO(GPIO_PTS6, PTS6_DATA),
1140 PINMUX_GPIO(GPIO_PTS5, PTS5_DATA),
1141 PINMUX_GPIO(GPIO_PTS4, PTS4_DATA),
1142 PINMUX_GPIO(GPIO_PTS3, PTS3_DATA),
1143 PINMUX_GPIO(GPIO_PTS2, PTS2_DATA),
1144 PINMUX_GPIO(GPIO_PTS1, PTS1_DATA),
1145 PINMUX_GPIO(GPIO_PTS0, PTS0_DATA),
1146
1147 /* PTT */
1148 PINMUX_GPIO(GPIO_PTT5, PTT5_DATA),
1149 PINMUX_GPIO(GPIO_PTT4, PTT4_DATA),
1150 PINMUX_GPIO(GPIO_PTT3, PTT3_DATA),
1151 PINMUX_GPIO(GPIO_PTT2, PTT2_DATA),
1152 PINMUX_GPIO(GPIO_PTT1, PTT1_DATA),
1153 PINMUX_GPIO(GPIO_PTT0, PTT0_DATA),
1154
1155 /* PTU */
1156 PINMUX_GPIO(GPIO_PTU7, PTU7_DATA),
1157 PINMUX_GPIO(GPIO_PTU6, PTU6_DATA),
1158 PINMUX_GPIO(GPIO_PTU5, PTU5_DATA),
1159 PINMUX_GPIO(GPIO_PTU4, PTU4_DATA),
1160 PINMUX_GPIO(GPIO_PTU3, PTU3_DATA),
1161 PINMUX_GPIO(GPIO_PTU2, PTU2_DATA),
1162 PINMUX_GPIO(GPIO_PTU1, PTU1_DATA),
1163 PINMUX_GPIO(GPIO_PTU0, PTU0_DATA),
1164
1165 /* PTV */
1166 PINMUX_GPIO(GPIO_PTV7, PTV7_DATA),
1167 PINMUX_GPIO(GPIO_PTV6, PTV6_DATA),
1168 PINMUX_GPIO(GPIO_PTV5, PTV5_DATA),
1169 PINMUX_GPIO(GPIO_PTV4, PTV4_DATA),
1170 PINMUX_GPIO(GPIO_PTV3, PTV3_DATA),
1171 PINMUX_GPIO(GPIO_PTV2, PTV2_DATA),
1172 PINMUX_GPIO(GPIO_PTV1, PTV1_DATA),
1173 PINMUX_GPIO(GPIO_PTV0, PTV0_DATA),
1174
1175 /* PTW */
1176 PINMUX_GPIO(GPIO_PTW7, PTW7_DATA),
1177 PINMUX_GPIO(GPIO_PTW6, PTW6_DATA),
1178 PINMUX_GPIO(GPIO_PTW5, PTW5_DATA),
1179 PINMUX_GPIO(GPIO_PTW4, PTW4_DATA),
1180 PINMUX_GPIO(GPIO_PTW3, PTW3_DATA),
1181 PINMUX_GPIO(GPIO_PTW2, PTW2_DATA),
1182 PINMUX_GPIO(GPIO_PTW1, PTW1_DATA),
1183 PINMUX_GPIO(GPIO_PTW0, PTW0_DATA),
1184
1185 /* PTX */
1186 PINMUX_GPIO(GPIO_PTX7, PTX7_DATA),
1187 PINMUX_GPIO(GPIO_PTX6, PTX6_DATA),
1188 PINMUX_GPIO(GPIO_PTX5, PTX5_DATA),
1189 PINMUX_GPIO(GPIO_PTX4, PTX4_DATA),
1190 PINMUX_GPIO(GPIO_PTX3, PTX3_DATA),
1191 PINMUX_GPIO(GPIO_PTX2, PTX2_DATA),
1192 PINMUX_GPIO(GPIO_PTX1, PTX1_DATA),
1193 PINMUX_GPIO(GPIO_PTX0, PTX0_DATA),
1194
1195 /* PTY */
1196 PINMUX_GPIO(GPIO_PTY7, PTY7_DATA),
1197 PINMUX_GPIO(GPIO_PTY6, PTY6_DATA),
1198 PINMUX_GPIO(GPIO_PTY5, PTY5_DATA),
1199 PINMUX_GPIO(GPIO_PTY4, PTY4_DATA),
1200 PINMUX_GPIO(GPIO_PTY3, PTY3_DATA),
1201 PINMUX_GPIO(GPIO_PTY2, PTY2_DATA),
1202 PINMUX_GPIO(GPIO_PTY1, PTY1_DATA),
1203 PINMUX_GPIO(GPIO_PTY0, PTY0_DATA),
1204
1205 /* PTZ */
1206 PINMUX_GPIO(GPIO_PTZ7, PTZ7_DATA),
1207 PINMUX_GPIO(GPIO_PTZ6, PTZ6_DATA),
1208 PINMUX_GPIO(GPIO_PTZ5, PTZ5_DATA),
1209 PINMUX_GPIO(GPIO_PTZ4, PTZ4_DATA),
1210 PINMUX_GPIO(GPIO_PTZ3, PTZ3_DATA),
1211 PINMUX_GPIO(GPIO_PTZ2, PTZ2_DATA),
1212 PINMUX_GPIO(GPIO_PTZ1, PTZ1_DATA),
1213 PINMUX_GPIO(GPIO_PTZ0, PTZ0_DATA),
1214
1215 /* PTA (mobule: LBSC, CPG, LPC) */
1216 PINMUX_GPIO(GPIO_FN_BS, BS_MARK),
1217 PINMUX_GPIO(GPIO_FN_RDWR, RDWR_MARK),
1218 PINMUX_GPIO(GPIO_FN_WE1, WE1_MARK),
1219 PINMUX_GPIO(GPIO_FN_RDY, RDY_MARK),
1220 PINMUX_GPIO(GPIO_FN_MD10, MD10_MARK),
1221 PINMUX_GPIO(GPIO_FN_MD9, MD9_MARK),
1222 PINMUX_GPIO(GPIO_FN_MD8, MD8_MARK),
1223 PINMUX_GPIO(GPIO_FN_LGPIO7, LGPIO7_MARK),
1224 PINMUX_GPIO(GPIO_FN_LGPIO6, LGPIO6_MARK),
1225 PINMUX_GPIO(GPIO_FN_LGPIO5, LGPIO5_MARK),
1226 PINMUX_GPIO(GPIO_FN_LGPIO4, LGPIO4_MARK),
1227 PINMUX_GPIO(GPIO_FN_LGPIO3, LGPIO3_MARK),
1228 PINMUX_GPIO(GPIO_FN_LGPIO2, LGPIO2_MARK),
1229 PINMUX_GPIO(GPIO_FN_LGPIO1, LGPIO1_MARK),
1230 PINMUX_GPIO(GPIO_FN_LGPIO0, LGPIO0_MARK),
1231
1232 /* PTB (mobule: LBSC, EtherC, SIM, LPC) */
1233 PINMUX_GPIO(GPIO_FN_D15, D15_MARK),
1234 PINMUX_GPIO(GPIO_FN_D14, D14_MARK),
1235 PINMUX_GPIO(GPIO_FN_D13, D13_MARK),
1236 PINMUX_GPIO(GPIO_FN_D12, D12_MARK),
1237 PINMUX_GPIO(GPIO_FN_D11, D11_MARK),
1238 PINMUX_GPIO(GPIO_FN_D10, D10_MARK),
1239 PINMUX_GPIO(GPIO_FN_D9, D9_MARK),
1240 PINMUX_GPIO(GPIO_FN_D8, D8_MARK),
1241 PINMUX_GPIO(GPIO_FN_ET0_MDC, ET0_MDC_MARK),
1242 PINMUX_GPIO(GPIO_FN_ET0_MDIO, ET0_MDIO_MARK),
1243 PINMUX_GPIO(GPIO_FN_ET1_MDC, ET1_MDC_MARK),
1244 PINMUX_GPIO(GPIO_FN_ET1_MDIO, ET1_MDIO_MARK),
1245 PINMUX_GPIO(GPIO_FN_WPSZ1, WPSZ1_MARK),
1246 PINMUX_GPIO(GPIO_FN_WPSZ0, WPSZ0_MARK),
1247 PINMUX_GPIO(GPIO_FN_FWID, FWID_MARK),
1248 PINMUX_GPIO(GPIO_FN_FLSHSZ, FLSHSZ_MARK),
1249 PINMUX_GPIO(GPIO_FN_LPC_SPIEN, LPC_SPIEN_MARK),
1250 PINMUX_GPIO(GPIO_FN_BASEL, BASEL_MARK),
1251
1252 /* PTC (mobule: SD) */
1253 PINMUX_GPIO(GPIO_FN_SD_WP, SD_WP_MARK),
1254 PINMUX_GPIO(GPIO_FN_SD_CD, SD_CD_MARK),
1255 PINMUX_GPIO(GPIO_FN_SD_CLK, SD_CLK_MARK),
1256 PINMUX_GPIO(GPIO_FN_SD_CMD, SD_CMD_MARK),
1257 PINMUX_GPIO(GPIO_FN_SD_D3, SD_D3_MARK),
1258 PINMUX_GPIO(GPIO_FN_SD_D2, SD_D2_MARK),
1259 PINMUX_GPIO(GPIO_FN_SD_D1, SD_D1_MARK),
1260 PINMUX_GPIO(GPIO_FN_SD_D0, SD_D0_MARK),
1261
1262 /* PTD (mobule: INTC, SPI0, LBSC, CPG, ADC) */
1263 PINMUX_GPIO(GPIO_FN_IRQ7, IRQ7_MARK),
1264 PINMUX_GPIO(GPIO_FN_IRQ6, IRQ6_MARK),
1265 PINMUX_GPIO(GPIO_FN_IRQ5, IRQ5_MARK),
1266 PINMUX_GPIO(GPIO_FN_IRQ4, IRQ4_MARK),
1267 PINMUX_GPIO(GPIO_FN_IRQ3, IRQ3_MARK),
1268 PINMUX_GPIO(GPIO_FN_IRQ2, IRQ2_MARK),
1269 PINMUX_GPIO(GPIO_FN_IRQ1, IRQ1_MARK),
1270 PINMUX_GPIO(GPIO_FN_IRQ0, IRQ0_MARK),
1271 PINMUX_GPIO(GPIO_FN_MD6, MD6_MARK),
1272 PINMUX_GPIO(GPIO_FN_MD5, MD5_MARK),
1273 PINMUX_GPIO(GPIO_FN_MD3, MD3_MARK),
1274 PINMUX_GPIO(GPIO_FN_MD2, MD2_MARK),
1275 PINMUX_GPIO(GPIO_FN_MD1, MD1_MARK),
1276 PINMUX_GPIO(GPIO_FN_MD0, MD0_MARK),
1277 PINMUX_GPIO(GPIO_FN_ADTRG1, ADTRG1_MARK),
1278 PINMUX_GPIO(GPIO_FN_ADTRG0, ADTRG0_MARK),
1279
1280 /* PTE (mobule: EtherC) */
1281 PINMUX_GPIO(GPIO_FN_ET0_CRS_DV, ET0_CRS_DV_MARK),
1282 PINMUX_GPIO(GPIO_FN_ET0_TXD1, ET0_TXD1_MARK),
1283 PINMUX_GPIO(GPIO_FN_ET0_TXD0, ET0_TXD0_MARK),
1284 PINMUX_GPIO(GPIO_FN_ET0_TX_EN, ET0_TX_EN_MARK),
1285 PINMUX_GPIO(GPIO_FN_ET0_REF_CLK, ET0_REF_CLK_MARK),
1286 PINMUX_GPIO(GPIO_FN_ET0_RXD1, ET0_RXD1_MARK),
1287 PINMUX_GPIO(GPIO_FN_ET0_RXD0, ET0_RXD0_MARK),
1288 PINMUX_GPIO(GPIO_FN_ET0_RX_ER, ET0_RX_ER_MARK),
1289
1290 /* PTF (mobule: EtherC) */
1291 PINMUX_GPIO(GPIO_FN_ET1_CRS_DV, ET1_CRS_DV_MARK),
1292 PINMUX_GPIO(GPIO_FN_ET1_TXD1, ET1_TXD1_MARK),
1293 PINMUX_GPIO(GPIO_FN_ET1_TXD0, ET1_TXD0_MARK),
1294 PINMUX_GPIO(GPIO_FN_ET1_TX_EN, ET1_TX_EN_MARK),
1295 PINMUX_GPIO(GPIO_FN_ET1_REF_CLK, ET1_REF_CLK_MARK),
1296 PINMUX_GPIO(GPIO_FN_ET1_RXD1, ET1_RXD1_MARK),
1297 PINMUX_GPIO(GPIO_FN_ET1_RXD0, ET1_RXD0_MARK),
1298 PINMUX_GPIO(GPIO_FN_ET1_RX_ER, ET1_RX_ER_MARK),
1299
1300 /* PTG (mobule: SYSTEM, PWMX, LPC) */
1301 PINMUX_GPIO(GPIO_FN_STATUS0, STATUS0_MARK),
1302 PINMUX_GPIO(GPIO_FN_STATUS1, STATUS1_MARK),
1303 PINMUX_GPIO(GPIO_FN_PWX0, PWX0_MARK),
1304 PINMUX_GPIO(GPIO_FN_PWX1, PWX1_MARK),
1305 PINMUX_GPIO(GPIO_FN_PWX2, PWX2_MARK),
1306 PINMUX_GPIO(GPIO_FN_PWX3, PWX3_MARK),
1307 PINMUX_GPIO(GPIO_FN_SERIRQ, SERIRQ_MARK),
1308 PINMUX_GPIO(GPIO_FN_CLKRUN, CLKRUN_MARK),
1309 PINMUX_GPIO(GPIO_FN_LPCPD, LPCPD_MARK),
1310 PINMUX_GPIO(GPIO_FN_LDRQ, LDRQ_MARK),
1311
1312 /* PTH (mobule: TMU, SCIF234, SPI1, SPI0) */
1313 PINMUX_GPIO(GPIO_FN_TCLK, TCLK_MARK),
1314 PINMUX_GPIO(GPIO_FN_RXD4, RXD4_MARK),
1315 PINMUX_GPIO(GPIO_FN_TXD4, TXD4_MARK),
1316 PINMUX_GPIO(GPIO_FN_SP1_MOSI, SP1_MOSI_MARK),
1317 PINMUX_GPIO(GPIO_FN_SP1_MISO, SP1_MISO_MARK),
1318 PINMUX_GPIO(GPIO_FN_SP1_SCK, SP1_SCK_MARK),
1319 PINMUX_GPIO(GPIO_FN_SP1_SCK_FB, SP1_SCK_FB_MARK),
1320 PINMUX_GPIO(GPIO_FN_SP1_SS0, SP1_SS0_MARK),
1321 PINMUX_GPIO(GPIO_FN_SP1_SS1, SP1_SS1_MARK),
1322 PINMUX_GPIO(GPIO_FN_SP0_SS1, SP0_SS1_MARK),
1323
1324 /* PTI (mobule: INTC) */
1325 PINMUX_GPIO(GPIO_FN_IRQ15, IRQ15_MARK),
1326 PINMUX_GPIO(GPIO_FN_IRQ14, IRQ14_MARK),
1327 PINMUX_GPIO(GPIO_FN_IRQ13, IRQ13_MARK),
1328 PINMUX_GPIO(GPIO_FN_IRQ12, IRQ12_MARK),
1329 PINMUX_GPIO(GPIO_FN_IRQ11, IRQ11_MARK),
1330 PINMUX_GPIO(GPIO_FN_IRQ10, IRQ10_MARK),
1331 PINMUX_GPIO(GPIO_FN_IRQ9, IRQ9_MARK),
1332 PINMUX_GPIO(GPIO_FN_IRQ8, IRQ8_MARK),
1333
1334 /* PTJ (mobule: SCIF234, SERMUX) */
1335 PINMUX_GPIO(GPIO_FN_RXD3, RXD3_MARK),
1336 PINMUX_GPIO(GPIO_FN_TXD3, TXD3_MARK),
1337 PINMUX_GPIO(GPIO_FN_RXD2, RXD2_MARK),
1338 PINMUX_GPIO(GPIO_FN_TXD2, TXD2_MARK),
1339 PINMUX_GPIO(GPIO_FN_COM1_TXD, COM1_TXD_MARK),
1340 PINMUX_GPIO(GPIO_FN_COM1_RXD, COM1_RXD_MARK),
1341 PINMUX_GPIO(GPIO_FN_COM1_RTS, COM1_RTS_MARK),
1342 PINMUX_GPIO(GPIO_FN_COM1_CTS, COM1_CTS_MARK),
1343
1344 /* PTK (mobule: SERMUX) */
1345 PINMUX_GPIO(GPIO_FN_COM2_TXD, COM2_TXD_MARK),
1346 PINMUX_GPIO(GPIO_FN_COM2_RXD, COM2_RXD_MARK),
1347 PINMUX_GPIO(GPIO_FN_COM2_RTS, COM2_RTS_MARK),
1348 PINMUX_GPIO(GPIO_FN_COM2_CTS, COM2_CTS_MARK),
1349 PINMUX_GPIO(GPIO_FN_COM2_DTR, COM2_DTR_MARK),
1350 PINMUX_GPIO(GPIO_FN_COM2_DSR, COM2_DSR_MARK),
1351 PINMUX_GPIO(GPIO_FN_COM2_DCD, COM2_DCD_MARK),
1352 PINMUX_GPIO(GPIO_FN_COM2_RI, COM2_RI_MARK),
1353
1354 /* PTL (mobule: SERMUX) */
1355 PINMUX_GPIO(GPIO_FN_RAC_TXD, RAC_TXD_MARK),
1356 PINMUX_GPIO(GPIO_FN_RAC_RXD, RAC_RXD_MARK),
1357 PINMUX_GPIO(GPIO_FN_RAC_RTS, RAC_RTS_MARK),
1358 PINMUX_GPIO(GPIO_FN_RAC_CTS, RAC_CTS_MARK),
1359 PINMUX_GPIO(GPIO_FN_RAC_DTR, RAC_DTR_MARK),
1360 PINMUX_GPIO(GPIO_FN_RAC_DSR, RAC_DSR_MARK),
1361 PINMUX_GPIO(GPIO_FN_RAC_DCD, RAC_DCD_MARK),
1362 PINMUX_GPIO(GPIO_FN_RAC_RI, RAC_RI_MARK),
1363
1364 /* PTM (mobule: IIC, LPC) */
1365 PINMUX_GPIO(GPIO_FN_SDA6, SDA6_MARK),
1366 PINMUX_GPIO(GPIO_FN_SCL6, SCL6_MARK),
1367 PINMUX_GPIO(GPIO_FN_SDA7, SDA7_MARK),
1368 PINMUX_GPIO(GPIO_FN_SCL7, SCL7_MARK),
1369 PINMUX_GPIO(GPIO_FN_WP, WP_MARK),
1370 PINMUX_GPIO(GPIO_FN_FMS0, FMS0_MARK),
1371 PINMUX_GPIO(GPIO_FN_FMS1, FMS1_MARK),
1372
1373 /* PTN (mobule: SCIF234, EVC) */
1374 PINMUX_GPIO(GPIO_FN_SCK2, SCK2_MARK),
1375 PINMUX_GPIO(GPIO_FN_RTS4, RTS4_MARK),
1376 PINMUX_GPIO(GPIO_FN_RTS3, RTS3_MARK),
1377 PINMUX_GPIO(GPIO_FN_RTS2, RTS2_MARK),
1378 PINMUX_GPIO(GPIO_FN_CTS4, CTS4_MARK),
1379 PINMUX_GPIO(GPIO_FN_CTS3, CTS3_MARK),
1380 PINMUX_GPIO(GPIO_FN_CTS2, CTS2_MARK),
1381 PINMUX_GPIO(GPIO_FN_EVENT7, EVENT7_MARK),
1382 PINMUX_GPIO(GPIO_FN_EVENT6, EVENT6_MARK),
1383 PINMUX_GPIO(GPIO_FN_EVENT5, EVENT5_MARK),
1384 PINMUX_GPIO(GPIO_FN_EVENT4, EVENT4_MARK),
1385 PINMUX_GPIO(GPIO_FN_EVENT3, EVENT3_MARK),
1386 PINMUX_GPIO(GPIO_FN_EVENT2, EVENT2_MARK),
1387 PINMUX_GPIO(GPIO_FN_EVENT1, EVENT1_MARK),
1388 PINMUX_GPIO(GPIO_FN_EVENT0, EVENT0_MARK),
1389
1390 /* PTO (mobule: SGPIO) */
1391 PINMUX_GPIO(GPIO_FN_SGPIO0_CLK, SGPIO0_CLK_MARK),
1392 PINMUX_GPIO(GPIO_FN_SGPIO0_LOAD, SGPIO0_LOAD_MARK),
1393 PINMUX_GPIO(GPIO_FN_SGPIO0_DI, SGPIO0_DI_MARK),
1394 PINMUX_GPIO(GPIO_FN_SGPIO0_DO, SGPIO0_DO_MARK),
1395 PINMUX_GPIO(GPIO_FN_SGPIO1_CLK, SGPIO1_CLK_MARK),
1396 PINMUX_GPIO(GPIO_FN_SGPIO1_LOAD, SGPIO1_LOAD_MARK),
1397 PINMUX_GPIO(GPIO_FN_SGPIO1_DI, SGPIO1_DI_MARK),
1398 PINMUX_GPIO(GPIO_FN_SGPIO1_DO, SGPIO1_DO_MARK),
1399
1400 /* PTP (mobule: JMC, SCIF234) */
1401 PINMUX_GPIO(GPIO_FN_JMCTCK, JMCTCK_MARK),
1402 PINMUX_GPIO(GPIO_FN_JMCTMS, JMCTMS_MARK),
1403 PINMUX_GPIO(GPIO_FN_JMCTDO, JMCTDO_MARK),
1404 PINMUX_GPIO(GPIO_FN_JMCTDI, JMCTDI_MARK),
1405 PINMUX_GPIO(GPIO_FN_JMCRST, JMCRST_MARK),
1406 PINMUX_GPIO(GPIO_FN_SCK4, SCK4_MARK),
1407 PINMUX_GPIO(GPIO_FN_SCK3, SCK3_MARK),
1408
1409 /* PTQ (mobule: LPC) */
1410 PINMUX_GPIO(GPIO_FN_LAD3, LAD3_MARK),
1411 PINMUX_GPIO(GPIO_FN_LAD2, LAD2_MARK),
1412 PINMUX_GPIO(GPIO_FN_LAD1, LAD1_MARK),
1413 PINMUX_GPIO(GPIO_FN_LAD0, LAD0_MARK),
1414 PINMUX_GPIO(GPIO_FN_LFRAME, LFRAME_MARK),
1415 PINMUX_GPIO(GPIO_FN_LRESET, LRESET_MARK),
1416 PINMUX_GPIO(GPIO_FN_LCLK, LCLK_MARK),
1417
1418 /* PTR (mobule: GRA, IIC) */
1419 PINMUX_GPIO(GPIO_FN_DDC3, DDC3_MARK),
1420 PINMUX_GPIO(GPIO_FN_DDC2, DDC2_MARK),
1421 PINMUX_GPIO(GPIO_FN_SDA8, SDA8_MARK),
1422 PINMUX_GPIO(GPIO_FN_SCL8, SCL8_MARK),
1423 PINMUX_GPIO(GPIO_FN_SDA2, SDA2_MARK),
1424 PINMUX_GPIO(GPIO_FN_SCL2, SCL2_MARK),
1425 PINMUX_GPIO(GPIO_FN_SDA1, SDA1_MARK),
1426 PINMUX_GPIO(GPIO_FN_SCL1, SCL1_MARK),
1427 PINMUX_GPIO(GPIO_FN_SDA0, SDA0_MARK),
1428 PINMUX_GPIO(GPIO_FN_SCL0, SCL0_MARK),
1429
1430 /* PTS (mobule: GRA, IIC) */
1431 PINMUX_GPIO(GPIO_FN_DDC1, DDC1_MARK),
1432 PINMUX_GPIO(GPIO_FN_DDC0, DDC0_MARK),
1433 PINMUX_GPIO(GPIO_FN_SDA9, SDA9_MARK),
1434 PINMUX_GPIO(GPIO_FN_SCL9, SCL9_MARK),
1435 PINMUX_GPIO(GPIO_FN_SDA5, SDA5_MARK),
1436 PINMUX_GPIO(GPIO_FN_SCL5, SCL5_MARK),
1437 PINMUX_GPIO(GPIO_FN_SDA4, SDA4_MARK),
1438 PINMUX_GPIO(GPIO_FN_SCL4, SCL4_MARK),
1439 PINMUX_GPIO(GPIO_FN_SDA3, SDA3_MARK),
1440 PINMUX_GPIO(GPIO_FN_SCL3, SCL3_MARK),
1441
1442 /* PTT (mobule: SYSTEM, PWMX) */
1443 PINMUX_GPIO(GPIO_FN_AUDSYNC, AUDSYNC_MARK),
1444 PINMUX_GPIO(GPIO_FN_AUDCK, AUDCK_MARK),
1445 PINMUX_GPIO(GPIO_FN_AUDATA3, AUDATA3_MARK),
1446 PINMUX_GPIO(GPIO_FN_AUDATA2, AUDATA2_MARK),
1447 PINMUX_GPIO(GPIO_FN_AUDATA1, AUDATA1_MARK),
1448 PINMUX_GPIO(GPIO_FN_AUDATA0, AUDATA0_MARK),
1449 PINMUX_GPIO(GPIO_FN_PWX7, PWX7_MARK),
1450 PINMUX_GPIO(GPIO_FN_PWX6, PWX6_MARK),
1451 PINMUX_GPIO(GPIO_FN_PWX5, PWX5_MARK),
1452 PINMUX_GPIO(GPIO_FN_PWX4, PWX4_MARK),
1453
1454 /* PTU (mobule: LBSC, DMAC) */
1455 PINMUX_GPIO(GPIO_FN_CS6, CS6_MARK),
1456 PINMUX_GPIO(GPIO_FN_CS5, CS5_MARK),
1457 PINMUX_GPIO(GPIO_FN_CS4, CS4_MARK),
1458 PINMUX_GPIO(GPIO_FN_CS0, CS0_MARK),
1459 PINMUX_GPIO(GPIO_FN_RD, RD_MARK),
1460 PINMUX_GPIO(GPIO_FN_WE0, WE0_MARK),
1461 PINMUX_GPIO(GPIO_FN_A25, A25_MARK),
1462 PINMUX_GPIO(GPIO_FN_A24, A24_MARK),
1463 PINMUX_GPIO(GPIO_FN_DREQ0, DREQ0_MARK),
1464 PINMUX_GPIO(GPIO_FN_DACK0, DACK0_MARK),
1465
1466 /* PTV (mobule: LBSC, DMAC) */
1467 PINMUX_GPIO(GPIO_FN_A23, A23_MARK),
1468 PINMUX_GPIO(GPIO_FN_A22, A22_MARK),
1469 PINMUX_GPIO(GPIO_FN_A21, A21_MARK),
1470 PINMUX_GPIO(GPIO_FN_A20, A20_MARK),
1471 PINMUX_GPIO(GPIO_FN_A19, A19_MARK),
1472 PINMUX_GPIO(GPIO_FN_A18, A18_MARK),
1473 PINMUX_GPIO(GPIO_FN_A17, A17_MARK),
1474 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1475 PINMUX_GPIO(GPIO_FN_TEND0, TEND0_MARK),
1476 PINMUX_GPIO(GPIO_FN_DREQ1, DREQ1_MARK),
1477 PINMUX_GPIO(GPIO_FN_DACK1, DACK1_MARK),
1478 PINMUX_GPIO(GPIO_FN_TEND1, TEND1_MARK),
1479
1480 /* PTW (mobule: LBSC) */
1481 PINMUX_GPIO(GPIO_FN_A16, A16_MARK),
1482 PINMUX_GPIO(GPIO_FN_A15, A15_MARK),
1483 PINMUX_GPIO(GPIO_FN_A14, A14_MARK),
1484 PINMUX_GPIO(GPIO_FN_A13, A13_MARK),
1485 PINMUX_GPIO(GPIO_FN_A12, A12_MARK),
1486 PINMUX_GPIO(GPIO_FN_A11, A11_MARK),
1487 PINMUX_GPIO(GPIO_FN_A10, A10_MARK),
1488 PINMUX_GPIO(GPIO_FN_A9, A9_MARK),
1489 PINMUX_GPIO(GPIO_FN_A8, A8_MARK),
1490
1491 /* PTX (mobule: LBSC) */
1492 PINMUX_GPIO(GPIO_FN_A7, A7_MARK),
1493 PINMUX_GPIO(GPIO_FN_A6, A6_MARK),
1494 PINMUX_GPIO(GPIO_FN_A5, A5_MARK),
1495 PINMUX_GPIO(GPIO_FN_A4, A4_MARK),
1496 PINMUX_GPIO(GPIO_FN_A3, A3_MARK),
1497 PINMUX_GPIO(GPIO_FN_A2, A2_MARK),
1498 PINMUX_GPIO(GPIO_FN_A1, A1_MARK),
1499 PINMUX_GPIO(GPIO_FN_A0, A0_MARK),
1500
1501 /* PTY (mobule: LBSC) */
1502 PINMUX_GPIO(GPIO_FN_D7, D7_MARK),
1503 PINMUX_GPIO(GPIO_FN_D6, D6_MARK),
1504 PINMUX_GPIO(GPIO_FN_D5, D5_MARK),
1505 PINMUX_GPIO(GPIO_FN_D4, D4_MARK),
1506 PINMUX_GPIO(GPIO_FN_D3, D3_MARK),
1507 PINMUX_GPIO(GPIO_FN_D2, D2_MARK),
1508 PINMUX_GPIO(GPIO_FN_D1, D1_MARK),
1509 PINMUX_GPIO(GPIO_FN_D0, D0_MARK),
1510 };
1511
1512static struct pinmux_cfg_reg pinmux_config_regs[] = {
1513 { PINMUX_CFG_REG("PACR", 0xffec0000, 16, 2) {
1514 PTA7_FN, PTA7_OUT, PTA7_IN, 0,
1515 PTA6_FN, PTA6_OUT, PTA6_IN, 0,
1516 PTA5_FN, PTA5_OUT, PTA5_IN, 0,
1517 PTA4_FN, PTA4_OUT, PTA4_IN, 0,
1518 PTA3_FN, PTA3_OUT, PTA3_IN, 0,
1519 PTA2_FN, PTA2_OUT, PTA2_IN, 0,
1520 PTA1_FN, PTA1_OUT, PTA1_IN, 0,
1521 PTA0_FN, PTA0_OUT, PTA0_IN, 0 }
1522 },
1523 { PINMUX_CFG_REG("PBCR", 0xffec0002, 16, 2) {
1524 PTB7_FN, PTB7_OUT, PTB7_IN, 0,
1525 PTB6_FN, PTB6_OUT, PTB6_IN, 0,
1526 PTB5_FN, PTB5_OUT, PTB5_IN, 0,
1527 PTB4_FN, PTB4_OUT, PTB4_IN, 0,
1528 PTB3_FN, PTB3_OUT, PTB3_IN, 0,
1529 PTB2_FN, PTB2_OUT, PTB2_IN, 0,
1530 PTB1_FN, PTB1_OUT, PTB1_IN, 0,
1531 PTB0_FN, PTB0_OUT, PTB0_IN, 0 }
1532 },
1533 { PINMUX_CFG_REG("PCCR", 0xffec0004, 16, 2) {
1534 PTC7_FN, PTC7_OUT, PTC7_IN, 0,
1535 PTC6_FN, PTC6_OUT, PTC6_IN, 0,
1536 PTC5_FN, PTC5_OUT, PTC5_IN, 0,
1537 PTC4_FN, PTC4_OUT, PTC4_IN, 0,
1538 PTC3_FN, PTC3_OUT, PTC3_IN, 0,
1539 PTC2_FN, PTC2_OUT, PTC2_IN, 0,
1540 PTC1_FN, PTC1_OUT, PTC1_IN, 0,
1541 PTC0_FN, PTC0_OUT, PTC0_IN, 0 }
1542 },
1543 { PINMUX_CFG_REG("PDCR", 0xffec0006, 16, 2) {
1544 PTD7_FN, PTD7_OUT, PTD7_IN, 0,
1545 PTD6_FN, PTD6_OUT, PTD6_IN, 0,
1546 PTD5_FN, PTD5_OUT, PTD5_IN, 0,
1547 PTD4_FN, PTD4_OUT, PTD4_IN, 0,
1548 PTD3_FN, PTD3_OUT, PTD3_IN, 0,
1549 PTD2_FN, PTD2_OUT, PTD2_IN, 0,
1550 PTD1_FN, PTD1_OUT, PTD1_IN, 0,
1551 PTD0_FN, PTD0_OUT, PTD0_IN, 0 }
1552 },
1553 { PINMUX_CFG_REG("PECR", 0xffec0008, 16, 2) {
1554 PTE7_FN, PTE7_OUT, PTE7_IN, 0,
1555 PTE6_FN, PTE6_OUT, PTE6_IN, 0,
1556 PTE5_FN, PTE5_OUT, PTE5_IN, 0,
1557 PTE4_FN, PTE4_OUT, PTE4_IN, 0,
1558 PTE3_FN, PTE3_OUT, PTE3_IN, 0,
1559 PTE2_FN, PTE2_OUT, PTE2_IN, 0,
1560 PTE1_FN, PTE1_OUT, PTE1_IN, 0,
1561 PTE0_FN, PTE0_OUT, PTE0_IN, 0 }
1562 },
1563 { PINMUX_CFG_REG("PFCR", 0xffec000a, 16, 2) {
1564 PTF7_FN, PTF7_OUT, PTF7_IN, 0,
1565 PTF6_FN, PTF6_OUT, PTF6_IN, 0,
1566 PTF5_FN, PTF5_OUT, PTF5_IN, 0,
1567 PTF4_FN, PTF4_OUT, PTF4_IN, 0,
1568 PTF3_FN, PTF3_OUT, PTF3_IN, 0,
1569 PTF2_FN, PTF2_OUT, PTF2_IN, 0,
1570 PTF1_FN, PTF1_OUT, PTF1_IN, 0,
1571 PTF0_FN, PTF0_OUT, PTF0_IN, 0 }
1572 },
1573 { PINMUX_CFG_REG("PGCR", 0xffec000c, 16, 2) {
1574 PTG7_FN, PTG7_OUT, PTG7_IN, 0,
1575 PTG6_FN, PTG6_OUT, PTG6_IN, 0,
1576 PTG5_FN, PTG5_OUT, PTG5_IN, 0,
1577 PTG4_FN, PTG4_OUT, PTG4_IN, 0,
1578 PTG3_FN, PTG3_OUT, PTG3_IN, 0,
1579 PTG2_FN, PTG2_OUT, PTG2_IN, 0,
1580 PTG1_FN, PTG1_OUT, PTG1_IN, 0,
1581 PTG0_FN, PTG0_OUT, PTG0_IN, 0 }
1582 },
1583 { PINMUX_CFG_REG("PHCR", 0xffec000e, 16, 2) {
1584 PTH7_FN, PTH7_OUT, PTH7_IN, 0,
1585 PTH6_FN, PTH6_OUT, PTH6_IN, 0,
1586 PTH5_FN, PTH5_OUT, PTH5_IN, 0,
1587 PTH4_FN, PTH4_OUT, PTH4_IN, 0,
1588 PTH3_FN, PTH3_OUT, PTH3_IN, 0,
1589 PTH2_FN, PTH2_OUT, PTH2_IN, 0,
1590 PTH1_FN, PTH1_OUT, PTH1_IN, 0,
1591 PTH0_FN, PTH0_OUT, PTH0_IN, 0 }
1592 },
1593 { PINMUX_CFG_REG("PICR", 0xffec0010, 16, 2) {
1594 PTI7_FN, PTI7_OUT, PTI7_IN, 0,
1595 PTI6_FN, PTI6_OUT, PTI6_IN, 0,
1596 PTI5_FN, PTI5_OUT, PTI5_IN, 0,
1597 PTI4_FN, PTI4_OUT, PTI4_IN, 0,
1598 PTI3_FN, PTI3_OUT, PTI3_IN, 0,
1599 PTI2_FN, PTI2_OUT, PTI2_IN, 0,
1600 PTI1_FN, PTI1_OUT, PTI1_IN, 0,
1601 PTI0_FN, PTI0_OUT, PTI0_IN, 0 }
1602 },
1603 { PINMUX_CFG_REG("PJCR", 0xffec0012, 16, 2) {
1604 PTJ7_FN, PTJ7_OUT, PTJ7_IN, 0,
1605 PTJ6_FN, PTJ6_OUT, PTJ6_IN, 0,
1606 PTJ5_FN, PTJ5_OUT, PTJ5_IN, 0,
1607 PTJ4_FN, PTJ4_OUT, PTJ4_IN, 0,
1608 PTJ3_FN, PTJ3_OUT, PTJ3_IN, 0,
1609 PTJ2_FN, PTJ2_OUT, PTJ2_IN, 0,
1610 PTJ1_FN, PTJ1_OUT, PTJ1_IN, 0,
1611 PTJ0_FN, PTJ0_OUT, PTJ0_IN, 0 }
1612 },
1613 { PINMUX_CFG_REG("PKCR", 0xffec0014, 16, 2) {
1614 PTK7_FN, PTK7_OUT, PTK7_IN, 0,
1615 PTK6_FN, PTK6_OUT, PTK6_IN, 0,
1616 PTK5_FN, PTK5_OUT, PTK5_IN, 0,
1617 PTK4_FN, PTK4_OUT, PTK4_IN, 0,
1618 PTK3_FN, PTK3_OUT, PTK3_IN, 0,
1619 PTK2_FN, PTK2_OUT, PTK2_IN, 0,
1620 PTK1_FN, PTK1_OUT, PTK1_IN, 0,
1621 PTK0_FN, PTK0_OUT, PTK0_IN, 0 }
1622 },
1623 { PINMUX_CFG_REG("PLCR", 0xffec0016, 16, 2) {
1624 PTL7_FN, PTL7_OUT, PTL7_IN, 0,
1625 PTL6_FN, PTL6_OUT, PTL6_IN, 0,
1626 PTL5_FN, PTL5_OUT, PTL5_IN, 0,
1627 PTL4_FN, PTL4_OUT, PTL4_IN, 0,
1628 PTL3_FN, PTL3_OUT, PTL3_IN, 0,
1629 PTL2_FN, PTL2_OUT, PTL2_IN, 0,
1630 PTL1_FN, PTL1_OUT, PTL1_IN, 0,
1631 PTL0_FN, PTL0_OUT, PTL0_IN, 0 }
1632 },
1633 { PINMUX_CFG_REG("PMCR", 0xffec0018, 16, 2) {
1634 0, 0, 0, 0, /* reserved: always set 1 */
1635 PTM6_FN, PTM6_OUT, PTM6_IN, 0,
1636 PTM5_FN, PTM5_OUT, PTM5_IN, 0,
1637 PTM4_FN, PTM4_OUT, PTM4_IN, 0,
1638 PTM3_FN, PTM3_OUT, PTM3_IN, 0,
1639 PTM2_FN, PTM2_OUT, PTM2_IN, 0,
1640 PTM1_FN, PTM1_OUT, PTM1_IN, 0,
1641 PTM0_FN, PTM0_OUT, PTM0_IN, 0 }
1642 },
1643 { PINMUX_CFG_REG("PNCR", 0xffec001a, 16, 2) {
1644 PTN7_FN, PTN7_OUT, PTN7_IN, 0,
1645 PTN6_FN, PTN6_OUT, PTN6_IN, 0,
1646 PTN5_FN, PTN5_OUT, PTN5_IN, 0,
1647 PTN4_FN, PTN4_OUT, PTN4_IN, 0,
1648 PTN3_FN, PTN3_OUT, PTN3_IN, 0,
1649 PTN2_FN, PTN2_OUT, PTN2_IN, 0,
1650 PTN1_FN, PTN1_OUT, PTN1_IN, 0,
1651 PTN0_FN, PTN0_OUT, PTN0_IN, 0 }
1652 },
1653 { PINMUX_CFG_REG("POCR", 0xffec001c, 16, 2) {
1654 PTO7_FN, PTO7_OUT, PTO7_IN, 0,
1655 PTO6_FN, PTO6_OUT, PTO6_IN, 0,
1656 PTO5_FN, PTO5_OUT, PTO5_IN, 0,
1657 PTO4_FN, PTO4_OUT, PTO4_IN, 0,
1658 PTO3_FN, PTO3_OUT, PTO3_IN, 0,
1659 PTO2_FN, PTO2_OUT, PTO2_IN, 0,
1660 PTO1_FN, PTO1_OUT, PTO1_IN, 0,
1661 PTO0_FN, PTO0_OUT, PTO0_IN, 0 }
1662 },
1663 { PINMUX_CFG_REG("PPCR", 0xffec001e, 16, 2) {
1664 0, 0, 0, 0, /* reserved: always set 1 */
1665 PTP6_FN, PTP6_OUT, PTP6_IN, 0,
1666 PTP5_FN, PTP5_OUT, PTP5_IN, 0,
1667 PTP4_FN, PTP4_OUT, PTP4_IN, 0,
1668 PTP3_FN, PTP3_OUT, PTP3_IN, 0,
1669 PTP2_FN, PTP2_OUT, PTP2_IN, 0,
1670 PTP1_FN, PTP1_OUT, PTP1_IN, 0,
1671 PTP0_FN, PTP0_OUT, PTP0_IN, 0 }
1672 },
1673 { PINMUX_CFG_REG("PQCR", 0xffec0020, 16, 2) {
1674 0, 0, 0, 0, /* reserved: always set 1 */
1675 PTQ6_FN, PTQ6_OUT, PTQ6_IN, 0,
1676 PTQ5_FN, PTQ5_OUT, PTQ5_IN, 0,
1677 PTQ4_FN, PTQ4_OUT, PTQ4_IN, 0,
1678 PTQ3_FN, PTQ3_OUT, PTQ3_IN, 0,
1679 PTQ2_FN, PTQ2_OUT, PTQ2_IN, 0,
1680 PTQ1_FN, PTQ1_OUT, PTQ1_IN, 0,
1681 PTQ0_FN, PTQ0_OUT, PTQ0_IN, 0 }
1682 },
1683 { PINMUX_CFG_REG("PRCR", 0xffec0022, 16, 2) {
1684 PTR7_FN, PTR7_OUT, PTR7_IN, 0,
1685 PTR6_FN, PTR6_OUT, PTR6_IN, 0,
1686 PTR5_FN, PTR5_OUT, PTR5_IN, 0,
1687 PTR4_FN, PTR4_OUT, PTR4_IN, 0,
1688 PTR3_FN, PTR3_OUT, PTR3_IN, 0,
1689 PTR2_FN, PTR2_OUT, PTR2_IN, 0,
1690 PTR1_FN, PTR1_OUT, PTR1_IN, 0,
1691 PTR0_FN, PTR0_OUT, PTR0_IN, 0 }
1692 },
1693 { PINMUX_CFG_REG("PSCR", 0xffec0024, 16, 2) {
1694 PTS7_FN, PTS7_OUT, PTS7_IN, 0,
1695 PTS6_FN, PTS6_OUT, PTS6_IN, 0,
1696 PTS5_FN, PTS5_OUT, PTS5_IN, 0,
1697 PTS4_FN, PTS4_OUT, PTS4_IN, 0,
1698 PTS3_FN, PTS3_OUT, PTS3_IN, 0,
1699 PTS2_FN, PTS2_OUT, PTS2_IN, 0,
1700 PTS1_FN, PTS1_OUT, PTS1_IN, 0,
1701 PTS0_FN, PTS0_OUT, PTS0_IN, 0 }
1702 },
1703 { PINMUX_CFG_REG("PTCR", 0xffec0026, 16, 2) {
1704 0, 0, 0, 0, /* reserved: always set 1 */
1705 0, 0, 0, 0, /* reserved: always set 1 */
1706 PTT5_FN, PTT5_OUT, PTT5_IN, 0,
1707 PTT4_FN, PTT4_OUT, PTT4_IN, 0,
1708 PTT3_FN, PTT3_OUT, PTT3_IN, 0,
1709 PTT2_FN, PTT2_OUT, PTT2_IN, 0,
1710 PTT1_FN, PTT1_OUT, PTT1_IN, 0,
1711 PTT0_FN, PTT0_OUT, PTT0_IN, 0 }
1712 },
1713 { PINMUX_CFG_REG("PUCR", 0xffec0028, 16, 2) {
1714 PTU7_FN, PTU7_OUT, PTU7_IN, PTU7_IN_PU,
1715 PTU6_FN, PTU6_OUT, PTU6_IN, PTU6_IN_PU,
1716 PTU5_FN, PTU5_OUT, PTU5_IN, PTU5_IN_PU,
1717 PTU4_FN, PTU4_OUT, PTU4_IN, PTU4_IN_PU,
1718 PTU3_FN, PTU3_OUT, PTU3_IN, PTU3_IN_PU,
1719 PTU2_FN, PTU2_OUT, PTU2_IN, PTU2_IN_PU,
1720 PTU1_FN, PTU1_OUT, PTU1_IN, PTU1_IN_PU,
1721 PTU0_FN, PTU0_OUT, PTU0_IN, PTU0_IN_PU }
1722 },
1723 { PINMUX_CFG_REG("PVCR", 0xffec002a, 16, 2) {
1724 PTV7_FN, PTV7_OUT, PTV7_IN, PTV7_IN_PU,
1725 PTV6_FN, PTV6_OUT, PTV6_IN, PTV6_IN_PU,
1726 PTV5_FN, PTV5_OUT, PTV5_IN, PTV5_IN_PU,
1727 PTV4_FN, PTV4_OUT, PTV4_IN, PTV4_IN_PU,
1728 PTV3_FN, PTV3_OUT, PTV3_IN, PTV3_IN_PU,
1729 PTV2_FN, PTV2_OUT, PTV2_IN, PTV2_IN_PU,
1730 PTV1_FN, PTV1_OUT, PTV1_IN, PTV1_IN_PU,
1731 PTV0_FN, PTV0_OUT, PTV0_IN, PTV0_IN_PU }
1732 },
1733 { PINMUX_CFG_REG("PWCR", 0xffec002c, 16, 2) {
1734 PTW7_FN, PTW7_OUT, PTW7_IN, PTW7_IN_PU,
1735 PTW6_FN, PTW6_OUT, PTW6_IN, PTW6_IN_PU,
1736 PTW5_FN, PTW5_OUT, PTW5_IN, PTW5_IN_PU,
1737 PTW4_FN, PTW4_OUT, PTW4_IN, PTW4_IN_PU,
1738 PTW3_FN, PTW3_OUT, PTW3_IN, PTW3_IN_PU,
1739 PTW2_FN, PTW2_OUT, PTW2_IN, PTW2_IN_PU,
1740 PTW1_FN, PTW1_OUT, PTW1_IN, PTW1_IN_PU,
1741 PTW0_FN, PTW0_OUT, PTW0_IN, PTW0_IN_PU }
1742 },
1743 { PINMUX_CFG_REG("PXCR", 0xffec002e, 16, 2) {
1744 PTX7_FN, PTX7_OUT, PTX7_IN, PTX7_IN_PU,
1745 PTX6_FN, PTX6_OUT, PTX6_IN, PTX6_IN_PU,
1746 PTX5_FN, PTX5_OUT, PTX5_IN, PTX5_IN_PU,
1747 PTX4_FN, PTX4_OUT, PTX4_IN, PTX4_IN_PU,
1748 PTX3_FN, PTX3_OUT, PTX3_IN, PTX3_IN_PU,
1749 PTX2_FN, PTX2_OUT, PTX2_IN, PTX2_IN_PU,
1750 PTX1_FN, PTX1_OUT, PTX1_IN, PTX1_IN_PU,
1751 PTX0_FN, PTX0_OUT, PTX0_IN, PTX0_IN_PU }
1752 },
1753 { PINMUX_CFG_REG("PYCR", 0xffec0030, 16, 2) {
1754 PTY7_FN, PTY7_OUT, PTY7_IN, PTY7_IN_PU,
1755 PTY6_FN, PTY6_OUT, PTY6_IN, PTY6_IN_PU,
1756 PTY5_FN, PTY5_OUT, PTY5_IN, PTY5_IN_PU,
1757 PTY4_FN, PTY4_OUT, PTY4_IN, PTY4_IN_PU,
1758 PTY3_FN, PTY3_OUT, PTY3_IN, PTY3_IN_PU,
1759 PTY2_FN, PTY2_OUT, PTY2_IN, PTY2_IN_PU,
1760 PTY1_FN, PTY1_OUT, PTY1_IN, PTY1_IN_PU,
1761 PTY0_FN, PTY0_OUT, PTY0_IN, PTY0_IN_PU }
1762 },
1763 { PINMUX_CFG_REG("PZCR", 0xffec0032, 16, 2) {
1764 0, PTZ7_OUT, PTZ7_IN, 0,
1765 0, PTZ6_OUT, PTZ6_IN, 0,
1766 0, PTZ5_OUT, PTZ5_IN, 0,
1767 0, PTZ4_OUT, PTZ4_IN, 0,
1768 0, PTZ3_OUT, PTZ3_IN, 0,
1769 0, PTZ2_OUT, PTZ2_IN, 0,
1770 0, PTZ1_OUT, PTZ1_IN, 0,
1771 0, PTZ0_OUT, PTZ0_IN, 0 }
1772 },
1773
1774 { PINMUX_CFG_REG("PSEL0", 0xffec0070, 16, 1) {
1775 PS0_15_FN3, PS0_15_FN1,
1776 PS0_14_FN3, PS0_14_FN1,
1777 PS0_13_FN3, PS0_13_FN1,
1778 PS0_12_FN3, PS0_12_FN1,
1779 0, 0,
1780 0, 0,
1781 0, 0,
1782 0, 0,
1783 PS0_7_FN2, PS0_7_FN1,
1784 PS0_6_FN2, PS0_6_FN1,
1785 PS0_5_FN2, PS0_5_FN1,
1786 PS0_4_FN2, PS0_4_FN1,
1787 PS0_3_FN2, PS0_3_FN1,
1788 PS0_2_FN2, PS0_2_FN1,
1789 PS0_1_FN2, PS0_1_FN1,
1790 0, 0, }
1791 },
1792 { PINMUX_CFG_REG("PSEL1", 0xffec0072, 16, 1) {
1793 0, 0,
1794 0, 0,
1795 0, 0,
1796 0, 0,
1797 0, 0,
1798 0, 0,
1799 0, 0,
1800 0, 0,
1801 PS1_7_FN1, PS1_7_FN3,
1802 PS1_6_FN1, PS1_6_FN3,
1803 0, 0,
1804 0, 0,
1805 0, 0,
1806 0, 0,
1807 0, 0,
1808 0, 0, }
1809 },
1810 { PINMUX_CFG_REG("PSEL2", 0xffec0074, 16, 1) {
1811 0, 0,
1812 0, 0,
1813 PS2_13_FN3, PS2_13_FN1,
1814 PS2_12_FN3, PS2_12_FN1,
1815 0, 0,
1816 0, 0,
1817 0, 0,
1818 0, 0,
1819 0, 0,
1820 0, 0,
1821 0, 0,
1822 0, 0,
1823 0, 0,
1824 0, 0,
1825 PS2_1_FN1, PS2_1_FN2,
1826 PS2_0_FN1, PS2_0_FN2, }
1827 },
1828 { PINMUX_CFG_REG("PSEL4", 0xffec0078, 16, 1) {
1829 PS4_15_FN2, PS4_15_FN1,
1830 PS4_14_FN2, PS4_14_FN1,
1831 PS4_13_FN2, PS4_13_FN1,
1832 PS4_12_FN2, PS4_12_FN1,
1833 PS4_11_FN2, PS4_11_FN1,
1834 PS4_10_FN2, PS4_10_FN1,
1835 PS4_9_FN2, PS4_9_FN1,
1836 0, 0,
1837 0, 0,
1838 0, 0,
1839 0, 0,
1840 0, 0,
1841 PS4_3_FN2, PS4_3_FN1,
1842 PS4_2_FN2, PS4_2_FN1,
1843 PS4_1_FN2, PS4_1_FN1,
1844 PS4_0_FN2, PS4_0_FN1, }
1845 },
1846 { PINMUX_CFG_REG("PSEL5", 0xffec007a, 16, 1) {
1847 0, 0,
1848 0, 0,
1849 0, 0,
1850 0, 0,
1851 0, 0,
1852 0, 0,
1853 PS5_9_FN1, PS5_9_FN2,
1854 PS5_8_FN1, PS5_8_FN2,
1855 PS5_7_FN1, PS5_7_FN2,
1856 PS5_6_FN1, PS5_6_FN2,
1857 PS5_5_FN1, PS5_5_FN2,
1858 0, 0,
1859 0, 0,
1860 0, 0,
1861 0, 0,
1862 0, 0, }
1863 },
1864 { PINMUX_CFG_REG("PSEL6", 0xffec007c, 16, 1) {
1865 0, 0,
1866 0, 0,
1867 0, 0,
1868 0, 0,
1869 0, 0,
1870 0, 0,
1871 0, 0,
1872 0, 0,
1873 PS6_7_FN_AN, PS6_7_FN_EV,
1874 PS6_6_FN_AN, PS6_6_FN_EV,
1875 PS6_5_FN_AN, PS6_5_FN_EV,
1876 PS6_4_FN_AN, PS6_4_FN_EV,
1877 PS6_3_FN_AN, PS6_3_FN_EV,
1878 PS6_2_FN_AN, PS6_2_FN_EV,
1879 PS6_1_FN_AN, PS6_1_FN_EV,
1880 PS6_0_FN_AN, PS6_0_FN_EV, }
1881 },
1882 {}
1883};
1884
1885static struct pinmux_data_reg pinmux_data_regs[] = {
1886 { PINMUX_DATA_REG("PADR", 0xffec0034, 8) {
1887 PTA7_DATA, PTA6_DATA, PTA5_DATA, PTA4_DATA,
1888 PTA3_DATA, PTA2_DATA, PTA1_DATA, PTA0_DATA }
1889 },
1890 { PINMUX_DATA_REG("PBDR", 0xffec0036, 8) {
1891 PTB7_DATA, PTB6_DATA, PTB5_DATA, PTB4_DATA,
1892 PTB3_DATA, PTB2_DATA, PTB1_DATA, PTB0_DATA }
1893 },
1894 { PINMUX_DATA_REG("PCDR", 0xffec0038, 8) {
1895 PTC7_DATA, PTC6_DATA, PTC5_DATA, PTC4_DATA,
1896 PTC3_DATA, PTC2_DATA, PTC1_DATA, PTC0_DATA }
1897 },
1898 { PINMUX_DATA_REG("PDDR", 0xffec003a, 8) {
1899 PTD7_DATA, PTD6_DATA, PTD5_DATA, PTD4_DATA,
1900 PTD3_DATA, PTD2_DATA, PTD1_DATA, PTD0_DATA }
1901 },
1902 { PINMUX_DATA_REG("PEDR", 0xffec003c, 8) {
1903 PTE7_DATA, PTE6_DATA, PTE5_DATA, PTE4_DATA,
1904 PTE3_DATA, PTE2_DATA, PTE1_DATA, PTE0_DATA }
1905 },
1906 { PINMUX_DATA_REG("PFDR", 0xffec003e, 8) {
1907 PTF7_DATA, PTF6_DATA, PTF5_DATA, PTF4_DATA,
1908 PTF3_DATA, PTF2_DATA, PTF1_DATA, PTF0_DATA }
1909 },
1910 { PINMUX_DATA_REG("PGDR", 0xffec0040, 8) {
1911 PTG7_DATA, PTG6_DATA, PTG5_DATA, PTG4_DATA,
1912 PTG3_DATA, PTG2_DATA, PTG1_DATA, PTG0_DATA }
1913 },
1914 { PINMUX_DATA_REG("PHDR", 0xffec0042, 8) {
1915 PTH7_DATA, PTH6_DATA, PTH5_DATA, PTH4_DATA,
1916 PTH3_DATA, PTH2_DATA, PTH1_DATA, PTH0_DATA }
1917 },
1918 { PINMUX_DATA_REG("PIDR", 0xffec0044, 8) {
1919 PTI7_DATA, PTI6_DATA, PTI5_DATA, PTI4_DATA,
1920 PTI3_DATA, PTI2_DATA, PTI1_DATA, PTI0_DATA }
1921 },
1922 { PINMUX_DATA_REG("PJDR", 0xffec0046, 8) {
1923 PTJ7_DATA, PTJ6_DATA, PTJ5_DATA, PTJ4_DATA,
1924 PTJ3_DATA, PTJ2_DATA, PTJ1_DATA, PTJ0_DATA }
1925 },
1926 { PINMUX_DATA_REG("PKDR", 0xffec0048, 8) {
1927 PTK7_DATA, PTK6_DATA, PTK5_DATA, PTK4_DATA,
1928 PTK3_DATA, PTK2_DATA, PTK1_DATA, PTK0_DATA }
1929 },
1930 { PINMUX_DATA_REG("PLDR", 0xffec004a, 8) {
1931 PTL7_DATA, PTL6_DATA, PTL5_DATA, PTL4_DATA,
1932 PTL3_DATA, PTL2_DATA, PTL1_DATA, PTL0_DATA }
1933 },
1934 { PINMUX_DATA_REG("PMDR", 0xffec004c, 8) {
1935 0, PTM6_DATA, PTM5_DATA, PTM4_DATA,
1936 PTM3_DATA, PTM2_DATA, PTM1_DATA, PTM0_DATA }
1937 },
1938 { PINMUX_DATA_REG("PNDR", 0xffec004e, 8) {
1939 PTN7_DATA, PTN6_DATA, PTN5_DATA, PTN4_DATA,
1940 PTN3_DATA, PTN2_DATA, PTN1_DATA, PTN0_DATA }
1941 },
1942 { PINMUX_DATA_REG("PODR", 0xffec0050, 8) {
1943 PTO7_DATA, PTO6_DATA, PTO5_DATA, PTO4_DATA,
1944 PTO3_DATA, PTO2_DATA, PTO1_DATA, PTO0_DATA }
1945 },
1946 { PINMUX_DATA_REG("PPDR", 0xffec0052, 8) {
1947 0, PTP6_DATA, PTP5_DATA, PTP4_DATA,
1948 PTP3_DATA, PTP2_DATA, PTP1_DATA, PTP0_DATA }
1949 },
1950 { PINMUX_DATA_REG("PQDR", 0xffec0054, 8) {
1951 0, PTQ6_DATA, PTQ5_DATA, PTQ4_DATA,
1952 PTQ3_DATA, PTQ2_DATA, PTQ1_DATA, PTQ0_DATA }
1953 },
1954 { PINMUX_DATA_REG("PRDR", 0xffec0056, 8) {
1955 PTR7_DATA, PTR6_DATA, PTR5_DATA, PTR4_DATA,
1956 PTR3_DATA, PTR2_DATA, PTR1_DATA, PTR0_DATA }
1957 },
1958 { PINMUX_DATA_REG("PSDR", 0xffec0058, 8) {
1959 PTS7_DATA, PTS6_DATA, PTS5_DATA, PTS4_DATA,
1960 PTS3_DATA, PTS2_DATA, PTS1_DATA, PTS0_DATA }
1961 },
1962 { PINMUX_DATA_REG("PTDR", 0xffec005a, 8) {
1963 0, 0, PTT5_DATA, PTT4_DATA,
1964 PTT3_DATA, PTT2_DATA, PTT1_DATA, PTT0_DATA }
1965 },
1966 { PINMUX_DATA_REG("PUDR", 0xffec005c, 8) {
1967 PTU7_DATA, PTU6_DATA, PTU5_DATA, PTU4_DATA,
1968 PTU3_DATA, PTU2_DATA, PTU1_DATA, PTU0_DATA }
1969 },
1970 { PINMUX_DATA_REG("PVDR", 0xffec005e, 8) {
1971 PTV7_DATA, PTV6_DATA, PTV5_DATA, PTV4_DATA,
1972 PTV3_DATA, PTV2_DATA, PTV1_DATA, PTV0_DATA }
1973 },
1974 { PINMUX_DATA_REG("PWDR", 0xffec0060, 8) {
1975 PTW7_DATA, PTW6_DATA, PTW5_DATA, PTW4_DATA,
1976 PTW3_DATA, PTW2_DATA, PTW1_DATA, PTW0_DATA }
1977 },
1978 { PINMUX_DATA_REG("PXDR", 0xffec0062, 8) {
1979 PTX7_DATA, PTX6_DATA, PTX5_DATA, PTX4_DATA,
1980 PTX3_DATA, PTX2_DATA, PTX1_DATA, PTX0_DATA }
1981 },
1982 { PINMUX_DATA_REG("PYDR", 0xffec0064, 8) {
1983 PTY7_DATA, PTY6_DATA, PTY5_DATA, PTY4_DATA,
1984 PTY3_DATA, PTY2_DATA, PTY1_DATA, PTY0_DATA }
1985 },
1986 { PINMUX_DATA_REG("PZDR", 0xffec0066, 8) {
1987 PTZ7_DATA, PTZ6_DATA, PTZ5_DATA, PTZ4_DATA,
1988 PTZ3_DATA, PTZ2_DATA, PTZ1_DATA, PTZ0_DATA }
1989 },
1990 { },
1991};
1992
1993static struct pinmux_info sh7757_pinmux_info = {
1994 .name = "sh7757_pfc",
1995 .reserved_id = PINMUX_RESERVED,
1996 .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
1997 .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
1998 .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
1999 .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2000 .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
2001 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2002
2003 .first_gpio = GPIO_PTA7,
2004 .last_gpio = GPIO_FN_D0,
2005
2006 .gpios = pinmux_gpios,
2007 .cfg_regs = pinmux_config_regs,
2008 .data_regs = pinmux_data_regs,
2009
2010 .gpio_data = pinmux_data,
2011 .gpio_data_size = ARRAY_SIZE(pinmux_data),
2012};
2013
2014static int __init plat_pinmux_setup(void)
2015{
2016 return register_pinmux(&sh7757_pinmux_info);
2017}
2018
2019arch_initcall(plat_pinmux_setup);
diff --git a/arch/sh/kernel/cpu/sh4a/setup-sh7757.c b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
new file mode 100644
index 000000000000..c470e15f2e03
--- /dev/null
+++ b/arch/sh/kernel/cpu/sh4a/setup-sh7757.c
@@ -0,0 +1,513 @@
1/*
2 * SH7757 Setup
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * based on setup-sh7785.c : Copyright (C) 2007 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12#include <linux/platform_device.h>
13#include <linux/init.h>
14#include <linux/serial.h>
15#include <linux/serial_sci.h>
16#include <linux/io.h>
17#include <linux/mm.h>
18#include <linux/sh_timer.h>
19
20static struct sh_timer_config tmu0_platform_data = {
21 .name = "TMU0",
22 .channel_offset = 0x04,
23 .timer_bit = 0,
24 .clk = "peripheral_clk",
25 .clockevent_rating = 200,
26};
27
28static struct resource tmu0_resources[] = {
29 [0] = {
30 .name = "TMU0",
31 .start = 0xfe430008,
32 .end = 0xfe430013,
33 .flags = IORESOURCE_MEM,
34 },
35 [1] = {
36 .start = 28,
37 .flags = IORESOURCE_IRQ,
38 },
39};
40
41static struct platform_device tmu0_device = {
42 .name = "sh_tmu",
43 .id = 0,
44 .dev = {
45 .platform_data = &tmu0_platform_data,
46 },
47 .resource = tmu0_resources,
48 .num_resources = ARRAY_SIZE(tmu0_resources),
49};
50
51static struct sh_timer_config tmu1_platform_data = {
52 .name = "TMU1",
53 .channel_offset = 0x10,
54 .timer_bit = 1,
55 .clk = "peripheral_clk",
56 .clocksource_rating = 200,
57};
58
59static struct resource tmu1_resources[] = {
60 [0] = {
61 .name = "TMU1",
62 .start = 0xfe430014,
63 .end = 0xfe43001f,
64 .flags = IORESOURCE_MEM,
65 },
66 [1] = {
67 .start = 29,
68 .flags = IORESOURCE_IRQ,
69 },
70};
71
72static struct platform_device tmu1_device = {
73 .name = "sh_tmu",
74 .id = 1,
75 .dev = {
76 .platform_data = &tmu1_platform_data,
77 },
78 .resource = tmu1_resources,
79 .num_resources = ARRAY_SIZE(tmu1_resources),
80};
81
82static struct plat_sci_port sci_platform_data[] = {
83 {
84 .mapbase = 0xfe4b0000, /* SCIF2 */
85 .flags = UPF_BOOT_AUTOCONF,
86 .type = PORT_SCIF,
87 .irqs = { 40, 40, 40, 40 },
88 }, {
89 .mapbase = 0xfe4c0000, /* SCIF3 */
90 .flags = UPF_BOOT_AUTOCONF,
91 .type = PORT_SCIF,
92 .irqs = { 76, 76, 76, 76 },
93 }, {
94 .mapbase = 0xfe4d0000, /* SCIF4 */
95 .flags = UPF_BOOT_AUTOCONF,
96 .type = PORT_SCIF,
97 .irqs = { 104, 104, 104, 104 },
98 }, {
99 .flags = 0,
100 }
101};
102
103static struct platform_device sci_device = {
104 .name = "sh-sci",
105 .id = -1,
106 .dev = {
107 .platform_data = sci_platform_data,
108 },
109};
110
111static struct platform_device *sh7757_devices[] __initdata = {
112 &tmu0_device,
113 &tmu1_device,
114 &sci_device,
115};
116
117static int __init sh7757_devices_setup(void)
118{
119 return platform_add_devices(sh7757_devices,
120 ARRAY_SIZE(sh7757_devices));
121}
122arch_initcall(sh7757_devices_setup);
123
124enum {
125 UNUSED = 0,
126
127 /* interrupt sources */
128
129 IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
130 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
131 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
132 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
133
134 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
135 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
136 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
137 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
138 IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
139
140 SDHI,
141 DVC,
142 IRQ8, IRQ9, IRQ10,
143 WDT0,
144 TMU0, TMU1, TMU2, TMU2_TICPI,
145 HUDI,
146
147 ARC4,
148 DMAC0,
149 IRQ11,
150 SCIF2,
151 DMAC1_6,
152 USB0,
153 IRQ12,
154 JMC,
155 SPI1,
156 IRQ13, IRQ14,
157 USB1,
158 TMR01, TMR23, TMR45,
159 WDT1,
160 FRT,
161 LPC,
162 SCIF0, SCIF1, SCIF3,
163 PECI0I, PECI1I, PECI2I,
164 IRQ15,
165 ETHERC,
166 SPI0,
167 ADC1,
168 DMAC1_8,
169 SIM,
170 TMU3, TMU4, TMU5,
171 ADC0,
172 SCIF4,
173 IIC0_0, IIC0_1, IIC0_2, IIC0_3,
174 IIC1_0, IIC1_1, IIC1_2, IIC1_3,
175 IIC2_0, IIC2_1, IIC2_2, IIC2_3,
176 IIC3_0, IIC3_1, IIC3_2, IIC3_3,
177 IIC4_0, IIC4_1, IIC4_2, IIC4_3,
178 IIC5_0, IIC5_1, IIC5_2, IIC5_3,
179 IIC6_0, IIC6_1, IIC6_2, IIC6_3,
180 IIC7_0, IIC7_1, IIC7_2, IIC7_3,
181 IIC8_0, IIC8_1, IIC8_2, IIC8_3,
182 IIC9_0, IIC9_1, IIC9_2, IIC9_3,
183 PCIINTA,
184 PCIE,
185 SGPIO,
186
187 /* interrupt groups */
188
189 TMU012, TMU345,
190};
191
192static struct intc_vect vectors[] __initdata = {
193 INTC_VECT(SDHI, 0x480), INTC_VECT(SDHI, 0x04a0),
194 INTC_VECT(SDHI, 0x4c0),
195 INTC_VECT(DVC, 0x4e0),
196 INTC_VECT(IRQ8, 0x500), INTC_VECT(IRQ9, 0x520),
197 INTC_VECT(IRQ10, 0x540),
198 INTC_VECT(WDT0, 0x560),
199 INTC_VECT(TMU0, 0x580), INTC_VECT(TMU1, 0x5a0),
200 INTC_VECT(TMU2, 0x5c0), INTC_VECT(TMU2_TICPI, 0x5e0),
201 INTC_VECT(HUDI, 0x600),
202 INTC_VECT(ARC4, 0x620),
203 INTC_VECT(DMAC0, 0x640), INTC_VECT(DMAC0, 0x660),
204 INTC_VECT(DMAC0, 0x680), INTC_VECT(DMAC0, 0x6a0),
205 INTC_VECT(DMAC0, 0x6c0),
206 INTC_VECT(IRQ11, 0x6e0),
207 INTC_VECT(SCIF2, 0x700), INTC_VECT(SCIF2, 0x720),
208 INTC_VECT(SCIF2, 0x740), INTC_VECT(SCIF2, 0x760),
209 INTC_VECT(DMAC0, 0x780), INTC_VECT(DMAC0, 0x7a0),
210 INTC_VECT(DMAC1_6, 0x7c0), INTC_VECT(DMAC1_6, 0x7e0),
211 INTC_VECT(USB0, 0x840),
212 INTC_VECT(IRQ12, 0x880),
213 INTC_VECT(JMC, 0x8a0),
214 INTC_VECT(SPI1, 0x8c0),
215 INTC_VECT(IRQ13, 0x8e0), INTC_VECT(IRQ14, 0x900),
216 INTC_VECT(USB1, 0x920),
217 INTC_VECT(TMR01, 0xa00), INTC_VECT(TMR23, 0xa20),
218 INTC_VECT(TMR45, 0xa40),
219 INTC_VECT(WDT1, 0xa60),
220 INTC_VECT(FRT, 0xa80),
221 INTC_VECT(LPC, 0xaa0), INTC_VECT(LPC, 0xac0),
222 INTC_VECT(LPC, 0xae0), INTC_VECT(LPC, 0xb00),
223 INTC_VECT(LPC, 0xb20),
224 INTC_VECT(SCIF0, 0xb40), INTC_VECT(SCIF1, 0xb60),
225 INTC_VECT(SCIF3, 0xb80), INTC_VECT(SCIF3, 0xba0),
226 INTC_VECT(SCIF3, 0xbc0), INTC_VECT(SCIF3, 0xbe0),
227 INTC_VECT(PECI0I, 0xc00), INTC_VECT(PECI1I, 0xc20),
228 INTC_VECT(PECI2I, 0xc40),
229 INTC_VECT(IRQ15, 0xc60),
230 INTC_VECT(ETHERC, 0xc80), INTC_VECT(ETHERC, 0xca0),
231 INTC_VECT(SPI0, 0xcc0),
232 INTC_VECT(ADC1, 0xce0),
233 INTC_VECT(DMAC1_8, 0xd00), INTC_VECT(DMAC1_8, 0xd20),
234 INTC_VECT(DMAC1_8, 0xd40), INTC_VECT(DMAC1_8, 0xd60),
235 INTC_VECT(SIM, 0xd80), INTC_VECT(SIM, 0xda0),
236 INTC_VECT(SIM, 0xdc0), INTC_VECT(SIM, 0xde0),
237 INTC_VECT(TMU3, 0xe00), INTC_VECT(TMU4, 0xe20),
238 INTC_VECT(TMU5, 0xe40),
239 INTC_VECT(ADC0, 0xe60),
240 INTC_VECT(SCIF4, 0xf00), INTC_VECT(SCIF4, 0xf20),
241 INTC_VECT(SCIF4, 0xf40), INTC_VECT(SCIF4, 0xf60),
242 INTC_VECT(IIC0_0, 0x1400), INTC_VECT(IIC0_1, 0x1420),
243 INTC_VECT(IIC0_2, 0x1440), INTC_VECT(IIC0_3, 0x1460),
244 INTC_VECT(IIC1_0, 0x1480), INTC_VECT(IIC1_1, 0x14e0),
245 INTC_VECT(IIC1_2, 0x1500), INTC_VECT(IIC1_3, 0x1520),
246 INTC_VECT(IIC2_0, 0x1540), INTC_VECT(IIC2_1, 0x1560),
247 INTC_VECT(IIC2_2, 0x1580), INTC_VECT(IIC2_3, 0x1600),
248 INTC_VECT(IIC3_0, 0x1620), INTC_VECT(IIC3_1, 0x1640),
249 INTC_VECT(IIC3_2, 0x16e0), INTC_VECT(IIC3_3, 0x1700),
250 INTC_VECT(IIC4_0, 0x17c0), INTC_VECT(IIC4_1, 0x1800),
251 INTC_VECT(IIC4_2, 0x1820), INTC_VECT(IIC4_3, 0x1840),
252 INTC_VECT(IIC5_0, 0x1860), INTC_VECT(IIC5_1, 0x1880),
253 INTC_VECT(IIC5_2, 0x18a0), INTC_VECT(IIC5_3, 0x18c0),
254 INTC_VECT(IIC6_0, 0x18e0), INTC_VECT(IIC6_1, 0x1900),
255 INTC_VECT(IIC6_2, 0x1920), INTC_VECT(IIC6_3, 0x1980),
256 INTC_VECT(IIC7_0, 0x19a0), INTC_VECT(IIC7_1, 0x1a00),
257 INTC_VECT(IIC7_2, 0x1a20), INTC_VECT(IIC7_3, 0x1a40),
258 INTC_VECT(IIC8_0, 0x1a60), INTC_VECT(IIC8_1, 0x1a80),
259 INTC_VECT(IIC8_2, 0x1aa0), INTC_VECT(IIC8_3, 0x1b40),
260 INTC_VECT(IIC9_0, 0x1b60), INTC_VECT(IIC9_1, 0x1b80),
261 INTC_VECT(IIC9_2, 0x1c00), INTC_VECT(IIC9_3, 0x1c20),
262 INTC_VECT(PCIINTA, 0x1ce0),
263 INTC_VECT(PCIE, 0x1e00),
264 INTC_VECT(SGPIO, 0x1f80),
265 INTC_VECT(SGPIO, 0x1fa0),
266};
267
268static struct intc_group groups[] __initdata = {
269 INTC_GROUP(TMU012, TMU0, TMU1, TMU2, TMU2_TICPI),
270 INTC_GROUP(TMU345, TMU3, TMU4, TMU5),
271};
272
273static struct intc_mask_reg mask_registers[] __initdata = {
274 { 0xffd00044, 0xffd00064, 32, /* INTMSK0 / INTMSKCLR0 */
275 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
276
277 { 0xffd40080, 0xffd40084, 32, /* INTMSK2 / INTMSKCLR2 */
278 { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
279 IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
280 IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
281 IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
282 IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
283 IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
284 IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
285 IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
286
287 { 0xffd40038, 0xffd4003c, 32, /* INT2MSKR / INT2MSKCR */
288 { 0, 0, 0, 0, 0, 0, 0, 0,
289 0, DMAC1_8, 0, PECI0I, LPC, FRT, WDT1, TMR45,
290 TMR23, TMR01, 0, 0, 0, 0, 0, DMAC0,
291 HUDI, 0, WDT0, SCIF3, SCIF2, SDHI, TMU345, TMU012
292 } },
293
294 { 0xffd400d0, 0xffd400d4, 32, /* INT2MSKR1 / INT2MSKCR1 */
295 { IRQ15, IRQ14, IRQ13, IRQ12, IRQ11, IRQ10, SCIF4, ETHERC,
296 IRQ9, IRQ8, SCIF1, SCIF0, USB0, 0, 0, USB1,
297 ADC1, 0, DMAC1_6, ADC0, SPI0, SIM, PECI2I, PECI1I,
298 ARC4, 0, SPI1, JMC, 0, 0, 0, DVC
299 } },
300
301 { 0xffd10038, 0xffd1003c, 32, /* INT2MSKR2 / INT2MSKCR2 */
302 { IIC4_1, IIC4_2, IIC5_0, 0, 0, 0, SGPIO, 0,
303 0, 0, 0, IIC9_2, IIC8_2, IIC8_1, IIC8_0, IIC7_3,
304 IIC7_2, IIC7_1, IIC6_3, IIC0_0, IIC0_1, IIC0_2, IIC0_3, IIC3_1,
305 IIC2_3, 0, IIC2_1, IIC9_1, IIC3_3, IIC1_0, PCIE, IIC2_2
306 } },
307
308 { 0xffd100d0, 0xff1400d4, 32, /* INT2MSKR3 / INT2MSKCR4 */
309 { 0, IIC6_1, IIC6_0, IIC5_1, IIC3_2, IIC2_0, 0, 0,
310 IIC1_3, IIC1_2, IIC9_0, IIC8_3, IIC4_3, IIC7_0, 0, IIC6_2,
311 PCIINTA, 0, IIC4_0, 0, 0, 0, 0, IIC9_3,
312 IIC3_0, 0, IIC5_3, IIC5_2, 0, 0, 0, IIC1_1
313 } },
314};
315
316#define INTPRI 0xffd00010
317#define INT2PRI0 0xffd40000
318#define INT2PRI1 0xffd40004
319#define INT2PRI2 0xffd40008
320#define INT2PRI3 0xffd4000c
321#define INT2PRI4 0xffd40010
322#define INT2PRI5 0xffd40014
323#define INT2PRI6 0xffd40018
324#define INT2PRI7 0xffd4001c
325#define INT2PRI8 0xffd400a0
326#define INT2PRI9 0xffd400a4
327#define INT2PRI10 0xffd400a8
328#define INT2PRI11 0xffd400ac
329#define INT2PRI12 0xffd400b0
330#define INT2PRI13 0xffd400b4
331#define INT2PRI14 0xffd400b8
332#define INT2PRI15 0xffd400bc
333#define INT2PRI16 0xffd10000
334#define INT2PRI17 0xffd10004
335#define INT2PRI18 0xffd10008
336#define INT2PRI19 0xffd1000c
337#define INT2PRI20 0xffd10010
338#define INT2PRI21 0xffd10014
339#define INT2PRI22 0xffd10018
340#define INT2PRI23 0xffd1001c
341#define INT2PRI24 0xffd100a0
342#define INT2PRI25 0xffd100a4
343#define INT2PRI26 0xffd100a8
344#define INT2PRI27 0xffd100ac
345#define INT2PRI28 0xffd100b0
346#define INT2PRI29 0xffd100b4
347#define INT2PRI30 0xffd100b8
348#define INT2PRI31 0xffd100bc
349
350static struct intc_prio_reg prio_registers[] __initdata = {
351 { INTPRI, 0, 32, 4, { IRQ0, IRQ1, IRQ2, IRQ3,
352 IRQ4, IRQ5, IRQ6, IRQ7 } },
353
354 { INT2PRI0, 0, 32, 8, { TMU0, TMU1, TMU2, TMU2_TICPI } },
355 { INT2PRI1, 0, 32, 8, { TMU3, TMU4, TMU5, SDHI } },
356 { INT2PRI2, 0, 32, 8, { SCIF2, SCIF3, WDT0, IRQ8 } },
357 { INT2PRI3, 0, 32, 8, { HUDI, DMAC0, ADC0, IRQ9 } },
358 { INT2PRI4, 0, 32, 8, { IRQ10, 0, TMR01, TMR23 } },
359 { INT2PRI5, 0, 32, 8, { TMR45, WDT1, FRT, LPC } },
360 { INT2PRI6, 0, 32, 8, { PECI0I, ETHERC, DMAC1_8, 0 } },
361 { INT2PRI7, 0, 32, 8, { SCIF4, 0, IRQ11, IRQ12 } },
362 { INT2PRI8, 0, 32, 8, { 0, 0, 0, DVC } },
363 { INT2PRI9, 0, 32, 8, { ARC4, 0, SPI1, JMC } },
364 { INT2PRI10, 0, 32, 8, { SPI0, SIM, PECI2I, PECI1I } },
365 { INT2PRI11, 0, 32, 8, { ADC1, IRQ13, DMAC1_6, IRQ14 } },
366 { INT2PRI12, 0, 32, 8, { USB0, 0, IRQ15, USB1 } },
367 { INT2PRI13, 0, 32, 8, { 0, 0, SCIF1, SCIF0 } },
368
369 { INT2PRI16, 0, 32, 8, { IIC2_2, 0, 0, 0 } },
370 { INT2PRI17, 0, 32, 8, { PCIE, 0, 0, IIC1_0 } },
371 { INT2PRI18, 0, 32, 8, { IIC3_3, IIC9_1, IIC2_1, IIC1_2 } },
372 { INT2PRI19, 0, 32, 8, { IIC2_3, IIC3_1, 0, IIC1_3 } },
373 { INT2PRI20, 0, 32, 8, { IIC2_0, IIC6_3, IIC7_1, IIC7_2 } },
374 { INT2PRI21, 0, 32, 8, { IIC7_3, IIC8_0, IIC8_1, IIC8_2 } },
375 { INT2PRI22, 0, 32, 8, { IIC9_2, 0, 0, 0 } },
376 { INT2PRI23, 0, 32, 8, { 0, SGPIO, IIC3_2, IIC5_1 } },
377 { INT2PRI24, 0, 32, 8, { 0, 0, 0, IIC1_1 } },
378 { INT2PRI25, 0, 32, 8, { IIC3_0, 0, IIC5_3, IIC5_2 } },
379 { INT2PRI26, 0, 32, 8, { 0, 0, 0, IIC9_3 } },
380 { INT2PRI27, 0, 32, 8, { PCIINTA, IIC6_0, IIC4_0, IIC6_1 } },
381 { INT2PRI28, 0, 32, 8, { IIC4_3, IIC7_0, 0, IIC6_2 } },
382 { INT2PRI29, 0, 32, 8, { 0, 0, IIC9_0, IIC8_3 } },
383 { INT2PRI30, 0, 32, 8, { IIC4_1, IIC4_2, IIC5_0, 0 } },
384 { INT2PRI31, 0, 32, 8, { IIC0_0, IIC0_1, IIC0_2, IIC0_3 } },
385};
386
387static DECLARE_INTC_DESC(intc_desc, "sh7757", vectors, groups,
388 mask_registers, prio_registers, NULL);
389
390/* Support for external interrupt pins in IRQ mode */
391static struct intc_vect vectors_irq0123[] __initdata = {
392 INTC_VECT(IRQ0, 0x240), INTC_VECT(IRQ1, 0x280),
393 INTC_VECT(IRQ2, 0x2c0), INTC_VECT(IRQ3, 0x300),
394};
395
396static struct intc_vect vectors_irq4567[] __initdata = {
397 INTC_VECT(IRQ4, 0x340), INTC_VECT(IRQ5, 0x380),
398 INTC_VECT(IRQ6, 0x3c0), INTC_VECT(IRQ7, 0x200),
399};
400
401static struct intc_sense_reg sense_registers[] __initdata = {
402 { 0xffd0001c, 32, 2, /* ICR1 */ { IRQ0, IRQ1, IRQ2, IRQ3,
403 IRQ4, IRQ5, IRQ6, IRQ7 } },
404};
405
406static struct intc_mask_reg ack_registers[] __initdata = {
407 { 0xffd00024, 0, 32, /* INTREQ */
408 { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
409};
410
411static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7757-irq0123",
412 vectors_irq0123, NULL, mask_registers,
413 prio_registers, sense_registers, ack_registers);
414
415static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7757-irq4567",
416 vectors_irq4567, NULL, mask_registers,
417 prio_registers, sense_registers, ack_registers);
418
419/* External interrupt pins in IRL mode */
420static struct intc_vect vectors_irl0123[] __initdata = {
421 INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
422 INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
423 INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
424 INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
425 INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
426 INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
427 INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
428 INTC_VECT(IRL0_HHHL, 0x3c0),
429};
430
431static struct intc_vect vectors_irl4567[] __initdata = {
432 INTC_VECT(IRL4_LLLL, 0xb00), INTC_VECT(IRL4_LLLH, 0xb20),
433 INTC_VECT(IRL4_LLHL, 0xb40), INTC_VECT(IRL4_LLHH, 0xb60),
434 INTC_VECT(IRL4_LHLL, 0xb80), INTC_VECT(IRL4_LHLH, 0xba0),
435 INTC_VECT(IRL4_LHHL, 0xbc0), INTC_VECT(IRL4_LHHH, 0xbe0),
436 INTC_VECT(IRL4_HLLL, 0xc00), INTC_VECT(IRL4_HLLH, 0xc20),
437 INTC_VECT(IRL4_HLHL, 0xc40), INTC_VECT(IRL4_HLHH, 0xc60),
438 INTC_VECT(IRL4_HHLL, 0xc80), INTC_VECT(IRL4_HHLH, 0xca0),
439 INTC_VECT(IRL4_HHHL, 0xcc0),
440};
441
442static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7757-irl0123", vectors_irl0123,
443 NULL, mask_registers, NULL, NULL);
444
445static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7757-irl4567", vectors_irl4567,
446 NULL, mask_registers, NULL, NULL);
447
448#define INTC_ICR0 0xffd00000
449#define INTC_INTMSK0 0xffd00044
450#define INTC_INTMSK1 0xffd00048
451#define INTC_INTMSK2 0xffd40080
452#define INTC_INTMSKCLR1 0xffd00068
453#define INTC_INTMSKCLR2 0xffd40084
454
455void __init plat_irq_setup(void)
456{
457 /* disable IRQ3-0 + IRQ7-4 */
458 ctrl_outl(0xff000000, INTC_INTMSK0);
459
460 /* disable IRL3-0 + IRL7-4 */
461 ctrl_outl(0xc0000000, INTC_INTMSK1);
462 ctrl_outl(0xfffefffe, INTC_INTMSK2);
463
464 /* select IRL mode for IRL3-0 + IRL7-4 */
465 ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
466
467 /* disable holding function, ie enable "SH-4 Mode" */
468 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00200000, INTC_ICR0);
469
470 register_intc_controller(&intc_desc);
471}
472
473void __init plat_irq_setup_pins(int mode)
474{
475 switch (mode) {
476 case IRQ_MODE_IRQ7654:
477 /* select IRQ mode for IRL7-4 */
478 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
479 register_intc_controller(&intc_desc_irq4567);
480 break;
481 case IRQ_MODE_IRQ3210:
482 /* select IRQ mode for IRL3-0 */
483 ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
484 register_intc_controller(&intc_desc_irq0123);
485 break;
486 case IRQ_MODE_IRL7654:
487 /* enable IRL7-4 but don't provide any masking */
488 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
489 ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
490 break;
491 case IRQ_MODE_IRL3210:
492 /* enable IRL0-3 but don't provide any masking */
493 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
494 ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
495 break;
496 case IRQ_MODE_IRL7654_MASK:
497 /* enable IRL7-4 and mask using cpu intc controller */
498 ctrl_outl(0x40000000, INTC_INTMSKCLR1);
499 register_intc_controller(&intc_desc_irl4567);
500 break;
501 case IRQ_MODE_IRL3210_MASK:
502 /* enable IRL0-3 and mask using cpu intc controller */
503 ctrl_outl(0x80000000, INTC_INTMSKCLR1);
504 register_intc_controller(&intc_desc_irl0123);
505 break;
506 default:
507 BUG();
508 }
509}
510
511void __init plat_mem_setup(void)
512{
513}
diff --git a/arch/sh/kernel/setup.c b/arch/sh/kernel/setup.c
index ceb409bf7741..212e6bddaeb8 100644
--- a/arch/sh/kernel/setup.c
+++ b/arch/sh/kernel/setup.c
@@ -481,7 +481,7 @@ static const char *cpu_name[] = {
481 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770", 481 [CPU_SH7763] = "SH7763", [CPU_SH7770] = "SH7770",
482 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781", 482 [CPU_SH7780] = "SH7780", [CPU_SH7781] = "SH7781",
483 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785", 483 [CPU_SH7343] = "SH7343", [CPU_SH7785] = "SH7785",
484 [CPU_SH7786] = "SH7786", 484 [CPU_SH7786] = "SH7786", [CPU_SH7757] = "SH7757",
485 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3", 485 [CPU_SH7722] = "SH7722", [CPU_SHX3] = "SH-X3",
486 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103", 486 [CPU_SH5_101] = "SH5-101", [CPU_SH5_103] = "SH5-103",
487 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723", 487 [CPU_MXG] = "MX-G", [CPU_SH7723] = "SH7723",
diff --git a/arch/sh/mm/Kconfig b/arch/sh/mm/Kconfig
index 2795618e4f07..64dc1ad59801 100644
--- a/arch/sh/mm/Kconfig
+++ b/arch/sh/mm/Kconfig
@@ -82,7 +82,7 @@ config 32BIT
82 82
83config PMB_ENABLE 83config PMB_ENABLE
84 bool "Support 32-bit physical addressing through PMB" 84 bool "Support 32-bit physical addressing through PMB"
85 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) 85 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
86 select 32BIT 86 select 32BIT
87 default y 87 default y
88 help 88 help
@@ -97,7 +97,7 @@ choice
97 97
98config PMB 98config PMB
99 bool "PMB" 99 bool "PMB"
100 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785) 100 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || CPU_SUBTYPE_SH7780 || CPU_SUBTYPE_SH7785)
101 select 32BIT 101 select 32BIT
102 help 102 help
103 If you say Y here, physical addressing will be extended to 103 If you say Y here, physical addressing will be extended to
@@ -106,7 +106,8 @@ config PMB
106 106
107config PMB_FIXED 107config PMB_FIXED
108 bool "fixed PMB" 108 bool "fixed PMB"
109 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7780 || \ 109 depends on MMU && EXPERIMENTAL && (CPU_SUBTYPE_SH7757 || \
110 CPU_SUBTYPE_SH7780 || \
110 CPU_SUBTYPE_SH7785) 111 CPU_SUBTYPE_SH7785)
111 select 32BIT 112 select 32BIT
112 help 113 help
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 4cbb87ad070a..32dc2fc50e6b 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -272,7 +272,8 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
272 __raw_writew(data, PSCR); 272 __raw_writew(data, PSCR);
273 } 273 }
274} 274}
275#elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \ 275#elif defined(CONFIG_CPU_SUBTYPE_SH7757) || \
276 defined(CONFIG_CPU_SUBTYPE_SH7763) || \
276 defined(CONFIG_CPU_SUBTYPE_SH7780) || \ 277 defined(CONFIG_CPU_SUBTYPE_SH7780) || \
277 defined(CONFIG_CPU_SUBTYPE_SH7785) || \ 278 defined(CONFIG_CPU_SUBTYPE_SH7785) || \
278 defined(CONFIG_CPU_SUBTYPE_SH7786) || \ 279 defined(CONFIG_CPU_SUBTYPE_SH7786) || \
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index 38072c15b845..3e2fcf93b42e 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -112,6 +112,13 @@
112#elif defined(CONFIG_H8S2678) 112#elif defined(CONFIG_H8S2678)
113# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ 113# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */
114# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) 114# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port)
115#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
116# define SCSPTR0 0xfe4b0020
117# define SCSPTR1 0xfe4b0020
118# define SCSPTR2 0xfe4b0020
119# define SCIF_ORER 0x0001
120# define SCSCR_INIT(port) 0x38
121# define SCIF_ONLY
115#elif defined(CONFIG_CPU_SUBTYPE_SH7763) 122#elif defined(CONFIG_CPU_SUBTYPE_SH7763)
116# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ 123# define SCSPTR0 0xffe00024 /* 16 bit SCIF */
117# define SCSPTR1 0xffe08024 /* 16 bit SCIF */ 124# define SCSPTR1 0xffe08024 /* 16 bit SCIF */
@@ -562,6 +569,16 @@ static inline int sci_rxd_in(struct uart_port *port)
562 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */ 569 return ctrl_inw(SCSPTR2)&0x0001 ? 1 : 0; /* SCIF */
563 return 1; 570 return 1;
564} 571}
572#elif defined(CONFIG_CPU_SUBTYPE_SH7757)
573static inline int sci_rxd_in(struct uart_port *port)
574{
575 if (port->mapbase == 0xfe4b0000)
576 return ctrl_inw(SCSPTR0) & 0x0001 ? 1 : 0;
577 if (port->mapbase == 0xfe4c0000)
578 return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0;
579 if (port->mapbase == 0xfe4d0000)
580 return ctrl_inw(SCSPTR2) & 0x0001 ? 1 : 0;
581}
565#elif defined(CONFIG_CPU_SUBTYPE_SH7760) 582#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
566static inline int sci_rxd_in(struct uart_port *port) 583static inline int sci_rxd_in(struct uart_port *port)
567{ 584{
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-30 23:58:42 -0500