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-rw-r--r--arch/mips/au1000/pb1100/Makefile6
-rw-r--r--arch/mips/au1000/pb1100/board_setup.c50
-rw-r--r--arch/mips/au1000/pb1100/init.c11
-rw-r--r--arch/mips/au1000/pb1100/irqmap.c10
-rw-r--r--include/asm-mips/mach-pb1x00/pb1100.h96
5 files changed, 87 insertions, 86 deletions
diff --git a/arch/mips/au1000/pb1100/Makefile b/arch/mips/au1000/pb1100/Makefile
index 996236df6375..793e97c49e46 100644
--- a/arch/mips/au1000/pb1100/Makefile
+++ b/arch/mips/au1000/pb1100/Makefile
@@ -1,8 +1,8 @@
1# 1#
2# Copyright 2000,2001 MontaVista Software Inc. 2# Copyright 2000, 2001, 2008 MontaVista Software Inc.
3# Author: MontaVista Software, Inc. 3# Author: MontaVista Software, Inc. <source@mvista.com>
4# ppopov@mvista.com or source@mvista.com
5# 4#
6# Makefile for the Alchemy Semiconductor Pb1100 board. 5# Makefile for the Alchemy Semiconductor Pb1100 board.
6#
7 7
8lib-y := init.o board_setup.o irqmap.o 8lib-y := init.o board_setup.o irqmap.o
diff --git a/arch/mips/au1000/pb1100/board_setup.c b/arch/mips/au1000/pb1100/board_setup.c
index 656164c8e9ca..c0bfd59a7a36 100644
--- a/arch/mips/au1000/pb1100/board_setup.c
+++ b/arch/mips/au1000/pb1100/board_setup.c
@@ -1,7 +1,6 @@
1/* 1/*
2 * Copyright 2002 MontaVista Software Inc. 2 * Copyright 2002, 2008 MontaVista Software Inc.
3 * Author: MontaVista Software, Inc. 3 * Author: MontaVista Software, Inc. <source@mvista.com>
4 * ppopov@mvista.com or source@mvista.com
5 * 4 *
6 * This program is free software; you can redistribute it and/or modify it 5 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the 6 * under the terms of the GNU General Public License as published by the
@@ -32,15 +31,15 @@
32 31
33void board_reset(void) 32void board_reset(void)
34{ 33{
35 /* Hit BCSR.SYSTEM_CONTROL[SW_RST] */ 34 /* Hit BCSR.RST_VDDI[SOFT_RESET] */
36 au_writel(0x00000000, 0xAE00001C); 35 au_writel(0x00000000, PB1100_RST_VDDI);
37} 36}
38 37
39void __init board_setup(void) 38void __init board_setup(void)
40{ 39{
41 volatile void __iomem * base = (volatile void __iomem *) 0xac000000UL; 40 volatile void __iomem *base = (volatile void __iomem *)0xac000000UL;
42 41
43 // set AUX clock to 12MHz * 8 = 96 MHz 42 /* Set AUX clock to 12 MHz * 8 = 96 MHz */
44 au_writel(8, SYS_AUXPLL); 43 au_writel(8, SYS_AUXPLL);
45 au_writel(0, SYS_PININPUTEN); 44 au_writel(0, SYS_PININPUTEN);
46 udelay(100); 45 udelay(100);
@@ -49,44 +48,47 @@ void __init board_setup(void)
49 { 48 {
50 u32 pin_func, sys_freqctrl, sys_clksrc; 49 u32 pin_func, sys_freqctrl, sys_clksrc;
51 50
52 // configure pins GPIO[14:9] as GPIO 51 /* Configure pins GPIO[14:9] as GPIO */
53 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x80); 52 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_UR3;
54 53
55 /* zero and disable FREQ2 */ 54 /* Zero and disable FREQ2 */
56 sys_freqctrl = au_readl(SYS_FREQCTRL0); 55 sys_freqctrl = au_readl(SYS_FREQCTRL0);
57 sys_freqctrl &= ~0xFFF00000; 56 sys_freqctrl &= ~0xFFF00000;
58 au_writel(sys_freqctrl, SYS_FREQCTRL0); 57 au_writel(sys_freqctrl, SYS_FREQCTRL0);
59 58
60 /* zero and disable USBH/USBD/IrDA clock */ 59 /* Zero and disable USBH/USBD/IrDA clock */
61 sys_clksrc = au_readl(SYS_CLKSRC); 60 sys_clksrc = au_readl(SYS_CLKSRC);
62 sys_clksrc &= ~0x0000001F; 61 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
63 au_writel(sys_clksrc, SYS_CLKSRC); 62 au_writel(sys_clksrc, SYS_CLKSRC);
64 63
65 sys_freqctrl = au_readl(SYS_FREQCTRL0); 64 sys_freqctrl = au_readl(SYS_FREQCTRL0);
66 sys_freqctrl &= ~0xFFF00000; 65 sys_freqctrl &= ~0xFFF00000;
67 66
68 sys_clksrc = au_readl(SYS_CLKSRC); 67 sys_clksrc = au_readl(SYS_CLKSRC);
69 sys_clksrc &= ~0x0000001F; 68 sys_clksrc &= ~(SYS_CS_CIR | SYS_CS_DIR | SYS_CS_MIR_MASK);
70 69
71 // FREQ2 = aux/2 = 48 MHz 70 /* FREQ2 = aux / 2 = 48 MHz */
72 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20)); 71 sys_freqctrl |= (0 << SYS_FC_FRDIV2_BIT) |
72 SYS_FC_FE2 | SYS_FC_FS2;
73 au_writel(sys_freqctrl, SYS_FREQCTRL0); 73 au_writel(sys_freqctrl, SYS_FREQCTRL0);
74 74
75 /* 75 /*
76 * Route 48MHz FREQ2 into USBH/USBD/IrDA 76 * Route 48 MHz FREQ2 into USBH/USBD/IrDA
77 */ 77 */
78 sys_clksrc |= ((4<<2) | (0<<1) | 0 ); 78 sys_clksrc |= SYS_CS_MUX_FQ2 << SYS_CS_MIR_BIT;
79 au_writel(sys_clksrc, SYS_CLKSRC); 79 au_writel(sys_clksrc, SYS_CLKSRC);
80 80
81 /* setup the static bus controller */ 81 /* Setup the static bus controller */
82 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */ 82 au_writel(0x00000002, MEM_STCFG3); /* type = PCMCIA */
83 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */ 83 au_writel(0x280E3D07, MEM_STTIME3); /* 250ns cycle time */
84 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */ 84 au_writel(0x10000000, MEM_STADDR3); /* any PCMCIA select */
85 85
86 // get USB Functionality pin state (device vs host drive pins) 86 /*
87 pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8000); 87 * Get USB Functionality pin state (device vs host drive pins).
88 // 2nd USB port is USB host 88 */
89 pin_func |= 0x8000; 89 pin_func = au_readl(SYS_PINFUNC) & ~SYS_PF_USB;
90 /* 2nd USB port is USB host. */
91 pin_func |= SYS_PF_USB;
90 au_writel(pin_func, SYS_PINFUNC); 92 au_writel(pin_func, SYS_PINFUNC);
91 } 93 }
92#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */ 94#endif /* defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE) */
@@ -94,12 +96,12 @@ void __init board_setup(void)
94 /* Enable sys bus clock divider when IDLE state or no bus activity. */ 96 /* Enable sys bus clock divider when IDLE state or no bus activity. */
95 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL); 97 au_writel(au_readl(SYS_POWERCTRL) | (0x3 << 5), SYS_POWERCTRL);
96 98
97 // Enable the RTC if not already enabled 99 /* Enable the RTC if not already enabled. */
98 if (!(readb(base + 0x28) & 0x20)) { 100 if (!(readb(base + 0x28) & 0x20)) {
99 writeb(readb(base + 0x28) | 0x20, base + 0x28); 101 writeb(readb(base + 0x28) | 0x20, base + 0x28);
100 au_sync(); 102 au_sync();
101 } 103 }
102 // Put the clock in BCD mode 104 /* Put the clock in BCD mode. */
103 if (readb(base + 0x2C) & 0x4) { /* reg B */ 105 if (readb(base + 0x2C) & 0x4) { /* reg B */
104 writeb(readb(base + 0x2c) & ~0x4, base + 0x2c); 106 writeb(readb(base + 0x2c) & ~0x4, base + 0x2c);
105 au_sync(); 107 au_sync();
diff --git a/arch/mips/au1000/pb1100/init.c b/arch/mips/au1000/pb1100/init.c
index c91344648ed3..8355483f3de2 100644
--- a/arch/mips/au1000/pb1100/init.c
+++ b/arch/mips/au1000/pb1100/init.c
@@ -3,9 +3,8 @@
3 * BRIEF MODULE DESCRIPTION 3 * BRIEF MODULE DESCRIPTION
4 * Pb1100 board setup 4 * Pb1100 board setup
5 * 5 *
6 * Copyright 2002 MontaVista Software Inc. 6 * Copyright 2002, 2008 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc. 7 * Author: MontaVista Software, Inc. <source@mvista.com>
8 * ppopov@mvista.com or source@mvista.com
9 * 8 *
10 * This program is free software; you can redistribute it and/or modify it 9 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the 10 * under the terms of the GNU General Public License as published by the
@@ -46,8 +45,8 @@ void __init prom_init(void)
46 unsigned long memsize; 45 unsigned long memsize;
47 46
48 prom_argc = fw_arg0; 47 prom_argc = fw_arg0;
49 prom_argv = (char **) fw_arg1; 48 prom_argv = (char **)fw_arg1;
50 prom_envp = (char **) fw_arg3; 49 prom_envp = (char **)fw_arg3;
51 50
52 prom_init_cmdline(); 51 prom_init_cmdline();
53 52
@@ -55,7 +54,7 @@ void __init prom_init(void)
55 if (!memsize_str) 54 if (!memsize_str)
56 memsize = 0x04000000; 55 memsize = 0x04000000;
57 else 56 else
58 memsize = simple_strtol(memsize_str, NULL, 0); 57 memsize = strict_strtol(memsize_str, 0, NULL);
59 58
60 add_memory_region(0, memsize, BOOT_MEM_RAM); 59 add_memory_region(0, memsize, BOOT_MEM_RAM);
61} 60}
diff --git a/arch/mips/au1000/pb1100/irqmap.c b/arch/mips/au1000/pb1100/irqmap.c
index b5021e3d477f..9b7dd8b41283 100644
--- a/arch/mips/au1000/pb1100/irqmap.c
+++ b/arch/mips/au1000/pb1100/irqmap.c
@@ -1,6 +1,6 @@
1/* 1/*
2 * BRIEF MODULE DESCRIPTION 2 * BRIEF MODULE DESCRIPTION
3 * Au1xxx irq map table 3 * Au1xx0 IRQ map table
4 * 4 *
5 * Copyright 2003 Embedded Edge, LLC 5 * Copyright 2003 Embedded Edge, LLC
6 * dan@embeddededge.com 6 * dan@embeddededge.com
@@ -31,10 +31,10 @@
31#include <asm/mach-au1x00/au1000.h> 31#include <asm/mach-au1x00/au1000.h>
32 32
33struct au1xxx_irqmap __initdata au1xxx_irq_map[] = { 33struct au1xxx_irqmap __initdata au1xxx_irq_map[] = {
34 { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card Fully_Interted# 34 { AU1000_GPIO_9, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card Fully_Inserted# */
35 { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card STSCHG# 35 { AU1000_GPIO_10, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card STSCHG# */
36 { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, // PCMCIA Card IRQ# 36 { AU1000_GPIO_11, INTC_INT_LOW_LEVEL, 0 }, /* PCMCIA Card IRQ# */
37 { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, // DC_IRQ# 37 { AU1000_GPIO_13, INTC_INT_LOW_LEVEL, 0 }, /* DC_IRQ# */
38}; 38};
39 39
40int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map); 40int __initdata au1xxx_nr_irqs = ARRAY_SIZE(au1xxx_irq_map);
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
index 63aa3926b297..b1a60f1cbd02 100644
--- a/include/asm-mips/mach-pb1x00/pb1100.h
+++ b/include/asm-mips/mach-pb1x00/pb1100.h
@@ -1,9 +1,8 @@
1/* 1/*
2 * Alchemy Semi PB1100 Referrence Board 2 * Alchemy Semi Pb1100 Referrence Board
3 * 3 *
4 * Copyright 2001 MontaVista Software Inc. 4 * Copyright 2001, 2008 MontaVista Software Inc.
5 * Author: MontaVista Software, Inc. 5 * Author: MontaVista Software, Inc. <source@mvista.com>
6 * ppopov@mvista.com or source@mvista.com
7 * 6 *
8 * ######################################################################## 7 * ########################################################################
9 * 8 *
@@ -27,59 +26,60 @@
27#ifndef __ASM_PB1100_H 26#ifndef __ASM_PB1100_H
28#define __ASM_PB1100_H 27#define __ASM_PB1100_H
29 28
30#define PB1100_IDENT 0xAE000000 29#define PB1100_IDENT 0xAE000000
31#define BOARD_STATUS_REG 0xAE000004 30#define BOARD_STATUS_REG 0xAE000004
32# define PB1100_ROM_SEL (1<<15) 31# define PB1100_ROM_SEL (1 << 15)
33# define PB1100_ROM_SIZ (1<<14) 32# define PB1100_ROM_SIZ (1 << 14)
34# define PB1100_SWAP_BOOT (1<<13) 33# define PB1100_SWAP_BOOT (1 << 13)
35# define PB1100_FLASH_WP (1<<12) 34# define PB1100_FLASH_WP (1 << 12)
36# define PB1100_ROM_H_STS (1<<11) 35# define PB1100_ROM_H_STS (1 << 11)
37# define PB1100_ROM_L_STS (1<<10) 36# define PB1100_ROM_L_STS (1 << 10)
38# define PB1100_FLASH_H_STS (1<<9) 37# define PB1100_FLASH_H_STS (1 << 9)
39# define PB1100_FLASH_L_STS (1<<8) 38# define PB1100_FLASH_L_STS (1 << 8)
40# define PB1100_SRAM_SIZ (1<<7) 39# define PB1100_SRAM_SIZ (1 << 7)
41# define PB1100_TSC_BUSY (1<<6) 40# define PB1100_TSC_BUSY (1 << 6)
42# define PB1100_PCMCIA_VS_MASK (3<<4) 41# define PB1100_PCMCIA_VS_MASK (3 << 4)
43# define PB1100_RS232_CD (1<<3) 42# define PB1100_RS232_CD (1 << 3)
44# define PB1100_RS232_CTS (1<<2) 43# define PB1100_RS232_CTS (1 << 2)
45# define PB1100_RS232_DSR (1<<1) 44# define PB1100_RS232_DSR (1 << 1)
46# define PB1100_RS232_RI (1<<0) 45# define PB1100_RS232_RI (1 << 0)
47 46
48#define PB1100_IRDA_RS232 0xAE00000C 47#define PB1100_IRDA_RS232 0xAE00000C
49# define PB1100_IRDA_FULL (0<<14) /* full power */ 48# define PB1100_IRDA_FULL (0 << 14) /* full power */
50# define PB1100_IRDA_SHUTDOWN (1<<14) 49# define PB1100_IRDA_SHUTDOWN (1 << 14)
51# define PB1100_IRDA_TT (2<<14) /* 2/3 power */ 50# define PB1100_IRDA_TT (2 << 14) /* 2/3 power */
52# define PB1100_IRDA_OT (3<<14) /* 1/3 power */ 51# define PB1100_IRDA_OT (3 << 14) /* 1/3 power */
53# define PB1100_IRDA_FIR (1<<13) 52# define PB1100_IRDA_FIR (1 << 13)
54 53
55#define PCMCIA_BOARD_REG 0xAE000010 54#define PCMCIA_BOARD_REG 0xAE000010
56# define PB1100_SD_WP1_RO (1<<15) /* read only */ 55# define PB1100_SD_WP1_RO (1 << 15) /* read only */
57# define PB1100_SD_WP0_RO (1<<14) /* read only */ 56# define PB1100_SD_WP0_RO (1 << 14) /* read only */
58# define PB1100_SD_PWR1 (1<<11) /* applies power to SD1 */ 57# define PB1100_SD_PWR1 (1 << 11) /* applies power to SD1 */
59# define PB1100_SD_PWR0 (1<<10) /* applies power to SD0 */ 58# define PB1100_SD_PWR0 (1 << 10) /* applies power to SD0 */
60# define PB1100_SEL_SD_CONN1 (1<<9) 59# define PB1100_SEL_SD_CONN1 (1 << 9)
61# define PB1100_SEL_SD_CONN0 (1<<8) 60# define PB1100_SEL_SD_CONN0 (1 << 8)
62# define PC_DEASSERT_RST (1<<7) 61# define PC_DEASSERT_RST (1 << 7)
63# define PC_DRV_EN (1<<4) 62# define PC_DRV_EN (1 << 4)
64 63
65#define PB1100_G_CONTROL 0xAE000014 /* graphics control */ 64#define PB1100_G_CONTROL 0xAE000014 /* graphics control */
66 65
67#define PB1100_RST_VDDI 0xAE00001C 66#define PB1100_RST_VDDI 0xAE00001C
68# define PB1100_SOFT_RESET (1<<15) /* clear to reset the board */ 67# define PB1100_SOFT_RESET (1 << 15) /* clear to reset the board */
69# define PB1100_VDDI_MASK (0x1F) 68# define PB1100_VDDI_MASK 0x1F
70 69
71#define PB1100_LEDS 0xAE000018 70#define PB1100_LEDS 0xAE000018
72 71
73/* 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED. 72/*
74 * 7:0 is the LED Display's decimal points. 73 * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
74 * 7:0 is the LED Display's decimal points.
75 */ 75 */
76#define PB1100_HEX_LED 0xAE000018 76#define PB1100_HEX_LED 0xAE000018
77 77
78/* PCMCIA PB1100 specific defines */ 78/* PCMCIA Pb1100 specific defines */
79#define PCMCIA_MAX_SOCK 0 79#define PCMCIA_MAX_SOCK 0
80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK+1) 80#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
81 81
82/* VPP/VCC */ 82/* VPP/VCC */
83#define SET_VCC_VPP(VCC, VPP) (((VCC)<<2) | ((VPP)<<0)) 83#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
84 84
85#endif /* __ASM_PB1100_H */ 85#endif /* __ASM_PB1100_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-04 23:11:52 -0500