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-rw-r--r--arch/arm/Kconfig5
-rw-r--r--arch/arm/Makefile1
-rw-r--r--arch/arm/mach-pxa/Makefile2
-rw-r--r--arch/arm/mach-pxa/include/mach/dma.h83
-rw-r--r--arch/arm/plat-pxa/Kconfig3
-rw-r--r--arch/arm/plat-pxa/Makefile6
-rw-r--r--arch/arm/plat-pxa/dma.c (renamed from arch/arm/mach-pxa/dma.c)6
-rw-r--r--arch/arm/plat-pxa/include/plat/dma.h85
8 files changed, 105 insertions, 86 deletions
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 12abdd43201f..5ba00358e805 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -481,6 +481,7 @@ config ARCH_PXA
481 select GENERIC_TIME 481 select GENERIC_TIME
482 select GENERIC_CLOCKEVENTS 482 select GENERIC_CLOCKEVENTS
483 select TICK_ONESHOT 483 select TICK_ONESHOT
484 select PLAT_PXA
484 help 485 help
485 Support for Intel/Marvell's PXA2xx/PXA3xx processor line. 486 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
486 487
@@ -618,6 +619,7 @@ source "arch/arm/mach-loki/Kconfig"
618source "arch/arm/mach-mv78xx0/Kconfig" 619source "arch/arm/mach-mv78xx0/Kconfig"
619 620
620source "arch/arm/mach-pxa/Kconfig" 621source "arch/arm/mach-pxa/Kconfig"
622source "arch/arm/plat-pxa/Kconfig"
621 623
622source "arch/arm/mach-sa1100/Kconfig" 624source "arch/arm/mach-sa1100/Kconfig"
623 625
@@ -687,6 +689,9 @@ config PLAT_IOP
687config PLAT_ORION 689config PLAT_ORION
688 bool 690 bool
689 691
692config PLAT_PXA
693 bool
694
690source arch/arm/mm/Kconfig 695source arch/arm/mm/Kconfig
691 696
692config IWMMXT 697config IWMMXT
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index e7ef876e574b..897f2830bc4d 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -109,6 +109,7 @@ ifeq ($(CONFIG_ARCH_SA1100),y)
109 textofs-$(CONFIG_SA1111) := 0x00208000 109 textofs-$(CONFIG_SA1111) := 0x00208000
110endif 110endif
111 machine-$(CONFIG_ARCH_PXA) := pxa 111 machine-$(CONFIG_ARCH_PXA) := pxa
112 plat-$(CONFIG_PLAT_PXA) := pxa
112 machine-$(CONFIG_ARCH_L7200) := l7200 113 machine-$(CONFIG_ARCH_L7200) := l7200
113 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator 114 machine-$(CONFIG_ARCH_INTEGRATOR) := integrator
114 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 115 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
diff --git a/arch/arm/mach-pxa/Makefile b/arch/arm/mach-pxa/Makefile
index fc96e7d454b1..70b46570c5cf 100644
--- a/arch/arm/mach-pxa/Makefile
+++ b/arch/arm/mach-pxa/Makefile
@@ -3,7 +3,7 @@
3# 3#
4 4
5# Common support (must be linked before board specific support) 5# Common support (must be linked before board specific support)
6obj-y += clock.o devices.o generic.o irq.o dma.o \ 6obj-y += clock.o devices.o generic.o irq.o \
7 time.o gpio.o reset.o 7 time.o gpio.o reset.o
8obj-$(CONFIG_PM) += pm.o sleep.o standby.o 8obj-$(CONFIG_PM) += pm.o sleep.o standby.o
9 9
diff --git a/arch/arm/mach-pxa/include/mach/dma.h b/arch/arm/mach-pxa/include/mach/dma.h
index b0812f59d3f8..5bd55894a48d 100644
--- a/arch/arm/mach-pxa/include/mach/dma.h
+++ b/arch/arm/mach-pxa/include/mach/dma.h
@@ -16,87 +16,6 @@
16 16
17/* DMA Controller Registers Definitions */ 17/* DMA Controller Registers Definitions */
18#define DMAC_REGS_VIRT io_p2v(0x40000000) 18#define DMAC_REGS_VIRT io_p2v(0x40000000)
19#define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
20
21#define DCSR(n) DMAC_REG((n) << 2)
22#define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */
23#define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */
24#define DDADR(n) DMAC_REG(0x0200 + ((n) << 4))
25#define DSADR(n) DMAC_REG(0x0204 + ((n) << 4))
26#define DTADR(n) DMAC_REG(0x0208 + ((n) << 4))
27#define DCMD(n) DMAC_REG(0x020c + ((n) << 4))
28#define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
29 (((n) & 0x3f) << 2))
30
31#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
32#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
33#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
34#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
35#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
36#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
37#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
38#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
39
40#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
41#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
42#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
43#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
44#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
45#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
46#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
47#define DCSR_EORINTR (1 << 9) /* The end of Receive */
48#endif
49
50#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
51#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
52
53#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
54#define DDADR_STOP (1 << 0) /* Stop (read / write) */
55
56#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
57#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
58#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
59#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
60#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
61#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
62#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
63#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
64#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
65#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
66#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
67#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
68#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
69#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
70
71/*
72 * Descriptor structure for PXA's DMA engine
73 * Note: this structure must always be aligned to a 16-byte boundary.
74 */
75
76typedef struct pxa_dma_desc {
77 volatile u32 ddadr; /* Points to the next descriptor + flags */
78 volatile u32 dsadr; /* DSADR value for the current transfer */
79 volatile u32 dtadr; /* DTADR value for the current transfer */
80 volatile u32 dcmd; /* DCMD value for the current transfer */
81} pxa_dma_desc;
82
83typedef enum {
84 DMA_PRIO_HIGH = 0,
85 DMA_PRIO_MEDIUM = 1,
86 DMA_PRIO_LOW = 2
87} pxa_dma_prio;
88
89/*
90 * DMA registration
91 */
92
93int __init pxa_init_dma(int irq, int num_ch);
94
95int pxa_request_dma (char *name,
96 pxa_dma_prio prio,
97 void (*irq_handler)(int, void *),
98 void *data);
99
100void pxa_free_dma (int dma_ch);
101 19
20#include <plat/dma.h>
102#endif /* _ASM_ARCH_DMA_H */ 21#endif /* _ASM_ARCH_DMA_H */
diff --git a/arch/arm/plat-pxa/Kconfig b/arch/arm/plat-pxa/Kconfig
new file mode 100644
index 000000000000..b158e98038ed
--- /dev/null
+++ b/arch/arm/plat-pxa/Kconfig
@@ -0,0 +1,3 @@
1if PLAT_PXA
2
3endif
diff --git a/arch/arm/plat-pxa/Makefile b/arch/arm/plat-pxa/Makefile
new file mode 100644
index 000000000000..dcc3ceaf717f
--- /dev/null
+++ b/arch/arm/plat-pxa/Makefile
@@ -0,0 +1,6 @@
1#
2# Makefile for code common across different PXA processor families
3#
4
5obj-y := dma.o
6
diff --git a/arch/arm/mach-pxa/dma.c b/arch/arm/plat-pxa/dma.c
index 01217e01f7d2..70aeee407f7d 100644
--- a/arch/arm/mach-pxa/dma.c
+++ b/arch/arm/plat-pxa/dma.c
@@ -1,5 +1,5 @@
1/* 1/*
2 * linux/arch/arm/mach-pxa/dma.c 2 * linux/arch/arm/plat-pxa/dma.c
3 * 3 *
4 * PXA DMA registration and IRQ dispatching 4 * PXA DMA registration and IRQ dispatching
5 * 5 *
@@ -34,8 +34,8 @@ static struct dma_channel *dma_channels;
34static int num_dma_channels; 34static int num_dma_channels;
35 35
36int pxa_request_dma (char *name, pxa_dma_prio prio, 36int pxa_request_dma (char *name, pxa_dma_prio prio,
37 void (*irq_handler)(int, void *), 37 void (*irq_handler)(int, void *),
38 void *data) 38 void *data)
39{ 39{
40 unsigned long flags; 40 unsigned long flags;
41 int i, found = 0; 41 int i, found = 0;
diff --git a/arch/arm/plat-pxa/include/plat/dma.h b/arch/arm/plat-pxa/include/plat/dma.h
new file mode 100644
index 000000000000..a7b91dc06852
--- /dev/null
+++ b/arch/arm/plat-pxa/include/plat/dma.h
@@ -0,0 +1,85 @@
1#ifndef __PLAT_DMA_H
2#define __PLAT_DMA_H
3
4#define DMAC_REG(x) (*((volatile u32 *)(DMAC_REGS_VIRT + (x))))
5
6#define DCSR(n) DMAC_REG((n) << 2)
7#define DALGN DMAC_REG(0x00a0) /* DMA Alignment Register */
8#define DINT DMAC_REG(0x00f0) /* DMA Interrupt Register */
9#define DDADR(n) DMAC_REG(0x0200 + ((n) << 4))
10#define DSADR(n) DMAC_REG(0x0204 + ((n) << 4))
11#define DTADR(n) DMAC_REG(0x0208 + ((n) << 4))
12#define DCMD(n) DMAC_REG(0x020c + ((n) << 4))
13#define DRCMR(n) DMAC_REG((((n) < 64) ? 0x0100 : 0x1100) + \
14 (((n) & 0x3f) << 2))
15
16#define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
17#define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
18#define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
19#define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
20#define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
21#define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
22#define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
23#define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
24
25#define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
26#define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
27#define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
28#define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
29#define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
30#define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
31#define DCSR_EORINTR (1 << 9) /* The end of Receive */
32
33#define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
34#define DRCMR_CHLNUM 0x1f /* mask for Channel Number (read / write) */
35
36#define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
37#define DDADR_STOP (1 << 0) /* Stop (read / write) */
38
39#define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
40#define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
41#define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
42#define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
43#define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
44#define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
45#define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
46#define DCMD_BURST8 (1 << 16) /* 8 byte burst */
47#define DCMD_BURST16 (2 << 16) /* 16 byte burst */
48#define DCMD_BURST32 (3 << 16) /* 32 byte burst */
49#define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
50#define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
51#define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
52#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
53
54/*
55 * Descriptor structure for PXA's DMA engine
56 * Note: this structure must always be aligned to a 16-byte boundary.
57 */
58
59typedef struct pxa_dma_desc {
60 volatile u32 ddadr; /* Points to the next descriptor + flags */
61 volatile u32 dsadr; /* DSADR value for the current transfer */
62 volatile u32 dtadr; /* DTADR value for the current transfer */
63 volatile u32 dcmd; /* DCMD value for the current transfer */
64} pxa_dma_desc;
65
66typedef enum {
67 DMA_PRIO_HIGH = 0,
68 DMA_PRIO_MEDIUM = 1,
69 DMA_PRIO_LOW = 2
70} pxa_dma_prio;
71
72/*
73 * DMA registration
74 */
75
76int __init pxa_init_dma(int irq, int num_ch);
77
78int pxa_request_dma (char *name,
79 pxa_dma_prio prio,
80 void (*irq_handler)(int, void *),
81 void *data);
82
83void pxa_free_dma (int dma_ch);
84
85#endif /* __PLAT_DMA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 23:34:34 -0500