diff options
| -rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 22 |
1 files changed, 5 insertions, 17 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index b0ab185b86f6..d3ca17080df7 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
| @@ -606,14 +606,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
| 606 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); | 606 | args.v1.usPixelClock = cpu_to_le16(mode->clock / 10); |
| 607 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; | 607 | args.v1.ucTransmitterID = radeon_encoder->encoder_id; |
| 608 | args.v1.ucEncodeMode = encoder_mode; | 608 | args.v1.ucEncodeMode = encoder_mode; |
| 609 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { | 609 | if (ss_enabled) |
| 610 | if (ss_enabled) | ||
| 611 | args.v1.ucConfig |= | ||
| 612 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; | ||
| 613 | } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) { | ||
| 614 | args.v1.ucConfig |= | 610 | args.v1.ucConfig |= |
| 615 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; | 611 | ADJUST_DISPLAY_CONFIG_SS_ENABLE; |
| 616 | } | ||
| 617 | 612 | ||
| 618 | atom_execute_table(rdev->mode_info.atom_context, | 613 | atom_execute_table(rdev->mode_info.atom_context, |
| 619 | index, (uint32_t *)&args); | 614 | index, (uint32_t *)&args); |
| @@ -624,12 +619,12 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
| 624 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; | 619 | args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id; |
| 625 | args.v3.sInput.ucEncodeMode = encoder_mode; | 620 | args.v3.sInput.ucEncodeMode = encoder_mode; |
| 626 | args.v3.sInput.ucDispPllConfig = 0; | 621 | args.v3.sInput.ucDispPllConfig = 0; |
| 622 | if (ss_enabled) | ||
| 623 | args.v3.sInput.ucDispPllConfig |= | ||
| 624 | DISPPLL_CONFIG_SS_ENABLE; | ||
| 627 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { | 625 | if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) { |
| 628 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; | 626 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
| 629 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { | 627 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { |
| 630 | if (ss_enabled) | ||
| 631 | args.v3.sInput.ucDispPllConfig |= | ||
| 632 | DISPPLL_CONFIG_SS_ENABLE; | ||
| 633 | args.v3.sInput.ucDispPllConfig |= | 628 | args.v3.sInput.ucDispPllConfig |= |
| 634 | DISPPLL_CONFIG_COHERENT_MODE; | 629 | DISPPLL_CONFIG_COHERENT_MODE; |
| 635 | /* 16200 or 27000 */ | 630 | /* 16200 or 27000 */ |
| @@ -649,18 +644,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
| 649 | } | 644 | } |
| 650 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { | 645 | } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { |
| 651 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { | 646 | if (encoder_mode == ATOM_ENCODER_MODE_DP) { |
| 652 | if (ss_enabled) | ||
| 653 | args.v3.sInput.ucDispPllConfig |= | ||
| 654 | DISPPLL_CONFIG_SS_ENABLE; | ||
| 655 | args.v3.sInput.ucDispPllConfig |= | 647 | args.v3.sInput.ucDispPllConfig |= |
| 656 | DISPPLL_CONFIG_COHERENT_MODE; | 648 | DISPPLL_CONFIG_COHERENT_MODE; |
| 657 | /* 16200 or 27000 */ | 649 | /* 16200 or 27000 */ |
| 658 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); | 650 | args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10); |
| 659 | } else if (encoder_mode == ATOM_ENCODER_MODE_LVDS) { | 651 | } else if (encoder_mode != ATOM_ENCODER_MODE_LVDS) { |
| 660 | if (ss_enabled) | ||
| 661 | args.v3.sInput.ucDispPllConfig |= | ||
| 662 | DISPPLL_CONFIG_SS_ENABLE; | ||
| 663 | } else { | ||
| 664 | if (mode->clock > 165000) | 652 | if (mode->clock > 165000) |
| 665 | args.v3.sInput.ucDispPllConfig |= | 653 | args.v3.sInput.ucDispPllConfig |= |
| 666 | DISPPLL_CONFIG_DUAL_LINK; | 654 | DISPPLL_CONFIG_DUAL_LINK; |
