aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
-rw-r--r--drivers/gpu/drm/radeon/cik.c17
-rw-r--r--drivers/gpu/drm/radeon/cikd.h1
2 files changed, 18 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e8544758b569..a2a30061172f 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -2714,6 +2714,23 @@ static void cik_gpu_init(struct radeon_device *rdev)
2714 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130; 2714 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
2715 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN; 2715 gb_addr_config = BONAIRE_GB_ADDR_CONFIG_GOLDEN;
2716 break; 2716 break;
2717 case CHIP_HAWAII:
2718 rdev->config.cik.max_shader_engines = 4;
2719 rdev->config.cik.max_tile_pipes = 16;
2720 rdev->config.cik.max_cu_per_sh = 11;
2721 rdev->config.cik.max_sh_per_se = 1;
2722 rdev->config.cik.max_backends_per_se = 4;
2723 rdev->config.cik.max_texture_channel_caches = 16;
2724 rdev->config.cik.max_gprs = 256;
2725 rdev->config.cik.max_gs_threads = 32;
2726 rdev->config.cik.max_hw_contexts = 8;
2727
2728 rdev->config.cik.sc_prim_fifo_size_frontend = 0x20;
2729 rdev->config.cik.sc_prim_fifo_size_backend = 0x100;
2730 rdev->config.cik.sc_hiz_tile_fifo_size = 0x30;
2731 rdev->config.cik.sc_earlyz_tile_fifo_size = 0x130;
2732 gb_addr_config = HAWAII_GB_ADDR_CONFIG_GOLDEN;
2733 break;
2717 case CHIP_KAVERI: 2734 case CHIP_KAVERI:
2718 rdev->config.cik.max_shader_engines = 1; 2735 rdev->config.cik.max_shader_engines = 1;
2719 rdev->config.cik.max_tile_pipes = 4; 2736 rdev->config.cik.max_tile_pipes = 4;
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h
index 380cea311a2b..aeb3d004431d 100644
--- a/drivers/gpu/drm/radeon/cikd.h
+++ b/drivers/gpu/drm/radeon/cikd.h
@@ -25,6 +25,7 @@
25#define CIK_H 25#define CIK_H
26 26
27#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001 27#define BONAIRE_GB_ADDR_CONFIG_GOLDEN 0x12010001
28#define HAWAII_GB_ADDR_CONFIG_GOLDEN 0x12011003
28 29
29#define CIK_RB_BITMAP_WIDTH_PER_SH 2 30#define CIK_RB_BITMAP_WIDTH_PER_SH 2
30 31