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| -rw-r--r-- | Documentation/parisc/registers | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/Documentation/parisc/registers b/Documentation/parisc/registers index dd3caddd1ad9..10c7d1730f5d 100644 --- a/Documentation/parisc/registers +++ b/Documentation/parisc/registers | |||
| @@ -78,6 +78,14 @@ Shadow Registers used by interruption handler code | |||
| 78 | TOC enable bit 1 | 78 | TOC enable bit 1 |
| 79 | 79 | ||
| 80 | ========================================================================= | 80 | ========================================================================= |
| 81 | |||
| 82 | The PA-RISC architecture defines 7 registers as "shadow registers". | ||
| 83 | Those are used in RETURN FROM INTERRUPTION AND RESTORE instruction to reduce | ||
| 84 | the state save and restore time by eliminating the need for general register | ||
| 85 | (GR) saves and restores in interruption handlers. | ||
| 86 | Shadow registers are the GRs 1, 8, 9, 16, 17, 24, and 25. | ||
| 87 | |||
| 88 | ========================================================================= | ||
| 81 | Register usage notes, originally from John Marvin, with some additional | 89 | Register usage notes, originally from John Marvin, with some additional |
| 82 | notes from Randolph Chung. | 90 | notes from Randolph Chung. |
| 83 | 91 | ||