263 files changed, 2919 insertions, 6559 deletions

diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
index 7f9fb85f5456..e7f4dc14eff2 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sunxi-ic.txt
+++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun4i-ic.txt
@@ -2,7 +2,7 @@ Allwinner Sunxi Interrupt Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sunxi-ic"
+- compatible : should be "allwinner,sun4i-ic"
 - reg : Specifies base physical address and size of the registers.
 - interrupt-controller : Identifies the node as an interrupt controller
 - #interrupt-cells : Specifies the number of cells needed to encode an
@@ -97,7 +97,7 @@ The interrupt sources are as follows:
 Example:
 
 intc: interrupt-controller {
-        compatible = "allwinner,sunxi-ic";
+        compatible = "allwinner,sun4i-ic";
         reg = <0x01c20400 0x400>;
         interrupt-controller;
         #interrupt-cells = <2>;
diff --git a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
index 0c7b64e95a61..48aeb7884ed3 100644
--- a/Documentation/devicetree/bindings/timer/allwinner,sunxi-timer.txt
+++ b/Documentation/devicetree/bindings/timer/allwinner,sun4i-timer.txt
@@ -2,7 +2,7 @@ Allwinner A1X SoCs Timer Controller
 
 Required properties:
 
-- compatible : should be "allwinner,sunxi-timer"
+- compatible : should be "allwinner,sun4i-timer"
 - reg : Specifies base physical address and size of the registers.
 - interrupts : The interrupt of the first timer
 - clocks: phandle to the source clock (usually a 24 MHz fixed clock)
@@ -10,7 +10,7 @@ Required properties:
 Example:
 
 timer {
-        compatible = "allwinner,sunxi-timer";
+        compatible = "allwinner,sun4i-timer";
         reg = <0x01c20c00 0x400>;
         interrupts = <22>;
         clocks = <&osc>;
diff --git a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt b/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt
index 0b2717775600..ecd650adff31 100644
--- a/Documentation/devicetree/bindings/watchdog/sunxi-wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/sun4i-wdt.txt
@@ -1,13 +1,13 @@
-Allwinner sunXi Watchdog timer
+Allwinner sun4i Watchdog timer
 
 Required properties:
 
-- compatible : should be "allwinner,sunxi-wdt"
+- compatible : should be "allwinner,sun4i-wdt"
 - reg : Specifies base physical address and size of the registers.
 
 Example:
 
 wdt: watchdog@01c20c90 {
-        compatible = "allwinner,sunxi-wdt";
+        compatible = "allwinner,sun4i-wdt";
         reg = <0x01c20c90 0x10>;
 };
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 006f9838dd43..7af7d1368942 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -411,6 +411,7 @@ config ARCH_GEMINI
         bool "Cortina Systems Gemini"
         select ARCH_REQUIRE_GPIOLIB
         select ARCH_USES_GETTIMEOFFSET
+        select NEED_MACH_GPIO_H
         select CPU_FA526
         help
           Support for the Cortina Systems Gemini family SoCs
@@ -474,12 +475,14 @@ config ARCH_MXS
         select ARCH_REQUIRE_GPIOLIB
         select CLKDEV_LOOKUP
         select CLKSRC_MMIO
+        select CLKSRC_OF
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select HAVE_CLK_PREPARE
         select MULTI_IRQ_HANDLER
         select PINCTRL
         select SPARSE_IRQ
+        select STMP_DEVICE
         select USE_OF
         help
           Support for Freescale MXS-based family of processors
@@ -493,14 +496,6 @@ config ARCH_NETX
         help
           This enables support for systems based on the Hilscher NetX Soc
 
-config ARCH_H720X
-        bool "Hynix HMS720x-based"
-        select ARCH_USES_GETTIMEOFFSET
-        select CPU_ARM720T
-        select ISA_DMA_API
-        help
-          This enables support for systems based on the Hynix HMS720x
-
 config ARCH_IOP13XX
         bool "IOP13xx-based"
         depends on MMU
@@ -1054,8 +1049,6 @@ source "arch/arm/mach-footbridge/Kconfig"
 
 source "arch/arm/mach-gemini/Kconfig"
 
-source "arch/arm/mach-h720x/Kconfig"
-
 source "arch/arm/mach-highbank/Kconfig"
 
 source "arch/arm/mach-integrator/Kconfig"
@@ -1176,7 +1169,6 @@ config PLAT_VERSATILE
 config ARM_TIMER_SP804
         bool
         select CLKSRC_MMIO
-        select HAVE_SCHED_CLOCK
 
 source arch/arm/mm/Kconfig
 
@@ -1606,6 +1598,7 @@ config HAVE_ARM_ARCH_TIMER
 config HAVE_ARM_TWD
         bool
         depends on SMP
+        select CLKSRC_OF if OF
         help
           This options enables support for the ARM timer and watchdog unit
 
@@ -2165,13 +2158,6 @@ menu "CPU Power Management"
 if ARCH_HAS_CPUFREQ
 source "drivers/cpufreq/Kconfig"
 
-config CPU_FREQ_IMX
-        tristate "CPUfreq driver for i.MX CPUs"
-        depends on ARCH_MXC && CPU_FREQ
-        select CPU_FREQ_TABLE
-        help
-          This enables the CPUfreq driver for i.MX CPUs.
-
 config CPU_FREQ_S3C
         bool
         help
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index ee4605f400b0..e4d1d23916b0 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -147,7 +147,6 @@ machine-$(CONFIG_ARCH_DOVE)		+= dove
 machine-$(CONFIG_ARCH_EBSA110)          += ebsa110
 machine-$(CONFIG_ARCH_EP93XX)           += ep93xx
 machine-$(CONFIG_ARCH_GEMINI)           += gemini
-machine-$(CONFIG_ARCH_H720X)            += h720x
 machine-$(CONFIG_ARCH_HIGHBANK)         += highbank
 machine-$(CONFIG_ARCH_INTEGRATOR)       += integrator
 machine-$(CONFIG_ARCH_IOP13XX)          += iop13xx
diff --git a/arch/arm/boot/dts/imx23.dtsi b/arch/arm/boot/dts/imx23.dtsi
index 56afcf41aae0..ad2d79324cd3 100644
--- a/arch/arm/boot/dts/imx23.dtsi
+++ b/arch/arm/boot/dts/imx23.dtsi
@@ -295,6 +295,7 @@
                         };
 
                         digctl@8001c000 {
+                                compatible = "fsl,imx23-digctl";
                                 reg = <0x8001c000 2000>;
                                 status = "disabled";
                         };
@@ -321,6 +322,7 @@
                         };
 
                         ocotp@8002c000 {
+                                compatible = "fsl,ocotp";
                                 reg = <0x8002c000 0x2000>;
                                 status = "disabled";
                         };
@@ -360,7 +362,7 @@
                         ranges;
 
                         clks: clkctrl@80040000 {
-                                compatible = "fsl,imx23-clkctrl";
+                                compatible = "fsl,imx23-clkctrl", "fsl,clkctrl";
                                 reg = <0x80040000 0x2000>;
                                 #clock-cells = <1>;
                         };
@@ -426,6 +428,7 @@
                                 compatible = "fsl,imx23-timrot", "fsl,timrot";
                                 reg = <0x80068000 0x2000>;
                                 interrupts = <28 29 30 31>;
+                                clocks = <&clks 28>;
                         };
 
                         auart0: serial@8006c000 {
diff --git a/arch/arm/boot/dts/imx28.dtsi b/arch/arm/boot/dts/imx28.dtsi
index 7ba49662b9bc..64af2381c1b0 100644
--- a/arch/arm/boot/dts/imx28.dtsi
+++ b/arch/arm/boot/dts/imx28.dtsi
@@ -647,6 +647,7 @@
                         };
 
                         digctl@8001c000 {
+                                compatible = "fsl,imx28-digctl";
                                 reg = <0x8001c000 0x2000>;
                                 interrupts = <89>;
                                 status = "disabled";
@@ -676,6 +677,7 @@
                         };
 
                         ocotp@8002c000 {
+                                compatible = "fsl,ocotp";
                                 reg = <0x8002c000 0x2000>;
                                 status = "disabled";
                         };
@@ -755,7 +757,7 @@
                         ranges;
 
                         clks: clkctrl@80040000 {
-                                compatible = "fsl,imx28-clkctrl";
+                                compatible = "fsl,imx28-clkctrl", "fsl,clkctrl";
                                 reg = <0x80040000 0x2000>;
                                 #clock-cells = <1>;
                         };
@@ -838,6 +840,7 @@
                                 compatible = "fsl,imx28-timrot", "fsl,timrot";
                                 reg = <0x80068000 0x2000>;
                                 interrupts = <48 49 50 51>;
+                                clocks = <&clks 26>;
                         };
 
                         auart0: serial@8006a000 {
diff --git a/arch/arm/boot/dts/tegra114.dtsi b/arch/arm/boot/dts/tegra114.dtsi
index 1dfaf2874c57..e4ddeddcd437 100644
--- a/arch/arm/boot/dts/tegra114.dtsi
+++ b/arch/arm/boot/dts/tegra114.dtsi
@@ -99,7 +99,7 @@
         };
 
         pmc {
-                compatible = "nvidia,tegra114-pmc", "nvidia,tegra30-pmc";
+                compatible = "nvidia,tegra114-pmc";
                 reg = <0x7000e400 0x400>;
         };
 
diff --git a/arch/arm/boot/dts/tegra20.dtsi b/arch/arm/boot/dts/tegra20.dtsi
index 3d3f64d2111a..ad64c8cc9da7 100644
--- a/arch/arm/boot/dts/tegra20.dtsi
+++ b/arch/arm/boot/dts/tegra20.dtsi
@@ -145,6 +145,7 @@
                               0 1 0x04
                               0 41 0x04
                               0 42 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
@@ -304,6 +305,7 @@
                 compatible = "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         i2c@7000c000 {
diff --git a/arch/arm/boot/dts/tegra30.dtsi b/arch/arm/boot/dts/tegra30.dtsi
index dbf46c272562..9491edf1a067 100644
--- a/arch/arm/boot/dts/tegra30.dtsi
+++ b/arch/arm/boot/dts/tegra30.dtsi
@@ -148,6 +148,7 @@
                               0 42 0x04
                               0 121 0x04
                               0 122 0x04>;
+                clocks = <&tegra_car 5>;
         };
 
         tegra_car: clock {
@@ -291,6 +292,7 @@
                 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
                 reg = <0x7000e000 0x100>;
                 interrupts = <0 2 0x04>;
+                clocks = <&tegra_car 4>;
         };
 
         i2c@7000c000 {
@@ -423,7 +425,7 @@
         };
 
         pmc {
-                compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
+                compatible = "nvidia,tegra30-pmc";
                 reg = <0x7000e400 0x400>;
         };
 
diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig
index 1ea959019fcd..047f2a415309 100644
--- a/arch/arm/configs/at91_dt_defconfig
+++ b/arch/arm/configs/at91_dt_defconfig
@@ -20,7 +20,7 @@ CONFIG_SOC_AT91SAM9263=y
 CONFIG_SOC_AT91SAM9G45=y
 CONFIG_SOC_AT91SAM9X5=y
 CONFIG_SOC_AT91SAM9N12=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_TIMER_HZ=128
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/at91sam9260_defconfig b/arch/arm/configs/at91sam9260_defconfig
index 0ea5d2c97fc4..05618eb694f8 100644
--- a/arch/arm/configs/at91sam9260_defconfig
+++ b/arch/arm/configs/at91sam9260_defconfig
@@ -22,7 +22,7 @@ CONFIG_MACH_QIL_A9260=y
 CONFIG_MACH_CPU9260=y
 CONFIG_MACH_FLEXIBITY=y
 CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_ZBOOT_ROM_TEXT=0x0
diff --git a/arch/arm/configs/at91sam9g20_defconfig b/arch/arm/configs/at91sam9g20_defconfig
index 3b1881033ad8..892e8287ed73 100644
--- a/arch/arm/configs/at91sam9g20_defconfig
+++ b/arch/arm/configs/at91sam9g20_defconfig
@@ -22,7 +22,7 @@ CONFIG_MACH_PCONTROL_G20=y
 CONFIG_MACH_GSIA18S=y
 CONFIG_MACH_USB_A9G20=y
 CONFIG_MACH_SNAPPER_9260=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 # CONFIG_ARM_THUMB is not set
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/at91sam9g45_defconfig b/arch/arm/configs/at91sam9g45_defconfig
index 606d48f3b8f8..5f551b76cb65 100644
--- a/arch/arm/configs/at91sam9g45_defconfig
+++ b/arch/arm/configs/at91sam9g45_defconfig
@@ -18,7 +18,7 @@ CONFIG_MODULE_UNLOAD=y
 CONFIG_ARCH_AT91=y
 CONFIG_ARCH_AT91SAM9G45=y
 CONFIG_MACH_AT91SAM9M10G45EK=y
-CONFIG_MACH_AT91SAM_DT=y
+CONFIG_MACH_AT91SAM9_DT=y
 CONFIG_AT91_PROGRAMMABLE_CLOCKS=y
 CONFIG_AT91_SLOW_CLOCK=y
 CONFIG_AEABI=y
diff --git a/arch/arm/configs/h7201_defconfig b/arch/arm/configs/h7201_defconfig
deleted file mode 100644
index bee94d29655e..000000000000
--- a/arch/arm/configs/h7201_defconfig
+++ /dev/null
@@ -1,27 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_BLK_DEV_INITRD=y
-CONFIG_MODULES=y
-CONFIG_ARCH_H720X=y
-CONFIG_ARCH_H7201=y
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_FPE_NWFPE=y
-CONFIG_MTD=y
-CONFIG_MTD_DEBUG=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_ADV_OPTIONS=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_BLK_DEV_RAM=y
-CONFIG_BLK_DEV_RAM_SIZE=8192
-# CONFIG_INPUT_KEYBOARD is not set
-# CONFIG_INPUT_MOUSE is not set
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_SOUND=m
-CONFIG_EXT2_FS=y
-CONFIG_JFFS2_FS=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/configs/h7202_defconfig b/arch/arm/configs/h7202_defconfig
deleted file mode 100644
index e16d3f372e2a..000000000000
--- a/arch/arm/configs/h7202_defconfig
+++ /dev/null
@@ -1,47 +0,0 @@
-CONFIG_EXPERIMENTAL=y
-CONFIG_SYSVIPC=y
-CONFIG_LOG_BUF_SHIFT=14
-CONFIG_MODULES=y
-CONFIG_ARCH_H720X=y
-CONFIG_ARCH_H7202=y
-# CONFIG_ARM_THUMB is not set
-CONFIG_ZBOOT_ROM_TEXT=0x0
-CONFIG_ZBOOT_ROM_BSS=0x0
-CONFIG_CMDLINE="console=ttyS0,19200"
-CONFIG_FPE_NWFPE=y
-CONFIG_FPE_NWFPE_XP=y
-CONFIG_NET=y
-CONFIG_UNIX=y
-CONFIG_INET=y
-CONFIG_IP_PNP=y
-CONFIG_IP_PNP_BOOTP=y
-# CONFIG_IPV6 is not set
-CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_MTD_CMDLINE_PARTS=y
-CONFIG_MTD_CHAR=y
-CONFIG_MTD_BLOCK=y
-CONFIG_MTD_CFI=y
-CONFIG_MTD_CFI_INTELEXT=y
-CONFIG_MTD_H720X=y
-CONFIG_NETDEVICES=y
-CONFIG_NET_ETHERNET=y
-CONFIG_SERIAL_8250=y
-CONFIG_SERIAL_8250_CONSOLE=y
-CONFIG_FB=y
-CONFIG_FB_MODE_HELPERS=y
-# CONFIG_VGA_CONSOLE is not set
-CONFIG_USB_GADGET=m
-CONFIG_USB_ZERO=m
-CONFIG_USB_GADGETFS=m
-CONFIG_USB_MASS_STORAGE=m
-CONFIG_USB_G_SERIAL=m
-CONFIG_EXT2_FS=y
-CONFIG_TMPFS=y
-CONFIG_JFFS2_FS=y
-CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
-CONFIG_MAGIC_SYSRQ=y
-CONFIG_DEBUG_KERNEL=y
-CONFIG_DEBUG_INFO=y
-CONFIG_DEBUG_USER=y
diff --git a/arch/arm/include/asm/irq.h b/arch/arm/include/asm/irq.h
index 35c21c375d81..53c15dec7af6 100644
--- a/arch/arm/include/asm/irq.h
+++ b/arch/arm/include/asm/irq.h
@@ -30,6 +30,11 @@ extern void asm_do_IRQ(unsigned int, struct pt_regs *);
 void handle_IRQ(unsigned int, struct pt_regs *);
 void init_IRQ(void);
 
+#ifdef CONFIG_MULTI_IRQ_HANDLER
+extern void (*handle_arch_irq)(struct pt_regs *);
+extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
+#endif
+
 #endif
 
 #endif
diff --git a/arch/arm/include/asm/mach/irq.h b/arch/arm/include/asm/mach/irq.h
index 18c883023339..2092ee1e1300 100644
--- a/arch/arm/include/asm/mach/irq.h
+++ b/arch/arm/include/asm/mach/irq.h
@@ -20,11 +20,6 @@ struct seq_file;
 extern void init_FIQ(int);
 extern int show_fiq_list(struct seq_file *, int);
 
-#ifdef CONFIG_MULTI_IRQ_HANDLER
-extern void (*handle_arch_irq)(struct pt_regs *);
-extern void set_handle_irq(void (*handle_irq)(struct pt_regs *));
-#endif
-
 /*
  * This is for easy migration, but should be changed in the source
  */
@@ -35,35 +30,4 @@ do {							\
         raw_spin_unlock(&desc->lock);                   \
 } while(0)
 
-#ifndef __ASSEMBLY__
-/*
- * Entry/exit functions for chained handlers where the primary IRQ chip
- * may implement either fasteoi or level-trigger flow control.
- */
-static inline void chained_irq_enter(struct irq_chip *chip,
-                                     struct irq_desc *desc)
-{
-        /* FastEOI controllers require no action on entry. */
-        if (chip->irq_eoi)
-                return;
-
-        if (chip->irq_mask_ack) {
-                chip->irq_mask_ack(&desc->irq_data);
-        } else {
-                chip->irq_mask(&desc->irq_data);
-                if (chip->irq_ack)
-                        chip->irq_ack(&desc->irq_data);
-        }
-}
-
-static inline void chained_irq_exit(struct irq_chip *chip,
-                                    struct irq_desc *desc)
-{
-        if (chip->irq_eoi)
-                chip->irq_eoi(&desc->irq_data);
-        else
-                chip->irq_unmask(&desc->irq_data);
-}
-#endif
-
 #endif
diff --git a/arch/arm/include/asm/smp_twd.h b/arch/arm/include/asm/smp_twd.h
index 0f01f4677bd2..7b2899c2f7fc 100644
--- a/arch/arm/include/asm/smp_twd.h
+++ b/arch/arm/include/asm/smp_twd.h
@@ -34,12 +34,4 @@ struct twd_local_timer name __initdata = {	\
 
 int twd_local_timer_register(struct twd_local_timer *);
 
-#ifdef CONFIG_HAVE_ARM_TWD
-void twd_local_timer_of_register(void);
-#else
-static inline void twd_local_timer_of_register(void)
-{
-}
-#endif
-
 #endif
diff --git a/arch/arm/kernel/irq.c b/arch/arm/kernel/irq.c
index 8e4ef4c83a74..9723d17b8f38 100644
--- a/arch/arm/kernel/irq.c
+++ b/arch/arm/kernel/irq.c
@@ -26,6 +26,7 @@
 #include <linux/ioport.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip.h>
 #include <linux/random.h>
 #include <linux/smp.h>
 #include <linux/init.h>
@@ -114,7 +115,10 @@ EXPORT_SYMBOL_GPL(set_irq_flags);
 
 void __init init_IRQ(void)
 {
-        machine_desc->init_irq();
+        if (IS_ENABLED(CONFIG_OF) && !machine_desc->init_irq)
+                irqchip_init();
+        else
+                machine_desc->init_irq();
 }
 
 #ifdef CONFIG_MULTI_IRQ_HANDLER
diff --git a/arch/arm/kernel/smp_twd.c b/arch/arm/kernel/smp_twd.c
index 3f2565037480..90525d9d290b 100644
--- a/arch/arm/kernel/smp_twd.c
+++ b/arch/arm/kernel/smp_twd.c
@@ -362,25 +362,13 @@ int __init twd_local_timer_register(struct twd_local_timer *tlt)
 }
 
 #ifdef CONFIG_OF
-const static struct of_device_id twd_of_match[] __initconst = {
-        { .compatible = "arm,cortex-a9-twd-timer",      },
-        { .compatible = "arm,cortex-a5-twd-timer",      },
-        { .compatible = "arm,arm11mp-twd-timer",        },
-        { },
-};
-
-void __init twd_local_timer_of_register(void)
+static void __init twd_local_timer_of_register(struct device_node *np)
 {
-        struct device_node *np;
         int err;
 
         if (!is_smp() || !setup_max_cpus)
                 return;
 
-        np = of_find_matching_node(NULL, twd_of_match);
-        if (!np)
-                return;
-
         twd_ppi = irq_of_parse_and_map(np, 0);
         if (!twd_ppi) {
                 err = -EINVAL;
@@ -398,4 +386,7 @@ void __init twd_local_timer_of_register(void)
 out:
         WARN(err, "twd_local_timer_of_register failed (%d)\n", err);
 }
+CLOCKSOURCE_OF_DECLARE(arm_twd_a9, "arm,cortex-a9-twd-timer", twd_local_timer_of_register);
+CLOCKSOURCE_OF_DECLARE(arm_twd_a5, "arm,cortex-a5-twd-timer", twd_local_timer_of_register);
+CLOCKSOURCE_OF_DECLARE(arm_twd_11mp, "arm,arm11mp-twd-timer", twd_local_timer_of_register);
 #endif
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 6071f4c3d654..440682b708f3 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -1,8 +1,5 @@
 if ARCH_AT91
 
-config HAVE_AT91_DATAFLASH_CARD
-        bool
-
 config HAVE_AT91_DBGU0
         bool
 
@@ -93,394 +90,13 @@ config SOC_AT91SAM9N12
         help
           Select this if you are using Atmel's AT91SAM9N12 SoC.
 
-choice
-        prompt "Atmel AT91 Processor Devices for non DT boards"
-
-config ARCH_AT91_NONE
-        bool "None"
-
-config ARCH_AT91RM9200
-        bool "AT91RM9200"
-        select SOC_AT91RM9200
-
-config ARCH_AT91SAM9260
-        bool "AT91SAM9260 or AT91SAM9XE"
-        select SOC_AT91SAM9260
-
-config ARCH_AT91SAM9261
-        bool "AT91SAM9261"
-        select SOC_AT91SAM9261
-
-config ARCH_AT91SAM9G10
-        bool "AT91SAM9G10"
-        select SOC_AT91SAM9261
-
-config ARCH_AT91SAM9263
-        bool "AT91SAM9263"
-        select SOC_AT91SAM9263
-
-config ARCH_AT91SAM9RL
-        bool "AT91SAM9RL"
-        select SOC_AT91SAM9RL
-
-config ARCH_AT91SAM9G20
-        bool "AT91SAM9G20"
-        select SOC_AT91SAM9260
-
-config ARCH_AT91SAM9G45
-        bool "AT91SAM9G45"
-        select SOC_AT91SAM9G45
-
-config ARCH_AT91X40
-        bool "AT91x40"
-        depends on !MMU
-        select ARCH_USES_GETTIMEOFFSET
-        select MULTI_IRQ_HANDLER
-        select SPARSE_IRQ
-
-endchoice
-
 config AT91_PMC_UNIT
         bool
         default !ARCH_AT91X40
 
 # ----------------------------------------------------------
 
-if ARCH_AT91RM9200
-
-comment "AT91RM9200 Board Type"
-
-config MACH_ONEARM
-        bool "Ajeco 1ARM Single Board Computer"
-        help
-          Select this if you are using Ajeco's 1ARM Single Board Computer.
-          <http://www.ajeco.fi/>
-
-config ARCH_AT91RM9200DK
-        bool "Atmel AT91RM9200-DK Development board"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91RM9200-DK Development board.
-          (Discontinued)
-
-config MACH_AT91RM9200EK
-        bool "Atmel AT91RM9200-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
-
-config MACH_CSB337
-        bool "Cogent CSB337"
-        help
-          Select this if you are using Cogent's CSB337 board.
-          <http://www.cogcomp.com/csb_csb337.htm>
-
-config MACH_CSB637
-        bool "Cogent CSB637"
-        help
-          Select this if you are using Cogent's CSB637 board.
-          <http://www.cogcomp.com/csb_csb637.htm>
-
-config MACH_CARMEVA
-        bool "Conitec ARM&EVA"
-        help
-          Select this if you are using Conitec's AT91RM9200-MCU-Module.
-          <http://www.conitec.net/english/linuxboard.php>
-
-config MACH_ATEB9200
-        bool "Embest ATEB9200"
-        help
-          Select this if you are using Embest's ATEB9200 board.
-          <http://www.embedinfo.com/english/product/ATEB9200.asp>
-
-config MACH_KB9200
-        bool "KwikByte KB920x"
-        help
-          Select this if you are using KwikByte's KB920x board.
-          <http://www.kwikbyte.com/KB9202.html>
-
-config MACH_PICOTUX2XX
-        bool "picotux 200"
-        help
-          Select this if you are using a picotux 200.
-          <http://www.picotux.com/>
-
-config MACH_KAFA
-        bool "Sperry-Sun KAFA board"
-        help
-          Select this if you are using Sperry-Sun's KAFA board.
-
-config MACH_ECBAT91
-        bool "emQbit ECB_AT91 SBC"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using emQbit's ECB_AT91 board.
-          <http://wiki.emqbit.com/free-ecb-at91>
-
-config MACH_YL9200
-        bool "ucDragon YL-9200"
-        help
-          Select this if you are using the ucDragon YL-9200 board.
-
-config MACH_CPUAT91
-        bool "Eukrea CPUAT91"
-        help
-          Select this if you are using the Eukrea Electromatique's
-          CPUAT91 board <http://www.eukrea.com/>.
-
-config MACH_ECO920
-        bool "eco920"
-        help
-          Select this if you are using the eco920 board
-
-config MACH_RSI_EWS
-        bool "RSI Embedded Webserver"
-        depends on ARCH_AT91RM9200
-        help
-          Select this if you are using RSIs EWS board.
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9260
-
-comment "AT91SAM9260 Variants"
-
-comment "AT91SAM9260 / AT91SAM9XE Board Type"
-
-config MACH_AT91SAM9260EK
-        bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
-
-config MACH_CAM60
-        bool "KwikByte KB9260 (CAM60) board"
-        help
-          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
-          <http://www.kwikbyte.com/KB9260.html>
-
-config MACH_SAM9_L9260
-        bool "Olimex SAM9-L9260 board"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
-          <http://www.olimex.com/dev/sam9-L9260.html>
-
-config MACH_AFEB9260
-        bool "Custom afeb9260 board v1"
-        help
-          Select this if you are using custom afeb9260 board based on
-          open hardware design. Select this for revision 1 of the board.
-          <svn://194.85.238.22/home/users/george/svn/arm9eb>
-          <http://groups.google.com/group/arm9fpga-evolution-board>
-
-config MACH_USB_A9260
-        bool "CALAO USB-A9260"
-        help
-          Select this if you are using a Calao Systems USB-A9260.
-          <http://www.calao-systems.com>
-
-config MACH_QIL_A9260
-        bool "CALAO QIL-A9260 board"
-        help
-          Select this if you are using a Calao Systems QIL-A9260 Board.
-          <http://www.calao-systems.com>
-
-config MACH_CPU9260
-        bool "Eukrea CPU9260 board"
-        help
-          Select this if you are using a Eukrea Electromatique's
-          CPU9260 Board <http://www.eukrea.com/>
-
-config MACH_FLEXIBITY
-        bool "Flexibity Connect board"
-        help
-          Select this if you are using Flexibity Connect board
-          <http://www.flexibity.com>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9261
-
-comment "AT91SAM9261 Board Type"
-
-config MACH_AT91SAM9261EK
-        bool "Atmel AT91SAM9261-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G10
-
-comment "AT91SAM9G10 Board Type"
-
-config MACH_AT91SAM9G10EK
-        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9263
-
-comment "AT91SAM9263 Board Type"
-
-config MACH_AT91SAM9263EK
-        bool "Atmel AT91SAM9263-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
-          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
-
-config MACH_USB_A9263
-        bool "CALAO USB-A9263"
-        help
-          Select this if you are using a Calao Systems USB-A9263.
-          <http://www.calao-systems.com>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9RL
-
-comment "AT91SAM9RL Board Type"
-
-config MACH_AT91SAM9RLEK
-        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G20
-
-comment "AT91SAM9G20 Board Type"
-
-config MACH_AT91SAM9G20EK
-        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
-        select HAVE_AT91_DATAFLASH_CARD
-        help
-          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
-          that embeds only one SD/MMC slot.
-
-config MACH_AT91SAM9G20EK_2MMC
-        depends on MACH_AT91SAM9G20EK
-        bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
-        help
-          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
-          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
-          onwards.
-          <http://www.atmel.com/tools/SAM9G20-EK.aspx>
-
-config MACH_CPU9G20
-        bool "Eukrea CPU9G20 board"
-        help
-          Select this if you are using a Eukrea Electromatique's
-          CPU9G20 Board <http://www.eukrea.com/>
-
-config MACH_ACMENETUSFOXG20
-        bool "Acme Systems srl FOX Board G20"
-        help
-          Select this if you are using Acme Systems
-          FOX Board G20 <http://www.acmesystems.it>
-
-config MACH_PORTUXG20
-        bool "taskit PortuxG20"
-        help
-          Select this if you are using taskit's PortuxG20.
-          <http://www.taskit.de/en/>
-
-config MACH_STAMP9G20
-        bool "taskit Stamp9G20 CPU module"
-        help
-          Select this if you are using taskit's Stamp9G20 CPU module on its
-          evaluation board.
-          <http://www.taskit.de/en/>
-
-config MACH_PCONTROL_G20
-        bool "PControl G20 CPU module"
-        help
-          Select this if you are using taskit's Stamp9G20 CPU module on this
-          carrier board, beeing the decentralized unit of a building automation
-          system; featuring nvram, eth-switch, iso-rs485, display, io
-
-config MACH_GSIA18S
-        bool "GS_IA18_S board"
-        help
-          This enables support for the GS_IA18_S board
-          produced by GeoSIG Ltd company. This is an internet accelerograph.
-          <http://www.geosig.com>
-
-config MACH_USB_A9G20
-        bool "CALAO USB-A9G20"
-        depends on ARCH_AT91SAM9G20
-        help
-          Select this if you are using a Calao Systems USB-A9G20.
-          <http://www.calao-systems.com>
-
-endif
-
-if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
-comment "AT91SAM9260/AT91SAM9G20 boards"
-
-config MACH_SNAPPER_9260
-        bool "Bluewater Systems Snapper 9260/9G20 module"
-        help
-          Select this if you are using the Bluewater Systems Snapper 9260 or
-          Snapper 9G20 modules.
-          <http://www.bluewatersys.com/>
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91SAM9G45
-
-comment "AT91SAM9G45 Board Type"
-
-config MACH_AT91SAM9M10G45EK
-        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
-        help
-          Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
-          Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
-          families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
-          <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
-
-endif
-
-# ----------------------------------------------------------
-
-if ARCH_AT91X40
-
-comment "AT91X40 Board Type"
-
-config MACH_AT91EB01
-        bool "Atmel AT91EB01 Evaluation Kit"
-        help
-          Select this if you are using Atmel's AT91EB01 Evaluation Kit.
-          It is also a popular target for simulators such as GDB's
-          ARM simulator (commonly known as the ARMulator) and the
-          Skyeye simulator.
-
-endif
-
-# ----------------------------------------------------------
+source arch/arm/mach-at91/Kconfig.non_dt
 
 comment "Generic Board Type"
 
@@ -492,7 +108,7 @@ config MACH_AT91RM9200_DT
           Select this if you want to experiment device-tree with
           an Atmel RM9200 Evaluation Kit.
 
-config MACH_AT91SAM_DT
+config MACH_AT91SAM9_DT
         bool "Atmel AT91SAM Evaluation Kits with device-tree support"
         depends on SOC_AT91SAM9
         select USE_OF
@@ -502,16 +118,6 @@ config MACH_AT91SAM_DT
 
 # ----------------------------------------------------------
 
-comment "AT91 Board Options"
-
-config MTD_AT91_DATAFLASH_CARD
-        bool "Enable DataFlash Card support"
-        depends on HAVE_AT91_DATAFLASH_CARD
-        help
-          Enable support for the DataFlash card.
-
-# ----------------------------------------------------------
-
 comment "AT91 Feature Selections"
 
 config AT91_PROGRAMMABLE_CLOCKS
diff --git a/arch/arm/mach-at91/Kconfig.non_dt b/arch/arm/mach-at91/Kconfig.non_dt
new file mode 100644
index 000000000000..6c24985515a2
--- /dev/null
+++ b/arch/arm/mach-at91/Kconfig.non_dt
@@ -0,0 +1,399 @@
+menu "Atmel Non-DT world"
+
+config HAVE_AT91_DATAFLASH_CARD
+        bool
+
+choice
+        prompt "Atmel AT91 Processor Devices for non DT boards"
+
+config ARCH_AT91_NONE
+        bool "None"
+
+config ARCH_AT91RM9200
+        bool "AT91RM9200"
+        select SOC_AT91RM9200
+
+config ARCH_AT91SAM9260
+        bool "AT91SAM9260 or AT91SAM9XE"
+        select SOC_AT91SAM9260
+
+config ARCH_AT91SAM9261
+        bool "AT91SAM9261"
+        select SOC_AT91SAM9261
+
+config ARCH_AT91SAM9G10
+        bool "AT91SAM9G10"
+        select SOC_AT91SAM9261
+
+config ARCH_AT91SAM9263
+        bool "AT91SAM9263"
+        select SOC_AT91SAM9263
+
+config ARCH_AT91SAM9RL
+        bool "AT91SAM9RL"
+        select SOC_AT91SAM9RL
+
+config ARCH_AT91SAM9G20
+        bool "AT91SAM9G20"
+        select SOC_AT91SAM9260
+
+config ARCH_AT91SAM9G45
+        bool "AT91SAM9G45"
+        select SOC_AT91SAM9G45
+
+config ARCH_AT91X40
+        bool "AT91x40"
+        depends on !MMU
+        select ARCH_USES_GETTIMEOFFSET
+        select MULTI_IRQ_HANDLER
+        select SPARSE_IRQ
+
+endchoice
+
+# ----------------------------------------------------------
+
+if ARCH_AT91RM9200
+
+comment "AT91RM9200 Board Type"
+
+config MACH_ONEARM
+        bool "Ajeco 1ARM Single Board Computer"
+        help
+          Select this if you are using Ajeco's 1ARM Single Board Computer.
+          <http://www.ajeco.fi/>
+
+config ARCH_AT91RM9200DK
+        bool "Atmel AT91RM9200-DK Development board"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91RM9200-DK Development board.
+          (Discontinued)
+
+config MACH_AT91RM9200EK
+        bool "Atmel AT91RM9200-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91RM9200-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3507>
+
+config MACH_CSB337
+        bool "Cogent CSB337"
+        help
+          Select this if you are using Cogent's CSB337 board.
+          <http://www.cogcomp.com/csb_csb337.htm>
+
+config MACH_CSB637
+        bool "Cogent CSB637"
+        help
+          Select this if you are using Cogent's CSB637 board.
+          <http://www.cogcomp.com/csb_csb637.htm>
+
+config MACH_CARMEVA
+        bool "Conitec ARM&EVA"
+        help
+          Select this if you are using Conitec's AT91RM9200-MCU-Module.
+          <http://www.conitec.net/english/linuxboard.php>
+
+config MACH_ATEB9200
+        bool "Embest ATEB9200"
+        help
+          Select this if you are using Embest's ATEB9200 board.
+          <http://www.embedinfo.com/english/product/ATEB9200.asp>
+
+config MACH_KB9200
+        bool "KwikByte KB920x"
+        help
+          Select this if you are using KwikByte's KB920x board.
+          <http://www.kwikbyte.com/KB9202.html>
+
+config MACH_PICOTUX2XX
+        bool "picotux 200"
+        help
+          Select this if you are using a picotux 200.
+          <http://www.picotux.com/>
+
+config MACH_KAFA
+        bool "Sperry-Sun KAFA board"
+        help
+          Select this if you are using Sperry-Sun's KAFA board.
+
+config MACH_ECBAT91
+        bool "emQbit ECB_AT91 SBC"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using emQbit's ECB_AT91 board.
+          <http://wiki.emqbit.com/free-ecb-at91>
+
+config MACH_YL9200
+        bool "ucDragon YL-9200"
+        help
+          Select this if you are using the ucDragon YL-9200 board.
+
+config MACH_CPUAT91
+        bool "Eukrea CPUAT91"
+        help
+          Select this if you are using the Eukrea Electromatique's
+          CPUAT91 board <http://www.eukrea.com/>.
+
+config MACH_ECO920
+        bool "eco920"
+        help
+          Select this if you are using the eco920 board
+
+config MACH_RSI_EWS
+        bool "RSI Embedded Webserver"
+        depends on ARCH_AT91RM9200
+        help
+          Select this if you are using RSIs EWS board.
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9260
+
+comment "AT91SAM9260 Variants"
+
+comment "AT91SAM9260 / AT91SAM9XE Board Type"
+
+config MACH_AT91SAM9260EK
+        bool "Atmel AT91SAM9260-EK / AT91SAM9XE Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9260-EK or AT91SAM9XE Evaluation Kit
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933>
+
+config MACH_CAM60
+        bool "KwikByte KB9260 (CAM60) board"
+        help
+          Select this if you are using KwikByte's KB9260 (CAM60) board based on the Atmel AT91SAM9260.
+          <http://www.kwikbyte.com/KB9260.html>
+
+config MACH_SAM9_L9260
+        bool "Olimex SAM9-L9260 board"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Olimex's SAM9-L9260 board based on the Atmel AT91SAM9260.
+          <http://www.olimex.com/dev/sam9-L9260.html>
+
+config MACH_AFEB9260
+        bool "Custom afeb9260 board v1"
+        help
+          Select this if you are using custom afeb9260 board based on
+          open hardware design. Select this for revision 1 of the board.
+          <svn://194.85.238.22/home/users/george/svn/arm9eb>
+          <http://groups.google.com/group/arm9fpga-evolution-board>
+
+config MACH_USB_A9260
+        bool "CALAO USB-A9260"
+        help
+          Select this if you are using a Calao Systems USB-A9260.
+          <http://www.calao-systems.com>
+
+config MACH_QIL_A9260
+        bool "CALAO QIL-A9260 board"
+        help
+          Select this if you are using a Calao Systems QIL-A9260 Board.
+          <http://www.calao-systems.com>
+
+config MACH_CPU9260
+        bool "Eukrea CPU9260 board"
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9260 Board <http://www.eukrea.com/>
+
+config MACH_FLEXIBITY
+        bool "Flexibity Connect board"
+        help
+          Select this if you are using Flexibity Connect board
+          <http://www.flexibity.com>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9261
+
+comment "AT91SAM9261 Board Type"
+
+config MACH_AT91SAM9261EK
+        bool "Atmel AT91SAM9261-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9261-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3820>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G10
+
+comment "AT91SAM9G10 Board Type"
+
+config MACH_AT91SAM9G10EK
+        bool "Atmel AT91SAM9G10-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9G10-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4588>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9263
+
+comment "AT91SAM9263 Board Type"
+
+config MACH_AT91SAM9263EK
+        bool "Atmel AT91SAM9263-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9263-EK Evaluation Kit.
+          <http://www.atmel.com/dyn/products/tools_card.asp?tool_id=4057>
+
+config MACH_USB_A9263
+        bool "CALAO USB-A9263"
+        help
+          Select this if you are using a Calao Systems USB-A9263.
+          <http://www.calao-systems.com>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9RL
+
+comment "AT91SAM9RL Board Type"
+
+config MACH_AT91SAM9RLEK
+        bool "Atmel AT91SAM9RL-EK Evaluation Kit"
+        help
+          Select this if you are using Atmel's AT91SAM9RL-EK Evaluation Kit.
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G20
+
+comment "AT91SAM9G20 Board Type"
+
+config MACH_AT91SAM9G20EK
+        bool "Atmel AT91SAM9G20-EK Evaluation Kit"
+        select HAVE_AT91_DATAFLASH_CARD
+        help
+          Select this if you are using Atmel's AT91SAM9G20-EK Evaluation Kit
+          that embeds only one SD/MMC slot.
+
+config MACH_AT91SAM9G20EK_2MMC
+        depends on MACH_AT91SAM9G20EK
+        bool "Atmel AT91SAM9G20-EK Evaluation Kit with 2 SD/MMC Slots"
+        help
+          Select this if you are using an Atmel AT91SAM9G20-EK Evaluation Kit
+          with 2 SD/MMC Slots. This is the case for AT91SAM9G20-EK rev. C and
+          onwards.
+          <http://www.atmel.com/tools/SAM9G20-EK.aspx>
+
+config MACH_CPU9G20
+        bool "Eukrea CPU9G20 board"
+        help
+          Select this if you are using a Eukrea Electromatique's
+          CPU9G20 Board <http://www.eukrea.com/>
+
+config MACH_ACMENETUSFOXG20
+        bool "Acme Systems srl FOX Board G20"
+        help
+          Select this if you are using Acme Systems
+          FOX Board G20 <http://www.acmesystems.it>
+
+config MACH_PORTUXG20
+        bool "taskit PortuxG20"
+        help
+          Select this if you are using taskit's PortuxG20.
+          <http://www.taskit.de/en/>
+
+config MACH_STAMP9G20
+        bool "taskit Stamp9G20 CPU module"
+        help
+          Select this if you are using taskit's Stamp9G20 CPU module on its
+          evaluation board.
+          <http://www.taskit.de/en/>
+
+config MACH_PCONTROL_G20
+        bool "PControl G20 CPU module"
+        help
+          Select this if you are using taskit's Stamp9G20 CPU module on this
+          carrier board, beeing the decentralized unit of a building automation
+          system; featuring nvram, eth-switch, iso-rs485, display, io
+
+config MACH_GSIA18S
+        bool "GS_IA18_S board"
+        help
+          This enables support for the GS_IA18_S board
+          produced by GeoSIG Ltd company. This is an internet accelerograph.
+          <http://www.geosig.com>
+
+config MACH_USB_A9G20
+        bool "CALAO USB-A9G20"
+        depends on ARCH_AT91SAM9G20
+        help
+          Select this if you are using a Calao Systems USB-A9G20.
+          <http://www.calao-systems.com>
+
+endif
+
+if (ARCH_AT91SAM9260 || ARCH_AT91SAM9G20)
+comment "AT91SAM9260/AT91SAM9G20 boards"
+
+config MACH_SNAPPER_9260
+        bool "Bluewater Systems Snapper 9260/9G20 module"
+        help
+          Select this if you are using the Bluewater Systems Snapper 9260 or
+          Snapper 9G20 modules.
+          <http://www.bluewatersys.com/>
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91SAM9G45
+
+comment "AT91SAM9G45 Board Type"
+
+config MACH_AT91SAM9M10G45EK
+        bool "Atmel AT91SAM9M10G45-EK Evaluation Kits"
+        help
+          Select this if you are using Atmel's AT91SAM9M10G45-EK Evaluation Kit.
+          Those boards can be populated with any SoC of AT91SAM9G45 or AT91SAM9M10
+          families: AT91SAM9G45, AT91SAM9G46, AT91SAM9M10 and AT91SAM9M11.
+          <http://www.atmel.com/tools/SAM9M10-G45-EK.aspx>
+
+endif
+
+# ----------------------------------------------------------
+
+if ARCH_AT91X40
+
+comment "AT91X40 Board Type"
+
+config MACH_AT91EB01
+        bool "Atmel AT91EB01 Evaluation Kit"
+        help
+          Select this if you are using Atmel's AT91EB01 Evaluation Kit.
+          It is also a popular target for simulators such as GDB's
+          ARM simulator (commonly known as the ARMulator) and the
+          Skyeye simulator.
+
+endif
+
+# ----------------------------------------------------------
+
+comment "AT91 Board Options"
+
+config MTD_AT91_DATAFLASH_CARD
+        bool "Enable DataFlash Card support"
+        depends on HAVE_AT91_DATAFLASH_CARD
+        help
+          Enable support for the DataFlash card.
+
+endmenu
diff --git a/arch/arm/mach-at91/Makefile b/arch/arm/mach-at91/Makefile
index 39218ca6d8e8..505fed961eb0 100644
--- a/arch/arm/mach-at91/Makefile
+++ b/arch/arm/mach-at91/Makefile
@@ -87,8 +87,8 @@ obj-$(CONFIG_MACH_SNAPPER_9260)	+= board-snapper9260.o
 obj-$(CONFIG_MACH_AT91SAM9M10G45EK) += board-sam9m10g45ek.o
 
 # AT91SAM board with device-tree
-obj-$(CONFIG_MACH_AT91RM9200_DT) += board-rm9200-dt.o
-obj-$(CONFIG_MACH_AT91SAM_DT) += board-dt.o
+obj-$(CONFIG_MACH_AT91RM9200_DT) += board-dt-rm9200.o
+obj-$(CONFIG_MACH_AT91SAM9_DT) += board-dt-sam9.o
 
 # AT91X40 board-specific support
 obj-$(CONFIG_MACH_AT91EB01)     += board-eb01.o
diff --git a/arch/arm/mach-at91/at91_rstc.h b/arch/arm/mach-at91/at91_rstc.h
index 875fa336800b..a600e6992920 100644
--- a/arch/arm/mach-at91/at91_rstc.h
+++ b/arch/arm/mach-at91/at91_rstc.h
@@ -23,7 +23,7 @@ extern void __iomem *at91_rstc_base;
         __raw_readl(at91_rstc_base + field)
 
 #define at91_rstc_write(field, value) \
-        __raw_writel(value, at91_rstc_base + field);
+        __raw_writel(value, at91_rstc_base + field)
 #else
 .extern at91_rstc_base
 #endif
diff --git a/arch/arm/mach-at91/at91_shdwc.h b/arch/arm/mach-at91/at91_shdwc.h
index 60478ea8bd46..9e29f31ec9a6 100644
--- a/arch/arm/mach-at91/at91_shdwc.h
+++ b/arch/arm/mach-at91/at91_shdwc.h
@@ -23,7 +23,7 @@ extern void __iomem *at91_shdwc_base;
         __raw_readl(at91_shdwc_base + field)
 
 #define at91_shdwc_write(field, value) \
-        __raw_writel(value, at91_shdwc_base + field);
+        __raw_writel(value, at91_shdwc_base + field)
 #endif
 
 #define AT91_SHDW_CR            0x00                    /* Shut Down Control Register */
diff --git a/arch/arm/mach-at91/at91x40_time.c b/arch/arm/mach-at91/at91x40_time.c
index 0c07a4459cb2..2919eba41ff4 100644
--- a/arch/arm/mach-at91/at91x40_time.c
+++ b/arch/arm/mach-at91/at91x40_time.c
@@ -33,7 +33,7 @@
         __raw_readl(AT91_IO_P2V(AT91_TC) + field)
 
 #define at91_tc_write(field, value) \
-        __raw_writel(value, AT91_IO_P2V(AT91_TC) + field);
+        __raw_writel(value, AT91_IO_P2V(AT91_TC) + field)
 
 /*
  *      3 counter/timer units present.
diff --git a/arch/arm/mach-at91/board-rm9200-dt.c b/arch/arm/mach-at91/board-dt-rm9200.c
index 3fcb6623a33e..3fcb6623a33e 100644
--- a/arch/arm/mach-at91/board-rm9200-dt.c
+++ b/arch/arm/mach-at91/board-dt-rm9200.c
diff --git a/arch/arm/mach-at91/board-dt.c b/arch/arm/mach-at91/board-dt-sam9.c
index 8db30132abed..8db30132abed 100644
--- a/arch/arm/mach-at91/board-dt.c
+++ b/arch/arm/mach-at91/board-dt-sam9.c
diff --git a/arch/arm/mach-at91/gpio.c b/arch/arm/mach-at91/gpio.c
index c5d7e1e9d757..a5afcf76550e 100644
--- a/arch/arm/mach-at91/gpio.c
+++ b/arch/arm/mach-at91/gpio.c
@@ -22,10 +22,9 @@
 #include <linux/module.h>
 #include <linux/io.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/of_address.h>
 
-#include <asm/mach/irq.h>
-
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
 
diff --git a/arch/arm/mach-at91/include/mach/at91_dbgu.h b/arch/arm/mach-at91/include/mach/at91_dbgu.h
index 2aa0c5e13495..3b5948566e52 100644
--- a/arch/arm/mach-at91/include/mach/at91_dbgu.h
+++ b/arch/arm/mach-at91/include/mach/at91_dbgu.h
@@ -16,9 +16,6 @@
 #ifndef AT91_DBGU_H
 #define AT91_DBGU_H
 
-#define dbgu_readl(dbgu, field) \
-        __raw_readl(AT91_VA_BASE_SYS + dbgu + AT91_DBGU_ ## field)
-
 #if !defined(CONFIG_ARCH_AT91X40)
 #define AT91_DBGU_CR            (0x00)  /* Control Register */
 #define AT91_DBGU_MR            (0x04)  /* Mode Register */
diff --git a/arch/arm/mach-at91/include/mach/at91_matrix.h b/arch/arm/mach-at91/include/mach/at91_matrix.h
index 02fae9de746b..f8996c954131 100644
--- a/arch/arm/mach-at91/include/mach/at91_matrix.h
+++ b/arch/arm/mach-at91/include/mach/at91_matrix.h
@@ -14,7 +14,7 @@ extern void __iomem *at91_matrix_base;
         __raw_readl(at91_matrix_base + field)
 
 #define at91_matrix_write(field, value) \
-        __raw_writel(value, at91_matrix_base + field);
+        __raw_writel(value, at91_matrix_base + field)
 
 #else
 .extern at91_matrix_base
diff --git a/arch/arm/mach-at91/include/mach/at91_st.h b/arch/arm/mach-at91/include/mach/at91_st.h
index 969aac27109f..67fdbd13c3ed 100644
--- a/arch/arm/mach-at91/include/mach/at91_st.h
+++ b/arch/arm/mach-at91/include/mach/at91_st.h
@@ -23,7 +23,7 @@ extern void __iomem *at91_st_base;
         __raw_readl(at91_st_base + field)
 
 #define at91_st_write(field, value) \
-        __raw_writel(value, at91_st_base + field);
+        __raw_writel(value, at91_st_base + field)
 #else
 .extern at91_st_base
 #endif
diff --git a/arch/arm/mach-at91/setup.c b/arch/arm/mach-at91/setup.c
index 4b678478cf95..9e7c1e1528e5 100644
--- a/arch/arm/mach-at91/setup.c
+++ b/arch/arm/mach-at91/setup.c
@@ -333,7 +333,7 @@ static void at91_dt_rstc(void)
 
         of_id = of_match_node(rstc_ids, np);
         if (!of_id)
-                panic("AT91: rtsc no restart function availlable\n");
+                panic("AT91: rtsc no restart function available\n");
 
         arm_pm_restart = of_id->data;
 
@@ -353,7 +353,7 @@ static void at91_dt_ramc(void)
 
         np = of_find_matching_node(NULL, ramc_ids);
         if (!np)
-                panic("unable to find compatible ram conroller node in dtb\n");
+                panic("unable to find compatible ram controller node in dtb\n");
 
         at91_ramc_base[0] = of_iomap(np, 0);
         if (!at91_ramc_base[0])
@@ -403,7 +403,7 @@ static void at91_dt_shdwc(void)
 
         np = of_find_matching_node(NULL, shdwc_ids);
         if (!np) {
-                pr_debug("AT91: unable to find compatible shutdown (shdwc) conroller node in dtb\n");
+                pr_debug("AT91: unable to find compatible shutdown (shdwc) controller node in dtb\n");
                 return;
         }
 
@@ -419,7 +419,7 @@ static void at91_dt_shdwc(void)
 
         if (!of_property_read_u32(np, "atmel,wakeup-counter", &reg)) {
                 if (reg > AT91_SHDW_CPTWK0_MAX) {
-                        pr_warn("AT91: shdwc wakeup conter 0x%x > 0x%x reduce it to 0x%x\n",
+                        pr_warn("AT91: shdwc wakeup counter 0x%x > 0x%x reduce it to 0x%x\n",
                                 reg, AT91_SHDW_CPTWK0_MAX, AT91_SHDW_CPTWK0_MAX);
                         reg = AT91_SHDW_CPTWK0_MAX;
                 }
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index d5dde0727339..42378fb90167 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -97,11 +97,6 @@ config EXYNOS4_DEV_AHCI
         help
           Compile in platform device definitions for AHCI
 
-config EXYNOS_DEV_DRM
-        bool
-        help
-          Compile in platform device definitions for core DRM device
-
 config EXYNOS4_SETUP_FIMD0
         bool
         help
@@ -201,7 +196,6 @@ config MACH_SMDKV310
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select EXYNOS_DEV_SYSMMU
         select S3C24XX_PWM
         select S3C_DEV_HSMMC
@@ -255,9 +249,7 @@ config MACH_UNIVERSAL_C210
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select EXYNOS_DEV_SYSMMU
-        select HAVE_SCHED_CLOCK
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
@@ -296,7 +288,6 @@ config MACH_NURI
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select S3C_DEV_HSMMC
         select S3C_DEV_HSMMC2
         select S3C_DEV_HSMMC3
@@ -332,7 +323,6 @@ config MACH_ORIGEN
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select EXYNOS_DEV_SYSMMU
         select S3C24XX_PWM
         select S3C_DEV_HSMMC
@@ -368,7 +358,6 @@ config MACH_SMDK4212
         select EXYNOS4_SETUP_SDHCI
         select EXYNOS4_SETUP_USB_PHY
         select EXYNOS_DEV_DMA
-        select EXYNOS_DEV_DRM
         select EXYNOS_DEV_SYSMMU
         select S3C24XX_PWM
         select S3C_DEV_HSMMC2
@@ -409,7 +398,7 @@ config MACH_EXYNOS4_DT
         depends on ARCH_EXYNOS4
         select ARM_AMBA
         select CPU_EXYNOS4210
-        select HAVE_SAMSUNG_KEYPAD if INPUT_KEYBOARD
+        select KEYBOARD_SAMSUNG if INPUT_KEYBOARD
         select PINCTRL
         select PINCTRL_EXYNOS
         select USE_OF
diff --git a/arch/arm/mach-exynos/common.c b/arch/arm/mach-exynos/common.c
index d63d399c7bae..1b0fa7afc7f8 100644
--- a/arch/arm/mach-exynos/common.c
+++ b/arch/arm/mach-exynos/common.c
@@ -23,9 +23,9 @@
 #include <linux/of_irq.h>
 #include <linux/export.h>
 #include <linux/irqdomain.h>
-#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/irqchip/chained_irq.h>
 
 #include <asm/proc-fns.h>
 #include <asm/exception.h>
diff --git a/arch/arm/mach-exynos/dev-ohci.c b/arch/arm/mach-exynos/dev-ohci.c
index 4244d02dafbd..d5bc129e6bb7 100644
--- a/arch/arm/mach-exynos/dev-ohci.c
+++ b/arch/arm/mach-exynos/dev-ohci.c
@@ -12,7 +12,7 @@
 
 #include <linux/dma-mapping.h>
 #include <linux/platform_device.h>
-#include <linux/platform_data/usb-exynos.h>
+#include <linux/platform_data/usb-ohci-exynos.h>
 
 #include <mach/irqs.h>
 #include <mach/map.h>
diff --git a/arch/arm/mach-exynos/mach-origen.c b/arch/arm/mach-exynos/mach-origen.c
index 579d2d171daa..bf946931ab32 100644
--- a/arch/arm/mach-exynos/mach-origen.c
+++ b/arch/arm/mach-exynos/mach-origen.c
@@ -26,7 +26,7 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/s3c-hsotg.h>
 #include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-exynos.h>
+#include <linux/platform_data/usb-ohci-exynos.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-exynos/mach-smdkv310.c b/arch/arm/mach-exynos/mach-smdkv310.c
index d71672922b19..8270929d7b44 100644
--- a/arch/arm/mach-exynos/mach-smdkv310.c
+++ b/arch/arm/mach-exynos/mach-smdkv310.c
@@ -23,7 +23,7 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/s3c-hsotg.h>
 #include <linux/platform_data/usb-ehci-s5p.h>
-#include <linux/platform_data/usb-exynos.h>
+#include <linux/platform_data/usb-ohci-exynos.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach-types.h>
diff --git a/arch/arm/mach-exynos/platsmp.c b/arch/arm/mach-exynos/platsmp.c
index 60f7c5be057d..95e04bd5813f 100644
--- a/arch/arm/mach-exynos/platsmp.c
+++ b/arch/arm/mach-exynos/platsmp.c
@@ -20,7 +20,6 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -76,13 +75,6 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit exynos_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/mach-gemini/Makefile b/arch/arm/mach-gemini/Makefile
index 7355c0bbcb5e..7963a77be637 100644
--- a/arch/arm/mach-gemini/Makefile
+++ b/arch/arm/mach-gemini/Makefile
@@ -4,7 +4,7 @@
 
 # Object file lists.
 
-obj-y                   := irq.o mm.o time.o devices.o gpio.o idle.o
+obj-y                   := irq.o mm.o time.o devices.o gpio.o idle.o reset.o
 
 # Board-specific support
 obj-$(CONFIG_MACH_NAS4220B)     += board-nas4220b.o
diff --git a/arch/arm/mach-gemini/board-nas4220b.c b/arch/arm/mach-gemini/board-nas4220b.c
index 08bd650c42f3..ca8a25bb3521 100644
--- a/arch/arm/mach-gemini/board-nas4220b.c
+++ b/arch/arm/mach-gemini/board-nas4220b.c
@@ -103,4 +103,5 @@ MACHINE_START(NAS4220B, "Raidsonic NAS IB-4220-B")
         .init_irq       = gemini_init_irq,
         .init_time      = gemini_timer_init,
         .init_machine   = ib4220b_init,
+        .restart        = gemini_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-rut1xx.c b/arch/arm/mach-gemini/board-rut1xx.c
index fa0a36337f4d..7a675f88ffd6 100644
--- a/arch/arm/mach-gemini/board-rut1xx.c
+++ b/arch/arm/mach-gemini/board-rut1xx.c
@@ -14,6 +14,7 @@
 #include <linux/leds.h>
 #include <linux/input.h>
 #include <linux/gpio_keys.h>
+#include <linux/sizes.h>
 
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
@@ -87,4 +88,5 @@ MACHINE_START(RUT100, "Teltonika RUT100")
         .init_irq       = gemini_init_irq,
         .init_time      = gemini_timer_init,
         .init_machine   = rut1xx_init,
+        .restart        = gemini_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-wbd111.c b/arch/arm/mach-gemini/board-wbd111.c
index 3321cd6cc1f3..418188cd1712 100644
--- a/arch/arm/mach-gemini/board-wbd111.c
+++ b/arch/arm/mach-gemini/board-wbd111.c
@@ -130,4 +130,5 @@ MACHINE_START(WBD111, "Wiliboard WBD-111")
         .init_irq       = gemini_init_irq,
         .init_time      = gemini_timer_init,
         .init_machine   = wbd111_init,
+        .restart        = gemini_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/board-wbd222.c b/arch/arm/mach-gemini/board-wbd222.c
index fe33c825fdaf..266b265090cd 100644
--- a/arch/arm/mach-gemini/board-wbd222.c
+++ b/arch/arm/mach-gemini/board-wbd222.c
@@ -130,4 +130,5 @@ MACHINE_START(WBD222, "Wiliboard WBD-222")
         .init_irq       = gemini_init_irq,
         .init_time      = gemini_timer_init,
         .init_machine   = wbd222_init,
+        .restart        = gemini_restart,
 MACHINE_END
diff --git a/arch/arm/mach-gemini/common.h b/arch/arm/mach-gemini/common.h
index 7670c39acb2f..38a45260a7c8 100644
--- a/arch/arm/mach-gemini/common.h
+++ b/arch/arm/mach-gemini/common.h
@@ -26,4 +26,6 @@ extern int platform_register_pflash(unsigned int size,
                                     struct mtd_partition *parts,
                                     unsigned int nr_parts);
 
+extern void gemini_restart(char mode, const char *cmd);
+
 #endif /* __GEMINI_COMMON_H__ */
diff --git a/arch/arm/mach-gemini/gpio.c b/arch/arm/mach-gemini/gpio.c
index fdc7ef1391d3..70bfa571b24b 100644
--- a/arch/arm/mach-gemini/gpio.c
+++ b/arch/arm/mach-gemini/gpio.c
@@ -21,6 +21,7 @@
 
 #include <mach/hardware.h>
 #include <mach/irqs.h>
+#include <mach/gpio.h>
 
 #define GPIO_BASE(x)            IO_ADDRESS(GEMINI_GPIO_BASE(x))
 
@@ -44,7 +45,7 @@
 
 #define GPIO_PORT_NUM           3
 
-static void _set_gpio_irqenable(unsigned int base, unsigned int index,
+static void _set_gpio_irqenable(void __iomem *base, unsigned int index,
                                 int enable)
 {
         unsigned int reg;
@@ -57,7 +58,7 @@ static void _set_gpio_irqenable(unsigned int base, unsigned int index,
 static void gpio_ack_irq(struct irq_data *d)
 {
         unsigned int gpio = irq_to_gpio(d->irq);
-        unsigned int base = GPIO_BASE(gpio / 32);
+        void __iomem *base = GPIO_BASE(gpio / 32);
 
         __raw_writel(1 << (gpio % 32), base + GPIO_INT_CLR);
 }
@@ -65,7 +66,7 @@ static void gpio_ack_irq(struct irq_data *d)
 static void gpio_mask_irq(struct irq_data *d)
 {
         unsigned int gpio = irq_to_gpio(d->irq);
-        unsigned int base = GPIO_BASE(gpio / 32);
+        void __iomem *base = GPIO_BASE(gpio / 32);
 
         _set_gpio_irqenable(base, gpio % 32, 0);
 }
@@ -73,7 +74,7 @@ static void gpio_mask_irq(struct irq_data *d)
 static void gpio_unmask_irq(struct irq_data *d)
 {
         unsigned int gpio = irq_to_gpio(d->irq);
-        unsigned int base = GPIO_BASE(gpio / 32);
+        void __iomem *base = GPIO_BASE(gpio / 32);
 
         _set_gpio_irqenable(base, gpio % 32, 1);
 }
@@ -82,7 +83,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
 {
         unsigned int gpio = irq_to_gpio(d->irq);
         unsigned int gpio_mask = 1 << (gpio % 32);
-        unsigned int base = GPIO_BASE(gpio / 32);
+        void __iomem *base = GPIO_BASE(gpio / 32);
         unsigned int reg_both, reg_level, reg_type;
 
         reg_type = __raw_readl(base + GPIO_INT_TYPE);
@@ -120,7 +121,7 @@ static int gpio_set_irq_type(struct irq_data *d, unsigned int type)
         __raw_writel(reg_level, base + GPIO_INT_LEVEL);
         __raw_writel(reg_both, base + GPIO_INT_BOTH_EDGE);
 
-        gpio_ack_irq(d->irq);
+        gpio_ack_irq(d);
 
         return 0;
 }
@@ -153,7 +154,7 @@ static struct irq_chip gpio_irq_chip = {
 static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
                                 int dir)
 {
-        unsigned int base = GPIO_BASE(offset / 32);
+        void __iomem *base = GPIO_BASE(offset / 32);
         unsigned int reg;
 
         reg = __raw_readl(base + GPIO_DIR);
@@ -166,7 +167,7 @@ static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
 
 static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 {
-        unsigned int base = GPIO_BASE(offset / 32);
+        void __iomem *base = GPIO_BASE(offset / 32);
 
         if (value)
                 __raw_writel(1 << (offset % 32), base + GPIO_DATA_SET);
@@ -176,7 +177,7 @@ static void gemini_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
 
 static int gemini_gpio_get(struct gpio_chip *chip, unsigned offset)
 {
-        unsigned int base = GPIO_BASE(offset / 32);
+        void __iomem *base = GPIO_BASE(offset / 32);
 
         return (__raw_readl(base + GPIO_DATA_IN) >> (offset % 32)) & 1;
 }
diff --git a/arch/arm/mach-gemini/include/mach/hardware.h b/arch/arm/mach-gemini/include/mach/hardware.h
index 8c950e1d06be..98e7b0f286bf 100644
--- a/arch/arm/mach-gemini/include/mach/hardware.h
+++ b/arch/arm/mach-gemini/include/mach/hardware.h
@@ -69,6 +69,6 @@
 /*
  * macro to get at IO space when running virtually
  */
-#define IO_ADDRESS(x)   ((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
+#define IO_ADDRESS(x)   IOMEM((((x) & 0xFFF00000) >> 4) | ((x) & 0x000FFFFF) | 0xF0000000)
 
 #endif
diff --git a/arch/arm/mach-gemini/irq.c b/arch/arm/mach-gemini/irq.c
index 6d8f6d1669ff..44f50dcb616d 100644
--- a/arch/arm/mach-gemini/irq.c
+++ b/arch/arm/mach-gemini/irq.c
@@ -67,8 +67,8 @@ static struct irq_chip gemini_irq_chip = {
 
 static struct resource irq_resource = {
         .name   = "irq_handler",
-        .start  = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
-        .end    = IO_ADDRESS(FIQ_STATUS(GEMINI_INTERRUPT_BASE)) + 4,
+        .start  = GEMINI_INTERRUPT_BASE,
+        .end    = FIQ_STATUS(GEMINI_INTERRUPT_BASE) + 4,
 };
 
 void __init gemini_init_irq(void)
diff --git a/arch/arm/mach-gemini/mm.c b/arch/arm/mach-gemini/mm.c
index 51948242ec09..2c2cd284bb6a 100644
--- a/arch/arm/mach-gemini/mm.c
+++ b/arch/arm/mach-gemini/mm.c
@@ -19,57 +19,57 @@
 /* Page table mapping for I/O region */
 static struct map_desc gemini_io_desc[] __initdata = {
         {
-                .virtual        = IO_ADDRESS(GEMINI_GLOBAL_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GLOBAL_BASE),
                 .pfn            =__phys_to_pfn(GEMINI_GLOBAL_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_UART_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_UART_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_UART_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_TIMER_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_TIMER_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_TIMER_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_INTERRUPT_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_INTERRUPT_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_INTERRUPT_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_POWER_CTRL_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_POWER_CTRL_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_GPIO_BASE(0)),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(0)),
                 .pfn            = __phys_to_pfn(GEMINI_GPIO_BASE(0)),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_GPIO_BASE(1)),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(1)),
                 .pfn            = __phys_to_pfn(GEMINI_GPIO_BASE(1)),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_GPIO_BASE(2)),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GPIO_BASE(2)),
                 .pfn            = __phys_to_pfn(GEMINI_GPIO_BASE(2)),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_FLASH_CTRL_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_FLASH_CTRL_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_DRAM_CTRL_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_DRAM_CTRL_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
+                .virtual        = (unsigned long)IO_ADDRESS(GEMINI_GENERAL_DMA_BASE),
                 .pfn            = __phys_to_pfn(GEMINI_GENERAL_DMA_BASE),
                 .length         = SZ_512K,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-gemini/include/mach/system.h b/arch/arm/mach-gemini/reset.c
index a33b5a1f8ab4..b26659759e27 100644
--- a/arch/arm/mach-gemini/include/mach/system.h
+++ b/arch/arm/mach-gemini/reset.c
@@ -14,7 +14,7 @@
 #include <mach/hardware.h>
 #include <mach/global_reg.h>
 
-static inline void arch_reset(char mode, const char *cmd)
+void gemini_restart(char mode, const char *cmd)
 {
         __raw_writel(RESET_GLOBAL | RESET_CPU1,
                      IO_ADDRESS(GEMINI_GLOBAL_BASE) + GLOBAL_RESET);
diff --git a/arch/arm/mach-h720x/Kconfig b/arch/arm/mach-h720x/Kconfig
deleted file mode 100644
index 6bb755bcb6f5..000000000000
--- a/arch/arm/mach-h720x/Kconfig
+++ /dev/null
@@ -1,40 +0,0 @@
-if ARCH_H720X
-
-menu "h720x Implementations"
-
-config ARCH_H7201
-        bool "gms30c7201"
-        depends on ARCH_H720X
-        select CPU_H7201
-        select ZONE_DMA
-        help
-          Say Y here if you are using the Hynix GMS30C7201 Reference Board
-
-config ARCH_H7202
-        bool "hms30c7202"
-        depends on ARCH_H720X
-        select CPU_H7202
-        select ZONE_DMA
-        help
-          Say Y here if you are using the Hynix HMS30C7202 Reference Board
-
-endmenu
-
-config CPU_H7201
-        bool
-        help
-          Select code specific to h7201 variants
-
-config CPU_H7202
-        bool
-        help
-          Select code specific to h7202 variants
-config H7202_SERIAL23
-        depends on CPU_H7202
-        bool "Use serial ports 2+3"
-        help
-          Say Y here if you wish to use serial ports 2+3. They share their
-          pins with the keyboard matrix controller, so you have to decide.
-
-
-endif
diff --git a/arch/arm/mach-h720x/Makefile b/arch/arm/mach-h720x/Makefile
deleted file mode 100644
index e4cf728948eb..000000000000
--- a/arch/arm/mach-h720x/Makefile
+++ /dev/null
@@ -1,16 +0,0 @@
-#
-# Makefile for the linux kernel.
-#
-
-# Common support
-obj-y := common.o
-obj-m :=
-obj-n :=
-obj-  :=
-
-# Specific board support
-
-obj-$(CONFIG_ARCH_H7201)                += h7201-eval.o
-obj-$(CONFIG_ARCH_H7202)                += h7202-eval.o
-obj-$(CONFIG_CPU_H7201)                 += cpu-h7201.o
-obj-$(CONFIG_CPU_H7202)                 += cpu-h7202.o
diff --git a/arch/arm/mach-h720x/Makefile.boot b/arch/arm/mach-h720x/Makefile.boot
deleted file mode 100644
index d875a7094dfe..000000000000
--- a/arch/arm/mach-h720x/Makefile.boot
+++ /dev/null
@@ -1,2 +0,0 @@
-   zreladdr-$(CONFIG_ARCH_H720X)        += 0x40008000
-
diff --git a/arch/arm/mach-h720x/common.c b/arch/arm/mach-h720x/common.c
deleted file mode 100644
index 17ef91fa3d56..000000000000
--- a/arch/arm/mach-h720x/common.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/common.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * common stuff for Hynix h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/sched.h>
-#include <linux/mman.h>
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/io.h>
-
-#include <asm/page.h>
-#include <asm/pgtable.h>
-#include <asm/dma.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <asm/system_misc.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/map.h>
-#include <mach/irqs.h>
-
-#include <asm/mach/dma.h>
-
-#if 0
-#define IRQDBG(args...) printk(args)
-#else
-#define IRQDBG(args...) do {} while(0)
-#endif
-
-void __init arch_dma_init(dma_t *dma)
-{
-}
-
-/*
- * Return nsecs since last timer reload
- * (timercount * (usecs perjiffie)) / (ticks per jiffie)
- */
-u32 h720x_gettimeoffset(void)
-{
-        return ((CPU_REG(TIMER_VIRT, TM0_COUNT) * tick_usec) / LATCH) * 1000;
-}
-
-/*
- * mask Global irq's
- */
-static void mask_global_irq(struct irq_data *d)
-{
-        CPU_REG (IRQC_VIRT, IRQC_IER) &= ~(1 << d->irq);
-}
-
-/*
- * unmask Global irq's
- */
-static void unmask_global_irq(struct irq_data *d)
-{
-        CPU_REG (IRQC_VIRT, IRQC_IER) |= (1 << d->irq);
-}
-
-
-/*
- * ack GPIO irq's
- * Ack only for edge triggered int's valid
- */
-static void inline ack_gpio_irq(struct irq_data *d)
-{
-        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
-        u32 bit = IRQ_TO_BIT(d->irq);
-        if ( (CPU_REG (reg_base, GPIO_EDGE) & bit))
-                CPU_REG (reg_base, GPIO_CLR) = bit;
-}
-
-/*
- * mask GPIO irq's
- */
-static void inline mask_gpio_irq(struct irq_data *d)
-{
-        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
-        u32 bit = IRQ_TO_BIT(d->irq);
-        CPU_REG (reg_base, GPIO_MASK) &= ~bit;
-}
-
-/*
- * unmask GPIO irq's
- */
-static void inline unmask_gpio_irq(struct irq_data *d)
-{
-        u32 reg_base = GPIO_VIRT(IRQ_TO_REGNO(d->irq));
-        u32 bit = IRQ_TO_BIT(d->irq);
-        CPU_REG (reg_base, GPIO_MASK) |= bit;
-}
-
-static void
-h720x_gpio_handler(unsigned int mask, unsigned int irq,
-                 struct irq_desc *desc)
-{
-        IRQDBG("%s irq: %d\n", __func__, irq);
-        while (mask) {
-                if (mask & 1) {
-                        IRQDBG("handling irq %d\n", irq);
-                        generic_handle_irq(irq);
-                }
-                irq++;
-                mask >>= 1;
-        }
-}
-
-static void
-h720x_gpioa_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG(GPIO_A_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOA(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-
-static void
-h720x_gpiob_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-        mask = CPU_REG(GPIO_B_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOB(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-
-static void
-h720x_gpioc_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG(GPIO_C_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOC(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-
-static void
-h720x_gpiod_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG(GPIO_D_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOD(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-
-#ifdef CONFIG_CPU_H7202
-static void
-h720x_gpioe_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG(GPIO_E_VIRT,GPIO_STAT);
-        irq = IRQ_CHAINED_GPIOE(0);
-        IRQDBG("%s mask: 0x%08x irq: %d\n", __func__, mask,irq);
-        h720x_gpio_handler(mask, irq, desc);
-}
-#endif
-
-static struct irq_chip h720x_global_chip = {
-        .irq_ack = mask_global_irq,
-        .irq_mask = mask_global_irq,
-        .irq_unmask = unmask_global_irq,
-};
-
-static struct irq_chip h720x_gpio_chip = {
-        .irq_ack = ack_gpio_irq,
-        .irq_mask = mask_gpio_irq,
-        .irq_unmask = unmask_gpio_irq,
-};
-
-/*
- * Initialize IRQ's, mask all, enable multiplexed irq's
- */
-void __init h720x_init_irq (void)
-{
-        int     irq;
-
-        /* Mask global irq's */
-        CPU_REG (IRQC_VIRT, IRQC_IER) = 0x0;
-
-        /* Mask all multiplexed irq's */
-        CPU_REG (GPIO_A_VIRT, GPIO_MASK) = 0x0;
-        CPU_REG (GPIO_B_VIRT, GPIO_MASK) = 0x0;
-        CPU_REG (GPIO_C_VIRT, GPIO_MASK) = 0x0;
-        CPU_REG (GPIO_D_VIRT, GPIO_MASK) = 0x0;
-
-        /* Initialize global IRQ's, fast path */
-        for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
-                irq_set_chip_and_handler(irq, &h720x_global_chip,
-                                         handle_level_irq);
-                set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
-        }
-
-        /* Initialize multiplexed IRQ's, slow path */
-        for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
-                irq_set_chip_and_handler(irq, &h720x_gpio_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID );
-        }
-        irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
-        irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
-        irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
-        irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
-
-#ifdef CONFIG_CPU_H7202
-        for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
-                irq_set_chip_and_handler(irq, &h720x_gpio_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID );
-        }
-        irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
-#endif
-
-        /* Enable multiplexed irq's */
-        CPU_REG (IRQC_VIRT, IRQC_IER) = IRQ_ENA_MUX;
-}
-
-static struct map_desc h720x_io_desc[] __initdata = {
-        {
-                .virtual        = IO_VIRT,
-                .pfn            = __phys_to_pfn(IO_PHYS),
-                .length         = IO_SIZE,
-                .type           = MT_DEVICE
-        },
-};
-
-/* Initialize io tables */
-void __init h720x_map_io(void)
-{
-        iotable_init(h720x_io_desc,ARRAY_SIZE(h720x_io_desc));
-}
-
-void h720x_restart(char mode, const char *cmd)
-{
-        CPU_REG (PMU_BASE, PMU_STAT) |= PMU_WARMRESET;
-}
-
-static void h720x__idle(void)
-{
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_IDLE;
-        nop();
-        nop();
-        CPU_REG (PMU_BASE, PMU_MODE) = PMU_MODE_RUN;
-        nop();
-        nop();
-}
-
-static int __init h720x_idle_init(void)
-{
-        arm_pm_idle = h720x__idle;
-        return 0;
-}
-
-arch_initcall(h720x_idle_init);
diff --git a/arch/arm/mach-h720x/common.h b/arch/arm/mach-h720x/common.h
deleted file mode 100644
index 7e738410ca93..000000000000
--- a/arch/arm/mach-h720x/common.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/common.h
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * Architecture specific stuff for Hynix GMS30C7201 development board
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-extern u32 h720x_gettimeoffset(void);
-extern void __init h720x_init_irq(void);
-extern void __init h720x_map_io(void);
-extern void h720x_restart(char, const char *);
-
-#ifdef CONFIG_ARCH_H7202
-extern void h7202_timer_init(void);
-extern void __init init_hw_h7202(void);
-extern void __init h7202_init_irq(void);
-extern void __init h7202_init_time(void);
-#endif
-
-#ifdef CONFIG_ARCH_H7201
-extern void h7201_timer_init(void);
-#endif
diff --git a/arch/arm/mach-h720x/cpu-h7201.c b/arch/arm/mach-h720x/cpu-h7201.c
deleted file mode 100644
index 13c741215387..000000000000
--- a/arch/arm/mach-h720x/cpu-h7201.c
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/cpu-h7201.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * processor specific stuff for the Hynix h7201
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <asm/types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/irqs.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include "common.h"
-/*
- * Timer interrupt handler
- */
-static irqreturn_t
-h7201_timer_interrupt(int irq, void *dev_id)
-{
-        CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
-        timer_tick();
-
-        return IRQ_HANDLED;
-}
-
-static struct irqaction h7201_timer_irq = {
-        .name           = "h7201 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = h7201_timer_interrupt,
-};
-
-/*
- * Setup TIMER0 as system timer
- */
-void __init h7201_timer_init(void)
-{
-        arch_gettimeoffset = h720x_gettimeoffset;
-
-        CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
-        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
-        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
-        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
-
-        setup_irq(IRQ_TIMER0, &h7201_timer_irq);
-}
diff --git a/arch/arm/mach-h720x/cpu-h7202.c b/arch/arm/mach-h720x/cpu-h7202.c
deleted file mode 100644
index e2ae7e898f9d..000000000000
--- a/arch/arm/mach-h720x/cpu-h7202.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/cpu-h7202.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * processor specific stuff for the Hynix h7202
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/module.h>
-#include <asm/types.h>
-#include <mach/hardware.h>
-#include <asm/irq.h>
-#include <mach/irqs.h>
-#include <asm/mach/irq.h>
-#include <asm/mach/time.h>
-#include <linux/device.h>
-#include <linux/serial_8250.h>
-#include "common.h"
-
-static struct resource h7202ps2_resources[] = {
-        [0] = {
-                .start  = 0x8002c000,
-                .end    = 0x8002c040,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_PS2,
-                .end    = IRQ_PS2,
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device h7202ps2_device = {
-        .name           = "h7202ps2",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(h7202ps2_resources),
-        .resource       = h7202ps2_resources,
-};
-
-static struct plat_serial8250_port serial_platform_data[] = {
-        {
-                .membase        = (void*)SERIAL0_VIRT,
-                .mapbase        = SERIAL0_BASE,
-                .irq            = IRQ_UART0,
-                .uartclk        = 2*1843200,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-        {
-                .membase        = (void*)SERIAL1_VIRT,
-                .mapbase        = SERIAL1_BASE,
-                .irq            = IRQ_UART1,
-                .uartclk        = 2*1843200,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-#ifdef CONFIG_H7202_SERIAL23
-        {
-                .membase        = (void*)SERIAL2_VIRT,
-                .mapbase        = SERIAL2_BASE,
-                .irq            = IRQ_UART2,
-                .uartclk        = 2*1843200,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-        {
-                .membase        = (void*)SERIAL3_VIRT,
-                .mapbase        = SERIAL3_BASE,
-                .irq            = IRQ_UART3,
-                .uartclk        = 2*1843200,
-                .regshift       = 2,
-                .iotype         = UPIO_MEM,
-                .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST,
-        },
-#endif
-        { },
-};
-
-static struct platform_device serial_device = {
-        .name                   = "serial8250",
-        .id                     = PLAT8250_DEV_PLATFORM,
-        .dev                    = {
-                .platform_data  = serial_platform_data,
-        },
-};
-
-static struct platform_device *devices[] __initdata = {
-        &h7202ps2_device,
-        &serial_device,
-};
-
-/* Although we have two interrupt lines for the timers, we only have one
- * status register which clears all pending timer interrupts on reading. So
- * we have to handle all timer interrupts in one place.
- */
-static void
-h7202_timerx_demux_handler(unsigned int irq_unused, struct irq_desc *desc)
-{
-        unsigned int mask, irq;
-
-        mask = CPU_REG (TIMER_VIRT, TIMER_TOPSTAT);
-
-        if ( mask & TSTAT_T0INT ) {
-                timer_tick();
-                if( mask == TSTAT_T0INT )
-                        return;
-        }
-
-        mask >>= 1;
-        irq = IRQ_TIMER1;
-        while (mask) {
-                if (mask & 1)
-                        generic_handle_irq(irq);
-                irq++;
-                mask >>= 1;
-        }
-}
-
-/*
- * Timer interrupt handler
- */
-static irqreturn_t
-h7202_timer_interrupt(int irq, void *dev_id)
-{
-        h7202_timerx_demux_handler(0, NULL);
-        return IRQ_HANDLED;
-}
-
-/*
- * mask multiplexed timer IRQs
- */
-static void inline __mask_timerx_irq(unsigned int irq)
-{
-        unsigned int bit;
-        bit = 2 << ((irq == IRQ_TIMER64B) ? 4 : (irq - IRQ_TIMER1));
-        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) &= ~bit;
-}
-
-static void inline mask_timerx_irq(struct irq_data *d)
-{
-        __mask_timerx_irq(d->irq);
-}
-
-/*
- * unmask multiplexed timer IRQs
- */
-static void inline unmask_timerx_irq(struct irq_data *d)
-{
-        unsigned int bit;
-        bit = 2 << ((d->irq == IRQ_TIMER64B) ? 4 : (d->irq - IRQ_TIMER1));
-        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) |= bit;
-}
-
-static struct irq_chip h7202_timerx_chip = {
-        .irq_ack = mask_timerx_irq,
-        .irq_mask = mask_timerx_irq,
-        .irq_unmask = unmask_timerx_irq,
-};
-
-static struct irqaction h7202_timer_irq = {
-        .name           = "h7202 Timer Tick",
-        .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler        = h7202_timer_interrupt,
-};
-
-/*
- * Setup TIMER0 as system timer
- */
-void __init h7202_timer_init(void)
-{
-        arch_gettimeoffset = h720x_gettimeoffset;
-
-        CPU_REG (TIMER_VIRT, TM0_PERIOD) = LATCH;
-        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_RESET;
-        CPU_REG (TIMER_VIRT, TM0_CTRL) = TM_REPEAT | TM_START;
-        CPU_REG (TIMER_VIRT, TIMER_TOPCTRL) = ENABLE_TM0_INTR | TIMER_ENABLE_BIT;
-
-        setup_irq(IRQ_TIMER0, &h7202_timer_irq);
-}
-
-void __init h7202_init_irq (void)
-{
-        int     irq;
-
-        CPU_REG (GPIO_E_VIRT, GPIO_MASK) = 0x0;
-
-        for (irq = IRQ_TIMER1;
-                          irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
-                __mask_timerx_irq(irq);
-                irq_set_chip_and_handler(irq, &h7202_timerx_chip,
-                                         handle_edge_irq);
-                set_irq_flags(irq, IRQF_VALID );
-        }
-        irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
-
-        h720x_init_irq();
-}
-
-void __init init_hw_h7202(void)
-{
-        /* Enable clocks */
-        CPU_REG (PMU_BASE, PMU_PLL_CTRL) |= PLL_2_EN | PLL_1_EN | PLL_3_MUTE;
-
-        CPU_REG (SERIAL0_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
-        CPU_REG (SERIAL1_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
-#ifdef CONFIG_H7202_SERIAL23
-        CPU_REG (SERIAL2_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
-        CPU_REG (SERIAL3_VIRT, SERIAL_ENABLE) = SERIAL_ENABLE_EN;
-        CPU_IO (GPIO_AMULSEL) = AMULSEL_USIN2 | AMULSEL_USOUT2 |
-                                AMULSEL_USIN3 | AMULSEL_USOUT3;
-#endif
-        (void) platform_add_devices(devices, ARRAY_SIZE(devices));
-}
diff --git a/arch/arm/mach-h720x/h7201-eval.c b/arch/arm/mach-h720x/h7201-eval.c
deleted file mode 100644
index 4fdeb686c0a9..000000000000
--- a/arch/arm/mach-h720x/h7201-eval.c
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/h7201-eval.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * Architecture specific stuff for Hynix GMS30C7201 development board
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/device.h>
-
-#include <asm/setup.h>
-#include <asm/types.h>
-#include <asm/mach-types.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <mach/hardware.h>
-#include "common.h"
-
-MACHINE_START(H7201, "Hynix GMS30C7201")
-        /* Maintainer: Robert Schwebel, Pengutronix */
-        .atag_offset    = 0x1000,
-        .map_io         = h720x_map_io,
-        .init_irq       = h720x_init_irq,
-        .init_time      = h7201_timer_init,
-        .dma_zone_size  = SZ_256M,
-        .restart        = h720x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-h720x/h7202-eval.c b/arch/arm/mach-h720x/h7202-eval.c
deleted file mode 100644
index f68e967a2062..000000000000
--- a/arch/arm/mach-h720x/h7202-eval.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * linux/arch/arm/mach-h720x/h7202-eval.c
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *               2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *               2004 Sascha Hauer <s.hauer@pengutronix.de>
- *
- * Architecture specific stuff for Hynix HMS30C7202 development board
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- */
-
-#include <linux/init.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-#include <linux/string.h>
-#include <linux/platform_device.h>
-
-#include <asm/setup.h>
-#include <asm/types.h>
-#include <asm/mach-types.h>
-#include <asm/page.h>
-#include <asm/mach/arch.h>
-#include <mach/irqs.h>
-#include <mach/hardware.h>
-#include "common.h"
-
-static struct resource cirrus_resources[] = {
-        [0] = {
-                .start  = ETH0_PHYS + 0x300,
-                .end    = ETH0_PHYS + 0x300 + 0x10,
-                .flags  = IORESOURCE_MEM,
-        },
-        [1] = {
-                .start  = IRQ_CHAINED_GPIOB(8),
-                .end    = IRQ_CHAINED_GPIOB(8),
-                .flags  = IORESOURCE_IRQ,
-        },
-};
-
-static struct platform_device cirrus_device = {
-        .name           = "cirrus-cs89x0",
-        .id             = -1,
-        .num_resources  = ARRAY_SIZE(cirrus_resources),
-        .resource       = cirrus_resources,
-};
-
-static struct platform_device *devices[] __initdata = {
-        &cirrus_device,
-};
-
-/*
- * Hardware init. This is called early in initcalls
- * Place pin inits here. So you avoid adding ugly
- * #ifdef stuff to common drivers.
- * Use this only, if your bootloader is not able
- * to initialize the pins proper.
- */
-static void __init init_eval_h7202(void)
-{
-        init_hw_h7202();
-        (void) platform_add_devices(devices, ARRAY_SIZE(devices));
-
-        /* Enable interrupt on portb bit 8 (ethernet) */
-        CPU_REG (GPIO_B_VIRT, GPIO_POL) &= ~(1 << 8);
-        CPU_REG (GPIO_B_VIRT, GPIO_EN) |= (1 << 8);
-}
-
-MACHINE_START(H7202, "Hynix HMS30C7202")
-        /* Maintainer: Robert Schwebel, Pengutronix */
-        .atag_offset    = 0x100,
-        .map_io         = h720x_map_io,
-        .init_irq       = h7202_init_irq,
-        .init_time      = h7202_timer_init,
-        .init_machine   = init_eval_h7202,
-        .dma_zone_size  = SZ_256M,
-        .restart        = h720x_restart,
-MACHINE_END
diff --git a/arch/arm/mach-h720x/include/mach/boards.h b/arch/arm/mach-h720x/include/mach/boards.h
deleted file mode 100644
index 38b8e0d61fbf..000000000000
--- a/arch/arm/mach-h720x/include/mach/boards.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/boards.h
- *
- * Copyright (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *
- * This file contains the board specific defines for various devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_INCMACH_H
-#error Do not include this file directly. Include asm/hardware.h instead !
-#endif
-
-/* Hynix H7202 developer board specific device defines */
-#ifdef CONFIG_ARCH_H7202
-
-/* FLASH */
-#define H720X_FLASH_VIRT        0xd0000000
-#define H720X_FLASH_PHYS        0x00000000
-#define H720X_FLASH_SIZE        0x02000000
-
-/* onboard LAN controller */
-# define ETH0_PHYS              0x08000000
-
-/* Touch screen defines */
-/* GPIO Port */
-#define PEN_GPIO                GPIO_B_VIRT
-/* Bitmask for pen down interrupt */
-#define PEN_INT_BIT             (1<<7)
-/* Bitmask for pen up interrupt */
-#define PEN_ENA_BIT             (1<<6)
-/* pen up interrupt */
-#define IRQ_PEN                 IRQ_MUX_GPIOB(7)
-
-#endif
-
-/* Hynix H7201 developer board specific device defines */
-#if defined (CONFIG_ARCH_H7201)
-/* ROM DISK SPACE */
-#define ROM_DISK_BASE           0xc1800000
-#define ROM_DISK_START          0x41800000
-#define ROM_DISK_SIZE           0x00700000
-
-/* SRAM DISK SPACE */
-#define SRAM_DISK_BASE          0xf1000000
-#define SRAM_DISK_START         0x04000000
-#define SRAM_DISK_SIZE          0x00400000
-#endif
-
diff --git a/arch/arm/mach-h720x/include/mach/debug-macro.S b/arch/arm/mach-h720x/include/mach/debug-macro.S
deleted file mode 100644
index 8a46157b0582..000000000000
--- a/arch/arm/mach-h720x/include/mach/debug-macro.S
+++ /dev/null
@@ -1,40 +0,0 @@
-/* arch/arm/mach-h720x/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#include <mach/hardware.h>
-
-                .equ    io_virt, IO_VIRT
-                .equ    io_phys, IO_PHYS
-
-                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0x00020000        @ UART1
-                add     \rv, \rp, #io_virt      @ virtual address
-                add     \rp, \rp, #io_phys      @ physical base address
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0]        @ UARTDR
-
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 5           @ UARTFLGUTXFF - 1 when full
-                bne     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 3           @ UARTFLGUBUSY - 1 when busy
-                bne     1001b
-                .endm
diff --git a/arch/arm/mach-h720x/include/mach/entry-macro.S b/arch/arm/mach-h720x/include/mach/entry-macro.S
deleted file mode 100644
index 75267fad7012..000000000000
--- a/arch/arm/mach-h720x/include/mach/entry-macro.S
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/entry-macro.S
- *
- * Low-level IRQ helper macros for Hynix HMS720x based platforms
- *
- * This file is licensed under  the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-                .macro  get_irqnr_preamble, base, tmp
-                .endm
-
-                .macro  get_irqnr_and_base, irqnr, irqstat, base, tmp
-#if defined (CONFIG_CPU_H7201) || defined (CONFIG_CPU_H7202)
-                @ we could use the id register on H7202, but this is not
-                @ properly updated when we come back from asm_do_irq
-                @ without a previous return from interrupt
-                @ (see loops below in irq_svc, irq_usr)
-                @ We see unmasked pending ints only, as the masked pending ints
-                @ are not visible here
-
-                mov     \base, #0xf0000000             @ base register
-                orr     \base, \base, #0x24000         @ irqbase
-                ldr     \irqstat, [\base, #0x04]        @ get interrupt status
-#if defined (CONFIG_CPU_H7201)
-                ldr     \tmp, =0x001fffff
-#else
-                mvn     \tmp, #0xc0000000
-#endif
-                and     \irqstat, \irqstat, \tmp        @ mask out unused ints
-                mov     \irqnr, #0
-
-                mov     \tmp, #0xff00
-                orr     \tmp, \tmp, #0xff
-                tst     \irqstat, \tmp
-                addeq   \irqnr, \irqnr, #16
-                moveq   \irqstat, \irqstat, lsr #16
-                tst     \irqstat, #255
-                addeq   \irqnr, \irqnr, #8
-                moveq   \irqstat, \irqstat, lsr #8
-                tst     \irqstat, #15
-                addeq   \irqnr, \irqnr, #4
-                moveq   \irqstat, \irqstat, lsr #4
-                tst     \irqstat, #3
-                addeq   \irqnr, \irqnr, #2
-                moveq   \irqstat, \irqstat, lsr #2
-                tst     \irqstat, #1
-                addeq   \irqnr, \irqnr, #1
-                moveq   \irqstat, \irqstat, lsr #1
-                tst     \irqstat, #1                   @ bit 0 should be set
-                .endm
-
-#else
-#error hynix processor selection missmatch
-#endif
-
diff --git a/arch/arm/mach-h720x/include/mach/h7201-regs.h b/arch/arm/mach-h720x/include/mach/h7201-regs.h
deleted file mode 100644
index 611b4947ccfc..000000000000
--- a/arch/arm/mach-h720x/include/mach/h7201-regs.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/h7201-regs.h
- *
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * This file contains the hardware definitions of the h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Do not add implementations specific defines here. This files contains
- * only defines of the onchip peripherals. Add those defines to boards.h,
- * which is included by this file.
- */
-
-#define SERIAL2_VIRT            (IO_VIRT + 0x50100)
-#define SERIAL3_VIRT            (IO_VIRT + 0x50200)
-
-/*
- * PCMCIA
- */
-#define PCMCIA0_ATT_BASE        0xe5000000
-#define PCMCIA0_ATT_SIZE        0x00200000
-#define PCMCIA0_ATT_START       0x20000000
-#define PCMCIA0_MEM_BASE        0xe5200000
-#define PCMCIA0_MEM_SIZE        0x00200000
-#define PCMCIA0_MEM_START       0x24000000
-#define PCMCIA0_IO_BASE         0xe5400000
-#define PCMCIA0_IO_SIZE         0x00200000
-#define PCMCIA0_IO_START        0x28000000
-
-#define PCMCIA1_ATT_BASE        0xe5600000
-#define PCMCIA1_ATT_SIZE        0x00200000
-#define PCMCIA1_ATT_START       0x30000000
-#define PCMCIA1_MEM_BASE        0xe5800000
-#define PCMCIA1_MEM_SIZE        0x00200000
-#define PCMCIA1_MEM_START       0x34000000
-#define PCMCIA1_IO_BASE         0xe5a00000
-#define PCMCIA1_IO_SIZE         0x00200000
-#define PCMCIA1_IO_START        0x38000000
-
-#define PRIME3C_BASE            0xf0050000
-#define PRIME3C_SIZE            0x00001000
-#define PRIME3C_START           0x10000000
-
-/* VGA Controller */
-#define VGA_RAMBASE             0x50
-#define VGA_TIMING0             0x60
-#define VGA_TIMING1             0x64
-#define VGA_TIMING2             0x68
-#define VGA_TIMING3             0x6c
-
-#define LCD_CTRL_VGA_ENABLE     0x00000100
-#define LCD_CTRL_VGA_BPP_MASK   0x00000600
-#define LCD_CTRL_VGA_4BPP       0x00000000
-#define LCD_CTRL_VGA_8BPP       0x00000200
-#define LCD_CTRL_VGA_16BPP      0x00000300
-#define LCD_CTRL_SHARE_DMA      0x00000800
-#define LCD_CTRL_VDE            0x00100000
-#define LCD_CTRL_LPE            0x00400000      /* LCD Power enable */
-#define LCD_CTRL_BLE            0x00800000      /* LCD backlight enable */
-
-#define VGA_PALETTE_BASE        (IO_VIRT + 0x10800)
diff --git a/arch/arm/mach-h720x/include/mach/h7202-regs.h b/arch/arm/mach-h720x/include/mach/h7202-regs.h
deleted file mode 100644
index 17c12eb34995..000000000000
--- a/arch/arm/mach-h720x/include/mach/h7202-regs.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/h7202-regs.h
- *
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *           (C) 2004 Sascha Hauer    <s.hauer@pengutronix.de>
- *
- * This file contains the hardware definitions of the h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Do not add implementations specific defines here. This files contains
- * only defines of the onchip peripherals. Add those defines to boards.h,
- * which is included by this file.
- */
-
-#define SERIAL2_OFS             0x2d000
-#define SERIAL2_BASE            (IO_PHYS + SERIAL2_OFS)
-#define SERIAL2_VIRT            (IO_VIRT + SERIAL2_OFS)
-#define SERIAL3_OFS             0x2e000
-#define SERIAL3_BASE            (IO_PHYS + SERIAL3_OFS)
-#define SERIAL3_VIRT            (IO_VIRT + SERIAL3_OFS)
-
-/* Matrix Keyboard Controller */
-#define KBD_VIRT                (IO_VIRT + 0x22000)
-#define KBD_KBCR                0x00
-#define KBD_KBSC                0x04
-#define KBD_KBTR                0x08
-#define KBD_KBVR0               0x0C
-#define KBD_KBVR1               0x10
-#define KBD_KBSR                0x18
-
-#define KBD_KBCR_SCANENABLE     (1 << 7)
-#define KBD_KBCR_NPOWERDOWN     (1 << 2)
-#define KBD_KBCR_CLKSEL_MASK    (3)
-#define KBD_KBCR_CLKSEL_PCLK2   0x0
-#define KBD_KBCR_CLKSEL_PCLK128 0x1
-#define KBD_KBCR_CLKSEL_PCLK256 0x2
-#define KBD_KBCR_CLKSEL_PCLK512 0x3
-
-#define KBD_KBSR_INTR           (1 << 0)
-#define KBD_KBSR_WAKEUP         (1 << 1)
-
-/* USB device controller */
-
-#define USBD_BASE               (IO_VIRT + 0x12000)
-#define USBD_LENGTH             0x3C
-
-#define USBD_GCTRL              0x00
-#define USBD_EPCTRL             0x04
-#define USBD_INTMASK            0x08
-#define USBD_INTSTAT            0x0C
-#define USBD_PWR                0x10
-#define USBD_DMARXTX            0x14
-#define USBD_DEVID              0x18
-#define USBD_DEVCLASS           0x1C
-#define USBD_INTCLASS           0x20
-#define USBD_SETUP0             0x24
-#define USBD_SETUP1             0x28
-#define USBD_ENDP0RD            0x2C
-#define USBD_ENDP0WT            0x30
-#define USBD_ENDP1RD            0x34
-#define USBD_ENDP2WT            0x38
-
-/* PS/2 port */
-#define PSDATA 0x00
-#define PSSTAT 0x04
-#define PSSTAT_TXEMPTY (1<<0)
-#define PSSTAT_TXBUSY (1<<1)
-#define PSSTAT_RXFULL (1<<2)
-#define PSSTAT_RXBUSY (1<<3)
-#define PSSTAT_CLKIN (1<<4)
-#define PSSTAT_DATAIN (1<<5)
-#define PSSTAT_PARITY (1<<6)
-
-#define PSCONF 0x08
-#define PSCONF_ENABLE (1<<0)
-#define PSCONF_TXINTEN (1<<2)
-#define PSCONF_RXINTEN (1<<3)
-#define PSCONF_FORCECLKLOW (1<<4)
-#define PSCONF_FORCEDATLOW (1<<5)
-#define PSCONF_LCE (1<<6)
-
-#define PSINTR 0x0C
-#define PSINTR_TXINT (1<<0)
-#define PSINTR_RXINT (1<<1)
-#define PSINTR_PAR (1<<2)
-#define PSINTR_RXTO (1<<3)
-#define PSINTR_TXTO (1<<4)
-
-#define PSTDLO 0x10 /* clk low before start transmission */
-#define PSTPRI 0x14 /* PRI clock */
-#define PSTXMT 0x18 /* maximum transmission time */
-#define PSTREC 0x20 /* maximum receive time */
-#define PSPWDN 0x3c
-
-/* ADC converter */
-#define ADC_BASE                (IO_VIRT + 0x29000)
-#define ADC_CR                  0x00
-#define ADC_TSCTRL              0x04
-#define ADC_BT_CTRL             0x08
-#define ADC_MC_CTRL             0x0C
-#define ADC_STATUS              0x10
-
-/* ADC control register bits */
-#define ADC_CR_PW_CTRL          0x80
-#define ADC_CR_DIRECTC          0x04
-#define ADC_CR_CONTIME_NO       0x00
-#define ADC_CR_CONTIME_2        0x04
-#define ADC_CR_CONTIME_4        0x08
-#define ADC_CR_CONTIME_ADE      0x0c
-#define ADC_CR_LONGCALTIME      0x01
-
-/* ADC touch panel register bits */
-#define ADC_TSCTRL_ENABLE       0x80
-#define ADC_TSCTRL_INTR         0x40
-#define ADC_TSCTRL_SWBYPSS      0x20
-#define ADC_TSCTRL_SWINVT       0x10
-#define ADC_TSCTRL_S400         0x03
-#define ADC_TSCTRL_S200         0x02
-#define ADC_TSCTRL_S100         0x01
-#define ADC_TSCTRL_S50          0x00
-
-/* ADC Interrupt Status Register bits */
-#define ADC_STATUS_TS_BIT       0x80
-#define ADC_STATUS_MBT_BIT      0x40
-#define ADC_STATUS_BBT_BIT      0x20
-#define ADC_STATUS_MIC_BIT      0x10
-
-/* Touch data registers */
-#define ADC_TS_X0X1             0x30
-#define ADC_TS_X2X3             0x34
-#define ADC_TS_Y0Y1             0x38
-#define ADC_TS_Y2Y3             0x3c
-#define ADC_TS_X4X5             0x40
-#define ADC_TS_X6X7             0x44
-#define ADC_TS_Y4Y5             0x48
-#define ADC_TS_Y6Y7             0x50
-
-/* battery data */
-#define ADC_MB_DATA             0x54
-#define ADC_BB_DATA             0x58
-
-/* Sound data register */
-#define ADC_SD_DAT0             0x60
-#define ADC_SD_DAT1             0x64
-#define ADC_SD_DAT2             0x68
-#define ADC_SD_DAT3             0x6c
-#define ADC_SD_DAT4             0x70
-#define ADC_SD_DAT5             0x74
-#define ADC_SD_DAT6             0x78
-#define ADC_SD_DAT7             0x7c
diff --git a/arch/arm/mach-h720x/include/mach/hardware.h b/arch/arm/mach-h720x/include/mach/hardware.h
deleted file mode 100644
index c55a52c6541d..000000000000
--- a/arch/arm/mach-h720x/include/mach/hardware.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/hardware.h
- *
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *
- * This file contains the hardware definitions of the h720x processors
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Do not add implementations specific defines here. This files contains
- * only defines of the onchip peripherals. Add those defines to boards.h,
- * which is included by this file.
- */
-
-#ifndef __ASM_ARCH_HARDWARE_H
-#define __ASM_ARCH_HARDWARE_H
-
-#define IOCLK (3686400L)
-
-/* Onchip peripherals */
-
-#define IO_VIRT                 0xf0000000      /* IO peripherals */
-#define IO_PHYS                 0x80000000
-#define IO_SIZE                 0x00050000
-
-#ifdef CONFIG_CPU_H7202
-#include "h7202-regs.h"
-#elif defined CONFIG_CPU_H7201
-#include "h7201-regs.h"
-#else
-#error machine definition mismatch
-#endif
-
-/* Macro to access the CPU IO */
-#define CPU_IO(x) (*(volatile u32*)(x))
-
-/* Macro to access general purpose regs (base, offset) */
-#define CPU_REG(x,y) CPU_IO(x+y)
-
-/* Macro to access irq related regs */
-#define IRQ_REG(x) CPU_REG(IRQC_VIRT,x)
-
-/* CPU registers */
-/* general purpose I/O */
-#define GPIO_VIRT(x)            (IO_VIRT + 0x23000 + ((x)<<5))
-#define GPIO_A_VIRT             (GPIO_VIRT(0))
-#define GPIO_B_VIRT             (GPIO_VIRT(1))
-#define GPIO_C_VIRT             (GPIO_VIRT(2))
-#define GPIO_D_VIRT             (GPIO_VIRT(3))
-#define GPIO_E_VIRT             (GPIO_VIRT(4))
-#define GPIO_AMULSEL            (GPIO_VIRT(0) + 0xA4)
-
-#define AMULSEL_USIN2   (1<<5)
-#define AMULSEL_USOUT2  (1<<6)
-#define AMULSEL_USIN3   (1<<13)
-#define AMULSEL_USOUT3  (1<<14)
-#define AMULSEL_IRDIN   (1<<15)
-#define AMULSEL_IRDOUT  (1<<7)
-
-/* Register offsets general purpose I/O */
-#define GPIO_DATA               0x00
-#define GPIO_DIR                0x04
-#define GPIO_MASK               0x08
-#define GPIO_STAT               0x0C
-#define GPIO_EDGE               0x10
-#define GPIO_CLR                0x14
-#define GPIO_POL                0x18
-#define GPIO_EN                 0x1C
-
-/*interrupt controller */
-#define IRQC_VIRT               (IO_VIRT + 0x24000)
-/* register offset interrupt controller */
-#define IRQC_IER                0x00
-#define IRQC_ISR                0x04
-
-/* timer unit */
-#define TIMER_VIRT              (IO_VIRT + 0x25000)
-/* Register offsets timer unit */
-#define TM0_PERIOD              0x00
-#define TM0_COUNT               0x08
-#define TM0_CTRL                0x10
-#define TM1_PERIOD              0x20
-#define TM1_COUNT               0x28
-#define TM1_CTRL                0x30
-#define TM2_PERIOD              0x40
-#define TM2_COUNT               0x48
-#define TM2_CTRL                0x50
-#define TIMER_TOPCTRL           0x60
-#define TIMER_TOPSTAT           0x64
-#define T64_COUNTL              0x80
-#define T64_COUNTH              0x84
-#define T64_CTRL                0x88
-#define T64_BASEL               0x94
-#define T64_BASEH               0x98
-/* Bitmaks timer unit TOPSTAT reg */
-#define TSTAT_T0INT             0x1
-#define TSTAT_T1INT             0x2
-#define TSTAT_T2INT             0x4
-#define TSTAT_T3INT             0x8
-/* Bit description of TMx_CTRL register */
-#define TM_START                0x1
-#define TM_REPEAT               0x2
-#define TM_RESET                0x4
-/* Bit description of TIMER_CTRL register */
-#define ENABLE_TM0_INTR         0x1
-#define ENABLE_TM1_INTR         0x2
-#define ENABLE_TM2_INTR         0x4
-#define TIMER_ENABLE_BIT        0x8
-#define ENABLE_TIMER64          0x10
-#define ENABLE_TIMER64_INT      0x20
-
-/* PMU & PLL */
-#define PMU_BASE                (IO_VIRT + 0x1000)
-#define PMU_MODE                0x00
-#define PMU_STAT                0x20
-#define PMU_PLL_CTRL            0x28
-
-/* PMU Mode bits */
-#define PMU_MODE_SLOW           0x00
-#define PMU_MODE_RUN            0x01
-#define PMU_MODE_IDLE           0x02
-#define PMU_MODE_SLEEP          0x03
-#define PMU_MODE_INIT           0x04
-#define PMU_MODE_DEEPSLEEP      0x07
-#define PMU_MODE_WAKEUP         0x08
-
-/* PMU ... */
-#define PLL_2_EN                0x8000
-#define PLL_1_EN                0x4000
-#define PLL_3_MUTE              0x0080
-
-/* Control bits for PMU/ PLL */
-#define PMU_WARMRESET           0x00010000
-#define PLL_CTRL_MASK23         0x000080ff
-
-/* LCD Controller */
-#define LCD_BASE                (IO_VIRT + 0x10000)
-#define LCD_CTRL                0x00
-#define LCD_STATUS              0x04
-#define LCD_STATUS_M            0x08
-#define LCD_INTERRUPT           0x0C
-#define LCD_DBAR                0x10
-#define LCD_DCAR                0x14
-#define LCD_TIMING0             0x20
-#define LCD_TIMING1             0x24
-#define LCD_TIMING2             0x28
-#define LCD_TEST                0x40
-
-/* LCD Control Bits */
-#define LCD_CTRL_LCD_ENABLE     0x00000001
-/* Bits per pixel */
-#define LCD_CTRL_LCD_BPP_MASK   0x00000006
-#define LCD_CTRL_LCD_4BPP       0x00000000
-#define LCD_CTRL_LCD_8BPP       0x00000002
-#define LCD_CTRL_LCD_16BPP      0x00000004
-#define LCD_CTRL_LCD_BW         0x00000008
-#define LCD_CTRL_LCD_TFT        0x00000010
-#define LCD_CTRL_BGR            0x00001000
-#define LCD_CTRL_LCD_VCOMP      0x00080000
-#define LCD_CTRL_LCD_MONO8      0x00200000
-#define LCD_CTRL_LCD_PWR        0x00400000
-#define LCD_CTRL_LCD_BLE        0x00800000
-#define LCD_CTRL_LDBUSEN        0x01000000
-
-/* Palette */
-#define LCD_PALETTE_BASE        (IO_VIRT + 0x10400)
-
-/* Serial ports */
-#define SERIAL0_OFS             0x20000
-#define SERIAL0_VIRT            (IO_VIRT + SERIAL0_OFS)
-#define SERIAL0_BASE            (IO_PHYS + SERIAL0_OFS)
-
-#define SERIAL1_OFS             0x21000
-#define SERIAL1_VIRT            (IO_VIRT + SERIAL1_OFS)
-#define SERIAL1_BASE            (IO_PHYS + SERIAL1_OFS)
-
-#define SERIAL_ENABLE           0x30
-#define SERIAL_ENABLE_EN        (1<<0)
-
-/* General defines to pacify gcc */
-
-#define __ASM_ARCH_HARDWARE_INCMACH_H
-#include "boards.h"
-#undef __ASM_ARCH_HARDWARE_INCMACH_H
-
-#endif                          /* __ASM_ARCH_HARDWARE_H */
diff --git a/arch/arm/mach-h720x/include/mach/irqs.h b/arch/arm/mach-h720x/include/mach/irqs.h
deleted file mode 100644
index 430a92b492f1..000000000000
--- a/arch/arm/mach-h720x/include/mach/irqs.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/irqs.h
- *
- * Copyright (C) 2000 Jungjun Kim
- *           (C) 2003 Robert Schwebel <r.schwebel@pengutronix.de>
- *           (C) 2003 Thomas Gleixner <tglx@linutronix.de>
- *
- */
-
-#ifndef __ASM_ARCH_IRQS_H
-#define __ASM_ARCH_IRQS_H
-
-#if defined (CONFIG_CPU_H7201)
-
-#define IRQ_PMU         0               /* 0x000001 */
-#define IRQ_DMA         1               /* 0x000002 */
-#define IRQ_LCD         2               /* 0x000004 */
-#define IRQ_VGA         3               /* 0x000008 */
-#define IRQ_PCMCIA1     4               /* 0x000010 */
-#define IRQ_PCMCIA2     5               /* 0x000020 */
-#define IRQ_AFE         6               /* 0x000040 */
-#define IRQ_AIC         7               /* 0x000080 */
-#define IRQ_KEYBOARD    8               /* 0x000100 */
-#define IRQ_TIMER0      9               /* 0x000200 */
-#define IRQ_RTC         10              /* 0x000400 */
-#define IRQ_SOUND       11              /* 0x000800 */
-#define IRQ_USB         12              /* 0x001000 */
-#define IRQ_IrDA        13              /* 0x002000 */
-#define IRQ_UART0       14              /* 0x004000 */
-#define IRQ_UART1       15              /* 0x008000 */
-#define IRQ_SPI         16              /* 0x010000 */
-#define IRQ_GPIOA       17              /* 0x020000 */
-#define IRQ_GPIOB       18              /* 0x040000 */
-#define IRQ_GPIOC       19              /* 0x080000 */
-#define IRQ_GPIOD       20              /* 0x100000 */
-#define IRQ_CommRX      21              /* 0x200000 */
-#define IRQ_CommTX      22              /* 0x400000 */
-#define IRQ_Soft        23              /* 0x800000 */
-
-#define NR_GLBL_IRQS    24
-
-#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
-#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
-#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
-#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
-#define NR_IRQS               IRQ_CHAINED_GPIOD(32)
-
-/* Enable mask for multiplexed interrupts */
-#define IRQ_ENA_MUX     (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) \
-                        | (1<<IRQ_GPIOC) | (1<<IRQ_GPIOD)
-
-
-#elif defined (CONFIG_CPU_H7202)
-
-#define IRQ_PMU         0               /* 0x00000001 */
-#define IRQ_DMA         1               /* 0x00000002 */
-#define IRQ_LCD         2               /* 0x00000004 */
-#define IRQ_SOUND       3               /* 0x00000008 */
-#define IRQ_I2S         4               /* 0x00000010 */
-#define IRQ_USB         5               /* 0x00000020 */
-#define IRQ_MMC         6               /* 0x00000040 */
-#define IRQ_RTC         7               /* 0x00000080 */
-#define IRQ_UART0       8               /* 0x00000100 */
-#define IRQ_UART1       9               /* 0x00000200 */
-#define IRQ_UART2       10              /* 0x00000400 */
-#define IRQ_UART3       11              /* 0x00000800 */
-#define IRQ_KBD         12              /* 0x00001000 */
-#define IRQ_PS2         13              /* 0x00002000 */
-#define IRQ_AIC         14              /* 0x00004000 */
-#define IRQ_TIMER0      15              /* 0x00008000 */
-#define IRQ_TIMERX      16              /* 0x00010000 */
-#define IRQ_WDT         17              /* 0x00020000 */
-#define IRQ_CAN0        18              /* 0x00040000 */
-#define IRQ_CAN1        19              /* 0x00080000 */
-#define IRQ_EXT0        20              /* 0x00100000 */
-#define IRQ_EXT1        21              /* 0x00200000 */
-#define IRQ_GPIOA       22              /* 0x00400000 */
-#define IRQ_GPIOB       23              /* 0x00800000 */
-#define IRQ_GPIOC       24              /* 0x01000000 */
-#define IRQ_GPIOD       25              /* 0x02000000 */
-#define IRQ_GPIOE       26              /* 0x04000000 */
-#define IRQ_COMMRX      27              /* 0x08000000 */
-#define IRQ_COMMTX      28              /* 0x10000000 */
-#define IRQ_SMC         29              /* 0x20000000 */
-#define IRQ_Soft        30              /* 0x40000000 */
-#define IRQ_RESERVED1   31              /* 0x80000000 */
-#define NR_GLBL_IRQS    32
-
-#define NR_TIMERX_IRQS  3
-
-#define IRQ_CHAINED_GPIOA(x)  (NR_GLBL_IRQS + x)
-#define IRQ_CHAINED_GPIOB(x)  (IRQ_CHAINED_GPIOA(32) + x)
-#define IRQ_CHAINED_GPIOC(x)  (IRQ_CHAINED_GPIOB(32) + x)
-#define IRQ_CHAINED_GPIOD(x)  (IRQ_CHAINED_GPIOC(32) + x)
-#define IRQ_CHAINED_GPIOE(x)  (IRQ_CHAINED_GPIOD(32) + x)
-#define IRQ_CHAINED_TIMERX(x) (IRQ_CHAINED_GPIOE(32) + x)
-#define IRQ_TIMER1            (IRQ_CHAINED_TIMERX(0))
-#define IRQ_TIMER2            (IRQ_CHAINED_TIMERX(1))
-#define IRQ_TIMER64B          (IRQ_CHAINED_TIMERX(2))
-
-#define NR_IRQS         (IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS))
-
-/* Enable mask for multiplexed interrupts */
-#define IRQ_ENA_MUX     (1<<IRQ_TIMERX) | (1<<IRQ_GPIOA) | (1<<IRQ_GPIOB) | \
-                        (1<<IRQ_GPIOC)  | (1<<IRQ_GPIOD) | (1<<IRQ_GPIOE) | \
-                        (1<<IRQ_TIMERX)
-
-#else
-#error cpu definition mismatch
-#endif
-
-/* decode irq number to register number */
-#define IRQ_TO_REGNO(irq) ((irq - NR_GLBL_IRQS) >> 5)
-#define IRQ_TO_BIT(irq) (1 << ((irq - NR_GLBL_IRQS) % 32))
-
-#endif
diff --git a/arch/arm/mach-h720x/include/mach/isa-dma.h b/arch/arm/mach-h720x/include/mach/isa-dma.h
deleted file mode 100644
index 3eafb3f163c0..000000000000
--- a/arch/arm/mach-h720x/include/mach/isa-dma.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/isa-dma.h
- *
- * Architecture DMA routes
- *
- * Copyright (C) 1997.1998 Russell King
- */
-#ifndef __ASM_ARCH_DMA_H
-#define __ASM_ARCH_DMA_H
-
-#if defined (CONFIG_CPU_H7201)
-#define MAX_DMA_CHANNELS        3
-#elif defined (CONFIG_CPU_H7202)
-#define MAX_DMA_CHANNELS        4
-#else
-#error processor definition missmatch
-#endif
-
-#endif /* __ASM_ARCH_DMA_H */
diff --git a/arch/arm/mach-h720x/include/mach/uncompress.h b/arch/arm/mach-h720x/include/mach/uncompress.h
deleted file mode 100644
index 43e343c4b50a..000000000000
--- a/arch/arm/mach-h720x/include/mach/uncompress.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * arch/arm/mach-h720x/include/mach/uncompress.h
- *
- * Copyright (C) 2001-2002 Jungjun Kim
- */
-
-#ifndef __ASM_ARCH_UNCOMPRESS_H
-#define __ASM_ARCH_UNCOMPRESS_H
-
-#include <mach/hardware.h>
-
-#define LSR     0x14
-#define TEMPTY  0x40
-
-static inline void putc(int c)
-{
-        volatile unsigned char *p = (volatile unsigned char *)(IO_PHYS+0x20000);
-
-        /* wait until transmit buffer is empty */
-        while((p[LSR] & TEMPTY) == 0x0)
-                barrier();
-
-        /* write next character */
-        *p = c;
-}
-
-static inline void flush(void)
-{
-}
-
-/*
- * nothing to do
- */
-#define arch_decomp_setup()
-
-#endif
diff --git a/arch/arm/mach-highbank/highbank.c b/arch/arm/mach-highbank/highbank.c
index a4f9f50247d4..76c1170b3528 100644
--- a/arch/arm/mach-highbank/highbank.c
+++ b/arch/arm/mach-highbank/highbank.c
@@ -32,7 +32,6 @@
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
 #include <asm/smp_plat.h>
-#include <asm/smp_twd.h>
 #include <asm/hardware/arm_timer.h>
 #include <asm/hardware/timer-sp.h>
 #include <asm/hardware/cache-l2x0.h>
@@ -119,10 +118,10 @@ static void __init highbank_timer_init(void)
         sp804_clocksource_and_sched_clock_init(timer_base + 0x20, "timer1");
         sp804_clockevents_init(timer_base, irq, "timer0");
 
-        twd_local_timer_of_register();
-
         arch_timer_of_register();
         arch_timer_sched_clock_init();
+
+        clocksource_of_init();
 }
 
 static void highbank_power_off(void)
diff --git a/arch/arm/mach-highbank/platsmp.c b/arch/arm/mach-highbank/platsmp.c
index 8797a7001720..a984573e0d02 100644
--- a/arch/arm/mach-highbank/platsmp.c
+++ b/arch/arm/mach-highbank/platsmp.c
@@ -17,7 +17,6 @@
 #include <linux/init.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/smp_scu.h>
 
@@ -25,11 +24,6 @@
 
 extern void secondary_startup(void);
 
-static void __cpuinit highbank_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 static int __cpuinit highbank_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         highbank_set_cpu_jump(cpu, secondary_startup);
@@ -67,7 +61,6 @@ static void __init highbank_smp_prepare_cpus(unsigned int max_cpus)
 struct smp_operations highbank_smp_ops __initdata = {
         .smp_init_cpus          = highbank_smp_init_cpus,
         .smp_prepare_cpus       = highbank_smp_prepare_cpus,
-        .smp_secondary_init     = highbank_secondary_init,
         .smp_boot_secondary     = highbank_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = highbank_cpu_die,
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 4c9c6f9d2c55..6575e4ebe26e 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -83,24 +83,12 @@ config ARCH_MXC_IOMUX_V3
 config ARCH_MX1
         bool
 
-config MACH_MX21
-        bool
-
 config ARCH_MX25
         bool
 
 config MACH_MX27
         bool
 
-config ARCH_MX5
-        bool
-
-config ARCH_MX51
-        bool
-
-config ARCH_MX53
-        bool
-
 config SOC_IMX1
         bool
         select ARCH_MX1
@@ -114,7 +102,6 @@ config SOC_IMX21
         select COMMON_CLK
         select CPU_ARM926T
         select IMX_HAVE_IOMUX_V1
-        select MACH_MX21
         select MXC_AVIC
 
 config SOC_IMX25
@@ -155,7 +142,6 @@ config SOC_IMX35
 config SOC_IMX5
         bool
         select ARCH_HAS_CPUFREQ
-        select ARCH_MX5
         select ARCH_MXC_IOMUX_V3
         select COMMON_CLK
         select CPU_V7
@@ -163,8 +149,6 @@ config SOC_IMX5
 
 config  SOC_IMX51
         bool
-        select ARCH_MX5
-        select ARCH_MX51
         select PINCTRL
         select PINCTRL_IMX51
         select SOC_IMX5
@@ -789,8 +773,6 @@ comment "Device tree only"
 
 config  SOC_IMX53
         bool "i.MX53 support"
-        select ARCH_MX5
-        select ARCH_MX53
         select HAVE_CAN_FLEXCAN if CAN
         select IMX_HAVE_PLATFORM_IMX2_WDT
         select PINCTRL
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index cb70961b6239..fbe60a145344 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -12,7 +12,7 @@ obj-$(CONFIG_SOC_IMX31) += mm-imx3.o cpu-imx31.o clk-imx31.o iomux-imx31.o ehci-
 obj-$(CONFIG_SOC_IMX35) += mm-imx3.o cpu-imx35.o clk-imx35.o ehci-imx35.o pm-imx3.o
 
 imx5-pm-$(CONFIG_PM) += pm-imx5.o
-obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y) cpu_op-mx51.o
+obj-$(CONFIG_SOC_IMX5) += cpu-imx5.o mm-imx5.o clk-imx51-imx53.o ehci-imx5.o $(imx5-pm-y)
 
 obj-$(CONFIG_COMMON_CLK) += clk-pllv1.o clk-pllv2.o clk-pllv3.o clk-gate2.o \
                             clk-pfd.o clk-busy.o clk.o
@@ -27,7 +27,6 @@ obj-$(CONFIG_IRAM_ALLOC) += iram_alloc.o
 obj-$(CONFIG_MXC_ULPI) += ulpi.o
 obj-$(CONFIG_MXC_USE_EPIT) += epit.o
 obj-$(CONFIG_MXC_DEBUG_BOARD) += 3ds_debugboard.o
-obj-$(CONFIG_CPU_FREQ_IMX)    += cpufreq.o
 
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_SOC_IMX5) += cpuidle-imx5.o
diff --git a/arch/arm/mach-imx/Makefile.boot b/arch/arm/mach-imx/Makefile.boot
deleted file mode 100644
index 41ba1bb0437b..000000000000
--- a/arch/arm/mach-imx/Makefile.boot
+++ /dev/null
@@ -1,35 +0,0 @@
-zreladdr-$(CONFIG_SOC_IMX1)     += 0x08008000
-params_phys-$(CONFIG_SOC_IMX1)  := 0x08000100
-initrd_phys-$(CONFIG_SOC_IMX1)  := 0x08800000
-
-zreladdr-$(CONFIG_SOC_IMX21)    += 0xC0008000
-params_phys-$(CONFIG_SOC_IMX21) := 0xC0000100
-initrd_phys-$(CONFIG_SOC_IMX21) := 0xC0800000
-
-zreladdr-$(CONFIG_SOC_IMX25)    += 0x80008000
-params_phys-$(CONFIG_SOC_IMX25) := 0x80000100
-initrd_phys-$(CONFIG_SOC_IMX25) := 0x80800000
-
-zreladdr-$(CONFIG_SOC_IMX27)    += 0xA0008000
-params_phys-$(CONFIG_SOC_IMX27) := 0xA0000100
-initrd_phys-$(CONFIG_SOC_IMX27) := 0xA0800000
-
-zreladdr-$(CONFIG_SOC_IMX31)    += 0x80008000
-params_phys-$(CONFIG_SOC_IMX31) := 0x80000100
-initrd_phys-$(CONFIG_SOC_IMX31) := 0x80800000
-
-zreladdr-$(CONFIG_SOC_IMX35)    += 0x80008000
-params_phys-$(CONFIG_SOC_IMX35) := 0x80000100
-initrd_phys-$(CONFIG_SOC_IMX35) := 0x80800000
-
-zreladdr-$(CONFIG_SOC_IMX51)    += 0x90008000
-params_phys-$(CONFIG_SOC_IMX51) := 0x90000100
-initrd_phys-$(CONFIG_SOC_IMX51) := 0x90800000
-
-zreladdr-$(CONFIG_SOC_IMX53)    += 0x70008000
-params_phys-$(CONFIG_SOC_IMX53) := 0x70000100
-initrd_phys-$(CONFIG_SOC_IMX53) := 0x70800000
-
-zreladdr-$(CONFIG_SOC_IMX6Q)    += 0x10008000
-params_phys-$(CONFIG_SOC_IMX6Q) := 0x10000100
-initrd_phys-$(CONFIG_SOC_IMX6Q) := 0x10800000
diff --git a/arch/arm/mach-imx/avic.c b/arch/arm/mach-imx/avic.c
index 9c3e014705b1..e163ec7a8441 100644
--- a/arch/arm/mach-imx/avic.c
+++ b/arch/arm/mach-imx/avic.c
@@ -54,8 +54,6 @@
 static void __iomem *avic_base;
 static struct irq_domain *domain;
 
-static u32 avic_saved_mask_reg[2];
-
 #ifdef CONFIG_MXC_IRQ_PRIOR
 static int avic_irq_set_priority(unsigned char irq, unsigned char prio)
 {
@@ -113,6 +111,8 @@ static struct mxc_extra_irq avic_extra_irq = {
 };
 
 #ifdef CONFIG_PM
+static u32 avic_saved_mask_reg[2];
+
 static void avic_irq_suspend(struct irq_data *d)
 {
         struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
diff --git a/arch/arm/mach-imx/clk-imx27.c b/arch/arm/mach-imx/clk-imx27.c
index 30b3242a7d49..8e3b65719106 100644
--- a/arch/arm/mach-imx/clk-imx27.c
+++ b/arch/arm/mach-imx/clk-imx27.c
@@ -278,8 +278,6 @@ int __init mx27_clocks_init(unsigned long fref)
         clk_register_clkdev(clk[scc_ipg_gate], "scc", NULL);
         clk_register_clkdev(clk[cpu_div], "cpu", NULL);
         clk_register_clkdev(clk[emi_ahb_gate], "emi_ahb" , NULL);
-        clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
-        clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
 
         mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
 
diff --git a/arch/arm/mach-imx/common.h b/arch/arm/mach-imx/common.h
index 5bf4a97ab241..9fea2522d7a3 100644
--- a/arch/arm/mach-imx/common.h
+++ b/arch/arm/mach-imx/common.h
@@ -113,7 +113,6 @@ extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 extern u32 imx_get_cpu_arg(int cpu);
 extern void imx_set_cpu_arg(int cpu, u32 arg);
 extern void v7_cpu_resume(void);
-extern u32 *pl310_get_save_ptr(void);
 #ifdef CONFIG_SMP
 extern void v7_secondary_startup(void);
 extern void imx_scu_map_io(void);
@@ -124,8 +123,6 @@ static inline void imx_scu_map_io(void) {}
 static inline void imx_smp_prepare(void) {}
 static inline void imx_scu_standby_enable(void) {}
 #endif
-extern void imx_enable_cpu(int cpu, bool enable);
-extern void imx_set_cpu_jump(int cpu, void *jump_addr);
 extern void imx_src_init(void);
 extern void imx_src_prepare_restart(void);
 extern void imx_gpc_init(void);
diff --git a/arch/arm/mach-imx/cpu_op-mx51.c b/arch/arm/mach-imx/cpu_op-mx51.c
deleted file mode 100644
index b9ef692b61a2..000000000000
--- a/arch/arm/mach-imx/cpu_op-mx51.c
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#include <linux/bug.h>
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include "hardware.h"
-
-static struct cpu_op mx51_cpu_op[] = {
-        {
-        .cpu_rate = 160000000,},
-        {
-        .cpu_rate = 800000000,},
-};
-
-struct cpu_op *mx51_get_cpu_op(int *op)
-{
-        *op = ARRAY_SIZE(mx51_cpu_op);
-        return mx51_cpu_op;
-}
diff --git a/arch/arm/mach-imx/cpu_op-mx51.h b/arch/arm/mach-imx/cpu_op-mx51.h
deleted file mode 100644
index 97477fecb469..000000000000
--- a/arch/arm/mach-imx/cpu_op-mx51.h
+++ /dev/null
@@ -1,14 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-extern struct cpu_op *mx51_get_cpu_op(int *op);
diff --git a/arch/arm/mach-imx/cpufreq.c b/arch/arm/mach-imx/cpufreq.c
deleted file mode 100644
index 387dc4cceca2..000000000000
--- a/arch/arm/mach-imx/cpufreq.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-/*
- * A driver for the Freescale Semiconductor i.MXC CPUfreq module.
- * The CPUFREQ driver is for controlling CPU frequency. It allows you to change
- * the CPU clock speed on the fly.
- */
-
-#include <linux/module.h>
-#include <linux/cpufreq.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/slab.h>
-
-#include "hardware.h"
-
-#define CLK32_FREQ      32768
-#define NANOSECOND      (1000 * 1000 * 1000)
-
-struct cpu_op *(*get_cpu_op)(int *op);
-
-static int cpu_freq_khz_min;
-static int cpu_freq_khz_max;
-
-static struct clk *cpu_clk;
-static struct cpufreq_frequency_table *imx_freq_table;
-
-static int cpu_op_nr;
-static struct cpu_op *cpu_op_tbl;
-
-static int set_cpu_freq(int freq)
-{
-        int ret = 0;
-        int org_cpu_rate;
-
-        org_cpu_rate = clk_get_rate(cpu_clk);
-        if (org_cpu_rate == freq)
-                return ret;
-
-        ret = clk_set_rate(cpu_clk, freq);
-        if (ret != 0) {
-                printk(KERN_DEBUG "cannot set CPU clock rate\n");
-                return ret;
-        }
-
-        return ret;
-}
-
-static int mxc_verify_speed(struct cpufreq_policy *policy)
-{
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        return cpufreq_frequency_table_verify(policy, imx_freq_table);
-}
-
-static unsigned int mxc_get_speed(unsigned int cpu)
-{
-        if (cpu)
-                return 0;
-
-        return clk_get_rate(cpu_clk) / 1000;
-}
-
-static int mxc_set_target(struct cpufreq_policy *policy,
-                          unsigned int target_freq, unsigned int relation)
-{
-        struct cpufreq_freqs freqs;
-        int freq_Hz;
-        int ret = 0;
-        unsigned int index;
-
-        cpufreq_frequency_table_target(policy, imx_freq_table,
-                        target_freq, relation, &index);
-        freq_Hz = imx_freq_table[index].frequency * 1000;
-
-        freqs.old = clk_get_rate(cpu_clk) / 1000;
-        freqs.new = freq_Hz / 1000;
-        freqs.flags = 0;
-        cpufreq_notify_transition(policy, &freqs, CPUFREQ_PRECHANGE);
-
-        ret = set_cpu_freq(freq_Hz);
-
-        cpufreq_notify_transition(policy, &freqs, CPUFREQ_POSTCHANGE);
-
-        return ret;
-}
-
-static int mxc_cpufreq_init(struct cpufreq_policy *policy)
-{
-        int ret;
-        int i;
-
-        printk(KERN_INFO "i.MXC CPU frequency driver\n");
-
-        if (policy->cpu != 0)
-                return -EINVAL;
-
-        if (!get_cpu_op)
-                return -EINVAL;
-
-        cpu_clk = clk_get(NULL, "cpu_clk");
-        if (IS_ERR(cpu_clk)) {
-                printk(KERN_ERR "%s: failed to get cpu clock\n", __func__);
-                return PTR_ERR(cpu_clk);
-        }
-
-        cpu_op_tbl = get_cpu_op(&cpu_op_nr);
-
-        cpu_freq_khz_min = cpu_op_tbl[0].cpu_rate / 1000;
-        cpu_freq_khz_max = cpu_op_tbl[0].cpu_rate / 1000;
-
-        imx_freq_table = kmalloc(
-                sizeof(struct cpufreq_frequency_table) * (cpu_op_nr + 1),
-                        GFP_KERNEL);
-        if (!imx_freq_table) {
-                ret = -ENOMEM;
-                goto err1;
-        }
-
-        for (i = 0; i < cpu_op_nr; i++) {
-                imx_freq_table[i].index = i;
-                imx_freq_table[i].frequency = cpu_op_tbl[i].cpu_rate / 1000;
-
-                if ((cpu_op_tbl[i].cpu_rate / 1000) < cpu_freq_khz_min)
-                        cpu_freq_khz_min = cpu_op_tbl[i].cpu_rate / 1000;
-
-                if ((cpu_op_tbl[i].cpu_rate / 1000) > cpu_freq_khz_max)
-                        cpu_freq_khz_max = cpu_op_tbl[i].cpu_rate / 1000;
-        }
-
-        imx_freq_table[i].index = i;
-        imx_freq_table[i].frequency = CPUFREQ_TABLE_END;
-
-        policy->cur = clk_get_rate(cpu_clk) / 1000;
-
-        /* Manual states, that PLL stabilizes in two CLK32 periods */
-        policy->cpuinfo.transition_latency = 2 * NANOSECOND / CLK32_FREQ;
-
-        ret = cpufreq_frequency_table_cpuinfo(policy, imx_freq_table);
-        if (ret < 0) {
-                printk(KERN_ERR "%s: failed to register i.MXC CPUfreq with error code %d\n",
-                       __func__, ret);
-                goto err;
-        }
-
-        cpufreq_frequency_table_get_attr(imx_freq_table, policy->cpu);
-        return 0;
-err:
-        kfree(imx_freq_table);
-err1:
-        clk_put(cpu_clk);
-        return ret;
-}
-
-static int mxc_cpufreq_exit(struct cpufreq_policy *policy)
-{
-        cpufreq_frequency_table_put_attr(policy->cpu);
-
-        set_cpu_freq(cpu_freq_khz_max * 1000);
-        clk_put(cpu_clk);
-        kfree(imx_freq_table);
-        return 0;
-}
-
-static struct cpufreq_driver mxc_driver = {
-        .flags = CPUFREQ_STICKY,
-        .verify = mxc_verify_speed,
-        .target = mxc_set_target,
-        .get = mxc_get_speed,
-        .init = mxc_cpufreq_init,
-        .exit = mxc_cpufreq_exit,
-        .name = "imx",
-};
-
-static int mxc_cpufreq_driver_init(void)
-{
-        return cpufreq_register_driver(&mxc_driver);
-}
-
-static void mxc_cpufreq_driver_exit(void)
-{
-        cpufreq_unregister_driver(&mxc_driver);
-}
-
-module_init(mxc_cpufreq_driver_init);
-module_exit(mxc_cpufreq_driver_exit);
-
-MODULE_AUTHOR("Freescale Semiconductor Inc. Yong Shen <yong.shen@linaro.org>");
-MODULE_DESCRIPTION("CPUfreq driver for i.MX");
-MODULE_LICENSE("GPL");
diff --git a/arch/arm/mach-imx/devices/Kconfig b/arch/arm/mach-imx/devices/Kconfig
index 9b9ba1f4ffe1..3dd2b1b041d1 100644
--- a/arch/arm/mach-imx/devices/Kconfig
+++ b/arch/arm/mach-imx/devices/Kconfig
@@ -86,7 +86,3 @@ config IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX
 
 config IMX_HAVE_PLATFORM_SPI_IMX
         bool
-
-config IMX_HAVE_PLATFORM_AHCI
-        bool
-        default y if ARCH_MX53
diff --git a/arch/arm/mach-imx/devices/Makefile b/arch/arm/mach-imx/devices/Makefile
index 6acf37e0c119..67416fb1dc69 100644
--- a/arch/arm/mach-imx/devices/Makefile
+++ b/arch/arm/mach-imx/devices/Makefile
@@ -29,5 +29,4 @@ obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_RTC) += platform-mxc_rtc.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MXC_W1) += platform-mxc_w1.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SDHCI_ESDHC_IMX) += platform-sdhci-esdhc-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_SPI_IMX) +=  platform-spi_imx.o
-obj-$(CONFIG_IMX_HAVE_PLATFORM_AHCI) +=  platform-ahci-imx.o
 obj-$(CONFIG_IMX_HAVE_PLATFORM_MX2_EMMA) += platform-mx2-emma.o
diff --git a/arch/arm/mach-imx/devices/devices-common.h b/arch/arm/mach-imx/devices/devices-common.h
index 9bd5777ff0e7..453e20bc2657 100644
--- a/arch/arm/mach-imx/devices/devices-common.h
+++ b/arch/arm/mach-imx/devices/devices-common.h
@@ -344,13 +344,3 @@ struct platform_device *imx_add_imx_dma(char *name, resource_size_t iobase,
                                         int irq, int irq_err);
 struct platform_device *imx_add_imx_sdma(char *name,
         resource_size_t iobase, int irq, struct sdma_platform_data *pdata);
-
-#include <linux/ahci_platform.h>
-struct imx_ahci_imx_data {
-        const char *devid;
-        resource_size_t iobase;
-        resource_size_t irq;
-};
-struct platform_device *__init imx_add_ahci_imx(
-                const struct imx_ahci_imx_data *data,
-                const struct ahci_platform_data *pdata);
diff --git a/arch/arm/mach-imx/devices/platform-ahci-imx.c b/arch/arm/mach-imx/devices/platform-ahci-imx.c
deleted file mode 100644
index 3d87dd9c284a..000000000000
--- a/arch/arm/mach-imx/devices/platform-ahci-imx.c
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
-
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
-
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/err.h>
-#include <linux/device.h>
-#include <linux/dma-mapping.h>
-#include <asm/sizes.h>
-
-#include "../hardware.h"
-#include "devices-common.h"
-
-#define imx_ahci_imx_data_entry_single(soc, _devid)             \
-        {                                                               \
-                .devid = _devid,                                        \
-                .iobase = soc ## _SATA_BASE_ADDR,                       \
-                .irq = soc ## _INT_SATA,                                \
-        }
-
-#ifdef CONFIG_SOC_IMX53
-const struct imx_ahci_imx_data imx53_ahci_imx_data __initconst =
-        imx_ahci_imx_data_entry_single(MX53, "imx53-ahci");
-#endif
-
-enum {
-        HOST_CAP = 0x00,
-        HOST_CAP_SSS = (1 << 27), /* Staggered Spin-up */
-        HOST_PORTS_IMPL = 0x0c,
-        HOST_TIMER1MS = 0xe0, /* Timer 1-ms */
-};
-
-static struct clk *sata_clk, *sata_ref_clk;
-
-/* AHCI module Initialization, if return 0, initialization is successful. */
-static int imx_sata_init(struct device *dev, void __iomem *addr)
-{
-        u32 tmpdata;
-        int ret = 0;
-        struct clk *clk;
-
-        sata_clk = clk_get(dev, "ahci");
-        if (IS_ERR(sata_clk)) {
-                dev_err(dev, "no sata clock.\n");
-                return PTR_ERR(sata_clk);
-        }
-        ret = clk_prepare_enable(sata_clk);
-        if (ret) {
-                dev_err(dev, "can't prepare/enable sata clock.\n");
-                goto put_sata_clk;
-        }
-
-        /* Get the AHCI SATA PHY CLK */
-        sata_ref_clk = clk_get(dev, "ahci_phy");
-        if (IS_ERR(sata_ref_clk)) {
-                dev_err(dev, "no sata ref clock.\n");
-                ret = PTR_ERR(sata_ref_clk);
-                goto release_sata_clk;
-        }
-        ret = clk_prepare_enable(sata_ref_clk);
-        if (ret) {
-                dev_err(dev, "can't prepare/enable sata ref clock.\n");
-                goto put_sata_ref_clk;
-        }
-
-        /* Get the AHB clock rate, and configure the TIMER1MS reg later */
-        clk = clk_get(dev, "ahci_dma");
-        if (IS_ERR(clk)) {
-                dev_err(dev, "no dma clock.\n");
-                ret = PTR_ERR(clk);
-                goto release_sata_ref_clk;
-        }
-        tmpdata = clk_get_rate(clk) / 1000;
-        clk_put(clk);
-
-        writel(tmpdata, addr + HOST_TIMER1MS);
-
-        tmpdata = readl(addr + HOST_CAP);
-        if (!(tmpdata & HOST_CAP_SSS)) {
-                tmpdata |= HOST_CAP_SSS;
-                writel(tmpdata, addr + HOST_CAP);
-        }
-
-        if (!(readl(addr + HOST_PORTS_IMPL) & 0x1))
-                writel((readl(addr + HOST_PORTS_IMPL) | 0x1),
-                        addr + HOST_PORTS_IMPL);
-
-        return 0;
-
-release_sata_ref_clk:
-        clk_disable_unprepare(sata_ref_clk);
-put_sata_ref_clk:
-        clk_put(sata_ref_clk);
-release_sata_clk:
-        clk_disable_unprepare(sata_clk);
-put_sata_clk:
-        clk_put(sata_clk);
-
-        return ret;
-}
-
-static void imx_sata_exit(struct device *dev)
-{
-        clk_disable_unprepare(sata_ref_clk);
-        clk_put(sata_ref_clk);
-
-        clk_disable_unprepare(sata_clk);
-        clk_put(sata_clk);
-
-}
-struct platform_device *__init imx_add_ahci_imx(
-                const struct imx_ahci_imx_data *data,
-                const struct ahci_platform_data *pdata)
-{
-        struct resource res[] = {
-                {
-                        .start = data->iobase,
-                        .end = data->iobase + SZ_4K - 1,
-                        .flags = IORESOURCE_MEM,
-                }, {
-                        .start = data->irq,
-                        .end = data->irq,
-                        .flags = IORESOURCE_IRQ,
-                },
-        };
-
-        return imx_add_platform_device_dmamask(data->devid, 0,
-                        res, ARRAY_SIZE(res),
-                        pdata, sizeof(*pdata),  DMA_BIT_MASK(32));
-}
-
-struct platform_device *__init imx53_add_ahci_imx(void)
-{
-        struct ahci_platform_data pdata = {
-                .init = imx_sata_init,
-                .exit = imx_sata_exit,
-        };
-
-        return imx_add_ahci_imx(&imx53_ahci_imx_data, &pdata);
-}
diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
index 911e9b31b03f..356131f7b591 100644
--- a/arch/arm/mach-imx/hardware.h
+++ b/arch/arm/mach-imx/hardware.h
@@ -102,7 +102,6 @@
 
 #include "mxc.h"
 
-#include "mx6q.h"
 #include "mx51.h"
 #include "mx53.h"
 #include "mx3x.h"
diff --git a/arch/arm/mach-imx/mach-cpuimx51sd.c b/arch/arm/mach-imx/mach-cpuimx51sd.c
index 9b7393234f6f..9b5ddf5bbd33 100644
--- a/arch/arm/mach-imx/mach-cpuimx51sd.c
+++ b/arch/arm/mach-imx/mach-cpuimx51sd.c
@@ -33,7 +33,6 @@
 
 #include "common.h"
 #include "devices-imx51.h"
-#include "cpu_op-mx51.h"
 #include "eukrea-baseboards.h"
 #include "hardware.h"
 #include "iomux-mx51.h"
@@ -285,10 +284,6 @@ static void __init eukrea_cpuimx51sd_init(void)
         mxc_iomux_v3_setup_multiple_pads(eukrea_cpuimx51sd_pads,
                                         ARRAY_SIZE(eukrea_cpuimx51sd_pads));
 
-#if defined(CONFIG_CPU_FREQ_IMX)
-        get_cpu_op = mx51_get_cpu_op;
-#endif
-
         imx51_add_imx_uart(0, &uart_pdata);
         imx51_add_mxc_nand(&eukrea_cpuimx51sd_nand_board_info);
         imx51_add_imx2_wdt(0);
diff --git a/arch/arm/mach-imx/mach-imx6q.c b/arch/arm/mach-imx/mach-imx6q.c
index fe1b7aafabdc..99502eeefdf7 100644
--- a/arch/arm/mach-imx/mach-imx6q.c
+++ b/arch/arm/mach-imx/mach-imx6q.c
@@ -12,6 +12,7 @@
 
 #include <linux/clk.h>
 #include <linux/clkdev.h>
+#include <linux/clocksource.h>
 #include <linux/cpu.h>
 #include <linux/delay.h>
 #include <linux/export.h>
@@ -28,11 +29,9 @@
 #include <linux/regmap.h>
 #include <linux/micrel_phy.h>
 #include <linux/mfd/syscon.h>
-#include <asm/smp_twd.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
-#include <asm/mach/time.h>
 #include <asm/system_misc.h>
 
 #include "common.h"
@@ -292,7 +291,7 @@ static void __init imx6q_init_irq(void)
 static void __init imx6q_timer_init(void)
 {
         mx6q_clocks_init();
-        twd_local_timer_of_register();
+        clocksource_of_init();
         imx_print_silicon_rev("i.MX6Q", imx6q_revision());
 }
 
diff --git a/arch/arm/mach-imx/mach-mx51_babbage.c b/arch/arm/mach-imx/mach-mx51_babbage.c
index 6c4d7feb4520..f3d264a636fa 100644
--- a/arch/arm/mach-imx/mach-mx51_babbage.c
+++ b/arch/arm/mach-imx/mach-mx51_babbage.c
@@ -27,7 +27,6 @@
 
 #include "common.h"
 #include "devices-imx51.h"
-#include "cpu_op-mx51.h"
 #include "hardware.h"
 #include "iomux-mx51.h"
 
@@ -371,9 +370,6 @@ static void __init mx51_babbage_init(void)
 
         imx51_soc_init();
 
-#if defined(CONFIG_CPU_FREQ_IMX)
-        get_cpu_op = mx51_get_cpu_op;
-#endif
         imx51_babbage_common_init();
 
         imx51_add_imx_uart(0, &uart_pdata);
diff --git a/arch/arm/mach-imx/mx6q.h b/arch/arm/mach-imx/mx6q.h
deleted file mode 100644
index 19d3f54db5af..000000000000
--- a/arch/arm/mach-imx/mx6q.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2011 Linaro Ltd.
- *
- * The code contained herein is licensed under the GNU General Public
- * License. You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- */
-
-#ifndef __MACH_MX6Q_H__
-#define __MACH_MX6Q_H__
-
-#define MX6Q_IO_P2V(x)                  IMX_IO_P2V(x)
-#define MX6Q_IO_ADDRESS(x)              IOMEM(MX6Q_IO_P2V(x))
-
-/*
- * The following are the blocks that need to be statically mapped.
- * For other blocks, the base address really should be retrieved from
- * device tree.
- */
-#define MX6Q_SCU_BASE_ADDR              0x00a00000
-#define MX6Q_SCU_SIZE                   0x1000
-#define MX6Q_CCM_BASE_ADDR              0x020c4000
-#define MX6Q_CCM_SIZE                   0x4000
-#define MX6Q_ANATOP_BASE_ADDR           0x020c8000
-#define MX6Q_ANATOP_SIZE                0x1000
-
-#endif  /* __MACH_MX6Q_H__ */
diff --git a/arch/arm/mach-imx/platsmp.c b/arch/arm/mach-imx/platsmp.c
index 7c0b03f67b05..77e9a25ed0f6 100644
--- a/arch/arm/mach-imx/platsmp.c
+++ b/arch/arm/mach-imx/platsmp.c
@@ -12,7 +12,6 @@
 
 #include <linux/init.h>
 #include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
 #include <asm/page.h>
 #include <asm/smp_scu.h>
 #include <asm/mach/map.h>
@@ -52,16 +51,6 @@ void imx_scu_standby_enable(void)
         writel_relaxed(val, scu_base);
 }
 
-static void __cpuinit imx_secondary_init(unsigned int cpu)
-{
-        /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-}
-
 static int __cpuinit imx_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         imx_set_cpu_jump(cpu, v7_secondary_startup);
@@ -96,7 +85,6 @@ static void __init imx_smp_prepare_cpus(unsigned int max_cpus)
 struct smp_operations  imx_smp_ops __initdata = {
         .smp_init_cpus          = imx_smp_init_cpus,
         .smp_prepare_cpus       = imx_smp_prepare_cpus,
-        .smp_secondary_init     = imx_secondary_init,
         .smp_boot_secondary     = imx_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = imx_cpu_die,
diff --git a/arch/arm/mach-l7200/include/mach/debug-macro.S b/arch/arm/mach-l7200/include/mach/debug-macro.S
deleted file mode 100644
index 0b4e760159b9..000000000000
--- a/arch/arm/mach-l7200/include/mach/debug-macro.S
+++ /dev/null
@@ -1,38 +0,0 @@
-/* arch/arm/mach-l7200/include/mach/debug-macro.S
- *
- * Debugging macro include header
- *
- *  Copyright (C) 1994-1999 Russell King
- *  Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-                .equ    io_virt, IO_BASE
-                .equ    io_phys, IO_START
-
-                .macro  addruart, rp, rv, tmp
-                mov     \rp, #0x00044000        @ UART1
-@               mov     \rp, #0x00045000        @ UART2
-                add     \rv, \rp, #io_virt      @ virtual address
-                add     \rp, \rp, #io_phys      @ physical base address
-                .endm
-
-                .macro  senduart,rd,rx
-                str     \rd, [\rx, #0x0]        @ UARTDR
-                .endm
-
-                .macro  waituart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 5            @ UARTFLGUTXFF - 1 when full
-                bne     1001b
-                .endm
-
-                .macro  busyuart,rd,rx
-1001:           ldr     \rd, [\rx, #0x18]       @ UARTFLG
-                tst     \rd, #1 << 3            @ UARTFLGUBUSY - 1 when busy
-                bne     1001b
-                .endm
diff --git a/arch/arm/mach-msm/board-halibut.c b/arch/arm/mach-msm/board-halibut.c
index 84d720af34ab..82eaf88d2026 100644
--- a/arch/arm/mach-msm/board-halibut.c
+++ b/arch/arm/mach-msm/board-halibut.c
@@ -59,6 +59,7 @@ static struct platform_device smc91x_device = {
 };
 
 static struct platform_device *devices[] __initdata = {
+        &msm_device_gpio_7201,
         &msm_device_uart3,
         &msm_device_smd,
         &msm_device_nand,
diff --git a/arch/arm/mach-msm/board-msm7x30.c b/arch/arm/mach-msm/board-msm7x30.c
index 7bc3f82e3ec9..520c141acd03 100644
--- a/arch/arm/mach-msm/board-msm7x30.c
+++ b/arch/arm/mach-msm/board-msm7x30.c
@@ -89,6 +89,7 @@ struct msm_gpiomux_config msm_gpiomux_configs[GPIOMUX_NGPIOS] = {
 };
 
 static struct platform_device *devices[] __initdata = {
+        &msm_device_gpio_7x30,
 #if defined(CONFIG_SERIAL_MSM) || defined(CONFIG_MSM_SERIAL_DEBUGGER)
         &msm_device_uart2,
 #endif
diff --git a/arch/arm/mach-msm/board-qsd8x50.c b/arch/arm/mach-msm/board-qsd8x50.c
index 686e7949a73a..38a532d6937c 100644
--- a/arch/arm/mach-msm/board-qsd8x50.c
+++ b/arch/arm/mach-msm/board-qsd8x50.c
@@ -89,6 +89,7 @@ static struct msm_otg_platform_data msm_otg_pdata = {
 };
 
 static struct platform_device *devices[] __initdata = {
+        &msm_device_gpio_8x50,
         &msm_device_uart3,
         &msm_device_smd,
         &msm_device_otg,
diff --git a/arch/arm/mach-msm/board-trout.c b/arch/arm/mach-msm/board-trout.c
index 919bfa32871a..80fe1c5ff5c1 100644
--- a/arch/arm/mach-msm/board-trout.c
+++ b/arch/arm/mach-msm/board-trout.c
@@ -36,6 +36,7 @@
 extern int trout_init_mmc(unsigned int);
 
 static struct platform_device *devices[] __initdata = {
+        &msm_device_gpio_7201,
         &msm_device_uart3,
         &msm_device_smd,
         &msm_device_nand,
diff --git a/arch/arm/mach-msm/devices-msm7x00.c b/arch/arm/mach-msm/devices-msm7x00.c
index f66ee6ea8720..1a0a2306b115 100644
--- a/arch/arm/mach-msm/devices-msm7x00.c
+++ b/arch/arm/mach-msm/devices-msm7x00.c
@@ -29,6 +29,37 @@
 #include "clock-pcom.h"
 #include <linux/platform_data/mmc-msm_sdcc.h>
 
+static struct resource msm_gpio_resources[] = {
+        {
+                .start  = 32 + 0,
+                .end    = 32 + 0,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 32 + 1,
+                .end    = 32 + 1,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 0xa9200800,
+                .end    = 0xa9200800 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio1"
+        },
+        {
+                .start  = 0xa9300C00,
+                .end    = 0xa9300C00 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio2"
+        },
+};
+
+struct platform_device msm_device_gpio_7201 = {
+        .name   = "gpio-msm-7201",
+        .num_resources  = ARRAY_SIZE(msm_gpio_resources),
+        .resource       = msm_gpio_resources,
+};
+
 static struct resource resources_uart1[] = {
         {
                 .start  = INT_UART1,
diff --git a/arch/arm/mach-msm/devices-msm7x30.c b/arch/arm/mach-msm/devices-msm7x30.c
index e90ab5938c5f..12f482c07740 100644
--- a/arch/arm/mach-msm/devices-msm7x30.c
+++ b/arch/arm/mach-msm/devices-msm7x30.c
@@ -33,6 +33,37 @@
 
 #include <linux/platform_data/mmc-msm_sdcc.h>
 
+static struct resource msm_gpio_resources[] = {
+        {
+                .start  = 32 + 18,
+                .end    = 32 + 18,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 32 + 19,
+                .end    = 32 + 19,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 0xac001000,
+                .end    = 0xac001000 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio1"
+        },
+        {
+                .start  = 0xac101400,
+                .end    = 0xac101400 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio2"
+        },
+};
+
+struct platform_device msm_device_gpio_7x30 = {
+        .name   = "gpio-msm-7x30",
+        .num_resources  = ARRAY_SIZE(msm_gpio_resources),
+        .resource       = msm_gpio_resources,
+};
+
 static struct resource resources_uart2[] = {
         {
                 .start  = INT_UART2,
diff --git a/arch/arm/mach-msm/devices-qsd8x50.c b/arch/arm/mach-msm/devices-qsd8x50.c
index 4db61d5fe317..2e1b3ec9dfc7 100644
--- a/arch/arm/mach-msm/devices-qsd8x50.c
+++ b/arch/arm/mach-msm/devices-qsd8x50.c
@@ -30,6 +30,37 @@
 #include <linux/platform_data/mmc-msm_sdcc.h>
 #include "clock-pcom.h"
 
+static struct resource msm_gpio_resources[] = {
+        {
+                .start  = 64 + 165 + 9,
+                .end    = 64 + 165 + 9,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 64 + 165 + 10,
+                .end    = 64 + 165 + 10,
+                .flags  = IORESOURCE_IRQ,
+        },
+        {
+                .start  = 0xa9000800,
+                .end    = 0xa9000800 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio1"
+        },
+        {
+                .start  = 0xa9100C00,
+                .end    = 0xa9100C00 + SZ_4K - 1,
+                .flags  = IORESOURCE_MEM,
+                .name  = "gpio2"
+        },
+};
+
+struct platform_device msm_device_gpio_8x50 = {
+        .name   = "gpio-msm-8x50",
+        .num_resources  = ARRAY_SIZE(msm_gpio_resources),
+        .resource       = msm_gpio_resources,
+};
+
 static struct resource resources_uart3[] = {
         {
                 .start  = INT_UART3,
diff --git a/arch/arm/mach-msm/devices.h b/arch/arm/mach-msm/devices.h
index 9545c196c6e8..da902cf51161 100644
--- a/arch/arm/mach-msm/devices.h
+++ b/arch/arm/mach-msm/devices.h
@@ -20,6 +20,10 @@
 
 #include "clock.h"
 
+extern struct platform_device msm_device_gpio_7201;
+extern struct platform_device msm_device_gpio_7x30;
+extern struct platform_device msm_device_gpio_8x50;
+
 extern struct platform_device msm_device_uart1;
 extern struct platform_device msm_device_uart2;
 extern struct platform_device msm_device_uart3;
diff --git a/arch/arm/mach-msm/dma.c b/arch/arm/mach-msm/dma.c
index 354b91d4c3ac..b279fd8a31b1 100644
--- a/arch/arm/mach-msm/dma.c
+++ b/arch/arm/mach-msm/dma.c
@@ -19,9 +19,35 @@
 #include <linux/interrupt.h>
 #include <linux/completion.h>
 #include <mach/dma.h>
+#include <mach/msm_iomap.h>
 
 #define MSM_DMOV_CHANNEL_COUNT 16
 
+#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
+#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
+#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
+#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
+
+#if defined(CONFIG_ARCH_MSM7X30)
+#define DMOV_SD_AARM DMOV_SD2
+#else
+#define DMOV_SD_AARM DMOV_SD3
+#endif
+
+#define DMOV_CMD_PTR(ch)      DMOV_SD_AARM(0x000, ch)
+#define DMOV_RSLT(ch)         DMOV_SD_AARM(0x040, ch)
+#define DMOV_FLUSH0(ch)       DMOV_SD_AARM(0x080, ch)
+#define DMOV_FLUSH1(ch)       DMOV_SD_AARM(0x0C0, ch)
+#define DMOV_FLUSH2(ch)       DMOV_SD_AARM(0x100, ch)
+#define DMOV_FLUSH3(ch)       DMOV_SD_AARM(0x140, ch)
+#define DMOV_FLUSH4(ch)       DMOV_SD_AARM(0x180, ch)
+#define DMOV_FLUSH5(ch)       DMOV_SD_AARM(0x1C0, ch)
+
+#define DMOV_STATUS(ch)       DMOV_SD_AARM(0x200, ch)
+#define DMOV_ISR              DMOV_SD_AARM(0x380, 0)
+
+#define DMOV_CONFIG(ch)       DMOV_SD_AARM(0x300, ch)
+
 enum {
         MSM_DMOV_PRINT_ERRORS = 1,
         MSM_DMOV_PRINT_IO = 2,
diff --git a/arch/arm/mach-msm/include/mach/cpu.h b/arch/arm/mach-msm/include/mach/cpu.h
deleted file mode 100644
index a9481b08d5c7..000000000000
--- a/arch/arm/mach-msm/include/mach/cpu.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* Copyright (c) 2011, Code Aurora Forum. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
- * 02110-1301, USA.
- */
-
-#ifndef __ARCH_ARM_MACH_MSM_CPU_H__
-#define __ARCH_ARM_MACH_MSM_CPU_H__
-
-/* TODO: For now, only one CPU can be compiled at a time. */
-
-#define cpu_is_msm7x01()        0
-#define cpu_is_msm7x30()        0
-#define cpu_is_qsd8x50()        0
-#define cpu_is_msm8x60()        0
-#define cpu_is_msm8960()        0
-
-#ifdef CONFIG_ARCH_MSM7X00A
-# undef cpu_is_msm7x01
-# define cpu_is_msm7x01()       1
-#endif
-
-#ifdef CONFIG_ARCH_MSM7X30
-# undef cpu_is_msm7x30
-# define cpu_is_msm7x30()       1
-#endif
-
-#ifdef CONFIG_ARCH_QSD8X50
-# undef cpu_is_qsd8x50
-# define cpu_is_qsd8x50()       1
-#endif
-
-#ifdef CONFIG_ARCH_MSM8X60
-# undef cpu_is_msm8x60
-# define cpu_is_msm8x60()       1
-#endif
-
-#ifdef CONFIG_ARCH_MSM8960
-# undef cpu_is_msm8960
-# define cpu_is_msm8960()       1
-#endif
-
-#endif
diff --git a/arch/arm/mach-msm/include/mach/dma.h b/arch/arm/mach-msm/include/mach/dma.h
index 05583f569524..a72d48d42342 100644
--- a/arch/arm/mach-msm/include/mach/dma.h
+++ b/arch/arm/mach-msm/include/mach/dma.h
@@ -16,7 +16,6 @@
 #ifndef __ASM_ARCH_MSM_DMA_H
 
 #include <linux/list.h>
-#include <mach/msm_iomap.h>
 
 struct msm_dmov_errdata {
         uint32_t flush[6];
@@ -45,48 +44,23 @@ static inline
 int msm_dmov_exec_cmd(unsigned id, unsigned int cmdptr) { return -EIO; }
 #endif
 
-
-#define DMOV_SD0(off, ch) (MSM_DMOV_BASE + 0x0000 + (off) + ((ch) << 2))
-#define DMOV_SD1(off, ch) (MSM_DMOV_BASE + 0x0400 + (off) + ((ch) << 2))
-#define DMOV_SD2(off, ch) (MSM_DMOV_BASE + 0x0800 + (off) + ((ch) << 2))
-#define DMOV_SD3(off, ch) (MSM_DMOV_BASE + 0x0C00 + (off) + ((ch) << 2))
-
-#if defined(CONFIG_ARCH_MSM7X30)
-#define DMOV_SD_AARM DMOV_SD2
-#else
-#define DMOV_SD_AARM DMOV_SD3
-#endif
-
-#define DMOV_CMD_PTR(ch)      DMOV_SD_AARM(0x000, ch)
 #define DMOV_CMD_LIST         (0 << 29) /* does not work */
 #define DMOV_CMD_PTR_LIST     (1 << 29) /* works */
 #define DMOV_CMD_INPUT_CFG    (2 << 29) /* untested */
 #define DMOV_CMD_OUTPUT_CFG   (3 << 29) /* untested */
 #define DMOV_CMD_ADDR(addr)   ((addr) >> 3)
 
-#define DMOV_RSLT(ch)         DMOV_SD_AARM(0x040, ch)
 #define DMOV_RSLT_VALID       (1 << 31) /* 0 == host has empties result fifo */
 #define DMOV_RSLT_ERROR       (1 << 3)
 #define DMOV_RSLT_FLUSH       (1 << 2)
 #define DMOV_RSLT_DONE        (1 << 1)  /* top pointer done */
 #define DMOV_RSLT_USER        (1 << 0)  /* command with FR force result */
 
-#define DMOV_FLUSH0(ch)       DMOV_SD_AARM(0x080, ch)
-#define DMOV_FLUSH1(ch)       DMOV_SD_AARM(0x0C0, ch)
-#define DMOV_FLUSH2(ch)       DMOV_SD_AARM(0x100, ch)
-#define DMOV_FLUSH3(ch)       DMOV_SD_AARM(0x140, ch)
-#define DMOV_FLUSH4(ch)       DMOV_SD_AARM(0x180, ch)
-#define DMOV_FLUSH5(ch)       DMOV_SD_AARM(0x1C0, ch)
-
-#define DMOV_STATUS(ch)       DMOV_SD_AARM(0x200, ch)
 #define DMOV_STATUS_RSLT_COUNT(n)    (((n) >> 29))
 #define DMOV_STATUS_CMD_COUNT(n)     (((n) >> 27) & 3)
 #define DMOV_STATUS_RSLT_VALID       (1 << 1)
 #define DMOV_STATUS_CMD_PTR_RDY      (1 << 0)
 
-#define DMOV_ISR              DMOV_SD_AARM(0x380, 0)
-  
-#define DMOV_CONFIG(ch)       DMOV_SD_AARM(0x300, ch)
 #define DMOV_CONFIG_FORCE_TOP_PTR_RSLT (1 << 2)
 #define DMOV_CONFIG_FORCE_FLUSH_RSLT   (1 << 1)
 #define DMOV_CONFIG_IRQ_EN             (1 << 0)
diff --git a/arch/arm/mach-msm/platsmp.c b/arch/arm/mach-msm/platsmp.c
index 42932865416a..00cdb0a5dac8 100644
--- a/arch/arm/mach-msm/platsmp.c
+++ b/arch/arm/mach-msm/platsmp.c
@@ -15,7 +15,6 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/cputype.h>
@@ -42,13 +41,6 @@ static inline int get_core_count(void)
 static void __cpuinit msm_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/mach-mxs/Makefile b/arch/arm/mach-mxs/Makefile
index 3d3c8a973062..80db7269760e 100644
--- a/arch/arm/mach-mxs/Makefile
+++ b/arch/arm/mach-mxs/Makefile
@@ -1,6 +1,2 @@
-# Common support
-obj-y := icoll.o ocotp.o system.o timer.o mm.o
-
 obj-$(CONFIG_PM) += pm.o
-
 obj-$(CONFIG_MACH_MXS_DT) += mach-mxs.o
diff --git a/arch/arm/mach-mxs/include/mach/common.h b/arch/arm/mach-mxs/include/mach/common.h
deleted file mode 100644
index be5a9c93cb2a..000000000000
--- a/arch/arm/mach-mxs/include/mach/common.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- */
-
-/*
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_MXS_COMMON_H__
-#define __MACH_MXS_COMMON_H__
-
-extern const u32 *mxs_get_ocotp(void);
-extern int mxs_reset_block(void __iomem *);
-extern void mxs_timer_init(void);
-extern void mxs_restart(char, const char *);
-extern int mxs_saif_clkmux_select(unsigned int clkmux);
-
-extern int mx23_clocks_init(void);
-extern void mx23_map_io(void);
-
-extern int mx28_clocks_init(void);
-extern void mx28_map_io(void);
-
-extern void icoll_init_irq(void);
-extern void icoll_handle_irq(struct pt_regs *);
-
-#endif /* __MACH_MXS_COMMON_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/debug-macro.S b/arch/arm/mach-mxs/include/mach/debug-macro.S
index 90c6b7836ad3..d86951551ca1 100644
--- a/arch/arm/mach-mxs/include/mach/debug-macro.S
+++ b/arch/arm/mach-mxs/include/mach/debug-macro.S
@@ -11,16 +11,13 @@
  *
  */
 
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-
 #ifdef CONFIG_DEBUG_IMX23_UART
-#define UART_PADDR      MX23_DUART_BASE_ADDR
+#define UART_PADDR      0x80070000
 #elif defined (CONFIG_DEBUG_IMX28_UART)
-#define UART_PADDR      MX28_DUART_BASE_ADDR
+#define UART_PADDR      0x80074000
 #endif
 
-#define UART_VADDR      MXS_IO_ADDRESS(UART_PADDR)
+#define UART_VADDR      0xfe100000
 
                 .macro  addruart, rp, rv, tmp
                 ldr     \rp, =UART_PADDR        @ physical
diff --git a/arch/arm/mach-mxs/include/mach/digctl.h b/arch/arm/mach-mxs/include/mach/digctl.h
deleted file mode 100644
index 17964066303f..000000000000
--- a/arch/arm/mach-mxs/include/mach/digctl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-#ifndef __MACH_DIGCTL_H__
-#define __MACH_DIGCTL_H__
-
-/* MXS DIGCTL SAIF CLKMUX */
-#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT           0x0
-#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT       0x1
-#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
-#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
-
-#define HW_DIGCTL_CTRL                  0x0
-#define  BP_DIGCTL_CTRL_SAIF_CLKMUX     10
-#define  BM_DIGCTL_CTRL_SAIF_CLKMUX     (0x3 << 10)
-#define HW_DIGCTL_CHIPID                0x310
-#endif
diff --git a/arch/arm/mach-mxs/include/mach/hardware.h b/arch/arm/mach-mxs/include/mach/hardware.h
deleted file mode 100644
index 4c0e8a64d8c7..000000000000
--- a/arch/arm/mach-mxs/include/mach/hardware.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
- * MA  02110-1301, USA.
- */
-
-#ifndef __MACH_MXS_HARDWARE_H__
-#define __MACH_MXS_HARDWARE_H__
-
-#endif /* __MACH_MXS_HARDWARE_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx23.h b/arch/arm/mach-mxs/include/mach/mx23.h
deleted file mode 100644
index 599094bc99de..000000000000
--- a/arch/arm/mach-mxs/include/mach/mx23.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_MX23_H__
-#define __MACH_MX23_H__
-
-#include <mach/mxs.h>
-
-/*
- * OCRAM
- */
-#define MX23_OCRAM_BASE_ADDR            0x00000000
-#define MX23_OCRAM_SIZE                 SZ_32K
-
-/*
- * IO
- */
-#define MX23_IO_BASE_ADDR               0x80000000
-#define MX23_IO_SIZE                    SZ_1M
-
-#define MX23_ICOLL_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x000000)
-#define MX23_APBH_DMA_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x004000)
-#define MX23_BCH_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x00a000)
-#define MX23_GPMI_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x00c000)
-#define MX23_SSP1_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x010000)
-#define MX23_PINCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x018000)
-#define MX23_DIGCTL_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x01c000)
-#define MX23_ETM_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x020000)
-#define MX23_APBX_DMA_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x024000)
-#define MX23_DCP_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x028000)
-#define MX23_PXP_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x02a000)
-#define MX23_OCOTP_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x02c000)
-#define MX23_AXI_AHB0_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x02e000)
-#define MX23_LCDIF_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x030000)
-#define MX23_SSP2_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x034000)
-#define MX23_TVENC_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x038000)
-#define MX23_CLKCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x040000)
-#define MX23_SAIF0_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x042000)
-#define MX23_POWER_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x044000)
-#define MX23_SAIF1_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x046000)
-#define MX23_AUDIOOUT_BASE_ADDR         (MX23_IO_BASE_ADDR + 0x048000)
-#define MX23_AUDIOIN_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x04c000)
-#define MX23_LRADC_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x050000)
-#define MX23_SPDIF_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x054000)
-#define MX23_I2C_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x058000)
-#define MX23_RTC_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x05c000)
-#define MX23_PWM_BASE_ADDR              (MX23_IO_BASE_ADDR + 0x064000)
-#define MX23_TIMROT_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x068000)
-#define MX23_AUART1_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x06c000)
-#define MX23_AUART2_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x06e000)
-#define MX23_DUART_BASE_ADDR            (MX23_IO_BASE_ADDR + 0x070000)
-#define MX23_USBPHY_BASE_ADDR           (MX23_IO_BASE_ADDR + 0x07c000)
-#define MX23_USBCTRL_BASE_ADDR          (MX23_IO_BASE_ADDR + 0x080000)
-#define MX23_DRAM_BASE_ADDR             (MX23_IO_BASE_ADDR + 0x0e0000)
-
-#define MX23_IO_P2V(x)                  MXS_IO_P2V(x)
-#define MX23_IO_ADDRESS(x)              IOMEM(MX23_IO_P2V(x))
-
-/*
- * IRQ
- */
-#define MX23_INT_DUART                  0
-#define MX23_INT_COMMS_RX               1
-#define MX23_INT_COMMS_TX               1
-#define MX23_INT_SSP2_ERROR             2
-#define MX23_INT_VDD5V                  3
-#define MX23_INT_HEADPHONE_SHORT        4
-#define MX23_INT_DAC_DMA                5
-#define MX23_INT_DAC_ERROR              6
-#define MX23_INT_ADC_DMA                7
-#define MX23_INT_ADC_ERROR              8
-#define MX23_INT_SPDIF_DMA              9
-#define MX23_INT_SAIF2_DMA              9
-#define MX23_INT_SPDIF_ERROR            10
-#define MX23_INT_SAIF1_IRQ              10
-#define MX23_INT_SAIF2_IRQ              10
-#define MX23_INT_USB_CTRL               11
-#define MX23_INT_USB_WAKEUP             12
-#define MX23_INT_GPMI_DMA               13
-#define MX23_INT_SSP1_DMA               14
-#define MX23_INT_SSP1_ERROR             15
-#define MX23_INT_GPIO0                  16
-#define MX23_INT_GPIO1                  17
-#define MX23_INT_GPIO2                  18
-#define MX23_INT_SAIF1_DMA              19
-#define MX23_INT_SSP2_DMA               20
-#define MX23_INT_ECC8_IRQ               21
-#define MX23_INT_RTC_ALARM              22
-#define MX23_INT_AUART1_TX_DMA          23
-#define MX23_INT_AUART1                 24
-#define MX23_INT_AUART1_RX_DMA          25
-#define MX23_INT_I2C_DMA                26
-#define MX23_INT_I2C_ERROR              27
-#define MX23_INT_TIMER0                 28
-#define MX23_INT_TIMER1                 29
-#define MX23_INT_TIMER2                 30
-#define MX23_INT_TIMER3                 31
-#define MX23_INT_BATT_BRNOUT            32
-#define MX23_INT_VDDD_BRNOUT            33
-#define MX23_INT_VDDIO_BRNOUT           34
-#define MX23_INT_VDD18_BRNOUT           35
-#define MX23_INT_TOUCH_DETECT           36
-#define MX23_INT_LRADC_CH0              37
-#define MX23_INT_LRADC_CH1              38
-#define MX23_INT_LRADC_CH2              39
-#define MX23_INT_LRADC_CH3              40
-#define MX23_INT_LRADC_CH4              41
-#define MX23_INT_LRADC_CH5              42
-#define MX23_INT_LRADC_CH6              43
-#define MX23_INT_LRADC_CH7              44
-#define MX23_INT_LCDIF_DMA              45
-#define MX23_INT_LCDIF_ERROR            46
-#define MX23_INT_DIGCTL_DEBUG_TRAP      47
-#define MX23_INT_RTC_1MSEC              48
-#define MX23_INT_DRI_DMA                49
-#define MX23_INT_DRI_ATTENTION          50
-#define MX23_INT_GPMI_ATTENTION         51
-#define MX23_INT_IR                     52
-#define MX23_INT_DCP_VMI                53
-#define MX23_INT_DCP                    54
-#define MX23_INT_BCH                    56
-#define MX23_INT_PXP                    57
-#define MX23_INT_AUART2_TX_DMA          58
-#define MX23_INT_AUART2                 59
-#define MX23_INT_AUART2_RX_DMA          60
-#define MX23_INT_VDAC_DETECT            61
-#define MX23_INT_VDD5V_DROOP            64
-#define MX23_INT_DCDC4P2_BO             65
-
-/*
- * APBH DMA
- */
-#define MX23_DMA_SSP1                   1
-#define MX23_DMA_SSP2                   2
-#define MX23_DMA_GPMI0                  4
-#define MX23_DMA_GPMI1                  5
-#define MX23_DMA_GPMI2                  6
-#define MX23_DMA_GPMI3                  7
-
-/*
- * APBX DMA
- */
-#define MX23_DMA_ADC                    0
-#define MX23_DMA_DAC                    1
-#define MX23_DMA_SPDIF                  2
-#define MX23_DMA_I2C                    3
-#define MX23_DMA_SAIF0                  4
-#define MX23_DMA_UART0_RX               6
-#define MX23_DMA_UART0_TX               7
-#define MX23_DMA_UART1_RX               8
-#define MX23_DMA_UART1_TX               9
-#define MX23_DMA_SAIF1                  10
-
-#endif /* __MACH_MX23_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mx28.h b/arch/arm/mach-mxs/include/mach/mx28.h
deleted file mode 100644
index 30c7990f3c01..000000000000
--- a/arch/arm/mach-mxs/include/mach/mx28.h
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_MX28_H__
-#define __MACH_MX28_H__
-
-#include <mach/mxs.h>
-
-/*
- * OCRAM
- */
-#define MX28_OCRAM_BASE_ADDR            0x00000000
-#define MX28_OCRAM_SIZE                 SZ_128K
-
-/*
- * IO
- */
-#define MX28_IO_BASE_ADDR               0x80000000
-#define MX28_IO_SIZE                    SZ_1M
-
-#define MX28_ICOLL_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x000000)
-#define MX28_HSADC_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x002000)
-#define MX28_APBH_DMA_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x004000)
-#define MX28_PERFMON_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x006000)
-#define MX28_BCH_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x00a000)
-#define MX28_GPMI_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x00c000)
-#define MX28_SSP0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x010000)
-#define MX28_SSP1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x012000)
-#define MX28_SSP2_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x014000)
-#define MX28_SSP3_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x016000)
-#define MX28_PINCTRL_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x018000)
-#define MX28_DIGCTL_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x01c000)
-#define MX28_ETM_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x022000)
-#define MX28_APBX_DMA_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x024000)
-#define MX28_DCP_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x028000)
-#define MX28_PXP_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x02a000)
-#define MX28_OCOTP_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x02c000)
-#define MX28_AXI_AHB0_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x02e000)
-#define MX28_LCDIF_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x030000)
-#define MX28_CAN0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x032000)
-#define MX28_CAN1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x034000)
-#define MX28_SIMDBG_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x03c000)
-#define MX28_SIMGPMISEL_BASE_ADDR       (MX28_IO_BASE_ADDR + 0x03c200)
-#define MX28_SIMSSPSEL_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x03c300)
-#define MX28_SIMMEMSEL_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x03c400)
-#define MX28_GPIOMON_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c500)
-#define MX28_SIMENET_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c700)
-#define MX28_ARMJTAG_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x03c800)
-#define MX28_CLKCTRL_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x040000)
-#define MX28_SAIF0_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x042000)
-#define MX28_POWER_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x044000)
-#define MX28_SAIF1_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x046000)
-#define MX28_LRADC_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x050000)
-#define MX28_SPDIF_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x054000)
-#define MX28_RTC_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x056000)
-#define MX28_I2C0_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x058000)
-#define MX28_I2C1_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x05a000)
-#define MX28_PWM_BASE_ADDR              (MX28_IO_BASE_ADDR + 0x064000)
-#define MX28_TIMROT_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x068000)
-#define MX28_AUART0_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06a000)
-#define MX28_AUART1_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06c000)
-#define MX28_AUART2_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x06e000)
-#define MX28_AUART3_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x070000)
-#define MX28_AUART4_BASE_ADDR           (MX28_IO_BASE_ADDR + 0x072000)
-#define MX28_DUART_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x074000)
-#define MX28_USBPHY0_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x07C000)
-#define MX28_USBPHY1_BASE_ADDR          (MX28_IO_BASE_ADDR + 0x07e000)
-#define MX28_USBCTRL0_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x080000)
-#define MX28_USBCTRL1_BASE_ADDR         (MX28_IO_BASE_ADDR + 0x090000)
-#define MX28_DFLPT_BASE_ADDR            (MX28_IO_BASE_ADDR + 0x0c0000)
-#define MX28_DRAM_BASE_ADDR             (MX28_IO_BASE_ADDR + 0x0e0000)
-#define MX28_ENET_MAC0_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x0f0000)
-#define MX28_ENET_MAC1_BASE_ADDR        (MX28_IO_BASE_ADDR + 0x0f4000)
-
-#define MX28_IO_P2V(x)                  MXS_IO_P2V(x)
-#define MX28_IO_ADDRESS(x)              IOMEM(MX28_IO_P2V(x))
-
-/*
- * IRQ
- */
-#define MX28_INT_BATT_BRNOUT            0
-#define MX28_INT_VDDD_BRNOUT            1
-#define MX28_INT_VDDIO_BRNOUT           2
-#define MX28_INT_VDDA_BRNOUT            3
-#define MX28_INT_VDD5V_DROOP            4
-#define MX28_INT_DCDC4P2_BRNOUT         5
-#define MX28_INT_VDD5V                  6
-#define MX28_INT_CAN0                   8
-#define MX28_INT_CAN1                   9
-#define MX28_INT_LRADC_TOUCH            10
-#define MX28_INT_HSADC                  13
-#define MX28_INT_LRADC_THRESH0          14
-#define MX28_INT_LRADC_THRESH1          15
-#define MX28_INT_LRADC_CH0              16
-#define MX28_INT_LRADC_CH1              17
-#define MX28_INT_LRADC_CH2              18
-#define MX28_INT_LRADC_CH3              19
-#define MX28_INT_LRADC_CH4              20
-#define MX28_INT_LRADC_CH5              21
-#define MX28_INT_LRADC_CH6              22
-#define MX28_INT_LRADC_CH7              23
-#define MX28_INT_LRADC_BUTTON0          24
-#define MX28_INT_LRADC_BUTTON1          25
-#define MX28_INT_PERFMON                27
-#define MX28_INT_RTC_1MSEC              28
-#define MX28_INT_RTC_ALARM              29
-#define MX28_INT_COMMS                  31
-#define MX28_INT_EMI_ERR                32
-#define MX28_INT_LCDIF                  38
-#define MX28_INT_PXP                    39
-#define MX28_INT_BCH                    41
-#define MX28_INT_GPMI                   42
-#define MX28_INT_SPDIF_ERROR            45
-#define MX28_INT_DUART                  47
-#define MX28_INT_TIMER0                 48
-#define MX28_INT_TIMER1                 49
-#define MX28_INT_TIMER2                 50
-#define MX28_INT_TIMER3                 51
-#define MX28_INT_DCP_VMI                52
-#define MX28_INT_DCP                    53
-#define MX28_INT_DCP_SECURE             54
-#define MX28_INT_SAIF1                  58
-#define MX28_INT_SAIF0                  59
-#define MX28_INT_SPDIF_DMA              66
-#define MX28_INT_I2C0_DMA               68
-#define MX28_INT_I2C1_DMA               69
-#define MX28_INT_AUART0_RX_DMA          70
-#define MX28_INT_AUART0_TX_DMA          71
-#define MX28_INT_AUART1_RX_DMA          72
-#define MX28_INT_AUART1_TX_DMA          73
-#define MX28_INT_AUART2_RX_DMA          74
-#define MX28_INT_AUART2_TX_DMA          75
-#define MX28_INT_AUART3_RX_DMA          76
-#define MX28_INT_AUART3_TX_DMA          77
-#define MX28_INT_AUART4_RX_DMA          78
-#define MX28_INT_AUART4_TX_DMA          79
-#define MX28_INT_SAIF0_DMA              80
-#define MX28_INT_SAIF1_DMA              81
-#define MX28_INT_SSP0_DMA               82
-#define MX28_INT_SSP1_DMA               83
-#define MX28_INT_SSP2_DMA               84
-#define MX28_INT_SSP3_DMA               85
-#define MX28_INT_LCDIF_DMA              86
-#define MX28_INT_HSADC_DMA              87
-#define MX28_INT_GPMI_DMA               88
-#define MX28_INT_DIGCTL_DEBUG_TRAP      89
-#define MX28_INT_USB1                   92
-#define MX28_INT_USB0                   93
-#define MX28_INT_USB1_WAKEUP            94
-#define MX28_INT_USB0_WAKEUP            95
-#define MX28_INT_SSP0_ERROR             96
-#define MX28_INT_SSP1_ERROR             97
-#define MX28_INT_SSP2_ERROR             98
-#define MX28_INT_SSP3_ERROR             99
-#define MX28_INT_ENET_SWI               100
-#define MX28_INT_ENET_MAC0              101
-#define MX28_INT_ENET_MAC1              102
-#define MX28_INT_ENET_MAC0_1588         103
-#define MX28_INT_ENET_MAC1_1588         104
-#define MX28_INT_I2C1_ERROR             110
-#define MX28_INT_I2C0_ERROR             111
-#define MX28_INT_AUART0                 112
-#define MX28_INT_AUART1                 113
-#define MX28_INT_AUART2                 114
-#define MX28_INT_AUART3                 115
-#define MX28_INT_AUART4                 116
-#define MX28_INT_GPIO4                  123
-#define MX28_INT_GPIO3                  124
-#define MX28_INT_GPIO2                  125
-#define MX28_INT_GPIO1                  126
-#define MX28_INT_GPIO0                  127
-
-/*
- * APBH DMA
- */
-#define MX28_DMA_SSP0                   0
-#define MX28_DMA_SSP1                   1
-#define MX28_DMA_SSP2                   2
-#define MX28_DMA_SSP3                   3
-#define MX28_DMA_GPMI0                  4
-#define MX28_DMA_GPMI1                  5
-#define MX28_DMA_GPMI2                  6
-#define MX28_DMA_GPMI3                  7
-#define MX28_DMA_GPMI4                  8
-#define MX28_DMA_GPMI5                  9
-#define MX28_DMA_GPMI6                  10
-#define MX28_DMA_GPMI7                  11
-#define MX28_DMA_HSADC                  12
-#define MX28_DMA_LCDIF                  13
-
-/*
- * APBX DMA
- */
-#define MX28_DMA_AUART4_RX              0
-#define MX28_DMA_AUART4_TX              1
-#define MX28_DMA_SPDIF_TX               2
-#define MX28_DMA_SAIF0                  4
-#define MX28_DMA_SAIF1                  5
-#define MX28_DMA_I2C0                   6
-#define MX28_DMA_I2C1                   7
-#define MX28_DMA_AUART0_RX              8
-#define MX28_DMA_AUART0_TX              9
-#define MX28_DMA_AUART1_RX              10
-#define MX28_DMA_AUART1_TX              11
-#define MX28_DMA_AUART2_RX              12
-#define MX28_DMA_AUART2_TX              13
-#define MX28_DMA_AUART3_RX              14
-#define MX28_DMA_AUART3_TX              15
-
-#endif /* __MACH_MX28_H__ */
diff --git a/arch/arm/mach-mxs/include/mach/mxs.h b/arch/arm/mach-mxs/include/mach/mxs.h
deleted file mode 100644
index 7d4fb6d0afda..000000000000
--- a/arch/arm/mach-mxs/include/mach/mxs.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
- */
-
-#ifndef __MACH_MXS_H__
-#define __MACH_MXS_H__
-
-#ifndef __ASSEMBLER__
-#include <linux/io.h>
-#endif
-#include <asm/mach-types.h>
-#include <mach/digctl.h>
-#include <mach/hardware.h>
-
-/*
- * IO addresses common to MXS-based
- */
-#define MXS_IO_BASE_ADDR                0x80000000
-#define MXS_IO_SIZE                     SZ_1M
-
-#define MXS_ICOLL_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x000000)
-#define MXS_APBH_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x004000)
-#define MXS_BCH_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x00a000)
-#define MXS_GPMI_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x00c000)
-#define MXS_PINCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x018000)
-#define MXS_DIGCTL_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x01c000)
-#define MXS_APBX_DMA_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x024000)
-#define MXS_DCP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x028000)
-#define MXS_PXP_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x02a000)
-#define MXS_OCOTP_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x02c000)
-#define MXS_AXI_AHB0_BASE_ADDR          (MXS_IO_BASE_ADDR + 0x02e000)
-#define MXS_LCDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x030000)
-#define MXS_CLKCTRL_BASE_ADDR           (MXS_IO_BASE_ADDR + 0x040000)
-#define MXS_SAIF0_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x042000)
-#define MXS_POWER_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x044000)
-#define MXS_SAIF1_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x046000)
-#define MXS_LRADC_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x050000)
-#define MXS_SPDIF_BASE_ADDR             (MXS_IO_BASE_ADDR + 0x054000)
-#define MXS_I2C0_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x058000)
-#define MXS_PWM_BASE_ADDR               (MXS_IO_BASE_ADDR + 0x064000)
-#define MXS_TIMROT_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x068000)
-#define MXS_AUART1_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06c000)
-#define MXS_AUART2_BASE_ADDR            (MXS_IO_BASE_ADDR + 0x06e000)
-#define MXS_DRAM_BASE_ADDR              (MXS_IO_BASE_ADDR + 0x0e0000)
-
-/*
- * It maps the whole address space to [0xf4000000, 0xf50fffff].
- *
- *      OCRAM   0x00000000+0x020000     ->      0xf4000000+0x020000
- *      IO      0x80000000+0x100000     ->      0xf5000000+0x100000
- */
-#define MXS_IO_P2V(x)   (0xf4000000 +                                   \
-                        (((x) & 0x80000000) >> 7) +                     \
-                        (((x) & 0x000fffff)))
-
-#define MXS_IO_ADDRESS(x)       IOMEM(MXS_IO_P2V(x))
-
-#define mxs_map_entry(soc, name, _type) {                               \
-        .virtual = soc ## _IO_P2V(soc ## _ ## name ## _BASE_ADDR),      \
-        .pfn = __phys_to_pfn(soc ## _ ## name ## _BASE_ADDR),           \
-        .length = soc ## _ ## name ## _SIZE,                            \
-        .type = _type,                                                  \
-}
-
-#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
-
-#define MXS_SET_ADDR            0x4
-#define MXS_CLR_ADDR            0x8
-#define MXS_TOG_ADDR            0xc
-
-#ifndef __ASSEMBLER__
-static inline void __mxs_setl(u32 mask, void __iomem *reg)
-{
-        __raw_writel(mask, reg + MXS_SET_ADDR);
-}
-
-static inline void __mxs_clrl(u32 mask, void __iomem *reg)
-{
-        __raw_writel(mask, reg + MXS_CLR_ADDR);
-}
-
-static inline void __mxs_togl(u32 mask, void __iomem *reg)
-{
-        __raw_writel(mask, reg + MXS_TOG_ADDR);
-}
-
-/*
- * MXS CPU types
- */
-#define MXS_CHIPID (MXS_IO_ADDRESS(MXS_DIGCTL_BASE_ADDR) + HW_DIGCTL_CHIPID)
-
-static inline int cpu_is_mx23(void)
-{
-        return ((__raw_readl(MXS_CHIPID) >> 16) == 0x3780);
-}
-
-static inline int cpu_is_mx28(void)
-{
-        return ((__raw_readl(MXS_CHIPID) >> 16) == 0x2800);
-}
-#endif
-
-#endif /* __MACH_MXS_H__ */
diff --git a/arch/arm/mach-mxs/mach-mxs.c b/arch/arm/mach-mxs/mach-mxs.c
index e7b781d3788f..16870bf853b8 100644
--- a/arch/arm/mach-mxs/mach-mxs.c
+++ b/arch/arm/mach-mxs/mach-mxs.c
@@ -11,22 +11,53 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk/mxs.h>
 #include <linux/clkdev.h>
+#include <linux/clocksource.h>
 #include <linux/can/platform/flexcan.h>
 #include <linux/delay.h>
 #include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/init.h>
+#include <linux/irqchip.h>
+#include <linux/irqchip/mxs.h>
 #include <linux/micrel_phy.h>
 #include <linux/mxsfb.h>
+#include <linux/of_address.h>
 #include <linux/of_platform.h>
 #include <linux/phy.h>
 #include <linux/pinctrl/consumer.h>
 #include <asm/mach/arch.h>
+#include <asm/mach/map.h>
 #include <asm/mach/time.h>
-#include <mach/common.h>
-#include <mach/digctl.h>
-#include <mach/mxs.h>
+#include <asm/system_misc.h>
+
+/* MXS DIGCTL SAIF CLKMUX */
+#define MXS_DIGCTL_SAIF_CLKMUX_DIRECT           0x0
+#define MXS_DIGCTL_SAIF_CLKMUX_CROSSINPUT       0x1
+#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR0         0x2
+#define MXS_DIGCTL_SAIF_CLKMUX_EXTMSTR1         0x3
+
+#define MXS_GPIO_NR(bank, nr)   ((bank) * 32 + (nr))
+
+#define MXS_SET_ADDR            0x4
+#define MXS_CLR_ADDR            0x8
+#define MXS_TOG_ADDR            0xc
+
+static inline void __mxs_setl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_SET_ADDR);
+}
+
+static inline void __mxs_clrl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_CLR_ADDR);
+}
+
+static inline void __mxs_togl(u32 mask, void __iomem *reg)
+{
+        __raw_writel(mask, reg + MXS_TOG_ADDR);
+}
 
 static struct fb_videomode mx23evk_video_modes[] = {
         {
@@ -165,14 +196,80 @@ static struct of_dev_auxdata mxs_auxdata_lookup[] __initdata = {
         { /* sentinel */ }
 };
 
-static void __init imx23_timer_init(void)
-{
-        mx23_clocks_init();
-}
+#define OCOTP_WORD_OFFSET               0x20
+#define OCOTP_WORD_COUNT                0x20
+
+#define BM_OCOTP_CTRL_BUSY              (1 << 8)
+#define BM_OCOTP_CTRL_ERROR             (1 << 9)
+#define BM_OCOTP_CTRL_RD_BANK_OPEN      (1 << 12)
 
-static void __init imx28_timer_init(void)
+static DEFINE_MUTEX(ocotp_mutex);
+static u32 ocotp_words[OCOTP_WORD_COUNT];
+
+static const u32 *mxs_get_ocotp(void)
 {
-        mx28_clocks_init();
+        struct device_node *np;
+        void __iomem *ocotp_base;
+        int timeout = 0x400;
+        size_t i;
+        static int once;
+
+        if (once)
+                return ocotp_words;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,ocotp");
+        ocotp_base = of_iomap(np, 0);
+        WARN_ON(!ocotp_base);
+
+        mutex_lock(&ocotp_mutex);
+
+        /*
+         * clk_enable(hbus_clk) for ocotp can be skipped
+         * as it must be on when system is running.
+         */
+
+        /* try to clear ERROR bit */
+        __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
+
+        /* check both BUSY and ERROR cleared */
+        while ((__raw_readl(ocotp_base) &
+                (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
+                cpu_relax();
+
+        if (unlikely(!timeout))
+                goto error_unlock;
+
+        /* open OCOTP banks for read */
+        __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
+
+        /* approximately wait 32 hclk cycles */
+        udelay(1);
+
+        /* poll BUSY bit becoming cleared */
+        timeout = 0x400;
+        while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
+                cpu_relax();
+
+        if (unlikely(!timeout))
+                goto error_unlock;
+
+        for (i = 0; i < OCOTP_WORD_COUNT; i++)
+                ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
+                                                i * 0x10);
+
+        /* close banks for power saving */
+        __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
+
+        once = 1;
+
+        mutex_unlock(&ocotp_mutex);
+
+        return ocotp_words;
+
+error_unlock:
+        mutex_unlock(&ocotp_mutex);
+        pr_err("%s: timeout in reading OCOTP\n", __func__);
+        return NULL;
 }
 
 enum mac_oui {
@@ -454,32 +551,62 @@ static void __init mxs_machine_init(void)
                 imx28_evk_post_init();
 }
 
-static const char *imx23_dt_compat[] __initdata = {
-        "fsl,imx23",
-        NULL,
-};
+#define MX23_CLKCTRL_RESET_OFFSET       0x120
+#define MX28_CLKCTRL_RESET_OFFSET       0x1e0
+#define MXS_CLKCTRL_RESET_CHIP          (1 << 1)
+
+/*
+ * Reset the system. It is called by machine_restart().
+ */
+static void mxs_restart(char mode, const char *cmd)
+{
+        struct device_node *np;
+        void __iomem *reset_addr;
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,clkctrl");
+        reset_addr = of_iomap(np, 0);
+        if (!reset_addr)
+                goto soft;
+
+        if (of_device_is_compatible(np, "fsl,imx23-clkctrl"))
+                reset_addr += MX23_CLKCTRL_RESET_OFFSET;
+        else
+                reset_addr += MX28_CLKCTRL_RESET_OFFSET;
 
-static const char *imx28_dt_compat[] __initdata = {
+        /* reset the chip */
+        __mxs_setl(MXS_CLKCTRL_RESET_CHIP, reset_addr);
+
+        pr_err("Failed to assert the chip reset\n");
+
+        /* Delay to allow the serial port to show the message */
+        mdelay(50);
+
+soft:
+        /* We'll take a jump through zero as a poor second */
+        soft_restart(0);
+}
+
+static void __init mxs_timer_init(void)
+{
+        if (of_machine_is_compatible("fsl,imx23"))
+                mx23_clocks_init();
+        else
+                mx28_clocks_init();
+        clocksource_of_init();
+}
+
+static const char *mxs_dt_compat[] __initdata = {
         "fsl,imx28",
+        "fsl,imx23",
         NULL,
 };
 
-DT_MACHINE_START(IMX23, "Freescale i.MX23 (Device Tree)")
-        .map_io         = mx23_map_io,
-        .init_irq       = icoll_init_irq,
-        .handle_irq     = icoll_handle_irq,
-        .init_time      = imx23_timer_init,
-        .init_machine   = mxs_machine_init,
-        .dt_compat      = imx23_dt_compat,
-        .restart        = mxs_restart,
-MACHINE_END
-
-DT_MACHINE_START(IMX28, "Freescale i.MX28 (Device Tree)")
-        .map_io         = mx28_map_io,
-        .init_irq       = icoll_init_irq,
+DT_MACHINE_START(MXS, "Freescale MXS (Device Tree)")
+        .map_io         = debug_ll_io_init,
+        .init_irq       = irqchip_init,
         .handle_irq     = icoll_handle_irq,
-        .init_time      = imx28_timer_init,
+        .init_time      = mxs_timer_init,
         .init_machine   = mxs_machine_init,
-        .dt_compat      = imx28_dt_compat,
+        .dt_compat      = mxs_dt_compat,
         .restart        = mxs_restart,
 MACHINE_END
diff --git a/arch/arm/mach-mxs/mm.c b/arch/arm/mach-mxs/mm.c
deleted file mode 100644
index e63b7d87acbd..000000000000
--- a/arch/arm/mach-mxs/mm.c
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * The code contained herein is licensed under the GNU General Public
- * License.  You may obtain a copy of the GNU General Public License
- * Version 2 or later at the following locations:
- *
- * http://www.opensource.org/licenses/gpl-license.html
- * http://www.gnu.org/copyleft/gpl.html
- *
- * Create static mapping between physical to virtual memory.
- */
-
-#include <linux/mm.h>
-#include <linux/init.h>
-
-#include <asm/mach/map.h>
-
-#include <mach/mx23.h>
-#include <mach/mx28.h>
-#include <mach/common.h>
-
-/*
- * Define the MX23 memory map.
- */
-static struct map_desc mx23_io_desc[] __initdata = {
-        mxs_map_entry(MX23, OCRAM, MT_DEVICE),
-        mxs_map_entry(MX23, IO, MT_DEVICE),
-};
-
-/*
- * Define the MX28 memory map.
- */
-static struct map_desc mx28_io_desc[] __initdata = {
-        mxs_map_entry(MX28, OCRAM, MT_DEVICE),
-        mxs_map_entry(MX28, IO, MT_DEVICE),
-};
-
-/*
- * This function initializes the memory map. It is called during the
- * system startup to create static physical to virtual memory mappings
- * for the IO modules.
- */
-void __init mx23_map_io(void)
-{
-        iotable_init(mx23_io_desc, ARRAY_SIZE(mx23_io_desc));
-}
-
-void __init mx28_map_io(void)
-{
-        iotable_init(mx28_io_desc, ARRAY_SIZE(mx28_io_desc));
-}
diff --git a/arch/arm/mach-mxs/ocotp.c b/arch/arm/mach-mxs/ocotp.c
deleted file mode 100644
index 1dff46703753..000000000000
--- a/arch/arm/mach-mxs/ocotp.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright 2010 Freescale Semiconductor, Inc. All Rights Reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/delay.h>
-#include <linux/err.h>
-#include <linux/mutex.h>
-
-#include <asm/processor.h>      /* for cpu_relax() */
-
-#include <mach/mxs.h>
-#include <mach/common.h>
-
-#define OCOTP_WORD_OFFSET               0x20
-#define OCOTP_WORD_COUNT                0x20
-
-#define BM_OCOTP_CTRL_BUSY              (1 << 8)
-#define BM_OCOTP_CTRL_ERROR             (1 << 9)
-#define BM_OCOTP_CTRL_RD_BANK_OPEN      (1 << 12)
-
-static DEFINE_MUTEX(ocotp_mutex);
-static u32 ocotp_words[OCOTP_WORD_COUNT];
-
-const u32 *mxs_get_ocotp(void)
-{
-        void __iomem *ocotp_base = MXS_IO_ADDRESS(MXS_OCOTP_BASE_ADDR);
-        int timeout = 0x400;
-        size_t i;
-        static int once = 0;
-
-        if (once)
-                return ocotp_words;
-
-        mutex_lock(&ocotp_mutex);
-
-        /*
-         * clk_enable(hbus_clk) for ocotp can be skipped
-         * as it must be on when system is running.
-         */
-
-        /* try to clear ERROR bit */
-        __mxs_clrl(BM_OCOTP_CTRL_ERROR, ocotp_base);
-
-        /* check both BUSY and ERROR cleared */
-        while ((__raw_readl(ocotp_base) &
-                (BM_OCOTP_CTRL_BUSY | BM_OCOTP_CTRL_ERROR)) && --timeout)
-                cpu_relax();
-
-        if (unlikely(!timeout))
-                goto error_unlock;
-
-        /* open OCOTP banks for read */
-        __mxs_setl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
-
-        /* approximately wait 32 hclk cycles */
-        udelay(1);
-
-        /* poll BUSY bit becoming cleared */
-        timeout = 0x400;
-        while ((__raw_readl(ocotp_base) & BM_OCOTP_CTRL_BUSY) && --timeout)
-                cpu_relax();
-
-        if (unlikely(!timeout))
-                goto error_unlock;
-
-        for (i = 0; i < OCOTP_WORD_COUNT; i++)
-                ocotp_words[i] = __raw_readl(ocotp_base + OCOTP_WORD_OFFSET +
-                                                i * 0x10);
-
-        /* close banks for power saving */
-        __mxs_clrl(BM_OCOTP_CTRL_RD_BANK_OPEN, ocotp_base);
-
-        once = 1;
-
-        mutex_unlock(&ocotp_mutex);
-
-        return ocotp_words;
-
-error_unlock:
-        mutex_unlock(&ocotp_mutex);
-        pr_err("%s: timeout in reading OCOTP\n", __func__);
-        return NULL;
-}
diff --git a/arch/arm/mach-mxs/system.c b/arch/arm/mach-mxs/system.c
deleted file mode 100644
index 30042e23bfa7..000000000000
--- a/arch/arm/mach-mxs/system.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * Copyright (C) 1999 ARM Limited
- * Copyright (C) 2000 Deep Blue Solutions Ltd
- * Copyright 2006-2007,2010 Freescale Semiconductor, Inc. All Rights Reserved.
- * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
- * Copyright 2009 Ilya Yanok, Emcraft Systems Ltd, yanok@emcraft.com
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/io.h>
-#include <linux/err.h>
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/module.h>
-
-#include <asm/proc-fns.h>
-#include <asm/system_misc.h>
-
-#include <mach/mxs.h>
-#include <mach/common.h>
-
-#define MX23_CLKCTRL_RESET_OFFSET       0x120
-#define MX28_CLKCTRL_RESET_OFFSET       0x1e0
-#define MXS_CLKCTRL_RESET_CHIP          (1 << 1)
-
-#define MXS_MODULE_CLKGATE              (1 << 30)
-#define MXS_MODULE_SFTRST               (1 << 31)
-
-static void __iomem *mxs_clkctrl_reset_addr;
-
-/*
- * Reset the system. It is called by machine_restart().
- */
-void mxs_restart(char mode, const char *cmd)
-{
-        /* reset the chip */
-        __mxs_setl(MXS_CLKCTRL_RESET_CHIP, mxs_clkctrl_reset_addr);
-
-        pr_err("Failed to assert the chip reset\n");
-
-        /* Delay to allow the serial port to show the message */
-        mdelay(50);
-
-        /* We'll take a jump through zero as a poor second */
-        soft_restart(0);
-}
-
-static int __init mxs_arch_reset_init(void)
-{
-        struct clk *clk;
-
-        mxs_clkctrl_reset_addr = MXS_IO_ADDRESS(MXS_CLKCTRL_BASE_ADDR) +
-                                (cpu_is_mx23() ? MX23_CLKCTRL_RESET_OFFSET :
-                                                 MX28_CLKCTRL_RESET_OFFSET);
-
-        clk = clk_get_sys("rtc", NULL);
-        if (!IS_ERR(clk))
-                clk_prepare_enable(clk);
-
-        return 0;
-}
-core_initcall(mxs_arch_reset_init);
-
-/*
- * Clear the bit and poll it cleared.  This is usually called with
- * a reset address and mask being either SFTRST(bit 31) or CLKGATE
- * (bit 30).
- */
-static int clear_poll_bit(void __iomem *addr, u32 mask)
-{
-        int timeout = 0x400;
-
-        /* clear the bit */
-        __mxs_clrl(mask, addr);
-
-        /*
-         * SFTRST needs 3 GPMI clocks to settle, the reference manual
-         * recommends to wait 1us.
-         */
-        udelay(1);
-
-        /* poll the bit becoming clear */
-        while ((__raw_readl(addr) & mask) && --timeout)
-                /* nothing */;
-
-        return !timeout;
-}
-
-int mxs_reset_block(void __iomem *reset_addr)
-{
-        int ret;
-        int timeout = 0x400;
-
-        /* clear and poll SFTRST */
-        ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
-        if (unlikely(ret))
-                goto error;
-
-        /* clear CLKGATE */
-        __mxs_clrl(MXS_MODULE_CLKGATE, reset_addr);
-
-        /* set SFTRST to reset the block */
-        __mxs_setl(MXS_MODULE_SFTRST, reset_addr);
-        udelay(1);
-
-        /* poll CLKGATE becoming set */
-        while ((!(__raw_readl(reset_addr) & MXS_MODULE_CLKGATE)) && --timeout)
-                /* nothing */;
-        if (unlikely(!timeout))
-                goto error;
-
-        /* clear and poll SFTRST */
-        ret = clear_poll_bit(reset_addr, MXS_MODULE_SFTRST);
-        if (unlikely(ret))
-                goto error;
-
-        /* clear and poll CLKGATE */
-        ret = clear_poll_bit(reset_addr, MXS_MODULE_CLKGATE);
-        if (unlikely(ret))
-                goto error;
-
-        return 0;
-
-error:
-        pr_err("%s(%p): module reset timeout\n", __func__, reset_addr);
-        return -ETIMEDOUT;
-}
-EXPORT_SYMBOL(mxs_reset_block);
diff --git a/arch/arm/mach-omap1/dma.h b/arch/arm/mach-omap1/dma.h
index da6345dab03f..d05909c96715 100644
--- a/arch/arm/mach-omap1/dma.h
+++ b/arch/arm/mach-omap1/dma.h
@@ -21,21 +21,10 @@
 
 /* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE              0
-#define OMAP_DMA_MCSI1_TX               1
-#define OMAP_DMA_MCSI1_RX               2
-#define OMAP_DMA_I2C_RX                 3
-#define OMAP_DMA_I2C_TX                 4
-#define OMAP_DMA_EXT_NDMA_REQ           5
-#define OMAP_DMA_EXT_NDMA_REQ2          6
-#define OMAP_DMA_UWIRE_TX               7
 #define OMAP_DMA_MCBSP1_TX              8
 #define OMAP_DMA_MCBSP1_RX              9
 #define OMAP_DMA_MCBSP3_TX              10
 #define OMAP_DMA_MCBSP3_RX              11
-#define OMAP_DMA_UART1_TX               12
-#define OMAP_DMA_UART1_RX               13
-#define OMAP_DMA_UART2_TX               14
-#define OMAP_DMA_UART2_RX               15
 #define OMAP_DMA_MCBSP2_TX              16
 #define OMAP_DMA_MCBSP2_RX              17
 #define OMAP_DMA_UART3_TX               18
@@ -43,41 +32,11 @@
 #define OMAP_DMA_CAMERA_IF_RX           20
 #define OMAP_DMA_MMC_TX                 21
 #define OMAP_DMA_MMC_RX                 22
-#define OMAP_DMA_NAND                   23
-#define OMAP_DMA_IRQ_LCD_LINE           24
-#define OMAP_DMA_MEMORY_STICK           25
 #define OMAP_DMA_USB_W2FC_RX0           26
-#define OMAP_DMA_USB_W2FC_RX1           27
-#define OMAP_DMA_USB_W2FC_RX2           28
 #define OMAP_DMA_USB_W2FC_TX0           29
-#define OMAP_DMA_USB_W2FC_TX1           30
-#define OMAP_DMA_USB_W2FC_TX2           31
 
 /* These are only for 1610 */
-#define OMAP_DMA_CRYPTO_DES_IN          32
-#define OMAP_DMA_SPI_TX                 33
-#define OMAP_DMA_SPI_RX                 34
-#define OMAP_DMA_CRYPTO_HASH            35
-#define OMAP_DMA_CCP_ATTN               36
-#define OMAP_DMA_CCP_FIFO_NOT_EMPTY     37
-#define OMAP_DMA_CMT_APE_TX_CHAN_0      38
-#define OMAP_DMA_CMT_APE_RV_CHAN_0      39
-#define OMAP_DMA_CMT_APE_TX_CHAN_1      40
-#define OMAP_DMA_CMT_APE_RV_CHAN_1      41
-#define OMAP_DMA_CMT_APE_TX_CHAN_2      42
-#define OMAP_DMA_CMT_APE_RV_CHAN_2      43
-#define OMAP_DMA_CMT_APE_TX_CHAN_3      44
-#define OMAP_DMA_CMT_APE_RV_CHAN_3      45
-#define OMAP_DMA_CMT_APE_TX_CHAN_4      46
-#define OMAP_DMA_CMT_APE_RV_CHAN_4      47
-#define OMAP_DMA_CMT_APE_TX_CHAN_5      48
-#define OMAP_DMA_CMT_APE_RV_CHAN_5      49
-#define OMAP_DMA_CMT_APE_TX_CHAN_6      50
-#define OMAP_DMA_CMT_APE_RV_CHAN_6      51
-#define OMAP_DMA_CMT_APE_TX_CHAN_7      52
-#define OMAP_DMA_CMT_APE_RV_CHAN_7      53
 #define OMAP_DMA_MMC2_TX                54
 #define OMAP_DMA_MMC2_RX                55
-#define OMAP_DMA_CRYPTO_DES_OUT         56
 
 #endif /* __OMAP1_DMA_CHANNEL_H */
diff --git a/arch/arm/mach-omap2/cclock2420_data.c b/arch/arm/mach-omap2/cclock2420_data.c
index 0f0a97c1fcc0..3662f4d4c8ea 100644
--- a/arch/arm/mach-omap2/cclock2420_data.c
+++ b/arch/arm/mach-omap2/cclock2420_data.c
@@ -1739,153 +1739,153 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
 
 static struct omap_clk omap2420_clks[] = {
         /* external root sources */
-        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_242X),
-        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_242X),
-        CLK(NULL,       "osc_ck",       &osc_ck,        CK_242X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_242X),
-        CLK(NULL,       "alt_ck",       &alt_ck,        CK_242X),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_242X),
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck),
+        CLK(NULL,       "osc_ck",       &osc_ck),
+        CLK(NULL,       "sys_ck",       &sys_ck),
+        CLK(NULL,       "alt_ck",       &alt_ck),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks),
         /* internal analog sources */
-        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_242X),
-        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_242X),
-        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_242X),
+        CLK(NULL,       "dpll_ck",      &dpll_ck),
+        CLK(NULL,       "apll96_ck",    &apll96_ck),
+        CLK(NULL,       "apll54_ck",    &apll54_ck),
         /* internal prcm root sources */
-        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_242X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_242X),
-        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_242X),
-        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_242X),
-        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_242X),
-        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_242X),
-        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_242X),
-        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src, CK_242X),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_242X),
-        CLK(NULL,       "emul_ck",      &emul_ck,       CK_242X),
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck),
+        CLK(NULL,       "core_ck",      &core_ck),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src),
+        CLK(NULL,       "sys_clkout",   &sys_clkout),
+        CLK(NULL,       "sys_clkout2_src", &sys_clkout2_src),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2),
+        CLK(NULL,       "emul_ck",      &emul_ck),
         /* mpu domain clocks */
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_242X),
+        CLK(NULL,       "mpu_ck",       &mpu_ck),
         /* dsp domain clocks */
-        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_242X),
-        CLK(NULL,       "dsp_ick",      &dsp_ick,       CK_242X),
-        CLK(NULL,       "iva1_ifck",    &iva1_ifck,     CK_242X),
-        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
+        CLK(NULL,       "dsp_fck",      &dsp_fck),
+        CLK(NULL,       "dsp_ick",      &dsp_ick),
+        CLK(NULL,       "iva1_ifck",    &iva1_ifck),
+        CLK(NULL,       "iva1_mpu_int_ifck", &iva1_mpu_int_ifck),
         /* GFX domain clocks */
-        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_242X),
-        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_242X),
-        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck),
+        CLK(NULL,       "gfx_ick",      &gfx_ick),
         /* DSS domain clocks */
-        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
-        CLK(NULL,       "dss_ick",              &dss_ick,       CK_242X),
-        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
-        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
-        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
+        CLK("omapdss_dss",      "ick",          &dss_ick),
+        CLK(NULL,       "dss_ick",              &dss_ick),
+        CLK(NULL,       "dss1_fck",             &dss1_fck),
+        CLK(NULL,       "dss2_fck",     &dss2_fck),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck),
         /* L3 domain clocks */
-        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_242X),
-        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_242X),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_242X),
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick),
         /* L4 domain clocks */
-        CLK(NULL,       "l4_ck",        &l4_ck,         CK_242X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_242X),
+        CLK(NULL,       "l4_ck",        &l4_ck),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick),
         /* virtual meta-group clock */
-        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_242X),
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set),
         /* general l4 interface ck, multi-parent functional clk */
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_242X),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_242X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_242X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_242X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_242X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_242X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_242X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_242X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_242X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_242X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_242X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_242X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_242X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_242X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_242X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_242X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_242X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_242X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_242X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_242X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_242X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_242X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
-        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_242X),
-        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
-        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_242X),
-        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
-        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_242X),
-        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
-        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_242X),
-        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_242X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_242X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_242X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_242X),
-        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
-        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
-        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
-        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick,   CK_242X),
-        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
-        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
-        CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
-        CLK(NULL,       "cam_fck",      &cam_fck,       CK_242X),
-        CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_242X),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
-        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
-        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_242X),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_242X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
-        CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
-        CLK(NULL,       "mmc_ick",      &mmc_ick,       CK_242X),
-        CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
-        CLK(NULL,       "mmc_fck",      &mmc_fck,       CK_242X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
-        CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
-        CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
-        CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
-        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_242X),
-        CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
-        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_242X),
-        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
-        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_242X),
-        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
-        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
-        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_242X),
-        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
-        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
-        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_242X),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_242X),
-        CLK(NULL,       "vlynq_ick",    &vlynq_ick,     CK_242X),
-        CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
-        CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
-        CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
-        CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
-        CLK(NULL,       "rng_ick",              &rng_ick,       CK_242X),
-        CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
-        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
-        CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
-        CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
-        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_242X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_242X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_242X),
-        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_242X),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck),
+        CLK(NULL,       "uart1_ick",    &uart1_ick),
+        CLK(NULL,       "uart1_fck",    &uart1_fck),
+        CLK(NULL,       "uart2_ick",    &uart2_ick),
+        CLK(NULL,       "uart2_fck",    &uart2_fck),
+        CLK(NULL,       "uart3_ick",    &uart3_ick),
+        CLK(NULL,       "uart3_fck",    &uart3_fck),
+        CLK(NULL,       "gpios_ick",    &gpios_ick),
+        CLK(NULL,       "gpios_fck",    &gpios_fck),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick),
+        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick),
+        CLK("omap24xxcam", "fck",       &cam_fck),
+        CLK(NULL,       "cam_fck",      &cam_fck),
+        CLK("omap24xxcam", "ick",       &cam_ick),
+        CLK(NULL,       "cam_ick",      &cam_ick),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck),
+        CLK(NULL,       "mspro_ick",    &mspro_ick),
+        CLK(NULL,       "mspro_fck",    &mspro_fck),
+        CLK("mmci-omap.0", "ick",       &mmc_ick),
+        CLK(NULL,       "mmc_ick",      &mmc_ick),
+        CLK("mmci-omap.0", "fck",       &mmc_fck),
+        CLK(NULL,       "mmc_fck",      &mmc_fck),
+        CLK(NULL,       "fac_ick",      &fac_ick),
+        CLK(NULL,       "fac_fck",      &fac_fck),
+        CLK(NULL,       "eac_ick",      &eac_ick),
+        CLK(NULL,       "eac_fck",      &eac_fck),
+        CLK("omap_hdq.0", "ick",        &hdq_ick),
+        CLK(NULL,       "hdq_ick",      &hdq_ick),
+        CLK("omap_hdq.0", "fck",        &hdq_fck),
+        CLK(NULL,       "hdq_fck",      &hdq_fck),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck),
+        CLK(NULL,       "sdma_fck",     &sdma_fck),
+        CLK(NULL,       "sdma_ick",     &sdma_ick),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick),
+        CLK(NULL,       "vlynq_ick",    &vlynq_ick),
+        CLK(NULL,       "vlynq_fck",    &vlynq_fck),
+        CLK(NULL,       "des_ick",      &des_ick),
+        CLK("omap-sham",        "ick",  &sha_ick),
+        CLK(NULL,       "sha_ick",      &sha_ick),
+        CLK("omap_rng", "ick",          &rng_ick),
+        CLK(NULL,       "rng_ick",              &rng_ick),
+        CLK("omap-aes", "ick",  &aes_ick),
+        CLK(NULL,       "aes_ick",      &aes_ick),
+        CLK(NULL,       "pka_ick",      &pka_ick),
+        CLK(NULL,       "usb_fck",      &usb_fck),
+        CLK("musb-hdrc",        "fck",  &osc_ck),
+        CLK(NULL,       "timer_32k_ck", &func_32k_ck),
+        CLK(NULL,       "timer_sys_ck", &sys_ck),
+        CLK(NULL,       "timer_ext_ck", &alt_ck),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set),
 };
 
 
@@ -1904,8 +1904,6 @@ static const char *enable_init_clks[] = {
 
 int __init omap2420_clk_init(void)
 {
-        struct omap_clk *c;
-
         prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
         cpu_mask = RATE_IN_242X;
         rate_table = omap2420_rate_table;
@@ -1914,12 +1912,7 @@ int __init omap2420_clk_init(void)
 
         omap2xxx_clkt_vps_check_bootloader_rates();
 
-        for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
-             c++) {
-                clkdev_add(&c->lk);
-                if (!__clk_init(NULL, c->lk.clk))
-                        omap2_init_clk_hw_omap_clocks(c->lk.clk);
-        }
+        omap_clocks_register(omap2420_clks, ARRAY_SIZE(omap2420_clks));
 
         omap2xxx_clkt_vps_late_init();
 
diff --git a/arch/arm/mach-omap2/cclock2430_data.c b/arch/arm/mach-omap2/cclock2430_data.c
index aed8f74ca076..bda353b2f7d9 100644
--- a/arch/arm/mach-omap2/cclock2430_data.c
+++ b/arch/arm/mach-omap2/cclock2430_data.c
@@ -1840,168 +1840,168 @@ DEFINE_STRUCT_CLK(wdt4_ick, aes_ick_parent_names, aes_ick_ops);
 
 static struct omap_clk omap2430_clks[] = {
         /* external root sources */
-        CLK(NULL,       "func_32k_ck",  &func_32k_ck,   CK_243X),
-        CLK(NULL,       "secure_32k_ck", &secure_32k_ck, CK_243X),
-        CLK(NULL,       "osc_ck",       &osc_ck,        CK_243X),
-        CLK("twl",      "fck",          &osc_ck,        CK_243X),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_243X),
-        CLK(NULL,       "alt_ck",       &alt_ck,        CK_243X),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_243X),
+        CLK(NULL,       "func_32k_ck",  &func_32k_ck),
+        CLK(NULL,       "secure_32k_ck", &secure_32k_ck),
+        CLK(NULL,       "osc_ck",       &osc_ck),
+        CLK("twl",      "fck",          &osc_ck),
+        CLK(NULL,       "sys_ck",       &sys_ck),
+        CLK(NULL,       "alt_ck",       &alt_ck),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks),
         /* internal analog sources */
-        CLK(NULL,       "dpll_ck",      &dpll_ck,       CK_243X),
-        CLK(NULL,       "apll96_ck",    &apll96_ck,     CK_243X),
-        CLK(NULL,       "apll54_ck",    &apll54_ck,     CK_243X),
+        CLK(NULL,       "dpll_ck",      &dpll_ck),
+        CLK(NULL,       "apll96_ck",    &apll96_ck),
+        CLK(NULL,       "apll54_ck",    &apll54_ck),
         /* internal prcm root sources */
-        CLK(NULL,       "func_54m_ck",  &func_54m_ck,   CK_243X),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_243X),
-        CLK(NULL,       "func_96m_ck",  &func_96m_ck,   CK_243X),
-        CLK(NULL,       "func_48m_ck",  &func_48m_ck,   CK_243X),
-        CLK(NULL,       "func_12m_ck",  &func_12m_ck,   CK_243X),
-        CLK(NULL,       "sys_clkout_src", &sys_clkout_src, CK_243X),
-        CLK(NULL,       "sys_clkout",   &sys_clkout,    CK_243X),
-        CLK(NULL,       "emul_ck",      &emul_ck,       CK_243X),
+        CLK(NULL,       "func_54m_ck",  &func_54m_ck),
+        CLK(NULL,       "core_ck",      &core_ck),
+        CLK(NULL,       "func_96m_ck",  &func_96m_ck),
+        CLK(NULL,       "func_48m_ck",  &func_48m_ck),
+        CLK(NULL,       "func_12m_ck",  &func_12m_ck),
+        CLK(NULL,       "sys_clkout_src", &sys_clkout_src),
+        CLK(NULL,       "sys_clkout",   &sys_clkout),
+        CLK(NULL,       "emul_ck",      &emul_ck),
         /* mpu domain clocks */
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_243X),
+        CLK(NULL,       "mpu_ck",       &mpu_ck),
         /* dsp domain clocks */
-        CLK(NULL,       "dsp_fck",      &dsp_fck,       CK_243X),
-        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick,    CK_243X),
+        CLK(NULL,       "dsp_fck",      &dsp_fck),
+        CLK(NULL,       "iva2_1_ick",   &iva2_1_ick),
         /* GFX domain clocks */
-        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck,    CK_243X),
-        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck,    CK_243X),
-        CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_243X),
+        CLK(NULL,       "gfx_3d_fck",   &gfx_3d_fck),
+        CLK(NULL,       "gfx_2d_fck",   &gfx_2d_fck),
+        CLK(NULL,       "gfx_ick",      &gfx_ick),
         /* Modem domain clocks */
-        CLK(NULL,       "mdm_ick",      &mdm_ick,       CK_243X),
-        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
+        CLK(NULL,       "mdm_ick",      &mdm_ick),
+        CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck),
         /* DSS domain clocks */
-        CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
-        CLK(NULL,       "dss_ick",              &dss_ick,       CK_243X),
-        CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
-        CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
-        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
+        CLK("omapdss_dss",      "ick",          &dss_ick),
+        CLK(NULL,       "dss_ick",              &dss_ick),
+        CLK(NULL,       "dss1_fck",             &dss1_fck),
+        CLK(NULL,       "dss2_fck",     &dss2_fck),
+        CLK(NULL,       "dss_54m_fck",  &dss_54m_fck),
         /* L3 domain clocks */
-        CLK(NULL,       "core_l3_ck",   &core_l3_ck,    CK_243X),
-        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck, CK_243X),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_243X),
+        CLK(NULL,       "core_l3_ck",   &core_l3_ck),
+        CLK(NULL,       "ssi_fck",      &ssi_ssr_sst_fck),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick),
         /* L4 domain clocks */
-        CLK(NULL,       "l4_ck",        &l4_ck,         CK_243X),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_243X),
+        CLK(NULL,       "l4_ck",        &l4_ck),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick),
         /* virtual meta-group clock */
-        CLK(NULL,       "virt_prcm_set", &virt_prcm_set, CK_243X),
+        CLK(NULL,       "virt_prcm_set", &virt_prcm_set),
         /* general l4 interface ck, multi-parent functional clk */
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_243X),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_243X),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_243X),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_243X),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_243X),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_243X),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_243X),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_243X),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_243X),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_243X),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_243X),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_243X),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_243X),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_243X),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_243X),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_243X),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_243X),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_243X),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_243X),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_243X),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_243X),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_243X),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
-        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_243X),
-        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
-        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_243X),
-        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
-        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_243X),
-        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
-        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick,    CK_243X),
-        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
-        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_243X),
-        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
-        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_243X),
-        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
-        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_243X),
-        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
-        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_243X),
-        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_243X),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_243X),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_243X),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_243X),
-        CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
-        CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
-        CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
-        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick,   CK_243X),
-        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
-        CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
-        CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
-        CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X),
-        CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
-        CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
-        CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_243X),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_243X),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
-        CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
-        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_243X),
-        CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
-        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_243X),
-        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
-        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_243X),
-        CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
-        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
-        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_243X),
-        CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
-        CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
-        CLK(NULL,       "sdma_ick",     &sdma_ick,      CK_243X),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_243X),
-        CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
-        CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
-        CLK(NULL,       "rng_ick",      &rng_ick,       CK_243X),
-        CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
-        CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
-        CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
-        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
-        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
-        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_243X),
-        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
-        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
-        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_243X),
-        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
-        CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
-        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
-        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
-        CLK(NULL,        "mmchsdb1_fck",        &mmchsdb1_fck,  CK_243X),
-        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
-        CLK(NULL,        "mmchsdb2_fck",        &mmchsdb2_fck,  CK_243X),
-        CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
-        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_243X),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck),
+        CLK(NULL,       "uart1_ick",    &uart1_ick),
+        CLK(NULL,       "uart1_fck",    &uart1_fck),
+        CLK(NULL,       "uart2_ick",    &uart2_ick),
+        CLK(NULL,       "uart2_fck",    &uart2_fck),
+        CLK(NULL,       "uart3_ick",    &uart3_ick),
+        CLK(NULL,       "uart3_fck",    &uart3_fck),
+        CLK(NULL,       "gpios_ick",    &gpios_ick),
+        CLK(NULL,       "gpios_fck",    &gpios_fck),
+        CLK("omap_wdt", "ick",          &mpu_wdt_ick),
+        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick),
+        CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck),
+        CLK(NULL,       "sync_32k_ick", &sync_32k_ick),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick),
+        CLK(NULL,       "icr_ick",      &icr_ick),
+        CLK("omap24xxcam", "fck",       &cam_fck),
+        CLK(NULL,       "cam_fck",      &cam_fck),
+        CLK("omap24xxcam", "ick",       &cam_ick),
+        CLK(NULL,       "cam_ick",      &cam_ick),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick),
+        CLK(NULL,       "wdt4_ick",     &wdt4_ick),
+        CLK(NULL,       "wdt4_fck",     &wdt4_fck),
+        CLK(NULL,       "mspro_ick",    &mspro_ick),
+        CLK(NULL,       "mspro_fck",    &mspro_fck),
+        CLK(NULL,       "fac_ick",      &fac_ick),
+        CLK(NULL,       "fac_fck",      &fac_fck),
+        CLK("omap_hdq.0", "ick",        &hdq_ick),
+        CLK(NULL,       "hdq_ick",      &hdq_ick),
+        CLK("omap_hdq.1", "fck",        &hdq_fck),
+        CLK(NULL,       "hdq_fck",      &hdq_fck),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick),
+        CLK(NULL,       "i2chs1_fck",   &i2chs1_fck),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick),
+        CLK(NULL,       "i2chs2_fck",   &i2chs2_fck),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck),
+        CLK(NULL,       "sdma_fck",     &sdma_fck),
+        CLK(NULL,       "sdma_ick",     &sdma_ick),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick),
+        CLK(NULL,       "des_ick",      &des_ick),
+        CLK("omap-sham",        "ick",  &sha_ick),
+        CLK("omap_rng", "ick",          &rng_ick),
+        CLK(NULL,       "rng_ick",      &rng_ick),
+        CLK("omap-aes", "ick",  &aes_ick),
+        CLK(NULL,       "pka_ick",      &pka_ick),
+        CLK(NULL,       "usb_fck",      &usb_fck),
+        CLK("musb-omap2430",    "ick",  &usbhs_ick),
+        CLK(NULL,       "usbhs_ick",    &usbhs_ick),
+        CLK("omap_hsmmc.0", "ick",      &mmchs1_ick),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck),
+        CLK("omap_hsmmc.1", "ick",      &mmchs2_ick),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick),
+        CLK(NULL,       "gpio5_fck",    &gpio5_fck),
+        CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick),
+        CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck),
+        CLK(NULL,        "mmchsdb1_fck",        &mmchsdb1_fck),
+        CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck),
+        CLK(NULL,        "mmchsdb2_fck",        &mmchsdb2_fck),
+        CLK(NULL,       "timer_32k_ck",  &func_32k_ck),
+        CLK(NULL,       "timer_sys_ck", &sys_ck),
+        CLK(NULL,       "timer_ext_ck", &alt_ck),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set),
 };
 
 static const char *enable_init_clks[] = {
@@ -2019,8 +2019,6 @@ static const char *enable_init_clks[] = {
 
 int __init omap2430_clk_init(void)
 {
-        struct omap_clk *c;
-
         prcm_clksrc_ctrl = OMAP2430_PRCM_CLKSRC_CTRL;
         cpu_mask = RATE_IN_243X;
         rate_table = omap2430_rate_table;
@@ -2029,12 +2027,7 @@ int __init omap2430_clk_init(void)
 
         omap2xxx_clkt_vps_check_bootloader_rates();
 
-        for (c = omap2430_clks; c < omap2430_clks + ARRAY_SIZE(omap2430_clks);
-             c++) {
-                clkdev_add(&c->lk);
-                if (!__clk_init(NULL, c->lk.clk))
-                        omap2_init_clk_hw_omap_clocks(c->lk.clk);
-        }
+        omap_clocks_register(omap2430_clks, ARRAY_SIZE(omap2430_clks));
 
         omap2xxx_clkt_vps_late_init();
 
diff --git a/arch/arm/mach-omap2/cclock33xx_data.c b/arch/arm/mach-omap2/cclock33xx_data.c
index 7f091c85384e..332c6d3e55a9 100644
--- a/arch/arm/mach-omap2/cclock33xx_data.c
+++ b/arch/arm/mach-omap2/cclock33xx_data.c
@@ -838,80 +838,80 @@ DEFINE_STRUCT_CLK(wdt1_fck, wdt_ck_parents, gpio_fck_ops);
  * clkdev
  */
 static struct omap_clk am33xx_clks[] = {
-        CLK(NULL,       "clk_32768_ck",         &clk_32768_ck,  CK_AM33XX),
-        CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck,  CK_AM33XX),
-        CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck,      CK_AM33XX),
-        CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck,      CK_AM33XX),
-        CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck,      CK_AM33XX),
-        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck,      CK_AM33XX),
-        CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck,  CK_AM33XX),
-        CLK(NULL,       "tclkin_ck",            &tclkin_ck,     CK_AM33XX),
-        CLK(NULL,       "dpll_core_ck",         &dpll_core_ck,  CK_AM33XX),
-        CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,   CK_AM33XX),
-        CLK("cpu0",     NULL,                   &dpll_mpu_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
-        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
-        CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck,  CK_AM33XX),
-        CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck,       CK_AM33XX),
-        CLK(NULL,       "dpll_per_ck",          &dpll_per_ck,   CK_AM33XX),
-        CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck,        CK_AM33XX),
-        CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck,    CK_AM33XX),
-        CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck,   CK_AM33XX),
-        CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck,   CK_AM33XX),
-        CLK(NULL,       "cefuse_fck",           &cefuse_fck,    CK_AM33XX),
-        CLK(NULL,       "clkdiv32k_ck",         &clkdiv32k_ck,  CK_AM33XX),
-        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick, CK_AM33XX),
-        CLK(NULL,       "dcan0_fck",            &dcan0_fck,     CK_AM33XX),
-        CLK("481cc000.d_can",   NULL,           &dcan0_fck,     CK_AM33XX),
-        CLK(NULL,       "dcan1_fck",            &dcan1_fck,     CK_AM33XX),
-        CLK("481d0000.d_can",   NULL,           &dcan1_fck,     CK_AM33XX),
-        CLK(NULL,       "debugss_ick",          &debugss_ick,   CK_AM33XX),
-        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk,        CK_AM33XX),
-        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck,    CK_AM33XX),
-        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck,    CK_AM33XX),
-        CLK(NULL,       "mmu_fck",              &mmu_fck,       CK_AM33XX),
-        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck,      CK_AM33XX),
-        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck,      CK_AM33XX),
-        CLK(NULL,       "timer1_fck",           &timer1_fck,    CK_AM33XX),
-        CLK(NULL,       "timer2_fck",           &timer2_fck,    CK_AM33XX),
-        CLK(NULL,       "timer3_fck",           &timer3_fck,    CK_AM33XX),
-        CLK(NULL,       "timer4_fck",           &timer4_fck,    CK_AM33XX),
-        CLK(NULL,       "timer5_fck",           &timer5_fck,    CK_AM33XX),
-        CLK(NULL,       "timer6_fck",           &timer6_fck,    CK_AM33XX),
-        CLK(NULL,       "timer7_fck",           &timer7_fck,    CK_AM33XX),
-        CLK(NULL,       "usbotg_fck",           &usbotg_fck,    CK_AM33XX),
-        CLK(NULL,       "ieee5000_fck",         &ieee5000_fck,  CK_AM33XX),
-        CLK(NULL,       "wdt1_fck",             &wdt1_fck,      CK_AM33XX),
-        CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk,   CK_AM33XX),
-        CLK(NULL,       "l3_gclk",              &l3_gclk,       CK_AM33XX),
-        CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck,  CK_AM33XX),
-        CLK(NULL,       "l4hs_gclk",            &l4hs_gclk,     CK_AM33XX),
-        CLK(NULL,       "l3s_gclk",             &l3s_gclk,      CK_AM33XX),
-        CLK(NULL,       "l4fw_gclk",            &l4fw_gclk,     CK_AM33XX),
-        CLK(NULL,       "l4ls_gclk",            &l4ls_gclk,     CK_AM33XX),
-        CLK(NULL,       "clk_24mhz",            &clk_24mhz,     CK_AM33XX),
-        CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck, CK_AM33XX),
-        CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk,      CK_AM33XX),
-        CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk,     CK_AM33XX),
-        CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck,    CK_AM33XX),
-        CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk,   CK_AM33XX),
-        CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk,   CK_AM33XX),
-        CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk,   CK_AM33XX),
-        CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk,   CK_AM33XX),
-        CLK(NULL,       "lcd_gclk",             &lcd_gclk,      CK_AM33XX),
-        CLK(NULL,       "mmc_clk",              &mmc_clk,       CK_AM33XX),
-        CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck,    CK_AM33XX),
-        CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck,        CK_AM33XX),
-        CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck,      CK_AM33XX),
-        CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck,        CK_AM33XX),
-        CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick, CK_AM33XX),
-        CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck,  CK_AM33XX),
+        CLK(NULL,       "clk_32768_ck",         &clk_32768_ck),
+        CLK(NULL,       "clk_rc32k_ck",         &clk_rc32k_ck),
+        CLK(NULL,       "virt_19200000_ck",     &virt_19200000_ck),
+        CLK(NULL,       "virt_24000000_ck",     &virt_24000000_ck),
+        CLK(NULL,       "virt_25000000_ck",     &virt_25000000_ck),
+        CLK(NULL,       "virt_26000000_ck",     &virt_26000000_ck),
+        CLK(NULL,       "sys_clkin_ck",         &sys_clkin_ck),
+        CLK(NULL,       "tclkin_ck",            &tclkin_ck),
+        CLK(NULL,       "dpll_core_ck",         &dpll_core_ck),
+        CLK(NULL,       "dpll_core_x2_ck",      &dpll_core_x2_ck),
+        CLK(NULL,       "dpll_core_m4_ck",      &dpll_core_m4_ck),
+        CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck),
+        CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck),
+        CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck),
+        CLK("cpu0",     NULL,                   &dpll_mpu_ck),
+        CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck),
+        CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck),
+        CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck),
+        CLK(NULL,       "dpll_ddr_m2_div2_ck",  &dpll_ddr_m2_div2_ck),
+        CLK(NULL,       "dpll_disp_ck",         &dpll_disp_ck),
+        CLK(NULL,       "dpll_disp_m2_ck",      &dpll_disp_m2_ck),
+        CLK(NULL,       "dpll_per_ck",          &dpll_per_ck),
+        CLK(NULL,       "dpll_per_m2_ck",       &dpll_per_m2_ck),
+        CLK(NULL,       "dpll_per_m2_div4_wkupdm_ck",   &dpll_per_m2_div4_wkupdm_ck),
+        CLK(NULL,       "dpll_per_m2_div4_ck",  &dpll_per_m2_div4_ck),
+        CLK(NULL,       "adc_tsc_fck",          &adc_tsc_fck),
+        CLK(NULL,       "cefuse_fck",           &cefuse_fck),
+        CLK(NULL,       "clkdiv32k_ck",         &clkdiv32k_ck),
+        CLK(NULL,       "clkdiv32k_ick",        &clkdiv32k_ick),
+        CLK(NULL,       "dcan0_fck",            &dcan0_fck),
+        CLK("481cc000.d_can",   NULL,           &dcan0_fck),
+        CLK(NULL,       "dcan1_fck",            &dcan1_fck),
+        CLK("481d0000.d_can",   NULL,           &dcan1_fck),
+        CLK(NULL,       "debugss_ick",          &debugss_ick),
+        CLK(NULL,       "pruss_ocp_gclk",       &pruss_ocp_gclk),
+        CLK(NULL,       "mcasp0_fck",           &mcasp0_fck),
+        CLK(NULL,       "mcasp1_fck",           &mcasp1_fck),
+        CLK(NULL,       "mmu_fck",              &mmu_fck),
+        CLK(NULL,       "smartreflex0_fck",     &smartreflex0_fck),
+        CLK(NULL,       "smartreflex1_fck",     &smartreflex1_fck),
+        CLK(NULL,       "timer1_fck",           &timer1_fck),
+        CLK(NULL,       "timer2_fck",           &timer2_fck),
+        CLK(NULL,       "timer3_fck",           &timer3_fck),
+        CLK(NULL,       "timer4_fck",           &timer4_fck),
+        CLK(NULL,       "timer5_fck",           &timer5_fck),
+        CLK(NULL,       "timer6_fck",           &timer6_fck),
+        CLK(NULL,       "timer7_fck",           &timer7_fck),
+        CLK(NULL,       "usbotg_fck",           &usbotg_fck),
+        CLK(NULL,       "ieee5000_fck",         &ieee5000_fck),
+        CLK(NULL,       "wdt1_fck",             &wdt1_fck),
+        CLK(NULL,       "l4_rtc_gclk",          &l4_rtc_gclk),
+        CLK(NULL,       "l3_gclk",              &l3_gclk),
+        CLK(NULL,       "dpll_core_m4_div2_ck", &dpll_core_m4_div2_ck),
+        CLK(NULL,       "l4hs_gclk",            &l4hs_gclk),
+        CLK(NULL,       "l3s_gclk",             &l3s_gclk),
+        CLK(NULL,       "l4fw_gclk",            &l4fw_gclk),
+        CLK(NULL,       "l4ls_gclk",            &l4ls_gclk),
+        CLK(NULL,       "clk_24mhz",            &clk_24mhz),
+        CLK(NULL,       "sysclk_div_ck",        &sysclk_div_ck),
+        CLK(NULL,       "cpsw_125mhz_gclk",     &cpsw_125mhz_gclk),
+        CLK(NULL,       "cpsw_cpts_rft_clk",    &cpsw_cpts_rft_clk),
+        CLK(NULL,       "gpio0_dbclk_mux_ck",   &gpio0_dbclk_mux_ck),
+        CLK(NULL,       "gpio0_dbclk",          &gpio0_dbclk),
+        CLK(NULL,       "gpio1_dbclk",          &gpio1_dbclk),
+        CLK(NULL,       "gpio2_dbclk",          &gpio2_dbclk),
+        CLK(NULL,       "gpio3_dbclk",          &gpio3_dbclk),
+        CLK(NULL,       "lcd_gclk",             &lcd_gclk),
+        CLK(NULL,       "mmc_clk",              &mmc_clk),
+        CLK(NULL,       "gfx_fclk_clksel_ck",   &gfx_fclk_clksel_ck),
+        CLK(NULL,       "gfx_fck_div_ck",       &gfx_fck_div_ck),
+        CLK(NULL,       "sysclkout_pre_ck",     &sysclkout_pre_ck),
+        CLK(NULL,       "clkout2_div_ck",       &clkout2_div_ck),
+        CLK(NULL,       "timer_32k_ck",         &clkdiv32k_ick),
+        CLK(NULL,       "timer_sys_ck",         &sys_clkin_ck),
 };
 
 
@@ -926,21 +926,10 @@ static const char *enable_init_clks[] = {
 
 int __init am33xx_clk_init(void)
 {
-        struct omap_clk *c;
-        u32 cpu_clkflg;
-
-        if (soc_is_am33xx()) {
+        if (soc_is_am33xx())
                 cpu_mask = RATE_IN_AM33XX;
-                cpu_clkflg = CK_AM33XX;
-        }
-
-        for (c = am33xx_clks; c < am33xx_clks + ARRAY_SIZE(am33xx_clks); c++) {
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        if (!__clk_init(NULL, c->lk.clk))
-                                omap2_init_clk_hw_omap_clocks(c->lk.clk);
-                }
-        }
+
+        omap_clocks_register(am33xx_clks, ARRAY_SIZE(am33xx_clks));
 
         omap2_clk_disable_autoidle_all();
 
diff --git a/arch/arm/mach-omap2/cclock3xxx_data.c b/arch/arm/mach-omap2/cclock3xxx_data.c
index 4579c3c5338f..438d13341e23 100644
--- a/arch/arm/mach-omap2/cclock3xxx_data.c
+++ b/arch/arm/mach-omap2/cclock3xxx_data.c
@@ -3219,289 +3219,325 @@ static struct clk_hw_omap wdt3_ick_hw = {
 DEFINE_STRUCT_CLK(wdt3_ick, gpio2_ick_parent_names, aes2_ick_ops);
 
 /*
- * clkdev
+ * clocks specific to omap3430es1
+ */
+static struct omap_clk omap3430es1_clks[] = {
+        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck),
+        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck),
+        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick),
+        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck),
+        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck),
+        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck),
+        CLK(NULL,       "fshostusb_fck", &fshostusb_fck),
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1),
+        CLK(NULL,       "fac_ick",      &fac_ick),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1),
+        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick),
+        CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es1),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es1),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es1),
+};
+
+/*
+ * clocks specific to am35xx
+ */
+static struct omap_clk am35xx_clks[] = {
+        CLK(NULL,       "ipss_ick",     &ipss_ick),
+        CLK(NULL,       "rmii_ck",      &rmii_ck),
+        CLK(NULL,       "pclk_ck",      &pclk_ck),
+        CLK(NULL,       "emac_ick",     &emac_ick),
+        CLK(NULL,       "emac_fck",     &emac_fck),
+        CLK("davinci_emac.0",   NULL,   &emac_ick),
+        CLK("davinci_mdio.0",   NULL,   &emac_fck),
+        CLK("vpfe-capture",     "master",       &vpfe_ick),
+        CLK("vpfe-capture",     "slave",        &vpfe_fck),
+        CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx),
+        CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx),
+        CLK(NULL,       "hecc_ck",      &hecc_ck),
+        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx),
+        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx),
+};
+
+/*
+ * clocks specific to omap36xx
+ */
+static struct omap_clk omap36xx_clks[] = {
+        CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck),
+        CLK(NULL,       "uart4_fck",    &uart4_fck),
+};
+
+/*
+ * clocks common to omap36xx omap34xx
+ */
+static struct omap_clk omap34xx_omap36xx_clks[] = {
+        CLK(NULL,       "aes1_ick",     &aes1_ick),
+        CLK("omap_rng", "ick",          &rng_ick),
+        CLK(NULL,       "sha11_ick",    &sha11_ick),
+        CLK(NULL,       "des1_ick",     &des1_ick),
+        CLK(NULL,       "cam_mclk",     &cam_mclk),
+        CLK(NULL,       "cam_ick",      &cam_ick),
+        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck),
+        CLK(NULL,       "security_l3_ick", &security_l3_ick),
+        CLK(NULL,       "pka_ick",      &pka_ick),
+        CLK(NULL,       "icr_ick",      &icr_ick),
+        CLK("omap-aes", "ick",  &aes2_ick),
+        CLK("omap-sham",        "ick",  &sha12_ick),
+        CLK(NULL,       "des2_ick",     &des2_ick),
+        CLK(NULL,       "mspro_ick",    &mspro_ick),
+        CLK(NULL,       "mailboxes_ick", &mailboxes_ick),
+        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick),
+        CLK(NULL,       "sr1_fck",      &sr1_fck),
+        CLK(NULL,       "sr2_fck",      &sr2_fck),
+        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick),
+        CLK(NULL,       "security_l4_ick2", &security_l4_ick2),
+        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick),
+        CLK(NULL,       "dpll2_fck",    &dpll2_fck),
+        CLK(NULL,       "iva2_ck",      &iva2_ck),
+        CLK(NULL,       "modem_fck",    &modem_fck),
+        CLK(NULL,       "sad2d_ick",    &sad2d_ick),
+        CLK(NULL,       "mad2d_ick",    &mad2d_ick),
+        CLK(NULL,       "mspro_fck",    &mspro_fck),
+        CLK(NULL,       "dpll2_ck",     &dpll2_ck),
+        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck),
+};
+
+/*
+ * clocks common to omap36xx and omap3430es2plus
+ */
+static struct omap_clk omap36xx_omap3430es2plus_clks[] = {
+        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2),
+        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2),
+        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2),
+        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2),
+        CLK(NULL,       "usim_fck",     &usim_fck),
+        CLK(NULL,       "usim_ick",     &usim_ick),
+};
+
+/*
+ * clocks common to am35xx omap36xx and omap3430es2plus
+ */
+static struct omap_clk omap36xx_am35xx_omap3430es2plus_clks[] = {
+        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck),
+        CLK(NULL,       "dpll5_ck",     &dpll5_ck),
+        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck),
+        CLK(NULL,       "sgx_fck",      &sgx_fck),
+        CLK(NULL,       "sgx_ick",      &sgx_ick),
+        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck),
+        CLK(NULL,       "ts_fck",       &ts_fck),
+        CLK(NULL,       "usbtll_fck",   &usbtll_fck),
+        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck),
+        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck),
+        CLK(NULL,       "usbtll_ick",   &usbtll_ick),
+        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick),
+        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick),
+        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick),
+        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick),
+        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck),
+        CLK(NULL,       "dss1_alwon_fck",       &dss1_alwon_fck_3430es2),
+        CLK("omapdss_dss",      "ick",          &dss_ick_3430es2),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es2),
+        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck),
+        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck),
+        CLK(NULL,       "usbhost_ick",  &usbhost_ick),
+        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick),
+};
+
+/*
+ * common clocks
  */
 static struct omap_clk omap3xxx_clks[] = {
-        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
-        CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
-        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck,   CK_3XXX),
-        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck,   CK_3XXX),
-        CLK(NULL,       "virt_16_8m_ck", &virt_16_8m_ck, CK_3430ES2PLUS | CK_AM35XX  | CK_36XX),
-        CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck, CK_3XXX),
-        CLK(NULL,       "virt_26000000_ck", &virt_26000000_ck, CK_3XXX),
-        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck, CK_3XXX),
-        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck,    CK_3XXX),
-        CLK("twl",      "fck",          &osc_sys_ck,    CK_3XXX),
-        CLK(NULL,       "sys_ck",       &sys_ck,        CK_3XXX),
-        CLK(NULL,       "sys_altclk",   &sys_altclk,    CK_3XXX),
-        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks,    CK_3XXX),
-        CLK(NULL,       "sys_clkout1",  &sys_clkout1,   CK_3XXX),
-        CLK(NULL,       "dpll1_ck",     &dpll1_ck,      CK_3XXX),
-        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_ck",     &dpll2_ck,      CK_34XX | CK_36XX),
-        CLK(NULL,       "dpll2_m2_ck",  &dpll2_m2_ck,   CK_34XX | CK_36XX),
-        CLK(NULL,       "dpll3_ck",     &dpll3_ck,      CK_3XXX),
-        CLK(NULL,       "core_ck",      &core_ck,       CK_3XXX),
-        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
-        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
-        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
-        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
-        CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
-        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
-        CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
-        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
-        CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
-        CLK(NULL,       "omap_48m_fck", &omap_48m_fck,  CK_3XXX),
-        CLK(NULL,       "omap_12m_fck", &omap_12m_fck,  CK_3XXX),
-        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
-        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
-        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
-        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck, CK_3XXX),
-        CLK(NULL,       "sys_clkout2",  &sys_clkout2,   CK_3XXX),
-        CLK(NULL,       "corex2_fck",   &corex2_fck,    CK_3XXX),
-        CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
-        CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
-        CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
-        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
-        CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
-        CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
-        CLK(NULL,       "l3_ick",       &l3_ick,        CK_3XXX),
-        CLK(NULL,       "l4_ick",       &l4_ick,        CK_3XXX),
-        CLK(NULL,       "rm_ick",       &rm_ick,        CK_3XXX),
-        CLK(NULL,       "gfx_l3_ck",    &gfx_l3_ck,     CK_3430ES1),
-        CLK(NULL,       "gfx_l3_fck",   &gfx_l3_fck,    CK_3430ES1),
-        CLK(NULL,       "gfx_l3_ick",   &gfx_l3_ick,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg1_ck",   &gfx_cg1_ck,    CK_3430ES1),
-        CLK(NULL,       "gfx_cg2_ck",   &gfx_cg2_ck,    CK_3430ES1),
-        CLK(NULL,       "sgx_fck",      &sgx_fck,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "sgx_ick",      &sgx_ick,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "d2d_26m_fck",  &d2d_26m_fck,   CK_3430ES1),
-        CLK(NULL,       "modem_fck",    &modem_fck,     CK_34XX | CK_36XX),
-        CLK(NULL,       "sad2d_ick",    &sad2d_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "mad2d_ick",    &mad2d_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "gpt10_fck",    &gpt10_fck,     CK_3XXX),
-        CLK(NULL,       "gpt11_fck",    &gpt11_fck,     CK_3XXX),
-        CLK(NULL,       "cpefuse_fck",  &cpefuse_fck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
-        CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
-        CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_34XX | CK_36XX),
-        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_3XXX),
-        CLK(NULL,       "i2c3_fck",     &i2c3_fck,      CK_3XXX),
-        CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_3XXX),
-        CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_3XXX),
-        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_3XXX),
-        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_3XXX),
-        CLK(NULL,       "core_48m_fck", &core_48m_fck,  CK_3XXX),
-        CLK(NULL,       "mcspi4_fck",   &mcspi4_fck,    CK_3XXX),
-        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_3XXX),
-        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_3XXX),
-        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_3XXX),
-        CLK(NULL,       "uart2_fck",    &uart2_fck,     CK_3XXX),
-        CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_3XXX),
-        CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
-        CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
-        CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
-        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
-        CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
-        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
-        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
-        CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
-        CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
-        CLK(NULL,       "pka_ick",      &pka_ick,       CK_34XX | CK_36XX),
-        CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
-        CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
-        CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
-        CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
-        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
-        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
-        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
-        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
-        CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
-        CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
-        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
-        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
-        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
-        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
-        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
-        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
-        CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
-        CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
-        CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
-        CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
-        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
-        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
-        CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
-        CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
-        CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
-        CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
-        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
-        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
-        CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
-        CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
-        CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
-        CLK(NULL,       "ssi_l4_ick",   &ssi_l4_ick,    CK_34XX | CK_36XX),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "ssi_ick",      &ssi_ick_3430es2,       CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "usb_l4_ick",   &usb_l4_ick,    CK_3430ES1),
-        CLK(NULL,       "security_l4_ick2", &security_l4_ick2, CK_34XX | CK_36XX),
-        CLK(NULL,       "aes1_ick",     &aes1_ick,      CK_34XX | CK_36XX),
-        CLK("omap_rng", "ick",          &rng_ick,       CK_34XX | CK_36XX),
-        CLK(NULL,       "sha11_ick",    &sha11_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "des1_ick",     &des1_ick,      CK_34XX | CK_36XX),
-        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es1, CK_3430ES1),
-        CLK(NULL,       "dss1_alwon_fck",               &dss1_alwon_fck_3430es2, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck,    CK_3XXX),
-        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
-        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
-        CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
-        CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
-        CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
-        CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
-        CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
-        CLK(NULL,       "usbhost_120m_fck", &usbhost_120m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "usbhost_48m_fck", &usbhost_48m_fck, CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK("usbhs_omap",       "usbhost_ick",  &usbhost_ick,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
-        CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
-        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
-        CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
-        CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
-        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck,  CK_3XXX),
-        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck,    CK_3XXX),
-        CLK(NULL,       "wdt2_fck",             &wdt2_fck,      CK_3XXX),
-        CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
-        CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
-        CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
-        CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
-        CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
-        CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
-        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
-        CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_3XXX),
-        CLK(NULL,       "gpt1_ick",     &gpt1_ick,      CK_3XXX),
-        CLK(NULL,       "per_96m_fck",  &per_96m_fck,   CK_3XXX),
-        CLK(NULL,       "per_48m_fck",  &per_48m_fck,   CK_3XXX),
-        CLK(NULL,       "uart3_fck",    &uart3_fck,     CK_3XXX),
-        CLK(NULL,       "uart4_fck",    &uart4_fck,     CK_36XX),
-        CLK(NULL,       "uart4_fck",    &uart4_fck_am35xx, CK_AM35XX),
-        CLK(NULL,       "gpt2_fck",     &gpt2_fck,      CK_3XXX),
-        CLK(NULL,       "gpt3_fck",     &gpt3_fck,      CK_3XXX),
-        CLK(NULL,       "gpt4_fck",     &gpt4_fck,      CK_3XXX),
-        CLK(NULL,       "gpt5_fck",     &gpt5_fck,      CK_3XXX),
-        CLK(NULL,       "gpt6_fck",     &gpt6_fck,      CK_3XXX),
-        CLK(NULL,       "gpt7_fck",     &gpt7_fck,      CK_3XXX),
-        CLK(NULL,       "gpt8_fck",     &gpt8_fck,      CK_3XXX),
-        CLK(NULL,       "gpt9_fck",     &gpt9_fck,      CK_3XXX),
-        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck, CK_3XXX),
-        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck,    CK_3XXX),
-        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck,    CK_3XXX),
-        CLK(NULL,       "wdt3_fck",     &wdt3_fck,      CK_3XXX),
-        CLK(NULL,       "per_l4_ick",   &per_l4_ick,    CK_3XXX),
-        CLK(NULL,       "gpio6_ick",    &gpio6_ick,     CK_3XXX),
-        CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_3XXX),
-        CLK(NULL,       "gpio4_ick",    &gpio4_ick,     CK_3XXX),
-        CLK(NULL,       "gpio3_ick",    &gpio3_ick,     CK_3XXX),
-        CLK(NULL,       "gpio2_ick",    &gpio2_ick,     CK_3XXX),
-        CLK(NULL,       "wdt3_ick",     &wdt3_ick,      CK_3XXX),
-        CLK(NULL,       "uart3_ick",    &uart3_ick,     CK_3XXX),
-        CLK(NULL,       "uart4_ick",    &uart4_ick,     CK_36XX),
-        CLK(NULL,       "gpt9_ick",     &gpt9_ick,      CK_3XXX),
-        CLK(NULL,       "gpt8_ick",     &gpt8_ick,      CK_3XXX),
-        CLK(NULL,       "gpt7_ick",     &gpt7_ick,      CK_3XXX),
-        CLK(NULL,       "gpt6_ick",     &gpt6_ick,      CK_3XXX),
-        CLK(NULL,       "gpt5_ick",     &gpt5_ick,      CK_3XXX),
-        CLK(NULL,       "gpt4_ick",     &gpt4_ick,      CK_3XXX),
-        CLK(NULL,       "gpt3_ick",     &gpt3_ick,      CK_3XXX),
-        CLK(NULL,       "gpt2_ick",     &gpt2_ick,      CK_3XXX),
-        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
-        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
-        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
-        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
-        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
-        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
-        CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
-        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
-        CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
-        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
-        CLK(NULL,       "atclk_fck",    &atclk_fck,     CK_3XXX),
-        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck, CK_3XXX),
-        CLK(NULL,       "traceclk_fck", &traceclk_fck,  CK_3XXX),
-        CLK(NULL,       "sr1_fck",      &sr1_fck,       CK_34XX | CK_36XX),
-        CLK(NULL,       "sr2_fck",      &sr2_fck,       CK_34XX | CK_36XX),
-        CLK(NULL,       "sr_l4_ick",    &sr_l4_ick,     CK_34XX | CK_36XX),
-        CLK(NULL,       "secure_32k_fck", &secure_32k_fck, CK_3XXX),
-        CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_3XXX),
-        CLK(NULL,       "wdt1_fck",     &wdt1_fck,      CK_3XXX),
-        CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
-        CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
-        CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
-        CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
-        CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
-        CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
-        CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
-        CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
-        CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
-        CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
-        CLK(NULL,       "hsotgusb_fck",         &hsotgusb_fck_am35xx,   CK_AM35XX),
-        CLK(NULL,       "hecc_ck",      &hecc_ck,       CK_AM35XX),
-        CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
-        CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
-        CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
+        CLK(NULL,       "apb_pclk",     &dummy_apb_pclk),
+        CLK(NULL,       "omap_32k_fck", &omap_32k_fck),
+        CLK(NULL,       "virt_12m_ck",  &virt_12m_ck),
+        CLK(NULL,       "virt_13m_ck",  &virt_13m_ck),
+        CLK(NULL,       "virt_19200000_ck", &virt_19200000_ck),
+        CLK(NULL,       "virt_26000000_ck", &virt_26000000_ck),
+        CLK(NULL,       "virt_38_4m_ck", &virt_38_4m_ck),
+        CLK(NULL,       "osc_sys_ck",   &osc_sys_ck),
+        CLK("twl",      "fck",          &osc_sys_ck),
+        CLK(NULL,       "sys_ck",       &sys_ck),
+        CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck),
+        CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck),
+        CLK(NULL,       "sys_altclk",   &sys_altclk),
+        CLK(NULL,       "mcbsp_clks",   &mcbsp_clks),
+        CLK(NULL,       "sys_clkout1",  &sys_clkout1),
+        CLK(NULL,       "dpll1_ck",     &dpll1_ck),
+        CLK(NULL,       "dpll1_x2_ck",  &dpll1_x2_ck),
+        CLK(NULL,       "dpll1_x2m2_ck", &dpll1_x2m2_ck),
+        CLK(NULL,       "dpll3_ck",     &dpll3_ck),
+        CLK(NULL,       "core_ck",      &core_ck),
+        CLK(NULL,       "dpll3_x2_ck",  &dpll3_x2_ck),
+        CLK(NULL,       "dpll3_m2_ck",  &dpll3_m2_ck),
+        CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck),
+        CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck),
+        CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck),
+        CLK(NULL,       "dpll4_ck",     &dpll4_ck),
+        CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck),
+        CLK(NULL,       "omap_96m_fck", &omap_96m_fck),
+        CLK(NULL,       "cm_96m_fck",   &cm_96m_fck),
+        CLK(NULL,       "omap_54m_fck", &omap_54m_fck),
+        CLK(NULL,       "omap_48m_fck", &omap_48m_fck),
+        CLK(NULL,       "omap_12m_fck", &omap_12m_fck),
+        CLK(NULL,       "dpll4_m2_ck",  &dpll4_m2_ck),
+        CLK(NULL,       "dpll4_m2x2_ck", &dpll4_m2x2_ck),
+        CLK(NULL,       "dpll4_m3_ck",  &dpll4_m3_ck),
+        CLK(NULL,       "dpll4_m3x2_ck", &dpll4_m3x2_ck),
+        CLK(NULL,       "dpll4_m4_ck",  &dpll4_m4_ck),
+        CLK(NULL,       "dpll4_m4x2_ck", &dpll4_m4x2_ck),
+        CLK(NULL,       "dpll4_m5_ck",  &dpll4_m5_ck),
+        CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck),
+        CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck),
+        CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck),
+        CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck),
+        CLK(NULL,       "clkout2_src_ck", &clkout2_src_ck),
+        CLK(NULL,       "sys_clkout2",  &sys_clkout2),
+        CLK(NULL,       "corex2_fck",   &corex2_fck),
+        CLK(NULL,       "dpll1_fck",    &dpll1_fck),
+        CLK(NULL,       "mpu_ck",       &mpu_ck),
+        CLK(NULL,       "arm_fck",      &arm_fck),
+        CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck),
+        CLK(NULL,       "l3_ick",       &l3_ick),
+        CLK(NULL,       "l4_ick",       &l4_ick),
+        CLK(NULL,       "rm_ick",       &rm_ick),
+        CLK(NULL,       "gpt10_fck",    &gpt10_fck),
+        CLK(NULL,       "gpt11_fck",    &gpt11_fck),
+        CLK(NULL,       "core_96m_fck", &core_96m_fck),
+        CLK(NULL,       "mmchs2_fck",   &mmchs2_fck),
+        CLK(NULL,       "mmchs1_fck",   &mmchs1_fck),
+        CLK(NULL,       "i2c3_fck",     &i2c3_fck),
+        CLK(NULL,       "i2c2_fck",     &i2c2_fck),
+        CLK(NULL,       "i2c1_fck",     &i2c1_fck),
+        CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck),
+        CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck),
+        CLK(NULL,       "core_48m_fck", &core_48m_fck),
+        CLK(NULL,       "mcspi4_fck",   &mcspi4_fck),
+        CLK(NULL,       "mcspi3_fck",   &mcspi3_fck),
+        CLK(NULL,       "mcspi2_fck",   &mcspi2_fck),
+        CLK(NULL,       "mcspi1_fck",   &mcspi1_fck),
+        CLK(NULL,       "uart2_fck",    &uart2_fck),
+        CLK(NULL,       "uart1_fck",    &uart1_fck),
+        CLK(NULL,       "core_12m_fck", &core_12m_fck),
+        CLK("omap_hdq.0",       "fck",  &hdq_fck),
+        CLK(NULL,       "hdq_fck",      &hdq_fck),
+        CLK(NULL,       "core_l3_ick",  &core_l3_ick),
+        CLK(NULL,       "sdrc_ick",     &sdrc_ick),
+        CLK(NULL,       "gpmc_fck",     &gpmc_fck),
+        CLK(NULL,       "core_l4_ick",  &core_l4_ick),
+        CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick),
+        CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick),
+        CLK("omap_hdq.0", "ick",        &hdq_ick),
+        CLK(NULL,       "hdq_ick",      &hdq_ick),
+        CLK("omap2_mcspi.4", "ick",     &mcspi4_ick),
+        CLK("omap2_mcspi.3", "ick",     &mcspi3_ick),
+        CLK("omap2_mcspi.2", "ick",     &mcspi2_ick),
+        CLK("omap2_mcspi.1", "ick",     &mcspi1_ick),
+        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick),
+        CLK("omap_i2c.3", "ick",        &i2c3_ick),
+        CLK("omap_i2c.2", "ick",        &i2c2_ick),
+        CLK("omap_i2c.1", "ick",        &i2c1_ick),
+        CLK(NULL,       "i2c3_ick",     &i2c3_ick),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick),
+        CLK(NULL,       "uart2_ick",    &uart2_ick),
+        CLK(NULL,       "uart1_ick",    &uart1_ick),
+        CLK(NULL,       "gpt11_ick",    &gpt11_ick),
+        CLK(NULL,       "gpt10_ick",    &gpt10_ick),
+        CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick),
+        CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick),
+        CLK(NULL,       "omapctrl_ick", &omapctrl_ick),
+        CLK(NULL,       "dss_tv_fck",   &dss_tv_fck),
+        CLK(NULL,       "dss_96m_fck",  &dss_96m_fck),
+        CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck),
+        CLK(NULL,       "utmi_p1_gfclk",        &dummy_ck),
+        CLK(NULL,       "utmi_p2_gfclk",        &dummy_ck),
+        CLK(NULL,       "xclk60mhsp1_ck",       &dummy_ck),
+        CLK(NULL,       "xclk60mhsp2_ck",       &dummy_ck),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &dummy_ck),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
+        CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck),
+        CLK(NULL,       "init_60m_fclk",        &dummy_ck),
+        CLK(NULL,       "gpt1_fck",     &gpt1_fck),
+        CLK(NULL,       "wkup_32k_fck", &wkup_32k_fck),
+        CLK(NULL,       "gpio1_dbck",   &gpio1_dbck),
+        CLK(NULL,       "wdt2_fck",             &wdt2_fck),
+        CLK("omap_wdt", "ick",          &wdt2_ick),
+        CLK(NULL,       "wdt2_ick",     &wdt2_ick),
+        CLK(NULL,       "wdt1_ick",     &wdt1_ick),
+        CLK(NULL,       "gpio1_ick",    &gpio1_ick),
+        CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick),
+        CLK(NULL,       "gpt12_ick",    &gpt12_ick),
+        CLK(NULL,       "gpt1_ick",     &gpt1_ick),
+        CLK(NULL,       "per_96m_fck",  &per_96m_fck),
+        CLK(NULL,       "per_48m_fck",  &per_48m_fck),
+        CLK(NULL,       "uart3_fck",    &uart3_fck),
+        CLK(NULL,       "gpt2_fck",     &gpt2_fck),
+        CLK(NULL,       "gpt3_fck",     &gpt3_fck),
+        CLK(NULL,       "gpt4_fck",     &gpt4_fck),
+        CLK(NULL,       "gpt5_fck",     &gpt5_fck),
+        CLK(NULL,       "gpt6_fck",     &gpt6_fck),
+        CLK(NULL,       "gpt7_fck",     &gpt7_fck),
+        CLK(NULL,       "gpt8_fck",     &gpt8_fck),
+        CLK(NULL,       "gpt9_fck",     &gpt9_fck),
+        CLK(NULL,       "per_32k_alwon_fck", &per_32k_alwon_fck),
+        CLK(NULL,       "gpio6_dbck",   &gpio6_dbck),
+        CLK(NULL,       "gpio5_dbck",   &gpio5_dbck),
+        CLK(NULL,       "gpio4_dbck",   &gpio4_dbck),
+        CLK(NULL,       "gpio3_dbck",   &gpio3_dbck),
+        CLK(NULL,       "gpio2_dbck",   &gpio2_dbck),
+        CLK(NULL,       "wdt3_fck",     &wdt3_fck),
+        CLK(NULL,       "per_l4_ick",   &per_l4_ick),
+        CLK(NULL,       "gpio6_ick",    &gpio6_ick),
+        CLK(NULL,       "gpio5_ick",    &gpio5_ick),
+        CLK(NULL,       "gpio4_ick",    &gpio4_ick),
+        CLK(NULL,       "gpio3_ick",    &gpio3_ick),
+        CLK(NULL,       "gpio2_ick",    &gpio2_ick),
+        CLK(NULL,       "wdt3_ick",     &wdt3_ick),
+        CLK(NULL,       "uart3_ick",    &uart3_ick),
+        CLK(NULL,       "uart4_ick",    &uart4_ick),
+        CLK(NULL,       "gpt9_ick",     &gpt9_ick),
+        CLK(NULL,       "gpt8_ick",     &gpt8_ick),
+        CLK(NULL,       "gpt7_ick",     &gpt7_ick),
+        CLK(NULL,       "gpt6_ick",     &gpt6_ick),
+        CLK(NULL,       "gpt5_ick",     &gpt5_ick),
+        CLK(NULL,       "gpt4_ick",     &gpt4_ick),
+        CLK(NULL,       "gpt3_ick",     &gpt3_ick),
+        CLK(NULL,       "gpt2_ick",     &gpt2_ick),
+        CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick),
+        CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick),
+        CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick),
+        CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck),
+        CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck),
+        CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck),
+        CLK("etb",      "emu_src_ck",   &emu_src_ck),
+        CLK(NULL,       "emu_src_ck",   &emu_src_ck),
+        CLK(NULL,       "pclk_fck",     &pclk_fck),
+        CLK(NULL,       "pclkx2_fck",   &pclkx2_fck),
+        CLK(NULL,       "atclk_fck",    &atclk_fck),
+        CLK(NULL,       "traceclk_src_fck", &traceclk_src_fck),
+        CLK(NULL,       "traceclk_fck", &traceclk_fck),
+        CLK(NULL,       "secure_32k_fck", &secure_32k_fck),
+        CLK(NULL,       "gpt12_fck",    &gpt12_fck),
+        CLK(NULL,       "wdt1_fck",     &wdt1_fck),
+        CLK(NULL,       "timer_32k_ck", &omap_32k_fck),
+        CLK(NULL,       "timer_sys_ck", &sys_ck),
+        CLK(NULL,       "cpufreq_ck",   &dpll1_ck),
 };
 
 static const char *enable_init_clks[] = {
@@ -3512,8 +3548,27 @@ static const char *enable_init_clks[] = {
 
 int __init omap3xxx_clk_init(void)
 {
-        struct omap_clk *c;
-        u32 cpu_clkflg = 0;
+        if (omap3_has_192mhz_clk())
+                omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
+
+        if (cpu_is_omap3630()) {
+                dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
+                dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
+                dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
+                dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
+                dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
+                dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
+        }
+
+        /*
+         * XXX This type of dynamic rewriting of the clock tree is
+         * deprecated and should be revised soon.
+         */
+        if (cpu_is_omap3630())
+                dpll4_dd = dpll4_dd_3630;
+        else
+                dpll4_dd = dpll4_dd_34xx;
+
 
         /*
          * 3505 must be tested before 3517, since 3517 returns true
@@ -3523,13 +3578,20 @@ int __init omap3xxx_clk_init(void)
          */
         if (soc_is_am35xx()) {
                 cpu_mask = RATE_IN_34XX;
-                cpu_clkflg = CK_AM35XX;
+                omap_clocks_register(am35xx_clks, ARRAY_SIZE(am35xx_clks));
+                omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
+                                     ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
+                omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
         } else if (cpu_is_omap3630()) {
                 cpu_mask = (RATE_IN_34XX | RATE_IN_36XX);
-                cpu_clkflg = CK_36XX;
-        } else if (cpu_is_ti816x()) {
-                cpu_mask = RATE_IN_TI816X;
-                cpu_clkflg = CK_TI816X;
+                omap_clocks_register(omap36xx_clks, ARRAY_SIZE(omap36xx_clks));
+                omap_clocks_register(omap36xx_omap3430es2plus_clks,
+                                     ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
+                omap_clocks_register(omap34xx_omap36xx_clks,
+                                     ARRAY_SIZE(omap34xx_omap36xx_clks));
+                omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
+                                     ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
+                omap_clocks_register(omap3xxx_clks, ARRAY_SIZE(omap3xxx_clks));
         } else if (soc_is_am33xx()) {
                 cpu_mask = RATE_IN_AM33XX;
         } else if (cpu_is_ti814x()) {
@@ -3537,49 +3599,32 @@ int __init omap3xxx_clk_init(void)
         } else if (cpu_is_omap34xx()) {
                 if (omap_rev() == OMAP3430_REV_ES1_0) {
                         cpu_mask = RATE_IN_3430ES1;
-                        cpu_clkflg = CK_3430ES1;
+                        omap_clocks_register(omap3430es1_clks,
+                                             ARRAY_SIZE(omap3430es1_clks));
+                        omap_clocks_register(omap34xx_omap36xx_clks,
+                                             ARRAY_SIZE(omap34xx_omap36xx_clks));
+                        omap_clocks_register(omap3xxx_clks,
+                                             ARRAY_SIZE(omap3xxx_clks));
                 } else {
                         /*
                          * Assume that anything that we haven't matched yet
                          * has 3430ES2-type clocks.
                          */
                         cpu_mask = RATE_IN_3430ES2PLUS;
-                        cpu_clkflg = CK_3430ES2PLUS;
+                        omap_clocks_register(omap34xx_omap36xx_clks,
+                                             ARRAY_SIZE(omap34xx_omap36xx_clks));
+                        omap_clocks_register(omap36xx_omap3430es2plus_clks,
+                                             ARRAY_SIZE(omap36xx_omap3430es2plus_clks));
+                        omap_clocks_register(omap36xx_am35xx_omap3430es2plus_clks,
+                                             ARRAY_SIZE(omap36xx_am35xx_omap3430es2plus_clks));
+                        omap_clocks_register(omap3xxx_clks,
+                                             ARRAY_SIZE(omap3xxx_clks));
                 }
         } else {
                 WARN(1, "clock: could not identify OMAP3 variant\n");
         }
 
-        if (omap3_has_192mhz_clk())
-                omap_96m_alwon_fck = omap_96m_alwon_fck_3630;
-
-        if (cpu_is_omap3630()) {
-                dpll3_m3x2_ck = dpll3_m3x2_ck_3630;
-                dpll4_m2x2_ck = dpll4_m2x2_ck_3630;
-                dpll4_m3x2_ck = dpll4_m3x2_ck_3630;
-                dpll4_m4x2_ck = dpll4_m4x2_ck_3630;
-                dpll4_m5x2_ck = dpll4_m5x2_ck_3630;
-                dpll4_m6x2_ck = dpll4_m6x2_ck_3630;
-        }
-
-        /*
-         * XXX This type of dynamic rewriting of the clock tree is
-         * deprecated and should be revised soon.
-         */
-        if (cpu_is_omap3630())
-                dpll4_dd = dpll4_dd_3630;
-        else
-                dpll4_dd = dpll4_dd_34xx;
-
-        for (c = omap3xxx_clks; c < omap3xxx_clks + ARRAY_SIZE(omap3xxx_clks);
-             c++)
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        if (!__clk_init(NULL, c->lk.clk))
-                                omap2_init_clk_hw_omap_clocks(c->lk.clk);
-                }
-
-        omap2_clk_disable_autoidle_all();
+                omap2_clk_disable_autoidle_all();
 
         omap2_clk_enable_init_clocks(enable_init_clks,
                                      ARRAY_SIZE(enable_init_clks));
diff --git a/arch/arm/mach-omap2/cclock44xx_data.c b/arch/arm/mach-omap2/cclock44xx_data.c
index 0c6834ae1fc4..88e37a474334 100644
--- a/arch/arm/mach-omap2/cclock44xx_data.c
+++ b/arch/arm/mach-omap2/cclock44xx_data.c
@@ -1424,284 +1424,285 @@ DEFINE_CLK_MUX(auxclkreq5_ck, auxclkreq_ck_parents, NULL, 0x0,
                0x0, NULL);
 
 /*
- * clkdev
+ * clocks specific to omap4460
  */
+static struct omap_clk omap446x_clks[] = {
+        CLK(NULL,       "div_ts_ck",                    &div_ts_ck),
+        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk),
+};
+
+/*
+ * clocks specific to omap4430
+ */
+static struct omap_clk omap443x_clks[] = {
+        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk),
+};
 
+/*
+ * clocks common to omap44xx
+ */
 static struct omap_clk omap44xx_clks[] = {
-        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck,       CK_443X),
-        CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck,       CK_443X),
-        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck,   CK_443X),
-        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck,      CK_443X),
-        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck, CK_443X),
-        CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk,       CK_443X),
-        CLK(NULL,       "slimbus_clk",                  &slimbus_clk,   CK_443X),
-        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck,    CK_443X),
-        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck,      CK_443X),
-        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck,      CK_443X),
-        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck,      CK_443X),
-        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck,      CK_443X),
-        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck,      CK_443X),
-        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck,      CK_443X),
-        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck,      CK_443X),
-        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck,  CK_443X),
-        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck,      CK_443X),
-        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck,    CK_443X),
-        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck,        CK_443X),
-        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck,        CK_443X),
-        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck, CK_443X),
-        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck,    CK_443X),
-        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck,        CK_443X),
-        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck,   CK_443X),
-        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck,        CK_443X),
-        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck,      CK_443X),
-        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk,  CK_443X),
-        CLK(NULL,       "abe_clk",                      &abe_clk,       CK_443X),
-        CLK(NULL,       "aess_fclk",                    &aess_fclk,     CK_443X),
-        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck,      CK_443X),
-        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck,       CK_443X),
-        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck,  CK_443X),
-        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck,       CK_443X),
-        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck,     CK_443X),
-        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck, CK_443X),
-        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck,       CK_443X),
-        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck,     CK_443X),
-        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck,     CK_443X),
-        CLK(NULL,       "div_core_ck",                  &div_core_ck,   CK_443X),
-        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk,        CK_443X),
-        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk,        CK_443X),
-        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck,     CK_443X),
-        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck,        CK_443X),
-        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck,        CK_443X),
-        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck,     CK_443X),
-        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck,     CK_443X),
-        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck,        CK_443X),
-        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck,   CK_443X),
-        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck,        CK_443X),
-        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck,   CK_443X),
-        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck,        CK_443X),
-        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck,     CK_443X),
-        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck,   CK_443X),
-        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck,        CK_443X),
-        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck,      CK_443X),
-        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck,      CK_443X),
-        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck,     CK_443X),
-        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck,   CK_443X),
-        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck, CK_443X),
-        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck,        CK_443X),
-        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck,     CK_443X),
-        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk, CK_443X),
-        CLK(NULL,       "func_24m_clk",                 &func_24m_clk,  CK_443X),
-        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk,        CK_443X),
-        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk, CK_443X),
-        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk,        CK_443X),
-        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk, CK_443X),
-        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk, CK_443X),
-        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk, CK_443X),
-        CLK(NULL,       "l3_div_ck",                    &l3_div_ck,     CK_443X),
-        CLK(NULL,       "l4_div_ck",                    &l4_div_ck,     CK_443X),
-        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck, CK_443X),
-        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck,    CK_443X),
-        CLK("smp_twd",  NULL,                           &mpu_periphclk, CK_443X),
-        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk,  CK_443X),
-        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk,      CK_443X),
-        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk,       CK_443X),
-        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck,        CK_443X),
-        CLK(NULL,       "aes1_fck",                     &aes1_fck,      CK_443X),
-        CLK(NULL,       "aes2_fck",                     &aes2_fck,      CK_443X),
-        CLK(NULL,       "bandgap_fclk",                 &bandgap_fclk,  CK_443X),
-        CLK(NULL,       "div_ts_ck",                    &div_ts_ck,     CK_446X),
-        CLK(NULL,       "bandgap_ts_fclk",              &bandgap_ts_fclk,       CK_446X),
-        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck,      CK_443X),
-        CLK(NULL,       "func_dmic_abe_gfclk",                  &func_dmic_abe_gfclk,   CK_443X),
-        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk,   CK_443X),
-        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
-        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
-        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
-        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
-        CLK("omapdss_dss",      "ick",                  &dss_fck,       CK_443X),
-        CLK(NULL,       "fdif_fck",                     &fdif_fck,      CK_443X),
-        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk,   CK_443X),
-        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk,   CK_443X),
-        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk,   CK_443X),
-        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk,   CK_443X),
-        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk,   CK_443X),
-        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk,   CK_443X),
-        CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux,   CK_443X),
-        CLK(NULL,       "hsi_fck",                      &hsi_fck,       CK_443X),
-        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk,   CK_443X),
-        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck,     CK_443X),
-        CLK(NULL,       "func_mcasp_abe_gfclk",                 &func_mcasp_abe_gfclk,  CK_443X),
-        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "func_mcbsp1_gfclk",                    &func_mcbsp1_gfclk,     CK_443X),
-        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "func_mcbsp2_gfclk",                    &func_mcbsp2_gfclk,     CK_443X),
-        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "func_mcbsp3_gfclk",                    &func_mcbsp3_gfclk,     CK_443X),
-        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck,    CK_443X),
-        CLK(NULL,       "per_mcbsp4_gfclk",                     &per_mcbsp4_gfclk,      CK_443X),
-        CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk,   CK_443X),
-        CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk,   CK_443X),
-        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
-        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
-        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1,       CK_443X),
-        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0,       CK_443X),
-        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2,       CK_443X),
-        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk,  CK_443X),
-        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1,       CK_443X),
-        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0,       CK_443X),
-        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk,  CK_443X),
-        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck,  CK_443X),
-        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck,   CK_443X),
-        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck,   CK_443X),
-        CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux,  CK_443X),
-        CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux,  CK_443X),
-        CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux,  CK_443X),
-        CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux,   CK_443X),
-        CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux,   CK_443X),
-        CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux,   CK_443X),
-        CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux,       CK_443X),
-        CLK(NULL,       "timer6_sync_mux",                      &timer6_sync_mux,       CK_443X),
-        CLK(NULL,       "timer7_sync_mux",                      &timer7_sync_mux,       CK_443X),
-        CLK(NULL,       "timer8_sync_mux",                      &timer8_sync_mux,       CK_443X),
-        CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux,   CK_443X),
-        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
-        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
-        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
-        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk,       CK_443X),
-        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk,       CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk,   CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk,    CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
-        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
-        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
-        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
-        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
-        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
-        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
-        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
-        CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick,        CK_443X),
-        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
-        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
-        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
-        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
-        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
-        CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
-        CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
-        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck,  CK_443X),
-        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck,  CK_443X),
-        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck,        CK_443X),
-        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck,      CK_443X),
-        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck, CK_443X),
-        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck, CK_443X),
-        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck, CK_443X),
-        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck, CK_443X),
-        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck, CK_443X),
-        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck,        CK_443X),
-        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck,    CK_443X),
-        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck, CK_443X),
-        CLK("omap-gpmc",        "fck",                  &dummy_ck,      CK_443X),
-        CLK("omap_i2c.1",       "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_i2c.2",       "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_i2c.3",       "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_i2c.4",       "ick",                  &dummy_ck,      CK_443X),
-        CLK(NULL,       "mailboxes_ick",                &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.0",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.1",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.2",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.3",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap_hsmmc.4",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.1",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.2",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.3",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap-mcbsp.4",     "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck,      CK_443X),
-        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart1_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart2_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart3_ick",                    &dummy_ck,      CK_443X),
-        CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
-        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
-        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
-        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
-        CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
-        CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
+        CLK(NULL,       "extalt_clkin_ck",              &extalt_clkin_ck),
+        CLK(NULL,       "pad_clks_src_ck",              &pad_clks_src_ck),
+        CLK(NULL,       "pad_clks_ck",                  &pad_clks_ck),
+        CLK(NULL,       "pad_slimbus_core_clks_ck",     &pad_slimbus_core_clks_ck),
+        CLK(NULL,       "secure_32k_clk_src_ck",        &secure_32k_clk_src_ck),
+        CLK(NULL,       "slimbus_src_clk",              &slimbus_src_clk),
+        CLK(NULL,       "slimbus_clk",                  &slimbus_clk),
+        CLK(NULL,       "sys_32k_ck",                   &sys_32k_ck),
+        CLK(NULL,       "virt_12000000_ck",             &virt_12000000_ck),
+        CLK(NULL,       "virt_13000000_ck",             &virt_13000000_ck),
+        CLK(NULL,       "virt_16800000_ck",             &virt_16800000_ck),
+        CLK(NULL,       "virt_19200000_ck",             &virt_19200000_ck),
+        CLK(NULL,       "virt_26000000_ck",             &virt_26000000_ck),
+        CLK(NULL,       "virt_27000000_ck",             &virt_27000000_ck),
+        CLK(NULL,       "virt_38400000_ck",             &virt_38400000_ck),
+        CLK(NULL,       "sys_clkin_ck",                 &sys_clkin_ck),
+        CLK(NULL,       "tie_low_clock_ck",             &tie_low_clock_ck),
+        CLK(NULL,       "utmi_phy_clkout_ck",           &utmi_phy_clkout_ck),
+        CLK(NULL,       "xclk60mhsp1_ck",               &xclk60mhsp1_ck),
+        CLK(NULL,       "xclk60mhsp2_ck",               &xclk60mhsp2_ck),
+        CLK(NULL,       "xclk60motg_ck",                &xclk60motg_ck),
+        CLK(NULL,       "abe_dpll_bypass_clk_mux_ck",   &abe_dpll_bypass_clk_mux_ck),
+        CLK(NULL,       "abe_dpll_refclk_mux_ck",       &abe_dpll_refclk_mux_ck),
+        CLK(NULL,       "dpll_abe_ck",                  &dpll_abe_ck),
+        CLK(NULL,       "dpll_abe_x2_ck",               &dpll_abe_x2_ck),
+        CLK(NULL,       "dpll_abe_m2x2_ck",             &dpll_abe_m2x2_ck),
+        CLK(NULL,       "abe_24m_fclk",                 &abe_24m_fclk),
+        CLK(NULL,       "abe_clk",                      &abe_clk),
+        CLK(NULL,       "aess_fclk",                    &aess_fclk),
+        CLK(NULL,       "dpll_abe_m3x2_ck",             &dpll_abe_m3x2_ck),
+        CLK(NULL,       "core_hsd_byp_clk_mux_ck",      &core_hsd_byp_clk_mux_ck),
+        CLK(NULL,       "dpll_core_ck",                 &dpll_core_ck),
+        CLK(NULL,       "dpll_core_x2_ck",              &dpll_core_x2_ck),
+        CLK(NULL,       "dpll_core_m6x2_ck",            &dpll_core_m6x2_ck),
+        CLK(NULL,       "dbgclk_mux_ck",                &dbgclk_mux_ck),
+        CLK(NULL,       "dpll_core_m2_ck",              &dpll_core_m2_ck),
+        CLK(NULL,       "ddrphy_ck",                    &ddrphy_ck),
+        CLK(NULL,       "dpll_core_m5x2_ck",            &dpll_core_m5x2_ck),
+        CLK(NULL,       "div_core_ck",                  &div_core_ck),
+        CLK(NULL,       "div_iva_hs_clk",               &div_iva_hs_clk),
+        CLK(NULL,       "div_mpu_hs_clk",               &div_mpu_hs_clk),
+        CLK(NULL,       "dpll_core_m4x2_ck",            &dpll_core_m4x2_ck),
+        CLK(NULL,       "dll_clk_div_ck",               &dll_clk_div_ck),
+        CLK(NULL,       "dpll_abe_m2_ck",               &dpll_abe_m2_ck),
+        CLK(NULL,       "dpll_core_m3x2_ck",            &dpll_core_m3x2_ck),
+        CLK(NULL,       "dpll_core_m7x2_ck",            &dpll_core_m7x2_ck),
+        CLK(NULL,       "iva_hsd_byp_clk_mux_ck",       &iva_hsd_byp_clk_mux_ck),
+        CLK(NULL,       "dpll_iva_ck",                  &dpll_iva_ck),
+        CLK(NULL,       "dpll_iva_x2_ck",               &dpll_iva_x2_ck),
+        CLK(NULL,       "dpll_iva_m4x2_ck",             &dpll_iva_m4x2_ck),
+        CLK(NULL,       "dpll_iva_m5x2_ck",             &dpll_iva_m5x2_ck),
+        CLK(NULL,       "dpll_mpu_ck",                  &dpll_mpu_ck),
+        CLK(NULL,       "dpll_mpu_m2_ck",               &dpll_mpu_m2_ck),
+        CLK(NULL,       "per_hs_clk_div_ck",            &per_hs_clk_div_ck),
+        CLK(NULL,       "per_hsd_byp_clk_mux_ck",       &per_hsd_byp_clk_mux_ck),
+        CLK(NULL,       "dpll_per_ck",                  &dpll_per_ck),
+        CLK(NULL,       "dpll_per_m2_ck",               &dpll_per_m2_ck),
+        CLK(NULL,       "dpll_per_x2_ck",               &dpll_per_x2_ck),
+        CLK(NULL,       "dpll_per_m2x2_ck",             &dpll_per_m2x2_ck),
+        CLK(NULL,       "dpll_per_m3x2_ck",             &dpll_per_m3x2_ck),
+        CLK(NULL,       "dpll_per_m4x2_ck",             &dpll_per_m4x2_ck),
+        CLK(NULL,       "dpll_per_m5x2_ck",             &dpll_per_m5x2_ck),
+        CLK(NULL,       "dpll_per_m6x2_ck",             &dpll_per_m6x2_ck),
+        CLK(NULL,       "dpll_per_m7x2_ck",             &dpll_per_m7x2_ck),
+        CLK(NULL,       "usb_hs_clk_div_ck",            &usb_hs_clk_div_ck),
+        CLK(NULL,       "dpll_usb_ck",                  &dpll_usb_ck),
+        CLK(NULL,       "dpll_usb_clkdcoldo_ck",        &dpll_usb_clkdcoldo_ck),
+        CLK(NULL,       "dpll_usb_m2_ck",               &dpll_usb_m2_ck),
+        CLK(NULL,       "ducati_clk_mux_ck",            &ducati_clk_mux_ck),
+        CLK(NULL,       "func_12m_fclk",                &func_12m_fclk),
+        CLK(NULL,       "func_24m_clk",                 &func_24m_clk),
+        CLK(NULL,       "func_24mc_fclk",               &func_24mc_fclk),
+        CLK(NULL,       "func_48m_fclk",                &func_48m_fclk),
+        CLK(NULL,       "func_48mc_fclk",               &func_48mc_fclk),
+        CLK(NULL,       "func_64m_fclk",                &func_64m_fclk),
+        CLK(NULL,       "func_96m_fclk",                &func_96m_fclk),
+        CLK(NULL,       "init_60m_fclk",                &init_60m_fclk),
+        CLK(NULL,       "l3_div_ck",                    &l3_div_ck),
+        CLK(NULL,       "l4_div_ck",                    &l4_div_ck),
+        CLK(NULL,       "lp_clk_div_ck",                &lp_clk_div_ck),
+        CLK(NULL,       "l4_wkup_clk_mux_ck",           &l4_wkup_clk_mux_ck),
+        CLK("smp_twd",  NULL,                           &mpu_periphclk),
+        CLK(NULL,       "ocp_abe_iclk",                 &ocp_abe_iclk),
+        CLK(NULL,       "per_abe_24m_fclk",             &per_abe_24m_fclk),
+        CLK(NULL,       "per_abe_nc_fclk",              &per_abe_nc_fclk),
+        CLK(NULL,       "syc_clk_div_ck",               &syc_clk_div_ck),
+        CLK(NULL,       "aes1_fck",                     &aes1_fck),
+        CLK(NULL,       "aes2_fck",                     &aes2_fck),
+        CLK(NULL,       "dmic_sync_mux_ck",             &dmic_sync_mux_ck),
+        CLK(NULL,       "func_dmic_abe_gfclk",          &func_dmic_abe_gfclk),
+        CLK(NULL,       "dss_sys_clk",                  &dss_sys_clk),
+        CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk),
+        CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk),
+        CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk),
+        CLK(NULL,       "dss_fck",                      &dss_fck),
+        CLK("omapdss_dss",      "ick",                  &dss_fck),
+        CLK(NULL,       "fdif_fck",                     &fdif_fck),
+        CLK(NULL,       "gpio1_dbclk",                  &gpio1_dbclk),
+        CLK(NULL,       "gpio2_dbclk",                  &gpio2_dbclk),
+        CLK(NULL,       "gpio3_dbclk",                  &gpio3_dbclk),
+        CLK(NULL,       "gpio4_dbclk",                  &gpio4_dbclk),
+        CLK(NULL,       "gpio5_dbclk",                  &gpio5_dbclk),
+        CLK(NULL,       "gpio6_dbclk",                  &gpio6_dbclk),
+        CLK(NULL,       "sgx_clk_mux",                  &sgx_clk_mux),
+        CLK(NULL,       "hsi_fck",                      &hsi_fck),
+        CLK(NULL,       "iss_ctrlclk",                  &iss_ctrlclk),
+        CLK(NULL,       "mcasp_sync_mux_ck",            &mcasp_sync_mux_ck),
+        CLK(NULL,       "func_mcasp_abe_gfclk",         &func_mcasp_abe_gfclk),
+        CLK(NULL,       "mcbsp1_sync_mux_ck",           &mcbsp1_sync_mux_ck),
+        CLK(NULL,       "func_mcbsp1_gfclk",            &func_mcbsp1_gfclk),
+        CLK(NULL,       "mcbsp2_sync_mux_ck",           &mcbsp2_sync_mux_ck),
+        CLK(NULL,       "func_mcbsp2_gfclk",            &func_mcbsp2_gfclk),
+        CLK(NULL,       "mcbsp3_sync_mux_ck",           &mcbsp3_sync_mux_ck),
+        CLK(NULL,       "func_mcbsp3_gfclk",            &func_mcbsp3_gfclk),
+        CLK(NULL,       "mcbsp4_sync_mux_ck",           &mcbsp4_sync_mux_ck),
+        CLK(NULL,       "per_mcbsp4_gfclk",             &per_mcbsp4_gfclk),
+        CLK(NULL,       "hsmmc1_fclk",                  &hsmmc1_fclk),
+        CLK(NULL,       "hsmmc2_fclk",                  &hsmmc2_fclk),
+        CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m),
+        CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck),
+        CLK(NULL,       "slimbus1_fclk_1",              &slimbus1_fclk_1),
+        CLK(NULL,       "slimbus1_fclk_0",              &slimbus1_fclk_0),
+        CLK(NULL,       "slimbus1_fclk_2",              &slimbus1_fclk_2),
+        CLK(NULL,       "slimbus1_slimbus_clk",         &slimbus1_slimbus_clk),
+        CLK(NULL,       "slimbus2_fclk_1",              &slimbus2_fclk_1),
+        CLK(NULL,       "slimbus2_fclk_0",              &slimbus2_fclk_0),
+        CLK(NULL,       "slimbus2_slimbus_clk",         &slimbus2_slimbus_clk),
+        CLK(NULL,       "smartreflex_core_fck",         &smartreflex_core_fck),
+        CLK(NULL,       "smartreflex_iva_fck",          &smartreflex_iva_fck),
+        CLK(NULL,       "smartreflex_mpu_fck",          &smartreflex_mpu_fck),
+        CLK(NULL,       "dmt1_clk_mux",                 &dmt1_clk_mux),
+        CLK(NULL,       "cm2_dm10_mux",                 &cm2_dm10_mux),
+        CLK(NULL,       "cm2_dm11_mux",                 &cm2_dm11_mux),
+        CLK(NULL,       "cm2_dm2_mux",                  &cm2_dm2_mux),
+        CLK(NULL,       "cm2_dm3_mux",                  &cm2_dm3_mux),
+        CLK(NULL,       "cm2_dm4_mux",                  &cm2_dm4_mux),
+        CLK(NULL,       "timer5_sync_mux",              &timer5_sync_mux),
+        CLK(NULL,       "timer6_sync_mux",              &timer6_sync_mux),
+        CLK(NULL,       "timer7_sync_mux",              &timer7_sync_mux),
+        CLK(NULL,       "timer8_sync_mux",              &timer8_sync_mux),
+        CLK(NULL,       "cm2_dm9_mux",                  &cm2_dm9_mux),
+        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck),
+        CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck),
+        CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk),
+        CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk),
+        CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk),
+        CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &usb_host_hs_utmi_p2_clk),
+        CLK(NULL,       "usb_host_hs_utmi_p3_clk",      &usb_host_hs_utmi_p3_clk),
+        CLK(NULL,       "usb_host_hs_hsic480m_p1_clk",  &usb_host_hs_hsic480m_p1_clk),
+        CLK(NULL,       "usb_host_hs_hsic60m_p1_clk",   &usb_host_hs_hsic60m_p1_clk),
+        CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk),
+        CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk),
+        CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck),
+        CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck),
+        CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk),
+        CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk),
+        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick),
+        CLK("musb-omap2430",    "ick",                  &usb_otg_hs_ick),
+        CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k),
+        CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk),
+        CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk),
+        CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick),
+        CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick),
+        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick),
+        CLK(NULL,       "usim_ck",                      &usim_ck),
+        CLK(NULL,       "usim_fclk",                    &usim_fclk),
+        CLK(NULL,       "pmd_stm_clock_mux_ck",         &pmd_stm_clock_mux_ck),
+        CLK(NULL,       "pmd_trace_clk_mux_ck",         &pmd_trace_clk_mux_ck),
+        CLK(NULL,       "stm_clk_div_ck",               &stm_clk_div_ck),
+        CLK(NULL,       "trace_clk_div_ck",             &trace_clk_div_ck),
+        CLK(NULL,       "auxclk0_src_ck",               &auxclk0_src_ck),
+        CLK(NULL,       "auxclk0_ck",                   &auxclk0_ck),
+        CLK(NULL,       "auxclkreq0_ck",                &auxclkreq0_ck),
+        CLK(NULL,       "auxclk1_src_ck",               &auxclk1_src_ck),
+        CLK(NULL,       "auxclk1_ck",                   &auxclk1_ck),
+        CLK(NULL,       "auxclkreq1_ck",                &auxclkreq1_ck),
+        CLK(NULL,       "auxclk2_src_ck",               &auxclk2_src_ck),
+        CLK(NULL,       "auxclk2_ck",                   &auxclk2_ck),
+        CLK(NULL,       "auxclkreq2_ck",                &auxclkreq2_ck),
+        CLK(NULL,       "auxclk3_src_ck",               &auxclk3_src_ck),
+        CLK(NULL,       "auxclk3_ck",                   &auxclk3_ck),
+        CLK(NULL,       "auxclkreq3_ck",                &auxclkreq3_ck),
+        CLK(NULL,       "auxclk4_src_ck",               &auxclk4_src_ck),
+        CLK(NULL,       "auxclk4_ck",                   &auxclk4_ck),
+        CLK(NULL,       "auxclkreq4_ck",                &auxclkreq4_ck),
+        CLK(NULL,       "auxclk5_src_ck",               &auxclk5_src_ck),
+        CLK(NULL,       "auxclk5_ck",                   &auxclk5_ck),
+        CLK(NULL,       "auxclkreq5_ck",                &auxclkreq5_ck),
+        CLK("omap-gpmc",        "fck",                  &dummy_ck),
+        CLK("omap_i2c.1",       "ick",                  &dummy_ck),
+        CLK("omap_i2c.2",       "ick",                  &dummy_ck),
+        CLK("omap_i2c.3",       "ick",                  &dummy_ck),
+        CLK("omap_i2c.4",       "ick",                  &dummy_ck),
+        CLK(NULL,       "mailboxes_ick",                &dummy_ck),
+        CLK("omap_hsmmc.0",     "ick",                  &dummy_ck),
+        CLK("omap_hsmmc.1",     "ick",                  &dummy_ck),
+        CLK("omap_hsmmc.2",     "ick",                  &dummy_ck),
+        CLK("omap_hsmmc.3",     "ick",                  &dummy_ck),
+        CLK("omap_hsmmc.4",     "ick",                  &dummy_ck),
+        CLK("omap-mcbsp.1",     "ick",                  &dummy_ck),
+        CLK("omap-mcbsp.2",     "ick",                  &dummy_ck),
+        CLK("omap-mcbsp.3",     "ick",                  &dummy_ck),
+        CLK("omap-mcbsp.4",     "ick",                  &dummy_ck),
+        CLK("omap2_mcspi.1",    "ick",                  &dummy_ck),
+        CLK("omap2_mcspi.2",    "ick",                  &dummy_ck),
+        CLK("omap2_mcspi.3",    "ick",                  &dummy_ck),
+        CLK("omap2_mcspi.4",    "ick",                  &dummy_ck),
+        CLK(NULL,       "uart1_ick",                    &dummy_ck),
+        CLK(NULL,       "uart2_ick",                    &dummy_ck),
+        CLK(NULL,       "uart3_ick",                    &dummy_ck),
+        CLK(NULL,       "uart4_ick",                    &dummy_ck),
+        CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck),
+        CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck),
+        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck),
+        CLK("omap_wdt", "ick",                          &dummy_ck),
+        CLK(NULL,       "timer_32k_ck", &sys_32k_ck),
         /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
-        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
-        CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
-        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
+        CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.4",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.9",     "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.10",    "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.11",    "timer_sys_ck", &sys_clkin_ck),
+        CLK("omap_timer.5",     "timer_sys_ck", &syc_clk_div_ck),
+        CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck),
+        CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck),
+        CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck),
+        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck),
+        CLK("40138000.timer",   "timer_sys_ck", &syc_clk_div_ck),
+        CLK("4013a000.timer",   "timer_sys_ck", &syc_clk_div_ck),
+        CLK("4013c000.timer",   "timer_sys_ck", &syc_clk_div_ck),
+        CLK("4013e000.timer",   "timer_sys_ck", &syc_clk_div_ck),
+        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck),
 };
 
 int __init omap4xxx_clk_init(void)
 {
-        u32 cpu_clkflg;
-        struct omap_clk *c;
         int rc;
 
         if (cpu_is_omap443x()) {
                 cpu_mask = RATE_IN_4430;
-                cpu_clkflg = CK_443X;
+                omap_clocks_register(omap443x_clks, ARRAY_SIZE(omap443x_clks));
         } else if (cpu_is_omap446x() || cpu_is_omap447x()) {
                 cpu_mask = RATE_IN_4460 | RATE_IN_4430;
-                cpu_clkflg = CK_446X | CK_443X;
-
+                omap_clocks_register(omap446x_clks, ARRAY_SIZE(omap446x_clks));
                 if (cpu_is_omap447x())
                         pr_warn("WARNING: OMAP4470 clock data incomplete!\n");
         } else {
                 return 0;
         }
 
-        for (c = omap44xx_clks; c < omap44xx_clks + ARRAY_SIZE(omap44xx_clks);
-                                                                        c++) {
-                if (c->cpu & cpu_clkflg) {
-                        clkdev_add(&c->lk);
-                        if (!__clk_init(NULL, c->lk.clk))
-                                omap2_init_clk_hw_omap_clocks(c->lk.clk);
-                }
-        }
+        omap_clocks_register(omap44xx_clks, ARRAY_SIZE(omap44xx_clks));
 
         omap2_clk_disable_autoidle_all();
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e4ec3a69ee2e..8474c7d228ee 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -23,7 +23,7 @@
 #include <linux/clk-provider.h>
 #include <linux/io.h>
 #include <linux/bitops.h>
-
+#include <linux/clk-private.h>
 #include <asm/cpu.h>
 
 
@@ -569,6 +569,21 @@ const struct clk_hw_omap_ops clkhwops_wait = {
 };
 
 /**
+ * omap_clocks_register - register an array of omap_clk
+ * @ocs: pointer to an array of omap_clk to register
+ */
+void __init omap_clocks_register(struct omap_clk oclks[], int cnt)
+{
+        struct omap_clk *c;
+
+        for (c = oclks; c < oclks + cnt; c++) {
+                clkdev_add(&c->lk);
+                if (!__clk_init(NULL, c->lk.clk))
+                        omap2_init_clk_hw_omap_clocks(c->lk.clk);
+        }
+}
+
+/**
  * omap2_clk_switch_mpurate_at_boot - switch ARM MPU rate by boot-time argument
  * @mpurate_ck_name: clk name of the clock to change rate
  *
diff --git a/arch/arm/mach-omap2/clock.h b/arch/arm/mach-omap2/clock.h
index 60ddd8612b4d..7aa32cd292f9 100644
--- a/arch/arm/mach-omap2/clock.h
+++ b/arch/arm/mach-omap2/clock.h
@@ -27,9 +27,8 @@ struct omap_clk {
         struct clk_lookup               lk;
 };
 
-#define CLK(dev, con, ck, cp)           \
+#define CLK(dev, con, ck)               \
         {                               \
-                 .cpu = cp,             \
                 .lk = {                 \
                         .dev_id = dev,  \
                         .con_id = con,  \
@@ -37,22 +36,6 @@ struct omap_clk {
                 },                      \
         }
 
-/* Platform flags for the clkdev-OMAP integration code */
-#define CK_242X         (1 << 0)
-#define CK_243X         (1 << 1)        /* 243x, 253x */
-#define CK_3430ES1      (1 << 2)        /* 34xxES1 only */
-#define CK_3430ES2PLUS  (1 << 3)        /* 34xxES2, ES3, non-Sitara 35xx only */
-#define CK_AM35XX       (1 << 4)        /* Sitara AM35xx */
-#define CK_36XX         (1 << 5)        /* 36xx/37xx-specific clocks */
-#define CK_443X         (1 << 6)
-#define CK_TI816X       (1 << 7)
-#define CK_446X         (1 << 8)
-#define CK_AM33XX       (1 << 9)        /* AM33xx specific clocks */
-
-
-#define CK_34XX         (CK_3430ES1 | CK_3430ES2PLUS)
-#define CK_3XXX         (CK_34XX | CK_AM35XX | CK_36XX)
-
 struct clockdomain;
 #define to_clk_hw_omap(_hw) container_of(_hw, struct clk_hw_omap, hw)
 
@@ -480,4 +463,5 @@ extern int am33xx_clk_init(void);
 extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
 extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
 
+extern void omap_clocks_register(struct omap_clk *oclks, int cnt);
 #endif
diff --git a/arch/arm/mach-omap2/cpuidle34xx.c b/arch/arm/mach-omap2/cpuidle34xx.c
index cca045c95fbf..e18709d3b95d 100644
--- a/arch/arm/mach-omap2/cpuidle34xx.c
+++ b/arch/arm/mach-omap2/cpuidle34xx.c
@@ -112,8 +112,6 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
 {
         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 
-        local_fiq_disable();
-
         if (omap_irq_pending() || need_resched())
                 goto return_sleep_time;
 
@@ -148,7 +146,6 @@ static int omap3_enter_idle(struct cpuidle_device *dev,
                 clkdm_allow_idle(mpu_pd->pwrdm_clkdms[0]);
 
 return_sleep_time:
-        local_fiq_enable();
 
         return index;
 }
diff --git a/arch/arm/mach-omap2/cpuidle44xx.c b/arch/arm/mach-omap2/cpuidle44xx.c
index 5a286b56205e..c443f2e97e10 100644
--- a/arch/arm/mach-omap2/cpuidle44xx.c
+++ b/arch/arm/mach-omap2/cpuidle44xx.c
@@ -71,10 +71,7 @@ static int omap_enter_idle_simple(struct cpuidle_device *dev,
                         struct cpuidle_driver *drv,
                         int index)
 {
-        local_fiq_disable();
         omap_do_wfi();
-        local_fiq_enable();
-
         return index;
 }
 
@@ -84,8 +81,6 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
 {
         struct idle_statedata *cx = state_ptr + index;
 
-        local_fiq_disable();
-
         /*
          * CPU0 has to wait and stay ON until CPU1 is OFF state.
          * This is necessary to honour hardware recommondation
@@ -134,6 +129,7 @@ static int omap_enter_idle_coupled(struct cpuidle_device *dev,
         /* Wakeup CPU1 only if it is not offlined */
         if (dev->cpu == 0 && cpumask_test_cpu(1, cpu_online_mask)) {
                 clkdm_wakeup(cpu_clkdm[1]);
+                omap_set_pwrdm_state(cpu_pd[1], PWRDM_POWER_ON);
                 clkdm_allow_idle(cpu_clkdm[1]);
         }
 
@@ -155,8 +151,6 @@ fail:
         cpuidle_coupled_parallel_barrier(dev, &abort_barrier);
         cpu_done[dev->cpu] = false;
 
-        local_fiq_enable();
-
         return index;
 }
 
diff --git a/arch/arm/mach-omap2/dma.h b/arch/arm/mach-omap2/dma.h
index eba80dbc5218..65f80cacf178 100644
--- a/arch/arm/mach-omap2/dma.h
+++ b/arch/arm/mach-omap2/dma.h
@@ -22,69 +22,20 @@
 
 /* DMA channels for 24xx */
 #define OMAP24XX_DMA_NO_DEVICE          0
-#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
 #define OMAP24XX_DMA_EXT_DMAREQ0        2       /* S_DMA_1 */
 #define OMAP24XX_DMA_EXT_DMAREQ1        3       /* S_DMA_2 */
 #define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
-#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
-#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
-#define OMAP242X_DMA_VLYNQ_TX           7       /* S_DMA_6 */
-#define OMAP24XX_DMA_EXT_DMAREQ2        7       /* S_DMA_6 */
-#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
 #define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
 #define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
-#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
-#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
-#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP34XX_DMA_SHA2MD5_RX         13      /* S_DMA_12 */
 #define OMAP242X_DMA_EXT_DMAREQ2        14      /* S_DMA_13 */
 #define OMAP242X_DMA_EXT_DMAREQ3        15      /* S_DMA_14 */
 #define OMAP242X_DMA_EXT_DMAREQ4        16      /* S_DMA_15 */
-#define OMAP242X_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP242X_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP242X_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP242X_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP242X_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP242X_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP242X_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP242X_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP242X_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
-#define OMAP242X_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
-#define OMAP243X_DMA_EXT_DMAREQ3        14      /* S_DMA_13 */
-#define OMAP24XX_DMA_SPI3_TX0           15      /* S_DMA_14 */
-#define OMAP24XX_DMA_SPI3_RX0           16      /* S_DMA_15 */
-#define OMAP24XX_DMA_MCBSP3_TX          17      /* S_DMA_16 */
-#define OMAP24XX_DMA_MCBSP3_RX          18      /* S_DMA_17 */
-#define OMAP24XX_DMA_MCBSP4_TX          19      /* S_DMA_18 */
-#define OMAP24XX_DMA_MCBSP4_RX          20      /* S_DMA_19 */
-#define OMAP24XX_DMA_MCBSP5_TX          21      /* S_DMA_20 */
-#define OMAP24XX_DMA_MCBSP5_RX          22      /* S_DMA_21 */
-#define OMAP24XX_DMA_SPI3_TX1           23      /* S_DMA_22 */
-#define OMAP24XX_DMA_SPI3_RX1           24      /* S_DMA_23 */
-#define OMAP243X_DMA_EXT_DMAREQ4        25      /* S_DMA_24 */
-#define OMAP243X_DMA_EXT_DMAREQ5        26      /* S_DMA_25 */
 #define OMAP34XX_DMA_I2C3_TX            25      /* S_DMA_24 */
 #define OMAP34XX_DMA_I2C3_RX            26      /* S_DMA_25 */
 #define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
 #define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
 #define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
 #define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP24XX_DMA_MCBSP1_TX          31      /* S_DMA_30 */
-#define OMAP24XX_DMA_MCBSP1_RX          32      /* S_DMA_31 */
-#define OMAP24XX_DMA_MCBSP2_TX          33      /* S_DMA_32 */
-#define OMAP24XX_DMA_MCBSP2_RX          34      /* S_DMA_33 */
-#define OMAP24XX_DMA_SPI1_TX0           35      /* S_DMA_34 */
-#define OMAP24XX_DMA_SPI1_RX0           36      /* S_DMA_35 */
-#define OMAP24XX_DMA_SPI1_TX1           37      /* S_DMA_36 */
-#define OMAP24XX_DMA_SPI1_RX1           38      /* S_DMA_37 */
-#define OMAP24XX_DMA_SPI1_TX2           39      /* S_DMA_38 */
-#define OMAP24XX_DMA_SPI1_RX2           40      /* S_DMA_39 */
-#define OMAP24XX_DMA_SPI1_TX3           41      /* S_DMA_40 */
-#define OMAP24XX_DMA_SPI1_RX3           42      /* S_DMA_41 */
-#define OMAP24XX_DMA_SPI2_TX0           43      /* S_DMA_42 */
-#define OMAP24XX_DMA_SPI2_RX0           44      /* S_DMA_43 */
-#define OMAP24XX_DMA_SPI2_TX1           45      /* S_DMA_44 */
-#define OMAP24XX_DMA_SPI2_RX1           46      /* S_DMA_45 */
 #define OMAP24XX_DMA_MMC2_TX            47      /* S_DMA_46 */
 #define OMAP24XX_DMA_MMC2_RX            48      /* S_DMA_47 */
 #define OMAP24XX_DMA_UART1_TX           49      /* S_DMA_48 */
@@ -93,33 +44,12 @@
 #define OMAP24XX_DMA_UART2_RX           52      /* S_DMA_51 */
 #define OMAP24XX_DMA_UART3_TX           53      /* S_DMA_52 */
 #define OMAP24XX_DMA_UART3_RX           54      /* S_DMA_53 */
-#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* S_DMA_54 */
-#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* S_DMA_55 */
-#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* S_DMA_56 */
-#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* S_DMA_57 */
-#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* S_DMA_58 */
-#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* S_DMA_59 */
 #define OMAP24XX_DMA_MMC1_TX            61      /* S_DMA_60 */
 #define OMAP24XX_DMA_MMC1_RX            62      /* S_DMA_61 */
-#define OMAP24XX_DMA_MS                 63      /* S_DMA_62 */
 #define OMAP242X_DMA_EXT_DMAREQ5        64      /* S_DMA_63 */
-#define OMAP243X_DMA_EXT_DMAREQ6        64      /* S_DMA_63 */
-#define OMAP34XX_DMA_EXT_DMAREQ3        64      /* S_DMA_63 */
 #define OMAP34XX_DMA_AES2_TX            65      /* S_DMA_64 */
 #define OMAP34XX_DMA_AES2_RX            66      /* S_DMA_65 */
-#define OMAP34XX_DMA_DES2_TX            67      /* S_DMA_66 */
-#define OMAP34XX_DMA_DES2_RX            68      /* S_DMA_67 */
 #define OMAP34XX_DMA_SHA1MD5_RX         69      /* S_DMA_68 */
-#define OMAP34XX_DMA_SPI4_TX0           70      /* S_DMA_69 */
-#define OMAP34XX_DMA_SPI4_RX0           71      /* S_DMA_70 */
-#define OMAP34XX_DSS_DMA0               72      /* S_DMA_71 */
-#define OMAP34XX_DSS_DMA1               73      /* S_DMA_72 */
-#define OMAP34XX_DSS_DMA2               74      /* S_DMA_73 */
-#define OMAP34XX_DSS_DMA3               75      /* S_DMA_74 */
-#define OMAP34XX_DMA_MMC3_TX            77      /* S_DMA_76 */
-#define OMAP34XX_DMA_MMC3_RX            78      /* S_DMA_77 */
-#define OMAP34XX_DMA_USIM_TX            79      /* S_DMA_78 */
-#define OMAP34XX_DMA_USIM_RX            80      /* S_DMA_79 */
 
 #define OMAP36XX_DMA_UART4_TX           81      /* S_DMA_80 */
 #define OMAP36XX_DMA_UART4_RX           82      /* S_DMA_81 */
diff --git a/arch/arm/mach-omap2/omap-hotplug.c b/arch/arm/mach-omap2/omap-hotplug.c
index e712d1725a8b..458f72f9dc8f 100644
--- a/arch/arm/mach-omap2/omap-hotplug.c
+++ b/arch/arm/mach-omap2/omap-hotplug.c
@@ -19,11 +19,8 @@
 #include <linux/smp.h>
 #include <linux/io.h>
 
-#include <asm/cacheflush.h>
 #include "omap-wakeupgen.h"
-
 #include "common.h"
-
 #include "powerdomain.h"
 
 /*
@@ -35,9 +32,6 @@ void __ref omap4_cpu_die(unsigned int cpu)
         unsigned int boot_cpu = 0;
         void __iomem *base = omap_get_wakeupgen_base();
 
-        flush_cache_all();
-        dsb();
-
         /*
          * we're ready for shutdown now, so do it
          */
diff --git a/arch/arm/mach-omap2/omap-smp.c b/arch/arm/mach-omap2/omap-smp.c
index d9727218dd0a..61174b78dee6 100644
--- a/arch/arm/mach-omap2/omap-smp.c
+++ b/arch/arm/mach-omap2/omap-smp.c
@@ -21,7 +21,6 @@
 #include <linux/io.h>
 #include <linux/irqchip/arm-gic.h>
 
-#include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
 
 #include "omap-secure.h"
@@ -67,13 +66,6 @@ static void __cpuinit omap4_secondary_init(unsigned int cpu)
                                                         4, 0, 0, 0, 0, 0);
 
         /*
-         * If any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * Synchronise with the boot thread.
          */
         spin_lock(&boot_lock);
@@ -84,6 +76,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
 {
         static struct clockdomain *cpu1_clkdm;
         static bool booted;
+        static struct powerdomain *cpu1_pwrdm;
         void __iomem *base = omap_get_wakeupgen_base();
 
         /*
@@ -103,11 +96,10 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
         else
                 __raw_writel(0x20, base + OMAP_AUX_CORE_BOOT_0);
 
-        flush_cache_all();
-        smp_wmb();
-
-        if (!cpu1_clkdm)
+        if (!cpu1_clkdm && !cpu1_pwrdm) {
                 cpu1_clkdm = clkdm_lookup("mpu1_clkdm");
+                cpu1_pwrdm = pwrdm_lookup("cpu1_pwrdm");
+        }
 
         /*
          * The SGI(Software Generated Interrupts) are not wakeup capable
@@ -120,7 +112,7 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
          * Section :
          *      4.3.4.2 Power States of CPU0 and CPU1
          */
-        if (booted) {
+        if (booted && cpu1_pwrdm && cpu1_clkdm) {
                 /*
                  * GIC distributor control register has changed between
                  * CortexA9 r1pX and r2pX. The Control Register secure
@@ -141,7 +133,12 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
                         gic_dist_disable();
                 }
 
+                /*
+                 * Ensure that CPU power state is set to ON to avoid CPU
+                 * powerdomain transition on wfi
+                 */
                 clkdm_wakeup(cpu1_clkdm);
+                omap_set_pwrdm_state(cpu1_pwrdm, PWRDM_POWER_ON);
                 clkdm_allow_idle(cpu1_clkdm);
 
                 if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD)) {
@@ -168,38 +165,6 @@ static int __cpuinit omap4_boot_secondary(unsigned int cpu, struct task_struct *
         return 0;
 }
 
-static void __init wakeup_secondary(void)
-{
-        void *startup_addr = omap_secondary_startup;
-        void __iomem *base = omap_get_wakeupgen_base();
-
-        if (cpu_is_omap446x()) {
-                startup_addr = omap_secondary_startup_4460;
-                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
-        }
-
-        /*
-         * Write the address of secondary startup routine into the
-         * AuxCoreBoot1 where ROM code will jump and start executing
-         * on secondary core once out of WFE
-         * A barrier is added to ensure that write buffer is drained
-         */
-        if (omap_secure_apis_support())
-                omap_auxcoreboot_addr(virt_to_phys(startup_addr));
-        else
-                __raw_writel(virt_to_phys(omap5_secondary_startup),
-                                                base + OMAP_AUX_CORE_BOOT_1);
-
-        smp_wmb();
-
-        /*
-         * Send a 'sev' to wake the secondary core from WFE.
-         * Drain the outstanding writes to memory
-         */
-        dsb_sev();
-        mb();
-}
-
 /*
  * Initialise the CPU possible map early - this describes the CPUs
  * which may be present or become present in the system.
@@ -235,6 +200,8 @@ static void __init omap4_smp_init_cpus(void)
 
 static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
 {
+        void *startup_addr = omap_secondary_startup;
+        void __iomem *base = omap_get_wakeupgen_base();
 
         /*
          * Initialise the SCU and wake up the secondary core using
@@ -242,7 +209,24 @@ static void __init omap4_smp_prepare_cpus(unsigned int max_cpus)
          */
         if (scu_base)
                 scu_enable(scu_base);
-        wakeup_secondary();
+
+        if (cpu_is_omap446x()) {
+                startup_addr = omap_secondary_startup_4460;
+                pm44xx_errata |= PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD;
+        }
+
+        /*
+         * Write the address of secondary startup routine into the
+         * AuxCoreBoot1 where ROM code will jump and start executing
+         * on secondary core once out of WFE
+         * A barrier is added to ensure that write buffer is drained
+         */
+        if (omap_secure_apis_support())
+                omap_auxcoreboot_addr(virt_to_phys(startup_addr));
+        else
+                __raw_writel(virt_to_phys(omap5_secondary_startup),
+                                                base + OMAP_AUX_CORE_BOOT_1);
+
 }
 
 struct smp_operations omap4_smp_ops __initdata = {
diff --git a/arch/arm/mach-omap2/omap4-common.c b/arch/arm/mach-omap2/omap4-common.c
index 2aeb928efdfd..13b27ffaf45e 100644
--- a/arch/arm/mach-omap2/omap4-common.c
+++ b/arch/arm/mach-omap2/omap4-common.c
@@ -22,6 +22,7 @@
 #include <linux/of_platform.h>
 #include <linux/export.h>
 #include <linux/irqchip/arm-gic.h>
+#include <linux/of_address.h>
 
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
@@ -264,6 +265,21 @@ omap_early_initcall(omap4_sar_ram_init);
 
 void __init omap_gic_of_init(void)
 {
+        struct device_node *np;
+
+        /* Extract GIC distributor and TWD bases for OMAP4460 ROM Errata WA */
+        if (!cpu_is_omap446x())
+                goto skip_errata_init;
+
+        np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-gic");
+        gic_dist_base_addr = of_iomap(np, 0);
+        WARN_ON(!gic_dist_base_addr);
+
+        np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-twd-timer");
+        twd_base = of_iomap(np, 0);
+        WARN_ON(!twd_base);
+
+skip_errata_init:
         omap_wakeupgen_init();
         irqchip_init();
 }
diff --git a/arch/arm/mach-omap2/omap4-sar-layout.h b/arch/arm/mach-omap2/omap4-sar-layout.h
index 937417523b8e..792b1069f724 100644
--- a/arch/arm/mach-omap2/omap4-sar-layout.h
+++ b/arch/arm/mach-omap2/omap4-sar-layout.h
@@ -20,13 +20,13 @@
 #define SAR_BANK4_OFFSET                0x3000
 
 /* Scratch pad memory offsets from SAR_BANK1 */
-#define SCU_OFFSET0                             0xd00
-#define SCU_OFFSET1                             0xd04
-#define OMAP_TYPE_OFFSET                        0xd10
-#define L2X0_SAVE_OFFSET0                       0xd14
-#define L2X0_SAVE_OFFSET1                       0xd18
-#define L2X0_AUXCTRL_OFFSET                     0xd1c
-#define L2X0_PREFETCH_CTRL_OFFSET               0xd20
+#define SCU_OFFSET0                             0xfe4
+#define SCU_OFFSET1                             0xfe8
+#define OMAP_TYPE_OFFSET                        0xfec
+#define L2X0_SAVE_OFFSET0                       0xff0
+#define L2X0_SAVE_OFFSET1                       0xff4
+#define L2X0_AUXCTRL_OFFSET                     0xff8
+#define L2X0_PREFETCH_CTRL_OFFSET               0xffc
 
 /* CPUx Wakeup Non-Secure Physical Address offsets in SAR_BANK3 */
 #define CPU0_WAKEUP_NS_PA_ADDR_OFFSET           0xa04
diff --git a/arch/arm/mach-omap2/pm24xx.c b/arch/arm/mach-omap2/pm24xx.c
index b59d93908341..ce956b0a7ba4 100644
--- a/arch/arm/mach-omap2/pm24xx.c
+++ b/arch/arm/mach-omap2/pm24xx.c
@@ -200,22 +200,17 @@ static int omap2_can_sleep(void)
 
 static void omap2_pm_idle(void)
 {
-        local_fiq_disable();
-
         if (!omap2_can_sleep()) {
                 if (omap_irq_pending())
-                        goto out;
+                        return;
                 omap2_enter_mpu_retention();
-                goto out;
+                return;
         }
 
         if (omap_irq_pending())
-                goto out;
+                return;
 
         omap2_enter_full_retention();
-
-out:
-        local_fiq_enable();
 }
 
 static void __init prcm_setup_regs(void)
diff --git a/arch/arm/mach-omap2/pm34xx.c b/arch/arm/mach-omap2/pm34xx.c
index 2d93d8b23835..c01859398b54 100644
--- a/arch/arm/mach-omap2/pm34xx.c
+++ b/arch/arm/mach-omap2/pm34xx.c
@@ -346,19 +346,14 @@ void omap_sram_idle(void)
 
 static void omap3_pm_idle(void)
 {
-        local_fiq_disable();
-
         if (omap_irq_pending())
-                goto out;
+                return;
 
         trace_cpu_idle(1, smp_processor_id());
 
         omap_sram_idle();
 
         trace_cpu_idle(PWR_EVENT_EXIT, smp_processor_id());
-
-out:
-        local_fiq_enable();
 }
 
 #ifdef CONFIG_SUSPEND
@@ -757,14 +752,12 @@ int __init omap3_pm_init(void)
                         pr_err("Memory allocation failed when allocating for secure sram context\n");
 
                 local_irq_disable();
-                local_fiq_disable();
 
                 omap_dma_global_context_save();
                 omap3_save_secure_ram_context();
                 omap_dma_global_context_restore();
 
                 local_irq_enable();
-                local_fiq_enable();
         }
 
         omap3_save_scratchpad_contents();
diff --git a/arch/arm/mach-omap2/pm44xx.c b/arch/arm/mach-omap2/pm44xx.c
index 152a10cf4f1d..a251f87fa2a2 100644
--- a/arch/arm/mach-omap2/pm44xx.c
+++ b/arch/arm/mach-omap2/pm44xx.c
@@ -131,11 +131,7 @@ static int __init pwrdms_setup(struct powerdomain *pwrdm, void *unused)
  */
 static void omap_default_idle(void)
 {
-        local_fiq_disable();
-
         omap_do_wfi();
-
-        local_fiq_enable();
 }
 
 /**
@@ -147,8 +143,8 @@ static void omap_default_idle(void)
 int __init omap4_pm_init(void)
 {
         int ret;
-        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm, *l4wkup;
-        struct clockdomain *ducati_clkdm, *l3_2_clkdm, *l4_per_clkdm;
+        struct clockdomain *emif_clkdm, *mpuss_clkdm, *l3_1_clkdm;
+        struct clockdomain *ducati_clkdm, *l3_2_clkdm;
 
         if (omap_rev() == OMAP4430_REV_ES1_0) {
                 WARN(1, "Power Management not supported on OMAP4430 ES1.0\n");
@@ -175,27 +171,19 @@ int __init omap4_pm_init(void)
          * MPUSS -> L4_PER/L3_* and DUCATI -> L3_* doesn't work as
          * expected. The hardware recommendation is to enable static
          * dependencies for these to avoid system lock ups or random crashes.
-         * The L4 wakeup depedency is added to workaround the OCP sync hardware
-         * BUG with 32K synctimer which lead to incorrect timer value read
-         * from the 32K counter. The BUG applies for GPTIMER1 and WDT2 which
-         * are part of L4 wakeup clockdomain.
          */
         mpuss_clkdm = clkdm_lookup("mpuss_clkdm");
         emif_clkdm = clkdm_lookup("l3_emif_clkdm");
         l3_1_clkdm = clkdm_lookup("l3_1_clkdm");
         l3_2_clkdm = clkdm_lookup("l3_2_clkdm");
-        l4_per_clkdm = clkdm_lookup("l4_per_clkdm");
-        l4wkup = clkdm_lookup("l4_wkup_clkdm");
         ducati_clkdm = clkdm_lookup("ducati_clkdm");
-        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) || (!l4wkup) ||
-                (!l3_2_clkdm) || (!ducati_clkdm) || (!l4_per_clkdm))
+        if ((!mpuss_clkdm) || (!emif_clkdm) || (!l3_1_clkdm) ||
+                (!l3_2_clkdm) || (!ducati_clkdm))
                 goto err2;
 
         ret = clkdm_add_wkdep(mpuss_clkdm, emif_clkdm);
         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_1_clkdm);
         ret |= clkdm_add_wkdep(mpuss_clkdm, l3_2_clkdm);
-        ret |= clkdm_add_wkdep(mpuss_clkdm, l4_per_clkdm);
-        ret |= clkdm_add_wkdep(mpuss_clkdm, l4wkup);
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_1_clkdm);
         ret |= clkdm_add_wkdep(ducati_clkdm, l3_2_clkdm);
         if (ret) {
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index d00d89c93f1c..ea6ea9aab092 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -602,7 +602,7 @@ void __init omap4_local_timer_init(void)
                 int err;
 
                 if (of_have_populated_dt()) {
-                        twd_local_timer_of_register();
+                        clocksource_of_init();
                         return;
                 }
 
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index d9c7c3bf0d9c..973db98a3c27 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -402,8 +402,9 @@ static void __init orion5x_pci_master_slave_enable(void)
         orion5x_pci_hw_wr_conf(bus_nr, 0, func, reg, 4, val | 0x7);
 }
 
-static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
+static void __init orion5x_setup_pci_wins(void)
 {
+        const struct mbus_dram_target_info *dram = mv_mbus_dram_info();
         u32 win_enable;
         int bus;
         int i;
@@ -420,7 +421,7 @@ static void __init orion5x_setup_pci_wins(struct mbus_dram_target_info *dram)
         bus = orion5x_pci_local_bus_nr();
 
         for (i = 0; i < dram->num_cs; i++) {
-                struct mbus_dram_window *cs = dram->cs + i;
+                const struct mbus_dram_window *cs = dram->cs + i;
                 u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
                 u32 reg;
                 u32 val;
@@ -467,7 +468,7 @@ static int __init pci_setup(struct pci_sys_data *sys)
         /*
          * Point PCI unit MBUS decode windows to DRAM space.
          */
-        orion5x_setup_pci_wins(&orion_mbus_dram_info);
+        orion5x_setup_pci_wins();
 
         /*
          * Master + Slave enable
diff --git a/arch/arm/mach-prima2/platsmp.c b/arch/arm/mach-prima2/platsmp.c
index 4b788310f6a6..c7c92e78f0cf 100644
--- a/arch/arm/mach-prima2/platsmp.c
+++ b/arch/arm/mach-prima2/platsmp.c
@@ -11,7 +11,6 @@
 #include <linux/delay.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
 #include <asm/page.h>
 #include <asm/mach/map.h>
 #include <asm/smp_plat.h>
@@ -49,13 +48,6 @@ void __init sirfsoc_map_scu(void)
 static void __cpuinit sirfsoc_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/mach-s3c24xx/Kconfig b/arch/arm/mach-s3c24xx/Kconfig
index 37f513d1588e..8d5fa6ece014 100644
--- a/arch/arm/mach-s3c24xx/Kconfig
+++ b/arch/arm/mach-s3c24xx/Kconfig
@@ -36,7 +36,6 @@ config CPU_S3C2410
 
 config CPU_S3C2412
         bool "SAMSUNG S3C2412"
-        depends on ARCH_S3C24XX
         select CPU_ARM926T
         select CPU_LLSERIAL_S3C2440
         select S3C2412_DMA if S3C24XX_DMA
@@ -46,7 +45,6 @@ config CPU_S3C2412
 
 config CPU_S3C2416
         bool "SAMSUNG S3C2416/S3C2450"
-        depends on ARCH_S3C24XX
         select CPU_ARM926T
         select CPU_LLSERIAL_S3C2440
         select S3C2416_PM if PM
@@ -81,7 +79,6 @@ config CPU_S3C244X
 
 config CPU_S3C2443
         bool "SAMSUNG S3C2443"
-        depends on ARCH_S3C24XX
         select CPU_ARM920T
         select CPU_LLSERIAL_S3C2440
         select S3C2443_COMMON
@@ -133,7 +130,6 @@ config S3C24XX_SETUP_TS
 
 config S3C24XX_DMA
         bool "S3C2410 DMA support"
-        depends on ARCH_S3C24XX
         select S3C_DMA
         help
           S3C2410 DMA support. This is needed for drivers like sound which
@@ -142,7 +138,7 @@ config S3C24XX_DMA
 
 config S3C2410_DMA_DEBUG
         bool "S3C2410 DMA support debug"
-        depends on ARCH_S3C24XX && S3C2410_DMA
+        depends on S3C2410_DMA
         help
           Enable debugging output for the DMA code. This option sends info
           to the kernel log, at priority KERN_DEBUG.
@@ -233,7 +229,7 @@ if CPU_S3C2410
 
 config S3C2410_CPUFREQ
         bool
-        depends on CPU_FREQ_S3C24XX && CPU_S3C2410
+        depends on CPU_FREQ_S3C24XX
         select S3C2410_CPUFREQ_UTILS
         help
           CPU Frequency scaling support for S3C2410
@@ -320,7 +316,6 @@ config PM_H1940
 
 config MACH_N30
         bool "Acer N30 family"
-        select MACH_N35
         select S3C_DEV_NAND
         select S3C_DEV_USB_HOST
         help
@@ -380,14 +375,13 @@ if CPU_S3C2412
 
 config CPU_S3C2412_ONLY
         bool
-        depends on ARCH_S3C24XX && !CPU_S3C2410 && \
-                   !CPU_S3C2416 && !CPU_S3C2440 && !CPU_S3C2442 && \
-                   !CPU_S3C2443 && CPU_S3C2412
+        depends on !CPU_S3C2410 && !CPU_S3C2416 && !CPU_S3C2440 && \
+                   !CPU_S3C2442 && !CPU_S3C2443
         default y
 
 config S3C2412_CPUFREQ
         bool
-        depends on CPU_FREQ_S3C24XX && CPU_S3C2412
+        depends on CPU_FREQ_S3C24XX
         default y
         select S3C2412_IOTIMING
         help
@@ -642,7 +636,6 @@ comment "S3C2442 Boards"
 config MACH_NEO1973_GTA02
         bool "Openmoko GTA02 / Freerunner phone"
         select I2C
-        select MACH_NEO1973
         select MFD_PCF50633
         select PCF50633_GPIO
         select POWER_SUPPLY
@@ -663,10 +656,7 @@ config MACH_RX1950
         help
            Say Y here if you're using HP iPAQ rx1950
 
-config SMDK2440_CPU2442
-        bool "SMDM2440 with S3C2442 CPU module"
-
-endif   # CPU_S3C2440
+endif   # CPU_S3C2442
 
 if CPU_S3C2443 || CPU_S3C2416
 
diff --git a/arch/arm/mach-s3c24xx/bast-irq.c b/arch/arm/mach-s3c24xx/bast-irq.c
index c0daa9590b4c..cb1b791954de 100644
--- a/arch/arm/mach-s3c24xx/bast-irq.c
+++ b/arch/arm/mach-s3c24xx/bast-irq.c
@@ -34,8 +34,6 @@
 #include <mach/hardware.h>
 #include <mach/regs-irq.h>
 
-#include <plat/irq.h>
-
 #include "bast.h"
 
 #define irqdbf(x...)
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2410.c b/arch/arm/mach-s3c24xx/clock-s3c2410.c
index 641266f3d152..34fffdf6fc1d 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2410.c
@@ -40,7 +40,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2410.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2412.c b/arch/arm/mach-s3c24xx/clock-s3c2412.c
index d10b695a9066..2cc017da88fe 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2412.c
@@ -41,7 +41,6 @@
 #include <mach/regs-clock.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/cpu.h>
 
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2416.c b/arch/arm/mach-s3c24xx/clock-s3c2416.c
index 14a81c2317a4..036056cea57c 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2416.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2416.c
@@ -14,7 +14,6 @@
 #include <linux/init.h>
 #include <linux/clk.h>
 
-#include <plat/s3c2416.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/clock-s3c2443.c b/arch/arm/mach-s3c24xx/clock-s3c2443.c
index bdaba59b42dc..0a53051b0787 100644
--- a/arch/arm/mach-s3c24xx/clock-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/clock-s3c2443.c
@@ -41,7 +41,6 @@
 
 #include <plat/cpu-freq.h>
 
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/clock-clksrc.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/common-smdk.c b/arch/arm/mach-s3c24xx/common-smdk.c
index 3b2cf6db3634..404444dd3840 100644
--- a/arch/arm/mach-s3c24xx/common-smdk.c
+++ b/arch/arm/mach-s3c24xx/common-smdk.c
@@ -41,11 +41,12 @@
 
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/pm.h>
 
+#include "common-smdk.h"
+
 /* LED devices */
 
 static struct s3c24xx_led_platdata smdk_pdata_led4 = {
diff --git a/arch/arm/plat-samsung/include/plat/common-smdk.h b/arch/arm/mach-s3c24xx/common-smdk.h
index ba028f1ed30b..98f733e1cb42 100644
--- a/arch/arm/plat-samsung/include/plat/common-smdk.h
+++ b/arch/arm/mach-s3c24xx/common-smdk.h
@@ -1,5 +1,4 @@
-/* linux/arch/arm/plat-samsung/include/plat/common-smdk.h
- *
+/*
  * Copyright (c) 2006 Simtec Electronics
  *      Ben Dooks <ben@simtec.co.uk>
  *
diff --git a/arch/arm/mach-s3c24xx/common.c b/arch/arm/mach-s3c24xx/common.c
index 92e609440c57..c157103ed8eb 100644
--- a/arch/arm/mach-s3c24xx/common.c
+++ b/arch/arm/mach-s3c24xx/common.c
@@ -47,14 +47,11 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
-#include <plat/s3c2416.h>
-#include <plat/s3c244x.h>
-#include <plat/s3c2443.h>
 #include <plat/cpu-freq.h>
 #include <plat/pll.h>
 
+#include "common.h"
+
 /* table of supported CPUs */
 
 static const char name_s3c2410[]  = "S3C2410";
diff --git a/arch/arm/mach-s3c24xx/common.h b/arch/arm/mach-s3c24xx/common.h
index ed6276fcaa3b..8a2b4137ddb6 100644
--- a/arch/arm/mach-s3c24xx/common.h
+++ b/arch/arm/mach-s3c24xx/common.h
@@ -12,8 +12,94 @@
 #ifndef __ARCH_ARM_MACH_S3C24XX_COMMON_H
 #define __ARCH_ARM_MACH_S3C24XX_COMMON_H __FILE__
 
-void s3c2410_restart(char mode, const char *cmd);
-void s3c244x_restart(char mode, const char *cmd);
+struct s3c2410_uartcfg;
+
+#ifdef CONFIG_CPU_S3C2410
+extern  int s3c2410_init(void);
+extern  int s3c2410a_init(void);
+extern void s3c2410_map_io(void);
+extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2410_init_clocks(int xtal);
+extern void s3c2410_restart(char mode, const char *cmd);
+#else
+#define s3c2410_init_clocks NULL
+#define s3c2410_init_uarts NULL
+#define s3c2410_map_io NULL
+#define s3c2410_init NULL
+#define s3c2410a_init NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2412
+extern  int s3c2412_init(void);
+extern void s3c2412_map_io(void);
+extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2412_init_clocks(int xtal);
+extern  int s3c2412_baseclk_add(void);
+extern void s3c2412_restart(char mode, const char *cmd);
+#else
+#define s3c2412_init_clocks NULL
+#define s3c2412_init_uarts NULL
+#define s3c2412_map_io NULL
+#define s3c2412_init NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2416
+extern  int s3c2416_init(void);
+extern void s3c2416_map_io(void);
+extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2416_init_clocks(int xtal);
+extern  int s3c2416_baseclk_add(void);
+extern void s3c2416_restart(char mode, const char *cmd);
+extern void s3c2416_init_irq(void);
+
+extern struct syscore_ops s3c2416_irq_syscore_ops;
+#else
+#define s3c2416_init_clocks NULL
+#define s3c2416_init_uarts NULL
+#define s3c2416_map_io NULL
+#define s3c2416_init NULL
+#endif
+
+#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
+extern void s3c244x_map_io(void);
+extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c244x_init_clocks(int xtal);
+extern void s3c244x_restart(char mode, const char *cmd);
+#else
+#define s3c244x_init_clocks NULL
+#define s3c244x_init_uarts NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2440
+extern  int s3c2440_init(void);
+extern void s3c2440_map_io(void);
+#else
+#define s3c2440_init NULL
+#define s3c2440_map_io NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2442
+extern  int s3c2442_init(void);
+extern void s3c2442_map_io(void);
+#else
+#define s3c2442_init NULL
+#define s3c2442_map_io NULL
+#endif
+
+#ifdef CONFIG_CPU_S3C2443
+extern  int s3c2443_init(void);
+extern void s3c2443_map_io(void);
+extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
+extern void s3c2443_init_clocks(int xtal);
+extern  int s3c2443_baseclk_add(void);
+extern void s3c2443_restart(char mode, const char *cmd);
+extern void s3c2443_init_irq(void);
+#else
+#define s3c2443_init_clocks NULL
+#define s3c2443_init_uarts NULL
+#define s3c2443_map_io NULL
+#define s3c2443_init NULL
+#endif
 
 extern struct syscore_ops s3c24xx_irq_syscore_ops;
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2410.c b/arch/arm/mach-s3c24xx/dma-s3c2410.c
index 25d085adc93c..a6c94b820954 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2410.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2410.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2412.c b/arch/arm/mach-s3c24xx/dma-s3c2412.c
index d2408ba372cb..c0e8c3f5057e 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2412.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2440.c b/arch/arm/mach-s3c24xx/dma-s3c2440.c
index 0b86e74d104f..1c08eccd9425 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2440.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2440.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/dma-s3c2443.c b/arch/arm/mach-s3c24xx/dma-s3c2443.c
index 05536254a3f8..000e4c69fce9 100644
--- a/arch/arm/mach-s3c24xx/dma-s3c2443.c
+++ b/arch/arm/mach-s3c24xx/dma-s3c2443.c
@@ -28,7 +28,6 @@
 #include <plat/regs-ac97.h>
 #include <plat/regs-dma.h>
 #include <mach/regs-lcd.h>
-#include <mach/regs-sdi.h>
 #include <plat/regs-iis.h>
 #include <plat/regs-spi.h>
 
diff --git a/arch/arm/mach-s3c24xx/include/mach/dma.h b/arch/arm/mach-s3c24xx/include/mach/dma.h
index 6b72d5a4b377..b55da1d8cd8f 100644
--- a/arch/arm/mach-s3c24xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c24xx/include/mach/dma.h
@@ -24,7 +24,6 @@
 */
 
 enum dma_ch {
-        DMACH_DT_PROP = -1,     /* not yet supported, do not use */
         DMACH_XD0 = 0,
         DMACH_XD1,
         DMACH_SDI,
diff --git a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h b/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
deleted file mode 100644
index cbf2d8884e30..000000000000
--- a/arch/arm/mach-s3c24xx/include/mach/regs-sdi.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-sdi.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 MMC/SDIO register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_SDI
-#define __ASM_ARM_REGS_SDI "regs-sdi.h"
-
-#define S3C2410_SDICON                (0x00)
-#define S3C2410_SDIPRE                (0x04)
-#define S3C2410_SDICMDARG             (0x08)
-#define S3C2410_SDICMDCON             (0x0C)
-#define S3C2410_SDICMDSTAT            (0x10)
-#define S3C2410_SDIRSP0               (0x14)
-#define S3C2410_SDIRSP1               (0x18)
-#define S3C2410_SDIRSP2               (0x1C)
-#define S3C2410_SDIRSP3               (0x20)
-#define S3C2410_SDITIMER              (0x24)
-#define S3C2410_SDIBSIZE              (0x28)
-#define S3C2410_SDIDCON               (0x2C)
-#define S3C2410_SDIDCNT               (0x30)
-#define S3C2410_SDIDSTA               (0x34)
-#define S3C2410_SDIFSTA               (0x38)
-
-#define S3C2410_SDIDATA               (0x3C)
-#define S3C2410_SDIIMSK               (0x40)
-
-#define S3C2440_SDIDATA               (0x40)
-#define S3C2440_SDIIMSK               (0x3C)
-
-#define S3C2440_SDICON_SDRESET        (1<<8)
-#define S3C2440_SDICON_MMCCLOCK       (1<<5)
-#define S3C2410_SDICON_BYTEORDER      (1<<4)
-#define S3C2410_SDICON_SDIOIRQ        (1<<3)
-#define S3C2410_SDICON_RWAITEN        (1<<2)
-#define S3C2410_SDICON_FIFORESET      (1<<1)
-#define S3C2410_SDICON_CLOCKTYPE      (1<<0)
-
-#define S3C2410_SDICMDCON_ABORT       (1<<12)
-#define S3C2410_SDICMDCON_WITHDATA    (1<<11)
-#define S3C2410_SDICMDCON_LONGRSP     (1<<10)
-#define S3C2410_SDICMDCON_WAITRSP     (1<<9)
-#define S3C2410_SDICMDCON_CMDSTART    (1<<8)
-#define S3C2410_SDICMDCON_SENDERHOST  (1<<6)
-#define S3C2410_SDICMDCON_INDEX       (0x3f)
-
-#define S3C2410_SDICMDSTAT_CRCFAIL    (1<<12)
-#define S3C2410_SDICMDSTAT_CMDSENT    (1<<11)
-#define S3C2410_SDICMDSTAT_CMDTIMEOUT (1<<10)
-#define S3C2410_SDICMDSTAT_RSPFIN     (1<<9)
-#define S3C2410_SDICMDSTAT_XFERING    (1<<8)
-#define S3C2410_SDICMDSTAT_INDEX      (0xff)
-
-#define S3C2440_SDIDCON_DS_BYTE       (0<<22)
-#define S3C2440_SDIDCON_DS_HALFWORD   (1<<22)
-#define S3C2440_SDIDCON_DS_WORD       (2<<22)
-#define S3C2410_SDIDCON_IRQPERIOD     (1<<21)
-#define S3C2410_SDIDCON_TXAFTERRESP   (1<<20)
-#define S3C2410_SDIDCON_RXAFTERCMD    (1<<19)
-#define S3C2410_SDIDCON_BUSYAFTERCMD  (1<<18)
-#define S3C2410_SDIDCON_BLOCKMODE     (1<<17)
-#define S3C2410_SDIDCON_WIDEBUS       (1<<16)
-#define S3C2410_SDIDCON_DMAEN         (1<<15)
-#define S3C2410_SDIDCON_STOP          (1<<14)
-#define S3C2440_SDIDCON_DATSTART      (1<<14)
-#define S3C2410_SDIDCON_DATMODE       (3<<12)
-#define S3C2410_SDIDCON_BLKNUM        (0x7ff)
-
-/* constants for S3C2410_SDIDCON_DATMODE */
-#define S3C2410_SDIDCON_XFER_READY    (0<<12)
-#define S3C2410_SDIDCON_XFER_CHKSTART (1<<12)
-#define S3C2410_SDIDCON_XFER_RXSTART  (2<<12)
-#define S3C2410_SDIDCON_XFER_TXSTART  (3<<12)
-
-#define S3C2410_SDIDCON_BLKNUM_MASK   (0xFFF)
-#define S3C2410_SDIDCNT_BLKNUM_SHIFT  (12)
-
-#define S3C2410_SDIDSTA_RDYWAITREQ    (1<<10)
-#define S3C2410_SDIDSTA_SDIOIRQDETECT (1<<9)
-#define S3C2410_SDIDSTA_FIFOFAIL      (1<<8)    /* reserved on 2440 */
-#define S3C2410_SDIDSTA_CRCFAIL       (1<<7)
-#define S3C2410_SDIDSTA_RXCRCFAIL     (1<<6)
-#define S3C2410_SDIDSTA_DATATIMEOUT   (1<<5)
-#define S3C2410_SDIDSTA_XFERFINISH    (1<<4)
-#define S3C2410_SDIDSTA_BUSYFINISH    (1<<3)
-#define S3C2410_SDIDSTA_SBITERR       (1<<2)    /* reserved on 2410a/2440 */
-#define S3C2410_SDIDSTA_TXDATAON      (1<<1)
-#define S3C2410_SDIDSTA_RXDATAON      (1<<0)
-
-#define S3C2440_SDIFSTA_FIFORESET      (1<<16)
-#define S3C2440_SDIFSTA_FIFOFAIL       (3<<14)  /* 3 is correct (2 bits) */
-#define S3C2410_SDIFSTA_TFDET          (1<<13)
-#define S3C2410_SDIFSTA_RFDET          (1<<12)
-#define S3C2410_SDIFSTA_TFHALF         (1<<11)
-#define S3C2410_SDIFSTA_TFEMPTY        (1<<10)
-#define S3C2410_SDIFSTA_RFLAST         (1<<9)
-#define S3C2410_SDIFSTA_RFFULL         (1<<8)
-#define S3C2410_SDIFSTA_RFHALF         (1<<7)
-#define S3C2410_SDIFSTA_COUNTMASK      (0x7f)
-
-#define S3C2410_SDIIMSK_RESPONSECRC    (1<<17)
-#define S3C2410_SDIIMSK_CMDSENT        (1<<16)
-#define S3C2410_SDIIMSK_CMDTIMEOUT     (1<<15)
-#define S3C2410_SDIIMSK_RESPONSEND     (1<<14)
-#define S3C2410_SDIIMSK_READWAIT       (1<<13)
-#define S3C2410_SDIIMSK_SDIOIRQ        (1<<12)
-#define S3C2410_SDIIMSK_FIFOFAIL       (1<<11)
-#define S3C2410_SDIIMSK_CRCSTATUS      (1<<10)
-#define S3C2410_SDIIMSK_DATACRC        (1<<9)
-#define S3C2410_SDIIMSK_DATATIMEOUT    (1<<8)
-#define S3C2410_SDIIMSK_DATAFINISH     (1<<7)
-#define S3C2410_SDIIMSK_BUSYFINISH     (1<<6)
-#define S3C2410_SDIIMSK_SBITERR        (1<<5)   /* reserved 2440/2410a */
-#define S3C2410_SDIIMSK_TXFIFOHALF     (1<<4)
-#define S3C2410_SDIIMSK_TXFIFOEMPTY    (1<<3)
-#define S3C2410_SDIIMSK_RXFIFOLAST     (1<<2)
-#define S3C2410_SDIIMSK_RXFIFOFULL     (1<<1)
-#define S3C2410_SDIIMSK_RXFIFOHALF     (1<<0)
-
-#endif /* __ASM_ARM_REGS_SDI */
diff --git a/arch/arm/mach-s3c24xx/irq-pm.c b/arch/arm/mach-s3c24xx/irq-pm.c
index e1199599873e..b91341ef2b2e 100644
--- a/arch/arm/mach-s3c24xx/irq-pm.c
+++ b/arch/arm/mach-s3c24xx/irq-pm.c
@@ -16,10 +16,15 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/syscore_ops.h>
+#include <linux/io.h>
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/irq.h>
+#include <plat/map-base.h>
+#include <plat/map-s3c.h>
+
+#include <mach/regs-irq.h>
+#include <mach/regs-gpio.h>
 
 #include <asm/irq.h>
 
diff --git a/arch/arm/mach-s3c24xx/irq.c b/arch/arm/mach-s3c24xx/irq.c
index d8ba9bee4c7e..b41c2cb7af4a 100644
--- a/arch/arm/mach-s3c24xx/irq.c
+++ b/arch/arm/mach-s3c24xx/irq.c
@@ -25,6 +25,7 @@
 #include <linux/ioport.h>
 #include <linux/device.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 
 #include <asm/mach/irq.h>
 
@@ -34,7 +35,6 @@
 #include <plat/cpu.h>
 #include <plat/regs-irqtype.h>
 #include <plat/pm.h>
-#include <plat/irq.h>
 
 #define S3C_IRQTYPE_NONE        0
 #define S3C_IRQTYPE_EINT        1
@@ -175,8 +175,7 @@ static int s3c_irqext_type_set(void __iomem *gpcon_reg,
         return 0;
 }
 
-/* FIXME: make static when it's out of plat-samsung/irq.h */
-int s3c_irqext_type(struct irq_data *data, unsigned int type)
+static int s3c_irqext_type(struct irq_data *data, unsigned int type)
 {
         void __iomem *extint_reg;
         void __iomem *gpcon_reg;
@@ -224,7 +223,7 @@ static int s3c_irqext0_type(struct irq_data *data, unsigned int type)
                                    extint_offset, type);
 }
 
-struct irq_chip s3c_irq_chip = {
+static struct irq_chip s3c_irq_chip = {
         .name           = "s3c",
         .irq_ack        = s3c_irq_ack,
         .irq_mask       = s3c_irq_mask,
@@ -232,7 +231,7 @@ struct irq_chip s3c_irq_chip = {
         .irq_set_wake   = s3c_irq_wake
 };
 
-struct irq_chip s3c_irq_level_chip = {
+static struct irq_chip s3c_irq_level_chip = {
         .name           = "s3c-level",
         .irq_mask       = s3c_irq_mask,
         .irq_unmask     = s3c_irq_unmask,
diff --git a/arch/arm/mach-s3c24xx/mach-jive.c b/arch/arm/mach-s3c24xx/mach-jive.c
index 54e83c1f780c..ca08d7df07f7 100644
--- a/arch/arm/mach-s3c24xx/mach-jive.c
+++ b/arch/arm/mach-s3c24xx/mach-jive.c
@@ -46,7 +46,6 @@
 #include <linux/mtd/nand_ecc.h>
 #include <linux/mtd/partitions.h>
 
-#include <plat/s3c2412.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
@@ -54,6 +53,7 @@
 #include <plat/pm.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 
+#include "common.h"
 #include "s3c2412-power.h"
 
 static struct map_desc jive_iodesc[] __initdata = {
diff --git a/arch/arm/mach-s3c24xx/mach-n30.c b/arch/arm/mach-s3c24xx/mach-n30.c
index d9d04b240295..8017c0fc1729 100644
--- a/arch/arm/mach-s3c24xx/mach-n30.c
+++ b/arch/arm/mach-s3c24xx/mach-n30.c
@@ -48,7 +48,6 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <linux/platform_data/mmc-s3cmci.h>
-#include <plat/s3c2410.h>
 #include <linux/platform_data/usb-s3c2410_udc.h>
 
 #include "common.h"
diff --git a/arch/arm/mach-s3c24xx/mach-nexcoder.c b/arch/arm/mach-s3c24xx/mach-nexcoder.c
index a454e2461860..144b9f80c4a5 100644
--- a/arch/arm/mach-s3c24xx/mach-nexcoder.c
+++ b/arch/arm/mach-s3c24xx/mach-nexcoder.c
@@ -41,8 +41,6 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 
 #include <plat/gpio-cfg.h>
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c24xx/mach-otom.c b/arch/arm/mach-s3c24xx/mach-otom.c
index 40a47d6c6a85..deb0ace585b0 100644
--- a/arch/arm/mach-s3c24xx/mach-otom.c
+++ b/arch/arm/mach-s3c24xx/mach-otom.c
@@ -33,7 +33,6 @@
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/regs-serial.h>
-#include <plat/s3c2410.h>
 
 #include "common.h"
 #include "otom.h"
diff --git a/arch/arm/mach-s3c24xx/mach-qt2410.c b/arch/arm/mach-s3c24xx/mach-qt2410.c
index 56175f0941b1..84c541602661 100644
--- a/arch/arm/mach-s3c24xx/mach-qt2410.c
+++ b/arch/arm/mach-s3c24xx/mach-qt2410.c
@@ -55,13 +55,13 @@
 #include <linux/platform_data/usb-s3c2410_udc.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/common-smdk.h>
 #include <plat/gpio-cfg.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/pm.h>
 
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc qt2410_iodesc[] __initdata = {
         { 0xe0000000, __phys_to_pfn(S3C2410_CS3+0x01000000), SZ_1M, MT_DEVICE }
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2410.c b/arch/arm/mach-s3c24xx/mach-smdk2410.c
index e184bfa9613a..cd0b1635c47e 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2410.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2410.c
@@ -52,9 +52,8 @@
 #include <plat/devs.h>
 #include <plat/cpu.h>
 
-#include <plat/common-smdk.h>
-
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2410_iodesc[] __initdata = {
   /* nothing here yet */
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2413.c b/arch/arm/mach-s3c24xx/mach-smdk2413.c
index 86d7847c9d45..79485907950f 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2413.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2413.c
@@ -41,13 +41,12 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <mach/fb.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2413_iodesc[] __initdata = {
 };
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2416.c b/arch/arm/mach-s3c24xx/mach-smdk2416.c
index ebb2e61f3d07..037a5da343bd 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2416.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2416.c
@@ -42,7 +42,6 @@
 #include <linux/platform_data/leds-s3c24xx.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2416.h>
 #include <plat/gpio-cfg.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
@@ -54,7 +53,8 @@
 
 #include <plat/fb.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2416_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2440.c b/arch/arm/mach-s3c24xx/mach-smdk2440.c
index 08cc38c8a4ae..29d31314e23c 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2440.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2440.c
@@ -38,15 +38,12 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 
-#include <plat/common-smdk.h>
-
 #include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2440_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
diff --git a/arch/arm/mach-s3c24xx/mach-smdk2443.c b/arch/arm/mach-s3c24xx/mach-smdk2443.c
index fc65d74d3c73..b3be4c4dc7bc 100644
--- a/arch/arm/mach-s3c24xx/mach-smdk2443.c
+++ b/arch/arm/mach-s3c24xx/mach-smdk2443.c
@@ -38,13 +38,12 @@
 #include <mach/fb.h>
 #include <linux/platform_data/i2c-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2443.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 
-#include <plat/common-smdk.h>
+#include "common.h"
+#include "common-smdk.h"
 
 static struct map_desc smdk2443_iodesc[] __initdata = {
         /* ISA IO Space map (memory space selected by A24) */
diff --git a/arch/arm/mach-s3c24xx/mach-vstms.c b/arch/arm/mach-s3c24xx/mach-vstms.c
index 3e2bfddc9df1..239129c2d8bc 100644
--- a/arch/arm/mach-s3c24xx/mach-vstms.c
+++ b/arch/arm/mach-s3c24xx/mach-vstms.c
@@ -41,12 +41,11 @@
 #include <linux/platform_data/i2c-s3c2410.h>
 #include <linux/platform_data/mtd-nand-s3c2410.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c2412.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 
+#include "common.h"
 
 static struct map_desc vstms_iodesc[] __initdata = {
 };
diff --git a/arch/arm/mach-s3c24xx/pm-s3c2412.c b/arch/arm/mach-s3c24xx/pm-s3c2412.c
index 668a78a8b195..4c4bc1c83b77 100644
--- a/arch/arm/mach-s3c24xx/pm-s3c2412.c
+++ b/arch/arm/mach-s3c24xx/pm-s3c2412.c
@@ -29,7 +29,6 @@
 
 #include <plat/cpu.h>
 #include <plat/pm.h>
-#include <plat/s3c2412.h>
 
 #include "regs-dsc.h"
 #include "s3c2412-power.h"
diff --git a/arch/arm/mach-s3c24xx/regs-dsc.h b/arch/arm/mach-s3c24xx/regs-dsc.h
index 98fd4a05587c..61b3d1387d76 100644
--- a/arch/arm/mach-s3c24xx/regs-dsc.h
+++ b/arch/arm/mach-s3c24xx/regs-dsc.h
@@ -1,5 +1,4 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-dsc.h
- *
+/*
  * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
  *                    http://www.simtec.co.uk/products/SWLINUX/
  *
@@ -12,209 +11,15 @@
 
 
 #ifndef __ASM_ARCH_REGS_DSC_H
-#define __ASM_ARCH_REGS_DSC_H "2440-dsc"
+#define __ASM_ARCH_REGS_DSC_H __FILE__
 
-#if defined(CONFIG_CPU_S3C2412)
+/* S3C2412 */
 #define S3C2412_DSC0       S3C2410_GPIOREG(0xdc)
 #define S3C2412_DSC1       S3C2410_GPIOREG(0xe0)
-#endif
-
-#if defined(CONFIG_CPU_S3C2416)
-#define S3C2416_DSC0       S3C2410_GPIOREG(0xc0)
-#define S3C2416_DSC1       S3C2410_GPIOREG(0xc4)
-#define S3C2416_DSC2       S3C2410_GPIOREG(0xc8)
-#define S3C2416_DSC3       S3C2410_GPIOREG(0x110)
-
-#define S3C2416_SELECT_DSC0     (0 << 30)
-#define S3C2416_SELECT_DSC1     (1 << 30)
-#define S3C2416_SELECT_DSC2     (2 << 30)
-#define S3C2416_SELECT_DSC3     (3 << 30)
-
-#define S3C2416_DSC_GETSHIFT(x) (x & 30)
-
-#define S3C2416_DSC0_CF         (S3C2416_SELECT_DSC0 | 28)
-#define S3C2416_DSC0_CF_5mA     (0 << 28)
-#define S3C2416_DSC0_CF_10mA    (1 << 28)
-#define S3C2416_DSC0_CF_15mA    (2 << 28)
-#define S3C2416_DSC0_CF_21mA    (3 << 28)
-#define S3C2416_DSC0_CF_MASK    (3 << 28)
-
-#define S3C2416_DSC0_nRBE       (S3C2416_SELECT_DSC0 | 26)
-#define S3C2416_DSC0_nRBE_5mA   (0 << 26)
-#define S3C2416_DSC0_nRBE_10mA  (1 << 26)
-#define S3C2416_DSC0_nRBE_15mA  (2 << 26)
-#define S3C2416_DSC0_nRBE_21mA  (3 << 26)
-#define S3C2416_DSC0_nRBE_MASK  (3 << 26)
-
-#define S3C2416_DSC0_nROE       (S3C2416_SELECT_DSC0 | 24)
-#define S3C2416_DSC0_nROE_5mA   (0 << 24)
-#define S3C2416_DSC0_nROE_10mA  (1 << 24)
-#define S3C2416_DSC0_nROE_15mA  (2 << 24)
-#define S3C2416_DSC0_nROE_21mA  (3 << 24)
-#define S3C2416_DSC0_nROE_MASK  (3 << 24)
-
-#endif
-
-#if defined(CONFIG_CPU_S3C244X)
 
+/* S3C2440 */
 #define S3C2440_DSC0       S3C2410_GPIOREG(0xc4)
 #define S3C2440_DSC1       S3C2410_GPIOREG(0xc8)
 
-#define S3C2440_SELECT_DSC0 (0)
-#define S3C2440_SELECT_DSC1 (1<<31)
-
-#define S3C2440_DSC_GETSHIFT(x) ((x) & 31)
-
-#define S3C2440_DSC0_DISABLE    (1<<31)
-
-#define S3C2440_DSC0_ADDR       (S3C2440_SELECT_DSC0 | 8)
-#define S3C2440_DSC0_ADDR_12mA  (0<<8)
-#define S3C2440_DSC0_ADDR_10mA  (1<<8)
-#define S3C2440_DSC0_ADDR_8mA   (2<<8)
-#define S3C2440_DSC0_ADDR_6mA   (3<<8)
-#define S3C2440_DSC0_ADDR_MASK  (3<<8)
-
-/* D24..D31 */
-#define S3C2440_DSC0_DATA3      (S3C2440_SELECT_DSC0 | 6)
-#define S3C2440_DSC0_DATA3_12mA (0<<6)
-#define S3C2440_DSC0_DATA3_10mA (1<<6)
-#define S3C2440_DSC0_DATA3_8mA  (2<<6)
-#define S3C2440_DSC0_DATA3_6mA  (3<<6)
-#define S3C2440_DSC0_DATA3_MASK (3<<6)
-
-/* D16..D23 */
-#define S3C2440_DSC0_DATA2      (S3C2440_SELECT_DSC0 | 4)
-#define S3C2440_DSC0_DATA2_12mA (0<<4)
-#define S3C2440_DSC0_DATA2_10mA (1<<4)
-#define S3C2440_DSC0_DATA2_8mA  (2<<4)
-#define S3C2440_DSC0_DATA2_6mA  (3<<4)
-#define S3C2440_DSC0_DATA2_MASK (3<<4)
-
-/* D8..D15 */
-#define S3C2440_DSC0_DATA1      (S3C2440_SELECT_DSC0 | 2)
-#define S3C2440_DSC0_DATA1_12mA (0<<2)
-#define S3C2440_DSC0_DATA1_10mA (1<<2)
-#define S3C2440_DSC0_DATA1_8mA  (2<<2)
-#define S3C2440_DSC0_DATA1_6mA  (3<<2)
-#define S3C2440_DSC0_DATA1_MASK (3<<2)
-
-/* D0..D7 */
-#define S3C2440_DSC0_DATA0      (S3C2440_SELECT_DSC0 | 0)
-#define S3C2440_DSC0_DATA0_12mA (0<<0)
-#define S3C2440_DSC0_DATA0_10mA (1<<0)
-#define S3C2440_DSC0_DATA0_8mA  (2<<0)
-#define S3C2440_DSC0_DATA0_6mA  (3<<0)
-#define S3C2440_DSC0_DATA0_MASK (3<<0)
-
-#define S3C2440_DSC1_SCK1       (S3C2440_SELECT_DSC1 | 28)
-#define S3C2440_DSC1_SCK1_12mA  (0<<28)
-#define S3C2440_DSC1_SCK1_10mA  (1<<28)
-#define S3C2440_DSC1_SCK1_8mA   (2<<28)
-#define S3C2440_DSC1_SCK1_6mA   (3<<28)
-#define S3C2440_DSC1_SCK1_MASK  (3<<28)
-
-#define S3C2440_DSC1_SCK0       (S3C2440_SELECT_DSC1 | 26)
-#define S3C2440_DSC1_SCK0_12mA  (0<<26)
-#define S3C2440_DSC1_SCK0_10mA  (1<<26)
-#define S3C2440_DSC1_SCK0_8mA   (2<<26)
-#define S3C2440_DSC1_SCK0_6mA   (3<<26)
-#define S3C2440_DSC1_SCK0_MASK  (3<<26)
-
-#define S3C2440_DSC1_SCKE       (S3C2440_SELECT_DSC1 | 24)
-#define S3C2440_DSC1_SCKE_10mA  (0<<24)
-#define S3C2440_DSC1_SCKE_8mA   (1<<24)
-#define S3C2440_DSC1_SCKE_6mA   (2<<24)
-#define S3C2440_DSC1_SCKE_4mA   (3<<24)
-#define S3C2440_DSC1_SCKE_MASK  (3<<24)
-
-/* SDRAM nRAS/nCAS */
-#define S3C2440_DSC1_SDR        (S3C2440_SELECT_DSC1 | 22)
-#define S3C2440_DSC1_SDR_10mA   (0<<22)
-#define S3C2440_DSC1_SDR_8mA    (1<<22)
-#define S3C2440_DSC1_SDR_6mA    (2<<22)
-#define S3C2440_DSC1_SDR_4mA    (3<<22)
-#define S3C2440_DSC1_SDR_MASK   (3<<22)
-
-/* NAND Flash Controller */
-#define S3C2440_DSC1_NFC        (S3C2440_SELECT_DSC1 | 20)
-#define S3C2440_DSC1_NFC_10mA   (0<<20)
-#define S3C2440_DSC1_NFC_8mA    (1<<20)
-#define S3C2440_DSC1_NFC_6mA    (2<<20)
-#define S3C2440_DSC1_NFC_4mA    (3<<20)
-#define S3C2440_DSC1_NFC_MASK   (3<<20)
-
-/* nBE[0..3] */
-#define S3C2440_DSC1_nBE        (S3C2440_SELECT_DSC1 | 18)
-#define S3C2440_DSC1_nBE_10mA   (0<<18)
-#define S3C2440_DSC1_nBE_8mA    (1<<18)
-#define S3C2440_DSC1_nBE_6mA    (2<<18)
-#define S3C2440_DSC1_nBE_4mA    (3<<18)
-#define S3C2440_DSC1_nBE_MASK   (3<<18)
-
-#define S3C2440_DSC1_WOE        (S3C2440_SELECT_DSC1 | 16)
-#define S3C2440_DSC1_WOE_10mA   (0<<16)
-#define S3C2440_DSC1_WOE_8mA    (1<<16)
-#define S3C2440_DSC1_WOE_6mA    (2<<16)
-#define S3C2440_DSC1_WOE_4mA    (3<<16)
-#define S3C2440_DSC1_WOE_MASK   (3<<16)
-
-#define S3C2440_DSC1_CS7        (S3C2440_SELECT_DSC1 | 14)
-#define S3C2440_DSC1_CS7_10mA   (0<<14)
-#define S3C2440_DSC1_CS7_8mA    (1<<14)
-#define S3C2440_DSC1_CS7_6mA    (2<<14)
-#define S3C2440_DSC1_CS7_4mA    (3<<14)
-#define S3C2440_DSC1_CS7_MASK   (3<<14)
-
-#define S3C2440_DSC1_CS6        (S3C2440_SELECT_DSC1 | 12)
-#define S3C2440_DSC1_CS6_10mA   (0<<12)
-#define S3C2440_DSC1_CS6_8mA    (1<<12)
-#define S3C2440_DSC1_CS6_6mA    (2<<12)
-#define S3C2440_DSC1_CS6_4mA    (3<<12)
-#define S3C2440_DSC1_CS6_MASK   (3<<12)
-
-#define S3C2440_DSC1_CS5        (S3C2440_SELECT_DSC1 | 10)
-#define S3C2440_DSC1_CS5_10mA   (0<<10)
-#define S3C2440_DSC1_CS5_8mA    (1<<10)
-#define S3C2440_DSC1_CS5_6mA    (2<<10)
-#define S3C2440_DSC1_CS5_4mA    (3<<10)
-#define S3C2440_DSC1_CS5_MASK   (3<<10)
-
-#define S3C2440_DSC1_CS4        (S3C2440_SELECT_DSC1 | 8)
-#define S3C2440_DSC1_CS4_10mA   (0<<8)
-#define S3C2440_DSC1_CS4_8mA    (1<<8)
-#define S3C2440_DSC1_CS4_6mA    (2<<8)
-#define S3C2440_DSC1_CS4_4mA    (3<<8)
-#define S3C2440_DSC1_CS4_MASK   (3<<8)
-
-#define S3C2440_DSC1_CS3        (S3C2440_SELECT_DSC1 | 6)
-#define S3C2440_DSC1_CS3_10mA   (0<<6)
-#define S3C2440_DSC1_CS3_8mA    (1<<6)
-#define S3C2440_DSC1_CS3_6mA    (2<<6)
-#define S3C2440_DSC1_CS3_4mA    (3<<6)
-#define S3C2440_DSC1_CS3_MASK   (3<<6)
-
-#define S3C2440_DSC1_CS2        (S3C2440_SELECT_DSC1 | 4)
-#define S3C2440_DSC1_CS2_10mA   (0<<4)
-#define S3C2440_DSC1_CS2_8mA    (1<<4)
-#define S3C2440_DSC1_CS2_6mA    (2<<4)
-#define S3C2440_DSC1_CS2_4mA    (3<<4)
-#define S3C2440_DSC1_CS2_MASK   (3<<4)
-
-#define S3C2440_DSC1_CS1        (S3C2440_SELECT_DSC1 | 2)
-#define S3C2440_DSC1_CS1_10mA   (0<<2)
-#define S3C2440_DSC1_CS1_8mA    (1<<2)
-#define S3C2440_DSC1_CS1_6mA    (2<<2)
-#define S3C2440_DSC1_CS1_4mA    (3<<2)
-#define S3C2440_DSC1_CS1_MASK   (3<<2)
-
-#define S3C2440_DSC1_CS0        (S3C2440_SELECT_DSC1 | 0)
-#define S3C2440_DSC1_CS0_10mA   (0<<0)
-#define S3C2440_DSC1_CS0_8mA    (1<<0)
-#define S3C2440_DSC1_CS0_6mA    (2<<0)
-#define S3C2440_DSC1_CS0_4mA    (3<<0)
-#define S3C2440_DSC1_CS0_MASK   (3<<0)
-
-#endif /* CONFIG_CPU_S3C2440 */
-
 #endif  /* __ASM_ARCH_REGS_DSC_H */
 
diff --git a/arch/arm/mach-s3c24xx/s3c2410.c b/arch/arm/mach-s3c24xx/s3c2410.c
index 9ebef95da721..d850ea5adac2 100644
--- a/arch/arm/mach-s3c24xx/s3c2410.c
+++ b/arch/arm/mach-s3c24xx/s3c2410.c
@@ -37,7 +37,6 @@
 #include <mach/regs-clock.h>
 #include <plat/regs-serial.h>
 
-#include <plat/s3c2410.h>
 #include <plat/cpu.h>
 #include <plat/devs.h>
 #include <plat/clock.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2412.c b/arch/arm/mach-s3c24xx/s3c2412.c
index 0d592159a5c3..0f864d4c97de 100644
--- a/arch/arm/mach-s3c24xx/s3c2412.c
+++ b/arch/arm/mach-s3c24xx/s3c2412.c
@@ -44,7 +44,6 @@
 #include <plat/pm.h>
 #include <plat/regs-serial.h>
 #include <plat/regs-spi.h>
-#include <plat/s3c2412.h>
 
 #include "common.h"
 #include "regs-dsc.h"
diff --git a/arch/arm/mach-s3c24xx/s3c2416.c b/arch/arm/mach-s3c24xx/s3c2416.c
index e30476db0295..b9c5d382dafb 100644
--- a/arch/arm/mach-s3c24xx/s3c2416.c
+++ b/arch/arm/mach-s3c24xx/s3c2416.c
@@ -50,7 +50,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
-#include <plat/s3c2416.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/sdhci.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2440.c b/arch/arm/mach-s3c24xx/s3c2440.c
index 559e394e8989..5f9d6569475d 100644
--- a/arch/arm/mach-s3c24xx/s3c2440.c
+++ b/arch/arm/mach-s3c24xx/s3c2440.c
@@ -33,7 +33,6 @@
 
 #include <plat/devs.h>
 #include <plat/cpu.h>
-#include <plat/s3c244x.h>
 #include <plat/pm.h>
 
 #include <plat/gpio-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2442.c b/arch/arm/mach-s3c24xx/s3c2442.c
index f732826c2359..6819961f6b19 100644
--- a/arch/arm/mach-s3c24xx/s3c2442.c
+++ b/arch/arm/mach-s3c24xx/s3c2442.c
@@ -44,7 +44,6 @@
 
 #include <plat/clock.h>
 #include <plat/cpu.h>
-#include <plat/s3c244x.h>
 #include <plat/pm.h>
 
 #include <plat/gpio-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c2443.c b/arch/arm/mach-s3c24xx/s3c2443.c
index 165b6a6b3daa..8328cd65bf3d 100644
--- a/arch/arm/mach-s3c24xx/s3c2443.c
+++ b/arch/arm/mach-s3c24xx/s3c2443.c
@@ -36,7 +36,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 #include <plat/gpio-cfg-helpers.h>
-#include <plat/s3c2443.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
 #include <plat/fb-core.h>
diff --git a/arch/arm/mach-s3c24xx/s3c244x.c b/arch/arm/mach-s3c24xx/s3c244x.c
index ad2671baa910..2a35edb67354 100644
--- a/arch/arm/mach-s3c24xx/s3c244x.c
+++ b/arch/arm/mach-s3c24xx/s3c244x.c
@@ -37,8 +37,6 @@
 #include <plat/regs-serial.h>
 #include <mach/regs-gpio.h>
 
-#include <plat/s3c2410.h>
-#include <plat/s3c244x.h>
 #include <plat/clock.h>
 #include <plat/devs.h>
 #include <plat/cpu.h>
diff --git a/arch/arm/mach-s3c64xx/Makefile b/arch/arm/mach-s3c64xx/Makefile
index f9ce1dc28ce4..31d0c9101272 100644
--- a/arch/arm/mach-s3c64xx/Makefile
+++ b/arch/arm/mach-s3c64xx/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_S3C64XX_DMA)	+= dma.o
 
 obj-y                           += dev-uart.o
 obj-y                           += dev-audio.o
-obj-$(CONFIG_S3C64XX_DEV_SPI)   += dev-spi.o
 
 # Device setup
 
diff --git a/arch/arm/mach-s3c64xx/include/mach/dma.h b/arch/arm/mach-s3c64xx/include/mach/dma.h
index 57b1ff4b2d7c..fe1a98cf0e4c 100644
--- a/arch/arm/mach-s3c64xx/include/mach/dma.h
+++ b/arch/arm/mach-s3c64xx/include/mach/dma.h
@@ -21,7 +21,6 @@
  */
 enum dma_ch {
         /* DMA0/SDMA0 */
-        DMACH_DT_PROP = -1, /* not yet supported, do not use */
         DMACH_UART0 = 0,
         DMACH_UART0_SRC2,
         DMACH_UART1,
diff --git a/arch/arm/mach-s5pc100/common.h b/arch/arm/mach-s5pc100/common.h
index 9fbd3ae2b401..c41f912e9e1f 100644
--- a/arch/arm/mach-s5pc100/common.h
+++ b/arch/arm/mach-s5pc100/common.h
@@ -20,18 +20,9 @@ void s5pc100_setup_clocks(void);
 
 void s5pc100_restart(char mode, const char *cmd);
 
-#ifdef CONFIG_CPU_S5PC100
-
 extern  int s5pc100_init(void);
 extern void s5pc100_map_io(void);
 extern void s5pc100_init_clocks(int xtal);
 extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 
-#else
-#define s5pc100_init_clocks NULL
-#define s5pc100_init_uarts NULL
-#define s5pc100_map_io NULL
-#define s5pc100_init NULL
-#endif
-
 #endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */
diff --git a/arch/arm/mach-s5pv210/common.h b/arch/arm/mach-s5pv210/common.h
index 6ed2af5c7518..0a1cc0aef720 100644
--- a/arch/arm/mach-s5pv210/common.h
+++ b/arch/arm/mach-s5pv210/common.h
@@ -20,18 +20,9 @@ void s5pv210_setup_clocks(void);
 
 void s5pv210_restart(char mode, const char *cmd);
 
-#ifdef CONFIG_CPU_S5PV210
-
 extern  int s5pv210_init(void);
 extern void s5pv210_map_io(void);
 extern void s5pv210_init_clocks(int xtal);
 extern void s5pv210_init_uarts(struct s3c2410_uartcfg *cfg, int no);
 
-#else
-#define s5pv210_init_clocks NULL
-#define s5pv210_init_uarts NULL
-#define s5pv210_map_io NULL
-#define s5pv210_init NULL
-#endif
-
 #endif /* __ARCH_ARM_MACH_S5PV210_COMMON_H */
diff --git a/arch/arm/mach-shmobile/smp-emev2.c b/arch/arm/mach-shmobile/smp-emev2.c
index 953eb1f9388d..384e27dd3601 100644
--- a/arch/arm/mach-shmobile/smp-emev2.c
+++ b/arch/arm/mach-shmobile/smp-emev2.c
@@ -23,7 +23,6 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/emev2.h>
 #include <asm/smp_plat.h>
@@ -85,11 +84,6 @@ static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
 }
 
 
-static void __cpuinit emev2_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         cpu = cpu_logical_map(cpu);
@@ -124,7 +118,6 @@ static void __init emev2_smp_init_cpus(void)
 struct smp_operations emev2_smp_ops __initdata = {
         .smp_init_cpus          = emev2_smp_init_cpus,
         .smp_prepare_cpus       = emev2_smp_prepare_cpus,
-        .smp_secondary_init     = emev2_secondary_init,
         .smp_boot_secondary     = emev2_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = emev2_cpu_kill,
diff --git a/arch/arm/mach-shmobile/smp-r8a7779.c b/arch/arm/mach-shmobile/smp-r8a7779.c
index 3a4acf23edcf..994906560edd 100644
--- a/arch/arm/mach-shmobile/smp-r8a7779.c
+++ b/arch/arm/mach-shmobile/smp-r8a7779.c
@@ -23,7 +23,6 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <mach/r8a7779.h>
 #include <asm/smp_plat.h>
@@ -132,11 +131,6 @@ static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
 }
 
 
-static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         struct r8a7779_pm_ch *ch = NULL;
@@ -186,7 +180,6 @@ static void __init r8a7779_smp_init_cpus(void)
 struct smp_operations r8a7779_smp_ops  __initdata = {
         .smp_init_cpus          = r8a7779_smp_init_cpus,
         .smp_prepare_cpus       = r8a7779_smp_prepare_cpus,
-        .smp_secondary_init     = r8a7779_secondary_init,
         .smp_boot_secondary     = r8a7779_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = r8a7779_cpu_kill,
diff --git a/arch/arm/mach-shmobile/smp-sh73a0.c b/arch/arm/mach-shmobile/smp-sh73a0.c
index acb46a94ccdf..d0f9aca22477 100644
--- a/arch/arm/mach-shmobile/smp-sh73a0.c
+++ b/arch/arm/mach-shmobile/smp-sh73a0.c
@@ -23,7 +23,6 @@
 #include <linux/spinlock.h>
 #include <linux/io.h>
 #include <linux/delay.h>
-#include <linux/irqchip/arm-gic.h>
 #include <mach/common.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -59,11 +58,6 @@ static unsigned int __init sh73a0_get_core_count(void)
         return scu_get_core_count(scu_base);
 }
 
-static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         cpu = cpu_logical_map(cpu);
@@ -138,7 +132,6 @@ static void sh73a0_cpu_die(unsigned int cpu)
 struct smp_operations sh73a0_smp_ops __initdata = {
         .smp_init_cpus          = sh73a0_smp_init_cpus,
         .smp_prepare_cpus       = sh73a0_smp_prepare_cpus,
-        .smp_secondary_init     = sh73a0_secondary_init,
         .smp_boot_secondary     = sh73a0_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_kill               = sh73a0_cpu_kill,
diff --git a/arch/arm/mach-socfpga/platsmp.c b/arch/arm/mach-socfpga/platsmp.c
index 84c60fa8daa0..ca14d1d5ac7f 100644
--- a/arch/arm/mach-socfpga/platsmp.c
+++ b/arch/arm/mach-socfpga/platsmp.c
@@ -22,7 +22,6 @@
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
@@ -33,16 +32,6 @@
 extern void __iomem *sys_manager_base_addr;
 extern void __iomem *rst_manager_base_addr;
 
-static void __cpuinit socfpga_secondary_init(unsigned int cpu)
-{
-        /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-}
-
 static int __cpuinit socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
         int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
@@ -109,7 +98,6 @@ static void socfpga_cpu_die(unsigned int cpu)
 struct smp_operations socfpga_smp_ops __initdata = {
         .smp_init_cpus          = socfpga_smp_init_cpus,
         .smp_prepare_cpus       = socfpga_smp_prepare_cpus,
-        .smp_secondary_init     = socfpga_secondary_init,
         .smp_boot_secondary     = socfpga_boot_secondary,
 #ifdef CONFIG_HOTPLUG_CPU
         .cpu_die                = socfpga_cpu_die,
diff --git a/arch/arm/mach-spear13xx/platsmp.c b/arch/arm/mach-spear13xx/platsmp.c
index af4ade61cd95..551c69c9a228 100644
--- a/arch/arm/mach-spear13xx/platsmp.c
+++ b/arch/arm/mach-spear13xx/platsmp.c
@@ -15,7 +15,6 @@
 #include <linux/jiffies.h>
 #include <linux/io.h>
 #include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
 #include <asm/cacheflush.h>
 #include <asm/smp_scu.h>
 #include <mach/spear.h>
@@ -28,13 +27,6 @@ static void __iomem *scu_base = IOMEM(VA_SCU_BASE);
 static void __cpuinit spear13xx_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/mach-spear13xx/spear13xx.c b/arch/arm/mach-spear13xx/spear13xx.c
index c7d2b4a8d8cc..25a10191b021 100644
--- a/arch/arm/mach-spear13xx/spear13xx.c
+++ b/arch/arm/mach-spear13xx/spear13xx.c
@@ -15,12 +15,12 @@
 
 #include <linux/amba/pl022.h>
 #include <linux/clk.h>
+#include <linux/clocksource.h>
 #include <linux/dw_dmac.h>
 #include <linux/err.h>
 #include <linux/of.h>
 #include <asm/hardware/cache-l2x0.h>
 #include <asm/mach/map.h>
-#include <asm/smp_twd.h>
 #include <mach/dma.h>
 #include <mach/generic.h>
 #include <mach/spear.h>
@@ -179,5 +179,5 @@ void __init spear13xx_timer_init(void)
         clk_put(pclk);
 
         spear_setup_of_timer();
-        twd_local_timer_of_register();
+        clocksource_of_init();
 }
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 8709a39bd34c..d259c782d742 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -1,10 +1,11 @@
 config ARCH_SUNXI
         bool "Allwinner A1X SOCs" if ARCH_MULTI_V7
         select CLKSRC_MMIO
+        select CLKSRC_OF
         select COMMON_CLK
         select GENERIC_CLOCKEVENTS
         select GENERIC_IRQ_CHIP
         select PINCTRL
         select SPARSE_IRQ
-        select SUNXI_TIMER
-        select PINCTRL_SUNXI
\ No newline at end of file
+        select SUN4I_TIMER
+        select PINCTRL_SUNXI
diff --git a/arch/arm/mach-sunxi/sunxi.c b/arch/arm/mach-sunxi/sunxi.c
index 23afb732cb40..706ce35396b8 100644
--- a/arch/arm/mach-sunxi/sunxi.c
+++ b/arch/arm/mach-sunxi/sunxi.c
@@ -10,63 +10,77 @@
  * warranty of any kind, whether express or implied.
  */
 
+#include <linux/clocksource.h>
 #include <linux/delay.h>
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/irqchip.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
 #include <linux/io.h>
-#include <linux/sunxi_timer.h>
 
-#include <linux/irqchip/sunxi.h>
+#include <linux/clk/sunxi.h>
 
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
+#include <asm/system_misc.h>
 
 #include "sunxi.h"
 
-#define WATCHDOG_CTRL_REG       0x00
-#define WATCHDOG_CTRL_RESTART           (1 << 0)
-#define WATCHDOG_MODE_REG       0x04
-#define WATCHDOG_MODE_ENABLE            (1 << 0)
-#define WATCHDOG_MODE_RESET_ENABLE      (1 << 1)
+#define SUN4I_WATCHDOG_CTRL_REG         0x00
+#define SUN4I_WATCHDOG_CTRL_RESTART             (1 << 0)
+#define SUN4I_WATCHDOG_MODE_REG         0x04
+#define SUN4I_WATCHDOG_MODE_ENABLE              (1 << 0)
+#define SUN4I_WATCHDOG_MODE_RESET_ENABLE        (1 << 1)
 
 static void __iomem *wdt_base;
 
-static void sunxi_setup_restart(void)
-{
-        struct device_node *np = of_find_compatible_node(NULL, NULL,
-                                                "allwinner,sunxi-wdt");
-        if (WARN(!np, "unable to setup watchdog restart"))
-                return;
-
-        wdt_base = of_iomap(np, 0);
-        WARN(!wdt_base, "failed to map watchdog base address");
-}
-
-static void sunxi_restart(char mode, const char *cmd)
+static void sun4i_restart(char mode, const char *cmd)
 {
         if (!wdt_base)
                 return;
 
         /* Enable timer and set reset bit in the watchdog */
-        writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
-                wdt_base + WATCHDOG_MODE_REG);
+        writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
+               wdt_base + SUN4I_WATCHDOG_MODE_REG);
 
         /*
          * Restart the watchdog. The default (and lowest) interval
          * value for the watchdog is 0.5s.
          */
-        writel(WATCHDOG_CTRL_RESTART, wdt_base + WATCHDOG_CTRL_REG);
+        writel(SUN4I_WATCHDOG_CTRL_RESTART, wdt_base + SUN4I_WATCHDOG_CTRL_REG);
 
         while (1) {
                 mdelay(5);
-                writel(WATCHDOG_MODE_ENABLE | WATCHDOG_MODE_RESET_ENABLE,
-                        wdt_base + WATCHDOG_MODE_REG);
+                writel(SUN4I_WATCHDOG_MODE_ENABLE | SUN4I_WATCHDOG_MODE_RESET_ENABLE,
+                       wdt_base + SUN4I_WATCHDOG_MODE_REG);
         }
 }
 
+static struct of_device_id sunxi_restart_ids[] = {
+        { .compatible = "allwinner,sun4i-wdt", .data = sun4i_restart },
+        { /*sentinel*/ }
+};
+
+static void sunxi_setup_restart(void)
+{
+        const struct of_device_id *of_id;
+        struct device_node *np;
+
+        np = of_find_matching_node(NULL, sunxi_restart_ids);
+        if (WARN(!np, "unable to setup watchdog restart"))
+                return;
+
+        wdt_base = of_iomap(np, 0);
+        WARN(!wdt_base, "failed to map watchdog base address");
+
+        of_id = of_match_node(sunxi_restart_ids, np);
+        WARN(!of_id, "restart function not available");
+
+        arm_pm_restart = of_id->data;
+}
+
 static struct map_desc sunxi_io_desc[] __initdata = {
         {
                 .virtual        = (unsigned long) SUNXI_REGS_VIRT_BASE,
@@ -81,6 +95,12 @@ void __init sunxi_map_io(void)
         iotable_init(sunxi_io_desc, ARRAY_SIZE(sunxi_io_desc));
 }
 
+static void __init sunxi_timer_init(void)
+{
+        sunxi_init_clocks();
+        clocksource_of_init();
+}
+
 static void __init sunxi_dt_init(void)
 {
         sunxi_setup_restart();
@@ -97,9 +117,7 @@ static const char * const sunxi_board_dt_compat[] = {
 DT_MACHINE_START(SUNXI_DT, "Allwinner A1X (Device Tree)")
         .init_machine   = sunxi_dt_init,
         .map_io         = sunxi_map_io,
-        .init_irq       = sunxi_init_irq,
-        .handle_irq     = sunxi_handle_irq,
-        .restart        = sunxi_restart,
-        .init_time      = &sunxi_timer_init,
+        .init_irq       = irqchip_init,
+        .init_time      = sunxi_timer_init,
         .dt_compat      = sunxi_board_dt_compat,
 MACHINE_END
diff --git a/arch/arm/mach-tegra/Makefile b/arch/arm/mach-tegra/Makefile
index 09b578f9eb84..c1970005f805 100644
--- a/arch/arm/mach-tegra/Makefile
+++ b/arch/arm/mach-tegra/Makefile
@@ -10,6 +10,7 @@ obj-y					+= pm.o
 obj-y                                   += reset.o
 obj-y                                   += reset-handler.o
 obj-y                                   += sleep.o
+obj-y                                   += tegra.o
 obj-$(CONFIG_CPU_IDLE)                  += cpuidle.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra20_speedo.o
 obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += tegra2_emc.o
@@ -26,9 +27,6 @@ obj-$(CONFIG_SMP)			+= platsmp.o headsmp.o
 obj-$(CONFIG_HOTPLUG_CPU)               += hotplug.o
 obj-$(CONFIG_TEGRA_PCI)                 += pcie.o
 
-obj-$(CONFIG_ARCH_TEGRA_2x_SOC)         += board-dt-tegra20.o
-obj-$(CONFIG_ARCH_TEGRA_3x_SOC)         += board-dt-tegra30.o
-obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += board-dt-tegra114.o
 ifeq ($(CONFIG_CPU_IDLE),y)
 obj-$(CONFIG_ARCH_TEGRA_114_SOC)        += cpuidle-tegra114.o
 endif
diff --git a/arch/arm/mach-tegra/board-dt-tegra114.c b/arch/arm/mach-tegra/board-dt-tegra114.c
deleted file mode 100644
index 085d63637b62..000000000000
--- a/arch/arm/mach-tegra/board-dt-tegra114.c
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * NVIDIA Tegra114 device tree board support
- *
- * Copyright (C) 2013 NVIDIA Corporation
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/of.h>
-#include <linux/of_platform.h>
-#include <linux/clocksource.h>
-
-#include <asm/mach/arch.h>
-
-#include "board.h"
-#include "common.h"
-
-static void __init tegra114_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char * const tegra114_dt_board_compat[] = {
-        "nvidia,tegra114",
-        NULL,
-};
-
-DT_MACHINE_START(TEGRA114_DT, "NVIDIA Tegra114 (Flattened Device Tree)")
-        .smp            = smp_ops(tegra_smp_ops),
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra114_init_early,
-        .init_irq       = tegra_dt_init_irq,
-        .init_time      = clocksource_of_init,
-        .init_machine   = tegra114_dt_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra114_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board-dt-tegra30.c b/arch/arm/mach-tegra/board-dt-tegra30.c
deleted file mode 100644
index bf68567e549d..000000000000
--- a/arch/arm/mach-tegra/board-dt-tegra30.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/arm/mach-tegra/board-dt-tegra30.c
- *
- * NVIDIA Tegra30 device tree board support
- *
- * Copyright (C) 2011 NVIDIA Corporation
- *
- * Derived from:
- *
- * arch/arm/mach-tegra/board-dt-tegra20.c
- *
- * Copyright (C) 2010 Secret Lab Technologies, Ltd.
- * Copyright (C) 2010 Google, Inc.
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-
-#include <linux/clocksource.h>
-#include <linux/kernel.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_fdt.h>
-#include <linux/of_irq.h>
-#include <linux/of_platform.h>
-
-#include <asm/mach/arch.h>
-
-#include "board.h"
-#include "common.h"
-#include "iomap.h"
-
-static void __init tegra30_dt_init(void)
-{
-        of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
-}
-
-static const char *tegra30_dt_board_compat[] = {
-        "nvidia,tegra30",
-        NULL
-};
-
-DT_MACHINE_START(TEGRA30_DT, "NVIDIA Tegra30 (Flattened Device Tree)")
-        .smp            = smp_ops(tegra_smp_ops),
-        .map_io         = tegra_map_common_io,
-        .init_early     = tegra30_init_early,
-        .init_irq       = tegra_dt_init_irq,
-        .init_time      = clocksource_of_init,
-        .init_machine   = tegra30_dt_init,
-        .init_late      = tegra_init_late,
-        .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra30_dt_board_compat,
-MACHINE_END
diff --git a/arch/arm/mach-tegra/board.h b/arch/arm/mach-tegra/board.h
index 86851c81a350..60431de585ca 100644
--- a/arch/arm/mach-tegra/board.h
+++ b/arch/arm/mach-tegra/board.h
@@ -26,9 +26,7 @@
 
 void tegra_assert_system_reset(char mode, const char *cmd);
 
-void __init tegra20_init_early(void);
-void __init tegra30_init_early(void);
-void __init tegra114_init_early(void);
+void __init tegra_init_early(void);
 void __init tegra_map_common_io(void);
 void __init tegra_init_irq(void);
 void __init tegra_dt_init_irq(void);
diff --git a/arch/arm/mach-tegra/common.c b/arch/arm/mach-tegra/common.c
index 5449a3f2977b..f0315c95c76d 100644
--- a/arch/arm/mach-tegra/common.c
+++ b/arch/arm/mach-tegra/common.c
@@ -94,7 +94,7 @@ static void __init tegra_init_cache(void)
 
 }
 
-static void __init tegra_init_early(void)
+void __init tegra_init_early(void)
 {
         tegra_cpu_reset_handler_init();
         tegra_apb_io_init();
@@ -102,31 +102,9 @@ static void __init tegra_init_early(void)
         tegra_init_cache();
         tegra_pmc_init();
         tegra_powergate_init();
+        tegra_hotplug_init();
 }
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-void __init tegra20_init_early(void)
-{
-        tegra_init_early();
-        tegra20_hotplug_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-void __init tegra30_init_early(void)
-{
-        tegra_init_early();
-        tegra30_hotplug_init();
-}
-#endif
-
-#ifdef CONFIG_ARCH_TEGRA_114_SOC
-void __init tegra114_init_early(void)
-{
-        tegra_init_early();
-}
-#endif
-
 void __init tegra_init_late(void)
 {
         tegra_powergate_debugfs_init();
diff --git a/arch/arm/mach-tegra/hotplug.c b/arch/arm/mach-tegra/hotplug.c
index a599f6e36dea..8da9f78475da 100644
--- a/arch/arm/mach-tegra/hotplug.c
+++ b/arch/arm/mach-tegra/hotplug.c
@@ -1,8 +1,7 @@
 /*
- *
  *  Copyright (C) 2002 ARM Ltd.
  *  All Rights Reserved
- *  Copyright (c) 2010, 2012 NVIDIA Corporation. All rights reserved.
+ *  Copyright (c) 2010, 2012-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,6 +14,7 @@
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
 
+#include "fuse.h"
 #include "sleep.h"
 
 static void (*tegra_hotplug_shutdown)(void);
@@ -56,18 +56,13 @@ int tegra_cpu_disable(unsigned int cpu)
         return cpu == 0 ? -EPERM : 0;
 }
 
-#ifdef CONFIG_ARCH_TEGRA_2x_SOC
-extern void tegra20_hotplug_shutdown(void);
-void __init tegra20_hotplug_init(void)
+void __init tegra_hotplug_init(void)
 {
-        tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
-}
-#endif
+        if (!IS_ENABLED(CONFIG_HOTPLUG_CPU))
+                return;
 
-#ifdef CONFIG_ARCH_TEGRA_3x_SOC
-extern void tegra30_hotplug_shutdown(void);
-void __init tegra30_hotplug_init(void)
-{
-        tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+                tegra_hotplug_shutdown = tegra20_hotplug_shutdown;
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+                tegra_hotplug_shutdown = tegra30_hotplug_shutdown;
 }
-#endif
diff --git a/arch/arm/mach-tegra/platsmp.c b/arch/arm/mach-tegra/platsmp.c
index e78d52d83acd..c31db797e199 100644
--- a/arch/arm/mach-tegra/platsmp.c
+++ b/arch/arm/mach-tegra/platsmp.c
@@ -18,7 +18,6 @@
 #include <linux/jiffies.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 #include <linux/clk/tegra.h>
 
 #include <asm/cacheflush.h>
@@ -26,53 +25,58 @@
 #include <asm/smp_scu.h>
 #include <asm/smp_plat.h>
 
-#include <mach/powergate.h>
-
 #include "fuse.h"
 #include "flowctrl.h"
 #include "reset.h"
+#include "pmc.h"
 
 #include "common.h"
 #include "iomap.h"
 
-extern void tegra_secondary_startup(void);
-
 static cpumask_t tegra_cpu_init_mask;
 
-#define EVP_CPU_RESET_VECTOR \
-        (IO_ADDRESS(TEGRA_EXCEPTION_VECTORS_BASE) + 0x100)
-
 static void __cpuinit tegra_secondary_init(unsigned int cpu)
 {
-        /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
         cpumask_set_cpu(cpu, &tegra_cpu_init_mask);
 }
 
-static int tegra20_power_up_cpu(unsigned int cpu)
+
+static int tegra20_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        /* Enable the CPU clock. */
-        tegra_enable_cpu_clock(cpu);
+        cpu = cpu_logical_map(cpu);
 
-        /* Clear flow controller CSR. */
-        flowctrl_write_cpu_csr(cpu, 0);
+        /*
+         * Force the CPU into reset. The CPU must remain in reset when
+         * the flow controller state is cleared (which will cause the
+         * flow controller to stop driving reset if the CPU has been
+         * power-gated via the flow controller). This will have no
+         * effect on first boot of the CPU since it should already be
+         * in reset.
+         */
+        tegra_put_cpu_in_reset(cpu);
 
+        /*
+         * Unhalt the CPU. If the flow controller was used to
+         * power-gate the CPU this will cause the flow controller to
+         * stop driving reset. The CPU will remain in reset because the
+         * clock and reset block is now driving reset.
+         */
+        flowctrl_write_cpu_halt(cpu, 0);
+
+        tegra_enable_cpu_clock(cpu);
+        flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
+        tegra_cpu_out_of_reset(cpu);
         return 0;
 }
 
-static int tegra30_power_up_cpu(unsigned int cpu)
+static int tegra30_boot_secondary(unsigned int cpu, struct task_struct *idle)
 {
-        int ret, pwrgateid;
+        int ret;
         unsigned long timeout;
 
-        pwrgateid = tegra_cpu_powergate_id(cpu);
-        if (pwrgateid < 0)
-                return pwrgateid;
+        cpu = cpu_logical_map(cpu);
+        tegra_put_cpu_in_reset(cpu);
+        flowctrl_write_cpu_halt(cpu, 0);
 
         /*
          * The power up sequence of cold boot CPU and warm boot CPU
@@ -85,13 +89,13 @@ static int tegra30_power_up_cpu(unsigned int cpu)
          * the IO clamps.
          * For cold boot CPU, do not wait. After the cold boot CPU be
          * booted, it will run to tegra_secondary_init() and set
-         * tegra_cpu_init_mask which influences what tegra30_power_up_cpu()
+         * tegra_cpu_init_mask which influences what tegra30_boot_secondary()
          * next time around.
          */
         if (cpumask_test_cpu(cpu, &tegra_cpu_init_mask)) {
                 timeout = jiffies + msecs_to_jiffies(50);
                 do {
-                        if (tegra_powergate_is_powered(pwrgateid))
+                        if (tegra_pmc_cpu_is_powered(cpu))
                                 goto remove_clamps;
                         udelay(10);
                 } while (time_before(jiffies, timeout));
@@ -103,14 +107,14 @@ static int tegra30_power_up_cpu(unsigned int cpu)
          * be un-gated by un-toggling the power gate register
          * manually.
          */
-        if (!tegra_powergate_is_powered(pwrgateid)) {
-                ret = tegra_powergate_power_on(pwrgateid);
+        if (!tegra_pmc_cpu_is_powered(cpu)) {
+                ret = tegra_pmc_cpu_power_on(cpu);
                 if (ret)
                         return ret;
 
                 /* Wait for the power to come up. */
                 timeout = jiffies + msecs_to_jiffies(100);
-                while (tegra_powergate_is_powered(pwrgateid)) {
+                while (tegra_pmc_cpu_is_powered(cpu)) {
                         if (time_after(jiffies, timeout))
                                 return -ETIMEDOUT;
                         udelay(10);
@@ -123,60 +127,26 @@ remove_clamps:
         udelay(10);
 
         /* Remove I/O clamps. */
-        ret = tegra_powergate_remove_clamping(pwrgateid);
+        ret = tegra_pmc_cpu_remove_clamping(cpu);
         if (ret)
                 return ret;
 
         udelay(10);
 
-        /* Clear flow controller CSR. */
-        flowctrl_write_cpu_csr(cpu, 0);
-
+        flowctrl_write_cpu_csr(cpu, 0); /* Clear flow controller CSR. */
+        tegra_cpu_out_of_reset(cpu);
         return 0;
 }
 
-static int __cpuinit tegra_boot_secondary(unsigned int cpu, struct task_struct *idle)
+static int __cpuinit tegra_boot_secondary(unsigned int cpu,
+                                          struct task_struct *idle)
 {
-        int status;
-
-        cpu = cpu_logical_map(cpu);
-
-        /*
-         * Force the CPU into reset. The CPU must remain in reset when the
-         * flow controller state is cleared (which will cause the flow
-         * controller to stop driving reset if the CPU has been power-gated
-         * via the flow controller). This will have no effect on first boot
-         * of the CPU since it should already be in reset.
-         */
-        tegra_put_cpu_in_reset(cpu);
-
-        /*
-         * Unhalt the CPU. If the flow controller was used to power-gate the
-         * CPU this will cause the flow controller to stop driving reset.
-         * The CPU will remain in reset because the clock and reset block
-         * is now driving reset.
-         */
-        flowctrl_write_cpu_halt(cpu, 0);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC) && tegra_chip_id == TEGRA20)
+                return tegra20_boot_secondary(cpu, idle);
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_3x_SOC) && tegra_chip_id == TEGRA30)
+                return tegra30_boot_secondary(cpu, idle);
 
-        switch (tegra_chip_id) {
-        case TEGRA20:
-                status = tegra20_power_up_cpu(cpu);
-                break;
-        case TEGRA30:
-                status = tegra30_power_up_cpu(cpu);
-                break;
-        default:
-                status = -EINVAL;
-                break;
-        }
-
-        if (status)
-                goto done;
-
-        /* Take the CPU out of reset. */
-        tegra_cpu_out_of_reset(cpu);
-done:
-        return status;
+        return -EINVAL;
 }
 
 static void __init tegra_smp_prepare_cpus(unsigned int max_cpus)
diff --git a/arch/arm/mach-tegra/pm.c b/arch/arm/mach-tegra/pm.c
index 04a8e06f59a9..891fb70d0aa7 100644
--- a/arch/arm/mach-tegra/pm.c
+++ b/arch/arm/mach-tegra/pm.c
@@ -169,12 +169,7 @@ int tegra_cpu_do_idle(void)
 
 static int tegra_sleep_cpu(unsigned long v2p)
 {
-        /* Switch to the identity mapping. */
-        cpu_switch_mm(idmap_pgd, &init_mm);
-
-        /* Flush the TLB. */
-        local_flush_tlb_all();
-
+        setup_mm_for_reboot();
         tegra_sleep_cpu_finish(v2p);
 
         /* should never here */
diff --git a/arch/arm/mach-tegra/pmc.c b/arch/arm/mach-tegra/pmc.c
index d4fdb5fcec20..b30e921cc3a9 100644
--- a/arch/arm/mach-tegra/pmc.c
+++ b/arch/arm/mach-tegra/pmc.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
+ * Copyright (C) 2012,2013 NVIDIA CORPORATION. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -18,57 +18,149 @@
 #include <linux/kernel.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 
-#include "iomap.h"
+#define PMC_CTRL                        0x0
+#define PMC_CTRL_INTR_LOW               (1 << 17)
+#define PMC_PWRGATE_TOGGLE              0x30
+#define PMC_PWRGATE_TOGGLE_START        (1 << 8)
+#define PMC_REMOVE_CLAMPING             0x34
+#define PMC_PWRGATE_STATUS              0x38
 
-#define PMC_CTRL                0x0
-#define PMC_CTRL_INTR_LOW       (1 << 17)
+#define TEGRA_POWERGATE_PCIE    3
+#define TEGRA_POWERGATE_VDEC    4
+#define TEGRA_POWERGATE_CPU1    9
+#define TEGRA_POWERGATE_CPU2    10
+#define TEGRA_POWERGATE_CPU3    11
+
+static u8 tegra_cpu_domains[] = {
+        0xFF,                   /* not available for CPU0 */
+        TEGRA_POWERGATE_CPU1,
+        TEGRA_POWERGATE_CPU2,
+        TEGRA_POWERGATE_CPU3,
+};
+static DEFINE_SPINLOCK(tegra_powergate_lock);
+
+static void __iomem *tegra_pmc_base;
+static bool tegra_pmc_invert_interrupt;
 
 static inline u32 tegra_pmc_readl(u32 reg)
 {
-        return readl(IO_ADDRESS(TEGRA_PMC_BASE + reg));
+        return readl(tegra_pmc_base + reg);
 }
 
 static inline void tegra_pmc_writel(u32 val, u32 reg)
 {
-        writel(val, IO_ADDRESS(TEGRA_PMC_BASE + reg));
+        writel(val, tegra_pmc_base + reg);
+}
+
+static int tegra_pmc_get_cpu_powerdomain_id(int cpuid)
+{
+        if (cpuid <= 0 || cpuid >= num_possible_cpus())
+                return -EINVAL;
+        return tegra_cpu_domains[cpuid];
+}
+
+static bool tegra_pmc_powergate_is_powered(int id)
+{
+        return (tegra_pmc_readl(PMC_PWRGATE_STATUS) >> id) & 1;
+}
+
+static int tegra_pmc_powergate_set(int id, bool new_state)
+{
+        bool old_state;
+        unsigned long flags;
+
+        spin_lock_irqsave(&tegra_powergate_lock, flags);
+
+        old_state = tegra_pmc_powergate_is_powered(id);
+        WARN_ON(old_state == new_state);
+
+        tegra_pmc_writel(PMC_PWRGATE_TOGGLE_START | id, PMC_PWRGATE_TOGGLE);
+
+        spin_unlock_irqrestore(&tegra_powergate_lock, flags);
+
+        return 0;
+}
+
+static int tegra_pmc_powergate_remove_clamping(int id)
+{
+        u32 mask;
+
+        /*
+         * Tegra has a bug where PCIE and VDE clamping masks are
+         * swapped relatively to the partition ids.
+         */
+        if (id ==  TEGRA_POWERGATE_VDEC)
+                mask = (1 << TEGRA_POWERGATE_PCIE);
+        else if (id == TEGRA_POWERGATE_PCIE)
+                mask = (1 << TEGRA_POWERGATE_VDEC);
+        else
+                mask = (1 << id);
+
+        tegra_pmc_writel(mask, PMC_REMOVE_CLAMPING);
+
+        return 0;
+}
+
+bool tegra_pmc_cpu_is_powered(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return false;
+        return tegra_pmc_powergate_is_powered(id);
+}
+
+int tegra_pmc_cpu_power_on(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return id;
+        return tegra_pmc_powergate_set(id, true);
+}
+
+int tegra_pmc_cpu_remove_clamping(int cpuid)
+{
+        int id;
+
+        id = tegra_pmc_get_cpu_powerdomain_id(cpuid);
+        if (id < 0)
+                return id;
+        return tegra_pmc_powergate_remove_clamping(id);
 }
 
-#ifdef CONFIG_OF
 static const struct of_device_id matches[] __initconst = {
+        { .compatible = "nvidia,tegra114-pmc" },
+        { .compatible = "nvidia,tegra30-pmc" },
         { .compatible = "nvidia,tegra20-pmc" },
         { }
 };
-#endif
 
-void __init tegra_pmc_init(void)
+static void tegra_pmc_parse_dt(void)
 {
-        /*
-         * For now, Harmony is the only board that uses the PMC, and it wants
-         * the signal inverted. Seaboard would too if it used the PMC.
-         * Hopefully by the time other boards want to use the PMC, everything
-         * will be device-tree, or they also want it inverted.
-         */
-        bool invert_interrupt = true;
-        u32 val;
+        struct device_node *np;
 
-#ifdef CONFIG_OF
-        if (of_have_populated_dt()) {
-                struct device_node *np;
+        np = of_find_matching_node(NULL, matches);
+        BUG_ON(!np);
 
-                invert_interrupt = false;
+        tegra_pmc_base = of_iomap(np, 0);
+
+        tegra_pmc_invert_interrupt = of_property_read_bool(np,
+                                     "nvidia,invert-interrupt");
+}
+
+void __init tegra_pmc_init(void)
+{
+        u32 val;
 
-                np = of_find_matching_node(NULL, matches);
-                if (np) {
-                        if (of_find_property(np, "nvidia,invert-interrupt",
-                                                NULL))
-                                invert_interrupt = true;
-                }
-        }
-#endif
+        tegra_pmc_parse_dt();
 
         val = tegra_pmc_readl(PMC_CTRL);
-        if (invert_interrupt)
+        if (tegra_pmc_invert_interrupt)
                 val |= PMC_CTRL_INTR_LOW;
         else
                 val &= ~PMC_CTRL_INTR_LOW;
diff --git a/arch/arm/mach-tegra/pmc.h b/arch/arm/mach-tegra/pmc.h
index 8995ee4a8768..7d44710368be 100644
--- a/arch/arm/mach-tegra/pmc.h
+++ b/arch/arm/mach-tegra/pmc.h
@@ -18,6 +18,10 @@
 #ifndef __MACH_TEGRA_PMC_H
 #define __MACH_TEGRA_PMC_H
 
+bool tegra_pmc_cpu_is_powered(int cpuid);
+int tegra_pmc_cpu_power_on(int cpuid);
+int tegra_pmc_cpu_remove_clamping(int cpuid);
+
 void tegra_pmc_init(void);
 
 #endif
diff --git a/arch/arm/mach-tegra/sleep.h b/arch/arm/mach-tegra/sleep.h
index bb308eab9079..2080fb12ce26 100644
--- a/arch/arm/mach-tegra/sleep.h
+++ b/arch/arm/mach-tegra/sleep.h
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010-2012, NVIDIA Corporation. All rights reserved.
+ * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify it
  * under the terms and conditions of the GNU General Public License,
@@ -124,11 +124,11 @@ int tegra_sleep_cpu_finish(unsigned long);
 void tegra_disable_clean_inv_dcache(void);
 
 #ifdef CONFIG_HOTPLUG_CPU
-void tegra20_hotplug_init(void);
-void tegra30_hotplug_init(void);
+void tegra20_hotplug_shutdown(void);
+void tegra30_hotplug_shutdown(void);
+void tegra_hotplug_init(void);
 #else
-static inline void tegra20_hotplug_init(void) {}
-static inline void tegra30_hotplug_init(void) {}
+static inline void tegra_hotplug_init(void) {}
 #endif
 
 void tegra20_cpu_shutdown(int cpu);
diff --git a/arch/arm/mach-tegra/board-dt-tegra20.c b/arch/arm/mach-tegra/tegra.c
index a0edf2510280..27232c901a22 100644
--- a/arch/arm/mach-tegra/board-dt-tegra20.c
+++ b/arch/arm/mach-tegra/tegra.c
@@ -1,6 +1,7 @@
 /*
- * nVidia Tegra device tree board support
+ * NVIDIA Tegra SoC device tree board support
  *
+ * Copyright (C) 2011, 2013, NVIDIA Corporation
  * Copyright (C) 2010 Secret Lab Technologies, Ltd.
  * Copyright (C) 2010 Google, Inc.
  *
@@ -111,7 +112,8 @@ static void __init harmony_init(void)
 
 static void __init paz00_init(void)
 {
-        tegra_paz00_wifikill_init();
+        if (IS_ENABLED(CONFIG_ARCH_TEGRA_2x_SOC))
+                tegra_paz00_wifikill_init();
 }
 
 static struct {
@@ -137,19 +139,21 @@ static void __init tegra_dt_init_late(void)
         }
 }
 
-static const char *tegra20_dt_board_compat[] = {
+static const char * const tegra_dt_board_compat[] = {
+        "nvidia,tegra114",
+        "nvidia,tegra30",
         "nvidia,tegra20",
         NULL
 };
 
-DT_MACHINE_START(TEGRA_DT, "nVidia Tegra20 (Flattened Device Tree)")
+DT_MACHINE_START(TEGRA_DT, "NVIDIA Tegra SoC (Flattened Device Tree)")
         .map_io         = tegra_map_common_io,
         .smp            = smp_ops(tegra_smp_ops),
-        .init_early     = tegra20_init_early,
+        .init_early     = tegra_init_early,
         .init_irq       = tegra_dt_init_irq,
         .init_time      = clocksource_of_init,
         .init_machine   = tegra_dt_init,
         .init_late      = tegra_dt_init_late,
         .restart        = tegra_assert_system_reset,
-        .dt_compat      = tegra20_dt_board_compat,
+        .dt_compat      = tegra_dt_board_compat,
 MACHINE_END
diff --git a/arch/arm/mach-ux500/platsmp.c b/arch/arm/mach-ux500/platsmp.c
index 18f7af339dc9..152b1309b9af 100644
--- a/arch/arm/mach-ux500/platsmp.c
+++ b/arch/arm/mach-ux500/platsmp.c
@@ -16,7 +16,6 @@
 #include <linux/device.h>
 #include <linux/smp.h>
 #include <linux/io.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -58,13 +57,6 @@ static DEFINE_SPINLOCK(boot_lock);
 static void __cpuinit ux500_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/arch/arm/mach-ux500/timer.c b/arch/arm/mach-ux500/timer.c
index a6af0b8732ba..d07bbe7f04a6 100644
--- a/arch/arm/mach-ux500/timer.c
+++ b/arch/arm/mach-ux500/timer.c
@@ -7,6 +7,7 @@
 #include <linux/io.h>
 #include <linux/errno.h>
 #include <linux/clksrc-dbx500-prcmu.h>
+#include <linux/clocksource.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/platform_data/clocksource-nomadik-mtu.h>
@@ -32,7 +33,7 @@ static void __init ux500_twd_init(void)
         twd_local_timer = &u8500_twd_local_timer;
 
         if (of_have_populated_dt())
-                twd_local_timer_of_register();
+                clocksource_of_init();
         else {
                 err = twd_local_timer_register(twd_local_timer);
                 if (err)
diff --git a/arch/arm/mach-vexpress/v2m.c b/arch/arm/mach-vexpress/v2m.c
index eb2b3a627f03..9366f37902d9 100644
--- a/arch/arm/mach-vexpress/v2m.c
+++ b/arch/arm/mach-vexpress/v2m.c
@@ -5,6 +5,7 @@
 #include <linux/amba/bus.h>
 #include <linux/amba/mmci.h>
 #include <linux/io.h>
+#include <linux/clocksource.h>
 #include <linux/smp.h>
 #include <linux/init.h>
 #include <linux/irqchip.h>
@@ -27,7 +28,6 @@
 #include <asm/arch_timer.h>
 #include <asm/mach-types.h>
 #include <asm/sizes.h>
-#include <asm/smp_twd.h>
 #include <asm/mach/arch.h>
 #include <asm/mach/map.h>
 #include <asm/mach/time.h>
@@ -434,6 +434,7 @@ static void __init v2m_dt_timer_init(void)
 
         of_clk_init(NULL);
 
+        clocksource_of_init();
         do {
                 node = of_find_compatible_node(node, NULL, "arm,sp804");
         } while (node && vexpress_get_site_by_node(node) != VEXPRESS_SITE_MB);
@@ -448,8 +449,7 @@ static void __init v2m_dt_timer_init(void)
                                 irq_of_parse_and_map(node, 0));
         }
 
-        if (arch_timer_of_register() != 0)
-                twd_local_timer_of_register();
+        arch_timer_of_register();
 
         if (arch_timer_sched_clock_init() != 0)
                 versatile_sched_clock_init(vexpress_get_24mhz_clock_base(),
diff --git a/arch/arm/mach-virt/platsmp.c b/arch/arm/mach-virt/platsmp.c
index 8badaabe70a1..f4143f5bfa5b 100644
--- a/arch/arm/mach-virt/platsmp.c
+++ b/arch/arm/mach-virt/platsmp.c
@@ -21,8 +21,6 @@
 #include <linux/smp.h>
 #include <linux/of.h>
 
-#include <linux/irqchip/arm-gic.h>
-
 #include <asm/psci.h>
 #include <asm/smp_plat.h>
 
@@ -45,14 +43,8 @@ static int __cpuinit virt_boot_secondary(unsigned int cpu,
         return -ENODEV;
 }
 
-static void __cpuinit virt_secondary_init(unsigned int cpu)
-{
-        gic_secondary_init(0);
-}
-
 struct smp_operations __initdata virt_smp_ops = {
         .smp_init_cpus          = virt_smp_init_cpus,
         .smp_prepare_cpus       = virt_smp_prepare_cpus,
-        .smp_secondary_init     = virt_secondary_init,
         .smp_boot_secondary     = virt_boot_secondary,
 };
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index a82cecb84948..ad97400ba3ad 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -3,7 +3,11 @@
 #
 ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
-obj-y                             += addr-map.o
+obj-$(CONFIG_ARCH_MVEBU)          += addr-map.o
+obj-$(CONFIG_ARCH_KIRKWOOD)       += addr-map.o
+obj-$(CONFIG_ARCH_DOVE)           += addr-map.o
+obj-$(CONFIG_ARCH_ORION5X)        += addr-map.o
+obj-$(CONFIG_ARCH_MV78XX0)        += addr-map.o
 
 orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
 obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
diff --git a/arch/arm/plat-orion/pcie.c b/arch/arm/plat-orion/pcie.c
index f20a321088a2..8b8c06d2e9c4 100644
--- a/arch/arm/plat-orion/pcie.c
+++ b/arch/arm/plat-orion/pcie.c
@@ -120,12 +120,14 @@ void __init orion_pcie_reset(void __iomem *base)
  * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
  * WIN[0-3] -> DRAM bank[0-3]
  */
-static void __init orion_pcie_setup_wins(void __iomem *base,
-                                         struct mbus_dram_target_info *dram)
+static void __init orion_pcie_setup_wins(void __iomem *base)
 {
+        const struct mbus_dram_target_info *dram;
         u32 size;
         int i;
 
+        dram = mv_mbus_dram_info();
+
         /*
          * First, disable and clear BARs and windows.
          */
@@ -150,7 +152,7 @@ static void __init orion_pcie_setup_wins(void __iomem *base,
          */
         size = 0;
         for (i = 0; i < dram->num_cs; i++) {
-                struct mbus_dram_window *cs = dram->cs + i;
+                const struct mbus_dram_window *cs = dram->cs + i;
 
                 writel(cs->base & 0xffff0000, base + PCIE_WIN04_BASE_OFF(i));
                 writel(0, base + PCIE_WIN04_REMAP_OFF(i));
@@ -184,7 +186,7 @@ void __init orion_pcie_setup(void __iomem *base)
         /*
          * Point PCIe unit MBUS decode windows to DRAM space.
          */
-        orion_pcie_setup_wins(base, &orion_mbus_dram_info);
+        orion_pcie_setup_wins(base);
 
         /*
          * Master + slave enable.
diff --git a/arch/arm/plat-samsung/Kconfig b/arch/arm/plat-samsung/Kconfig
index a9d52167e16e..91c2d72e689b 100644
--- a/arch/arm/plat-samsung/Kconfig
+++ b/arch/arm/plat-samsung/Kconfig
@@ -37,14 +37,6 @@ if PLAT_SAMSUNG
 
 comment "Boot options"
 
-config S3C_BOOT_WATCHDOG
-        bool "S3C Initialisation watchdog"
-        depends on S3C2410_WATCHDOG
-        help
-          Say y to enable the watchdog during the kernel decompression
-          stage. If the kernel fails to uncompress, then the watchdog
-          will trigger a reset and the system should restart.
-
 config S3C_BOOT_ERROR_RESET
         bool "S3C Reboot on decompression error"
         help
@@ -125,12 +117,6 @@ config SAMSUNG_GPIOLIB_4BIT
           configuration. GPIOlib shall be compiled only for S3C64XX and S5P
           series of processors.
 
-config S3C_GPIO_CFG_S3C64XX
-        bool
-        help
-          Internal configuration to enable S3C64XX style GPIO configuration
-          functions.
-
 config S5P_GPIO_DRVSTR
         bool
         help
diff --git a/arch/arm/plat-samsung/dma-ops.c b/arch/arm/plat-samsung/dma-ops.c
index 71d58ddea9c1..ec0d731b0e7b 100644
--- a/arch/arm/plat-samsung/dma-ops.c
+++ b/arch/arm/plat-samsung/dma-ops.c
@@ -23,23 +23,15 @@ static unsigned samsung_dmadev_request(enum dma_ch dma_ch,
                                 struct device *dev, char *ch_name)
 {
         dma_cap_mask_t mask;
-        void *filter_param;
 
         dma_cap_zero(mask);
         dma_cap_set(param->cap, mask);
 
-        /*
-         * If a dma channel property of a device node from device tree is
-         * specified, use that as the fliter parameter.
-         */
-        filter_param = (dma_ch == DMACH_DT_PROP) ?
-                (void *)param->dt_dmach_prop : (void *)dma_ch;
-
         if (dev->of_node)
                 return (unsigned)dma_request_slave_channel(dev, ch_name);
         else
                 return (unsigned)dma_request_channel(mask, pl330_filter,
-                                                        filter_param);
+                                                        (void *)dma_ch);
 }
 
 static int samsung_dmadev_release(unsigned ch, void *param)
diff --git a/arch/arm/plat-samsung/include/plat/dma-ops.h b/arch/arm/plat-samsung/include/plat/dma-ops.h
index 114178268b75..ce6d7634b6cb 100644
--- a/arch/arm/plat-samsung/include/plat/dma-ops.h
+++ b/arch/arm/plat-samsung/include/plat/dma-ops.h
@@ -18,7 +18,6 @@
 
 struct samsung_dma_req {
         enum dma_transaction_type cap;
-        struct property *dt_dmach_prop;
         struct s3c2410_dma_client *client;
 };
 
diff --git a/arch/arm/plat-samsung/include/plat/dma-pl330.h b/arch/arm/plat-samsung/include/plat/dma-pl330.h
index d384a8016b47..abe07fae71db 100644
--- a/arch/arm/plat-samsung/include/plat/dma-pl330.h
+++ b/arch/arm/plat-samsung/include/plat/dma-pl330.h
@@ -21,7 +21,6 @@
  * use these just as IDs.
  */
 enum dma_ch {
-        DMACH_DT_PROP = -1,
         DMACH_UART0_RX = 0,
         DMACH_UART0_TX,
         DMACH_UART1_RX,
diff --git a/arch/arm/plat-samsung/include/plat/irq.h b/arch/arm/plat-samsung/include/plat/irq.h
deleted file mode 100644
index e21a89bc26c9..000000000000
--- a/arch/arm/plat-samsung/include/plat/irq.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/irq.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU IRQ support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <linux/io.h>
-
-#include <mach/hardware.h>
-#include <mach/regs-irq.h>
-#include <mach/regs-gpio.h>
-
-#define irqdbf(x...)
-#define irqdbf2(x...)
-
-#define EXTINT_OFF (IRQ_EINT4 - 4)
-
-/* these are exported for arch/arm/mach-* usage */
-extern struct irq_chip s3c_irq_level_chip;
-extern struct irq_chip s3c_irq_chip;
-
-static inline void s3c_irqsub_mask(unsigned int irqno,
-                                   unsigned int parentbit,
-                                   int subcheck)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
-
-        /* check to see if we need to mask the parent IRQ */
-
-        if ((submask  & subcheck) == subcheck)
-                __raw_writel(mask | parentbit, S3C2410_INTMSK);
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-
-}
-
-static inline void s3c_irqsub_unmask(unsigned int irqno,
-                                     unsigned int parentbit)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
-        mask &= ~parentbit;
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-        __raw_writel(mask, S3C2410_INTMSK);
-}
-
-
-static inline void s3c_irqsub_maskack(unsigned int irqno,
-                                      unsigned int parentmask,
-                                      unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        s3c_irqsub_mask(irqno, parentmask, group);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-static inline void s3c_irqsub_ack(unsigned int irqno,
-                                  unsigned int parentmask,
-                                  unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-/* exported for use in arch/arm/mach-s3c2410 */
-
-#ifdef CONFIG_PM
-extern int s3c_irq_wake(struct irq_data *data, unsigned int state);
-#else
-#define s3c_irq_wake NULL
-#endif
-
-extern int s3c_irqext_type(struct irq_data *d, unsigned int type);
diff --git a/arch/arm/plat-samsung/include/plat/rtc-core.h b/arch/arm/plat-samsung/include/plat/rtc-core.h
index 21d8594d37ca..7b542f7b7938 100644
--- a/arch/arm/plat-samsung/include/plat/rtc-core.h
+++ b/arch/arm/plat-samsung/include/plat/rtc-core.h
@@ -19,7 +19,7 @@
 /* re-define device name depending on support. */
 static inline void s3c_rtc_setname(char *name)
 {
-#if defined(CONFIG_SAMSUNG_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
+#if defined(CONFIG_S3C_DEV_RTC) || defined(CONFIG_PLAT_S3C24XX)
         s3c_device_rtc.name = name;
 #endif
 }
diff --git a/arch/arm/plat-samsung/include/plat/s3c2410.h b/arch/arm/plat-samsung/include/plat/s3c2410.h
deleted file mode 100644
index 55b0e5f51e97..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2410.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2410.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 machine directory
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#ifdef CONFIG_CPU_S3C2410
-
-extern  int s3c2410_init(void);
-extern  int s3c2410a_init(void);
-
-extern void s3c2410_map_io(void);
-
-extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2410_init_clocks(int xtal);
-
-#else
-#define s3c2410_init_clocks NULL
-#define s3c2410_init_uarts NULL
-#define s3c2410_map_io NULL
-#define s3c2410_init NULL
-#define s3c2410a_init NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2412.h b/arch/arm/plat-samsung/include/plat/s3c2412.h
deleted file mode 100644
index cbae50ddacc8..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2412.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2412.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2412 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2412
-
-extern  int s3c2412_init(void);
-
-extern void s3c2412_map_io(void);
-
-extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2412_init_clocks(int xtal);
-
-extern  int s3c2412_baseclk_add(void);
-
-extern void s3c2412_restart(char mode, const char *cmd);
-#else
-#define s3c2412_init_clocks NULL
-#define s3c2412_init_uarts NULL
-#define s3c2412_map_io NULL
-#define s3c2412_init NULL
-#define s3c2412_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2416.h b/arch/arm/plat-samsung/include/plat/s3c2416.h
deleted file mode 100644
index f27399a3c68d..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2416.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2416.h
- *
- * Copyright (c) 2009 Yauhen Kharuzhy <jekhor@gmail.com>
- *
- * Header file for s3c2416 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2416
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2416_init(void);
-
-extern void s3c2416_map_io(void);
-
-extern void s3c2416_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2416_init_clocks(int xtal);
-
-extern  int s3c2416_baseclk_add(void);
-
-extern void s3c2416_restart(char mode, const char *cmd);
-
-extern void s3c2416_init_irq(void);
-extern struct syscore_ops s3c2416_irq_syscore_ops;
-
-#else
-#define s3c2416_init_clocks NULL
-#define s3c2416_init_uarts NULL
-#define s3c2416_map_io NULL
-#define s3c2416_init NULL
-#define s3c2416_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c2443.h b/arch/arm/plat-samsung/include/plat/s3c2443.h
deleted file mode 100644
index 71b88ec48956..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c2443.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c2443.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2443 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2443
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2443_init(void);
-
-extern void s3c2443_map_io(void);
-
-extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2443_init_clocks(int xtal);
-
-extern  int s3c2443_baseclk_add(void);
-
-extern void s3c2443_restart(char mode, const char *cmd);
-
-extern void s3c2443_init_irq(void);
-#else
-#define s3c2443_init_clocks NULL
-#define s3c2443_init_uarts NULL
-#define s3c2443_map_io NULL
-#define s3c2443_init NULL
-#define s3c2443_restart NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/s3c244x.h b/arch/arm/plat-samsung/include/plat/s3c244x.h
deleted file mode 100644
index ea0c961b7603..000000000000
--- a/arch/arm/plat-samsung/include/plat/s3c244x.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/* linux/arch/arm/plat-samsung/include/plat/s3c244x.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C2440 and S3C2442 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#if defined(CONFIG_CPU_S3C2440) || defined(CONFIG_CPU_S3C2442)
-
-extern void s3c244x_map_io(void);
-
-extern void s3c244x_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c244x_init_clocks(int xtal);
-
-#else
-#define s3c244x_init_clocks NULL
-#define s3c244x_init_uarts NULL
-#endif
-
-#ifdef CONFIG_CPU_S3C2440
-extern  int s3c2440_init(void);
-
-extern void s3c2440_map_io(void);
-#else
-#define s3c2440_init NULL
-#define s3c2440_map_io NULL
-#endif
-
-#ifdef CONFIG_CPU_S3C2442
-extern  int s3c2442_init(void);
-
-extern void s3c2442_map_io(void);
-#else
-#define s3c2442_init NULL
-#define s3c2442_map_io NULL
-#endif
diff --git a/arch/arm/plat-samsung/include/plat/sdhci.h b/arch/arm/plat-samsung/include/plat/sdhci.h
index 9b87f38fc4f4..5560586abec0 100644
--- a/arch/arm/plat-samsung/include/plat/sdhci.h
+++ b/arch/arm/plat-samsung/include/plat/sdhci.h
@@ -206,7 +206,7 @@ static inline void s3c6400_default_sdhci2(void) { }
 
 /* S5P64X0 SDHCI setup */
 
-#ifdef CONFIG_S5P64X0_SETUP_SDHCI
+#ifdef CONFIG_S5P64X0_SETUP_SDHCI_GPIO
 static inline void s5p64x0_default_sdhci0(void)
 {
 #ifdef CONFIG_S3C_DEV_HSMMC
@@ -241,7 +241,7 @@ static inline void s5p64x0_default_sdhci1(void) { }
 static inline void s5p6440_default_sdhci2(void) { }
 static inline void s5p6450_default_sdhci2(void) { }
 
-#endif /* CONFIG_S5P64X0_SETUP_SDHCI */
+#endif /* CONFIG_S5P64X0_SETUP_SDHCI_GPIO */
 
 /* S5PC100 SDHCI setup */
 
diff --git a/arch/arm/plat-samsung/irq-vic-timer.c b/arch/arm/plat-samsung/irq-vic-timer.c
index f980cf3d2baa..5d205e74e495 100644
--- a/arch/arm/plat-samsung/irq-vic-timer.c
+++ b/arch/arm/plat-samsung/irq-vic-timer.c
@@ -16,6 +16,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 
 #include <mach/map.h>
@@ -23,8 +24,6 @@
 #include <plat/irq-vic-timer.h>
 #include <plat/regs-timer.h>
 
-#include <asm/mach/irq.h>
-
 static void s3c_irq_demux_vic_timer(unsigned int irq, struct irq_desc *desc)
 {
         struct irq_chip *chip = irq_get_chip(irq);
diff --git a/arch/arm/plat-samsung/s5p-irq-gpioint.c b/arch/arm/plat-samsung/s5p-irq-gpioint.c
index bae56131a50a..fafdb059043a 100644
--- a/arch/arm/plat-samsung/s5p-irq-gpioint.c
+++ b/arch/arm/plat-samsung/s5p-irq-gpioint.c
@@ -14,6 +14,7 @@
 #include <linux/kernel.h>
 #include <linux/interrupt.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/slab.h>
@@ -22,8 +23,6 @@
 #include <plat/gpio-core.h>
 #include <plat/gpio-cfg.h>
 
-#include <asm/mach/irq.h>
-
 #define GPIO_BASE(chip)         ((void __iomem *)((unsigned long)((chip)->base) & 0xFFFFF000u))
 
 #define CON_OFFSET              0x700
diff --git a/arch/arm/plat-versatile/platsmp.c b/arch/arm/plat-versatile/platsmp.c
index f2ac15561778..1e1b2d769748 100644
--- a/arch/arm/plat-versatile/platsmp.c
+++ b/arch/arm/plat-versatile/platsmp.c
@@ -14,7 +14,6 @@
 #include <linux/device.h>
 #include <linux/jiffies.h>
 #include <linux/smp.h>
-#include <linux/irqchip/arm-gic.h>
 
 #include <asm/cacheflush.h>
 #include <asm/smp_plat.h>
@@ -37,13 +36,6 @@ static DEFINE_SPINLOCK(boot_lock);
 void __cpuinit versatile_secondary_init(unsigned int cpu)
 {
         /*
-         * if any interrupts are already enabled for the primary
-         * core (e.g. timer irq), then they will not have been enabled
-         * for us: do so
-         */
-        gic_secondary_init(0);
-
-        /*
          * let the primary processor know we're out of the
          * pen, then head off into the C entry point
          */
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index b5c06f9766f6..f6a74872f14e 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -15,12 +15,15 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/of.h>
-#include <mach/common.h>
-#include <mach/mx23.h>
+#include <linux/of_address.h>
 #include "clk.h"
 
-#define DIGCTRL                 MX23_IO_ADDRESS(MX23_DIGCTL_BASE_ADDR)
-#define CLKCTRL                 MX23_IO_ADDRESS(MX23_CLKCTRL_BASE_ADDR)
+static void __iomem *clkctrl;
+static void __iomem *digctrl;
+
+#define CLKCTRL clkctrl
+#define DIGCTRL digctrl
+
 #define PLLCTRL0                (CLKCTRL + 0x0000)
 #define CPU                     (CLKCTRL + 0x0020)
 #define HBUS                    (CLKCTRL + 0x0030)
@@ -48,10 +51,10 @@ static void __init clk_misc_init(void)
         u32 val;
 
         /* Gate off cpu clock in WFI for power saving */
-        __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
+        writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
 
         /* Clear BYPASS for SAIF */
-        __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ);
+        writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR);
 
         /* SAIF has to use frac div for functional operation */
         val = readl_relaxed(SAIF);
@@ -62,14 +65,14 @@ static void __init clk_misc_init(void)
          * Source ssp clock from ref_io than ref_xtal,
          * as ref_xtal only provides 24 MHz as maximum.
          */
-        __mxs_clrl(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ);
+        writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR);
 
         /*
          * 480 MHz seems too high to be ssp clock source directly,
          * so set frac to get a 288 MHz ref_io.
          */
-        __mxs_clrl(0x3f << BP_FRAC_IOFRAC, FRAC);
-        __mxs_setl(30 << BP_FRAC_IOFRAC, FRAC);
+        writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR);
+        writel_relaxed(30 << BP_FRAC_IOFRAC, FRAC + SET);
 }
 
 static const char *sel_pll[]  __initconst = { "pll", "ref_xtal", };
@@ -101,6 +104,14 @@ int __init mx23_clocks_init(void)
         struct device_node *np;
         u32 i;
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx23-digctl");
+        digctrl = of_iomap(np, 0);
+        WARN_ON(!digctrl);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
+        clkctrl = of_iomap(np, 0);
+        WARN_ON(!clkctrl);
+
         clk_misc_init();
 
         clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
@@ -153,19 +164,12 @@ int __init mx23_clocks_init(void)
                         return PTR_ERR(clks[i]);
                 }
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx23-clkctrl");
-        if (np) {
-                clk_data.clks = clks;
-                clk_data.clk_num = ARRAY_SIZE(clks);
-                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-        }
-
-        clk_register_clkdev(clks[clk32k], NULL, "timrot");
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clks[clks_init_on[i]]);
 
-        mxs_timer_init();
-
         return 0;
 }
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 76ce6c6d1113..d0e5eed146de 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -15,11 +15,12 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/of.h>
-#include <mach/common.h>
-#include <mach/mx28.h>
+#include <linux/of_address.h>
 #include "clk.h"
 
-#define CLKCTRL                 MX28_IO_ADDRESS(MX28_CLKCTRL_BASE_ADDR)
+static void __iomem *clkctrl;
+#define CLKCTRL clkctrl
+
 #define PLL0CTRL0               (CLKCTRL + 0x0000)
 #define PLL1CTRL0               (CLKCTRL + 0x0020)
 #define PLL2CTRL0               (CLKCTRL + 0x0040)
@@ -53,7 +54,8 @@
 #define BP_FRAC0_IO1FRAC        16
 #define BP_FRAC0_IO0FRAC        24
 
-#define DIGCTRL                 MX28_IO_ADDRESS(MX28_DIGCTL_BASE_ADDR)
+static void __iomem *digctrl;
+#define DIGCTRL digctrl
 #define BP_SAIF_CLKMUX          10
 
 /*
@@ -72,8 +74,8 @@ int mxs_saif_clkmux_select(unsigned int clkmux)
         if (clkmux > 0x3)
                 return -EINVAL;
 
-        __mxs_clrl(0x3 << BP_SAIF_CLKMUX, DIGCTRL);
-        __mxs_setl(clkmux << BP_SAIF_CLKMUX, DIGCTRL);
+        writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR);
+        writel_relaxed(clkmux << BP_SAIF_CLKMUX, DIGCTRL + SET);
 
         return 0;
 }
@@ -83,13 +85,13 @@ static void __init clk_misc_init(void)
         u32 val;
 
         /* Gate off cpu clock in WFI for power saving */
-        __mxs_setl(1 << BP_CPU_INTERRUPT_WAIT, CPU);
+        writel_relaxed(1 << BP_CPU_INTERRUPT_WAIT, CPU + SET);
 
         /* 0 is a bad default value for a divider */
-        __mxs_setl(1 << BP_ENET_DIV_TIME, ENET);
+        writel_relaxed(1 << BP_ENET_DIV_TIME, ENET + SET);
 
         /* Clear BYPASS for SAIF */
-        __mxs_clrl(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ);
+        writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR);
 
         /* SAIF has to use frac div for functional operation */
         val = readl_relaxed(SAIF0);
@@ -109,7 +111,7 @@ static void __init clk_misc_init(void)
          * Source ssp clock from ref_io than ref_xtal,
          * as ref_xtal only provides 24 MHz as maximum.
          */
-        __mxs_clrl(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ);
+        writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR);
 
         /*
          * 480 MHz seems too high to be ssp clock source directly,
@@ -156,6 +158,14 @@ int __init mx28_clocks_init(void)
         struct device_node *np;
         u32 i;
 
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx28-digctl");
+        digctrl = of_iomap(np, 0);
+        WARN_ON(!digctrl);
+
+        np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
+        clkctrl = of_iomap(np, 0);
+        WARN_ON(!clkctrl);
+
         clk_misc_init();
 
         clks[ref_xtal] = mxs_clk_fixed("ref_xtal", 24000000);
@@ -231,20 +241,14 @@ int __init mx28_clocks_init(void)
                         return PTR_ERR(clks[i]);
                 }
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,imx28-clkctrl");
-        if (np) {
-                clk_data.clks = clks;
-                clk_data.clk_num = ARRAY_SIZE(clks);
-                of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-        }
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
-        clk_register_clkdev(clks[xbus], NULL, "timrot");
         clk_register_clkdev(clks[enet_out], NULL, "enet_out");
 
         for (i = 0; i < ARRAY_SIZE(clks_init_on); i++)
                 clk_prepare_enable(clks[clks_init_on[i]]);
 
-        mxs_timer_init();
-
         return 0;
 }
diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig
index e507ab7df60b..9002185a0a1a 100644
--- a/drivers/clocksource/Kconfig
+++ b/drivers/clocksource/Kconfig
@@ -25,7 +25,7 @@ config DW_APB_TIMER_OF
 config ARMADA_370_XP_TIMER
         bool
 
-config SUNXI_TIMER
+config SUN4I_TIMER
         bool
 
 config VT8500_TIMER
diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile
index 96e25319659b..4897f243a000 100644
--- a/drivers/clocksource/Makefile
+++ b/drivers/clocksource/Makefile
@@ -16,7 +16,8 @@ obj-$(CONFIG_CLKSRC_NOMADIK_MTU)	+= nomadik-mtu.o
 obj-$(CONFIG_CLKSRC_DBX500_PRCMU)       += clksrc-dbx500-prcmu.o
 obj-$(CONFIG_ARMADA_370_XP_TIMER)       += time-armada-370-xp.o
 obj-$(CONFIG_ARCH_BCM2835)      += bcm2835_timer.o
-obj-$(CONFIG_SUNXI_TIMER)       += sunxi_timer.o
+obj-$(CONFIG_ARCH_MXS)          += mxs_timer.o
+obj-$(CONFIG_SUN4I_TIMER)       += sun4i_timer.o
 obj-$(CONFIG_ARCH_TEGRA)        += tegra20_timer.o
 obj-$(CONFIG_VT8500_TIMER)      += vt8500_timer.o
 obj-$(CONFIG_ARCH_BCM)          += bcm_kona_timer.o
diff --git a/drivers/clocksource/bcm2835_timer.c b/drivers/clocksource/bcm2835_timer.c
index 50c68fef944b..766611d29945 100644
--- a/drivers/clocksource/bcm2835_timer.c
+++ b/drivers/clocksource/bcm2835_timer.c
@@ -95,23 +95,13 @@ static irqreturn_t bcm2835_time_interrupt(int irq, void *dev_id)
         }
 }
 
-static struct of_device_id bcm2835_time_match[] __initconst = {
-        { .compatible = "brcm,bcm2835-system-timer" },
-        {}
-};
-
-static void __init bcm2835_timer_init(void)
+static void __init bcm2835_timer_init(struct device_node *node)
 {
-        struct device_node *node;
         void __iomem *base;
         u32 freq;
         int irq;
         struct bcm2835_timer *timer;
 
-        node = of_find_matching_node(NULL, bcm2835_time_match);
-        if (!node)
-                panic("No bcm2835 timer node");
-
         base = of_iomap(node, 0);
         if (!base)
                 panic("Can't remap registers");
diff --git a/drivers/clocksource/clksrc-of.c b/drivers/clocksource/clksrc-of.c
index bdabdaa8d00f..37f5325bec95 100644
--- a/drivers/clocksource/clksrc-of.c
+++ b/drivers/clocksource/clksrc-of.c
@@ -16,6 +16,7 @@
 
 #include <linux/init.h>
 #include <linux/of.h>
+#include <linux/clocksource.h>
 
 extern struct of_device_id __clksrc_of_table[];
 
@@ -26,10 +27,10 @@ void __init clocksource_of_init(void)
 {
         struct device_node *np;
         const struct of_device_id *match;
-        void (*init_func)(void);
+        clocksource_of_init_fn init_func;
 
         for_each_matching_node_and_match(np, __clksrc_of_table, &match) {
                 init_func = match->data;
-                init_func();
+                init_func(np);
         }
 }
diff --git a/arch/arm/mach-mxs/timer.c b/drivers/clocksource/mxs_timer.c
index 421020498a1b..02af4204af86 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/drivers/clocksource/mxs_timer.c
@@ -26,12 +26,12 @@
 #include <linux/clockchips.h>
 #include <linux/clk.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/stmp_device.h>
 
 #include <asm/mach/time.h>
 #include <asm/sched_clock.h>
-#include <mach/mxs.h>
-#include <mach/common.h>
 
 /*
  * There are 2 versions of the timrot on Freescale MXS-based SoCs.
@@ -79,25 +79,25 @@
 static struct clock_event_device mxs_clockevent_device;
 static enum clock_event_mode mxs_clockevent_mode = CLOCK_EVT_MODE_UNUSED;
 
-static void __iomem *mxs_timrot_base = MXS_IO_ADDRESS(MXS_TIMROT_BASE_ADDR);
+static void __iomem *mxs_timrot_base;
 static u32 timrot_major_version;
 
 static inline void timrot_irq_disable(void)
 {
-        __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ_EN,
-                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+        __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
+                     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
 }
 
 static inline void timrot_irq_enable(void)
 {
-        __mxs_setl(BM_TIMROT_TIMCTRLn_IRQ_EN,
-                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+        __raw_writel(BM_TIMROT_TIMCTRLn_IRQ_EN, mxs_timrot_base +
+                     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_SET);
 }
 
 static void timrot_irq_acknowledge(void)
 {
-        __mxs_clrl(BM_TIMROT_TIMCTRLn_IRQ,
-                        mxs_timrot_base + HW_TIMROT_TIMCTRLn(0));
+        __raw_writel(BM_TIMROT_TIMCTRLn_IRQ, mxs_timrot_base +
+                     HW_TIMROT_TIMCTRLn(0) + STMP_OFFSET_REG_CLR);
 }
 
 static cycle_t timrotv1_get_cycles(struct clocksource *cs)
@@ -242,19 +242,15 @@ static int __init mxs_clocksource_init(struct clk *timer_clk)
         return 0;
 }
 
-void __init mxs_timer_init(void)
+static void __init mxs_timer_init(struct device_node *np)
 {
-        struct device_node *np;
         struct clk *timer_clk;
         int irq;
 
-        np = of_find_compatible_node(NULL, NULL, "fsl,timrot");
-        if (!np) {
-                pr_err("%s: failed find timrot node\n", __func__);
-                return;
-        }
+        mxs_timrot_base = of_iomap(np, 0);
+        WARN_ON(!mxs_timrot_base);
 
-        timer_clk = clk_get_sys("timrot", NULL);
+        timer_clk = of_clk_get(np, 0);
         if (IS_ERR(timer_clk)) {
                 pr_err("%s: failed to get clk\n", __func__);
                 return;
@@ -265,11 +261,12 @@ void __init mxs_timer_init(void)
         /*
          * Initialize timers to a known state
          */
-        mxs_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
+        stmp_reset_block(mxs_timrot_base + HW_TIMROT_ROTCTRL);
 
         /* get timrot version */
         timrot_major_version = __raw_readl(mxs_timrot_base +
-                                (cpu_is_mx23() ? MX23_TIMROT_VERSION_OFFSET :
+                        (of_device_is_compatible(np, "fsl,imx23-timrot") ?
+                                                MX23_TIMROT_VERSION_OFFSET :
                                                 MX28_TIMROT_VERSION_OFFSET));
         timrot_major_version >>= BP_TIMROT_MAJOR_VERSION;
 
@@ -304,3 +301,4 @@ void __init mxs_timer_init(void)
         irq = irq_of_parse_and_map(np, 0);
         setup_irq(irq, &mxs_timer_irq);
 }
+CLOCKSOURCE_OF_DECLARE(mxs, "fsl,timrot", mxs_timer_init);
diff --git a/drivers/clocksource/sunxi_timer.c b/drivers/clocksource/sun4i_timer.c
index 0ce85e29769b..d4674e78ef35 100644
--- a/drivers/clocksource/sunxi_timer.c
+++ b/drivers/clocksource/sun4i_timer.c
@@ -22,66 +22,64 @@
 #include <linux/of.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
-#include <linux/sunxi_timer.h>
-#include <linux/clk/sunxi.h>
 
-#define TIMER_CTL_REG           0x00
-#define TIMER_CTL_ENABLE                (1 << 0)
+#define TIMER_IRQ_EN_REG        0x00
+#define TIMER_IRQ_EN(val)               (1 << val)
 #define TIMER_IRQ_ST_REG        0x04
-#define TIMER0_CTL_REG          0x10
-#define TIMER0_CTL_ENABLE               (1 << 0)
-#define TIMER0_CTL_AUTORELOAD           (1 << 1)
-#define TIMER0_CTL_ONESHOT              (1 << 7)
-#define TIMER0_INTVAL_REG       0x14
-#define TIMER0_CNTVAL_REG       0x18
+#define TIMER_CTL_REG(val)      (0x10 * val + 0x10)
+#define TIMER_CTL_ENABLE                (1 << 0)
+#define TIMER_CTL_AUTORELOAD            (1 << 1)
+#define TIMER_CTL_ONESHOT               (1 << 7)
+#define TIMER_INTVAL_REG(val)   (0x10 * val + 0x14)
+#define TIMER_CNTVAL_REG(val)   (0x10 * val + 0x18)
 
 #define TIMER_SCAL              16
 
 static void __iomem *timer_base;
 
-static void sunxi_clkevt_mode(enum clock_event_mode mode,
+static void sun4i_clkevt_mode(enum clock_event_mode mode,
                               struct clock_event_device *clk)
 {
-        u32 u = readl(timer_base + TIMER0_CTL_REG);
+        u32 u = readl(timer_base + TIMER_CTL_REG(0));
 
         switch (mode) {
         case CLOCK_EVT_MODE_PERIODIC:
-                u &= ~(TIMER0_CTL_ONESHOT);
-                writel(u | TIMER0_CTL_ENABLE, timer_base + TIMER0_CTL_REG);
+                u &= ~(TIMER_CTL_ONESHOT);
+                writel(u | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG(0));
                 break;
 
         case CLOCK_EVT_MODE_ONESHOT:
-                writel(u | TIMER0_CTL_ONESHOT, timer_base + TIMER0_CTL_REG);
+                writel(u | TIMER_CTL_ONESHOT, timer_base + TIMER_CTL_REG(0));
                 break;
         case CLOCK_EVT_MODE_UNUSED:
         case CLOCK_EVT_MODE_SHUTDOWN:
         default:
-                writel(u & ~(TIMER0_CTL_ENABLE), timer_base + TIMER0_CTL_REG);
+                writel(u & ~(TIMER_CTL_ENABLE), timer_base + TIMER_CTL_REG(0));
                 break;
         }
 }
 
-static int sunxi_clkevt_next_event(unsigned long evt,
+static int sun4i_clkevt_next_event(unsigned long evt,
                                    struct clock_event_device *unused)
 {
-        u32 u = readl(timer_base + TIMER0_CTL_REG);
-        writel(evt, timer_base + TIMER0_CNTVAL_REG);
-        writel(u | TIMER0_CTL_ENABLE | TIMER0_CTL_AUTORELOAD,
-               timer_base + TIMER0_CTL_REG);
+        u32 u = readl(timer_base + TIMER_CTL_REG(0));
+        writel(evt, timer_base + TIMER_CNTVAL_REG(0));
+        writel(u | TIMER_CTL_ENABLE | TIMER_CTL_AUTORELOAD,
+               timer_base + TIMER_CTL_REG(0));
 
         return 0;
 }
 
-static struct clock_event_device sunxi_clockevent = {
-        .name = "sunxi_tick",
+static struct clock_event_device sun4i_clockevent = {
+        .name = "sun4i_tick",
         .rating = 300,
         .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
-        .set_mode = sunxi_clkevt_mode,
-        .set_next_event = sunxi_clkevt_next_event,
+        .set_mode = sun4i_clkevt_mode,
+        .set_next_event = sun4i_clkevt_next_event,
 };
 
 
-static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
+static irqreturn_t sun4i_timer_interrupt(int irq, void *dev_id)
 {
         struct clock_event_device *evt = (struct clock_event_device *)dev_id;
 
@@ -91,30 +89,20 @@ static irqreturn_t sunxi_timer_interrupt(int irq, void *dev_id)
         return IRQ_HANDLED;
 }
 
-static struct irqaction sunxi_timer_irq = {
-        .name = "sunxi_timer0",
+static struct irqaction sun4i_timer_irq = {
+        .name = "sun4i_timer0",
         .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
-        .handler = sunxi_timer_interrupt,
-        .dev_id = &sunxi_clockevent,
-};
-
-static struct of_device_id sunxi_timer_dt_ids[] = {
-        { .compatible = "allwinner,sunxi-timer" },
-        { }
+        .handler = sun4i_timer_interrupt,
+        .dev_id = &sun4i_clockevent,
 };
 
-void __init sunxi_timer_init(void)
+static void __init sun4i_timer_init(struct device_node *node)
 {
-        struct device_node *node;
         unsigned long rate = 0;
         struct clk *clk;
         int ret, irq;
         u32 val;
 
-        node = of_find_matching_node(NULL, sunxi_timer_dt_ids);
-        if (!node)
-                panic("No sunxi timer node");
-
         timer_base = of_iomap(node, 0);
         if (!timer_base)
                 panic("Can't map registers");
@@ -123,8 +111,6 @@ void __init sunxi_timer_init(void)
         if (irq <= 0)
                 panic("Can't parse IRQ");
 
-        sunxi_init_clocks();
-
         clk = of_clk_get(node, 0);
         if (IS_ERR(clk))
                 panic("Can't get timer clock");
@@ -132,29 +118,31 @@ void __init sunxi_timer_init(void)
         rate = clk_get_rate(clk);
 
         writel(rate / (TIMER_SCAL * HZ),
-               timer_base + TIMER0_INTVAL_REG);
+               timer_base + TIMER_INTVAL_REG(0));
 
         /* set clock source to HOSC, 16 pre-division */
-        val = readl(timer_base + TIMER0_CTL_REG);
+        val = readl(timer_base + TIMER_CTL_REG(0));
         val &= ~(0x07 << 4);
         val &= ~(0x03 << 2);
         val |= (4 << 4) | (1 << 2);
-        writel(val, timer_base + TIMER0_CTL_REG);
+        writel(val, timer_base + TIMER_CTL_REG(0));
 
         /* set mode to auto reload */
-        val = readl(timer_base + TIMER0_CTL_REG);
-        writel(val | TIMER0_CTL_AUTORELOAD, timer_base + TIMER0_CTL_REG);
+        val = readl(timer_base + TIMER_CTL_REG(0));
+        writel(val | TIMER_CTL_AUTORELOAD, timer_base + TIMER_CTL_REG(0));
 
-        ret = setup_irq(irq, &sunxi_timer_irq);
+        ret = setup_irq(irq, &sun4i_timer_irq);
         if (ret)
                 pr_warn("failed to setup irq %d\n", irq);
 
         /* Enable timer0 interrupt */
-        val = readl(timer_base + TIMER_CTL_REG);
-        writel(val | TIMER_CTL_ENABLE, timer_base + TIMER_CTL_REG);
+        val = readl(timer_base + TIMER_IRQ_EN_REG);
+        writel(val | TIMER_IRQ_EN(0), timer_base + TIMER_IRQ_EN_REG);
 
-        sunxi_clockevent.cpumask = cpumask_of(0);
+        sun4i_clockevent.cpumask = cpumask_of(0);
 
-        clockevents_config_and_register(&sunxi_clockevent, rate / TIMER_SCAL,
+        clockevents_config_and_register(&sun4i_clockevent, rate / TIMER_SCAL,
                                         0x1, 0xff);
 }
+CLOCKSOURCE_OF_DECLARE(sun4i, "allwinner,sun4i-timer",
+                       sun4i_timer_init);
diff --git a/drivers/clocksource/tegra20_timer.c b/drivers/clocksource/tegra20_timer.c
index 0bde03feb095..ae877b021b54 100644
--- a/drivers/clocksource/tegra20_timer.c
+++ b/drivers/clocksource/tegra20_timer.c
@@ -154,29 +154,12 @@ static struct irqaction tegra_timer_irq = {
         .dev_id         = &tegra_clockevent,
 };
 
-static const struct of_device_id timer_match[] __initconst = {
-        { .compatible = "nvidia,tegra20-timer" },
-        {}
-};
-
-static const struct of_device_id rtc_match[] __initconst = {
-        { .compatible = "nvidia,tegra20-rtc" },
-        {}
-};
-
-static void __init tegra20_init_timer(void)
+static void __init tegra20_init_timer(struct device_node *np)
 {
-        struct device_node *np;
         struct clk *clk;
         unsigned long rate;
         int ret;
 
-        np = of_find_matching_node(NULL, timer_match);
-        if (!np) {
-                pr_err("Failed to find timer DT node\n");
-                BUG();
-        }
-
         timer_reg_base = of_iomap(np, 0);
         if (!timer_reg_base) {
                 pr_err("Can't map timer registers\n");
@@ -189,7 +172,7 @@ static void __init tegra20_init_timer(void)
                 BUG();
         }
 
-        clk = clk_get_sys("timer", NULL);
+        clk = of_clk_get(np, 0);
         if (IS_ERR(clk)) {
                 pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
                 rate = 12000000;
@@ -200,30 +183,6 @@ static void __init tegra20_init_timer(void)
 
         of_node_put(np);
 
-        np = of_find_matching_node(NULL, rtc_match);
-        if (!np) {
-                pr_err("Failed to find RTC DT node\n");
-                BUG();
-        }
-
-        rtc_base = of_iomap(np, 0);
-        if (!rtc_base) {
-                pr_err("Can't map RTC registers");
-                BUG();
-        }
-
-        /*
-         * rtc registers are used by read_persistent_clock, keep the rtc clock
-         * enabled
-         */
-        clk = clk_get_sys("rtc-tegra", NULL);
-        if (IS_ERR(clk))
-                pr_warn("Unable to get rtc-tegra clock\n");
-        else
-                clk_prepare_enable(clk);
-
-        of_node_put(np);
-
         switch (rate) {
         case 12000000:
                 timer_writel(0x000b, TIMERUS_USEC_CFG);
@@ -259,12 +218,34 @@ static void __init tegra20_init_timer(void)
         tegra_clockevent.irq = tegra_timer_irq.irq;
         clockevents_config_and_register(&tegra_clockevent, 1000000,
                                         0x1, 0x1fffffff);
-#ifdef CONFIG_HAVE_ARM_TWD
-        twd_local_timer_of_register();
-#endif
+}
+CLOCKSOURCE_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer);
+
+static void __init tegra20_init_rtc(struct device_node *np)
+{
+        struct clk *clk;
+
+        rtc_base = of_iomap(np, 0);
+        if (!rtc_base) {
+                pr_err("Can't map RTC registers");
+                BUG();
+        }
+
+        /*
+         * rtc registers are used by read_persistent_clock, keep the rtc clock
+         * enabled
+         */
+        clk = of_clk_get(np, 0);
+        if (IS_ERR(clk))
+                pr_warn("Unable to get rtc-tegra clock\n");
+        else
+                clk_prepare_enable(clk);
+
+        of_node_put(np);
+
         register_persistent_clock(NULL, tegra_read_persistent_clock);
 }
-CLOCKSOURCE_OF_DECLARE(tegra20, "nvidia,tegra20-timer", tegra20_init_timer);
+CLOCKSOURCE_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc);
 
 #ifdef CONFIG_PM
 static u32 usec_config;
diff --git a/drivers/clocksource/vt8500_timer.c b/drivers/clocksource/vt8500_timer.c
index 8efc86b5b5dd..64f553f04fa4 100644
--- a/drivers/clocksource/vt8500_timer.c
+++ b/drivers/clocksource/vt8500_timer.c
@@ -129,22 +129,10 @@ static struct irqaction irq = {
         .dev_id  = &clockevent,
 };
 
-static struct of_device_id vt8500_timer_ids[] = {
-        { .compatible = "via,vt8500-timer" },
-        { }
-};
-
-static void __init vt8500_timer_init(void)
+static void __init vt8500_timer_init(struct device_node *np)
 {
-        struct device_node *np;
         int timer_irq;
 
-        np = of_find_matching_node(NULL, vt8500_timer_ids);
-        if (!np) {
-                pr_err("%s: Timer description missing from Device Tree\n",
-                                                                __func__);
-                return;
-        }
         regbase = of_iomap(np, 0);
         if (!regbase) {
                 pr_err("%s: Missing iobase description in Device Tree\n",
@@ -177,4 +165,4 @@ static void __init vt8500_timer_init(void)
                                         4, 0xf0000000);
 }
 
-CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init)
+CLOCKSOURCE_OF_DECLARE(vt8500, "via,vt8500-timer", vt8500_timer_init);
diff --git a/drivers/gpio/gpio-msm-v1.c b/drivers/gpio/gpio-msm-v1.c
index 52a4d4286eba..c798585a3fe5 100644
--- a/drivers/gpio/gpio-msm-v1.c
+++ b/drivers/gpio/gpio-msm-v1.c
@@ -1,6 +1,6 @@
 /*
  * Copyright (C) 2007 Google, Inc.
- * Copyright (c) 2009-2011, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2009-2012, The Linux Foundation. All rights reserved.
  *
  * This software is licensed under the terms of the GNU General Public
  * License version 2, as published by the Free Software Foundation, and
@@ -19,9 +19,10 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/module.h>
-#include <mach/cpu.h>
+#include <linux/device.h>
+#include <linux/platform_device.h>
+
 #include <mach/msm_gpiomux.h>
-#include <mach/msm_iomap.h>
 
 /* see 80-VA736-2 Rev C pp 695-751
 **
@@ -34,10 +35,10 @@
 ** macros.
 */
 
-#define MSM_GPIO1_REG(off) (MSM_GPIO1_BASE + (off))
-#define MSM_GPIO2_REG(off) (MSM_GPIO2_BASE + 0x400 + (off))
-#define MSM_GPIO1_SHADOW_REG(off) (MSM_GPIO1_BASE + 0x800 + (off))
-#define MSM_GPIO2_SHADOW_REG(off) (MSM_GPIO2_BASE + 0xC00 + (off))
+#define MSM_GPIO1_REG(off) (off)
+#define MSM_GPIO2_REG(off) (off)
+#define MSM_GPIO1_SHADOW_REG(off) (off)
+#define MSM_GPIO2_SHADOW_REG(off) (off)
 
 /*
  * MSM7X00 registers
@@ -276,16 +277,14 @@
 
 #define MSM_GPIO_BANK(soc, bank, first, last)                           \
         {                                                               \
-                .regs = {                                               \
-                        .out =         soc##_GPIO_OUT_##bank,           \
-                        .in =          soc##_GPIO_IN_##bank,            \
-                        .int_status =  soc##_GPIO_INT_STATUS_##bank,    \
-                        .int_clear =   soc##_GPIO_INT_CLEAR_##bank,     \
-                        .int_en =      soc##_GPIO_INT_EN_##bank,        \
-                        .int_edge =    soc##_GPIO_INT_EDGE_##bank,      \
-                        .int_pos =     soc##_GPIO_INT_POS_##bank,       \
-                        .oe =          soc##_GPIO_OE_##bank,            \
-                },                                                      \
+                .regs[MSM_GPIO_OUT] =         soc##_GPIO_OUT_##bank,    \
+                .regs[MSM_GPIO_IN] =          soc##_GPIO_IN_##bank,     \
+                .regs[MSM_GPIO_INT_STATUS] =  soc##_GPIO_INT_STATUS_##bank, \
+                .regs[MSM_GPIO_INT_CLEAR] =   soc##_GPIO_INT_CLEAR_##bank, \
+                .regs[MSM_GPIO_INT_EN] =      soc##_GPIO_INT_EN_##bank, \
+                .regs[MSM_GPIO_INT_EDGE] =    soc##_GPIO_INT_EDGE_##bank, \
+                .regs[MSM_GPIO_INT_POS] =     soc##_GPIO_INT_POS_##bank, \
+                .regs[MSM_GPIO_OE] =          soc##_GPIO_OE_##bank,     \
                 .chip = {                                               \
                         .base = (first),                                \
                         .ngpio = (last) - (first) + 1,                  \
@@ -301,39 +300,57 @@
 
 #define MSM_GPIO_BROKEN_INT_CLEAR 1
 
-struct msm_gpio_regs {
-        void __iomem *out;
-        void __iomem *in;
-        void __iomem *int_status;
-        void __iomem *int_clear;
-        void __iomem *int_en;
-        void __iomem *int_edge;
-        void __iomem *int_pos;
-        void __iomem *oe;
+enum msm_gpio_reg {
+        MSM_GPIO_IN,
+        MSM_GPIO_OUT,
+        MSM_GPIO_INT_STATUS,
+        MSM_GPIO_INT_CLEAR,
+        MSM_GPIO_INT_EN,
+        MSM_GPIO_INT_EDGE,
+        MSM_GPIO_INT_POS,
+        MSM_GPIO_OE,
+        MSM_GPIO_REG_NR
 };
 
 struct msm_gpio_chip {
         spinlock_t              lock;
         struct gpio_chip        chip;
-        struct msm_gpio_regs    regs;
+        unsigned long           regs[MSM_GPIO_REG_NR];
 #if MSM_GPIO_BROKEN_INT_CLEAR
         unsigned                int_status_copy;
 #endif
         unsigned int            both_edge_detect;
         unsigned int            int_enable[2]; /* 0: awake, 1: sleep */
+        void __iomem            *base;
+};
+
+struct msm_gpio_initdata {
+        struct msm_gpio_chip *chips;
+        int count;
 };
 
+static void msm_gpio_writel(struct msm_gpio_chip *chip, u32 val,
+                            enum msm_gpio_reg reg)
+{
+        writel(val, chip->base + chip->regs[reg]);
+}
+
+static u32 msm_gpio_readl(struct msm_gpio_chip *chip, enum msm_gpio_reg reg)
+{
+        return readl(chip->base + chip->regs[reg]);
+}
+
 static int msm_gpio_write(struct msm_gpio_chip *msm_chip,
                           unsigned offset, unsigned on)
 {
         unsigned mask = BIT(offset);
         unsigned val;
 
-        val = readl(msm_chip->regs.out);
+        val = msm_gpio_readl(msm_chip, MSM_GPIO_OUT);
         if (on)
-                writel(val | mask, msm_chip->regs.out);
+                msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_OUT);
         else
-                writel(val & ~mask, msm_chip->regs.out);
+                msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_OUT);
         return 0;
 }
 
@@ -342,13 +359,13 @@ static void msm_gpio_update_both_edge_detect(struct msm_gpio_chip *msm_chip)
         int loop_limit = 100;
         unsigned pol, val, val2, intstat;
         do {
-                val = readl(msm_chip->regs.in);
-                pol = readl(msm_chip->regs.int_pos);
+                val = msm_gpio_readl(msm_chip, MSM_GPIO_IN);
+                pol = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS);
                 pol = (pol & ~msm_chip->both_edge_detect) |
                       (~val & msm_chip->both_edge_detect);
-                writel(pol, msm_chip->regs.int_pos);
-                intstat = readl(msm_chip->regs.int_status);
-                val2 = readl(msm_chip->regs.in);
+                msm_gpio_writel(msm_chip, pol, MSM_GPIO_INT_POS);
+                intstat = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
+                val2 = msm_gpio_readl(msm_chip, MSM_GPIO_IN);
                 if (((val ^ val2) & msm_chip->both_edge_detect & ~intstat) == 0)
                         return;
         } while (loop_limit-- > 0);
@@ -365,10 +382,11 @@ static int msm_gpio_clear_detect_status(struct msm_gpio_chip *msm_chip,
         /* Save interrupts that already triggered before we loose them. */
         /* Any interrupt that triggers between the read of int_status */
         /* and the write to int_clear will still be lost though. */
-        msm_chip->int_status_copy |= readl(msm_chip->regs.int_status);
+        msm_chip->int_status_copy |=
+                msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
         msm_chip->int_status_copy &= ~bit;
 #endif
-        writel(bit, msm_chip->regs.int_clear);
+        msm_gpio_writel(msm_chip, bit, MSM_GPIO_INT_CLEAR);
         msm_gpio_update_both_edge_detect(msm_chip);
         return 0;
 }
@@ -377,10 +395,12 @@ static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
 {
         struct msm_gpio_chip *msm_chip;
         unsigned long irq_flags;
+        u32 val;
 
         msm_chip = container_of(chip, struct msm_gpio_chip, chip);
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
-        writel(readl(msm_chip->regs.oe) & ~BIT(offset), msm_chip->regs.oe);
+        val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) & ~BIT(offset);
+        msm_gpio_writel(msm_chip, val, MSM_GPIO_OE);
         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
         return 0;
 }
@@ -390,11 +410,13 @@ msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
 {
         struct msm_gpio_chip *msm_chip;
         unsigned long irq_flags;
+        u32 val;
 
         msm_chip = container_of(chip, struct msm_gpio_chip, chip);
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
         msm_gpio_write(msm_chip, offset, value);
-        writel(readl(msm_chip->regs.oe) | BIT(offset), msm_chip->regs.oe);
+        val = msm_gpio_readl(msm_chip, MSM_GPIO_OE) | BIT(offset);
+        msm_gpio_writel(msm_chip, val, MSM_GPIO_OE);
         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
         return 0;
 }
@@ -404,7 +426,7 @@ static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
         struct msm_gpio_chip *msm_chip;
 
         msm_chip = container_of(chip, struct msm_gpio_chip, chip);
-        return (readl(msm_chip->regs.in) & (1U << offset)) ? 1 : 0;
+        return (msm_gpio_readl(msm_chip, MSM_GPIO_IN) & (1U << offset)) ? 1 : 0;
 }
 
 static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
@@ -450,6 +472,11 @@ static struct msm_gpio_chip msm_gpio_chips_msm7x01[] = {
         MSM_GPIO_BANK(MSM7X00, 5, 107, 121),
 };
 
+static struct msm_gpio_initdata msm_gpio_7x01_init = {
+        .chips = msm_gpio_chips_msm7x01,
+        .count = ARRAY_SIZE(msm_gpio_chips_msm7x01),
+};
+
 static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
         MSM_GPIO_BANK(MSM7X30, 0,   0,  15),
         MSM_GPIO_BANK(MSM7X30, 1,  16,  43),
@@ -461,6 +488,11 @@ static struct msm_gpio_chip msm_gpio_chips_msm7x30[] = {
         MSM_GPIO_BANK(MSM7X30, 7, 151, 181),
 };
 
+static struct msm_gpio_initdata msm_gpio_7x30_init = {
+        .chips = msm_gpio_chips_msm7x30,
+        .count = ARRAY_SIZE(msm_gpio_chips_msm7x30),
+};
+
 static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
         MSM_GPIO_BANK(QSD8X50, 0,   0,  15),
         MSM_GPIO_BANK(QSD8X50, 1,  16,  42),
@@ -472,6 +504,11 @@ static struct msm_gpio_chip msm_gpio_chips_qsd8x50[] = {
         MSM_GPIO_BANK(QSD8X50, 7, 153, 164),
 };
 
+static struct msm_gpio_initdata msm_gpio_8x50_init = {
+        .chips = msm_gpio_chips_qsd8x50,
+        .count = ARRAY_SIZE(msm_gpio_chips_qsd8x50),
+};
+
 static void msm_gpio_irq_ack(struct irq_data *d)
 {
         unsigned long irq_flags;
@@ -490,10 +527,10 @@ static void msm_gpio_irq_mask(struct irq_data *d)
 
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
         /* level triggered interrupts are also latched */
-        if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
+        if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset)))
                 msm_gpio_clear_detect_status(msm_chip, offset);
         msm_chip->int_enable[0] &= ~BIT(offset);
-        writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
+        msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN);
         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 }
 
@@ -505,10 +542,10 @@ static void msm_gpio_irq_unmask(struct irq_data *d)
 
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
         /* level triggered interrupts are also latched */
-        if (!(readl(msm_chip->regs.int_edge) & BIT(offset)))
+        if (!(msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE) & BIT(offset)))
                 msm_gpio_clear_detect_status(msm_chip, offset);
         msm_chip->int_enable[0] |= BIT(offset);
-        writel(msm_chip->int_enable[0], msm_chip->regs.int_en);
+        msm_gpio_writel(msm_chip, msm_chip->int_enable[0], MSM_GPIO_INT_EN);
         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
 }
 
@@ -537,12 +574,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
         unsigned val, mask = BIT(offset);
 
         spin_lock_irqsave(&msm_chip->lock, irq_flags);
-        val = readl(msm_chip->regs.int_edge);
+        val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_EDGE);
         if (flow_type & IRQ_TYPE_EDGE_BOTH) {
-                writel(val | mask, msm_chip->regs.int_edge);
+                msm_gpio_writel(msm_chip, val | mask, MSM_GPIO_INT_EDGE);
                 __irq_set_handler_locked(d->irq, handle_edge_irq);
         } else {
-                writel(val & ~mask, msm_chip->regs.int_edge);
+                msm_gpio_writel(msm_chip, val & ~mask, MSM_GPIO_INT_EDGE);
                 __irq_set_handler_locked(d->irq, handle_level_irq);
         }
         if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
@@ -550,11 +587,12 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
                 msm_gpio_update_both_edge_detect(msm_chip);
         } else {
                 msm_chip->both_edge_detect &= ~mask;
-                val = readl(msm_chip->regs.int_pos);
+                val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_POS);
                 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
-                        writel(val | mask, msm_chip->regs.int_pos);
+                        val |= mask;
                 else
-                        writel(val & ~mask, msm_chip->regs.int_pos);
+                        val &= ~mask;
+                msm_gpio_writel(msm_chip, val, MSM_GPIO_INT_POS);
         }
         spin_unlock_irqrestore(&msm_chip->lock, irq_flags);
         return 0;
@@ -567,7 +605,7 @@ static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
 
         for (i = 0; i < msm_gpio_count; i++) {
                 struct msm_gpio_chip *msm_chip = &msm_gpio_chips[i];
-                val = readl(msm_chip->regs.int_status);
+                val = msm_gpio_readl(msm_chip, MSM_GPIO_INT_STATUS);
                 val &= msm_chip->int_enable[0];
                 while (val) {
                         mask = val & -val;
@@ -592,22 +630,36 @@ static struct irq_chip msm_gpio_irq_chip = {
         .irq_set_type  = msm_gpio_irq_set_type,
 };
 
-static int __init msm_init_gpio(void)
+static int __devinit gpio_msm_v1_probe(struct platform_device *pdev)
 {
         int i, j = 0;
-
-        if (cpu_is_msm7x01()) {
-                msm_gpio_chips = msm_gpio_chips_msm7x01;
-                msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x01);
-        } else if (cpu_is_msm7x30()) {
-                msm_gpio_chips = msm_gpio_chips_msm7x30;
-                msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_msm7x30);
-        } else if (cpu_is_qsd8x50()) {
-                msm_gpio_chips = msm_gpio_chips_qsd8x50;
-                msm_gpio_count = ARRAY_SIZE(msm_gpio_chips_qsd8x50);
-        } else {
-                return 0;
-        }
+        const struct platform_device_id *dev_id = platform_get_device_id(pdev);
+        struct msm_gpio_initdata *data;
+        int irq1, irq2;
+        struct resource *res;
+        void __iomem *base1, __iomem *base2;
+
+        data = (struct msm_gpio_initdata *)dev_id->driver_data;
+        msm_gpio_chips = data->chips;
+        msm_gpio_count = data->count;
+
+        irq1 = platform_get_irq(pdev, 0);
+        if (irq1 < 0)
+                return irq1;
+
+        irq2 = platform_get_irq(pdev, 1);
+        if (irq2 < 0)
+                return irq2;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        base1 = devm_request_and_ioremap(&pdev->dev, res);
+        if (!base1)
+                return -EADDRNOTAVAIL;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        base2 = devm_request_and_ioremap(&pdev->dev, res);
+        if (!base2)
+                return -EADDRNOTAVAIL;
 
         for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) {
                 if (i - FIRST_GPIO_IRQ >=
@@ -621,16 +673,42 @@ static int __init msm_init_gpio(void)
         }
 
         for (i = 0; i < msm_gpio_count; i++) {
+                if (i == 1)
+                        msm_gpio_chips[i].base = base2;
+                else
+                        msm_gpio_chips[i].base = base1;
                 spin_lock_init(&msm_gpio_chips[i].lock);
-                writel(0, msm_gpio_chips[i].regs.int_en);
+                msm_gpio_writel(&msm_gpio_chips[i], 0, MSM_GPIO_INT_EN);
                 gpiochip_add(&msm_gpio_chips[i].chip);
         }
 
-        irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
-        irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
-        irq_set_irq_wake(INT_GPIO_GROUP1, 1);
-        irq_set_irq_wake(INT_GPIO_GROUP2, 2);
+        irq_set_chained_handler(irq1, msm_gpio_irq_handler);
+        irq_set_chained_handler(irq2, msm_gpio_irq_handler);
+        irq_set_irq_wake(irq1, 1);
+        irq_set_irq_wake(irq2, 2);
         return 0;
 }
 
-postcore_initcall(msm_init_gpio);
+static struct platform_device_id gpio_msm_v1_device_ids[] = {
+        { "gpio-msm-7201", (unsigned long)&msm_gpio_7x01_init },
+        { "gpio-msm-7x30", (unsigned long)&msm_gpio_7x30_init },
+        { "gpio-msm-8x50", (unsigned long)&msm_gpio_8x50_init },
+        { }
+};
+MODULE_DEVICE_TABLE(platform, gpio_msm_v1_device_ids);
+
+static struct platform_driver gpio_msm_v1_driver = {
+        .driver = {
+                .name = "gpio-msm-v1",
+                .owner = THIS_MODULE,
+        },
+        .probe = gpio_msm_v1_probe,
+        .id_table = gpio_msm_v1_device_ids,
+};
+
+static int __init gpio_msm_v1_init(void)
+{
+        return platform_driver_register(&gpio_msm_v1_driver);
+}
+postcore_initcall(gpio_msm_v1_init);
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/gpio/gpio-msm-v2.c b/drivers/gpio/gpio-msm-v2.c
index 55a7e7769af6..dd2eddeb1e0c 100644
--- a/drivers/gpio/gpio-msm-v2.c
+++ b/drivers/gpio/gpio-msm-v2.c
@@ -23,13 +23,12 @@
 #include <linux/init.h>
 #include <linux/interrupt.h>
 #include <linux/io.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/irq.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 
-#include <asm/mach/irq.h>
-
 #include <mach/msm_gpiomux.h>
 #include <mach/msm_iomap.h>
 
diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c
index 7877335c4cc8..7176743915d3 100644
--- a/drivers/gpio/gpio-mxc.c
+++ b/drivers/gpio/gpio-mxc.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_device.h>
 #include <linux/slab.h>
@@ -32,7 +33,6 @@
 #include <linux/of_device.h>
 #include <linux/module.h>
 #include <asm-generic/bug.h>
-#include <asm/mach/irq.h>
 
 enum mxc_gpio_hwtype {
         IMX1_GPIO,      /* runs on i.mx1 */
diff --git a/drivers/gpio/gpio-omap.c b/drivers/gpio/gpio-omap.c
index 159f5c57eb45..a612ea1c53cb 100644
--- a/drivers/gpio/gpio-omap.c
+++ b/drivers/gpio/gpio-omap.c
@@ -25,11 +25,10 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/gpio.h>
 #include <linux/platform_data/gpio-omap.h>
 
-#include <asm/mach/irq.h>
-
 #define OFF_MODE        1
 
 static LIST_HEAD(omap_gpio_list);
diff --git a/drivers/gpio/gpio-pl061.c b/drivers/gpio/gpio-pl061.c
index d7008dfdd6f0..6a4bd0dae0ce 100644
--- a/drivers/gpio/gpio-pl061.c
+++ b/drivers/gpio/gpio-pl061.c
@@ -16,6 +16,7 @@
 #include <linux/ioport.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/bitops.h>
 #include <linux/workqueue.h>
 #include <linux/gpio.h>
@@ -25,7 +26,6 @@
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pm.h>
-#include <asm/mach/irq.h>
 
 #define GPIODIR 0x400
 #define GPIOIS  0x404
diff --git a/drivers/gpio/gpio-pxa.c b/drivers/gpio/gpio-pxa.c
index 8325f580c0f1..2d3af981641e 100644
--- a/drivers/gpio/gpio-pxa.c
+++ b/drivers/gpio/gpio-pxa.c
@@ -19,6 +19,7 @@
 #include <linux/init.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/of.h>
 #include <linux/of_device.h>
@@ -26,8 +27,6 @@
 #include <linux/syscore_ops.h>
 #include <linux/slab.h>
 
-#include <asm/mach/irq.h>
-
 #include <mach/irqs.h>
 
 /*
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c
index 414ad912232f..8e2155548888 100644
--- a/drivers/gpio/gpio-tegra.c
+++ b/drivers/gpio/gpio-tegra.c
@@ -27,11 +27,10 @@
 #include <linux/platform_device.h>
 #include <linux/module.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pm.h>
 
-#include <asm/mach/irq.h>
-
 #define GPIO_BANK(x)            ((x) >> 5)
 #define GPIO_PORT(x)            (((x) >> 3) & 0x3)
 #define GPIO_BIT(x)             ((x) & 0x7)
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 98e3b87bdf1b..d5e119ca9425 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -2,9 +2,10 @@ obj-$(CONFIG_IRQCHIP)			+= irqchip.o
 
 obj-$(CONFIG_ARCH_BCM2835)              += irq-bcm2835.o
 obj-$(CONFIG_ARCH_EXYNOS)               += exynos-combiner.o
+obj-$(CONFIG_ARCH_MXS)                  += irq-mxs.o
 obj-$(CONFIG_METAG)                     += irq-metag-ext.o
 obj-$(CONFIG_METAG_PERFCOUNTER_IRQS)    += irq-metag.o
-obj-$(CONFIG_ARCH_SUNXI)                += irq-sunxi.o
+obj-$(CONFIG_ARCH_SUNXI)                += irq-sun4i.o
 obj-$(CONFIG_ARCH_SPEAR3XX)             += spear-shirq.o
 obj-$(CONFIG_ARM_GIC)                   += irq-gic.o
 obj-$(CONFIG_ARM_VIC)                   += irq-vic.o
diff --git a/drivers/irqchip/exynos-combiner.c b/drivers/irqchip/exynos-combiner.c
index 04d86a9803f4..6a5201351507 100644
--- a/drivers/irqchip/exynos-combiner.c
+++ b/drivers/irqchip/exynos-combiner.c
@@ -13,6 +13,7 @@
 #include <linux/init.h>
 #include <linux/io.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/of_address.h>
 #include <linux/of_irq.h>
 #include <asm/mach/irq.h>
diff --git a/drivers/irqchip/irq-gic.c b/drivers/irqchip/irq-gic.c
index fc6aebf1e4b2..1760ceb68b7b 100644
--- a/drivers/irqchip/irq-gic.c
+++ b/drivers/irqchip/irq-gic.c
@@ -28,6 +28,7 @@
 #include <linux/module.h>
 #include <linux/list.h>
 #include <linux/smp.h>
+#include <linux/cpu.h>
 #include <linux/cpu_pm.h>
 #include <linux/cpumask.h>
 #include <linux/io.h>
@@ -38,12 +39,12 @@
 #include <linux/interrupt.h>
 #include <linux/percpu.h>
 #include <linux/slab.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/irqchip/arm-gic.h>
 
 #include <asm/irq.h>
 #include <asm/exception.h>
 #include <asm/smp_plat.h>
-#include <asm/mach/irq.h>
 
 #include "irqchip.h"
 
@@ -127,7 +128,7 @@ static inline void gic_set_base_accessor(struct gic_chip_data *data,
 #else
 #define gic_data_dist_base(d)   ((d)->dist_base.common_base)
 #define gic_data_cpu_base(d)    ((d)->cpu_base.common_base)
-#define gic_set_base_accessor(d,f)
+#define gic_set_base_accessor(d, f)
 #endif
 
 static inline void __iomem *gic_dist_base(struct irq_data *d)
@@ -324,7 +325,7 @@ static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
 
         cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
         if (unlikely(gic_irq < 32 || gic_irq > 1020))
-                do_bad_IRQ(cascade_irq, desc);
+                handle_bad_irq(cascade_irq, desc);
         else
                 generic_handle_irq(cascade_irq);
 
@@ -700,6 +701,25 @@ static int gic_irq_domain_xlate(struct irq_domain *d,
         return 0;
 }
 
+#ifdef CONFIG_SMP
+static int __cpuinit gic_secondary_init(struct notifier_block *nfb,
+                                        unsigned long action, void *hcpu)
+{
+        if (action == CPU_STARTING)
+                gic_cpu_init(&gic_data[0]);
+        return NOTIFY_OK;
+}
+
+/*
+ * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
+ * priority because the GIC needs to be up before the ARM generic timers.
+ */
+static struct notifier_block __cpuinitdata gic_cpu_notifier = {
+        .notifier_call = gic_secondary_init,
+        .priority = 100,
+};
+#endif
+
 const struct irq_domain_ops gic_irq_domain_ops = {
         .map = gic_irq_domain_map,
         .xlate = gic_irq_domain_xlate,
@@ -790,6 +810,7 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
 
 #ifdef CONFIG_SMP
         set_smp_cross_call(gic_raise_softirq);
+        register_cpu_notifier(&gic_cpu_notifier);
 #endif
 
         set_handle_irq(gic_handle_irq);
@@ -800,15 +821,8 @@ void __init gic_init_bases(unsigned int gic_nr, int irq_start,
         gic_pm_init(gic);
 }
 
-void __cpuinit gic_secondary_init(unsigned int gic_nr)
-{
-        BUG_ON(gic_nr >= MAX_GIC_NR);
-
-        gic_cpu_init(&gic_data[gic_nr]);
-}
-
 #ifdef CONFIG_OF
-static int gic_cnt __initdata = 0;
+static int gic_cnt __initdata;
 
 int __init gic_of_init(struct device_node *node, struct device_node *parent)
 {
diff --git a/arch/arm/mach-mxs/icoll.c b/drivers/irqchip/irq-mxs.c
index e26eeba46598..29889bbdcc6d 100644
--- a/arch/arm/mach-mxs/icoll.c
+++ b/drivers/irqchip/irq-mxs.c
@@ -22,10 +22,12 @@
 #include <linux/irqdomain.h>
 #include <linux/io.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_irq.h>
+#include <linux/stmp_device.h>
 #include <asm/exception.h>
-#include <mach/mxs.h>
-#include <mach/common.h>
+
+#include "irqchip.h"
 
 #define HW_ICOLL_VECTOR                         0x0000
 #define HW_ICOLL_LEVELACK                       0x0010
@@ -38,7 +40,7 @@
 
 #define ICOLL_NUM_IRQS          128
 
-static void __iomem *icoll_base = MXS_IO_ADDRESS(MXS_ICOLL_BASE_ADDR);
+static void __iomem *icoll_base;
 static struct irq_domain *icoll_domain;
 
 static void icoll_ack_irq(struct irq_data *d)
@@ -103,23 +105,17 @@ static struct irq_domain_ops icoll_irq_domain_ops = {
 static void __init icoll_of_init(struct device_node *np,
                           struct device_node *interrupt_parent)
 {
+        icoll_base = of_iomap(np, 0);
+        WARN_ON(!icoll_base);
+
         /*
          * Interrupt Collector reset, which initializes the priority
          * for each irq to level 0.
          */
-        mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
+        stmp_reset_block(icoll_base + HW_ICOLL_CTRL);
 
         icoll_domain = irq_domain_add_linear(np, ICOLL_NUM_IRQS,
                                              &icoll_irq_domain_ops, NULL);
         WARN_ON(!icoll_domain);
 }
-
-static const struct of_device_id icoll_of_match[] __initconst = {
-        {.compatible = "fsl,icoll", .data = icoll_of_init},
-        { /* sentinel */ }
-};
-
-void __init icoll_init_irq(void)
-{
-        of_irq_init(icoll_of_match);
-}
+IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init);
diff --git a/drivers/irqchip/irq-sun4i.c b/drivers/irqchip/irq-sun4i.c
new file mode 100644
index 000000000000..b66d4ae06898
--- /dev/null
+++ b/drivers/irqchip/irq-sun4i.c
@@ -0,0 +1,149 @@
+/*
+ * Allwinner A1X SoCs IRQ chip driver.
+ *
+ * Copyright (C) 2012 Maxime Ripard
+ *
+ * Maxime Ripard <maxime.ripard@free-electrons.com>
+ *
+ * Based on code from
+ * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
+ * Benn Huang <benn@allwinnertech.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/io.h>
+#include <linux/irq.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+
+#include <asm/exception.h>
+#include <asm/mach/irq.h>
+
+#include "irqchip.h"
+
+#define SUN4I_IRQ_VECTOR_REG            0x00
+#define SUN4I_IRQ_PROTECTION_REG        0x08
+#define SUN4I_IRQ_NMI_CTRL_REG          0x0c
+#define SUN4I_IRQ_PENDING_REG(x)        (0x10 + 0x4 * x)
+#define SUN4I_IRQ_FIQ_PENDING_REG(x)    (0x20 + 0x4 * x)
+#define SUN4I_IRQ_ENABLE_REG(x)         (0x40 + 0x4 * x)
+#define SUN4I_IRQ_MASK_REG(x)           (0x50 + 0x4 * x)
+
+static void __iomem *sun4i_irq_base;
+static struct irq_domain *sun4i_irq_domain;
+
+static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs);
+
+void sun4i_irq_ack(struct irq_data *irqd)
+{
+        unsigned int irq = irqd_to_hwirq(irqd);
+        unsigned int irq_off = irq % 32;
+        int reg = irq / 32;
+        u32 val;
+
+        val = readl(sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
+        writel(val | (1 << irq_off),
+               sun4i_irq_base + SUN4I_IRQ_PENDING_REG(reg));
+}
+
+static void sun4i_irq_mask(struct irq_data *irqd)
+{
+        unsigned int irq = irqd_to_hwirq(irqd);
+        unsigned int irq_off = irq % 32;
+        int reg = irq / 32;
+        u32 val;
+
+        val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+        writel(val & ~(1 << irq_off),
+               sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+}
+
+static void sun4i_irq_unmask(struct irq_data *irqd)
+{
+        unsigned int irq = irqd_to_hwirq(irqd);
+        unsigned int irq_off = irq % 32;
+        int reg = irq / 32;
+        u32 val;
+
+        val = readl(sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+        writel(val | (1 << irq_off),
+               sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(reg));
+}
+
+static struct irq_chip sun4i_irq_chip = {
+        .name           = "sun4i_irq",
+        .irq_ack        = sun4i_irq_ack,
+        .irq_mask       = sun4i_irq_mask,
+        .irq_unmask     = sun4i_irq_unmask,
+};
+
+static int sun4i_irq_map(struct irq_domain *d, unsigned int virq,
+                         irq_hw_number_t hw)
+{
+        irq_set_chip_and_handler(virq, &sun4i_irq_chip,
+                                 handle_level_irq);
+        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
+
+        return 0;
+}
+
+static struct irq_domain_ops sun4i_irq_ops = {
+        .map = sun4i_irq_map,
+        .xlate = irq_domain_xlate_onecell,
+};
+
+static int __init sun4i_of_init(struct device_node *node,
+                                struct device_node *parent)
+{
+        sun4i_irq_base = of_iomap(node, 0);
+        if (!sun4i_irq_base)
+                panic("%s: unable to map IC registers\n",
+                        node->full_name);
+
+        /* Disable all interrupts */
+        writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(0));
+        writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(1));
+        writel(0, sun4i_irq_base + SUN4I_IRQ_ENABLE_REG(2));
+
+        /* Mask all the interrupts */
+        writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(0));
+        writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(1));
+        writel(0, sun4i_irq_base + SUN4I_IRQ_MASK_REG(2));
+
+        /* Clear all the pending interrupts */
+        writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(0));
+        writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(1));
+        writel(0xffffffff, sun4i_irq_base + SUN4I_IRQ_PENDING_REG(2));
+
+        /* Enable protection mode */
+        writel(0x01, sun4i_irq_base + SUN4I_IRQ_PROTECTION_REG);
+
+        /* Configure the external interrupt source type */
+        writel(0x00, sun4i_irq_base + SUN4I_IRQ_NMI_CTRL_REG);
+
+        sun4i_irq_domain = irq_domain_add_linear(node, 3 * 32,
+                                                 &sun4i_irq_ops, NULL);
+        if (!sun4i_irq_domain)
+                panic("%s: unable to create IRQ domain\n", node->full_name);
+
+        set_handle_irq(sun4i_handle_irq);
+
+        return 0;
+}
+IRQCHIP_DECLARE(allwinner_sun4i_ic, "allwinner,sun4i-ic", sun4i_of_init);
+
+static asmlinkage void __exception_irq_entry sun4i_handle_irq(struct pt_regs *regs)
+{
+        u32 irq, hwirq;
+
+        hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
+        while (hwirq != 0) {
+                irq = irq_find_mapping(sun4i_irq_domain, hwirq);
+                handle_IRQ(irq, regs);
+                hwirq = readl(sun4i_irq_base + SUN4I_IRQ_VECTOR_REG) >> 2;
+        }
+}
diff --git a/drivers/irqchip/irq-sunxi.c b/drivers/irqchip/irq-sunxi.c
deleted file mode 100644
index 10974fa42653..000000000000
--- a/drivers/irqchip/irq-sunxi.c
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Allwinner A1X SoCs IRQ chip driver.
- *
- * Copyright (C) 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * Based on code from
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Benn Huang <benn@allwinnertech.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#include <linux/io.h>
-#include <linux/irq.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-#include <linux/of_irq.h>
-
-#include <linux/irqchip/sunxi.h>
-
-#define SUNXI_IRQ_VECTOR_REG            0x00
-#define SUNXI_IRQ_PROTECTION_REG        0x08
-#define SUNXI_IRQ_NMI_CTRL_REG          0x0c
-#define SUNXI_IRQ_PENDING_REG(x)        (0x10 + 0x4 * x)
-#define SUNXI_IRQ_FIQ_PENDING_REG(x)    (0x20 + 0x4 * x)
-#define SUNXI_IRQ_ENABLE_REG(x)         (0x40 + 0x4 * x)
-#define SUNXI_IRQ_MASK_REG(x)           (0x50 + 0x4 * x)
-
-static void __iomem *sunxi_irq_base;
-static struct irq_domain *sunxi_irq_domain;
-
-void sunxi_irq_ack(struct irq_data *irqd)
-{
-        unsigned int irq = irqd_to_hwirq(irqd);
-        unsigned int irq_off = irq % 32;
-        int reg = irq / 32;
-        u32 val;
-
-        val = readl(sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
-        writel(val | (1 << irq_off),
-               sunxi_irq_base + SUNXI_IRQ_PENDING_REG(reg));
-}
-
-static void sunxi_irq_mask(struct irq_data *irqd)
-{
-        unsigned int irq = irqd_to_hwirq(irqd);
-        unsigned int irq_off = irq % 32;
-        int reg = irq / 32;
-        u32 val;
-
-        val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
-        writel(val & ~(1 << irq_off),
-               sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
-}
-
-static void sunxi_irq_unmask(struct irq_data *irqd)
-{
-        unsigned int irq = irqd_to_hwirq(irqd);
-        unsigned int irq_off = irq % 32;
-        int reg = irq / 32;
-        u32 val;
-
-        val = readl(sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
-        writel(val | (1 << irq_off),
-               sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(reg));
-}
-
-static struct irq_chip sunxi_irq_chip = {
-        .name           = "sunxi_irq",
-        .irq_ack        = sunxi_irq_ack,
-        .irq_mask       = sunxi_irq_mask,
-        .irq_unmask     = sunxi_irq_unmask,
-};
-
-static int sunxi_irq_map(struct irq_domain *d, unsigned int virq,
-                         irq_hw_number_t hw)
-{
-        irq_set_chip_and_handler(virq, &sunxi_irq_chip,
-                                 handle_level_irq);
-        set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);
-
-        return 0;
-}
-
-static struct irq_domain_ops sunxi_irq_ops = {
-        .map = sunxi_irq_map,
-        .xlate = irq_domain_xlate_onecell,
-};
-
-static int __init sunxi_of_init(struct device_node *node,
-                                struct device_node *parent)
-{
-        sunxi_irq_base = of_iomap(node, 0);
-        if (!sunxi_irq_base)
-                panic("%s: unable to map IC registers\n",
-                        node->full_name);
-
-        /* Disable all interrupts */
-        writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(0));
-        writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(1));
-        writel(0, sunxi_irq_base + SUNXI_IRQ_ENABLE_REG(2));
-
-        /* Mask all the interrupts */
-        writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(0));
-        writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(1));
-        writel(0, sunxi_irq_base + SUNXI_IRQ_MASK_REG(2));
-
-        /* Clear all the pending interrupts */
-        writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(0));
-        writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(1));
-        writel(0xffffffff, sunxi_irq_base + SUNXI_IRQ_PENDING_REG(2));
-
-        /* Enable protection mode */
-        writel(0x01, sunxi_irq_base + SUNXI_IRQ_PROTECTION_REG);
-
-        /* Configure the external interrupt source type */
-        writel(0x00, sunxi_irq_base + SUNXI_IRQ_NMI_CTRL_REG);
-
-        sunxi_irq_domain = irq_domain_add_linear(node, 3 * 32,
-                                                 &sunxi_irq_ops, NULL);
-        if (!sunxi_irq_domain)
-                panic("%s: unable to create IRQ domain\n", node->full_name);
-
-        return 0;
-}
-
-static struct of_device_id sunxi_irq_dt_ids[] __initconst = {
-        { .compatible = "allwinner,sunxi-ic", .data = sunxi_of_init },
-        { }
-};
-
-void __init sunxi_init_irq(void)
-{
-        of_irq_init(sunxi_irq_dt_ids);
-}
-
-asmlinkage void __exception_irq_entry sunxi_handle_irq(struct pt_regs *regs)
-{
-        u32 irq, hwirq;
-
-        hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
-        while (hwirq != 0) {
-                irq = irq_find_mapping(sunxi_irq_domain, hwirq);
-                handle_IRQ(irq, regs);
-                hwirq = readl(sunxi_irq_base + SUNXI_IRQ_VECTOR_REG) >> 2;
-        }
-}
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 3cf97aaebe40..884d11c7355f 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -23,6 +23,7 @@
 #include <linux/init.h>
 #include <linux/list.h>
 #include <linux/io.h>
+#include <linux/irq.h>
 #include <linux/irqdomain.h>
 #include <linux/of.h>
 #include <linux/of_address.h>
@@ -33,7 +34,7 @@
 #include <linux/irqchip/arm-vic.h>
 
 #include <asm/exception.h>
-#include <asm/mach/irq.h>
+#include <asm/irq.h>
 
 #include "irqchip.h"
 
diff --git a/drivers/mmc/host/msm_sdcc.c b/drivers/mmc/host/msm_sdcc.c
index 7c0af0e80047..0ee4a57fe6b2 100644
--- a/drivers/mmc/host/msm_sdcc.c
+++ b/drivers/mmc/host/msm_sdcc.c
@@ -43,7 +43,6 @@
 #include <asm/sizes.h>
 
 #include <linux/platform_data/mmc-msm_sdcc.h>
-#include <mach/msm_iomap.h>
 #include <mach/dma.h>
 #include <mach/clk.h>
 
diff --git a/drivers/mmc/host/s3cmci.c b/drivers/mmc/host/s3cmci.c
index 63fb265e0da6..8d6794cdf899 100644
--- a/drivers/mmc/host/s3cmci.c
+++ b/drivers/mmc/host/s3cmci.c
@@ -25,14 +25,93 @@
 
 #include <mach/dma.h>
 
-#include <mach/regs-sdi.h>
-
 #include <linux/platform_data/mmc-s3cmci.h>
 
 #include "s3cmci.h"
 
 #define DRIVER_NAME "s3c-mci"
 
+#define S3C2410_SDICON                  (0x00)
+#define S3C2410_SDIPRE                  (0x04)
+#define S3C2410_SDICMDARG               (0x08)
+#define S3C2410_SDICMDCON               (0x0C)
+#define S3C2410_SDICMDSTAT              (0x10)
+#define S3C2410_SDIRSP0                 (0x14)
+#define S3C2410_SDIRSP1                 (0x18)
+#define S3C2410_SDIRSP2                 (0x1C)
+#define S3C2410_SDIRSP3                 (0x20)
+#define S3C2410_SDITIMER                (0x24)
+#define S3C2410_SDIBSIZE                (0x28)
+#define S3C2410_SDIDCON                 (0x2C)
+#define S3C2410_SDIDCNT                 (0x30)
+#define S3C2410_SDIDSTA                 (0x34)
+#define S3C2410_SDIFSTA                 (0x38)
+
+#define S3C2410_SDIDATA                 (0x3C)
+#define S3C2410_SDIIMSK                 (0x40)
+
+#define S3C2440_SDIDATA                 (0x40)
+#define S3C2440_SDIIMSK                 (0x3C)
+
+#define S3C2440_SDICON_SDRESET          (1 << 8)
+#define S3C2410_SDICON_SDIOIRQ          (1 << 3)
+#define S3C2410_SDICON_FIFORESET        (1 << 1)
+#define S3C2410_SDICON_CLOCKTYPE        (1 << 0)
+
+#define S3C2410_SDICMDCON_LONGRSP       (1 << 10)
+#define S3C2410_SDICMDCON_WAITRSP       (1 << 9)
+#define S3C2410_SDICMDCON_CMDSTART      (1 << 8)
+#define S3C2410_SDICMDCON_SENDERHOST    (1 << 6)
+#define S3C2410_SDICMDCON_INDEX         (0x3f)
+
+#define S3C2410_SDICMDSTAT_CRCFAIL      (1 << 12)
+#define S3C2410_SDICMDSTAT_CMDSENT      (1 << 11)
+#define S3C2410_SDICMDSTAT_CMDTIMEOUT   (1 << 10)
+#define S3C2410_SDICMDSTAT_RSPFIN       (1 << 9)
+
+#define S3C2440_SDIDCON_DS_WORD         (2 << 22)
+#define S3C2410_SDIDCON_TXAFTERRESP     (1 << 20)
+#define S3C2410_SDIDCON_RXAFTERCMD      (1 << 19)
+#define S3C2410_SDIDCON_BLOCKMODE       (1 << 17)
+#define S3C2410_SDIDCON_WIDEBUS         (1 << 16)
+#define S3C2410_SDIDCON_DMAEN           (1 << 15)
+#define S3C2410_SDIDCON_STOP            (1 << 14)
+#define S3C2440_SDIDCON_DATSTART        (1 << 14)
+
+#define S3C2410_SDIDCON_XFER_RXSTART    (2 << 12)
+#define S3C2410_SDIDCON_XFER_TXSTART    (3 << 12)
+
+#define S3C2410_SDIDCON_BLKNUM_MASK     (0xFFF)
+
+#define S3C2410_SDIDSTA_SDIOIRQDETECT   (1 << 9)
+#define S3C2410_SDIDSTA_FIFOFAIL        (1 << 8)
+#define S3C2410_SDIDSTA_CRCFAIL         (1 << 7)
+#define S3C2410_SDIDSTA_RXCRCFAIL       (1 << 6)
+#define S3C2410_SDIDSTA_DATATIMEOUT     (1 << 5)
+#define S3C2410_SDIDSTA_XFERFINISH      (1 << 4)
+#define S3C2410_SDIDSTA_TXDATAON        (1 << 1)
+#define S3C2410_SDIDSTA_RXDATAON        (1 << 0)
+
+#define S3C2440_SDIFSTA_FIFORESET       (1 << 16)
+#define S3C2440_SDIFSTA_FIFOFAIL        (3 << 14)
+#define S3C2410_SDIFSTA_TFDET           (1 << 13)
+#define S3C2410_SDIFSTA_RFDET           (1 << 12)
+#define S3C2410_SDIFSTA_COUNTMASK       (0x7f)
+
+#define S3C2410_SDIIMSK_RESPONSECRC     (1 << 17)
+#define S3C2410_SDIIMSK_CMDSENT         (1 << 16)
+#define S3C2410_SDIIMSK_CMDTIMEOUT      (1 << 15)
+#define S3C2410_SDIIMSK_RESPONSEND      (1 << 14)
+#define S3C2410_SDIIMSK_SDIOIRQ         (1 << 12)
+#define S3C2410_SDIIMSK_FIFOFAIL        (1 << 11)
+#define S3C2410_SDIIMSK_CRCSTATUS       (1 << 10)
+#define S3C2410_SDIIMSK_DATACRC         (1 << 9)
+#define S3C2410_SDIIMSK_DATATIMEOUT     (1 << 8)
+#define S3C2410_SDIIMSK_DATAFINISH      (1 << 7)
+#define S3C2410_SDIIMSK_TXFIFOHALF      (1 << 4)
+#define S3C2410_SDIIMSK_RXFIFOLAST      (1 << 2)
+#define S3C2410_SDIIMSK_RXFIFOHALF      (1 << 0)
+
 enum dbg_channels {
         dbg_err   = (1 << 0),
         dbg_debug = (1 << 1),
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 4d7f531e945d..5d7529ed5392 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -18,6 +18,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/io.h>
 #include <linux/gpio.h>
 #include <linux/pinctrl/machine.h>
@@ -27,8 +28,6 @@
 /* Since we request GPIOs from ourself */
 #include <linux/pinctrl/consumer.h>
 
-#include <asm/mach/irq.h>
-
 #include <mach/hardware.h>
 #include <mach/at91_pio.h>
 
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index 8b10b1ac9071..ec1567842a7e 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -23,14 +23,13 @@
 #include <linux/interrupt.h>
 #include <linux/irqdomain.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/of_irq.h>
 #include <linux/io.h>
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 #include <linux/err.h>
 
-#include <asm/mach/irq.h>
-
 #include "pinctrl-samsung.h"
 #include "pinctrl-exynos.h"
 
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 435bf3078d2c..34281754b629 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -23,6 +23,7 @@
 #include <linux/interrupt.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/slab.h>
 #include <linux/of_device.h>
 #include <linux/of_address.h>
@@ -33,7 +34,6 @@
 /* Since we request GPIOs from ourself */
 #include <linux/pinctrl/consumer.h>
 #include <linux/platform_data/pinctrl-nomadik.h>
-#include <asm/mach/irq.h>
 #include "pinctrl-nomadik.h"
 #include "core.h"
 
diff --git a/drivers/pinctrl/pinctrl-sirf.c b/drivers/pinctrl/pinctrl-sirf.c
index fb9062570745..1ed23d02011e 100644
--- a/drivers/pinctrl/pinctrl-sirf.c
+++ b/drivers/pinctrl/pinctrl-sirf.c
@@ -14,6 +14,7 @@
 #include <linux/slab.h>
 #include <linux/err.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/pinctrl/pinctrl.h>
 #include <linux/pinctrl/pinmux.h>
 #include <linux/pinctrl/consumer.h>
@@ -25,7 +26,6 @@
 #include <linux/bitops.h>
 #include <linux/gpio.h>
 #include <linux/of_gpio.h>
-#include <asm/mach/irq.h>
 
 #define DRIVER_NAME "pinmux-sirf"
 
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index 295b349a05cf..a4908ecd74fb 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -15,12 +15,12 @@
 #include <linux/io.h>
 #include <linux/irq.h>
 #include <linux/irqdomain.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/module.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/platform_device.h>
 #include <linux/pm.h>
 #include <linux/spinlock.h>
-#include <asm/mach/irq.h>
 
 #define MAX_GPIO_PER_REG                32
 #define PIN_OFFSET(pin)                 (pin % MAX_GPIO_PER_REG)
diff --git a/drivers/rtc/rtc-stmp3xxx.c b/drivers/rtc/rtc-stmp3xxx.c
index a9cd26a26dc0..483ce086990b 100644
--- a/drivers/rtc/rtc-stmp3xxx.c
+++ b/drivers/rtc/rtc-stmp3xxx.c
@@ -30,8 +30,6 @@
 #include <linux/stmp_device.h>
 #include <linux/stmp3xxx_rtc_wdt.h>
 
-#include <mach/common.h>
-
 #define STMP3XXX_RTC_CTRL                       0x0
 #define STMP3XXX_RTC_CTRL_SET                   0x4
 #define STMP3XXX_RTC_CTRL_CLR                   0x8
@@ -264,7 +262,7 @@ static int stmp3xxx_rtc_probe(struct platform_device *pdev)
 
         platform_set_drvdata(pdev, rtc_data);
 
-        mxs_reset_block(rtc_data->io);
+        stmp_reset_block(rtc_data->io);
         writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
                         STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
                         STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
@@ -307,7 +305,7 @@ static int stmp3xxx_rtc_resume(struct device *dev)
 {
         struct stmp3xxx_rtc_data *rtc_data = dev_get_drvdata(dev);
 
-        mxs_reset_block(rtc_data->io);
+        stmp_reset_block(rtc_data->io);
         writel(STMP3XXX_RTC_PERSISTENT0_ALARM_EN |
                         STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE_EN |
                         STMP3XXX_RTC_PERSISTENT0_ALARM_WAKE,
diff --git a/drivers/staging/iio/adc/mxs-lradc.c b/drivers/staging/iio/adc/mxs-lradc.c
index 6044e1717b20..2856b8fd44ad 100644
--- a/drivers/staging/iio/adc/mxs-lradc.c
+++ b/drivers/staging/iio/adc/mxs-lradc.c
@@ -36,9 +36,6 @@
 #include <linux/delay.h>
 #include <linux/input.h>
 
-#include <mach/mxs.h>
-#include <mach/common.h>
-
 #include <linux/iio/iio.h>
 #include <linux/iio/buffer.h>
 #include <linux/iio/trigger.h>
diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-common.c b/drivers/staging/imx-drm/ipu-v3/ipu-common.c
index 055b99db50ff..0880ef1a01ba 100644
--- a/drivers/staging/imx-drm/ipu-v3/ipu-common.c
+++ b/drivers/staging/imx-drm/ipu-v3/ipu-common.c
@@ -25,8 +25,8 @@
 #include <linux/clk.h>
 #include <linux/list.h>
 #include <linux/irq.h>
+#include <linux/irqchip/chained_irq.h>
 #include <linux/of_device.h>
-#include <asm/mach/irq.h>
 
 #include "imx-ipu-v3.h"
 #include "ipu-prv.h"
diff --git a/drivers/usb/host/ohci-exynos.c b/drivers/usb/host/ohci-exynos.c
index 114583a8e92b..07592c00af26 100644
--- a/drivers/usb/host/ohci-exynos.c
+++ b/drivers/usb/host/ohci-exynos.c
@@ -14,7 +14,7 @@
 #include <linux/clk.h>
 #include <linux/of.h>
 #include <linux/platform_device.h>
-#include <linux/platform_data/usb-exynos.h>
+#include <linux/platform_data/usb-ohci-exynos.h>
 #include <linux/usb/phy.h>
 #include <linux/usb/samsung_usb_phy.h>
 
diff --git a/include/linux/clk/mxs.h b/include/linux/clk/mxs.h
new file mode 100644
index 000000000000..90c30dc3efc7
--- /dev/null
+++ b/include/linux/clk/mxs.h
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_CLK_MXS_H
+#define __LINUX_CLK_MXS_H
+
+int mx23_clocks_init(void);
+int mx28_clocks_init(void);
+int mxs_saif_clkmux_select(unsigned int clkmux);
+
+#endif
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
index aa7032c7238f..7279b94c01da 100644
--- a/include/linux/clocksource.h
+++ b/include/linux/clocksource.h
@@ -333,15 +333,23 @@ extern int clocksource_mmio_init(void __iomem *, const char *,
 
 extern int clocksource_i8253_init(void);
 
+struct device_node;
+typedef void(*clocksource_of_init_fn)(struct device_node *);
 #ifdef CONFIG_CLKSRC_OF
 extern void clocksource_of_init(void);
 
 #define CLOCKSOURCE_OF_DECLARE(name, compat, fn)                        \
         static const struct of_device_id __clksrc_of_table_##name       \
                 __used __section(__clksrc_of_table)                     \
-                 = { .compatible = compat, .data = fn };
+                 = { .compatible = compat,                              \
+                     .data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn }
 #else
-#define CLOCKSOURCE_OF_DECLARE(name, compat, fn)
+static inline void clocksource_of_init(void) {}
+#define CLOCKSOURCE_OF_DECLARE(name, compat, fn)                        \
+        static const struct of_device_id __clksrc_of_table_##name       \
+                __attribute__((unused))                                 \
+                 = { .compatible = compat,                              \
+                     .data = (fn == (clocksource_of_init_fn)NULL) ? fn : fn }
 #endif
 
 #endif /* _LINUX_CLOCKSOURCE_H */
diff --git a/include/linux/irqchip/arm-gic.h b/include/linux/irqchip/arm-gic.h
index 3fd8e4290a1c..3e203eb23cc7 100644
--- a/include/linux/irqchip/arm-gic.h
+++ b/include/linux/irqchip/arm-gic.h
@@ -65,7 +65,6 @@ extern struct irq_chip gic_arch_extn;
 
 void gic_init_bases(unsigned int, int, void __iomem *, void __iomem *,
                     u32 offset, struct device_node *);
-void gic_secondary_init(unsigned int);
 void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
 
 static inline void gic_init(unsigned int nr, int start,
diff --git a/include/linux/irqchip/chained_irq.h b/include/linux/irqchip/chained_irq.h
new file mode 100644
index 000000000000..adf4c30f3af6
--- /dev/null
+++ b/include/linux/irqchip/chained_irq.h
@@ -0,0 +1,52 @@
+/*
+ * Chained IRQ handlers support.
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef __IRQCHIP_CHAINED_IRQ_H
+#define __IRQCHIP_CHAINED_IRQ_H
+
+#include <linux/irq.h>
+
+/*
+ * Entry/exit functions for chained handlers where the primary IRQ chip
+ * may implement either fasteoi or level-trigger flow control.
+ */
+static inline void chained_irq_enter(struct irq_chip *chip,
+                                     struct irq_desc *desc)
+{
+        /* FastEOI controllers require no action on entry. */
+        if (chip->irq_eoi)
+                return;
+
+        if (chip->irq_mask_ack) {
+                chip->irq_mask_ack(&desc->irq_data);
+        } else {
+                chip->irq_mask(&desc->irq_data);
+                if (chip->irq_ack)
+                        chip->irq_ack(&desc->irq_data);
+        }
+}
+
+static inline void chained_irq_exit(struct irq_chip *chip,
+                                    struct irq_desc *desc)
+{
+        if (chip->irq_eoi)
+                chip->irq_eoi(&desc->irq_data);
+        else
+                chip->irq_unmask(&desc->irq_data);
+}
+
+#endif /* __IRQCHIP_CHAINED_IRQ_H */
diff --git a/arch/arm/mach-h720x/include/mach/timex.h b/include/linux/irqchip/mxs.h
index 3f2f447ff36b..9039a538a919 100644
--- a/arch/arm/mach-h720x/include/mach/timex.h
+++ b/include/linux/irqchip/mxs.h
@@ -1,15 +1,14 @@
 /*
- * arch/arm/mach-h720x/include/mach/timex.h
- * Copyright (C) 2000 Jungjun Kim, Hynix Semiconductor Inc.
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
 
-#ifndef __ASM_ARCH_TIMEX
-#define __ASM_ARCH_TIMEX
+#ifndef __LINUX_IRQCHIP_MXS_H
+#define __LINUX_IRQCHIP_MXS_H
 
-#define CLOCK_TICK_RATE         3686400
+extern void icoll_handle_irq(struct pt_regs *);
 
 #endif
diff --git a/include/linux/irqchip/sunxi.h b/include/linux/irqchip/sunxi.h
deleted file mode 100644
index 1fe2c2260e2b..000000000000
--- a/include/linux/irqchip/sunxi.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Copyright 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __LINUX_IRQCHIP_SUNXI_H
-#define __LINUX_IRQCHIP_SUNXI_H
-
-#include <asm/exception.h>
-
-extern void sunxi_init_irq(void);
-
-extern asmlinkage void __exception_irq_entry sunxi_handle_irq(
-        struct pt_regs *regs);
-
-#endif
diff --git a/include/linux/platform_data/usb-exynos.h b/include/linux/platform_data/usb-ohci-exynos.h
index c256c595be5e..c256c595be5e 100644
--- a/include/linux/platform_data/usb-exynos.h
+++ b/include/linux/platform_data/usb-ohci-exynos.h
diff --git a/include/linux/sunxi_timer.h b/include/linux/sunxi_timer.h
deleted file mode 100644
index 18081787e5f3..000000000000
--- a/include/linux/sunxi_timer.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Copyright 2012 Maxime Ripard
- *
- * Maxime Ripard <maxime.ripard@free-electrons.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef __SUNXI_TIMER_H
-#define __SUNXI_TIMER_H
-
-#include <asm/mach/time.h>
-
-void sunxi_timer_init(void);
-
-#endif
diff --git a/sound/soc/mxs/mxs-saif.c b/sound/soc/mxs/mxs-saif.c
index 3a2aa1d19b93..41a6136e3535 100644
--- a/sound/soc/mxs/mxs-saif.c
+++ b/sound/soc/mxs/mxs-saif.c
@@ -33,11 +33,12 @@
 #include <sound/pcm_params.h>
 #include <sound/soc.h>
 #include <asm/mach-types.h>
-#include <mach/hardware.h>
-#include <mach/mxs.h>
 
 #include "mxs-saif.h"
 
+#define MXS_SET_ADDR    0x4
+#define MXS_CLR_ADDR    0x8
+
 static struct mxs_saif *mxs_saif[2];
 
 /*