5 files changed, 43 insertions, 43 deletions

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 88913a47cd34..a69a3d0d3acf 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3754,17 +3754,6 @@ static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
                         continue;
                 }
 
-                if (intel_encoder->type == INTEL_OUTPUT_EDP) {
-                        /* Use VBT settings if we have an eDP panel */
-                        unsigned int edp_bpc = dev_priv->edp.bpp / 3;
-
-                        if (edp_bpc < display_bpc) {
-                                DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
-                                display_bpc = edp_bpc;
-                        }
-                        continue;
-                }
-
                 /* Not one of the known troublemakers, check the EDID */
                 list_for_each_entry(connector, &dev->mode_config.connector_list,
                                     head) {
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 0a56b9ab0f58..a6c426afaa7a 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1174,10 +1174,14 @@ static void ironlake_edp_panel_off(struct intel_dp *intel_dp)
         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
 
         pp = ironlake_get_pp_control(dev_priv);
-        pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_BLC_ENABLE);
+        /* We need to switch off panel power _and_ force vdd, for otherwise some
+         * panels get very unhappy and cease to work. */
+        pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
         I915_WRITE(PCH_PP_CONTROL, pp);
         POSTING_READ(PCH_PP_CONTROL);
 
+        intel_dp->want_panel_vdd = false;
+
         ironlake_wait_panel_off(intel_dp);
 }
 
@@ -1287,11 +1291,9 @@ static void intel_dp_prepare(struct drm_encoder *encoder)
          * ensure that we have vdd while we switch off the panel. */
         ironlake_edp_panel_vdd_on(intel_dp);
         ironlake_edp_backlight_off(intel_dp);
-        ironlake_edp_panel_off(intel_dp);
-
         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
+        ironlake_edp_panel_off(intel_dp);
         intel_dp_link_down(intel_dp);
-        ironlake_edp_panel_vdd_off(intel_dp, false);
 }
 
 static void intel_dp_commit(struct drm_encoder *encoder)
@@ -1326,11 +1328,9 @@ intel_dp_dpms(struct drm_encoder *encoder, int mode)
                 /* Switching the panel off requires vdd. */
                 ironlake_edp_panel_vdd_on(intel_dp);
                 ironlake_edp_backlight_off(intel_dp);
-                ironlake_edp_panel_off(intel_dp);
-
                 intel_dp_sink_dpms(intel_dp, mode);
+                ironlake_edp_panel_off(intel_dp);
                 intel_dp_link_down(intel_dp);
-                ironlake_edp_panel_vdd_off(intel_dp, false);
 
                 if (is_cpu_edp(intel_dp))
                         ironlake_edp_pll_off(encoder);
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index d79500bc1ce5..b9755f6378d8 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -486,9 +486,6 @@ int intel_setup_gmbus(struct drm_device *dev)
                 bus->dev_priv = dev_priv;
 
                 bus->adapter.algo = &gmbus_algorithm;
-                ret = i2c_add_adapter(&bus->adapter);
-                if (ret)
-                        goto err;
 
                 /* By default use a conservative clock rate */
                 bus->reg0 = port | GMBUS_RATE_100KHZ;
@@ -498,6 +495,10 @@ int intel_setup_gmbus(struct drm_device *dev)
                         bus->force_bit = true;
 
                 intel_gpio_setup(bus, port);
+
+                ret = i2c_add_adapter(&bus->adapter);
+                if (ret)
+                        goto err;
         }
 
         intel_i2c_reset(dev_priv->dev);
diff --git a/drivers/gpu/drm/i915/intel_panel.c b/drivers/gpu/drm/i915/intel_panel.c
index 9474488db948..3df4f5fa892a 100644
--- a/drivers/gpu/drm/i915/intel_panel.c
+++ b/drivers/gpu/drm/i915/intel_panel.c
@@ -311,9 +311,6 @@ void intel_panel_enable_backlight(struct drm_device *dev,
         if (dev_priv->backlight_level == 0)
                 dev_priv->backlight_level = intel_panel_get_max_backlight(dev);
 
-        dev_priv->backlight_enabled = true;
-        intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
-
         if (INTEL_INFO(dev)->gen >= 4) {
                 uint32_t reg, tmp;
 
@@ -326,7 +323,7 @@ void intel_panel_enable_backlight(struct drm_device *dev,
                  * we don't track the backlight dpms state, hence check whether
                  * we have to do anything first. */
                 if (tmp & BLM_PWM_ENABLE)
-                        return;
+                        goto set_level;
 
                 if (dev_priv->num_pipe == 3)
                         tmp &= ~BLM_PIPE_SELECT_IVB;
@@ -347,6 +344,14 @@ void intel_panel_enable_backlight(struct drm_device *dev,
                         I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
                 }
         }
+
+set_level:
+        /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
+         * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
+         * registers are set.
+         */
+        dev_priv->backlight_enabled = true;
+        intel_panel_actually_set_backlight(dev, dev_priv->backlight_level);
 }
 
 static void intel_panel_init_backlight(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 414af1e2973b..e2a73b38abe9 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -227,31 +227,36 @@ gen6_render_ring_flush(struct intel_ring_buffer *ring,
          * number of bits based on the write domains has little performance
          * impact.
          */
-        flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
-        flags |= PIPE_CONTROL_TLB_INVALIDATE;
-        flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
-        flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
-        flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
-        /*
-         * Ensure that any following seqno writes only happen when the render
-         * cache is indeed flushed (but only if the caller actually wants that).
-         */
-        if (flush_domains)
+        if (flush_domains) {
+                flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
+                flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
+                /*
+                 * Ensure that any following seqno writes only happen
+                 * when the render cache is indeed flushed.
+                 */
                 flags |= PIPE_CONTROL_CS_STALL;
+        }
+        if (invalidate_domains) {
+                flags |= PIPE_CONTROL_TLB_INVALIDATE;
+                flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
+                flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+                /*
+                 * TLB invalidate requires a post-sync write.
+                 */
+                flags |= PIPE_CONTROL_QW_WRITE;
+        }
 
-        ret = intel_ring_begin(ring, 6);
+        ret = intel_ring_begin(ring, 4);
         if (ret)
                 return ret;
 
-        intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
+        intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
         intel_ring_emit(ring, flags);
         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
-        intel_ring_emit(ring, 0); /* lower dword */
-        intel_ring_emit(ring, 0); /* uppwer dword */
-        intel_ring_emit(ring, MI_NOOP);
+        intel_ring_emit(ring, 0);
         intel_ring_advance(ring);
 
         return 0;