3 files changed, 23 insertions, 8 deletions

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 544675895c8d..b607bbe55261 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -32,8 +32,19 @@
 #define _PIPE3(pipe, a, b, c) ((pipe) == PIPE_A ? (a) : \
                                (pipe) == PIPE_B ? (b) : (c))
 
-#define _MASKED_BIT_ENABLE(a) (((a) << 16) | (a))
-#define _MASKED_BIT_DISABLE(a) ((a) << 16)
+#define _MASKED_FIELD(mask, value) ({                                      \
+        if (__builtin_constant_p(mask))                                    \
+                BUILD_BUG_ON_MSG(((mask) & 0xffff0000), "Incorrect mask"); \
+        if (__builtin_constant_p(value))                                   \
+                BUILD_BUG_ON_MSG((value) & 0xffff0000, "Incorrect value"); \
+        if (__builtin_constant_p(mask) && __builtin_constant_p(value))     \
+                BUILD_BUG_ON_MSG((value) & ~(mask),                        \
+                                 "Incorrect value for mask");              \
+        (mask) << 16 | (value); })
+#define _MASKED_BIT_ENABLE(a)   ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
+#define _MASKED_BIT_DISABLE(a)  (_MASKED_FIELD((a), 0))
+
+
 
 /* PCI config space */
 
@@ -1282,7 +1293,7 @@ enum punit_power_well {
 #define   GEN6_WIZ_HASHING_8x8                          GEN6_WIZ_HASHING(0, 0)
 #define   GEN6_WIZ_HASHING_8x4                          GEN6_WIZ_HASHING(0, 1)
 #define   GEN6_WIZ_HASHING_16x4                         GEN6_WIZ_HASHING(1, 0)
-#define   GEN6_WIZ_HASHING_MASK                         (GEN6_WIZ_HASHING(1, 1) << 16)
+#define   GEN6_WIZ_HASHING_MASK                         GEN6_WIZ_HASHING(1, 1)
 #define   GEN6_TD_FOUR_ROW_DISPATCH_DISABLE             (1 << 5)
 
 #define GFX_MODE        0x02520
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9af0af49382e..1f4b56e273c8 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6508,7 +6508,7 @@ static void gen6_init_clock_gating(struct drm_device *dev)
          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
          */
         I915_WRITE(GEN6_GT_MODE,
-                   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
+                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
 
         ilk_init_lp_watermarks(dev);
 
@@ -6706,7 +6706,7 @@ static void haswell_init_clock_gating(struct drm_device *dev)
          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
          */
         I915_WRITE(GEN7_GT_MODE,
-                   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
+                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
 
         /* WaSwitchSolVfFArbitrationPriority:hsw */
         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
@@ -6803,7 +6803,7 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
          */
         I915_WRITE(GEN7_GT_MODE,
-                   GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
+                   _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
 
         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
         snpcr &= ~GEN6_MBC_SNPCR_MASK;
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 1d01b51ff058..28db934b2359 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -729,6 +729,9 @@ static int wa_add(struct drm_i915_private *dev_priv,
 #define WA_CLR_BIT_MASKED(addr, mask) \
         WA_REG(addr, _MASKED_BIT_DISABLE(mask), (mask) & 0xffff)
 
+#define WA_SET_FIELD_MASKED(addr, mask, value) \
+        WA_REG(addr, _MASKED_FIELD(mask, value), mask)
+
 #define WA_SET_BIT(addr, mask) WA_REG(addr, I915_READ(addr) | (mask), mask)
 #define WA_CLR_BIT(addr, mask) WA_REG(addr, I915_READ(addr) & ~(mask), mask)
 
@@ -773,8 +776,9 @@ static int bdw_init_workarounds(struct intel_engine_cs *ring)
          * disable bit, which we don't touch here, but it's good
          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
          */
-        WA_SET_BIT_MASKED(GEN7_GT_MODE,
-                          GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4);
+        WA_SET_FIELD_MASKED(GEN7_GT_MODE,
+                            GEN6_WIZ_HASHING_MASK,
+                            GEN6_WIZ_HASHING_16x4);
 
         return 0;
 }