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-rw-r--r--Documentation/devicetree/bindings/clock/imx23-clock.txt2
-rw-r--r--Documentation/devicetree/bindings/clock/imx28-clock.txt4
-rw-r--r--MAINTAINERS1
-rw-r--r--arch/arm/include/asm/hardware/sp810.h2
-rw-r--r--arch/arm/mach-integrator/impd1.c69
-rw-r--r--arch/arm/mach-ux500/cpu-db8500.c6
-rw-r--r--drivers/clk/Kconfig16
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/clk-bcm2835.c8
-rw-r--r--drivers/clk/clk-fixed-rate.c2
-rw-r--r--drivers/clk/clk-prima2.c84
-rw-r--r--drivers/clk/clk-twl6040.c126
-rw-r--r--drivers/clk/clk-vt8500.c18
-rw-r--r--drivers/clk/clk-wm831x.c34
-rw-r--r--drivers/clk/clk.c154
-rw-r--r--drivers/clk/mxs/clk-imx23.c6
-rw-r--r--drivers/clk/mxs/clk-imx28.c10
-rw-r--r--drivers/clk/spear/clk-aux-synth.c3
-rw-r--r--drivers/clk/spear/clk-vco-pll.c2
-rw-r--r--drivers/clk/spear/clk.c3
-rw-r--r--drivers/clk/spear/spear1310_clock.c106
-rw-r--r--drivers/clk/spear/spear1340_clock.c237
-rw-r--r--drivers/clk/spear/spear3xx_clock.c154
-rw-r--r--drivers/clk/spear/spear6xx_clock.c13
-rw-r--r--drivers/clk/ux500/Makefile3
-rw-r--r--drivers/clk/ux500/abx500-clk.c73
-rw-r--r--drivers/clk/ux500/clk-prcmu.c72
-rw-r--r--drivers/clk/ux500/clk.h12
-rw-r--r--drivers/clk/ux500/u8500_clk.c28
-rw-r--r--drivers/clk/versatile/Makefile3
-rw-r--r--drivers/clk/versatile/clk-icst.c66
-rw-r--r--drivers/clk/versatile/clk-icst.h14
-rw-r--r--drivers/clk/versatile/clk-impd1.c97
-rw-r--r--drivers/clk/versatile/clk-integrator.c55
-rw-r--r--drivers/clk/versatile/clk-realview.c65
-rw-r--r--drivers/clk/versatile/clk-vexpress-osc.c146
-rw-r--r--drivers/clk/versatile/clk-vexpress.c142
-rw-r--r--drivers/cpufreq/db8500-cpufreq.c101
-rw-r--r--drivers/mfd/db8500-prcmu.c86
-rw-r--r--include/linux/clk-provider.h24
-rw-r--r--include/linux/mfd/db8500-prcmu.h4
-rw-r--r--include/linux/mfd/dbx500-prcmu.h10
-rw-r--r--include/linux/platform_data/clk-integrator.h2
43 files changed, 1491 insertions, 573 deletions
diff --git a/Documentation/devicetree/bindings/clock/imx23-clock.txt b/Documentation/devicetree/bindings/clock/imx23-clock.txt
index a0b867ef8d96..baadbb11fe98 100644
--- a/Documentation/devicetree/bindings/clock/imx23-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx23-clock.txt
@@ -52,7 +52,7 @@ clocks and IDs.
52 lcdif 38 52 lcdif 38
53 etm 39 53 etm 39
54 usb 40 54 usb 40
55 usb_pwr 41 55 usb_phy 41
56 56
57Examples: 57Examples:
58 58
diff --git a/Documentation/devicetree/bindings/clock/imx28-clock.txt b/Documentation/devicetree/bindings/clock/imx28-clock.txt
index aa2af2866fe8..52a49a4a50b3 100644
--- a/Documentation/devicetree/bindings/clock/imx28-clock.txt
+++ b/Documentation/devicetree/bindings/clock/imx28-clock.txt
@@ -73,8 +73,8 @@ clocks and IDs.
73 can1 59 73 can1 59
74 usb0 60 74 usb0 60
75 usb1 61 75 usb1 61
76 usb0_pwr 62 76 usb0_phy 62
77 usb1_pwr 63 77 usb1_phy 63
78 enet_out 64 78 enet_out 64
79 79
80Examples: 80Examples:
diff --git a/MAINTAINERS b/MAINTAINERS
index d02cdb596d35..cf7ff78f019b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1987,7 +1987,6 @@ F: fs/coda/
1987F: include/linux/coda*.h 1987F: include/linux/coda*.h
1988 1988
1989COMMON CLK FRAMEWORK 1989COMMON CLK FRAMEWORK
1990M: Mike Turquette <mturquette@ti.com>
1991M: Mike Turquette <mturquette@linaro.org> 1990M: Mike Turquette <mturquette@linaro.org>
1992L: linux-arm-kernel@lists.infradead.org (same as CLK API & CLKDEV) 1991L: linux-arm-kernel@lists.infradead.org (same as CLK API & CLKDEV)
1993T: git git://git.linaro.org/people/mturquette/linux.git 1992T: git git://git.linaro.org/people/mturquette/linux.git
diff --git a/arch/arm/include/asm/hardware/sp810.h b/arch/arm/include/asm/hardware/sp810.h
index 6b9b077d86b3..afd7e916472f 100644
--- a/arch/arm/include/asm/hardware/sp810.h
+++ b/arch/arm/include/asm/hardware/sp810.h
@@ -56,6 +56,8 @@
56#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17) 56#define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17)
57#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17) 57#define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17)
58 58
59#define SCCTRL_TIMERENnSEL_SHIFT(n) (15 + ((n) * 2))
60
59static inline void sysctl_soft_reset(void __iomem *base) 61static inline void sysctl_soft_reset(void __iomem *base)
60{ 62{
61 /* switch to slow mode */ 63 /* switch to slow mode */
diff --git a/arch/arm/mach-integrator/impd1.c b/arch/arm/mach-integrator/impd1.c
index e428f3ab15c7..b3d86d7081a0 100644
--- a/arch/arm/mach-integrator/impd1.c
+++ b/arch/arm/mach-integrator/impd1.c
@@ -21,10 +21,9 @@
21#include <linux/amba/bus.h> 21#include <linux/amba/bus.h>
22#include <linux/amba/clcd.h> 22#include <linux/amba/clcd.h>
23#include <linux/io.h> 23#include <linux/io.h>
24#include <linux/platform_data/clk-integrator.h>
24#include <linux/slab.h> 25#include <linux/slab.h>
25#include <linux/clkdev.h>
26 26
27#include <asm/hardware/icst.h>
28#include <mach/lm.h> 27#include <mach/lm.h>
29#include <mach/impd1.h> 28#include <mach/impd1.h>
30#include <asm/sizes.h> 29#include <asm/sizes.h>
@@ -36,45 +35,6 @@ MODULE_PARM_DESC(lmid, "logic module stack position");
36 35
37struct impd1_module { 36struct impd1_module {
38 void __iomem *base; 37 void __iomem *base;
39 struct clk vcos[2];
40 struct clk_lookup *clks[3];
41};
42
43static const struct icst_params impd1_vco_params = {
44 .ref = 24000000, /* 24 MHz */
45 .vco_max = ICST525_VCO_MAX_3V,
46 .vco_min = ICST525_VCO_MIN,
47 .vd_min = 12,
48 .vd_max = 519,
49 .rd_min = 3,
50 .rd_max = 120,
51 .s2div = icst525_s2div,
52 .idx2s = icst525_idx2s,
53};
54
55static void impd1_setvco(struct clk *clk, struct icst_vco vco)
56{
57 struct impd1_module *impd1 = clk->data;
58 u32 val = vco.v | (vco.r << 9) | (vco.s << 16);
59
60 writel(0xa05f, impd1->base + IMPD1_LOCK);
61 writel(val, clk->vcoreg);
62 writel(0, impd1->base + IMPD1_LOCK);
63
64#ifdef DEBUG
65 vco.v = val & 0x1ff;
66 vco.r = (val >> 9) & 0x7f;
67 vco.s = (val >> 16) & 7;
68
69 pr_debug("IM-PD1: VCO%d clock is %ld Hz\n",
70 vconr, icst525_hz(&impd1_vco_params, vco));
71#endif
72}
73
74static const struct clk_ops impd1_clk_ops = {
75 .round = icst_clk_round,
76 .set = icst_clk_set,
77 .setvco = impd1_setvco,
78}; 38};
79 39
80void impd1_tweak_control(struct device *dev, u32 mask, u32 val) 40void impd1_tweak_control(struct device *dev, u32 mask, u32 val)
@@ -344,10 +304,6 @@ static struct impd1_device impd1_devs[] = {
344 } 304 }
345}; 305};
346 306
347static struct clk fixed_14745600 = {
348 .rate = 14745600,
349};
350
351static int impd1_probe(struct lm_device *dev) 307static int impd1_probe(struct lm_device *dev)
352{ 308{
353 struct impd1_module *impd1; 309 struct impd1_module *impd1;
@@ -376,23 +332,7 @@ static int impd1_probe(struct lm_device *dev)
376 printk("IM-PD1 found at 0x%08lx\n", 332 printk("IM-PD1 found at 0x%08lx\n",
377 (unsigned long)dev->resource.start); 333 (unsigned long)dev->resource.start);
378 334
379 for (i = 0; i < ARRAY_SIZE(impd1->vcos); i++) { 335 integrator_impd1_clk_init(impd1->base, dev->id);
380 impd1->vcos[i].ops = &impd1_clk_ops,
381 impd1->vcos[i].owner = THIS_MODULE,
382 impd1->vcos[i].params = &impd1_vco_params,
383 impd1->vcos[i].data = impd1;
384 }
385 impd1->vcos[0].vcoreg = impd1->base + IMPD1_OSC1;
386 impd1->vcos[1].vcoreg = impd1->base + IMPD1_OSC2;
387
388 impd1->clks[0] = clkdev_alloc(&impd1->vcos[0], NULL, "lm%x:01000",
389 dev->id);
390 impd1->clks[1] = clkdev_alloc(&fixed_14745600, NULL, "lm%x:00100",
391 dev->id);
392 impd1->clks[2] = clkdev_alloc(&fixed_14745600, NULL, "lm%x:00200",
393 dev->id);
394 for (i = 0; i < ARRAY_SIZE(impd1->clks); i++)
395 clkdev_add(impd1->clks[i]);
396 336
397 for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) { 337 for (i = 0; i < ARRAY_SIZE(impd1_devs); i++) {
398 struct impd1_device *idev = impd1_devs + i; 338 struct impd1_device *idev = impd1_devs + i;
@@ -431,12 +371,9 @@ static int impd1_remove_one(struct device *dev, void *data)
431static void impd1_remove(struct lm_device *dev) 371static void impd1_remove(struct lm_device *dev)
432{ 372{
433 struct impd1_module *impd1 = lm_get_drvdata(dev); 373 struct impd1_module *impd1 = lm_get_drvdata(dev);
434 int i;
435 374
436 device_for_each_child(&dev->dev, NULL, impd1_remove_one); 375 device_for_each_child(&dev->dev, NULL, impd1_remove_one);
437 376 integrator_impd1_clk_exit(dev->id);
438 for (i = 0; i < ARRAY_SIZE(impd1->clks); i++)
439 clkdev_drop(impd1->clks[i]);
440 377
441 lm_set_drvdata(dev, NULL); 378 lm_set_drvdata(dev, NULL);
442 379
diff --git a/arch/arm/mach-ux500/cpu-db8500.c b/arch/arm/mach-ux500/cpu-db8500.c
index 113d9c47a842..91f028c1264a 100644
--- a/arch/arm/mach-ux500/cpu-db8500.c
+++ b/arch/arm/mach-ux500/cpu-db8500.c
@@ -214,9 +214,6 @@ struct device * __init u8500_init_devices(struct ab8500_platform_data *ab8500)
214 db8500_add_gpios(parent); 214 db8500_add_gpios(parent);
215 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 215 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
216 216
217 platform_device_register_data(parent,
218 "cpufreq-u8500", -1, NULL, 0);
219
220 for (i = 0; i < ARRAY_SIZE(platform_devs); i++) 217 for (i = 0; i < ARRAY_SIZE(platform_devs); i++)
221 platform_devs[i]->dev.parent = parent; 218 platform_devs[i]->dev.parent = parent;
222 219
@@ -236,9 +233,6 @@ struct device * __init u8500_of_init_devices(void)
236 233
237 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg); 234 db8500_add_usb(parent, usb_db8500_rx_dma_cfg, usb_db8500_tx_dma_cfg);
238 235
239 platform_device_register_data(parent,
240 "cpufreq-u8500", -1, NULL, 0);
241
242 u8500_dma40_device.dev.parent = parent; 236 u8500_dma40_device.dev.parent = parent;
243 237
244 /* 238 /*
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index bace9e98f75d..823f62d900ba 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -42,10 +42,12 @@ config COMMON_CLK_WM831X
42 42
43config COMMON_CLK_VERSATILE 43config COMMON_CLK_VERSATILE
44 bool "Clock driver for ARM Reference designs" 44 bool "Clock driver for ARM Reference designs"
45 depends on ARCH_INTEGRATOR || ARCH_REALVIEW 45 depends on ARCH_INTEGRATOR || ARCH_REALVIEW || ARCH_VEXPRESS
46 ---help--- 46 ---help---
47 Supports clocking on ARM Reference designs Integrator/AP, 47 Supports clocking on ARM Reference designs:
48 Integrator/CP, RealView PB1176, EB, PB11MP and PBX. 48 - Integrator/AP and Integrator/CP
49 - RealView PB1176, EB, PB11MP and PBX
50 - Versatile Express
49 51
50config COMMON_CLK_MAX77686 52config COMMON_CLK_MAX77686
51 tristate "Clock driver for Maxim 77686 MFD" 53 tristate "Clock driver for Maxim 77686 MFD"
@@ -53,4 +55,12 @@ config COMMON_CLK_MAX77686
53 ---help--- 55 ---help---
54 This driver supports Maxim 77686 crystal oscillator clock. 56 This driver supports Maxim 77686 crystal oscillator clock.
55 57
58config CLK_TWL6040
59 tristate "External McPDM functional clock from twl6040"
60 depends on TWL6040_CORE
61 ---help---
62 Enable the external functional clock support on OMAP4+ platforms for
63 McPDM. McPDM module is using the external bit clock on the McPDM bus
64 as functional clock.
65
56endmenu 66endmenu
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 71a25b91de00..2701235d5757 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -23,3 +23,4 @@ obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
23# Chip specific 23# Chip specific
24obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o 24obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
25obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o 25obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
26obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
diff --git a/drivers/clk/clk-bcm2835.c b/drivers/clk/clk-bcm2835.c
index 67ad16b20b81..b61ee2c5af84 100644
--- a/drivers/clk/clk-bcm2835.c
+++ b/drivers/clk/clk-bcm2835.c
@@ -33,17 +33,17 @@ void __init bcm2835_init_clocks(void)
33 33
34 clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT, 34 clk = clk_register_fixed_rate(NULL, "sys_pclk", NULL, CLK_IS_ROOT,
35 250000000); 35 250000000);
36 if (!clk) 36 if (IS_ERR(clk))
37 pr_err("sys_pclk not registered\n"); 37 pr_err("sys_pclk not registered\n");
38 38
39 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 39 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT,
40 126000000); 40 126000000);
41 if (!clk) 41 if (IS_ERR(clk))
42 pr_err("apb_pclk not registered\n"); 42 pr_err("apb_pclk not registered\n");
43 43
44 clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT, 44 clk = clk_register_fixed_rate(NULL, "uart0_pclk", NULL, CLK_IS_ROOT,
45 3000000); 45 3000000);
46 if (!clk) 46 if (IS_ERR(clk))
47 pr_err("uart0_pclk not registered\n"); 47 pr_err("uart0_pclk not registered\n");
48 ret = clk_register_clkdev(clk, NULL, "20201000.uart"); 48 ret = clk_register_clkdev(clk, NULL, "20201000.uart");
49 if (ret) 49 if (ret)
@@ -51,7 +51,7 @@ void __init bcm2835_init_clocks(void)
51 51
52 clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT, 52 clk = clk_register_fixed_rate(NULL, "uart1_pclk", NULL, CLK_IS_ROOT,
53 125000000); 53 125000000);
54 if (!clk) 54 if (IS_ERR(clk))
55 pr_err("uart1_pclk not registered\n"); 55 pr_err("uart1_pclk not registered\n");
56 ret = clk_register_clkdev(clk, NULL, "20215000.uart"); 56 ret = clk_register_clkdev(clk, NULL, "20215000.uart");
57 if (ret) 57 if (ret)
diff --git a/drivers/clk/clk-fixed-rate.c b/drivers/clk/clk-fixed-rate.c
index f5ec0eebd4d7..af78ed6b67ef 100644
--- a/drivers/clk/clk-fixed-rate.c
+++ b/drivers/clk/clk-fixed-rate.c
@@ -97,7 +97,7 @@ void __init of_fixed_clk_setup(struct device_node *node)
97 of_property_read_string(node, "clock-output-names", &clk_name); 97 of_property_read_string(node, "clock-output-names", &clk_name);
98 98
99 clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate); 99 clk = clk_register_fixed_rate(NULL, clk_name, NULL, CLK_IS_ROOT, rate);
100 if (clk) 100 if (!IS_ERR(clk))
101 of_clk_add_provider(node, of_clk_src_simple_get, clk); 101 of_clk_add_provider(node, of_clk_src_simple_get, clk);
102} 102}
103EXPORT_SYMBOL_GPL(of_fixed_clk_setup); 103EXPORT_SYMBOL_GPL(of_fixed_clk_setup);
diff --git a/drivers/clk/clk-prima2.c b/drivers/clk/clk-prima2.c
index 517874fa6858..a203ecccdc4f 100644
--- a/drivers/clk/clk-prima2.c
+++ b/drivers/clk/clk-prima2.c
@@ -1054,118 +1054,118 @@ void __init sirfsoc_of_clk_init(void)
1054 /* These are always available (RTC and 26MHz OSC)*/ 1054 /* These are always available (RTC and 26MHz OSC)*/
1055 clk = clk_register_fixed_rate(NULL, "rtc", NULL, 1055 clk = clk_register_fixed_rate(NULL, "rtc", NULL,
1056 CLK_IS_ROOT, 32768); 1056 CLK_IS_ROOT, 32768);
1057 BUG_ON(!clk); 1057 BUG_ON(IS_ERR(clk));
1058 clk = clk_register_fixed_rate(NULL, "osc", NULL, 1058 clk = clk_register_fixed_rate(NULL, "osc", NULL,
1059 CLK_IS_ROOT, 26000000); 1059 CLK_IS_ROOT, 26000000);
1060 BUG_ON(!clk); 1060 BUG_ON(IS_ERR(clk));
1061 1061
1062 clk = clk_register(NULL, &clk_pll1.hw); 1062 clk = clk_register(NULL, &clk_pll1.hw);
1063 BUG_ON(!clk); 1063 BUG_ON(IS_ERR(clk));
1064 clk = clk_register(NULL, &clk_pll2.hw); 1064 clk = clk_register(NULL, &clk_pll2.hw);
1065 BUG_ON(!clk); 1065 BUG_ON(IS_ERR(clk));
1066 clk = clk_register(NULL, &clk_pll3.hw); 1066 clk = clk_register(NULL, &clk_pll3.hw);
1067 BUG_ON(!clk); 1067 BUG_ON(IS_ERR(clk));
1068 clk = clk_register(NULL, &clk_mem.hw); 1068 clk = clk_register(NULL, &clk_mem.hw);
1069 BUG_ON(!clk); 1069 BUG_ON(IS_ERR(clk));
1070 clk = clk_register(NULL, &clk_sys.hw); 1070 clk = clk_register(NULL, &clk_sys.hw);
1071 BUG_ON(!clk); 1071 BUG_ON(IS_ERR(clk));
1072 clk = clk_register(NULL, &clk_security.hw); 1072 clk = clk_register(NULL, &clk_security.hw);
1073 BUG_ON(!clk); 1073 BUG_ON(IS_ERR(clk));
1074 clk_register_clkdev(clk, NULL, "b8030000.security"); 1074 clk_register_clkdev(clk, NULL, "b8030000.security");
1075 clk = clk_register(NULL, &clk_dsp.hw); 1075 clk = clk_register(NULL, &clk_dsp.hw);
1076 BUG_ON(!clk); 1076 BUG_ON(IS_ERR(clk));
1077 clk = clk_register(NULL, &clk_gps.hw); 1077 clk = clk_register(NULL, &clk_gps.hw);
1078 BUG_ON(!clk); 1078 BUG_ON(IS_ERR(clk));
1079 clk_register_clkdev(clk, NULL, "a8010000.gps"); 1079 clk_register_clkdev(clk, NULL, "a8010000.gps");
1080 clk = clk_register(NULL, &clk_mf.hw); 1080 clk = clk_register(NULL, &clk_mf.hw);
1081 BUG_ON(!clk); 1081 BUG_ON(IS_ERR(clk));
1082 clk = clk_register(NULL, &clk_io.hw); 1082 clk = clk_register(NULL, &clk_io.hw);
1083 BUG_ON(!clk); 1083 BUG_ON(IS_ERR(clk));
1084 clk_register_clkdev(clk, NULL, "io"); 1084 clk_register_clkdev(clk, NULL, "io");
1085 clk = clk_register(NULL, &clk_cpu.hw); 1085 clk = clk_register(NULL, &clk_cpu.hw);
1086 BUG_ON(!clk); 1086 BUG_ON(IS_ERR(clk));
1087 clk_register_clkdev(clk, NULL, "cpu"); 1087 clk_register_clkdev(clk, NULL, "cpu");
1088 clk = clk_register(NULL, &clk_uart0.hw); 1088 clk = clk_register(NULL, &clk_uart0.hw);
1089 BUG_ON(!clk); 1089 BUG_ON(IS_ERR(clk));
1090 clk_register_clkdev(clk, NULL, "b0050000.uart"); 1090 clk_register_clkdev(clk, NULL, "b0050000.uart");
1091 clk = clk_register(NULL, &clk_uart1.hw); 1091 clk = clk_register(NULL, &clk_uart1.hw);
1092 BUG_ON(!clk); 1092 BUG_ON(IS_ERR(clk));
1093 clk_register_clkdev(clk, NULL, "b0060000.uart"); 1093 clk_register_clkdev(clk, NULL, "b0060000.uart");
1094 clk = clk_register(NULL, &clk_uart2.hw); 1094 clk = clk_register(NULL, &clk_uart2.hw);
1095 BUG_ON(!clk); 1095 BUG_ON(IS_ERR(clk));
1096 clk_register_clkdev(clk, NULL, "b0070000.uart"); 1096 clk_register_clkdev(clk, NULL, "b0070000.uart");
1097 clk = clk_register(NULL, &clk_tsc.hw); 1097 clk = clk_register(NULL, &clk_tsc.hw);
1098 BUG_ON(!clk); 1098 BUG_ON(IS_ERR(clk));
1099 clk_register_clkdev(clk, NULL, "b0110000.tsc"); 1099 clk_register_clkdev(clk, NULL, "b0110000.tsc");
1100 clk = clk_register(NULL, &clk_i2c0.hw); 1100 clk = clk_register(NULL, &clk_i2c0.hw);
1101 BUG_ON(!clk); 1101 BUG_ON(IS_ERR(clk));
1102 clk_register_clkdev(clk, NULL, "b00e0000.i2c"); 1102 clk_register_clkdev(clk, NULL, "b00e0000.i2c");
1103 clk = clk_register(NULL, &clk_i2c1.hw); 1103 clk = clk_register(NULL, &clk_i2c1.hw);
1104 BUG_ON(!clk); 1104 BUG_ON(IS_ERR(clk));
1105 clk_register_clkdev(clk, NULL, "b00f0000.i2c"); 1105 clk_register_clkdev(clk, NULL, "b00f0000.i2c");
1106 clk = clk_register(NULL, &clk_spi0.hw); 1106 clk = clk_register(NULL, &clk_spi0.hw);
1107 BUG_ON(!clk); 1107 BUG_ON(IS_ERR(clk));
1108 clk_register_clkdev(clk, NULL, "b00d0000.spi"); 1108 clk_register_clkdev(clk, NULL, "b00d0000.spi");
1109 clk = clk_register(NULL, &clk_spi1.hw); 1109 clk = clk_register(NULL, &clk_spi1.hw);
1110 BUG_ON(!clk); 1110 BUG_ON(IS_ERR(clk));
1111 clk_register_clkdev(clk, NULL, "b0170000.spi"); 1111 clk_register_clkdev(clk, NULL, "b0170000.spi");
1112 clk = clk_register(NULL, &clk_pwmc.hw); 1112 clk = clk_register(NULL, &clk_pwmc.hw);
1113 BUG_ON(!clk); 1113 BUG_ON(IS_ERR(clk));
1114 clk_register_clkdev(clk, NULL, "b0130000.pwm"); 1114 clk_register_clkdev(clk, NULL, "b0130000.pwm");
1115 clk = clk_register(NULL, &clk_efuse.hw); 1115 clk = clk_register(NULL, &clk_efuse.hw);
1116 BUG_ON(!clk); 1116 BUG_ON(IS_ERR(clk));
1117 clk_register_clkdev(clk, NULL, "b0140000.efusesys"); 1117 clk_register_clkdev(clk, NULL, "b0140000.efusesys");
1118 clk = clk_register(NULL, &clk_pulse.hw); 1118 clk = clk_register(NULL, &clk_pulse.hw);
1119 BUG_ON(!clk); 1119 BUG_ON(IS_ERR(clk));
1120 clk_register_clkdev(clk, NULL, "b0150000.pulsec"); 1120 clk_register_clkdev(clk, NULL, "b0150000.pulsec");
1121 clk = clk_register(NULL, &clk_dmac0.hw); 1121 clk = clk_register(NULL, &clk_dmac0.hw);
1122 BUG_ON(!clk); 1122 BUG_ON(IS_ERR(clk));
1123 clk_register_clkdev(clk, NULL, "b00b0000.dma-controller"); 1123 clk_register_clkdev(clk, NULL, "b00b0000.dma-controller");
1124 clk = clk_register(NULL, &clk_dmac1.hw); 1124 clk = clk_register(NULL, &clk_dmac1.hw);
1125 BUG_ON(!clk); 1125 BUG_ON(IS_ERR(clk));
1126 clk_register_clkdev(clk, NULL, "b0160000.dma-controller"); 1126 clk_register_clkdev(clk, NULL, "b0160000.dma-controller");
1127 clk = clk_register(NULL, &clk_nand.hw); 1127 clk = clk_register(NULL, &clk_nand.hw);
1128 BUG_ON(!clk); 1128 BUG_ON(IS_ERR(clk));
1129 clk_register_clkdev(clk, NULL, "b0030000.nand"); 1129 clk_register_clkdev(clk, NULL, "b0030000.nand");
1130 clk = clk_register(NULL, &clk_audio.hw); 1130 clk = clk_register(NULL, &clk_audio.hw);
1131 BUG_ON(!clk); 1131 BUG_ON(IS_ERR(clk));
1132 clk_register_clkdev(clk, NULL, "b0040000.audio"); 1132 clk_register_clkdev(clk, NULL, "b0040000.audio");
1133 clk = clk_register(NULL, &clk_usp0.hw); 1133 clk = clk_register(NULL, &clk_usp0.hw);
1134 BUG_ON(!clk); 1134 BUG_ON(IS_ERR(clk));
1135 clk_register_clkdev(clk, NULL, "b0080000.usp"); 1135 clk_register_clkdev(clk, NULL, "b0080000.usp");
1136 clk = clk_register(NULL, &clk_usp1.hw); 1136 clk = clk_register(NULL, &clk_usp1.hw);
1137 BUG_ON(!clk); 1137 BUG_ON(IS_ERR(clk));
1138 clk_register_clkdev(clk, NULL, "b0090000.usp"); 1138 clk_register_clkdev(clk, NULL, "b0090000.usp");
1139 clk = clk_register(NULL, &clk_usp2.hw); 1139 clk = clk_register(NULL, &clk_usp2.hw);
1140 BUG_ON(!clk); 1140 BUG_ON(IS_ERR(clk));
1141 clk_register_clkdev(clk, NULL, "b00a0000.usp"); 1141 clk_register_clkdev(clk, NULL, "b00a0000.usp");
1142 clk = clk_register(NULL, &clk_vip.hw); 1142 clk = clk_register(NULL, &clk_vip.hw);
1143 BUG_ON(!clk); 1143 BUG_ON(IS_ERR(clk));
1144 clk_register_clkdev(clk, NULL, "b00c0000.vip"); 1144 clk_register_clkdev(clk, NULL, "b00c0000.vip");
1145 clk = clk_register(NULL, &clk_gfx.hw); 1145 clk = clk_register(NULL, &clk_gfx.hw);
1146 BUG_ON(!clk); 1146 BUG_ON(IS_ERR(clk));
1147 clk_register_clkdev(clk, NULL, "98000000.graphics"); 1147 clk_register_clkdev(clk, NULL, "98000000.graphics");
1148 clk = clk_register(NULL, &clk_mm.hw); 1148 clk = clk_register(NULL, &clk_mm.hw);
1149 BUG_ON(!clk); 1149 BUG_ON(IS_ERR(clk));
1150 clk_register_clkdev(clk, NULL, "a0000000.multimedia"); 1150 clk_register_clkdev(clk, NULL, "a0000000.multimedia");
1151 clk = clk_register(NULL, &clk_lcd.hw); 1151 clk = clk_register(NULL, &clk_lcd.hw);
1152 BUG_ON(!clk); 1152 BUG_ON(IS_ERR(clk));
1153 clk_register_clkdev(clk, NULL, "90010000.display"); 1153 clk_register_clkdev(clk, NULL, "90010000.display");
1154 clk = clk_register(NULL, &clk_vpp.hw); 1154 clk = clk_register(NULL, &clk_vpp.hw);
1155 BUG_ON(!clk); 1155 BUG_ON(IS_ERR(clk));
1156 clk_register_clkdev(clk, NULL, "90020000.vpp"); 1156 clk_register_clkdev(clk, NULL, "90020000.vpp");
1157 clk = clk_register(NULL, &clk_mmc01.hw); 1157 clk = clk_register(NULL, &clk_mmc01.hw);
1158 BUG_ON(!clk); 1158 BUG_ON(IS_ERR(clk));
1159 clk = clk_register(NULL, &clk_mmc23.hw); 1159 clk = clk_register(NULL, &clk_mmc23.hw);
1160 BUG_ON(!clk); 1160 BUG_ON(IS_ERR(clk));
1161 clk = clk_register(NULL, &clk_mmc45.hw); 1161 clk = clk_register(NULL, &clk_mmc45.hw);
1162 BUG_ON(!clk); 1162 BUG_ON(IS_ERR(clk));
1163 clk = clk_register(NULL, &usb_pll_clk_hw); 1163 clk = clk_register(NULL, &usb_pll_clk_hw);
1164 BUG_ON(!clk); 1164 BUG_ON(IS_ERR(clk));
1165 clk = clk_register(NULL, &clk_usb0.hw); 1165 clk = clk_register(NULL, &clk_usb0.hw);
1166 BUG_ON(!clk); 1166 BUG_ON(IS_ERR(clk));
1167 clk_register_clkdev(clk, NULL, "b00e0000.usb"); 1167 clk_register_clkdev(clk, NULL, "b00e0000.usb");
1168 clk = clk_register(NULL, &clk_usb1.hw); 1168 clk = clk_register(NULL, &clk_usb1.hw);
1169 BUG_ON(!clk); 1169 BUG_ON(IS_ERR(clk));
1170 clk_register_clkdev(clk, NULL, "b00f0000.usb"); 1170 clk_register_clkdev(clk, NULL, "b00f0000.usb");
1171} 1171}
diff --git a/drivers/clk/clk-twl6040.c b/drivers/clk/clk-twl6040.c
new file mode 100644
index 000000000000..bc1e713e7b9c
--- /dev/null
+++ b/drivers/clk/clk-twl6040.c
@@ -0,0 +1,126 @@
1/*
2* TWL6040 clock module driver for OMAP4 McPDM functional clock
3*
4* Copyright (C) 2012 Texas Instruments Inc.
5* Peter Ujfalusi <peter.ujfalusi@ti.com>
6*
7* This program is free software; you can redistribute it and/or
8* modify it under the terms of the GNU General Public License
9* version 2 as published by the Free Software Foundation.
10*
11* This program is distributed in the hope that it will be useful, but
12* WITHOUT ANY WARRANTY; without even the implied warranty of
13* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14* General Public License for more details.
15*
16* You should have received a copy of the GNU General Public License
17* along with this program; if not, write to the Free Software
18* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
19* 02110-1301 USA
20*
21*/
22
23#include <linux/clk.h>
24#include <linux/module.h>
25#include <linux/slab.h>
26#include <linux/platform_device.h>
27#include <linux/mfd/twl6040.h>
28#include <linux/clk-provider.h>
29
30struct twl6040_clk {
31 struct twl6040 *twl6040;
32 struct device *dev;
33 struct clk_hw mcpdm_fclk;
34 struct clk *clk;
35 int enabled;
36};
37
38static int twl6040_bitclk_is_enabled(struct clk_hw *hw)
39{
40 struct twl6040_clk *twl6040_clk = container_of(hw, struct twl6040_clk,
41 mcpdm_fclk);
42 return twl6040_clk->enabled;
43}
44
45static int twl6040_bitclk_prepare(struct clk_hw *hw)
46{
47 struct twl6040_clk *twl6040_clk = container_of(hw, struct twl6040_clk,
48 mcpdm_fclk);
49 int ret;
50
51 ret = twl6040_power(twl6040_clk->twl6040, 1);
52 if (!ret)
53 twl6040_clk->enabled = 1;
54
55 return ret;
56}
57
58static void twl6040_bitclk_unprepare(struct clk_hw *hw)
59{
60 struct twl6040_clk *twl6040_clk = container_of(hw, struct twl6040_clk,
61 mcpdm_fclk);
62 int ret;
63
64 ret = twl6040_power(twl6040_clk->twl6040, 0);
65 if (!ret)
66 twl6040_clk->enabled = 0;
67}
68
69static const struct clk_ops twl6040_mcpdm_ops = {
70 .is_enabled = twl6040_bitclk_is_enabled,
71 .prepare = twl6040_bitclk_prepare,
72 .unprepare = twl6040_bitclk_unprepare,
73};
74
75static struct clk_init_data wm831x_clkout_init = {
76 .name = "mcpdm_fclk",
77 .ops = &twl6040_mcpdm_ops,
78 .flags = CLK_IS_ROOT,
79};
80
81static int __devinit twl6040_clk_probe(struct platform_device *pdev)
82{
83 struct twl6040 *twl6040 = dev_get_drvdata(pdev->dev.parent);
84 struct twl6040_clk *clkdata;
85
86 clkdata = devm_kzalloc(&pdev->dev, sizeof(*clkdata), GFP_KERNEL);
87 if (!clkdata)
88 return -ENOMEM;
89
90 clkdata->dev = &pdev->dev;
91 clkdata->twl6040 = twl6040;
92
93 clkdata->mcpdm_fclk.init = &wm831x_clkout_init;
94 clkdata->clk = clk_register(&pdev->dev, &clkdata->mcpdm_fclk);
95 if (IS_ERR(clkdata->clk))
96 return PTR_ERR(clkdata->clk);
97
98 dev_set_drvdata(&pdev->dev, clkdata);
99
100 return 0;
101}
102
103static int __devexit twl6040_clk_remove(struct platform_device *pdev)
104{
105 struct twl6040_clk *clkdata = dev_get_drvdata(&pdev->dev);
106
107 clk_unregister(clkdata->clk);
108
109 return 0;
110}
111
112static struct platform_driver twl6040_clk_driver = {
113 .driver = {
114 .name = "twl6040-clk",
115 .owner = THIS_MODULE,
116 },
117 .probe = twl6040_clk_probe,
118 .remove = __devexit_p(twl6040_clk_remove),
119};
120
121module_platform_driver(twl6040_clk_driver);
122
123MODULE_DESCRIPTION("TWL6040 clock driver for McPDM functional clock");
124MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>");
125MODULE_ALIAS("platform:twl6040-clk");
126MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index a885600f5270..fe25570874d6 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -120,8 +120,17 @@ static unsigned long vt8500_dclk_recalc_rate(struct clk_hw *hw,
120static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate, 120static long vt8500_dclk_round_rate(struct clk_hw *hw, unsigned long rate,
121 unsigned long *prate) 121 unsigned long *prate)
122{ 122{
123 struct clk_device *cdev = to_clk_device(hw);
123 u32 divisor = *prate / rate; 124 u32 divisor = *prate / rate;
124 125
126 /*
127 * If this is a request for SDMMC we have to adjust the divisor
128 * when >31 to use the fixed predivisor
129 */
130 if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
131 divisor = 64 * ((divisor / 64) + 1);
132 }
133
125 return *prate / divisor; 134 return *prate / divisor;
126} 135}
127 136
@@ -135,6 +144,15 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
135 if (divisor == cdev->div_mask + 1) 144 if (divisor == cdev->div_mask + 1)
136 divisor = 0; 145 divisor = 0;
137 146
147 /* SDMMC mask may need to be corrected before testing if its valid */
148 if ((cdev->div_mask == 0x3F) && (divisor > 31)) {
149 /*
150 * Bit 5 is a fixed /64 predivisor. If the requested divisor
151 * is >31 then correct for the fixed divisor being required.
152 */
153 divisor = 0x20 + (divisor / 64);
154 }
155
138 if (divisor > cdev->div_mask) { 156 if (divisor > cdev->div_mask) {
139 pr_err("%s: invalid divisor for clock\n", __func__); 157 pr_err("%s: invalid divisor for clock\n", __func__);
140 return -EINVAL; 158 return -EINVAL;
diff --git a/drivers/clk/clk-wm831x.c b/drivers/clk/clk-wm831x.c
index e7b7765e85f3..db4fbf20ffd7 100644
--- a/drivers/clk/clk-wm831x.c
+++ b/drivers/clk/clk-wm831x.c
@@ -370,43 +370,27 @@ static __devinit int wm831x_clk_probe(struct platform_device *pdev)
370 clkdata->xtal_ena = ret & WM831X_XTAL_ENA; 370 clkdata->xtal_ena = ret & WM831X_XTAL_ENA;
371 371
372 clkdata->xtal_hw.init = &wm831x_xtal_init; 372 clkdata->xtal_hw.init = &wm831x_xtal_init;
373 clkdata->xtal = clk_register(&pdev->dev, &clkdata->xtal_hw); 373 clkdata->xtal = devm_clk_register(&pdev->dev, &clkdata->xtal_hw);
374 if (!clkdata->xtal) 374 if (IS_ERR(clkdata->xtal))
375 return -EINVAL; 375 return PTR_ERR(clkdata->xtal);
376 376
377 clkdata->fll_hw.init = &wm831x_fll_init; 377 clkdata->fll_hw.init = &wm831x_fll_init;
378 clkdata->fll = clk_register(&pdev->dev, &clkdata->fll_hw); 378 clkdata->fll = devm_clk_register(&pdev->dev, &clkdata->fll_hw);
379 if (!clkdata->fll) { 379 if (IS_ERR(clkdata->fll))
380 ret = -EINVAL; 380 return PTR_ERR(clkdata->fll);
381 goto err_xtal;
382 }
383 381
384 clkdata->clkout_hw.init = &wm831x_clkout_init; 382 clkdata->clkout_hw.init = &wm831x_clkout_init;
385 clkdata->clkout = clk_register(&pdev->dev, &clkdata->clkout_hw); 383 clkdata->clkout = devm_clk_register(&pdev->dev, &clkdata->clkout_hw);
386 if (!clkdata->clkout) { 384 if (IS_ERR(clkdata->clkout))
387 ret = -EINVAL; 385 return PTR_ERR(clkdata->clkout);
388 goto err_fll;
389 }
390 386
391 dev_set_drvdata(&pdev->dev, clkdata); 387 dev_set_drvdata(&pdev->dev, clkdata);
392 388
393 return 0; 389 return 0;
394
395err_fll:
396 clk_unregister(clkdata->fll);
397err_xtal:
398 clk_unregister(clkdata->xtal);
399 return ret;
400} 390}
401 391
402static int __devexit wm831x_clk_remove(struct platform_device *pdev) 392static int __devexit wm831x_clk_remove(struct platform_device *pdev)
403{ 393{
404 struct wm831x_clk *clkdata = dev_get_drvdata(&pdev->dev);
405
406 clk_unregister(clkdata->clkout);
407 clk_unregister(clkdata->fll);
408 clk_unregister(clkdata->xtal);
409
410 return 0; 394 return 0;
411} 395}
412 396
diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c
index 56e4495ebeb1..251e45d6024d 100644
--- a/drivers/clk/clk.c
+++ b/drivers/clk/clk.c
@@ -17,6 +17,7 @@
17#include <linux/list.h> 17#include <linux/list.h>
18#include <linux/slab.h> 18#include <linux/slab.h>
19#include <linux/of.h> 19#include <linux/of.h>
20#include <linux/device.h>
20 21
21static DEFINE_SPINLOCK(enable_lock); 22static DEFINE_SPINLOCK(enable_lock);
22static DEFINE_MUTEX(prepare_lock); 23static DEFINE_MUTEX(prepare_lock);
@@ -218,8 +219,17 @@ static void clk_disable_unused_subtree(struct clk *clk)
218 if (clk->flags & CLK_IGNORE_UNUSED) 219 if (clk->flags & CLK_IGNORE_UNUSED)
219 goto unlock_out; 220 goto unlock_out;
220 221
221 if (__clk_is_enabled(clk) && clk->ops->disable) 222 /*
222 clk->ops->disable(clk->hw); 223 * some gate clocks have special needs during the disable-unused
224 * sequence. call .disable_unused if available, otherwise fall
225 * back to .disable
226 */
227 if (__clk_is_enabled(clk)) {
228 if (clk->ops->disable_unused)
229 clk->ops->disable_unused(clk->hw);
230 else if (clk->ops->disable)
231 clk->ops->disable(clk->hw);
232 }
223 233
224unlock_out: 234unlock_out:
225 spin_unlock_irqrestore(&enable_lock, flags); 235 spin_unlock_irqrestore(&enable_lock, flags);
@@ -261,7 +271,7 @@ inline struct clk_hw *__clk_get_hw(struct clk *clk)
261 271
262inline u8 __clk_get_num_parents(struct clk *clk) 272inline u8 __clk_get_num_parents(struct clk *clk)
263{ 273{
264 return !clk ? -EINVAL : clk->num_parents; 274 return !clk ? 0 : clk->num_parents;
265} 275}
266 276
267inline struct clk *__clk_get_parent(struct clk *clk) 277inline struct clk *__clk_get_parent(struct clk *clk)
@@ -269,14 +279,14 @@ inline struct clk *__clk_get_parent(struct clk *clk)
269 return !clk ? NULL : clk->parent; 279 return !clk ? NULL : clk->parent;
270} 280}
271 281
272inline int __clk_get_enable_count(struct clk *clk) 282inline unsigned int __clk_get_enable_count(struct clk *clk)
273{ 283{
274 return !clk ? -EINVAL : clk->enable_count; 284 return !clk ? 0 : clk->enable_count;
275} 285}
276 286
277inline int __clk_get_prepare_count(struct clk *clk) 287inline unsigned int __clk_get_prepare_count(struct clk *clk)
278{ 288{
279 return !clk ? -EINVAL : clk->prepare_count; 289 return !clk ? 0 : clk->prepare_count;
280} 290}
281 291
282unsigned long __clk_get_rate(struct clk *clk) 292unsigned long __clk_get_rate(struct clk *clk)
@@ -302,15 +312,15 @@ out:
302 312
303inline unsigned long __clk_get_flags(struct clk *clk) 313inline unsigned long __clk_get_flags(struct clk *clk)
304{ 314{
305 return !clk ? -EINVAL : clk->flags; 315 return !clk ? 0 : clk->flags;
306} 316}
307 317
308int __clk_is_enabled(struct clk *clk) 318bool __clk_is_enabled(struct clk *clk)
309{ 319{
310 int ret; 320 int ret;
311 321
312 if (!clk) 322 if (!clk)
313 return -EINVAL; 323 return false;
314 324
315 /* 325 /*
316 * .is_enabled is only mandatory for clocks that gate 326 * .is_enabled is only mandatory for clocks that gate
@@ -323,7 +333,7 @@ int __clk_is_enabled(struct clk *clk)
323 333
324 ret = clk->ops->is_enabled(clk->hw); 334 ret = clk->ops->is_enabled(clk->hw);
325out: 335out:
326 return ret; 336 return !!ret;
327} 337}
328 338
329static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk) 339static struct clk *__clk_lookup_subtree(const char *name, struct clk *clk)
@@ -568,7 +578,7 @@ unsigned long __clk_round_rate(struct clk *clk, unsigned long rate)
568 unsigned long parent_rate = 0; 578 unsigned long parent_rate = 0;
569 579
570 if (!clk) 580 if (!clk)
571 return -EINVAL; 581 return 0;
572 582
573 if (!clk->ops->round_rate) { 583 if (!clk->ops->round_rate) {
574 if (clk->flags & CLK_SET_RATE_PARENT) 584 if (clk->flags & CLK_SET_RATE_PARENT)
@@ -1297,12 +1307,20 @@ int __clk_init(struct device *dev, struct clk *clk)
1297 * walk the list of orphan clocks and reparent any that are children of 1307 * walk the list of orphan clocks and reparent any that are children of
1298 * this clock 1308 * this clock
1299 */ 1309 */
1300 hlist_for_each_entry_safe(orphan, tmp, tmp2, &clk_orphan_list, child_node) 1310 hlist_for_each_entry_safe(orphan, tmp, tmp2, &clk_orphan_list, child_node) {
1311 if (orphan->ops->get_parent) {
1312 i = orphan->ops->get_parent(orphan->hw);
1313 if (!strcmp(clk->name, orphan->parent_names[i]))
1314 __clk_reparent(orphan, clk);
1315 continue;
1316 }
1317
1301 for (i = 0; i < orphan->num_parents; i++) 1318 for (i = 0; i < orphan->num_parents; i++)
1302 if (!strcmp(clk->name, orphan->parent_names[i])) { 1319 if (!strcmp(clk->name, orphan->parent_names[i])) {
1303 __clk_reparent(orphan, clk); 1320 __clk_reparent(orphan, clk);
1304 break; 1321 break;
1305 } 1322 }
1323 }
1306 1324
1307 /* 1325 /*
1308 * optional platform-specific magic 1326 * optional platform-specific magic
@@ -1361,28 +1379,9 @@ struct clk *__clk_register(struct device *dev, struct clk_hw *hw)
1361} 1379}
1362EXPORT_SYMBOL_GPL(__clk_register); 1380EXPORT_SYMBOL_GPL(__clk_register);
1363 1381
1364/** 1382static int _clk_register(struct device *dev, struct clk_hw *hw, struct clk *clk)
1365 * clk_register - allocate a new clock, register it and return an opaque cookie
1366 * @dev: device that is registering this clock
1367 * @hw: link to hardware-specific clock data
1368 *
1369 * clk_register is the primary interface for populating the clock tree with new
1370 * clock nodes. It returns a pointer to the newly allocated struct clk which
1371 * cannot be dereferenced by driver code but may be used in conjuction with the
1372 * rest of the clock API. In the event of an error clk_register will return an
1373 * error code; drivers must test for an error code after calling clk_register.
1374 */
1375struct clk *clk_register(struct device *dev, struct clk_hw *hw)
1376{ 1383{
1377 int i, ret; 1384 int i, ret;
1378 struct clk *clk;
1379
1380 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
1381 if (!clk) {
1382 pr_err("%s: could not allocate clk\n", __func__);
1383 ret = -ENOMEM;
1384 goto fail_out;
1385 }
1386 1385
1387 clk->name = kstrdup(hw->init->name, GFP_KERNEL); 1386 clk->name = kstrdup(hw->init->name, GFP_KERNEL);
1388 if (!clk->name) { 1387 if (!clk->name) {
@@ -1420,7 +1419,7 @@ struct clk *clk_register(struct device *dev, struct clk_hw *hw)
1420 1419
1421 ret = __clk_init(dev, clk); 1420 ret = __clk_init(dev, clk);
1422 if (!ret) 1421 if (!ret)
1423 return clk; 1422 return 0;
1424 1423
1425fail_parent_names_copy: 1424fail_parent_names_copy:
1426 while (--i >= 0) 1425 while (--i >= 0)
@@ -1429,6 +1428,36 @@ fail_parent_names_copy:
1429fail_parent_names: 1428fail_parent_names:
1430 kfree(clk->name); 1429 kfree(clk->name);
1431fail_name: 1430fail_name:
1431 return ret;
1432}
1433
1434/**
1435 * clk_register - allocate a new clock, register it and return an opaque cookie
1436 * @dev: device that is registering this clock
1437 * @hw: link to hardware-specific clock data
1438 *
1439 * clk_register is the primary interface for populating the clock tree with new
1440 * clock nodes. It returns a pointer to the newly allocated struct clk which
1441 * cannot be dereferenced by driver code but may be used in conjuction with the
1442 * rest of the clock API. In the event of an error clk_register will return an
1443 * error code; drivers must test for an error code after calling clk_register.
1444 */
1445struct clk *clk_register(struct device *dev, struct clk_hw *hw)
1446{
1447 int ret;
1448 struct clk *clk;
1449
1450 clk = kzalloc(sizeof(*clk), GFP_KERNEL);
1451 if (!clk) {
1452 pr_err("%s: could not allocate clk\n", __func__);
1453 ret = -ENOMEM;
1454 goto fail_out;
1455 }
1456
1457 ret = _clk_register(dev, hw, clk);
1458 if (!ret)
1459 return clk;
1460
1432 kfree(clk); 1461 kfree(clk);
1433fail_out: 1462fail_out:
1434 return ERR_PTR(ret); 1463 return ERR_PTR(ret);
@@ -1444,6 +1473,63 @@ EXPORT_SYMBOL_GPL(clk_register);
1444void clk_unregister(struct clk *clk) {} 1473void clk_unregister(struct clk *clk) {}
1445EXPORT_SYMBOL_GPL(clk_unregister); 1474EXPORT_SYMBOL_GPL(clk_unregister);
1446 1475
1476static void devm_clk_release(struct device *dev, void *res)
1477{
1478 clk_unregister(res);
1479}
1480
1481/**
1482 * devm_clk_register - resource managed clk_register()
1483 * @dev: device that is registering this clock
1484 * @hw: link to hardware-specific clock data
1485 *
1486 * Managed clk_register(). Clocks returned from this function are
1487 * automatically clk_unregister()ed on driver detach. See clk_register() for
1488 * more information.
1489 */
1490struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw)
1491{
1492 struct clk *clk;
1493 int ret;
1494
1495 clk = devres_alloc(devm_clk_release, sizeof(*clk), GFP_KERNEL);
1496 if (!clk)
1497 return ERR_PTR(-ENOMEM);
1498
1499 ret = _clk_register(dev, hw, clk);
1500 if (!ret) {
1501 devres_add(dev, clk);
1502 } else {
1503 devres_free(clk);
1504 clk = ERR_PTR(ret);
1505 }
1506
1507 return clk;
1508}
1509EXPORT_SYMBOL_GPL(devm_clk_register);
1510
1511static int devm_clk_match(struct device *dev, void *res, void *data)
1512{
1513 struct clk *c = res;
1514 if (WARN_ON(!c))
1515 return 0;
1516 return c == data;
1517}
1518
1519/**
1520 * devm_clk_unregister - resource managed clk_unregister()
1521 * @clk: clock to unregister
1522 *
1523 * Deallocate a clock allocated with devm_clk_register(). Normally
1524 * this function will not need to be called and the resource management
1525 * code will ensure that the resource is freed.
1526 */
1527void devm_clk_unregister(struct device *dev, struct clk *clk)
1528{
1529 WARN_ON(devres_release(dev, devm_clk_release, devm_clk_match, clk));
1530}
1531EXPORT_SYMBOL_GPL(devm_clk_unregister);
1532
1447/*** clk rate change notifiers ***/ 1533/*** clk rate change notifiers ***/
1448 1534
1449/** 1535/**
diff --git a/drivers/clk/mxs/clk-imx23.c b/drivers/clk/mxs/clk-imx23.c
index f00dffb9ad60..8dd476e2a9c5 100644
--- a/drivers/clk/mxs/clk-imx23.c
+++ b/drivers/clk/mxs/clk-imx23.c
@@ -85,7 +85,7 @@ enum imx23_clk {
85 cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll, 85 cpu_xtal, hbus, xbus, lcdif_div, ssp_div, gpmi_div, emi_pll,
86 emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div, 86 emi_xtal, etm_div, saif_div, clk32k_div, rtc, adc, spdif_div,
87 clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif, 87 clk32k, dri, pwm, filt, uart, ssp, gpmi, spdif, emi, saif,
88 lcdif, etm, usb, usb_pwr, 88 lcdif, etm, usb, usb_phy,
89 clk_max 89 clk_max
90}; 90};
91 91
@@ -143,8 +143,8 @@ int __init mx23_clocks_init(void)
143 clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31); 143 clks[saif] = mxs_clk_gate("saif", "saif_div", SAIF, 31);
144 clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31); 144 clks[lcdif] = mxs_clk_gate("lcdif", "lcdif_div", PIX, 31);
145 clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31); 145 clks[etm] = mxs_clk_gate("etm", "etm_div", ETM, 31);
146 clks[usb] = mxs_clk_gate("usb", "usb_pwr", DIGCTRL, 2); 146 clks[usb] = mxs_clk_gate("usb", "usb_phy", DIGCTRL, 2);
147 clks[usb_pwr] = clk_register_gate(NULL, "usb_pwr", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock); 147 clks[usb_phy] = clk_register_gate(NULL, "usb_phy", "pll", 0, PLLCTRL0, 18, 0, &mxs_lock);
148 148
149 for (i = 0; i < ARRAY_SIZE(clks); i++) 149 for (i = 0; i < ARRAY_SIZE(clks); i++)
150 if (IS_ERR(clks[i])) { 150 if (IS_ERR(clks[i])) {
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index 42978f1b4bd2..db3af0874121 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -140,7 +140,7 @@ enum imx28_clk {
140 emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div, 140 emi_xtal, lcdif_div, etm_div, ptp, saif0_div, saif1_div,
141 clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0, 141 clk32k_div, rtc, lradc, spdif_div, clk32k, pwm, uart, ssp0,
142 ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm, 142 ssp1, ssp2, ssp3, gpmi, spdif, emi, saif0, saif1, lcdif, etm,
143 fec, can0, can1, usb0, usb1, usb0_pwr, usb1_pwr, enet_out, 143 fec, can0, can1, usb0, usb1, usb0_phy, usb1_phy, enet_out,
144 clk_max 144 clk_max
145}; 145};
146 146
@@ -218,10 +218,10 @@ int __init mx28_clocks_init(void)
218 clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30); 218 clks[fec] = mxs_clk_gate("fec", "hbus", ENET, 30);
219 clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30); 219 clks[can0] = mxs_clk_gate("can0", "ref_xtal", FLEXCAN, 30);
220 clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28); 220 clks[can1] = mxs_clk_gate("can1", "ref_xtal", FLEXCAN, 28);
221 clks[usb0] = mxs_clk_gate("usb0", "usb0_pwr", DIGCTRL, 2); 221 clks[usb0] = mxs_clk_gate("usb0", "usb0_phy", DIGCTRL, 2);
222 clks[usb1] = mxs_clk_gate("usb1", "usb1_pwr", DIGCTRL, 16); 222 clks[usb1] = mxs_clk_gate("usb1", "usb1_phy", DIGCTRL, 16);
223 clks[usb0_pwr] = clk_register_gate(NULL, "usb0_pwr", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock); 223 clks[usb0_phy] = clk_register_gate(NULL, "usb0_phy", "pll0", 0, PLL0CTRL0, 18, 0, &mxs_lock);
224 clks[usb1_pwr] = clk_register_gate(NULL, "usb1_pwr", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock); 224 clks[usb1_phy] = clk_register_gate(NULL, "usb1_phy", "pll1", 0, PLL1CTRL0, 18, 0, &mxs_lock);
225 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock); 225 clks[enet_out] = clk_register_gate(NULL, "enet_out", "pll2", 0, ENET, 18, 0, &mxs_lock);
226 226
227 for (i = 0; i < ARRAY_SIZE(clks); i++) 227 for (i = 0; i < ARRAY_SIZE(clks); i++)
diff --git a/drivers/clk/spear/clk-aux-synth.c b/drivers/clk/spear/clk-aux-synth.c
index 6756e7c3bc07..bdfb4421c643 100644
--- a/drivers/clk/spear/clk-aux-synth.c
+++ b/drivers/clk/spear/clk-aux-synth.c
@@ -179,7 +179,8 @@ struct clk *clk_register_aux(const char *aux_name, const char *gate_name,
179 if (gate_name) { 179 if (gate_name) {
180 struct clk *tgate_clk; 180 struct clk *tgate_clk;
181 181
182 tgate_clk = clk_register_gate(NULL, gate_name, aux_name, 0, reg, 182 tgate_clk = clk_register_gate(NULL, gate_name, aux_name,
183 CLK_SET_RATE_PARENT, reg,
183 aux->masks->enable_bit, 0, lock); 184 aux->masks->enable_bit, 0, lock);
184 if (IS_ERR_OR_NULL(tgate_clk)) 185 if (IS_ERR_OR_NULL(tgate_clk))
185 goto free_aux; 186 goto free_aux;
diff --git a/drivers/clk/spear/clk-vco-pll.c b/drivers/clk/spear/clk-vco-pll.c
index 5f1b6badeb15..1b9b65bca51e 100644
--- a/drivers/clk/spear/clk-vco-pll.c
+++ b/drivers/clk/spear/clk-vco-pll.c
@@ -147,7 +147,7 @@ static int clk_pll_set_rate(struct clk_hw *hw, unsigned long drate,
147 struct clk_pll *pll = to_clk_pll(hw); 147 struct clk_pll *pll = to_clk_pll(hw);
148 struct pll_rate_tbl *rtbl = pll->vco->rtbl; 148 struct pll_rate_tbl *rtbl = pll->vco->rtbl;
149 unsigned long flags = 0, val; 149 unsigned long flags = 0, val;
150 int i; 150 int uninitialized_var(i);
151 151
152 clk_pll_round_rate_index(hw, drate, NULL, &i); 152 clk_pll_round_rate_index(hw, drate, NULL, &i);
153 153
diff --git a/drivers/clk/spear/clk.c b/drivers/clk/spear/clk.c
index 7cd63788d546..628b6d5ed3d9 100644
--- a/drivers/clk/spear/clk.c
+++ b/drivers/clk/spear/clk.c
@@ -32,5 +32,8 @@ long clk_round_rate_index(struct clk_hw *hw, unsigned long drate,
32 } 32 }
33 } 33 }
34 34
35 if ((*index) == rtbl_cnt)
36 (*index)--;
37
35 return rate; 38 return rate;
36} 39}
diff --git a/drivers/clk/spear/spear1310_clock.c b/drivers/clk/spear/spear1310_clock.c
index 0fcec2aae19c..147e25f00405 100644
--- a/drivers/clk/spear/spear1310_clock.c
+++ b/drivers/clk/spear/spear1310_clock.c
@@ -313,6 +313,20 @@ static struct aux_clk_masks i2s_sclk_masks = {
313/* i2s prs1 aux rate configuration table, in ascending order of rates */ 313/* i2s prs1 aux rate configuration table, in ascending order of rates */
314static struct aux_rate_tbl i2s_prs1_rtbl[] = { 314static struct aux_rate_tbl i2s_prs1_rtbl[] = {
315 /* For parent clk = 49.152 MHz */ 315 /* For parent clk = 49.152 MHz */
316 {.xscale = 1, .yscale = 12, .eq = 0}, /* 2.048 MHz, smp freq = 8Khz */
317 {.xscale = 11, .yscale = 96, .eq = 0}, /* 2.816 MHz, smp freq = 11Khz */
318 {.xscale = 1, .yscale = 6, .eq = 0}, /* 4.096 MHz, smp freq = 16Khz */
319 {.xscale = 11, .yscale = 48, .eq = 0}, /* 5.632 MHz, smp freq = 22Khz */
320
321 /*
322 * with parent clk = 49.152, freq gen is 8.192 MHz, smp freq = 32Khz
323 * with parent clk = 12.288, freq gen is 2.048 MHz, smp freq = 8Khz
324 */
325 {.xscale = 1, .yscale = 3, .eq = 0},
326
327 /* For parent clk = 49.152 MHz */
328 {.xscale = 17, .yscale = 37, .eq = 0}, /* 11.289 MHz, smp freq = 44Khz*/
329
316 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */ 330 {.xscale = 1, .yscale = 2, .eq = 0}, /* 12.288 MHz */
317}; 331};
318 332
@@ -374,9 +388,6 @@ void __init spear1310_clk_init(void)
374{ 388{
375 struct clk *clk, *clk1; 389 struct clk *clk, *clk1;
376 390
377 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
378 clk_register_clkdev(clk, "apb_pclk", NULL);
379
380 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 391 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
381 32000); 392 32000);
382 clk_register_clkdev(clk, "osc_32k_clk", NULL); 393 clk_register_clkdev(clk, "osc_32k_clk", NULL);
@@ -401,7 +412,7 @@ void __init spear1310_clk_init(void)
401 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, 412 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
402 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0, 413 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_RTC_CLK_ENB, 0,
403 &_lock); 414 &_lock);
404 clk_register_clkdev(clk, NULL, "fc900000.rtc"); 415 clk_register_clkdev(clk, NULL, "e0580000.rtc");
405 416
406 /* clock derived from 24 or 25 MHz osc clk */ 417 /* clock derived from 24 or 25 MHz osc clk */
407 /* vco-pll */ 418 /* vco-pll */
@@ -483,13 +494,18 @@ void __init spear1310_clk_init(void)
483 clk_register_clkdev(clk, "ddr_clk", NULL); 494 clk_register_clkdev(clk, "ddr_clk", NULL);
484 495
485 /* clock derived from pll1 clk */ 496 /* clock derived from pll1 clk */
486 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 2); 497 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
498 CLK_SET_RATE_PARENT, 1, 2);
487 clk_register_clkdev(clk, "cpu_clk", NULL); 499 clk_register_clkdev(clk, "cpu_clk", NULL);
488 500
489 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1, 501 clk = clk_register_fixed_factor(NULL, "wdt_clk", "cpu_clk", 0, 1,
490 2); 502 2);
491 clk_register_clkdev(clk, NULL, "ec800620.wdt"); 503 clk_register_clkdev(clk, NULL, "ec800620.wdt");
492 504
505 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
506 2);
507 clk_register_clkdev(clk, NULL, "smp_twd");
508
493 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1, 509 clk = clk_register_fixed_factor(NULL, "ahb_clk", "pll1_clk", 0, 1,
494 6); 510 6);
495 clk_register_clkdev(clk, "ahb_clk", NULL); 511 clk_register_clkdev(clk, "ahb_clk", NULL);
@@ -547,14 +563,14 @@ void __init spear1310_clk_init(void)
547 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 563 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
548 564
549 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 565 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
550 ARRAY_SIZE(uart0_parents), 0, SPEAR1310_PERIP_CLK_CFG, 566 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
551 SPEAR1310_UART_CLK_SHIFT, SPEAR1310_UART_CLK_MASK, 0, 567 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_UART_CLK_SHIFT,
552 &_lock); 568 SPEAR1310_UART_CLK_MASK, 0, &_lock);
553 clk_register_clkdev(clk, "uart0_mclk", NULL); 569 clk_register_clkdev(clk, "uart0_mclk", NULL);
554 570
555 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0, 571 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
556 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UART_CLK_ENB, 0, 572 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
557 &_lock); 573 SPEAR1310_UART_CLK_ENB, 0, &_lock);
558 clk_register_clkdev(clk, NULL, "e0000000.serial"); 574 clk_register_clkdev(clk, NULL, "e0000000.serial");
559 575
560 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk", 576 clk = clk_register_aux("sdhci_syn_clk", "sdhci_syn_gclk",
@@ -563,9 +579,9 @@ void __init spear1310_clk_init(void)
563 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); 579 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
564 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); 580 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
565 581
566 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0, 582 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
567 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SDHCI_CLK_ENB, 0, 583 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
568 &_lock); 584 SPEAR1310_SDHCI_CLK_ENB, 0, &_lock);
569 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 585 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
570 586
571 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 587 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
@@ -574,9 +590,9 @@ void __init spear1310_clk_init(void)
574 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); 590 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
575 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); 591 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
576 592
577 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0, 593 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
578 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CFXD_CLK_ENB, 0, 594 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
579 &_lock); 595 SPEAR1310_CFXD_CLK_ENB, 0, &_lock);
580 clk_register_clkdev(clk, NULL, "b2800000.cf"); 596 clk_register_clkdev(clk, NULL, "b2800000.cf");
581 clk_register_clkdev(clk, NULL, "arasan_xd"); 597 clk_register_clkdev(clk, NULL, "arasan_xd");
582 598
@@ -587,9 +603,9 @@ void __init spear1310_clk_init(void)
587 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 603 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
588 604
589 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 605 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
590 ARRAY_SIZE(c3_parents), 0, SPEAR1310_PERIP_CLK_CFG, 606 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
591 SPEAR1310_C3_CLK_SHIFT, SPEAR1310_C3_CLK_MASK, 0, 607 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_C3_CLK_SHIFT,
592 &_lock); 608 SPEAR1310_C3_CLK_MASK, 0, &_lock);
593 clk_register_clkdev(clk, "c3_mclk", NULL); 609 clk_register_clkdev(clk, "c3_mclk", NULL);
594 610
595 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, 611 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0,
@@ -615,7 +631,7 @@ void __init spear1310_clk_init(void)
615 ARRAY_SIZE(gmac_phy_parents), 0, 631 ARRAY_SIZE(gmac_phy_parents), 0,
616 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT, 632 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_GMAC_PHY_CLK_SHIFT,
617 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock); 633 SPEAR1310_GMAC_PHY_CLK_MASK, 0, &_lock);
618 clk_register_clkdev(clk, NULL, "stmmacphy.0"); 634 clk_register_clkdev(clk, "stmmacphy.0", NULL);
619 635
620 /* clcd */ 636 /* clcd */
621 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 637 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
@@ -630,22 +646,22 @@ void __init spear1310_clk_init(void)
630 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 646 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
631 647
632 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 648 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
633 ARRAY_SIZE(clcd_pixel_parents), 0, 649 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
634 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT, 650 SPEAR1310_PERIP_CLK_CFG, SPEAR1310_CLCD_CLK_SHIFT,
635 SPEAR1310_CLCD_CLK_MASK, 0, &_lock); 651 SPEAR1310_CLCD_CLK_MASK, 0, &_lock);
636 clk_register_clkdev(clk, "clcd_pixel_clk", NULL); 652 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
637 653
638 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, 654 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
639 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0, 655 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_CLCD_CLK_ENB, 0,
640 &_lock); 656 &_lock);
641 clk_register_clkdev(clk, "clcd_clk", NULL); 657 clk_register_clkdev(clk, NULL, "e1000000.clcd");
642 658
643 /* i2s */ 659 /* i2s */
644 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 660 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
645 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG, 661 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1310_I2S_CLK_CFG,
646 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK, 662 SPEAR1310_I2S_SRC_CLK_SHIFT, SPEAR1310_I2S_SRC_CLK_MASK,
647 0, &_lock); 663 0, &_lock);
648 clk_register_clkdev(clk, "i2s_src_clk", NULL); 664 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
649 665
650 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, 666 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0,
651 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, 667 SPEAR1310_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl,
@@ -653,10 +669,10 @@ void __init spear1310_clk_init(void)
653 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 669 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
654 670
655 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 671 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
656 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1310_I2S_CLK_CFG, 672 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
657 SPEAR1310_I2S_REF_SHIFT, SPEAR1310_I2S_REF_SEL_MASK, 0, 673 SPEAR1310_I2S_CLK_CFG, SPEAR1310_I2S_REF_SHIFT,
658 &_lock); 674 SPEAR1310_I2S_REF_SEL_MASK, 0, &_lock);
659 clk_register_clkdev(clk, "i2s_ref_clk", NULL); 675 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
660 676
661 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, 677 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
662 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB, 678 SPEAR1310_PERIP2_CLK_ENB, SPEAR1310_I2S_REF_PAD_CLK_ENB,
@@ -664,7 +680,7 @@ void __init spear1310_clk_init(void)
664 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL); 680 clk_register_clkdev(clk, "i2s_ref_pad_clk", NULL);
665 681
666 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk", 682 clk = clk_register_aux("i2s_sclk_clk", "i2s_sclk_gclk",
667 "i2s_ref_pad_clk", 0, SPEAR1310_I2S_CLK_CFG, 683 "i2s_ref_mclk", 0, SPEAR1310_I2S_CLK_CFG,
668 &i2s_sclk_masks, i2s_sclk_rtbl, 684 &i2s_sclk_masks, i2s_sclk_rtbl,
669 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1); 685 ARRAY_SIZE(i2s_sclk_rtbl), &_lock, &clk1);
670 clk_register_clkdev(clk, "i2s_sclk_clk", NULL); 686 clk_register_clkdev(clk, "i2s_sclk_clk", NULL);
@@ -705,35 +721,37 @@ void __init spear1310_clk_init(void)
705 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, 721 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
706 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0, 722 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC0_CLK_ENB, 0,
707 &_lock); 723 &_lock);
708 clk_register_clkdev(clk, "usbh.0_clk", NULL); 724 clk_register_clkdev(clk, NULL, "e4000000.ohci");
725 clk_register_clkdev(clk, NULL, "e4800000.ehci");
709 726
710 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, 727 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
711 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0, 728 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UHC1_CLK_ENB, 0,
712 &_lock); 729 &_lock);
713 clk_register_clkdev(clk, "usbh.1_clk", NULL); 730 clk_register_clkdev(clk, NULL, "e5000000.ohci");
731 clk_register_clkdev(clk, NULL, "e5800000.ehci");
714 732
715 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, 733 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
716 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0, 734 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_UOC_CLK_ENB, 0,
717 &_lock); 735 &_lock);
718 clk_register_clkdev(clk, NULL, "uoc"); 736 clk_register_clkdev(clk, NULL, "e3800000.otg");
719 737
720 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0, 738 clk = clk_register_gate(NULL, "pcie_sata_0_clk", "ahb_clk", 0,
721 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB, 739 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_0_CLK_ENB,
722 0, &_lock); 740 0, &_lock);
723 clk_register_clkdev(clk, NULL, "dw_pcie.0"); 741 clk_register_clkdev(clk, NULL, "dw_pcie.0");
724 clk_register_clkdev(clk, NULL, "ahci.0"); 742 clk_register_clkdev(clk, NULL, "b1000000.ahci");
725 743
726 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0, 744 clk = clk_register_gate(NULL, "pcie_sata_1_clk", "ahb_clk", 0,
727 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB, 745 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_1_CLK_ENB,
728 0, &_lock); 746 0, &_lock);
729 clk_register_clkdev(clk, NULL, "dw_pcie.1"); 747 clk_register_clkdev(clk, NULL, "dw_pcie.1");
730 clk_register_clkdev(clk, NULL, "ahci.1"); 748 clk_register_clkdev(clk, NULL, "b1800000.ahci");
731 749
732 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0, 750 clk = clk_register_gate(NULL, "pcie_sata_2_clk", "ahb_clk", 0,
733 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB, 751 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_PCIE_SATA_2_CLK_ENB,
734 0, &_lock); 752 0, &_lock);
735 clk_register_clkdev(clk, NULL, "dw_pcie.2"); 753 clk_register_clkdev(clk, NULL, "dw_pcie.2");
736 clk_register_clkdev(clk, NULL, "ahci.2"); 754 clk_register_clkdev(clk, NULL, "b4000000.ahci");
737 755
738 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 756 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
739 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0, 757 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_SYSRAM0_CLK_ENB, 0,
@@ -751,10 +769,10 @@ void __init spear1310_clk_init(void)
751 clk_register_clkdev(clk, "adc_syn_clk", NULL); 769 clk_register_clkdev(clk, "adc_syn_clk", NULL);
752 clk_register_clkdev(clk1, "adc_syn_gclk", NULL); 770 clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
753 771
754 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0, 772 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
755 SPEAR1310_PERIP1_CLK_ENB, SPEAR1310_ADC_CLK_ENB, 0, 773 CLK_SET_RATE_PARENT, SPEAR1310_PERIP1_CLK_ENB,
756 &_lock); 774 SPEAR1310_ADC_CLK_ENB, 0, &_lock);
757 clk_register_clkdev(clk, NULL, "adc_clk"); 775 clk_register_clkdev(clk, NULL, "e0080000.adc");
758 776
759 /* clock derived from apb clk */ 777 /* clock derived from apb clk */
760 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0, 778 clk = clk_register_gate(NULL, "ssp0_clk", "apb_clk", 0,
@@ -916,15 +934,15 @@ void __init spear1310_clk_init(void)
916 SPEAR1310_RAS_CTRL_REG1, 934 SPEAR1310_RAS_CTRL_REG1,
917 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT, 935 SPEAR1310_SMII_RGMII_PHY_CLK_SHIFT,
918 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 936 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
919 clk_register_clkdev(clk, NULL, "stmmacphy.1"); 937 clk_register_clkdev(clk, "stmmacphy.1", NULL);
920 clk_register_clkdev(clk, NULL, "stmmacphy.2"); 938 clk_register_clkdev(clk, "stmmacphy.2", NULL);
921 clk_register_clkdev(clk, NULL, "stmmacphy.4"); 939 clk_register_clkdev(clk, "stmmacphy.4", NULL);
922 940
923 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents, 941 clk = clk_register_mux(NULL, "rmii_phy_mclk", rmii_phy_parents,
924 ARRAY_SIZE(rmii_phy_parents), 0, 942 ARRAY_SIZE(rmii_phy_parents), 0,
925 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT, 943 SPEAR1310_RAS_CTRL_REG1, SPEAR1310_RMII_PHY_CLK_SHIFT,
926 SPEAR1310_PHY_CLK_MASK, 0, &_lock); 944 SPEAR1310_PHY_CLK_MASK, 0, &_lock);
927 clk_register_clkdev(clk, NULL, "stmmacphy.3"); 945 clk_register_clkdev(clk, "stmmacphy.3", NULL);
928 946
929 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents, 947 clk = clk_register_mux(NULL, "uart1_mclk", uart_parents,
930 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0, 948 ARRAY_SIZE(uart_parents), 0, SPEAR1310_RAS_CTRL_REG0,
diff --git a/drivers/clk/spear/spear1340_clock.c b/drivers/clk/spear/spear1340_clock.c
index 2352cee7f645..82abea366b78 100644
--- a/drivers/clk/spear/spear1340_clock.c
+++ b/drivers/clk/spear/spear1340_clock.c
@@ -190,6 +190,7 @@ static struct pll_rate_tbl pll4_rtbl[] = {
190 * different values of vco1div2 190 * different values of vco1div2
191 */ 191 */
192static struct frac_rate_tbl amba_synth_rtbl[] = { 192static struct frac_rate_tbl amba_synth_rtbl[] = {
193 {.div = 0x073A8}, /* for vco1div2 = 600 MHz */
193 {.div = 0x06062}, /* for vco1div2 = 500 MHz */ 194 {.div = 0x06062}, /* for vco1div2 = 500 MHz */
194 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */ 195 {.div = 0x04D1B}, /* for vco1div2 = 400 MHz */
195 {.div = 0x04000}, /* for vco1div2 = 332 MHz */ 196 {.div = 0x04000}, /* for vco1div2 = 332 MHz */
@@ -220,6 +221,12 @@ static struct frac_rate_tbl amba_synth_rtbl[] = {
220 * 500 400 200 0x02800 221 * 500 400 200 0x02800
221 * 500 500 250 0x02000 222 * 500 500 250 0x02000
222 * -------------------------------------------------------------------- 223 * --------------------------------------------------------------------
224 * 600 200 100 0x06000
225 * 600 250 125 0x04CCE
226 * 600 332 166 0x039D5
227 * 600 400 200 0x03000
228 * 600 500 250 0x02666
229 * --------------------------------------------------------------------
223 * 664 200 100 0x06a38 230 * 664 200 100 0x06a38
224 * 664 250 125 0x054FD 231 * 664 250 125 0x054FD
225 * 664 332 166 0x04000 232 * 664 332 166 0x04000
@@ -238,28 +245,50 @@ static struct frac_rate_tbl sys_synth_rtbl[] = {
238 {.div = 0x08000}, 245 {.div = 0x08000},
239 {.div = 0x06a38}, 246 {.div = 0x06a38},
240 {.div = 0x06666}, 247 {.div = 0x06666},
248 {.div = 0x06000},
241 {.div = 0x054FD}, 249 {.div = 0x054FD},
242 {.div = 0x05000}, 250 {.div = 0x05000},
243 {.div = 0x04D18}, 251 {.div = 0x04D18},
252 {.div = 0x04CCE},
244 {.div = 0x04000}, 253 {.div = 0x04000},
254 {.div = 0x039D5},
245 {.div = 0x0351E}, 255 {.div = 0x0351E},
246 {.div = 0x03333}, 256 {.div = 0x03333},
247 {.div = 0x03031}, 257 {.div = 0x03031},
258 {.div = 0x03000},
248 {.div = 0x02A7E}, 259 {.div = 0x02A7E},
249 {.div = 0x02800}, 260 {.div = 0x02800},
250 {.div = 0x0268D}, 261 {.div = 0x0268D},
262 {.div = 0x02666},
251 {.div = 0x02000}, 263 {.div = 0x02000},
252}; 264};
253 265
254/* aux rate configuration table, in ascending order of rates */ 266/* aux rate configuration table, in ascending order of rates */
255static struct aux_rate_tbl aux_rtbl[] = { 267static struct aux_rate_tbl aux_rtbl[] = {
256 /* For VCO1div2 = 500 MHz */ 268 /* 12.29MHz for vic1div2=600MHz and 10.24MHz for VCO1div2=500MHz */
257 {.xscale = 10, .yscale = 204, .eq = 0}, /* 12.29 MHz */ 269 {.xscale = 5, .yscale = 122, .eq = 0},
258 {.xscale = 4, .yscale = 21, .eq = 0}, /* 48 MHz */ 270 /* 14.70MHz for vic1div2=600MHz and 12.29MHz for VCO1div2=500MHz */
259 {.xscale = 2, .yscale = 6, .eq = 0}, /* 83 MHz */ 271 {.xscale = 10, .yscale = 204, .eq = 0},
260 {.xscale = 2, .yscale = 4, .eq = 0}, /* 125 MHz */ 272 /* 48MHz for vic1div2=600MHz and 40 MHz for VCO1div2=500MHz */
261 {.xscale = 1, .yscale = 3, .eq = 1}, /* 166 MHz */ 273 {.xscale = 4, .yscale = 25, .eq = 0},
262 {.xscale = 1, .yscale = 2, .eq = 1}, /* 250 MHz */ 274 /* 57.14MHz for vic1div2=600MHz and 48 MHz for VCO1div2=500MHz */
275 {.xscale = 4, .yscale = 21, .eq = 0},
276 /* 83.33MHz for vic1div2=600MHz and 69.44MHz for VCO1div2=500MHz */
277 {.xscale = 5, .yscale = 18, .eq = 0},
278 /* 100MHz for vic1div2=600MHz and 83.33 MHz for VCO1div2=500MHz */
279 {.xscale = 2, .yscale = 6, .eq = 0},
280 /* 125MHz for vic1div2=600MHz and 104.1MHz for VCO1div2=500MHz */
281 {.xscale = 5, .yscale = 12, .eq = 0},
282 /* 150MHz for vic1div2=600MHz and 125MHz for VCO1div2=500MHz */
283 {.xscale = 2, .yscale = 4, .eq = 0},
284 /* 166MHz for vic1div2=600MHz and 138.88MHz for VCO1div2=500MHz */
285 {.xscale = 5, .yscale = 18, .eq = 1},
286 /* 200MHz for vic1div2=600MHz and 166MHz for VCO1div2=500MHz */
287 {.xscale = 1, .yscale = 3, .eq = 1},
288 /* 250MHz for vic1div2=600MHz and 208.33MHz for VCO1div2=500MHz */
289 {.xscale = 5, .yscale = 12, .eq = 1},
290 /* 300MHz for vic1div2=600MHz and 250MHz for VCO1div2=500MHz */
291 {.xscale = 1, .yscale = 2, .eq = 1},
263}; 292};
264 293
265/* gmac rate configuration table, in ascending order of rates */ 294/* gmac rate configuration table, in ascending order of rates */
@@ -273,16 +302,23 @@ static struct aux_rate_tbl gmac_rtbl[] = {
273 302
274/* clcd rate configuration table, in ascending order of rates */ 303/* clcd rate configuration table, in ascending order of rates */
275static struct frac_rate_tbl clcd_rtbl[] = { 304static struct frac_rate_tbl clcd_rtbl[] = {
305 {.div = 0x18000}, /* 25 Mhz , for vc01div4 = 300 MHz*/
306 {.div = 0x1638E}, /* 27 Mhz , for vc01div4 = 300 MHz*/
276 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/ 307 {.div = 0x14000}, /* 25 Mhz , for vc01div4 = 250 MHz*/
277 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/ 308 {.div = 0x1284B}, /* 27 Mhz , for vc01div4 = 250 MHz*/
278 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */ 309 {.div = 0x0D8D3}, /* 58 Mhz , for vco1div4 = 393 MHz */
279 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */ 310 {.div = 0x0B72C}, /* 58 Mhz , for vco1div4 = 332 MHz */
311 {.div = 0x0A584}, /* 58 Mhz , for vco1div4 = 300 MHz */
312 {.div = 0x093B1}, /* 65 Mhz , for vc01div4 = 300 MHz*/
280 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/ 313 {.div = 0x089EE}, /* 58 Mhz , for vc01div4 = 250 MHz*/
314 {.div = 0x081BA}, /* 74 Mhz , for vc01div4 = 300 MHz*/
281 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/ 315 {.div = 0x07BA0}, /* 65 Mhz , for vc01div4 = 250 MHz*/
282 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/ 316 {.div = 0x06f1C}, /* 72 Mhz , for vc01div4 = 250 MHz*/
283 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */ 317 {.div = 0x06E58}, /* 58 Mhz , for vco1div4 = 200 MHz */
284 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/ 318 {.div = 0x06c1B}, /* 74 Mhz , for vc01div4 = 250 MHz*/
319 {.div = 0x058E3}, /* 108 Mhz , for vc01div4 = 300 MHz*/
285 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/ 320 {.div = 0x04A12}, /* 108 Mhz , for vc01div4 = 250 MHz*/
321 {.div = 0x040A5}, /* 148.5 Mhz , for vc01div4 = 300 MHz*/
286 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/ 322 {.div = 0x0378E}, /* 144 Mhz , for vc01div4 = 250 MHz*/
287 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/ 323 {.div = 0x0360D}, /* 148 Mhz , for vc01div4 = 250 MHz*/
288 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/ 324 {.div = 0x035E0}, /* 148.5 MHz, for vc01div4 = 250 MHz*/
@@ -351,26 +387,37 @@ static struct aux_rate_tbl adc_rtbl[] = {
351 387
352/* General synth rate configuration table, in ascending order of rates */ 388/* General synth rate configuration table, in ascending order of rates */
353static struct frac_rate_tbl gen_rtbl[] = { 389static struct frac_rate_tbl gen_rtbl[] = {
354 /* For vco1div4 = 250 MHz */ 390 {.div = 0x1A92B}, /* 22.5792 MHz for vco1div4=300 MHz*/
355 {.div = 0x1624E}, /* 22.5792 MHz */ 391 {.div = 0x186A0}, /* 24.576 MHz for vco1div4=300 MHz*/
356 {.div = 0x14585}, /* 24.576 MHz */ 392 {.div = 0x18000}, /* 25 MHz for vco1div4=300 MHz*/
357 {.div = 0x14000}, /* 25 MHz */ 393 {.div = 0x1624E}, /* 22.5792 MHz for vco1div4=250 MHz*/
358 {.div = 0x0B127}, /* 45.1584 MHz */ 394 {.div = 0x14585}, /* 24.576 MHz for vco1div4=250 MHz*/
359 {.div = 0x0A000}, /* 50 MHz */ 395 {.div = 0x14000}, /* 25 MHz for vco1div4=250 MHz*/
360 {.div = 0x061A8}, /* 81.92 MHz */ 396 {.div = 0x0D495}, /* 45.1584 MHz for vco1div4=300 MHz*/
361 {.div = 0x05000}, /* 100 MHz */ 397 {.div = 0x0C000}, /* 50 MHz for vco1div4=300 MHz*/
362 {.div = 0x02800}, /* 200 MHz */ 398 {.div = 0x0B127}, /* 45.1584 MHz for vco1div4=250 MHz*/
363 {.div = 0x02620}, /* 210 MHz */ 399 {.div = 0x0A000}, /* 50 MHz for vco1div4=250 MHz*/
364 {.div = 0x02460}, /* 220 MHz */ 400 {.div = 0x07530}, /* 81.92 MHz for vco1div4=300 MHz*/
365 {.div = 0x022C0}, /* 230 MHz */ 401 {.div = 0x061A8}, /* 81.92 MHz for vco1div4=250 MHz*/
366 {.div = 0x02160}, /* 240 MHz */ 402 {.div = 0x06000}, /* 100 MHz for vco1div4=300 MHz*/
367 {.div = 0x02000}, /* 250 MHz */ 403 {.div = 0x05000}, /* 100 MHz for vco1div4=250 MHz*/
404 {.div = 0x03000}, /* 200 MHz for vco1div4=300 MHz*/
405 {.div = 0x02DB6}, /* 210 MHz for vco1div4=300 MHz*/
406 {.div = 0x02BA2}, /* 220 MHz for vco1div4=300 MHz*/
407 {.div = 0x029BD}, /* 230 MHz for vco1div4=300 MHz*/
408 {.div = 0x02800}, /* 200 MHz for vco1div4=250 MHz*/
409 {.div = 0x02666}, /* 250 MHz for vco1div4=300 MHz*/
410 {.div = 0x02620}, /* 210 MHz for vco1div4=250 MHz*/
411 {.div = 0x02460}, /* 220 MHz for vco1div4=250 MHz*/
412 {.div = 0x022C0}, /* 230 MHz for vco1div4=250 MHz*/
413 {.div = 0x02160}, /* 240 MHz for vco1div4=250 MHz*/
414 {.div = 0x02000}, /* 250 MHz for vco1div4=250 MHz*/
368}; 415};
369 416
370/* clock parents */ 417/* clock parents */
371static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", }; 418static const char *vco_parents[] = { "osc_24m_clk", "osc_25m_clk", };
372static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk", 419static const char *sys_parents[] = { "pll1_clk", "pll1_clk", "pll1_clk",
373 "pll1_clk", "sys_synth_clk", "sys_synth_clk", "pll2_clk", "pll3_clk", }; 420 "pll1_clk", "sys_syn_clk", "sys_syn_clk", "pll2_clk", "pll3_clk", };
374static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", }; 421static const char *ahb_parents[] = { "cpu_div3_clk", "amba_syn_clk", };
375static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", }; 422static const char *gpt_parents[] = { "osc_24m_clk", "apb_clk", };
376static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk", 423static const char *uart0_parents[] = { "pll5_clk", "osc_24m_clk",
@@ -391,16 +438,13 @@ static const char *spdif_in_parents[] = { "pll2_clk", "gen_syn3_clk", };
391 438
392static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk", 439static const char *gen_synth0_1_parents[] = { "vco1div4_clk", "vco3div2_clk",
393 "pll3_clk", }; 440 "pll3_clk", };
394static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco3div2_clk", 441static const char *gen_synth2_3_parents[] = { "vco1div4_clk", "vco2div2_clk",
395 "pll2_clk", }; 442 "pll2_clk", };
396 443
397void __init spear1340_clk_init(void) 444void __init spear1340_clk_init(void)
398{ 445{
399 struct clk *clk, *clk1; 446 struct clk *clk, *clk1;
400 447
401 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
402 clk_register_clkdev(clk, "apb_pclk", NULL);
403
404 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 448 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
405 32000); 449 32000);
406 clk_register_clkdev(clk, "osc_32k_clk", NULL); 450 clk_register_clkdev(clk, "osc_32k_clk", NULL);
@@ -425,7 +469,7 @@ void __init spear1340_clk_init(void)
425 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0, 469 clk = clk_register_gate(NULL, "rtc-spear", "osc_32k_clk", 0,
426 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0, 470 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_RTC_CLK_ENB, 0,
427 &_lock); 471 &_lock);
428 clk_register_clkdev(clk, NULL, "fc900000.rtc"); 472 clk_register_clkdev(clk, NULL, "e0580000.rtc");
429 473
430 /* clock derived from 24 or 25 MHz osc clk */ 474 /* clock derived from 24 or 25 MHz osc clk */
431 /* vco-pll */ 475 /* vco-pll */
@@ -499,7 +543,7 @@ void __init spear1340_clk_init(void)
499 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0, 543 clk = clk_register_gate(NULL, "thermal_gclk", "thermal_clk", 0,
500 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0, 544 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_THSENS_CLK_ENB, 0,
501 &_lock); 545 &_lock);
502 clk_register_clkdev(clk, NULL, "spear_thermal"); 546 clk_register_clkdev(clk, NULL, "e07008c4.thermal");
503 547
504 /* clock derived from pll4 clk */ 548 /* clock derived from pll4 clk */
505 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1, 549 clk = clk_register_fixed_factor(NULL, "ddr_clk", "pll4_clk", 0, 1,
@@ -521,7 +565,7 @@ void __init spear1340_clk_init(void)
521 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL, 565 ARRAY_SIZE(sys_parents), 0, SPEAR1340_SYS_CLK_CTRL,
522 SPEAR1340_SCLK_SRC_SEL_SHIFT, 566 SPEAR1340_SCLK_SRC_SEL_SHIFT,
523 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock); 567 SPEAR1340_SCLK_SRC_SEL_MASK, 0, &_lock);
524 clk_register_clkdev(clk, "sys_clk", NULL); 568 clk_register_clkdev(clk, "sys_mclk", NULL);
525 569
526 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1, 570 clk = clk_register_fixed_factor(NULL, "cpu_clk", "sys_mclk", 0, 1,
527 2); 571 2);
@@ -535,6 +579,10 @@ void __init spear1340_clk_init(void)
535 2); 579 2);
536 clk_register_clkdev(clk, NULL, "ec800620.wdt"); 580 clk_register_clkdev(clk, NULL, "ec800620.wdt");
537 581
582 clk = clk_register_fixed_factor(NULL, "smp_twd_clk", "cpu_clk", 0, 1,
583 2);
584 clk_register_clkdev(clk, NULL, "smp_twd");
585
538 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents, 586 clk = clk_register_mux(NULL, "ahb_clk", ahb_parents,
539 ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL, 587 ARRAY_SIZE(ahb_parents), 0, SPEAR1340_SYS_CLK_CTRL,
540 SPEAR1340_HCLK_SRC_SEL_SHIFT, 588 SPEAR1340_HCLK_SRC_SEL_SHIFT,
@@ -594,14 +642,14 @@ void __init spear1340_clk_init(void)
594 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL); 642 clk_register_clkdev(clk1, "uart0_syn_gclk", NULL);
595 643
596 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 644 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
597 ARRAY_SIZE(uart0_parents), 0, SPEAR1340_PERIP_CLK_CFG, 645 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
598 SPEAR1340_UART0_CLK_SHIFT, SPEAR1340_UART_CLK_MASK, 0, 646 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_UART0_CLK_SHIFT,
599 &_lock); 647 SPEAR1340_UART_CLK_MASK, 0, &_lock);
600 clk_register_clkdev(clk, "uart0_mclk", NULL); 648 clk_register_clkdev(clk, "uart0_mclk", NULL);
601 649
602 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk", 0, 650 clk = clk_register_gate(NULL, "uart0_clk", "uart0_mclk",
603 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UART0_CLK_ENB, 0, 651 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
604 &_lock); 652 SPEAR1340_UART0_CLK_ENB, 0, &_lock);
605 clk_register_clkdev(clk, NULL, "e0000000.serial"); 653 clk_register_clkdev(clk, NULL, "e0000000.serial");
606 654
607 clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk", 655 clk = clk_register_aux("uart1_syn_clk", "uart1_syn_gclk",
@@ -627,9 +675,9 @@ void __init spear1340_clk_init(void)
627 clk_register_clkdev(clk, "sdhci_syn_clk", NULL); 675 clk_register_clkdev(clk, "sdhci_syn_clk", NULL);
628 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL); 676 clk_register_clkdev(clk1, "sdhci_syn_gclk", NULL);
629 677
630 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk", 0, 678 clk = clk_register_gate(NULL, "sdhci_clk", "sdhci_syn_gclk",
631 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SDHCI_CLK_ENB, 0, 679 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
632 &_lock); 680 SPEAR1340_SDHCI_CLK_ENB, 0, &_lock);
633 clk_register_clkdev(clk, NULL, "b3000000.sdhci"); 681 clk_register_clkdev(clk, NULL, "b3000000.sdhci");
634 682
635 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk", 683 clk = clk_register_aux("cfxd_syn_clk", "cfxd_syn_gclk", "vco1div2_clk",
@@ -638,9 +686,9 @@ void __init spear1340_clk_init(void)
638 clk_register_clkdev(clk, "cfxd_syn_clk", NULL); 686 clk_register_clkdev(clk, "cfxd_syn_clk", NULL);
639 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL); 687 clk_register_clkdev(clk1, "cfxd_syn_gclk", NULL);
640 688
641 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk", 0, 689 clk = clk_register_gate(NULL, "cfxd_clk", "cfxd_syn_gclk",
642 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CFXD_CLK_ENB, 0, 690 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
643 &_lock); 691 SPEAR1340_CFXD_CLK_ENB, 0, &_lock);
644 clk_register_clkdev(clk, NULL, "b2800000.cf"); 692 clk_register_clkdev(clk, NULL, "b2800000.cf");
645 clk_register_clkdev(clk, NULL, "arasan_xd"); 693 clk_register_clkdev(clk, NULL, "arasan_xd");
646 694
@@ -651,15 +699,15 @@ void __init spear1340_clk_init(void)
651 clk_register_clkdev(clk1, "c3_syn_gclk", NULL); 699 clk_register_clkdev(clk1, "c3_syn_gclk", NULL);
652 700
653 clk = clk_register_mux(NULL, "c3_mclk", c3_parents, 701 clk = clk_register_mux(NULL, "c3_mclk", c3_parents,
654 ARRAY_SIZE(c3_parents), 0, SPEAR1340_PERIP_CLK_CFG, 702 ARRAY_SIZE(c3_parents), CLK_SET_RATE_PARENT,
655 SPEAR1340_C3_CLK_SHIFT, SPEAR1340_C3_CLK_MASK, 0, 703 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_C3_CLK_SHIFT,
656 &_lock); 704 SPEAR1340_C3_CLK_MASK, 0, &_lock);
657 clk_register_clkdev(clk, "c3_mclk", NULL); 705 clk_register_clkdev(clk, "c3_mclk", NULL);
658 706
659 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", 0, 707 clk = clk_register_gate(NULL, "c3_clk", "c3_mclk", CLK_SET_RATE_PARENT,
660 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0, 708 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_C3_CLK_ENB, 0,
661 &_lock); 709 &_lock);
662 clk_register_clkdev(clk, NULL, "c3"); 710 clk_register_clkdev(clk, NULL, "e1800000.c3");
663 711
664 /* gmac */ 712 /* gmac */
665 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents, 713 clk = clk_register_mux(NULL, "phy_input_mclk", gmac_phy_input_parents,
@@ -679,7 +727,7 @@ void __init spear1340_clk_init(void)
679 ARRAY_SIZE(gmac_phy_parents), 0, 727 ARRAY_SIZE(gmac_phy_parents), 0,
680 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT, 728 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_GMAC_PHY_CLK_SHIFT,
681 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock); 729 SPEAR1340_GMAC_PHY_CLK_MASK, 0, &_lock);
682 clk_register_clkdev(clk, NULL, "stmmacphy.0"); 730 clk_register_clkdev(clk, "stmmacphy.0", NULL);
683 731
684 /* clcd */ 732 /* clcd */
685 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents, 733 clk = clk_register_mux(NULL, "clcd_syn_mclk", clcd_synth_parents,
@@ -694,33 +742,34 @@ void __init spear1340_clk_init(void)
694 clk_register_clkdev(clk, "clcd_syn_clk", NULL); 742 clk_register_clkdev(clk, "clcd_syn_clk", NULL);
695 743
696 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents, 744 clk = clk_register_mux(NULL, "clcd_pixel_mclk", clcd_pixel_parents,
697 ARRAY_SIZE(clcd_pixel_parents), 0, 745 ARRAY_SIZE(clcd_pixel_parents), CLK_SET_RATE_PARENT,
698 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT, 746 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_CLCD_CLK_SHIFT,
699 SPEAR1340_CLCD_CLK_MASK, 0, &_lock); 747 SPEAR1340_CLCD_CLK_MASK, 0, &_lock);
700 clk_register_clkdev(clk, "clcd_pixel_clk", NULL); 748 clk_register_clkdev(clk, "clcd_pixel_mclk", NULL);
701 749
702 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0, 750 clk = clk_register_gate(NULL, "clcd_clk", "clcd_pixel_mclk", 0,
703 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0, 751 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_CLCD_CLK_ENB, 0,
704 &_lock); 752 &_lock);
705 clk_register_clkdev(clk, "clcd_clk", NULL); 753 clk_register_clkdev(clk, NULL, "e1000000.clcd");
706 754
707 /* i2s */ 755 /* i2s */
708 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents, 756 clk = clk_register_mux(NULL, "i2s_src_mclk", i2s_src_parents,
709 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG, 757 ARRAY_SIZE(i2s_src_parents), 0, SPEAR1340_I2S_CLK_CFG,
710 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK, 758 SPEAR1340_I2S_SRC_CLK_SHIFT, SPEAR1340_I2S_SRC_CLK_MASK,
711 0, &_lock); 759 0, &_lock);
712 clk_register_clkdev(clk, "i2s_src_clk", NULL); 760 clk_register_clkdev(clk, "i2s_src_mclk", NULL);
713 761
714 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk", 0, 762 clk = clk_register_aux("i2s_prs1_clk", NULL, "i2s_src_mclk",
715 SPEAR1340_I2S_CLK_CFG, &i2s_prs1_masks, i2s_prs1_rtbl, 763 CLK_SET_RATE_PARENT, SPEAR1340_I2S_CLK_CFG,
764 &i2s_prs1_masks, i2s_prs1_rtbl,
716 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL); 765 ARRAY_SIZE(i2s_prs1_rtbl), &_lock, NULL);
717 clk_register_clkdev(clk, "i2s_prs1_clk", NULL); 766 clk_register_clkdev(clk, "i2s_prs1_clk", NULL);
718 767
719 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents, 768 clk = clk_register_mux(NULL, "i2s_ref_mclk", i2s_ref_parents,
720 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR1340_I2S_CLK_CFG, 769 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
721 SPEAR1340_I2S_REF_SHIFT, SPEAR1340_I2S_REF_SEL_MASK, 0, 770 SPEAR1340_I2S_CLK_CFG, SPEAR1340_I2S_REF_SHIFT,
722 &_lock); 771 SPEAR1340_I2S_REF_SEL_MASK, 0, &_lock);
723 clk_register_clkdev(clk, "i2s_ref_clk", NULL); 772 clk_register_clkdev(clk, "i2s_ref_mclk", NULL);
724 773
725 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0, 774 clk = clk_register_gate(NULL, "i2s_ref_pad_clk", "i2s_ref_mclk", 0,
726 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB, 775 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_I2S_REF_PAD_CLK_ENB,
@@ -769,23 +818,25 @@ void __init spear1340_clk_init(void)
769 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0, 818 clk = clk_register_gate(NULL, "usbh0_clk", "ahb_clk", 0,
770 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0, 819 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC0_CLK_ENB, 0,
771 &_lock); 820 &_lock);
772 clk_register_clkdev(clk, "usbh.0_clk", NULL); 821 clk_register_clkdev(clk, NULL, "e4000000.ohci");
822 clk_register_clkdev(clk, NULL, "e4800000.ehci");
773 823
774 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0, 824 clk = clk_register_gate(NULL, "usbh1_clk", "ahb_clk", 0,
775 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0, 825 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UHC1_CLK_ENB, 0,
776 &_lock); 826 &_lock);
777 clk_register_clkdev(clk, "usbh.1_clk", NULL); 827 clk_register_clkdev(clk, NULL, "e5000000.ohci");
828 clk_register_clkdev(clk, NULL, "e5800000.ehci");
778 829
779 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0, 830 clk = clk_register_gate(NULL, "uoc_clk", "ahb_clk", 0,
780 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0, 831 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_UOC_CLK_ENB, 0,
781 &_lock); 832 &_lock);
782 clk_register_clkdev(clk, NULL, "uoc"); 833 clk_register_clkdev(clk, NULL, "e3800000.otg");
783 834
784 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0, 835 clk = clk_register_gate(NULL, "pcie_sata_clk", "ahb_clk", 0,
785 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB, 836 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_PCIE_SATA_CLK_ENB,
786 0, &_lock); 837 0, &_lock);
787 clk_register_clkdev(clk, NULL, "dw_pcie"); 838 clk_register_clkdev(clk, NULL, "dw_pcie");
788 clk_register_clkdev(clk, NULL, "ahci"); 839 clk_register_clkdev(clk, NULL, "b1000000.ahci");
789 840
790 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0, 841 clk = clk_register_gate(NULL, "sysram0_clk", "ahb_clk", 0,
791 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0, 842 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_SYSRAM0_CLK_ENB, 0,
@@ -803,10 +854,10 @@ void __init spear1340_clk_init(void)
803 clk_register_clkdev(clk, "adc_syn_clk", NULL); 854 clk_register_clkdev(clk, "adc_syn_clk", NULL);
804 clk_register_clkdev(clk1, "adc_syn_gclk", NULL); 855 clk_register_clkdev(clk1, "adc_syn_gclk", NULL);
805 856
806 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk", 0, 857 clk = clk_register_gate(NULL, "adc_clk", "adc_syn_gclk",
807 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_ADC_CLK_ENB, 0, 858 CLK_SET_RATE_PARENT, SPEAR1340_PERIP1_CLK_ENB,
808 &_lock); 859 SPEAR1340_ADC_CLK_ENB, 0, &_lock);
809 clk_register_clkdev(clk, NULL, "adc_clk"); 860 clk_register_clkdev(clk, NULL, "e0080000.adc");
810 861
811 /* clock derived from apb clk */ 862 /* clock derived from apb clk */
812 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0, 863 clk = clk_register_gate(NULL, "ssp_clk", "apb_clk", 0,
@@ -827,12 +878,12 @@ void __init spear1340_clk_init(void)
827 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0, 878 clk = clk_register_gate(NULL, "i2s_play_clk", "apb_clk", 0,
828 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0, 879 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_PLAY_CLK_ENB, 0,
829 &_lock); 880 &_lock);
830 clk_register_clkdev(clk, NULL, "b2400000.i2s"); 881 clk_register_clkdev(clk, NULL, "b2400000.i2s-play");
831 882
832 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0, 883 clk = clk_register_gate(NULL, "i2s_rec_clk", "apb_clk", 0,
833 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0, 884 SPEAR1340_PERIP1_CLK_ENB, SPEAR1340_I2S_REC_CLK_ENB, 0,
834 &_lock); 885 &_lock);
835 clk_register_clkdev(clk, NULL, "b2000000.i2s"); 886 clk_register_clkdev(clk, NULL, "b2000000.i2s-rec");
836 887
837 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0, 888 clk = clk_register_gate(NULL, "kbd_clk", "apb_clk", 0,
838 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0, 889 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_KBD_CLK_ENB, 0,
@@ -844,37 +895,37 @@ void __init spear1340_clk_init(void)
844 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG, 895 ARRAY_SIZE(gen_synth0_1_parents), 0, SPEAR1340_PLL_CFG,
845 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT, 896 SPEAR1340_GEN_SYNT0_1_CLK_SHIFT,
846 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 897 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
847 clk_register_clkdev(clk, "gen_syn0_1_clk", NULL); 898 clk_register_clkdev(clk, "gen_syn0_1_mclk", NULL);
848 899
849 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents, 900 clk = clk_register_mux(NULL, "gen_syn2_3_mclk", gen_synth2_3_parents,
850 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG, 901 ARRAY_SIZE(gen_synth2_3_parents), 0, SPEAR1340_PLL_CFG,
851 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT, 902 SPEAR1340_GEN_SYNT2_3_CLK_SHIFT,
852 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock); 903 SPEAR1340_GEN_SYNT_CLK_MASK, 0, &_lock);
853 clk_register_clkdev(clk, "gen_syn2_3_clk", NULL); 904 clk_register_clkdev(clk, "gen_syn2_3_mclk", NULL);
854 905
855 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_clk", 0, 906 clk = clk_register_frac("gen_syn0_clk", "gen_syn0_1_mclk", 0,
856 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl), 907 SPEAR1340_GEN_CLK_SYNT0, gen_rtbl, ARRAY_SIZE(gen_rtbl),
857 &_lock); 908 &_lock);
858 clk_register_clkdev(clk, "gen_syn0_clk", NULL); 909 clk_register_clkdev(clk, "gen_syn0_clk", NULL);
859 910
860 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_clk", 0, 911 clk = clk_register_frac("gen_syn1_clk", "gen_syn0_1_mclk", 0,
861 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl), 912 SPEAR1340_GEN_CLK_SYNT1, gen_rtbl, ARRAY_SIZE(gen_rtbl),
862 &_lock); 913 &_lock);
863 clk_register_clkdev(clk, "gen_syn1_clk", NULL); 914 clk_register_clkdev(clk, "gen_syn1_clk", NULL);
864 915
865 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_clk", 0, 916 clk = clk_register_frac("gen_syn2_clk", "gen_syn2_3_mclk", 0,
866 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl), 917 SPEAR1340_GEN_CLK_SYNT2, gen_rtbl, ARRAY_SIZE(gen_rtbl),
867 &_lock); 918 &_lock);
868 clk_register_clkdev(clk, "gen_syn2_clk", NULL); 919 clk_register_clkdev(clk, "gen_syn2_clk", NULL);
869 920
870 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_clk", 0, 921 clk = clk_register_frac("gen_syn3_clk", "gen_syn2_3_mclk", 0,
871 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl), 922 SPEAR1340_GEN_CLK_SYNT3, gen_rtbl, ARRAY_SIZE(gen_rtbl),
872 &_lock); 923 &_lock);
873 clk_register_clkdev(clk, "gen_syn3_clk", NULL); 924 clk_register_clkdev(clk, "gen_syn3_clk", NULL);
874 925
875 clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk", 0, 926 clk = clk_register_gate(NULL, "mali_clk", "gen_syn3_clk",
876 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_MALI_CLK_ENB, 0, 927 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
877 &_lock); 928 SPEAR1340_MALI_CLK_ENB, 0, &_lock);
878 clk_register_clkdev(clk, NULL, "mali"); 929 clk_register_clkdev(clk, NULL, "mali");
879 930
880 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0, 931 clk = clk_register_gate(NULL, "cec0_clk", "ahb_clk", 0,
@@ -888,26 +939,26 @@ void __init spear1340_clk_init(void)
888 clk_register_clkdev(clk, NULL, "spear_cec.1"); 939 clk_register_clkdev(clk, NULL, "spear_cec.1");
889 940
890 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents, 941 clk = clk_register_mux(NULL, "spdif_out_mclk", spdif_out_parents,
891 ARRAY_SIZE(spdif_out_parents), 0, 942 ARRAY_SIZE(spdif_out_parents), CLK_SET_RATE_PARENT,
892 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT, 943 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_OUT_CLK_SHIFT,
893 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 944 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
894 clk_register_clkdev(clk, "spdif_out_mclk", NULL); 945 clk_register_clkdev(clk, "spdif_out_mclk", NULL);
895 946
896 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk", 0, 947 clk = clk_register_gate(NULL, "spdif_out_clk", "spdif_out_mclk",
897 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_OUT_CLK_ENB, 948 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
898 0, &_lock); 949 SPEAR1340_SPDIF_OUT_CLK_ENB, 0, &_lock);
899 clk_register_clkdev(clk, NULL, "spdif-out"); 950 clk_register_clkdev(clk, NULL, "d0000000.spdif-out");
900 951
901 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents, 952 clk = clk_register_mux(NULL, "spdif_in_mclk", spdif_in_parents,
902 ARRAY_SIZE(spdif_in_parents), 0, 953 ARRAY_SIZE(spdif_in_parents), CLK_SET_RATE_PARENT,
903 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT, 954 SPEAR1340_PERIP_CLK_CFG, SPEAR1340_SPDIF_IN_CLK_SHIFT,
904 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock); 955 SPEAR1340_SPDIF_CLK_MASK, 0, &_lock);
905 clk_register_clkdev(clk, "spdif_in_mclk", NULL); 956 clk_register_clkdev(clk, "spdif_in_mclk", NULL);
906 957
907 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk", 0, 958 clk = clk_register_gate(NULL, "spdif_in_clk", "spdif_in_mclk",
908 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_SPDIF_IN_CLK_ENB, 0, 959 CLK_SET_RATE_PARENT, SPEAR1340_PERIP3_CLK_ENB,
909 &_lock); 960 SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
910 clk_register_clkdev(clk, NULL, "spdif-in"); 961 clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
911 962
912 clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0, 963 clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0,
913 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0, 964 SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
@@ -917,7 +968,7 @@ void __init spear1340_clk_init(void)
917 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0, 968 clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0,
918 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0, 969 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
919 &_lock); 970 &_lock);
920 clk_register_clkdev(clk, NULL, "plgpio"); 971 clk_register_clkdev(clk, NULL, "e2800000.gpio");
921 972
922 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0, 973 clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0,
923 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB, 974 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
@@ -937,25 +988,25 @@ void __init spear1340_clk_init(void)
937 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0, 988 clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0,
938 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0, 989 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
939 &_lock); 990 &_lock);
940 clk_register_clkdev(clk, NULL, "spear_camif.0"); 991 clk_register_clkdev(clk, NULL, "d0200000.cam0");
941 992
942 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0, 993 clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0,
943 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0, 994 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
944 &_lock); 995 &_lock);
945 clk_register_clkdev(clk, NULL, "spear_camif.1"); 996 clk_register_clkdev(clk, NULL, "d0300000.cam1");
946 997
947 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0, 998 clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0,
948 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0, 999 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
949 &_lock); 1000 &_lock);
950 clk_register_clkdev(clk, NULL, "spear_camif.2"); 1001 clk_register_clkdev(clk, NULL, "d0400000.cam2");
951 1002
952 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0, 1003 clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0,
953 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0, 1004 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
954 &_lock); 1005 &_lock);
955 clk_register_clkdev(clk, NULL, "spear_camif.3"); 1006 clk_register_clkdev(clk, NULL, "d0500000.cam3");
956 1007
957 clk = clk_register_gate(NULL, "pwm_clk", "pwm_mclk", 0, 1008 clk = clk_register_gate(NULL, "pwm_clk", "ahb_clk", 0,
958 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0, 1009 SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PWM_CLK_ENB, 0,
959 &_lock); 1010 &_lock);
960 clk_register_clkdev(clk, NULL, "pwm"); 1011 clk_register_clkdev(clk, NULL, "e0180000.pwm");
961} 1012}
diff --git a/drivers/clk/spear/spear3xx_clock.c b/drivers/clk/spear/spear3xx_clock.c
index c3157454bb3f..33d3ac588da7 100644
--- a/drivers/clk/spear/spear3xx_clock.c
+++ b/drivers/clk/spear/spear3xx_clock.c
@@ -107,6 +107,12 @@ static struct pll_rate_tbl pll_rtbl[] = {
107/* aux rate configuration table, in ascending order of rates */ 107/* aux rate configuration table, in ascending order of rates */
108static struct aux_rate_tbl aux_rtbl[] = { 108static struct aux_rate_tbl aux_rtbl[] = {
109 /* For PLL1 = 332 MHz */ 109 /* For PLL1 = 332 MHz */
110 {.xscale = 1, .yscale = 81, .eq = 0}, /* 2.049 MHz */
111 {.xscale = 1, .yscale = 59, .eq = 0}, /* 2.822 MHz */
112 {.xscale = 2, .yscale = 81, .eq = 0}, /* 4.098 MHz */
113 {.xscale = 3, .yscale = 89, .eq = 0}, /* 5.644 MHz */
114 {.xscale = 4, .yscale = 81, .eq = 0}, /* 8.197 MHz */
115 {.xscale = 4, .yscale = 59, .eq = 0}, /* 11.254 MHz */
110 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */ 116 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
111 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ 117 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
112 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ 118 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
@@ -157,6 +163,8 @@ static void __init spear300_clk_init(void)
157 1); 163 1);
158 clk_register_clkdev(clk, NULL, "a0000000.kbd"); 164 clk_register_clkdev(clk, NULL, "a0000000.kbd");
159} 165}
166#else
167static inline void spear300_clk_init(void) { }
160#endif 168#endif
161 169
162/* array of all spear 310 clock lookups */ 170/* array of all spear 310 clock lookups */
@@ -197,6 +205,8 @@ static void __init spear310_clk_init(void)
197 1); 205 1);
198 clk_register_clkdev(clk, NULL, "b2200000.serial"); 206 clk_register_clkdev(clk, NULL, "b2200000.serial");
199} 207}
208#else
209static inline void spear310_clk_init(void) { }
200#endif 210#endif
201 211
202/* array of all spear 320 clock lookups */ 212/* array of all spear 320 clock lookups */
@@ -251,7 +261,7 @@ static void __init spear320_clk_init(void)
251 261
252 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1, 262 clk = clk_register_fixed_factor(NULL, "pwm_clk", "ras_ahb_clk", 0, 1,
253 1); 263 1);
254 clk_register_clkdev(clk, "pwm", NULL); 264 clk_register_clkdev(clk, NULL, "a8000000.pwm");
255 265
256 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1, 266 clk = clk_register_fixed_factor(NULL, "ssp1_clk", "ras_ahb_clk", 0, 1,
257 1); 267 1);
@@ -271,26 +281,37 @@ static void __init spear320_clk_init(void)
271 281
272 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1, 282 clk = clk_register_fixed_factor(NULL, "i2s_clk", "ras_apb_clk", 0, 1,
273 1); 283 1);
274 clk_register_clkdev(clk, NULL, "i2s"); 284 clk_register_clkdev(clk, NULL, "a9400000.i2s");
275 285
276 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents, 286 clk = clk_register_mux(NULL, "i2s_ref_clk", i2s_ref_parents,
277 ARRAY_SIZE(i2s_ref_parents), 0, SPEAR320_CONTROL_REG, 287 ARRAY_SIZE(i2s_ref_parents), CLK_SET_RATE_PARENT,
278 I2S_REF_PCLK_SHIFT, I2S_REF_PCLK_MASK, 0, &_lock); 288 SPEAR320_CONTROL_REG, I2S_REF_PCLK_SHIFT,
289 I2S_REF_PCLK_MASK, 0, &_lock);
279 clk_register_clkdev(clk, "i2s_ref_clk", NULL); 290 clk_register_clkdev(clk, "i2s_ref_clk", NULL);
280 291
281 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk", 0, 1, 292 clk = clk_register_fixed_factor(NULL, "i2s_sclk", "i2s_ref_clk",
293 CLK_SET_RATE_PARENT, 1,
282 4); 294 4);
283 clk_register_clkdev(clk, "i2s_sclk", NULL); 295 clk_register_clkdev(clk, "i2s_sclk", NULL);
284 296
297 clk = clk_register_fixed_factor(NULL, "macb1_clk", "ras_apb_clk", 0, 1,
298 1);
299 clk_register_clkdev(clk, "hclk", "aa000000.eth");
300
301 clk = clk_register_fixed_factor(NULL, "macb2_clk", "ras_apb_clk", 0, 1,
302 1);
303 clk_register_clkdev(clk, "hclk", "ab000000.eth");
304
285 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents, 305 clk = clk_register_mux(NULL, "rs485_clk", uartx_parents,
286 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 306 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
287 SPEAR320_RS485_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 307 SPEAR320_EXT_CTRL_REG, SPEAR320_RS485_PCLK_SHIFT,
288 &_lock); 308 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
289 clk_register_clkdev(clk, NULL, "a9300000.serial"); 309 clk_register_clkdev(clk, NULL, "a9300000.serial");
290 310
291 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents, 311 clk = clk_register_mux(NULL, "sdhci_clk", sdhci_parents,
292 ARRAY_SIZE(sdhci_parents), 0, SPEAR320_CONTROL_REG, 312 ARRAY_SIZE(sdhci_parents), CLK_SET_RATE_PARENT,
293 SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK, 0, &_lock); 313 SPEAR320_CONTROL_REG, SDHCI_PCLK_SHIFT, SDHCI_PCLK_MASK,
314 0, &_lock);
294 clk_register_clkdev(clk, NULL, "70000000.sdhci"); 315 clk_register_clkdev(clk, NULL, "70000000.sdhci");
295 316
296 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents, 317 clk = clk_register_mux(NULL, "smii_pclk", smii0_parents,
@@ -302,49 +323,49 @@ static void __init spear320_clk_init(void)
302 clk_register_clkdev(clk, NULL, "smii"); 323 clk_register_clkdev(clk, NULL, "smii");
303 324
304 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents, 325 clk = clk_register_mux(NULL, "uart1_clk", uartx_parents,
305 ARRAY_SIZE(uartx_parents), 0, SPEAR320_CONTROL_REG, 326 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
306 UART1_PCLK_SHIFT, UART1_PCLK_MASK, 0, &_lock); 327 SPEAR320_CONTROL_REG, UART1_PCLK_SHIFT, UART1_PCLK_MASK,
328 0, &_lock);
307 clk_register_clkdev(clk, NULL, "a3000000.serial"); 329 clk_register_clkdev(clk, NULL, "a3000000.serial");
308 330
309 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents, 331 clk = clk_register_mux(NULL, "uart2_clk", uartx_parents,
310 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 332 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
311 SPEAR320_UART2_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 333 SPEAR320_EXT_CTRL_REG, SPEAR320_UART2_PCLK_SHIFT,
312 &_lock); 334 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
313 clk_register_clkdev(clk, NULL, "a4000000.serial"); 335 clk_register_clkdev(clk, NULL, "a4000000.serial");
314 336
315 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents, 337 clk = clk_register_mux(NULL, "uart3_clk", uartx_parents,
316 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 338 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
317 SPEAR320_UART3_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 339 SPEAR320_EXT_CTRL_REG, SPEAR320_UART3_PCLK_SHIFT,
318 &_lock); 340 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
319 clk_register_clkdev(clk, NULL, "a9100000.serial"); 341 clk_register_clkdev(clk, NULL, "a9100000.serial");
320 342
321 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents, 343 clk = clk_register_mux(NULL, "uart4_clk", uartx_parents,
322 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 344 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
323 SPEAR320_UART4_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 345 SPEAR320_EXT_CTRL_REG, SPEAR320_UART4_PCLK_SHIFT,
324 &_lock); 346 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
325 clk_register_clkdev(clk, NULL, "a9200000.serial"); 347 clk_register_clkdev(clk, NULL, "a9200000.serial");
326 348
327 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents, 349 clk = clk_register_mux(NULL, "uart5_clk", uartx_parents,
328 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 350 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
329 SPEAR320_UART5_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 351 SPEAR320_EXT_CTRL_REG, SPEAR320_UART5_PCLK_SHIFT,
330 &_lock); 352 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
331 clk_register_clkdev(clk, NULL, "60000000.serial"); 353 clk_register_clkdev(clk, NULL, "60000000.serial");
332 354
333 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents, 355 clk = clk_register_mux(NULL, "uart6_clk", uartx_parents,
334 ARRAY_SIZE(uartx_parents), 0, SPEAR320_EXT_CTRL_REG, 356 ARRAY_SIZE(uartx_parents), CLK_SET_RATE_PARENT,
335 SPEAR320_UART6_PCLK_SHIFT, SPEAR320_UARTX_PCLK_MASK, 0, 357 SPEAR320_EXT_CTRL_REG, SPEAR320_UART6_PCLK_SHIFT,
336 &_lock); 358 SPEAR320_UARTX_PCLK_MASK, 0, &_lock);
337 clk_register_clkdev(clk, NULL, "60100000.serial"); 359 clk_register_clkdev(clk, NULL, "60100000.serial");
338} 360}
361#else
362static inline void spear320_clk_init(void) { }
339#endif 363#endif
340 364
341void __init spear3xx_clk_init(void) 365void __init spear3xx_clk_init(void)
342{ 366{
343 struct clk *clk, *clk1; 367 struct clk *clk, *clk1;
344 368
345 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
346 clk_register_clkdev(clk, "apb_pclk", NULL);
347
348 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 369 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
349 32000); 370 32000);
350 clk_register_clkdev(clk, "osc_32k_clk", NULL); 371 clk_register_clkdev(clk, "osc_32k_clk", NULL);
@@ -380,7 +401,8 @@ void __init spear3xx_clk_init(void)
380 clk_register_clkdev(clk1, "pll2_clk", NULL); 401 clk_register_clkdev(clk1, "pll2_clk", NULL);
381 402
382 /* clock derived from pll1 clk */ 403 /* clock derived from pll1 clk */
383 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1); 404 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
405 CLK_SET_RATE_PARENT, 1, 1);
384 clk_register_clkdev(clk, "cpu_clk", NULL); 406 clk_register_clkdev(clk, "cpu_clk", NULL);
385 407
386 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 408 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
@@ -395,12 +417,14 @@ void __init spear3xx_clk_init(void)
395 clk_register_clkdev(clk1, "uart_syn_gclk", NULL); 417 clk_register_clkdev(clk1, "uart_syn_gclk", NULL);
396 418
397 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents, 419 clk = clk_register_mux(NULL, "uart0_mclk", uart0_parents,
398 ARRAY_SIZE(uart0_parents), 0, PERIP_CLK_CFG, 420 ARRAY_SIZE(uart0_parents), CLK_SET_RATE_PARENT,
399 UART_CLK_SHIFT, UART_CLK_MASK, 0, &_lock); 421 PERIP_CLK_CFG, UART_CLK_SHIFT, UART_CLK_MASK, 0,
422 &_lock);
400 clk_register_clkdev(clk, "uart0_mclk", NULL); 423 clk_register_clkdev(clk, "uart0_mclk", NULL);
401 424
402 clk = clk_register_gate(NULL, "uart0", "uart0_mclk", 0, PERIP1_CLK_ENB, 425 clk = clk_register_gate(NULL, "uart0", "uart0_mclk",
403 UART_CLK_ENB, 0, &_lock); 426 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, UART_CLK_ENB, 0,
427 &_lock);
404 clk_register_clkdev(clk, NULL, "d0000000.serial"); 428 clk_register_clkdev(clk, NULL, "d0000000.serial");
405 429
406 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0, 430 clk = clk_register_aux("firda_syn_clk", "firda_syn_gclk", "pll1_clk", 0,
@@ -410,40 +434,44 @@ void __init spear3xx_clk_init(void)
410 clk_register_clkdev(clk1, "firda_syn_gclk", NULL); 434 clk_register_clkdev(clk1, "firda_syn_gclk", NULL);
411 435
412 clk = clk_register_mux(NULL, "firda_mclk", firda_parents, 436 clk = clk_register_mux(NULL, "firda_mclk", firda_parents,
413 ARRAY_SIZE(firda_parents), 0, PERIP_CLK_CFG, 437 ARRAY_SIZE(firda_parents), CLK_SET_RATE_PARENT,
414 FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0, &_lock); 438 PERIP_CLK_CFG, FIRDA_CLK_SHIFT, FIRDA_CLK_MASK, 0,
439 &_lock);
415 clk_register_clkdev(clk, "firda_mclk", NULL); 440 clk_register_clkdev(clk, "firda_mclk", NULL);
416 441
417 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk", 0, 442 clk = clk_register_gate(NULL, "firda_clk", "firda_mclk",
418 PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0, &_lock); 443 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, FIRDA_CLK_ENB, 0,
444 &_lock);
419 clk_register_clkdev(clk, NULL, "firda"); 445 clk_register_clkdev(clk, NULL, "firda");
420 446
421 /* gpt clocks */ 447 /* gpt clocks */
422 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl, 448 clk_register_gpt("gpt0_syn_clk", "pll1_clk", 0, PRSC0_CLK_CFG, gpt_rtbl,
423 ARRAY_SIZE(gpt_rtbl), &_lock); 449 ARRAY_SIZE(gpt_rtbl), &_lock);
424 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents, 450 clk = clk_register_mux(NULL, "gpt0_clk", gpt0_parents,
425 ARRAY_SIZE(gpt0_parents), 0, PERIP_CLK_CFG, 451 ARRAY_SIZE(gpt0_parents), CLK_SET_RATE_PARENT,
426 GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 452 PERIP_CLK_CFG, GPT0_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
427 clk_register_clkdev(clk, NULL, "gpt0"); 453 clk_register_clkdev(clk, NULL, "gpt0");
428 454
429 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl, 455 clk_register_gpt("gpt1_syn_clk", "pll1_clk", 0, PRSC1_CLK_CFG, gpt_rtbl,
430 ARRAY_SIZE(gpt_rtbl), &_lock); 456 ARRAY_SIZE(gpt_rtbl), &_lock);
431 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents, 457 clk = clk_register_mux(NULL, "gpt1_mclk", gpt1_parents,
432 ARRAY_SIZE(gpt1_parents), 0, PERIP_CLK_CFG, 458 ARRAY_SIZE(gpt1_parents), CLK_SET_RATE_PARENT,
433 GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 459 PERIP_CLK_CFG, GPT1_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
434 clk_register_clkdev(clk, "gpt1_mclk", NULL); 460 clk_register_clkdev(clk, "gpt1_mclk", NULL);
435 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk", 0, 461 clk = clk_register_gate(NULL, "gpt1_clk", "gpt1_mclk",
436 PERIP1_CLK_ENB, GPT1_CLK_ENB, 0, &_lock); 462 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT1_CLK_ENB, 0,
463 &_lock);
437 clk_register_clkdev(clk, NULL, "gpt1"); 464 clk_register_clkdev(clk, NULL, "gpt1");
438 465
439 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl, 466 clk_register_gpt("gpt2_syn_clk", "pll1_clk", 0, PRSC2_CLK_CFG, gpt_rtbl,
440 ARRAY_SIZE(gpt_rtbl), &_lock); 467 ARRAY_SIZE(gpt_rtbl), &_lock);
441 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents, 468 clk = clk_register_mux(NULL, "gpt2_mclk", gpt2_parents,
442 ARRAY_SIZE(gpt2_parents), 0, PERIP_CLK_CFG, 469 ARRAY_SIZE(gpt2_parents), CLK_SET_RATE_PARENT,
443 GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock); 470 PERIP_CLK_CFG, GPT2_CLK_SHIFT, GPT_CLK_MASK, 0, &_lock);
444 clk_register_clkdev(clk, "gpt2_mclk", NULL); 471 clk_register_clkdev(clk, "gpt2_mclk", NULL);
445 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk", 0, 472 clk = clk_register_gate(NULL, "gpt2_clk", "gpt2_mclk",
446 PERIP1_CLK_ENB, GPT2_CLK_ENB, 0, &_lock); 473 CLK_SET_RATE_PARENT, PERIP1_CLK_ENB, GPT2_CLK_ENB, 0,
474 &_lock);
447 clk_register_clkdev(clk, NULL, "gpt2"); 475 clk_register_clkdev(clk, NULL, "gpt2");
448 476
449 /* general synths clocks */ 477 /* general synths clocks */
@@ -480,7 +508,9 @@ void __init spear3xx_clk_init(void)
480 /* clock derived from pll3 clk */ 508 /* clock derived from pll3 clk */
481 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 509 clk = clk_register_gate(NULL, "usbh_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
482 USBH_CLK_ENB, 0, &_lock); 510 USBH_CLK_ENB, 0, &_lock);
483 clk_register_clkdev(clk, "usbh_clk", NULL); 511 clk_register_clkdev(clk, NULL, "e1800000.ehci");
512 clk_register_clkdev(clk, NULL, "e1900000.ohci");
513 clk_register_clkdev(clk, NULL, "e2100000.ohci");
484 514
485 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1, 515 clk = clk_register_fixed_factor(NULL, "usbh.0_clk", "usbh_clk", 0, 1,
486 1); 516 1);
@@ -492,7 +522,7 @@ void __init spear3xx_clk_init(void)
492 522
493 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 523 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
494 USBD_CLK_ENB, 0, &_lock); 524 USBD_CLK_ENB, 0, &_lock);
495 clk_register_clkdev(clk, NULL, "designware_udc"); 525 clk_register_clkdev(clk, NULL, "e1100000.usbd");
496 526
497 /* clock derived from ahb clk */ 527 /* clock derived from ahb clk */
498 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2, 528 clk = clk_register_fixed_factor(NULL, "ahbmult2_clk", "ahb_clk", 0, 2,
@@ -540,7 +570,7 @@ void __init spear3xx_clk_init(void)
540 /* clock derived from apb clk */ 570 /* clock derived from apb clk */
541 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB, 571 clk = clk_register_gate(NULL, "adc_clk", "apb_clk", 0, PERIP1_CLK_ENB,
542 ADC_CLK_ENB, 0, &_lock); 572 ADC_CLK_ENB, 0, &_lock);
543 clk_register_clkdev(clk, NULL, "adc"); 573 clk_register_clkdev(clk, NULL, "d0080000.adc");
544 574
545 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB, 575 clk = clk_register_gate(NULL, "gpio0_clk", "apb_clk", 0, PERIP1_CLK_ENB,
546 GPIO_CLK_ENB, 0, &_lock); 576 GPIO_CLK_ENB, 0, &_lock);
@@ -579,20 +609,24 @@ void __init spear3xx_clk_init(void)
579 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock); 609 RAS_CLK_ENB, RAS_48M_CLK_ENB, 0, &_lock);
580 clk_register_clkdev(clk, "ras_pll3_clk", NULL); 610 clk_register_clkdev(clk, "ras_pll3_clk", NULL);
581 611
582 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk", 0, 612 clk = clk_register_gate(NULL, "ras_syn0_gclk", "gen0_syn_gclk",
583 RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0, &_lock); 613 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT0_CLK_ENB, 0,
614 &_lock);
584 clk_register_clkdev(clk, "ras_syn0_gclk", NULL); 615 clk_register_clkdev(clk, "ras_syn0_gclk", NULL);
585 616
586 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk", 0, 617 clk = clk_register_gate(NULL, "ras_syn1_gclk", "gen1_syn_gclk",
587 RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0, &_lock); 618 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT1_CLK_ENB, 0,
619 &_lock);
588 clk_register_clkdev(clk, "ras_syn1_gclk", NULL); 620 clk_register_clkdev(clk, "ras_syn1_gclk", NULL);
589 621
590 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk", 0, 622 clk = clk_register_gate(NULL, "ras_syn2_gclk", "gen2_syn_gclk",
591 RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0, &_lock); 623 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT2_CLK_ENB, 0,
624 &_lock);
592 clk_register_clkdev(clk, "ras_syn2_gclk", NULL); 625 clk_register_clkdev(clk, "ras_syn2_gclk", NULL);
593 626
594 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk", 0, 627 clk = clk_register_gate(NULL, "ras_syn3_gclk", "gen3_syn_gclk",
595 RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0, &_lock); 628 CLK_SET_RATE_PARENT, RAS_CLK_ENB, RAS_SYNT3_CLK_ENB, 0,
629 &_lock);
596 clk_register_clkdev(clk, "ras_syn3_gclk", NULL); 630 clk_register_clkdev(clk, "ras_syn3_gclk", NULL);
597 631
598 if (of_machine_is_compatible("st,spear300")) 632 if (of_machine_is_compatible("st,spear300"))
diff --git a/drivers/clk/spear/spear6xx_clock.c b/drivers/clk/spear/spear6xx_clock.c
index a98d0866f541..e862a333ad30 100644
--- a/drivers/clk/spear/spear6xx_clock.c
+++ b/drivers/clk/spear/spear6xx_clock.c
@@ -92,6 +92,7 @@ static struct pll_rate_tbl pll_rtbl[] = {
92/* aux rate configuration table, in ascending order of rates */ 92/* aux rate configuration table, in ascending order of rates */
93static struct aux_rate_tbl aux_rtbl[] = { 93static struct aux_rate_tbl aux_rtbl[] = {
94 /* For PLL1 = 332 MHz */ 94 /* For PLL1 = 332 MHz */
95 {.xscale = 2, .yscale = 27, .eq = 0}, /* 12.296 MHz */
95 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */ 96 {.xscale = 2, .yscale = 8, .eq = 0}, /* 41.5 MHz */
96 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */ 97 {.xscale = 2, .yscale = 4, .eq = 0}, /* 83 MHz */
97 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */ 98 {.xscale = 1, .yscale = 2, .eq = 1}, /* 166 MHz */
@@ -118,9 +119,6 @@ void __init spear6xx_clk_init(void)
118{ 119{
119 struct clk *clk, *clk1; 120 struct clk *clk, *clk1;
120 121
121 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
122 clk_register_clkdev(clk, "apb_pclk", NULL);
123
124 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT, 122 clk = clk_register_fixed_rate(NULL, "osc_32k_clk", NULL, CLK_IS_ROOT,
125 32000); 123 32000);
126 clk_register_clkdev(clk, "osc_32k_clk", NULL); 124 clk_register_clkdev(clk, "osc_32k_clk", NULL);
@@ -156,7 +154,8 @@ void __init spear6xx_clk_init(void)
156 clk_register_clkdev(clk, NULL, "wdt"); 154 clk_register_clkdev(clk, NULL, "wdt");
157 155
158 /* clock derived from pll1 clk */ 156 /* clock derived from pll1 clk */
159 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk", 0, 1, 1); 157 clk = clk_register_fixed_factor(NULL, "cpu_clk", "pll1_clk",
158 CLK_SET_RATE_PARENT, 1, 1);
160 clk_register_clkdev(clk, "cpu_clk", NULL); 159 clk_register_clkdev(clk, "cpu_clk", NULL);
161 160
162 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk", 161 clk = clk_register_divider(NULL, "ahb_clk", "pll1_clk",
@@ -261,11 +260,13 @@ void __init spear6xx_clk_init(void)
261 /* clock derived from pll3 clk */ 260 /* clock derived from pll3 clk */
262 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0, 261 clk = clk_register_gate(NULL, "usbh0_clk", "pll3_clk", 0,
263 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock); 262 PERIP1_CLK_ENB, USBH0_CLK_ENB, 0, &_lock);
264 clk_register_clkdev(clk, NULL, "usbh.0_clk"); 263 clk_register_clkdev(clk, NULL, "e1800000.ehci");
264 clk_register_clkdev(clk, NULL, "e1900000.ohci");
265 265
266 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0, 266 clk = clk_register_gate(NULL, "usbh1_clk", "pll3_clk", 0,
267 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock); 267 PERIP1_CLK_ENB, USBH1_CLK_ENB, 0, &_lock);
268 clk_register_clkdev(clk, NULL, "usbh.1_clk"); 268 clk_register_clkdev(clk, NULL, "e2000000.ehci");
269 clk_register_clkdev(clk, NULL, "e2100000.ohci");
269 270
270 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB, 271 clk = clk_register_gate(NULL, "usbd_clk", "pll3_clk", 0, PERIP1_CLK_ENB,
271 USBD_CLK_ENB, 0, &_lock); 272 USBD_CLK_ENB, 0, &_lock);
diff --git a/drivers/clk/ux500/Makefile b/drivers/clk/ux500/Makefile
index 858fbfe66281..bcc0c11a507c 100644
--- a/drivers/clk/ux500/Makefile
+++ b/drivers/clk/ux500/Makefile
@@ -10,3 +10,6 @@ obj-y += clk-prcmu.o
10obj-y += u8500_clk.o 10obj-y += u8500_clk.o
11obj-y += u9540_clk.o 11obj-y += u9540_clk.o
12obj-y += u8540_clk.o 12obj-y += u8540_clk.o
13
14# ABX500 clock driver
15obj-y += abx500-clk.o
diff --git a/drivers/clk/ux500/abx500-clk.c b/drivers/clk/ux500/abx500-clk.c
new file mode 100644
index 000000000000..e27c52317ffe
--- /dev/null
+++ b/drivers/clk/ux500/abx500-clk.c
@@ -0,0 +1,73 @@
1/*
2 * abx500 clock implementation for ux500 platform.
3 *
4 * Copyright (C) 2012 ST-Ericsson SA
5 * Author: Ulf Hansson <ulf.hansson@linaro.org>
6 *
7 * License terms: GNU General Public License (GPL) version 2
8 */
9
10#include <linux/err.h>
11#include <linux/module.h>
12#include <linux/device.h>
13#include <linux/platform_device.h>
14#include <linux/mfd/abx500/ab8500.h>
15
16/* TODO: Add clock implementations here */
17
18
19/* Clock definitions for ab8500 */
20static int ab8500_reg_clks(struct device *dev)
21{
22 return 0;
23}
24
25/* Clock definitions for ab8540 */
26static int ab8540_reg_clks(struct device *dev)
27{
28 return 0;
29}
30
31/* Clock definitions for ab9540 */
32static int ab9540_reg_clks(struct device *dev)
33{
34 return 0;
35}
36
37static int __devinit abx500_clk_probe(struct platform_device *pdev)
38{
39 struct ab8500 *parent = dev_get_drvdata(pdev->dev.parent);
40 int ret;
41
42 if (is_ab8500(parent) || is_ab8505(parent)) {
43 ret = ab8500_reg_clks(&pdev->dev);
44 } else if (is_ab8540(parent)) {
45 ret = ab8540_reg_clks(&pdev->dev);
46 } else if (is_ab9540(parent)) {
47 ret = ab9540_reg_clks(&pdev->dev);
48 } else {
49 dev_err(&pdev->dev, "non supported plf id\n");
50 return -ENODEV;
51 }
52
53 return ret;
54}
55
56static struct platform_driver abx500_clk_driver = {
57 .driver = {
58 .name = "abx500-clk",
59 .owner = THIS_MODULE,
60 },
61 .probe = abx500_clk_probe,
62};
63
64static int __init abx500_clk_init(void)
65{
66 return platform_driver_register(&abx500_clk_driver);
67}
68
69arch_initcall(abx500_clk_init);
70
71MODULE_AUTHOR("Ulf Hansson <ulf.hansson@linaro.org");
72MODULE_DESCRIPTION("ABX500 clk driver");
73MODULE_LICENSE("GPL v2");
diff --git a/drivers/clk/ux500/clk-prcmu.c b/drivers/clk/ux500/clk-prcmu.c
index 930cdfeb47ab..74faa7e3cf59 100644
--- a/drivers/clk/ux500/clk-prcmu.c
+++ b/drivers/clk/ux500/clk-prcmu.c
@@ -133,6 +133,40 @@ out_error:
133 hw->init->name); 133 hw->init->name);
134} 134}
135 135
136static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw)
137{
138 int err;
139 struct clk_prcmu *clk = to_clk_prcmu(hw);
140
141 err = prcmu_request_ape_opp_100_voltage(true);
142 if (err) {
143 pr_err("clk_prcmu: %s failed to request APE OPP VOLT for %s.\n",
144 __func__, hw->init->name);
145 return err;
146 }
147
148 err = prcmu_request_clock(clk->cg_sel, true);
149 if (err)
150 prcmu_request_ape_opp_100_voltage(false);
151
152 return err;
153}
154
155static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw)
156{
157 struct clk_prcmu *clk = to_clk_prcmu(hw);
158
159 if (prcmu_request_clock(clk->cg_sel, false))
160 goto out_error;
161 if (prcmu_request_ape_opp_100_voltage(false))
162 goto out_error;
163 return;
164
165out_error:
166 pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
167 hw->init->name);
168}
169
136static struct clk_ops clk_prcmu_scalable_ops = { 170static struct clk_ops clk_prcmu_scalable_ops = {
137 .prepare = clk_prcmu_prepare, 171 .prepare = clk_prcmu_prepare,
138 .unprepare = clk_prcmu_unprepare, 172 .unprepare = clk_prcmu_unprepare,
@@ -153,6 +187,13 @@ static struct clk_ops clk_prcmu_gate_ops = {
153 .recalc_rate = clk_prcmu_recalc_rate, 187 .recalc_rate = clk_prcmu_recalc_rate,
154}; 188};
155 189
190static struct clk_ops clk_prcmu_scalable_rate_ops = {
191 .is_enabled = clk_prcmu_is_enabled,
192 .recalc_rate = clk_prcmu_recalc_rate,
193 .round_rate = clk_prcmu_round_rate,
194 .set_rate = clk_prcmu_set_rate,
195};
196
156static struct clk_ops clk_prcmu_rate_ops = { 197static struct clk_ops clk_prcmu_rate_ops = {
157 .is_enabled = clk_prcmu_is_enabled, 198 .is_enabled = clk_prcmu_is_enabled,
158 .recalc_rate = clk_prcmu_recalc_rate, 199 .recalc_rate = clk_prcmu_recalc_rate,
@@ -167,6 +208,17 @@ static struct clk_ops clk_prcmu_opp_gate_ops = {
167 .recalc_rate = clk_prcmu_recalc_rate, 208 .recalc_rate = clk_prcmu_recalc_rate,
168}; 209};
169 210
211static struct clk_ops clk_prcmu_opp_volt_scalable_ops = {
212 .prepare = clk_prcmu_opp_volt_prepare,
213 .unprepare = clk_prcmu_opp_volt_unprepare,
214 .enable = clk_prcmu_enable,
215 .disable = clk_prcmu_disable,
216 .is_enabled = clk_prcmu_is_enabled,
217 .recalc_rate = clk_prcmu_recalc_rate,
218 .round_rate = clk_prcmu_round_rate,
219 .set_rate = clk_prcmu_set_rate,
220};
221
170static struct clk *clk_reg_prcmu(const char *name, 222static struct clk *clk_reg_prcmu(const char *name,
171 const char *parent_name, 223 const char *parent_name,
172 u8 cg_sel, 224 u8 cg_sel,
@@ -233,6 +285,16 @@ struct clk *clk_reg_prcmu_gate(const char *name,
233 &clk_prcmu_gate_ops); 285 &clk_prcmu_gate_ops);
234} 286}
235 287
288struct clk *clk_reg_prcmu_scalable_rate(const char *name,
289 const char *parent_name,
290 u8 cg_sel,
291 unsigned long rate,
292 unsigned long flags)
293{
294 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
295 &clk_prcmu_scalable_rate_ops);
296}
297
236struct clk *clk_reg_prcmu_rate(const char *name, 298struct clk *clk_reg_prcmu_rate(const char *name,
237 const char *parent_name, 299 const char *parent_name,
238 u8 cg_sel, 300 u8 cg_sel,
@@ -250,3 +312,13 @@ struct clk *clk_reg_prcmu_opp_gate(const char *name,
250 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags, 312 return clk_reg_prcmu(name, parent_name, cg_sel, 0, flags,
251 &clk_prcmu_opp_gate_ops); 313 &clk_prcmu_opp_gate_ops);
252} 314}
315
316struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
317 const char *parent_name,
318 u8 cg_sel,
319 unsigned long rate,
320 unsigned long flags)
321{
322 return clk_reg_prcmu(name, parent_name, cg_sel, rate, flags,
323 &clk_prcmu_opp_volt_scalable_ops);
324}
diff --git a/drivers/clk/ux500/clk.h b/drivers/clk/ux500/clk.h
index 836d7d16751e..c3e449169a83 100644
--- a/drivers/clk/ux500/clk.h
+++ b/drivers/clk/ux500/clk.h
@@ -35,6 +35,12 @@ struct clk *clk_reg_prcmu_gate(const char *name,
35 u8 cg_sel, 35 u8 cg_sel,
36 unsigned long flags); 36 unsigned long flags);
37 37
38struct clk *clk_reg_prcmu_scalable_rate(const char *name,
39 const char *parent_name,
40 u8 cg_sel,
41 unsigned long rate,
42 unsigned long flags);
43
38struct clk *clk_reg_prcmu_rate(const char *name, 44struct clk *clk_reg_prcmu_rate(const char *name,
39 const char *parent_name, 45 const char *parent_name,
40 u8 cg_sel, 46 u8 cg_sel,
@@ -45,4 +51,10 @@ struct clk *clk_reg_prcmu_opp_gate(const char *name,
45 u8 cg_sel, 51 u8 cg_sel,
46 unsigned long flags); 52 unsigned long flags);
47 53
54struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
55 const char *parent_name,
56 u8 cg_sel,
57 unsigned long rate,
58 unsigned long flags);
59
48#endif /* __UX500_CLK_H */ 60#endif /* __UX500_CLK_H */
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index e2c17d187d98..7d0e0258f204 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -170,10 +170,11 @@ void u8500_clk_init(void)
170 clk_register_clkdev(clk, NULL, "mtu0"); 170 clk_register_clkdev(clk, NULL, "mtu0");
171 clk_register_clkdev(clk, NULL, "mtu1"); 171 clk_register_clkdev(clk, NULL, "mtu1");
172 172
173 clk = clk_reg_prcmu_gate("sdmmcclk", NULL, PRCMU_SDMMCCLK, CLK_IS_ROOT); 173 clk = clk_reg_prcmu_opp_volt_scalable("sdmmcclk", NULL, PRCMU_SDMMCCLK,
174 100000000,
175 CLK_IS_ROOT|CLK_SET_RATE_GATE);
174 clk_register_clkdev(clk, NULL, "sdmmc"); 176 clk_register_clkdev(clk, NULL, "sdmmc");
175 177
176
177 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk", 178 clk = clk_reg_prcmu_scalable("dsi_pll", "hdmiclk",
178 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE); 179 PRCMU_PLLDSI, 0, CLK_SET_RATE_GATE);
179 clk_register_clkdev(clk, "dsihs2", "mcde"); 180 clk_register_clkdev(clk, "dsihs2", "mcde");
@@ -205,16 +206,18 @@ void u8500_clk_init(void)
205 clk_register_clkdev(clk, "dsilp2", "dsilink.2"); 206 clk_register_clkdev(clk, "dsilp2", "dsilink.2");
206 clk_register_clkdev(clk, "dsilp2", "mcde"); 207 clk_register_clkdev(clk, "dsilp2", "mcde");
207 208
208 clk = clk_reg_prcmu_rate("smp_twd", NULL, PRCMU_ARMSS, 209 clk = clk_reg_prcmu_scalable_rate("armss", NULL,
209 CLK_IS_ROOT|CLK_GET_RATE_NOCACHE| 210 PRCMU_ARMSS, 0, CLK_IS_ROOT|CLK_IGNORE_UNUSED);
210 CLK_IGNORE_UNUSED); 211 clk_register_clkdev(clk, "armss", NULL);
212
213 clk = clk_register_fixed_factor(NULL, "smp_twd", "armss",
214 CLK_IGNORE_UNUSED, 1, 2);
211 clk_register_clkdev(clk, NULL, "smp_twd"); 215 clk_register_clkdev(clk, NULL, "smp_twd");
212 216
213 /* 217 /*
214 * FIXME: Add special handled PRCMU clocks here: 218 * FIXME: Add special handled PRCMU clocks here:
215 * 1. clk_arm, use PRCMU_ARMCLK. 219 * 1. clkout0yuv, use PRCMU as parent + need regulator + pinctrl.
216 * 2. clkout0yuv, use PRCMU as parent + need regulator + pinctrl. 220 * 2. ab9540_clkout1yuv, see clkout0yuv
217 * 3. ab9540_clkout1yuv, see clkout0yuv
218 */ 221 */
219 222
220 /* PRCC P-clocks */ 223 /* PRCC P-clocks */
@@ -323,7 +326,7 @@ void u8500_clk_init(void)
323 clk_register_clkdev(clk, NULL, "gpioblock1"); 326 clk_register_clkdev(clk, NULL, "gpioblock1");
324 327
325 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE, 328 clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", U8500_CLKRST2_BASE,
326 BIT(11), 0); 329 BIT(12), 0);
327 330
328 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE, 331 clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", U8500_CLKRST3_BASE,
329 BIT(0), 0); 332 BIT(0), 0);
@@ -347,6 +350,8 @@ void u8500_clk_init(void)
347 350
348 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE, 351 clk = clk_reg_prcc_pclk("p3_pclk5", "per3clk", U8500_CLKRST3_BASE,
349 BIT(5), 0); 352 BIT(5), 0);
353 clk_register_clkdev(clk, "apb_pclk", "ske");
354 clk_register_clkdev(clk, "apb_pclk", "nmk-ske-keypad");
350 355
351 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE, 356 clk = clk_reg_prcc_pclk("p3_pclk6", "per3clk", U8500_CLKRST3_BASE,
352 BIT(6), 0); 357 BIT(6), 0);
@@ -375,6 +380,7 @@ void u8500_clk_init(void)
375 380
376 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE, 381 clk = clk_reg_prcc_pclk("p6_pclk0", "per6clk", U8500_CLKRST6_BASE,
377 BIT(0), 0); 382 BIT(0), 0);
383 clk_register_clkdev(clk, "apb_pclk", "rng");
378 384
379 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE, 385 clk = clk_reg_prcc_pclk("p6_pclk1", "per6clk", U8500_CLKRST6_BASE,
380 BIT(1), 0); 386 BIT(1), 0);
@@ -503,6 +509,8 @@ void u8500_clk_init(void)
503 509
504 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k", 510 clk = clk_reg_prcc_kclk("p3_ske_kclk", "rtc32k",
505 U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE); 511 U8500_CLKRST3_BASE, BIT(5), CLK_SET_RATE_GATE);
512 clk_register_clkdev(clk, NULL, "ske");
513 clk_register_clkdev(clk, NULL, "nmk-ske-keypad");
506 514
507 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk", 515 clk = clk_reg_prcc_kclk("p3_uart2_kclk", "uartclk",
508 U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE); 516 U8500_CLKRST3_BASE, BIT(6), CLK_SET_RATE_GATE);
@@ -515,5 +523,5 @@ void u8500_clk_init(void)
515 /* Periph6 */ 523 /* Periph6 */
516 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk", 524 clk = clk_reg_prcc_kclk("p3_rng_kclk", "rngclk",
517 U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE); 525 U8500_CLKRST6_BASE, BIT(0), CLK_SET_RATE_GATE);
518 526 clk_register_clkdev(clk, NULL, "rng");
519} 527}
diff --git a/drivers/clk/versatile/Makefile b/drivers/clk/versatile/Makefile
index c0a0f6478798..ec3b88fe3e6d 100644
--- a/drivers/clk/versatile/Makefile
+++ b/drivers/clk/versatile/Makefile
@@ -1,4 +1,7 @@
1# Makefile for Versatile-specific clocks 1# Makefile for Versatile-specific clocks
2obj-$(CONFIG_ICST) += clk-icst.o 2obj-$(CONFIG_ICST) += clk-icst.o
3obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o 3obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o
4obj-$(CONFIG_INTEGRATOR_IMPD1) += clk-impd1.o
4obj-$(CONFIG_ARCH_REALVIEW) += clk-realview.o 5obj-$(CONFIG_ARCH_REALVIEW) += clk-realview.o
6obj-$(CONFIG_ARCH_VEXPRESS) += clk-vexpress.o
7obj-$(CONFIG_VEXPRESS_CONFIG) += clk-vexpress-osc.o
diff --git a/drivers/clk/versatile/clk-icst.c b/drivers/clk/versatile/clk-icst.c
index f555b50a5fa5..67ccf4aa7277 100644
--- a/drivers/clk/versatile/clk-icst.c
+++ b/drivers/clk/versatile/clk-icst.c
@@ -3,6 +3,12 @@
3 * We wrap the custom interface from <asm/hardware/icst.h> into the generic 3 * We wrap the custom interface from <asm/hardware/icst.h> into the generic
4 * clock framework. 4 * clock framework.
5 * 5 *
6 * Copyright (C) 2012 Linus Walleij
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
6 * TODO: when all ARM reference designs are migrated to generic clocks, the 12 * TODO: when all ARM reference designs are migrated to generic clocks, the
7 * ICST clock code from the ARM tree should probably be merged into this 13 * ICST clock code from the ARM tree should probably be merged into this
8 * file. 14 * file.
@@ -11,33 +17,74 @@
11#include <linux/clkdev.h> 17#include <linux/clkdev.h>
12#include <linux/err.h> 18#include <linux/err.h>
13#include <linux/clk-provider.h> 19#include <linux/clk-provider.h>
20#include <linux/io.h>
14 21
15#include "clk-icst.h" 22#include "clk-icst.h"
16 23
17/** 24/**
18 * struct clk_icst - ICST VCO clock wrapper 25 * struct clk_icst - ICST VCO clock wrapper
19 * @hw: corresponding clock hardware entry 26 * @hw: corresponding clock hardware entry
27 * @vcoreg: VCO register address
28 * @lockreg: VCO lock register address
20 * @params: parameters for this ICST instance 29 * @params: parameters for this ICST instance
21 * @rate: current rate 30 * @rate: current rate
22 * @setvco: function to commit ICST settings to hardware
23 */ 31 */
24struct clk_icst { 32struct clk_icst {
25 struct clk_hw hw; 33 struct clk_hw hw;
34 void __iomem *vcoreg;
35 void __iomem *lockreg;
26 const struct icst_params *params; 36 const struct icst_params *params;
27 unsigned long rate; 37 unsigned long rate;
28 struct icst_vco (*getvco)(void);
29 void (*setvco)(struct icst_vco);
30}; 38};
31 39
32#define to_icst(_hw) container_of(_hw, struct clk_icst, hw) 40#define to_icst(_hw) container_of(_hw, struct clk_icst, hw)
33 41
42/**
43 * vco_get() - get ICST VCO settings from a certain register
44 * @vcoreg: register containing the VCO settings
45 */
46static struct icst_vco vco_get(void __iomem *vcoreg)
47{
48 u32 val;
49 struct icst_vco vco;
50
51 val = readl(vcoreg);
52 vco.v = val & 0x1ff;
53 vco.r = (val >> 9) & 0x7f;
54 vco.s = (val >> 16) & 03;
55 return vco;
56}
57
58/**
59 * vco_set() - commit changes to an ICST VCO
60 * @locreg: register to poke to unlock the VCO for writing
61 * @vcoreg: register containing the VCO settings
62 * @vco: ICST VCO parameters to commit
63 */
64static void vco_set(void __iomem *lockreg,
65 void __iomem *vcoreg,
66 struct icst_vco vco)
67{
68 u32 val;
69
70 val = readl(vcoreg) & ~0x7ffff;
71 val |= vco.v | (vco.r << 9) | (vco.s << 16);
72
73 /* This magic unlocks the VCO so it can be controlled */
74 writel(0xa05f, lockreg);
75 writel(val, vcoreg);
76 /* This locks the VCO again */
77 writel(0, lockreg);
78}
79
80
34static unsigned long icst_recalc_rate(struct clk_hw *hw, 81static unsigned long icst_recalc_rate(struct clk_hw *hw,
35 unsigned long parent_rate) 82 unsigned long parent_rate)
36{ 83{
37 struct clk_icst *icst = to_icst(hw); 84 struct clk_icst *icst = to_icst(hw);
38 struct icst_vco vco; 85 struct icst_vco vco;
39 86
40 vco = icst->getvco(); 87 vco = vco_get(icst->vcoreg);
41 icst->rate = icst_hz(icst->params, vco); 88 icst->rate = icst_hz(icst->params, vco);
42 return icst->rate; 89 return icst->rate;
43} 90}
@@ -60,7 +107,7 @@ static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
60 107
61 vco = icst_hz_to_vco(icst->params, rate); 108 vco = icst_hz_to_vco(icst->params, rate);
62 icst->rate = icst_hz(icst->params, vco); 109 icst->rate = icst_hz(icst->params, vco);
63 icst->setvco(vco); 110 vco_set(icst->vcoreg, icst->lockreg, vco);
64 return 0; 111 return 0;
65} 112}
66 113
@@ -70,8 +117,9 @@ static const struct clk_ops icst_ops = {
70 .set_rate = icst_set_rate, 117 .set_rate = icst_set_rate,
71}; 118};
72 119
73struct clk * __init icst_clk_register(struct device *dev, 120struct clk *icst_clk_register(struct device *dev,
74 const struct clk_icst_desc *desc) 121 const struct clk_icst_desc *desc,
122 void __iomem *base)
75{ 123{
76 struct clk *clk; 124 struct clk *clk;
77 struct clk_icst *icst; 125 struct clk_icst *icst;
@@ -89,8 +137,8 @@ struct clk * __init icst_clk_register(struct device *dev,
89 init.num_parents = 0; 137 init.num_parents = 0;
90 icst->hw.init = &init; 138 icst->hw.init = &init;
91 icst->params = desc->params; 139 icst->params = desc->params;
92 icst->getvco = desc->getvco; 140 icst->vcoreg = base + desc->vco_offset;
93 icst->setvco = desc->setvco; 141 icst->lockreg = base + desc->lock_offset;
94 142
95 clk = clk_register(dev, &icst->hw); 143 clk = clk_register(dev, &icst->hw);
96 if (IS_ERR(clk)) 144 if (IS_ERR(clk))
diff --git a/drivers/clk/versatile/clk-icst.h b/drivers/clk/versatile/clk-icst.h
index 71b4c56c1410..dad51b6ffd00 100644
--- a/drivers/clk/versatile/clk-icst.h
+++ b/drivers/clk/versatile/clk-icst.h
@@ -1,10 +1,18 @@
1#include <asm/hardware/icst.h> 1#include <asm/hardware/icst.h>
2 2
3/**
4 * struct clk_icst_desc - descriptor for the ICST VCO
5 * @params: ICST parameters
6 * @vco_offset: offset to the ICST VCO from the provided memory base
7 * @lock_offset: offset to the ICST VCO locking register from the provided
8 * memory base
9 */
3struct clk_icst_desc { 10struct clk_icst_desc {
4 const struct icst_params *params; 11 const struct icst_params *params;
5 struct icst_vco (*getvco)(void); 12 u32 vco_offset;
6 void (*setvco)(struct icst_vco); 13 u32 lock_offset;
7}; 14};
8 15
9struct clk *icst_clk_register(struct device *dev, 16struct clk *icst_clk_register(struct device *dev,
10 const struct clk_icst_desc *desc); 17 const struct clk_icst_desc *desc,
18 void __iomem *base);
diff --git a/drivers/clk/versatile/clk-impd1.c b/drivers/clk/versatile/clk-impd1.c
new file mode 100644
index 000000000000..369139af2a3b
--- /dev/null
+++ b/drivers/clk/versatile/clk-impd1.c
@@ -0,0 +1,97 @@
1/*
2 * Clock driver for the ARM Integrator/IM-PD1 board
3 * Copyright (C) 2012 Linus Walleij
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/clk-provider.h>
10#include <linux/clk.h>
11#include <linux/clkdev.h>
12#include <linux/err.h>
13#include <linux/io.h>
14#include <linux/platform_data/clk-integrator.h>
15
16#include <mach/impd1.h>
17
18#include "clk-icst.h"
19
20struct impd1_clk {
21 struct clk *vcoclk;
22 struct clk *uartclk;
23 struct clk_lookup *clks[3];
24};
25
26static struct impd1_clk impd1_clks[4];
27
28/*
29 * There are two VCO's on the IM-PD1 but only one is used by the
30 * kernel, that is why we are only implementing the control of
31 * IMPD1_OSC1 here.
32 */
33
34static const struct icst_params impd1_vco_params = {
35 .ref = 24000000, /* 24 MHz */
36 .vco_max = ICST525_VCO_MAX_3V,
37 .vco_min = ICST525_VCO_MIN,
38 .vd_min = 12,
39 .vd_max = 519,
40 .rd_min = 3,
41 .rd_max = 120,
42 .s2div = icst525_s2div,
43 .idx2s = icst525_idx2s,
44};
45
46static const struct clk_icst_desc impd1_icst1_desc = {
47 .params = &impd1_vco_params,
48 .vco_offset = IMPD1_OSC1,
49 .lock_offset = IMPD1_LOCK,
50};
51
52/**
53 * integrator_impd1_clk_init() - set up the integrator clock tree
54 * @base: base address of the logic module (LM)
55 * @id: the ID of this LM
56 */
57void integrator_impd1_clk_init(void __iomem *base, unsigned int id)
58{
59 struct impd1_clk *imc;
60 struct clk *clk;
61 int i;
62
63 if (id > 3) {
64 pr_crit("no more than 4 LMs can be attached\n");
65 return;
66 }
67 imc = &impd1_clks[id];
68
69 clk = icst_clk_register(NULL, &impd1_icst1_desc, base);
70 imc->vcoclk = clk;
71 imc->clks[0] = clkdev_alloc(clk, NULL, "lm%x:01000", id);
72
73 /* UART reference clock */
74 clk = clk_register_fixed_rate(NULL, "uartclk", NULL, CLK_IS_ROOT,
75 14745600);
76 imc->uartclk = clk;
77 imc->clks[1] = clkdev_alloc(clk, NULL, "lm%x:00100", id);
78 imc->clks[2] = clkdev_alloc(clk, NULL, "lm%x:00200", id);
79
80 for (i = 0; i < ARRAY_SIZE(imc->clks); i++)
81 clkdev_add(imc->clks[i]);
82}
83
84void integrator_impd1_clk_exit(unsigned int id)
85{
86 int i;
87 struct impd1_clk *imc;
88
89 if (id > 3)
90 return;
91 imc = &impd1_clks[id];
92
93 for (i = 0; i < ARRAY_SIZE(imc->clks); i++)
94 clkdev_drop(imc->clks[i]);
95 clk_unregister(imc->uartclk);
96 clk_unregister(imc->vcoclk);
97}
diff --git a/drivers/clk/versatile/clk-integrator.c b/drivers/clk/versatile/clk-integrator.c
index a5053921bf7f..08593b4ee2c9 100644
--- a/drivers/clk/versatile/clk-integrator.c
+++ b/drivers/clk/versatile/clk-integrator.c
@@ -1,8 +1,16 @@
1/*
2 * Clock driver for the ARM Integrator/AP and Integrator/CP boards
3 * Copyright (C) 2012 Linus Walleij
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
9#include <linux/clk-provider.h>
1#include <linux/clk.h> 10#include <linux/clk.h>
2#include <linux/clkdev.h> 11#include <linux/clkdev.h>
3#include <linux/err.h> 12#include <linux/err.h>
4#include <linux/io.h> 13#include <linux/platform_data/clk-integrator.h>
5#include <linux/clk-provider.h>
6 14
7#include <mach/hardware.h> 15#include <mach/hardware.h>
8#include <mach/platform.h> 16#include <mach/platform.h>
@@ -14,42 +22,6 @@
14 * Inspired by portions of: 22 * Inspired by portions of:
15 * plat-versatile/clock.c and plat-versatile/include/plat/clock.h 23 * plat-versatile/clock.c and plat-versatile/include/plat/clock.h
16 */ 24 */
17#define CM_LOCK (__io_address(INTEGRATOR_HDR_BASE)+INTEGRATOR_HDR_LOCK_OFFSET)
18#define CM_AUXOSC (__io_address(INTEGRATOR_HDR_BASE)+0x1c)
19
20/**
21 * cp_auxvco_get() - get ICST VCO settings for the Integrator/CP
22 * @vco: ICST VCO parameters to update with hardware status
23 */
24static struct icst_vco cp_auxvco_get(void)
25{
26 u32 val;
27 struct icst_vco vco;
28
29 val = readl(CM_AUXOSC);
30 vco.v = val & 0x1ff;
31 vco.r = (val >> 9) & 0x7f;
32 vco.s = (val >> 16) & 03;
33 return vco;
34}
35
36/**
37 * cp_auxvco_set() - commit changes to Integrator/CP ICST VCO
38 * @vco: ICST VCO parameters to commit
39 */
40static void cp_auxvco_set(struct icst_vco vco)
41{
42 u32 val;
43
44 val = readl(CM_AUXOSC) & ~0x7ffff;
45 val |= vco.v | (vco.r << 9) | (vco.s << 16);
46
47 /* This magic unlocks the CM VCO so it can be controlled */
48 writel(0xa05f, CM_LOCK);
49 writel(val, CM_AUXOSC);
50 /* This locks the CM again */
51 writel(0, CM_LOCK);
52}
53 25
54static const struct icst_params cp_auxvco_params = { 26static const struct icst_params cp_auxvco_params = {
55 .ref = 24000000, 27 .ref = 24000000,
@@ -65,8 +37,8 @@ static const struct icst_params cp_auxvco_params = {
65 37
66static const struct clk_icst_desc __initdata cp_icst_desc = { 38static const struct clk_icst_desc __initdata cp_icst_desc = {
67 .params = &cp_auxvco_params, 39 .params = &cp_auxvco_params,
68 .getvco = cp_auxvco_get, 40 .vco_offset = 0x1c,
69 .setvco = cp_auxvco_set, 41 .lock_offset = INTEGRATOR_HDR_LOCK_OFFSET,
70}; 42};
71 43
72/* 44/*
@@ -106,6 +78,7 @@ void __init integrator_clk_init(bool is_cp)
106 clk_register_clkdev(clk, NULL, "sp804"); 78 clk_register_clkdev(clk, NULL, "sp804");
107 79
108 /* ICST VCO clock used on the Integrator/CP CLCD */ 80 /* ICST VCO clock used on the Integrator/CP CLCD */
109 clk = icst_clk_register(NULL, &cp_icst_desc); 81 clk = icst_clk_register(NULL, &cp_icst_desc,
82 __io_address(INTEGRATOR_HDR_BASE));
110 clk_register_clkdev(clk, NULL, "clcd"); 83 clk_register_clkdev(clk, NULL, "clcd");
111} 84}
diff --git a/drivers/clk/versatile/clk-realview.c b/drivers/clk/versatile/clk-realview.c
index e21a99cef378..cda07e70a408 100644
--- a/drivers/clk/versatile/clk-realview.c
+++ b/drivers/clk/versatile/clk-realview.c
@@ -1,3 +1,11 @@
1/*
2 * Clock driver for the ARM RealView boards
3 * Copyright (C) 2012 Linus Walleij
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */
1#include <linux/clk.h> 9#include <linux/clk.h>
2#include <linux/clkdev.h> 10#include <linux/clkdev.h>
3#include <linux/err.h> 11#include <linux/err.h>
@@ -13,38 +21,6 @@
13 * Implementation of the ARM RealView clock trees. 21 * Implementation of the ARM RealView clock trees.
14 */ 22 */
15 23
16static void __iomem *sys_lock;
17static void __iomem *sys_vcoreg;
18
19/**
20 * realview_oscvco_get() - get ICST OSC settings for the RealView
21 */
22static struct icst_vco realview_oscvco_get(void)
23{
24 u32 val;
25 struct icst_vco vco;
26
27 val = readl(sys_vcoreg);
28 vco.v = val & 0x1ff;
29 vco.r = (val >> 9) & 0x7f;
30 vco.s = (val >> 16) & 03;
31 return vco;
32}
33
34static void realview_oscvco_set(struct icst_vco vco)
35{
36 u32 val;
37
38 val = readl(sys_vcoreg) & ~0x7ffff;
39 val |= vco.v | (vco.r << 9) | (vco.s << 16);
40
41 /* This magic unlocks the CM VCO so it can be controlled */
42 writel(0xa05f, sys_lock);
43 writel(val, sys_vcoreg);
44 /* This locks the CM again */
45 writel(0, sys_lock);
46}
47
48static const struct icst_params realview_oscvco_params = { 24static const struct icst_params realview_oscvco_params = {
49 .ref = 24000000, 25 .ref = 24000000,
50 .vco_max = ICST307_VCO_MAX, 26 .vco_max = ICST307_VCO_MAX,
@@ -57,10 +33,16 @@ static const struct icst_params realview_oscvco_params = {
57 .idx2s = icst307_idx2s, 33 .idx2s = icst307_idx2s,
58}; 34};
59 35
60static const struct clk_icst_desc __initdata realview_icst_desc = { 36static const struct clk_icst_desc __initdata realview_osc0_desc = {
37 .params = &realview_oscvco_params,
38 .vco_offset = REALVIEW_SYS_OSC0_OFFSET,
39 .lock_offset = REALVIEW_SYS_LOCK_OFFSET,
40};
41
42static const struct clk_icst_desc __initdata realview_osc4_desc = {
61 .params = &realview_oscvco_params, 43 .params = &realview_oscvco_params,
62 .getvco = realview_oscvco_get, 44 .vco_offset = REALVIEW_SYS_OSC4_OFFSET,
63 .setvco = realview_oscvco_set, 45 .lock_offset = REALVIEW_SYS_LOCK_OFFSET,
64}; 46};
65 47
66/* 48/*
@@ -70,13 +52,6 @@ void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176)
70{ 52{
71 struct clk *clk; 53 struct clk *clk;
72 54
73 sys_lock = sysbase + REALVIEW_SYS_LOCK_OFFSET;
74 if (is_pb1176)
75 sys_vcoreg = sysbase + REALVIEW_SYS_OSC0_OFFSET;
76 else
77 sys_vcoreg = sysbase + REALVIEW_SYS_OSC4_OFFSET;
78
79
80 /* APB clock dummy */ 55 /* APB clock dummy */
81 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0); 56 clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
82 clk_register_clkdev(clk, "apb_pclk", NULL); 57 clk_register_clkdev(clk, "apb_pclk", NULL);
@@ -108,7 +83,11 @@ void __init realview_clk_init(void __iomem *sysbase, bool is_pb1176)
108 clk_register_clkdev(clk, NULL, "sp804"); 83 clk_register_clkdev(clk, NULL, "sp804");
109 84
110 /* ICST VCO clock */ 85 /* ICST VCO clock */
111 clk = icst_clk_register(NULL, &realview_icst_desc); 86 if (is_pb1176)
87 clk = icst_clk_register(NULL, &realview_osc0_desc, sysbase);
88 else
89 clk = icst_clk_register(NULL, &realview_osc4_desc, sysbase);
90
112 clk_register_clkdev(clk, NULL, "dev:clcd"); 91 clk_register_clkdev(clk, NULL, "dev:clcd");
113 clk_register_clkdev(clk, NULL, "issp:clcd"); 92 clk_register_clkdev(clk, NULL, "issp:clcd");
114} 93}
diff --git a/drivers/clk/versatile/clk-vexpress-osc.c b/drivers/clk/versatile/clk-vexpress-osc.c
new file mode 100644
index 000000000000..dcb6ae0a0425
--- /dev/null
+++ b/drivers/clk/versatile/clk-vexpress-osc.c
@@ -0,0 +1,146 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2012 ARM Limited
12 */
13
14#define pr_fmt(fmt) "vexpress-osc: " fmt
15
16#include <linux/clkdev.h>
17#include <linux/clk-provider.h>
18#include <linux/err.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/slab.h>
22#include <linux/vexpress.h>
23
24struct vexpress_osc {
25 struct vexpress_config_func *func;
26 struct clk_hw hw;
27 unsigned long rate_min;
28 unsigned long rate_max;
29};
30
31#define to_vexpress_osc(osc) container_of(osc, struct vexpress_osc, hw)
32
33static unsigned long vexpress_osc_recalc_rate(struct clk_hw *hw,
34 unsigned long parent_rate)
35{
36 struct vexpress_osc *osc = to_vexpress_osc(hw);
37 u32 rate;
38
39 vexpress_config_read(osc->func, 0, &rate);
40
41 return rate;
42}
43
44static long vexpress_osc_round_rate(struct clk_hw *hw, unsigned long rate,
45 unsigned long *parent_rate)
46{
47 struct vexpress_osc *osc = to_vexpress_osc(hw);
48
49 if (WARN_ON(osc->rate_min && rate < osc->rate_min))
50 rate = osc->rate_min;
51
52 if (WARN_ON(osc->rate_max && rate > osc->rate_max))
53 rate = osc->rate_max;
54
55 return rate;
56}
57
58static int vexpress_osc_set_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long parent_rate)
60{
61 struct vexpress_osc *osc = to_vexpress_osc(hw);
62
63 return vexpress_config_write(osc->func, 0, rate);
64}
65
66static struct clk_ops vexpress_osc_ops = {
67 .recalc_rate = vexpress_osc_recalc_rate,
68 .round_rate = vexpress_osc_round_rate,
69 .set_rate = vexpress_osc_set_rate,
70};
71
72
73struct clk * __init vexpress_osc_setup(struct device *dev)
74{
75 struct clk_init_data init;
76 struct vexpress_osc *osc = kzalloc(sizeof(*osc), GFP_KERNEL);
77
78 if (!osc)
79 return NULL;
80
81 osc->func = vexpress_config_func_get_by_dev(dev);
82 if (!osc->func) {
83 kfree(osc);
84 return NULL;
85 }
86
87 init.name = dev_name(dev);
88 init.ops = &vexpress_osc_ops;
89 init.flags = CLK_IS_ROOT;
90 init.num_parents = 0;
91 osc->hw.init = &init;
92
93 return clk_register(NULL, &osc->hw);
94}
95
96void __init vexpress_osc_of_setup(struct device_node *node)
97{
98 struct clk_init_data init;
99 struct vexpress_osc *osc;
100 struct clk *clk;
101 u32 range[2];
102
103 osc = kzalloc(sizeof(*osc), GFP_KERNEL);
104 if (!osc)
105 goto error;
106
107 osc->func = vexpress_config_func_get_by_node(node);
108 if (!osc->func) {
109 pr_err("Failed to obtain config func for node '%s'!\n",
110 node->name);
111 goto error;
112 }
113
114 if (of_property_read_u32_array(node, "freq-range", range,
115 ARRAY_SIZE(range)) == 0) {
116 osc->rate_min = range[0];
117 osc->rate_max = range[1];
118 }
119
120 of_property_read_string(node, "clock-output-names", &init.name);
121 if (!init.name)
122 init.name = node->name;
123
124 init.ops = &vexpress_osc_ops;
125 init.flags = CLK_IS_ROOT;
126 init.num_parents = 0;
127
128 osc->hw.init = &init;
129
130 clk = clk_register(NULL, &osc->hw);
131 if (IS_ERR(clk)) {
132 pr_err("Failed to register clock '%s'!\n", init.name);
133 goto error;
134 }
135
136 of_clk_add_provider(node, of_clk_src_simple_get, clk);
137
138 pr_debug("Registered clock '%s'\n", init.name);
139
140 return;
141
142error:
143 if (osc->func)
144 vexpress_config_func_put(osc->func);
145 kfree(osc);
146}
diff --git a/drivers/clk/versatile/clk-vexpress.c b/drivers/clk/versatile/clk-vexpress.c
new file mode 100644
index 000000000000..c742ac7c60bb
--- /dev/null
+++ b/drivers/clk/versatile/clk-vexpress.c
@@ -0,0 +1,142 @@
1/*
2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License version 2 as
4 * published by the Free Software Foundation.
5 *
6 * This program is distributed in the hope that it will be useful,
7 * but WITHOUT ANY WARRANTY; without even the implied warranty of
8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
9 * GNU General Public License for more details.
10 *
11 * Copyright (C) 2012 ARM Limited
12 */
13
14#include <linux/clkdev.h>
15#include <linux/clk-provider.h>
16#include <linux/err.h>
17#include <linux/of.h>
18#include <linux/of_address.h>
19#include <linux/vexpress.h>
20
21#include <asm/hardware/sp810.h>
22
23static struct clk *vexpress_sp810_timerclken[4];
24static DEFINE_SPINLOCK(vexpress_sp810_lock);
25
26static void __init vexpress_sp810_init(void __iomem *base)
27{
28 int i;
29
30 if (WARN_ON(!base))
31 return;
32
33 for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++) {
34 char name[12];
35 const char *parents[] = {
36 "v2m:refclk32khz", /* REFCLK */
37 "v2m:refclk1mhz" /* TIMCLK */
38 };
39
40 snprintf(name, ARRAY_SIZE(name), "timerclken%d", i);
41
42 vexpress_sp810_timerclken[i] = clk_register_mux(NULL, name,
43 parents, 2, 0, base + SCCTRL,
44 SCCTRL_TIMERENnSEL_SHIFT(i), 1,
45 0, &vexpress_sp810_lock);
46
47 if (WARN_ON(IS_ERR(vexpress_sp810_timerclken[i])))
48 break;
49 }
50}
51
52
53static const char * const vexpress_clk_24mhz_periphs[] __initconst = {
54 "mb:uart0", "mb:uart1", "mb:uart2", "mb:uart3",
55 "mb:mmci", "mb:kmi0", "mb:kmi1"
56};
57
58void __init vexpress_clk_init(void __iomem *sp810_base)
59{
60 struct clk *clk;
61 int i;
62
63 clk = clk_register_fixed_rate(NULL, "dummy_apb_pclk", NULL,
64 CLK_IS_ROOT, 0);
65 WARN_ON(clk_register_clkdev(clk, "apb_pclk", NULL));
66
67 clk = clk_register_fixed_rate(NULL, "v2m:clk_24mhz", NULL,
68 CLK_IS_ROOT, 24000000);
69 for (i = 0; i < ARRAY_SIZE(vexpress_clk_24mhz_periphs); i++)
70 WARN_ON(clk_register_clkdev(clk, NULL,
71 vexpress_clk_24mhz_periphs[i]));
72
73 clk = clk_register_fixed_rate(NULL, "v2m:refclk32khz", NULL,
74 CLK_IS_ROOT, 32768);
75 WARN_ON(clk_register_clkdev(clk, NULL, "v2m:wdt"));
76
77 clk = clk_register_fixed_rate(NULL, "v2m:refclk1mhz", NULL,
78 CLK_IS_ROOT, 1000000);
79
80 vexpress_sp810_init(sp810_base);
81
82 for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++)
83 WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i], clk));
84
85 WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0],
86 "v2m-timer0", "sp804"));
87 WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1],
88 "v2m-timer1", "sp804"));
89}
90
91#if defined(CONFIG_OF)
92
93struct clk *vexpress_sp810_of_get(struct of_phandle_args *clkspec, void *data)
94{
95 if (WARN_ON(clkspec->args_count != 1 || clkspec->args[0] >
96 ARRAY_SIZE(vexpress_sp810_timerclken)))
97 return NULL;
98
99 return vexpress_sp810_timerclken[clkspec->args[0]];
100}
101
102static const __initconst struct of_device_id vexpress_fixed_clk_match[] = {
103 { .compatible = "fixed-clock", .data = of_fixed_clk_setup, },
104 { .compatible = "arm,vexpress-osc", .data = vexpress_osc_of_setup, },
105 {}
106};
107
108void __init vexpress_clk_of_init(void)
109{
110 struct device_node *node;
111 struct clk *clk;
112 struct clk *refclk, *timclk;
113
114 of_clk_init(vexpress_fixed_clk_match);
115
116 node = of_find_compatible_node(NULL, NULL, "arm,sp810");
117 vexpress_sp810_init(of_iomap(node, 0));
118 of_clk_add_provider(node, vexpress_sp810_of_get, NULL);
119
120 /* Select "better" (faster) parent for SP804 timers */
121 refclk = of_clk_get_by_name(node, "refclk");
122 timclk = of_clk_get_by_name(node, "timclk");
123 if (!WARN_ON(IS_ERR(refclk) || IS_ERR(timclk))) {
124 int i = 0;
125
126 if (clk_get_rate(refclk) > clk_get_rate(timclk))
127 clk = refclk;
128 else
129 clk = timclk;
130
131 for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++)
132 WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i],
133 clk));
134 }
135
136 WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0],
137 "v2m-timer0", "sp804"));
138 WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1],
139 "v2m-timer1", "sp804"));
140}
141
142#endif
diff --git a/drivers/cpufreq/db8500-cpufreq.c b/drivers/cpufreq/db8500-cpufreq.c
index 74b830b635a6..4f154bc0ebe4 100644
--- a/drivers/cpufreq/db8500-cpufreq.c
+++ b/drivers/cpufreq/db8500-cpufreq.c
@@ -8,43 +8,17 @@
8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com> 8 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
9 * 9 *
10 */ 10 */
11#include <linux/module.h>
11#include <linux/kernel.h> 12#include <linux/kernel.h>
12#include <linux/cpufreq.h> 13#include <linux/cpufreq.h>
13#include <linux/delay.h> 14#include <linux/delay.h>
14#include <linux/slab.h> 15#include <linux/slab.h>
15#include <linux/mfd/dbx500-prcmu.h> 16#include <linux/platform_device.h>
17#include <linux/clk.h>
16#include <mach/id.h> 18#include <mach/id.h>
17 19
18static struct cpufreq_frequency_table freq_table[] = { 20static struct cpufreq_frequency_table *freq_table;
19 [0] = { 21static struct clk *armss_clk;
20 .index = 0,
21 .frequency = 200000,
22 },
23 [1] = {
24 .index = 1,
25 .frequency = 400000,
26 },
27 [2] = {
28 .index = 2,
29 .frequency = 800000,
30 },
31 [3] = {
32 /* Used for MAX_OPP, if available */
33 .index = 3,
34 .frequency = CPUFREQ_TABLE_END,
35 },
36 [4] = {
37 .index = 4,
38 .frequency = CPUFREQ_TABLE_END,
39 },
40};
41
42static enum arm_opp idx2opp[] = {
43 ARM_EXTCLK,
44 ARM_50_OPP,
45 ARM_100_OPP,
46 ARM_MAX_OPP
47};
48 22
49static struct freq_attr *db8500_cpufreq_attr[] = { 23static struct freq_attr *db8500_cpufreq_attr[] = {
50 &cpufreq_freq_attr_scaling_available_freqs, 24 &cpufreq_freq_attr_scaling_available_freqs,
@@ -85,9 +59,9 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy,
85 for_each_cpu(freqs.cpu, policy->cpus) 59 for_each_cpu(freqs.cpu, policy->cpus)
86 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE); 60 cpufreq_notify_transition(&freqs, CPUFREQ_PRECHANGE);
87 61
88 /* request the PRCM unit for opp change */ 62 /* update armss clk frequency */
89 if (prcmu_set_arm_opp(idx2opp[idx])) { 63 if (clk_set_rate(armss_clk, freq_table[idx].frequency * 1000)) {
90 pr_err("db8500-cpufreq: Failed to set OPP level\n"); 64 pr_err("db8500-cpufreq: Failed to update armss clk\n");
91 return -EINVAL; 65 return -EINVAL;
92 } 66 }
93 67
@@ -100,25 +74,36 @@ static int db8500_cpufreq_target(struct cpufreq_policy *policy,
100 74
101static unsigned int db8500_cpufreq_getspeed(unsigned int cpu) 75static unsigned int db8500_cpufreq_getspeed(unsigned int cpu)
102{ 76{
103 int i; 77 int i = 0;
104 /* request the prcm to get the current ARM opp */ 78 unsigned long freq = clk_get_rate(armss_clk) / 1000;
105 for (i = 0; prcmu_get_arm_opp() != idx2opp[i]; i++) 79
106 ; 80 while (freq_table[i].frequency != CPUFREQ_TABLE_END) {
107 return freq_table[i].frequency; 81 if (freq <= freq_table[i].frequency)
82 return freq_table[i].frequency;
83 i++;
84 }
85
86 /* We could not find a corresponding frequency. */
87 pr_err("db8500-cpufreq: Failed to find cpufreq speed\n");
88 return 0;
108} 89}
109 90
110static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy) 91static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy)
111{ 92{
112 int i, res; 93 int i = 0;
113 94 int res;
114 BUILD_BUG_ON(ARRAY_SIZE(idx2opp) + 1 != ARRAY_SIZE(freq_table));
115 95
116 if (prcmu_has_arm_maxopp()) 96 armss_clk = clk_get(NULL, "armss");
117 freq_table[3].frequency = 1000000; 97 if (IS_ERR(armss_clk)) {
98 pr_err("db8500-cpufreq : Failed to get armss clk\n");
99 return PTR_ERR(armss_clk);
100 }
118 101
119 pr_info("db8500-cpufreq : Available frequencies:\n"); 102 pr_info("db8500-cpufreq : Available frequencies:\n");
120 for (i = 0; freq_table[i].frequency != CPUFREQ_TABLE_END; i++) 103 while (freq_table[i].frequency != CPUFREQ_TABLE_END) {
121 pr_info(" %d Mhz\n", freq_table[i].frequency/1000); 104 pr_info(" %d Mhz\n", freq_table[i].frequency/1000);
105 i++;
106 }
122 107
123 /* get policy fields based on the table */ 108 /* get policy fields based on the table */
124 res = cpufreq_frequency_table_cpuinfo(policy, freq_table); 109 res = cpufreq_frequency_table_cpuinfo(policy, freq_table);
@@ -126,6 +111,7 @@ static int __cpuinit db8500_cpufreq_init(struct cpufreq_policy *policy)
126 cpufreq_frequency_table_get_attr(freq_table, policy->cpu); 111 cpufreq_frequency_table_get_attr(freq_table, policy->cpu);
127 else { 112 else {
128 pr_err("db8500-cpufreq : Failed to read policy table\n"); 113 pr_err("db8500-cpufreq : Failed to read policy table\n");
114 clk_put(armss_clk);
129 return res; 115 return res;
130 } 116 }
131 117
@@ -159,12 +145,35 @@ static struct cpufreq_driver db8500_cpufreq_driver = {
159 .attr = db8500_cpufreq_attr, 145 .attr = db8500_cpufreq_attr,
160}; 146};
161 147
148static int db8500_cpufreq_probe(struct platform_device *pdev)
149{
150 freq_table = dev_get_platdata(&pdev->dev);
151
152 if (!freq_table) {
153 pr_err("db8500-cpufreq: Failed to fetch cpufreq table\n");
154 return -ENODEV;
155 }
156
157 return cpufreq_register_driver(&db8500_cpufreq_driver);
158}
159
160static struct platform_driver db8500_cpufreq_plat_driver = {
161 .driver = {
162 .name = "cpufreq-u8500",
163 .owner = THIS_MODULE,
164 },
165 .probe = db8500_cpufreq_probe,
166};
167
162static int __init db8500_cpufreq_register(void) 168static int __init db8500_cpufreq_register(void)
163{ 169{
164 if (!cpu_is_u8500_family()) 170 if (!cpu_is_u8500_family())
165 return -ENODEV; 171 return -ENODEV;
166 172
167 pr_info("cpufreq for DB8500 started\n"); 173 pr_info("cpufreq for DB8500 started\n");
168 return cpufreq_register_driver(&db8500_cpufreq_driver); 174 return platform_driver_register(&db8500_cpufreq_plat_driver);
169} 175}
170device_initcall(db8500_cpufreq_register); 176device_initcall(db8500_cpufreq_register);
177
178MODULE_LICENSE("GPL v2");
179MODULE_DESCRIPTION("cpufreq driver for DB8500");
diff --git a/drivers/mfd/db8500-prcmu.c b/drivers/mfd/db8500-prcmu.c
index 00b8b0f3dfb6..b96661d453aa 100644
--- a/drivers/mfd/db8500-prcmu.c
+++ b/drivers/mfd/db8500-prcmu.c
@@ -31,6 +31,7 @@
31#include <linux/mfd/abx500/ab8500.h> 31#include <linux/mfd/abx500/ab8500.h>
32#include <linux/regulator/db8500-prcmu.h> 32#include <linux/regulator/db8500-prcmu.h>
33#include <linux/regulator/machine.h> 33#include <linux/regulator/machine.h>
34#include <linux/cpufreq.h>
34#include <asm/hardware/gic.h> 35#include <asm/hardware/gic.h>
35#include <mach/hardware.h> 36#include <mach/hardware.h>
36#include <mach/irqs.h> 37#include <mach/irqs.h>
@@ -420,9 +421,6 @@ static struct {
420 421
421static atomic_t ac_wake_req_state = ATOMIC_INIT(0); 422static atomic_t ac_wake_req_state = ATOMIC_INIT(0);
422 423
423/* Functions definition */
424static void compute_armss_rate(void);
425
426/* Spinlocks */ 424/* Spinlocks */
427static DEFINE_SPINLOCK(prcmu_lock); 425static DEFINE_SPINLOCK(prcmu_lock);
428static DEFINE_SPINLOCK(clkout_lock); 426static DEFINE_SPINLOCK(clkout_lock);
@@ -1019,7 +1017,6 @@ int db8500_prcmu_set_arm_opp(u8 opp)
1019 (mb1_transfer.ack.arm_opp != opp)) 1017 (mb1_transfer.ack.arm_opp != opp))
1020 r = -EIO; 1018 r = -EIO;
1021 1019
1022 compute_armss_rate();
1023 mutex_unlock(&mb1_transfer.lock); 1020 mutex_unlock(&mb1_transfer.lock);
1024 1021
1025 return r; 1022 return r;
@@ -1169,12 +1166,12 @@ int db8500_prcmu_get_ape_opp(void)
1169} 1166}
1170 1167
1171/** 1168/**
1172 * prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage 1169 * db8500_prcmu_request_ape_opp_100_voltage - Request APE OPP 100% voltage
1173 * @enable: true to request the higher voltage, false to drop a request. 1170 * @enable: true to request the higher voltage, false to drop a request.
1174 * 1171 *
1175 * Calls to this function to enable and disable requests must be balanced. 1172 * Calls to this function to enable and disable requests must be balanced.
1176 */ 1173 */
1177int prcmu_request_ape_opp_100_voltage(bool enable) 1174int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
1178{ 1175{
1179 int r = 0; 1176 int r = 0;
1180 u8 header; 1177 u8 header;
@@ -1669,13 +1666,8 @@ static unsigned long clock_rate(u8 clock)
1669 else 1666 else
1670 return 0; 1667 return 0;
1671} 1668}
1672static unsigned long latest_armss_rate;
1673static unsigned long armss_rate(void)
1674{
1675 return latest_armss_rate;
1676}
1677 1669
1678static void compute_armss_rate(void) 1670static unsigned long armss_rate(void)
1679{ 1671{
1680 u32 r; 1672 u32 r;
1681 unsigned long rate; 1673 unsigned long rate;
@@ -1700,7 +1692,7 @@ static void compute_armss_rate(void)
1700 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV); 1692 rate = pll_rate(PRCM_PLLARM_FREQ, ROOT_CLOCK_RATE, PLL_DIV);
1701 } 1693 }
1702 1694
1703 latest_armss_rate = rate; 1695 return rate;
1704} 1696}
1705 1697
1706static unsigned long dsiclk_rate(u8 n) 1698static unsigned long dsiclk_rate(u8 n)
@@ -1820,6 +1812,35 @@ static long round_clock_rate(u8 clock, unsigned long rate)
1820 return rounded_rate; 1812 return rounded_rate;
1821} 1813}
1822 1814
1815/* CPU FREQ table, may be changed due to if MAX_OPP is supported. */
1816static struct cpufreq_frequency_table db8500_cpufreq_table[] = {
1817 { .frequency = 200000, .index = ARM_EXTCLK,},
1818 { .frequency = 400000, .index = ARM_50_OPP,},
1819 { .frequency = 800000, .index = ARM_100_OPP,},
1820 { .frequency = CPUFREQ_TABLE_END,}, /* To be used for MAX_OPP. */
1821 { .frequency = CPUFREQ_TABLE_END,},
1822};
1823
1824static long round_armss_rate(unsigned long rate)
1825{
1826 long freq = 0;
1827 int i = 0;
1828
1829 /* cpufreq table frequencies is in KHz. */
1830 rate = rate / 1000;
1831
1832 /* Find the corresponding arm opp from the cpufreq table. */
1833 while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1834 freq = db8500_cpufreq_table[i].frequency;
1835 if (freq == rate)
1836 break;
1837 i++;
1838 }
1839
1840 /* Return the last valid value, even if a match was not found. */
1841 return freq * 1000;
1842}
1843
1823#define MIN_PLL_VCO_RATE 600000000ULL 1844#define MIN_PLL_VCO_RATE 600000000ULL
1824#define MAX_PLL_VCO_RATE 1680640000ULL 1845#define MAX_PLL_VCO_RATE 1680640000ULL
1825 1846
@@ -1891,6 +1912,8 @@ long prcmu_round_clock_rate(u8 clock, unsigned long rate)
1891{ 1912{
1892 if (clock < PRCMU_NUM_REG_CLOCKS) 1913 if (clock < PRCMU_NUM_REG_CLOCKS)
1893 return round_clock_rate(clock, rate); 1914 return round_clock_rate(clock, rate);
1915 else if (clock == PRCMU_ARMSS)
1916 return round_armss_rate(rate);
1894 else if (clock == PRCMU_PLLDSI) 1917 else if (clock == PRCMU_PLLDSI)
1895 return round_plldsi_rate(rate); 1918 return round_plldsi_rate(rate);
1896 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 1919 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
@@ -1950,6 +1973,27 @@ static void set_clock_rate(u8 clock, unsigned long rate)
1950 spin_unlock_irqrestore(&clk_mgt_lock, flags); 1973 spin_unlock_irqrestore(&clk_mgt_lock, flags);
1951} 1974}
1952 1975
1976static int set_armss_rate(unsigned long rate)
1977{
1978 int i = 0;
1979
1980 /* cpufreq table frequencies is in KHz. */
1981 rate = rate / 1000;
1982
1983 /* Find the corresponding arm opp from the cpufreq table. */
1984 while (db8500_cpufreq_table[i].frequency != CPUFREQ_TABLE_END) {
1985 if (db8500_cpufreq_table[i].frequency == rate)
1986 break;
1987 i++;
1988 }
1989
1990 if (db8500_cpufreq_table[i].frequency != rate)
1991 return -EINVAL;
1992
1993 /* Set the new arm opp. */
1994 return db8500_prcmu_set_arm_opp(db8500_cpufreq_table[i].index);
1995}
1996
1953static int set_plldsi_rate(unsigned long rate) 1997static int set_plldsi_rate(unsigned long rate)
1954{ 1998{
1955 unsigned long src_rate; 1999 unsigned long src_rate;
@@ -2030,6 +2074,8 @@ int prcmu_set_clock_rate(u8 clock, unsigned long rate)
2030{ 2074{
2031 if (clock < PRCMU_NUM_REG_CLOCKS) 2075 if (clock < PRCMU_NUM_REG_CLOCKS)
2032 set_clock_rate(clock, rate); 2076 set_clock_rate(clock, rate);
2077 else if (clock == PRCMU_ARMSS)
2078 return set_armss_rate(rate);
2033 else if (clock == PRCMU_PLLDSI) 2079 else if (clock == PRCMU_PLLDSI)
2034 return set_plldsi_rate(rate); 2080 return set_plldsi_rate(rate);
2035 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK)) 2081 else if ((clock == PRCMU_DSI0CLK) || (clock == PRCMU_DSI1CLK))
@@ -2754,8 +2800,6 @@ void __init db8500_prcmu_early_init(void)
2754 init_completion(&mb5_transfer.work); 2800 init_completion(&mb5_transfer.work);
2755 2801
2756 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work); 2802 INIT_WORK(&mb0_transfer.mask_work, prcmu_mask_work);
2757
2758 compute_armss_rate();
2759} 2803}
2760 2804
2761static void __init init_prcm_registers(void) 2805static void __init init_prcm_registers(void)
@@ -3020,6 +3064,8 @@ static struct mfd_cell db8500_prcmu_devs[] = {
3020 { 3064 {
3021 .name = "cpufreq-u8500", 3065 .name = "cpufreq-u8500",
3022 .of_compatible = "stericsson,cpufreq-u8500", 3066 .of_compatible = "stericsson,cpufreq-u8500",
3067 .platform_data = &db8500_cpufreq_table,
3068 .pdata_size = sizeof(db8500_cpufreq_table),
3023 }, 3069 },
3024 { 3070 {
3025 .name = "ab8500-core", 3071 .name = "ab8500-core",
@@ -3030,6 +3076,14 @@ static struct mfd_cell db8500_prcmu_devs[] = {
3030 }, 3076 },
3031}; 3077};
3032 3078
3079static void db8500_prcmu_update_cpufreq(void)
3080{
3081 if (prcmu_has_arm_maxopp()) {
3082 db8500_cpufreq_table[3].frequency = 1000000;
3083 db8500_cpufreq_table[3].index = ARM_MAX_OPP;
3084 }
3085}
3086
3033/** 3087/**
3034 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic 3088 * prcmu_fw_init - arch init call for the Linux PRCMU fw init logic
3035 * 3089 *
@@ -3074,6 +3128,8 @@ static int __devinit db8500_prcmu_probe(struct platform_device *pdev)
3074 if (cpu_is_u8500v20_or_later()) 3128 if (cpu_is_u8500v20_or_later())
3075 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET); 3129 prcmu_config_esram0_deep_sleep(ESRAM0_DEEP_SLEEP_STATE_RET);
3076 3130
3131 db8500_prcmu_update_cpufreq();
3132
3077 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs, 3133 err = mfd_add_devices(&pdev->dev, 0, db8500_prcmu_devs,
3078 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL); 3134 ARRAY_SIZE(db8500_prcmu_devs), NULL, 0, NULL);
3079 if (err) { 3135 if (err) {
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index f9f5e9eeb9dd..4989b8a7bed1 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -53,9 +53,18 @@ struct clk_hw;
53 * @disable: Disable the clock atomically. Called with enable_lock held. 53 * @disable: Disable the clock atomically. Called with enable_lock held.
54 * This function must not sleep. 54 * This function must not sleep.
55 * 55 *
56 * @recalc_rate Recalculate the rate of this clock, by quering hardware. The 56 * @is_enabled: Queries the hardware to determine if the clock is enabled.
57 * This function must not sleep. Optional, if this op is not
58 * set then the enable count will be used.
59 *
60 * @disable_unused: Disable the clock atomically. Only called from
61 * clk_disable_unused for gate clocks with special needs.
62 * Called with enable_lock held. This function must not
63 * sleep.
64 *
65 * @recalc_rate Recalculate the rate of this clock, by querying hardware. The
57 * parent rate is an input parameter. It is up to the caller to 66 * parent rate is an input parameter. It is up to the caller to
58 * insure that the prepare_mutex is held across this call. 67 * ensure that the prepare_mutex is held across this call.
59 * Returns the calculated rate. Optional, but recommended - if 68 * Returns the calculated rate. Optional, but recommended - if
60 * this op is not set then clock rate will be initialized to 0. 69 * this op is not set then clock rate will be initialized to 0.
61 * 70 *
@@ -89,7 +98,7 @@ struct clk_hw;
89 * implementations to split any work between atomic (enable) and sleepable 98 * implementations to split any work between atomic (enable) and sleepable
90 * (prepare) contexts. If enabling a clock requires code that might sleep, 99 * (prepare) contexts. If enabling a clock requires code that might sleep,
91 * this must be done in clk_prepare. Clock enable code that will never be 100 * this must be done in clk_prepare. Clock enable code that will never be
92 * called in a sleepable context may be implement in clk_enable. 101 * called in a sleepable context may be implemented in clk_enable.
93 * 102 *
94 * Typically, drivers will call clk_prepare when a clock may be needed later 103 * Typically, drivers will call clk_prepare when a clock may be needed later
95 * (eg. when a device is opened), and clk_enable when the clock is actually 104 * (eg. when a device is opened), and clk_enable when the clock is actually
@@ -102,6 +111,7 @@ struct clk_ops {
102 int (*enable)(struct clk_hw *hw); 111 int (*enable)(struct clk_hw *hw);
103 void (*disable)(struct clk_hw *hw); 112 void (*disable)(struct clk_hw *hw);
104 int (*is_enabled)(struct clk_hw *hw); 113 int (*is_enabled)(struct clk_hw *hw);
114 void (*disable_unused)(struct clk_hw *hw);
105 unsigned long (*recalc_rate)(struct clk_hw *hw, 115 unsigned long (*recalc_rate)(struct clk_hw *hw,
106 unsigned long parent_rate); 116 unsigned long parent_rate);
107 long (*round_rate)(struct clk_hw *hw, unsigned long, 117 long (*round_rate)(struct clk_hw *hw, unsigned long,
@@ -327,19 +337,21 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
327 * error code; drivers must test for an error code after calling clk_register. 337 * error code; drivers must test for an error code after calling clk_register.
328 */ 338 */
329struct clk *clk_register(struct device *dev, struct clk_hw *hw); 339struct clk *clk_register(struct device *dev, struct clk_hw *hw);
340struct clk *devm_clk_register(struct device *dev, struct clk_hw *hw);
330 341
331void clk_unregister(struct clk *clk); 342void clk_unregister(struct clk *clk);
343void devm_clk_unregister(struct device *dev, struct clk *clk);
332 344
333/* helper functions */ 345/* helper functions */
334const char *__clk_get_name(struct clk *clk); 346const char *__clk_get_name(struct clk *clk);
335struct clk_hw *__clk_get_hw(struct clk *clk); 347struct clk_hw *__clk_get_hw(struct clk *clk);
336u8 __clk_get_num_parents(struct clk *clk); 348u8 __clk_get_num_parents(struct clk *clk);
337struct clk *__clk_get_parent(struct clk *clk); 349struct clk *__clk_get_parent(struct clk *clk);
338int __clk_get_enable_count(struct clk *clk); 350unsigned int __clk_get_enable_count(struct clk *clk);
339int __clk_get_prepare_count(struct clk *clk); 351unsigned int __clk_get_prepare_count(struct clk *clk);
340unsigned long __clk_get_rate(struct clk *clk); 352unsigned long __clk_get_rate(struct clk *clk);
341unsigned long __clk_get_flags(struct clk *clk); 353unsigned long __clk_get_flags(struct clk *clk);
342int __clk_is_enabled(struct clk *clk); 354bool __clk_is_enabled(struct clk *clk);
343struct clk *__clk_lookup(const char *name); 355struct clk *__clk_lookup(const char *name);
344 356
345/* 357/*
diff --git a/include/linux/mfd/db8500-prcmu.h b/include/linux/mfd/db8500-prcmu.h
index b82f6ee66a0b..6ee4247df11e 100644
--- a/include/linux/mfd/db8500-prcmu.h
+++ b/include/linux/mfd/db8500-prcmu.h
@@ -515,7 +515,6 @@ enum romcode_read prcmu_get_rc_p2a(void);
515enum ap_pwrst prcmu_get_xp70_current_state(void); 515enum ap_pwrst prcmu_get_xp70_current_state(void);
516bool prcmu_has_arm_maxopp(void); 516bool prcmu_has_arm_maxopp(void);
517struct prcmu_fw_version *prcmu_get_fw_version(void); 517struct prcmu_fw_version *prcmu_get_fw_version(void);
518int prcmu_request_ape_opp_100_voltage(bool enable);
519int prcmu_release_usb_wakeup_state(void); 518int prcmu_release_usb_wakeup_state(void);
520void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep, 519void prcmu_configure_auto_pm(struct prcmu_auto_pm_config *sleep,
521 struct prcmu_auto_pm_config *idle); 520 struct prcmu_auto_pm_config *idle);
@@ -564,6 +563,7 @@ int db8500_prcmu_set_arm_opp(u8 opp);
564int db8500_prcmu_get_arm_opp(void); 563int db8500_prcmu_get_arm_opp(void);
565int db8500_prcmu_set_ape_opp(u8 opp); 564int db8500_prcmu_set_ape_opp(u8 opp);
566int db8500_prcmu_get_ape_opp(void); 565int db8500_prcmu_get_ape_opp(void);
566int db8500_prcmu_request_ape_opp_100_voltage(bool enable);
567int db8500_prcmu_set_ddr_opp(u8 opp); 567int db8500_prcmu_set_ddr_opp(u8 opp);
568int db8500_prcmu_get_ddr_opp(void); 568int db8500_prcmu_get_ddr_opp(void);
569 569
@@ -610,7 +610,7 @@ static inline int db8500_prcmu_get_ape_opp(void)
610 return APE_100_OPP; 610 return APE_100_OPP;
611} 611}
612 612
613static inline int prcmu_request_ape_opp_100_voltage(bool enable) 613static inline int db8500_prcmu_request_ape_opp_100_voltage(bool enable)
614{ 614{
615 return 0; 615 return 0;
616} 616}
diff --git a/include/linux/mfd/dbx500-prcmu.h b/include/linux/mfd/dbx500-prcmu.h
index c410d99bd667..c202d6c4d879 100644
--- a/include/linux/mfd/dbx500-prcmu.h
+++ b/include/linux/mfd/dbx500-prcmu.h
@@ -336,6 +336,11 @@ static inline int prcmu_get_ape_opp(void)
336 return db8500_prcmu_get_ape_opp(); 336 return db8500_prcmu_get_ape_opp();
337} 337}
338 338
339static inline int prcmu_request_ape_opp_100_voltage(bool enable)
340{
341 return db8500_prcmu_request_ape_opp_100_voltage(enable);
342}
343
339static inline void prcmu_system_reset(u16 reset_code) 344static inline void prcmu_system_reset(u16 reset_code)
340{ 345{
341 return db8500_prcmu_system_reset(reset_code); 346 return db8500_prcmu_system_reset(reset_code);
@@ -507,6 +512,11 @@ static inline int prcmu_get_ape_opp(void)
507 return APE_100_OPP; 512 return APE_100_OPP;
508} 513}
509 514
515static inline int prcmu_request_ape_opp_100_voltage(bool enable)
516{
517 return 0;
518}
519
510static inline int prcmu_set_arm_opp(u8 opp) 520static inline int prcmu_set_arm_opp(u8 opp)
511{ 521{
512 return 0; 522 return 0;
diff --git a/include/linux/platform_data/clk-integrator.h b/include/linux/platform_data/clk-integrator.h
index 83fe9c283bb8..280edac9d0a5 100644
--- a/include/linux/platform_data/clk-integrator.h
+++ b/include/linux/platform_data/clk-integrator.h
@@ -1 +1,3 @@
1void integrator_clk_init(bool is_cp); 1void integrator_clk_init(bool is_cp);
2void integrator_impd1_clk_init(void __iomem *base, unsigned int id);
3void integrator_impd1_clk_exit(unsigned int id);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-20 02:16:08 -0500