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-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi101
-rw-r--r--arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi15
2 files changed, 114 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
index f1bdcae5b97d..6b2c8922877d 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pbab01.dtsi
@@ -9,10 +9,96 @@
9 * http://www.gnu.org/copyleft/gpl.html 9 * http://www.gnu.org/copyleft/gpl.html
10 */ 10 */
11 11
12#include <dt-bindings/sound/fsl-imx-audmux.h>
13
12/ { 14/ {
13 chosen { 15 chosen {
14 linux,stdout-path = &uart4; 16 linux,stdout-path = &uart4;
15 }; 17 };
18
19 regulators {
20 sound_1v8: regulator@2 {
21 compatible = "regulator-fixed";
22 reg = <2>;
23 regulator-name = "i2s-audio-1v8";
24 regulator-min-microvolt = <1800000>;
25 regulator-max-microvolt = <1800000>;
26 };
27
28 sound_3v3: regulator@3 {
29 compatible = "regulator-fixed";
30 reg = <3>;
31 regulator-name = "i2s-audio-3v3";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
34 };
35 };
36
37 tlv320_mclk: oscillator {
38 compatible = "fixed-clock";
39 #clock-cells = <0>;
40 clock-frequency = <19200000>;
41 clock-output-names = "tlv320-mclk";
42 };
43
44 sound {
45 compatible = "simple-audio-card";
46 simple-audio-card,name = "OnboardTLV320AIC3007";
47 simple-audio-card,format = "i2s";
48 simple-audio-card,bitclock-master = <&dailink_master>;
49 simple-audio-card,frame-master = <&dailink_master>;
50 simple-audio-card,widgets =
51 "Microphone", "Mic Jack",
52 "Line", "Line In",
53 "Line", "Line Out",
54 "Speaker", "Speaker",
55 "Headphone", "Headphone Jack";
56 simple-audio-card,routing =
57 "Line Out", "LLOUT",
58 "Line Out", "RLOUT",
59 "Speaker", "SPOP",
60 "Speaker", "SPOM",
61 "Headphone Jack", "HPLOUT",
62 "Headphone Jack", "HPROUT",
63 "MIC3L", "Mic Jack",
64 "MIC3R", "Mic Jack",
65 "Mic Jack", "Mic Bias",
66 "LINE1L", "Line In",
67 "LINE1R", "Line In";
68
69 simple-audio-card,cpu {
70 sound-dai = <&ssi2>;
71 };
72
73 dailink_master: simple-audio-card,codec {
74 sound-dai = <&codec>;
75 clocks = <&tlv320_mclk>;
76 };
77 };
78
79};
80
81&audmux {
82 status = "okay";
83
84 ssi2 {
85 fsl,audmux-port = <1>;
86 fsl,port-config = <
87 (IMX_AUDMUX_V2_PTCR_TFSDIR |
88 IMX_AUDMUX_V2_PTCR_TFSEL(4) |
89 IMX_AUDMUX_V2_PTCR_TCLKDIR |
90 IMX_AUDMUX_V2_PTCR_TCSEL(4))
91 IMX_AUDMUX_V2_PDCR_RXDSEL(4)
92 >;
93 };
94
95 pins5 {
96 fsl,audmux-port = <4>;
97 fsl,port-config = <
98 0x00000000
99 IMX_AUDMUX_V2_PDCR_RXDSEL(1)
100 >;
101 };
16}; 102};
17 103
18&fec { 104&fec {
@@ -30,9 +116,16 @@
30&i2c2 { 116&i2c2 {
31 status = "okay"; 117 status = "okay";
32 118
33 tlv320@18 { 119 codec: tlv320@18 {
34 compatible = "ti,tlv320aic3x"; 120 compatible = "ti,tlv320aic3007";
121 #sound-dai-cells = <0>;
35 reg = <0x18>; 122 reg = <0x18>;
123 ai3x-micbias-vg = <2>;
124
125 AVDD-supply = <&sound_3v3>;
126 IOVDD-supply = <&sound_3v3>;
127 DRVDD-supply = <&sound_3v3>;
128 DVDD-supply = <&sound_1v8>;
36 }; 129 };
37 130
38 stmpe@41 { 131 stmpe@41 {
@@ -55,6 +148,10 @@
55 status = "okay"; 148 status = "okay";
56}; 149};
57 150
151&ssi2 {
152 status = "okay";
153};
154
58&uart3 { 155&uart3 {
59 status = "okay"; 156 status = "okay";
60}; 157};
diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
index aa2275671d2c..ab3b1f9eec6e 100644
--- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
+++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi
@@ -58,6 +58,12 @@
58 }; 58 };
59}; 59};
60 60
61&audmux {
62 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_audmux>;
64 status = "disabled";
65};
66
61&ecspi3 { 67&ecspi3 {
62 pinctrl-names = "default"; 68 pinctrl-names = "default";
63 pinctrl-0 = <&pinctrl_ecspi3>; 69 pinctrl-0 = <&pinctrl_ecspi3>;
@@ -319,6 +325,15 @@
319 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 325 MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000
320 >; 326 >;
321 }; 327 };
328
329 pinctrl_audmux: audmuxgrp {
330 fsl,pins = <
331 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x130b0
332 MX6QDL_PAD_DISP0_DAT17__AUD5_TXD 0x110b0
333 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x130b0
334 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
335 >;
336 };
322 }; 337 };
323}; 338};
324 339