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-rw-r--r--drivers/net/ethernet/intel/e1000e/e1000.h6
-rw-r--r--drivers/net/ethernet/intel/e1000e/netdev.c2
2 files changed, 4 insertions, 4 deletions
diff --git a/drivers/net/ethernet/intel/e1000e/e1000.h b/drivers/net/ethernet/intel/e1000e/e1000.h
index cb3356c9af80..04668b47a1df 100644
--- a/drivers/net/ethernet/intel/e1000e/e1000.h
+++ b/drivers/net/ethernet/intel/e1000e/e1000.h
@@ -175,13 +175,13 @@ struct e1000_info;
175/* 175/*
176 * in the case of WTHRESH, it appears at least the 82571/2 hardware 176 * in the case of WTHRESH, it appears at least the 82571/2 hardware
177 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when 177 * writes back 4 descriptors when WTHRESH=5, and 3 descriptors when
178 * WTHRESH=4, and since we want 64 bytes at a time written back, set 178 * WTHRESH=4, so a setting of 5 gives the most efficient bus
179 * it to 5 179 * utilization but to avoid possible Tx stalls, set it to 1
180 */ 180 */
181#define E1000_TXDCTL_DMA_BURST_ENABLE \ 181#define E1000_TXDCTL_DMA_BURST_ENABLE \
182 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \ 182 (E1000_TXDCTL_GRAN | /* set descriptor granularity */ \
183 E1000_TXDCTL_COUNT_DESC | \ 183 E1000_TXDCTL_COUNT_DESC | \
184 (5 << 16) | /* wthresh must be +1 more than desired */\ 184 (1 << 16) | /* wthresh must be +1 more than desired */\
185 (1 << 8) | /* hthresh */ \ 185 (1 << 8) | /* hthresh */ \
186 0x1f) /* pthresh */ 186 0x1f) /* pthresh */
187 187
diff --git a/drivers/net/ethernet/intel/e1000e/netdev.c b/drivers/net/ethernet/intel/e1000e/netdev.c
index de57a2ba6bde..f444eb0b76d8 100644
--- a/drivers/net/ethernet/intel/e1000e/netdev.c
+++ b/drivers/net/ethernet/intel/e1000e/netdev.c
@@ -2831,7 +2831,7 @@ static void e1000_configure_tx(struct e1000_adapter *adapter)
2831 * set up some performance related parameters to encourage the 2831 * set up some performance related parameters to encourage the
2832 * hardware to use the bus more efficiently in bursts, depends 2832 * hardware to use the bus more efficiently in bursts, depends
2833 * on the tx_int_delay to be enabled, 2833 * on the tx_int_delay to be enabled,
2834 * wthresh = 5 ==> burst write a cacheline (64 bytes) at a time 2834 * wthresh = 1 ==> burst write is disabled to avoid Tx stalls
2835 * hthresh = 1 ==> prefetch when one or more available 2835 * hthresh = 1 ==> prefetch when one or more available
2836 * pthresh = 0x1f ==> prefetch if internal cache 31 or less 2836 * pthresh = 0x1f ==> prefetch if internal cache 31 or less
2837 * BEWARE: this seems to work but should be considered first if 2837 * BEWARE: this seems to work but should be considered first if