12 files changed, 14 insertions, 21 deletions

diff --git a/drivers/gpu/drm/gma500/psb_irq.c b/drivers/gpu/drm/gma500/psb_irq.c
index ef00bce9991a..a9bb34704738 100644
--- a/drivers/gpu/drm/gma500/psb_irq.c
+++ b/drivers/gpu/drm/gma500/psb_irq.c
@@ -253,7 +253,7 @@ irqreturn_t psb_irq_handler(int irq, void *arg)
 
         PSB_WVDC32(vdc_stat, PSB_INT_IDENTITY_R);
         (void) PSB_RVDC32(PSB_INT_IDENTITY_R);
-        DRM_READMEMORYBARRIER();
+        rmb();
 
         if (!handled)
                 return IRQ_NONE;
diff --git a/drivers/gpu/drm/mga/mga_drv.h b/drivers/gpu/drm/mga/mga_drv.h
index 901e4f935fed..fe453213600a 100644
--- a/drivers/gpu/drm/mga/mga_drv.h
+++ b/drivers/gpu/drm/mga/mga_drv.h
@@ -193,7 +193,7 @@ extern void mga_driver_irq_uninstall(struct drm_device *dev);
 extern long mga_compat_ioctl(struct file *filp, unsigned int cmd,
                              unsigned long arg);
 
-#define mga_flush_write_combine()       DRM_WRITEMEMORYBARRIER()
+#define mga_flush_write_combine()       wmb()
 
 #define MGA_READ8(reg)          DRM_READ8(dev_priv->mmio, (reg))
 #define MGA_READ(reg)           DRM_READ32(dev_priv->mmio, (reg))
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.c b/drivers/gpu/drm/nouveau/nouveau_dma.c
index 40f91e1e5842..c177272152e2 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.c
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.c
@@ -100,7 +100,7 @@ nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
 
         chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
 
-        DRM_MEMORYBARRIER();
+        mb();
         /* Flush writes. */
         nouveau_bo_rd32(pb, 0);
 
diff --git a/drivers/gpu/drm/nouveau/nouveau_dma.h b/drivers/gpu/drm/nouveau/nouveau_dma.h
index 984004d66a6d..dc0e0c5cadb4 100644
--- a/drivers/gpu/drm/nouveau/nouveau_dma.h
+++ b/drivers/gpu/drm/nouveau/nouveau_dma.h
@@ -155,7 +155,7 @@ BEGIN_IMC0(struct nouveau_channel *chan, int subc, int mthd, u16 data)
 }
 
 #define WRITE_PUT(val) do {                                                    \
-        DRM_MEMORYBARRIER();                                                   \
+        mb();                                                   \
         nouveau_bo_rd32(chan->push.buffer, 0);                                 \
         nv_wo32(chan->object, chan->user_put, ((val) << 2) + chan->push.vma.offset);  \
 } while (0)
diff --git a/drivers/gpu/drm/r128/r128_drv.h b/drivers/gpu/drm/r128/r128_drv.h
index 4318bfa845cb..5bf3f5ff805d 100644
--- a/drivers/gpu/drm/r128/r128_drv.h
+++ b/drivers/gpu/drm/r128/r128_drv.h
@@ -514,7 +514,7 @@ do {									\
         if (R128_VERBOSE)                                               \
                 DRM_INFO("COMMIT_RING() tail=0x%06x\n",                 \
                          dev_priv->ring.tail);                          \
-        DRM_MEMORYBARRIER();                                            \
+        mb();                                           \
         R128_WRITE(R128_PM4_BUFFER_DL_WPTR, dev_priv->ring.tail);       \
         R128_READ(R128_PM4_BUFFER_DL_WPTR);                             \
 } while (0)
diff --git a/drivers/gpu/drm/radeon/radeon_cp.c b/drivers/gpu/drm/radeon/radeon_cp.c
index d73013e6f58a..bb0d5c3a8311 100644
--- a/drivers/gpu/drm/radeon/radeon_cp.c
+++ b/drivers/gpu/drm/radeon/radeon_cp.c
@@ -2228,7 +2228,7 @@ void radeon_commit_ring(drm_radeon_private_t *dev_priv)
 
         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
 
-        DRM_MEMORYBARRIER();
+        mb();
         GET_RING_HEAD( dev_priv );
 
         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index 9214403ae173..ca2d71afeb02 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -463,7 +463,7 @@ void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
         while (ring->wptr & ring->align_mask) {
                 radeon_ring_write(ring, ring->nop);
         }
-        DRM_MEMORYBARRIER();
+        mb();
         radeon_ring_set_wptr(rdev, ring);
 }
 
diff --git a/drivers/gpu/drm/savage/savage_bci.c b/drivers/gpu/drm/savage/savage_bci.c
index 6e673fa968e5..d2b2df9e26f3 100644
--- a/drivers/gpu/drm/savage/savage_bci.c
+++ b/drivers/gpu/drm/savage/savage_bci.c
@@ -49,7 +49,7 @@ savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n)
 #endif
 
         for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
-                DRM_MEMORYBARRIER();
+                mb();
                 status = dev_priv->status_ptr[0];
                 if ((status & mask) < threshold)
                         return 0;
@@ -123,7 +123,7 @@ savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e)
         int i;
 
         for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
-                DRM_MEMORYBARRIER();
+                mb();
                 status = dev_priv->status_ptr[1];
                 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
                     (status & 0xffff) == 0)
@@ -449,7 +449,7 @@ static void savage_dma_flush(drm_savage_private_t * dev_priv)
                 }
         }
 
-        DRM_MEMORYBARRIER();
+        mb();
 
         /* do flush ... */
         phys_addr = dev_priv->cmd_dma->offset +
diff --git a/drivers/gpu/drm/savage/savage_state.c b/drivers/gpu/drm/savage/savage_state.c
index 2d3e56d94be3..c01ad0aeaa58 100644
--- a/drivers/gpu/drm/savage/savage_state.c
+++ b/drivers/gpu/drm/savage/savage_state.c
@@ -1032,7 +1032,7 @@ int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_
 
         /* Make sure writes to DMA buffers are finished before sending
          * DMA commands to the graphics hardware. */
-        DRM_MEMORYBARRIER();
+        mb();
 
         /* Coming from user space. Don't know if the Xserver has
          * emitted wait commands. Assuming the worst. */
diff --git a/drivers/gpu/drm/via/via_dma.c b/drivers/gpu/drm/via/via_dma.c
index 3436fdad22c5..5d4179284964 100644
--- a/drivers/gpu/drm/via/via_dma.c
+++ b/drivers/gpu/drm/via/via_dma.c
@@ -60,7 +60,7 @@
         dev_priv->dma_low += 8;                                 \
 }
 
-#define via_flush_write_combine() DRM_MEMORYBARRIER()
+#define via_flush_write_combine() mb()
 
 #define VIA_OUT_RING_QW(w1, w2) do {            \
         *vb++ = (w1);                           \
@@ -543,7 +543,7 @@ static void via_cmdbuf_start(drm_via_private_t *dev_priv)
 
         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_hi);
         VIA_WRITE(VIA_REG_TRANSPACE, pause_addr_lo);
-        DRM_WRITEMEMORYBARRIER();
+        wmb();
         VIA_WRITE(VIA_REG_TRANSPACE, command | HC_HAGPCMNT_MASK);
         VIA_READ(VIA_REG_TRANSPACE);
 
diff --git a/drivers/gpu/drm/via/via_dmablit.c b/drivers/gpu/drm/via/via_dmablit.c
index 694b9954cbbc..ba33cf679180 100644
--- a/drivers/gpu/drm/via/via_dmablit.c
+++ b/drivers/gpu/drm/via/via_dmablit.c
@@ -217,7 +217,7 @@ via_fire_dmablit(struct drm_device *dev, drm_via_sg_info_t *vsg, int engine)
         VIA_WRITE(VIA_PCI_DMA_MR0  + engine*0x04, VIA_DMA_MR_CM | VIA_DMA_MR_TDIE);
         VIA_WRITE(VIA_PCI_DMA_BCR0 + engine*0x10, 0);
         VIA_WRITE(VIA_PCI_DMA_DPR0 + engine*0x10, vsg->chain_start);
-        DRM_WRITEMEMORYBARRIER();
+        wmb();
         VIA_WRITE(VIA_PCI_DMA_CSR0 + engine*0x04, VIA_DMA_CSR_DE | VIA_DMA_CSR_TS);
         VIA_READ(VIA_PCI_DMA_CSR0 + engine*0x04);
 }
diff --git a/include/drm/drm_os_linux.h b/include/drm/drm_os_linux.h
index 2953b1d83022..43008938b6b2 100644
--- a/include/drm/drm_os_linux.h
+++ b/include/drm/drm_os_linux.h
@@ -35,19 +35,12 @@ static inline void writeq(u64 val, void __iomem *reg)
 #define DRM_WRITE16(map, offset, val)   writew(val, ((void __iomem *)(map)->handle) + (offset))
 /** Write a dword into a MMIO region */
 #define DRM_WRITE32(map, offset, val)   writel(val, ((void __iomem *)(map)->handle) + (offset))
-/** Read memory barrier */
 
 /** Read a qword from a MMIO region - be careful using these unless you really understand them */
 #define DRM_READ64(map, offset)         readq(((void __iomem *)(map)->handle) + (offset))
 /** Write a qword into a MMIO region */
 #define DRM_WRITE64(map, offset, val)   writeq(val, ((void __iomem *)(map)->handle) + (offset))
 
-#define DRM_READMEMORYBARRIER()         rmb()
-/** Write memory barrier */
-#define DRM_WRITEMEMORYBARRIER()        wmb()
-/** Read/write memory barrier */
-#define DRM_MEMORYBARRIER()             mb()
-
 #define DRM_WAIT_ON( ret, queue, timeout, condition )           \
 do {                                                            \
         DECLARE_WAITQUEUE(entry, current);                      \