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-rw-r--r--arch/arm/mach-at91/at91rm9200_time.c7
-rw-r--r--arch/arm/mach-cns3xxx/core.c13
-rw-r--r--arch/arm/mach-exynos/mct.c18
-rw-r--r--arch/arm/mach-footbridge/dc21285-timer.c6
-rw-r--r--arch/arm/mach-imx/epit.c15
-rw-r--r--arch/arm/mach-imx/time.c15
-rw-r--r--arch/arm/mach-ixp4xx/common.c11
-rw-r--r--arch/arm/mach-lpc32xx/timer.c9
-rw-r--r--arch/arm/mach-mmp/time.c7
-rw-r--r--arch/arm/mach-msm/timer.c6
-rw-r--r--arch/arm/mach-mxs/timer.c24
-rw-r--r--arch/arm/mach-netx/time.c10
-rw-r--r--arch/arm/mach-omap1/time.c11
-rw-r--r--arch/arm/mach-omap1/timer32k.c12
-rw-r--r--arch/arm/mach-omap2/timer.c13
-rw-r--r--arch/arm/mach-prima2/timer.c10
-rw-r--r--arch/arm/mach-pxa/time.c8
-rw-r--r--arch/arm/mach-sa1100/time.c8
-rw-r--r--arch/arm/mach-tegra/timer.c8
-rw-r--r--arch/arm/mach-vt8500/timer.c9
-rw-r--r--arch/arm/mach-w90x900/time.c10
-rw-r--r--arch/arm/plat-iop/time.c9
-rw-r--r--arch/arm/plat-orion/time.c6
-rw-r--r--arch/arm/plat-samsung/s5p-time.c9
-rw-r--r--arch/arm/plat-spear/time.c8
25 files changed, 53 insertions, 209 deletions
diff --git a/arch/arm/mach-at91/at91rm9200_time.c b/arch/arm/mach-at91/at91rm9200_time.c
index cafe98836c8a..20a28acdc8a7 100644
--- a/arch/arm/mach-at91/at91rm9200_time.c
+++ b/arch/arm/mach-at91/at91rm9200_time.c
@@ -174,7 +174,6 @@ clkevt32k_next_event(unsigned long delta, struct clock_event_device *dev)
174static struct clock_event_device clkevt = { 174static struct clock_event_device clkevt = {
175 .name = "at91_tick", 175 .name = "at91_tick",
176 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 176 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
177 .shift = 32,
178 .rating = 150, 177 .rating = 150,
179 .set_next_event = clkevt32k_next_event, 178 .set_next_event = clkevt32k_next_event,
180 .set_mode = clkevt32k_mode, 179 .set_mode = clkevt32k_mode,
@@ -265,11 +264,9 @@ void __init at91rm9200_timer_init(void)
265 at91_st_write(AT91_ST_RTMR, 1); 264 at91_st_write(AT91_ST_RTMR, 1);
266 265
267 /* Setup timer clockevent, with minimum of two ticks (important!!) */ 266 /* Setup timer clockevent, with minimum of two ticks (important!!) */
268 clkevt.mult = div_sc(AT91_SLOW_CLOCK, NSEC_PER_SEC, clkevt.shift);
269 clkevt.max_delta_ns = clockevent_delta2ns(AT91_ST_ALMV, &clkevt);
270 clkevt.min_delta_ns = clockevent_delta2ns(2, &clkevt) + 1;
271 clkevt.cpumask = cpumask_of(0); 267 clkevt.cpumask = cpumask_of(0);
272 clockevents_register_device(&clkevt); 268 clockevents_config_and_register(&clkevt, AT91_SLOW_CLOCK,
269 2, AT91_ST_ALMV);
273 270
274 /* register clocksource */ 271 /* register clocksource */
275 clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK); 272 clocksource_register_hz(&clk32k, AT91_SLOW_CLOCK);
diff --git a/arch/arm/mach-cns3xxx/core.c b/arch/arm/mach-cns3xxx/core.c
index 031805b1428d..3eb74d1ba067 100644
--- a/arch/arm/mach-cns3xxx/core.c
+++ b/arch/arm/mach-cns3xxx/core.c
@@ -134,7 +134,6 @@ static int cns3xxx_timer_set_next_event(unsigned long evt,
134 134
135static struct clock_event_device cns3xxx_tmr1_clockevent = { 135static struct clock_event_device cns3xxx_tmr1_clockevent = {
136 .name = "cns3xxx timer1", 136 .name = "cns3xxx timer1",
137 .shift = 8,
138 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 137 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
139 .set_mode = cns3xxx_timer_set_mode, 138 .set_mode = cns3xxx_timer_set_mode,
140 .set_next_event = cns3xxx_timer_set_next_event, 139 .set_next_event = cns3xxx_timer_set_next_event,
@@ -145,15 +144,9 @@ static struct clock_event_device cns3xxx_tmr1_clockevent = {
145static void __init cns3xxx_clockevents_init(unsigned int timer_irq) 144static void __init cns3xxx_clockevents_init(unsigned int timer_irq)
146{ 145{
147 cns3xxx_tmr1_clockevent.irq = timer_irq; 146 cns3xxx_tmr1_clockevent.irq = timer_irq;
148 cns3xxx_tmr1_clockevent.mult = 147 clockevents_config_and_register(&cns3xxx_tmr1_clockevent,
149 div_sc((cns3xxx_cpu_clock() >> 3) * 1000000, NSEC_PER_SEC, 148 (cns3xxx_cpu_clock() >> 3) * 1000000,
150 cns3xxx_tmr1_clockevent.shift); 149 0xf, 0xffffffff);
151 cns3xxx_tmr1_clockevent.max_delta_ns =
152 clockevent_delta2ns(0xffffffff, &cns3xxx_tmr1_clockevent);
153 cns3xxx_tmr1_clockevent.min_delta_ns =
154 clockevent_delta2ns(0xf, &cns3xxx_tmr1_clockevent);
155
156 clockevents_register_device(&cns3xxx_tmr1_clockevent);
157} 150}
158 151
159/* 152/*
diff --git a/arch/arm/mach-exynos/mct.c b/arch/arm/mach-exynos/mct.c
index 57668eb68e75..070d51eea93e 100644
--- a/arch/arm/mach-exynos/mct.c
+++ b/arch/arm/mach-exynos/mct.c
@@ -255,13 +255,9 @@ static struct irqaction mct_comp_event_irq = {
255 255
256static void exynos4_clockevent_init(void) 256static void exynos4_clockevent_init(void)
257{ 257{
258 clockevents_calc_mult_shift(&mct_comp_device, clk_rate, 5);
259 mct_comp_device.max_delta_ns =
260 clockevent_delta2ns(0xffffffff, &mct_comp_device);
261 mct_comp_device.min_delta_ns =
262 clockevent_delta2ns(0xf, &mct_comp_device);
263 mct_comp_device.cpumask = cpumask_of(0); 258 mct_comp_device.cpumask = cpumask_of(0);
264 clockevents_register_device(&mct_comp_device); 259 clockevents_config_and_register(&mct_comp_device, clk_rate,
260 0xf, 0xffffffff);
265 261
266 if (soc_is_exynos5250()) 262 if (soc_is_exynos5250())
267 setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq); 263 setup_irq(EXYNOS5_IRQ_MCT_G0, &mct_comp_event_irq);
@@ -404,14 +400,8 @@ static int __cpuinit exynos4_local_timer_setup(struct clock_event_device *evt)
404 evt->set_mode = exynos4_tick_set_mode; 400 evt->set_mode = exynos4_tick_set_mode;
405 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; 401 evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
406 evt->rating = 450; 402 evt->rating = 450;
407 403 clockevents_config_and_register(evt, clk_rate / (TICK_BASE_CNT + 1),
408 clockevents_calc_mult_shift(evt, clk_rate / (TICK_BASE_CNT + 1), 5); 404 0xf, 0x7fffffff);
409 evt->max_delta_ns =
410 clockevent_delta2ns(0x7fffffff, evt);
411 evt->min_delta_ns =
412 clockevent_delta2ns(0xf, evt);
413
414 clockevents_register_device(evt);
415 405
416 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); 406 exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET);
417 407
diff --git a/arch/arm/mach-footbridge/dc21285-timer.c b/arch/arm/mach-footbridge/dc21285-timer.c
index 3b54196447c7..a9918b691a84 100644
--- a/arch/arm/mach-footbridge/dc21285-timer.c
+++ b/arch/arm/mach-footbridge/dc21285-timer.c
@@ -101,12 +101,8 @@ static void __init footbridge_timer_init(void)
101 101
102 setup_irq(ce->irq, &footbridge_timer_irq); 102 setup_irq(ce->irq, &footbridge_timer_irq);
103 103
104 clockevents_calc_mult_shift(ce, mem_fclk_21285, 5);
105 ce->max_delta_ns = clockevent_delta2ns(0xffffff, ce);
106 ce->min_delta_ns = clockevent_delta2ns(0x000004, ce);
107 ce->cpumask = cpumask_of(smp_processor_id()); 104 ce->cpumask = cpumask_of(smp_processor_id());
108 105 clockevents_config_and_register(ce, mem_fclk_21285, 0x4, 0xffffff);
109 clockevents_register_device(ce);
110} 106}
111 107
112struct sys_timer footbridge_timer = { 108struct sys_timer footbridge_timer = {
diff --git a/arch/arm/mach-imx/epit.c b/arch/arm/mach-imx/epit.c
index 04a5961beeac..e02de188ae83 100644
--- a/arch/arm/mach-imx/epit.c
+++ b/arch/arm/mach-imx/epit.c
@@ -178,7 +178,6 @@ static struct irqaction epit_timer_irq = {
178static struct clock_event_device clockevent_epit = { 178static struct clock_event_device clockevent_epit = {
179 .name = "epit", 179 .name = "epit",
180 .features = CLOCK_EVT_FEAT_ONESHOT, 180 .features = CLOCK_EVT_FEAT_ONESHOT,
181 .shift = 32,
182 .set_mode = epit_set_mode, 181 .set_mode = epit_set_mode,
183 .set_next_event = epit_set_next_event, 182 .set_next_event = epit_set_next_event,
184 .rating = 200, 183 .rating = 200,
@@ -186,18 +185,10 @@ static struct clock_event_device clockevent_epit = {
186 185
187static int __init epit_clockevent_init(struct clk *timer_clk) 186static int __init epit_clockevent_init(struct clk *timer_clk)
188{ 187{
189 unsigned int c = clk_get_rate(timer_clk);
190
191 clockevent_epit.mult = div_sc(c, NSEC_PER_SEC,
192 clockevent_epit.shift);
193 clockevent_epit.max_delta_ns =
194 clockevent_delta2ns(0xfffffffe, &clockevent_epit);
195 clockevent_epit.min_delta_ns =
196 clockevent_delta2ns(0x800, &clockevent_epit);
197
198 clockevent_epit.cpumask = cpumask_of(0); 188 clockevent_epit.cpumask = cpumask_of(0);
199 189 clockevents_config_and_register(&clockevent_epit,
200 clockevents_register_device(&clockevent_epit); 190 clk_get_rate(timer_clk),
191 0x800, 0xfffffffe);
201 192
202 return 0; 193 return 0;
203} 194}
diff --git a/arch/arm/mach-imx/time.c b/arch/arm/mach-imx/time.c
index f017302f6d09..62769df36db1 100644
--- a/arch/arm/mach-imx/time.c
+++ b/arch/arm/mach-imx/time.c
@@ -256,7 +256,6 @@ static struct irqaction mxc_timer_irq = {
256static struct clock_event_device clockevent_mxc = { 256static struct clock_event_device clockevent_mxc = {
257 .name = "mxc_timer1", 257 .name = "mxc_timer1",
258 .features = CLOCK_EVT_FEAT_ONESHOT, 258 .features = CLOCK_EVT_FEAT_ONESHOT,
259 .shift = 32,
260 .set_mode = mxc_set_mode, 259 .set_mode = mxc_set_mode,
261 .set_next_event = mx1_2_set_next_event, 260 .set_next_event = mx1_2_set_next_event,
262 .rating = 200, 261 .rating = 200,
@@ -264,21 +263,13 @@ static struct clock_event_device clockevent_mxc = {
264 263
265static int __init mxc_clockevent_init(struct clk *timer_clk) 264static int __init mxc_clockevent_init(struct clk *timer_clk)
266{ 265{
267 unsigned int c = clk_get_rate(timer_clk);
268
269 if (timer_is_v2()) 266 if (timer_is_v2())
270 clockevent_mxc.set_next_event = v2_set_next_event; 267 clockevent_mxc.set_next_event = v2_set_next_event;
271 268
272 clockevent_mxc.mult = div_sc(c, NSEC_PER_SEC,
273 clockevent_mxc.shift);
274 clockevent_mxc.max_delta_ns =
275 clockevent_delta2ns(0xfffffffe, &clockevent_mxc);
276 clockevent_mxc.min_delta_ns =
277 clockevent_delta2ns(0xff, &clockevent_mxc);
278
279 clockevent_mxc.cpumask = cpumask_of(0); 269 clockevent_mxc.cpumask = cpumask_of(0);
280 270 clockevents_config_and_register(&clockevent_mxc,
281 clockevents_register_device(&clockevent_mxc); 271 clk_get_rate(timer_clk),
272 0xff, 0xfffffffe);
282 273
283 return 0; 274 return 0;
284} 275}
diff --git a/arch/arm/mach-ixp4xx/common.c b/arch/arm/mach-ixp4xx/common.c
index 8c0c0e2d0727..65ff98cc865c 100644
--- a/arch/arm/mach-ixp4xx/common.c
+++ b/arch/arm/mach-ixp4xx/common.c
@@ -523,22 +523,15 @@ static struct clock_event_device clockevent_ixp4xx = {
523 .name = "ixp4xx timer1", 523 .name = "ixp4xx timer1",
524 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 524 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
525 .rating = 200, 525 .rating = 200,
526 .shift = 24,
527 .set_mode = ixp4xx_set_mode, 526 .set_mode = ixp4xx_set_mode,
528 .set_next_event = ixp4xx_set_next_event, 527 .set_next_event = ixp4xx_set_next_event,
529}; 528};
530 529
531static void __init ixp4xx_clockevent_init(void) 530static void __init ixp4xx_clockevent_init(void)
532{ 531{
533 clockevent_ixp4xx.mult = div_sc(IXP4XX_TIMER_FREQ, NSEC_PER_SEC,
534 clockevent_ixp4xx.shift);
535 clockevent_ixp4xx.max_delta_ns =
536 clockevent_delta2ns(0xfffffffe, &clockevent_ixp4xx);
537 clockevent_ixp4xx.min_delta_ns =
538 clockevent_delta2ns(0xf, &clockevent_ixp4xx);
539 clockevent_ixp4xx.cpumask = cpumask_of(0); 532 clockevent_ixp4xx.cpumask = cpumask_of(0);
540 533 clockevents_config_and_register(&clockevent_ixp4xx, IXP4XX_TIMER_FREQ,
541 clockevents_register_device(&clockevent_ixp4xx); 534 0xf, 0xfffffffe);
542} 535}
543 536
544void ixp4xx_restart(char mode, const char *cmd) 537void ixp4xx_restart(char mode, const char *cmd)
diff --git a/arch/arm/mach-lpc32xx/timer.c b/arch/arm/mach-lpc32xx/timer.c
index c40667c33161..502b3c6ee295 100644
--- a/arch/arm/mach-lpc32xx/timer.c
+++ b/arch/arm/mach-lpc32xx/timer.c
@@ -70,7 +70,6 @@ static void lpc32xx_clkevt_mode(enum clock_event_mode mode,
70static struct clock_event_device lpc32xx_clkevt = { 70static struct clock_event_device lpc32xx_clkevt = {
71 .name = "lpc32xx_clkevt", 71 .name = "lpc32xx_clkevt",
72 .features = CLOCK_EVT_FEAT_ONESHOT, 72 .features = CLOCK_EVT_FEAT_ONESHOT,
73 .shift = 32,
74 .rating = 300, 73 .rating = 300,
75 .set_next_event = lpc32xx_clkevt_next_event, 74 .set_next_event = lpc32xx_clkevt_next_event,
76 .set_mode = lpc32xx_clkevt_mode, 75 .set_mode = lpc32xx_clkevt_mode,
@@ -141,14 +140,8 @@ static void __init lpc32xx_timer_init(void)
141 setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq); 140 setup_irq(IRQ_LPC32XX_TIMER0, &lpc32xx_timer_irq);
142 141
143 /* Setup the clockevent structure. */ 142 /* Setup the clockevent structure. */
144 lpc32xx_clkevt.mult = div_sc(clkrate, NSEC_PER_SEC,
145 lpc32xx_clkevt.shift);
146 lpc32xx_clkevt.max_delta_ns = clockevent_delta2ns(-1,
147 &lpc32xx_clkevt);
148 lpc32xx_clkevt.min_delta_ns = clockevent_delta2ns(1,
149 &lpc32xx_clkevt) + 1;
150 lpc32xx_clkevt.cpumask = cpumask_of(0); 143 lpc32xx_clkevt.cpumask = cpumask_of(0);
151 clockevents_register_device(&lpc32xx_clkevt); 144 clockevents_config_and_register(&lpc32xx_clkevt, clkrate, 1, -1);
152 145
153 /* Use timer1 as clock source. */ 146 /* Use timer1 as clock source. */
154 __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET, 147 __raw_writel(LPC32XX_TIMER_CNTR_TCR_RESET,
diff --git a/arch/arm/mach-mmp/time.c b/arch/arm/mach-mmp/time.c
index 936447c70977..86a18b3d252e 100644
--- a/arch/arm/mach-mmp/time.c
+++ b/arch/arm/mach-mmp/time.c
@@ -141,7 +141,6 @@ static void timer_set_mode(enum clock_event_mode mode,
141static struct clock_event_device ckevt = { 141static struct clock_event_device ckevt = {
142 .name = "clockevent", 142 .name = "clockevent",
143 .features = CLOCK_EVT_FEAT_ONESHOT, 143 .features = CLOCK_EVT_FEAT_ONESHOT,
144 .shift = 32,
145 .rating = 200, 144 .rating = 200,
146 .set_next_event = timer_set_next_event, 145 .set_next_event = timer_set_next_event,
147 .set_mode = timer_set_mode, 146 .set_mode = timer_set_mode,
@@ -198,15 +197,13 @@ void __init timer_init(int irq)
198 197
199 setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE); 198 setup_sched_clock(mmp_read_sched_clock, 32, CLOCK_TICK_RATE);
200 199
201 ckevt.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC, ckevt.shift);
202 ckevt.max_delta_ns = clockevent_delta2ns(MAX_DELTA, &ckevt);
203 ckevt.min_delta_ns = clockevent_delta2ns(MIN_DELTA, &ckevt);
204 ckevt.cpumask = cpumask_of(0); 200 ckevt.cpumask = cpumask_of(0);
205 201
206 setup_irq(irq, &timer_irq); 202 setup_irq(irq, &timer_irq);
207 203
208 clocksource_register_hz(&cksrc, CLOCK_TICK_RATE); 204 clocksource_register_hz(&cksrc, CLOCK_TICK_RATE);
209 clockevents_register_device(&ckevt); 205 clockevents_config_and_register(&ckevt, CLOCK_TICK_RATE,
206 MIN_DELTA, MAX_DELTA);
210} 207}
211 208
212#ifdef CONFIG_OF 209#ifdef CONFIG_OF
diff --git a/arch/arm/mach-msm/timer.c b/arch/arm/mach-msm/timer.c
index 476549a8a709..b9e7449adcde 100644
--- a/arch/arm/mach-msm/timer.c
+++ b/arch/arm/mach-msm/timer.c
@@ -144,13 +144,9 @@ static int __cpuinit msm_local_timer_setup(struct clock_event_device *evt)
144 evt->rating = msm_clockevent.rating; 144 evt->rating = msm_clockevent.rating;
145 evt->set_mode = msm_timer_set_mode; 145 evt->set_mode = msm_timer_set_mode;
146 evt->set_next_event = msm_timer_set_next_event; 146 evt->set_next_event = msm_timer_set_next_event;
147 evt->shift = msm_clockevent.shift;
148 evt->mult = div_sc(GPT_HZ, NSEC_PER_SEC, evt->shift);
149 evt->max_delta_ns = clockevent_delta2ns(0xf0000000, evt);
150 evt->min_delta_ns = clockevent_delta2ns(4, evt);
151 147
152 *__this_cpu_ptr(msm_evt.percpu_evt) = evt; 148 *__this_cpu_ptr(msm_evt.percpu_evt) = evt;
153 clockevents_register_device(evt); 149 clockevents_config_and_register(evt, GPT_HZ, 4, 0xf0000000);
154 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING); 150 enable_percpu_irq(evt->irq, IRQ_TYPE_EDGE_RISING);
155 return 0; 151 return 0;
156} 152}
diff --git a/arch/arm/mach-mxs/timer.c b/arch/arm/mach-mxs/timer.c
index 856f4c796061..27451b1ba3f1 100644
--- a/arch/arm/mach-mxs/timer.c
+++ b/arch/arm/mach-mxs/timer.c
@@ -195,7 +195,6 @@ static void mxs_set_mode(enum clock_event_mode mode,
195static struct clock_event_device mxs_clockevent_device = { 195static struct clock_event_device mxs_clockevent_device = {
196 .name = "mxs_timrot", 196 .name = "mxs_timrot",
197 .features = CLOCK_EVT_FEAT_ONESHOT, 197 .features = CLOCK_EVT_FEAT_ONESHOT,
198 .shift = 32,
199 .set_mode = mxs_set_mode, 198 .set_mode = mxs_set_mode,
200 .set_next_event = timrotv2_set_next_event, 199 .set_next_event = timrotv2_set_next_event,
201 .rating = 200, 200 .rating = 200,
@@ -203,25 +202,12 @@ static struct clock_event_device mxs_clockevent_device = {
203 202
204static int __init mxs_clockevent_init(struct clk *timer_clk) 203static int __init mxs_clockevent_init(struct clk *timer_clk)
205{ 204{
206 unsigned int c = clk_get_rate(timer_clk); 205 if (timrot_is_v1())
207
208 mxs_clockevent_device.mult =
209 div_sc(c, NSEC_PER_SEC, mxs_clockevent_device.shift);
210 mxs_clockevent_device.cpumask = cpumask_of(0);
211 if (timrot_is_v1()) {
212 mxs_clockevent_device.set_next_event = timrotv1_set_next_event; 206 mxs_clockevent_device.set_next_event = timrotv1_set_next_event;
213 mxs_clockevent_device.max_delta_ns = 207 mxs_clockevent_device.cpumask = cpumask_of(0);
214 clockevent_delta2ns(0xfffe, &mxs_clockevent_device); 208 clockevents_config_and_register(&mxs_clockevent_device,
215 mxs_clockevent_device.min_delta_ns = 209 clk_get_rate(timer_clk), 0xf,
216 clockevent_delta2ns(0xf, &mxs_clockevent_device); 210 timrot_is_v1() ? 0xfffe : 0xfffffffe);
217 } else {
218 mxs_clockevent_device.max_delta_ns =
219 clockevent_delta2ns(0xfffffffe, &mxs_clockevent_device);
220 mxs_clockevent_device.min_delta_ns =
221 clockevent_delta2ns(0xf, &mxs_clockevent_device);
222 }
223
224 clockevents_register_device(&mxs_clockevent_device);
225 211
226 return 0; 212 return 0;
227} 213}
diff --git a/arch/arm/mach-netx/time.c b/arch/arm/mach-netx/time.c
index e24c141ba489..d780a93e1cf7 100644
--- a/arch/arm/mach-netx/time.c
+++ b/arch/arm/mach-netx/time.c
@@ -76,7 +76,6 @@ static int netx_set_next_event(unsigned long evt,
76 76
77static struct clock_event_device netx_clockevent = { 77static struct clock_event_device netx_clockevent = {
78 .name = "netx-timer" __stringify(TIMER_CLOCKEVENT), 78 .name = "netx-timer" __stringify(TIMER_CLOCKEVENT),
79 .shift = 32,
80 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 79 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
81 .set_next_event = netx_set_next_event, 80 .set_next_event = netx_set_next_event,
82 .set_mode = netx_set_mode, 81 .set_mode = netx_set_mode,
@@ -140,16 +139,11 @@ static void __init netx_timer_init(void)
140 clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE), 139 clocksource_mmio_init(NETX_GPIO_COUNTER_CURRENT(TIMER_CLOCKSOURCE),
141 "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up); 140 "netx_timer", CLOCK_TICK_RATE, 200, 32, clocksource_mmio_readl_up);
142 141
143 netx_clockevent.mult = div_sc(CLOCK_TICK_RATE, NSEC_PER_SEC,
144 netx_clockevent.shift);
145 netx_clockevent.max_delta_ns =
146 clockevent_delta2ns(0xfffffffe, &netx_clockevent);
147 /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine. 142 /* with max_delta_ns >= delta2ns(0x800) the system currently runs fine.
148 * Adding some safety ... */ 143 * Adding some safety ... */
149 netx_clockevent.min_delta_ns =
150 clockevent_delta2ns(0xa00, &netx_clockevent);
151 netx_clockevent.cpumask = cpumask_of(0); 144 netx_clockevent.cpumask = cpumask_of(0);
152 clockevents_register_device(&netx_clockevent); 145 clockevents_config_and_register(&netx_clockevent, CLOCK_TICK_RATE,
146 0xa00, 0xfffffffe);
153} 147}
154 148
155struct sys_timer netx_timer = { 149struct sys_timer netx_timer = {
diff --git a/arch/arm/mach-omap1/time.c b/arch/arm/mach-omap1/time.c
index 4d4816fd6fc9..5b7c556e9b12 100644
--- a/arch/arm/mach-omap1/time.c
+++ b/arch/arm/mach-omap1/time.c
@@ -145,7 +145,6 @@ static void omap_mpu_set_mode(enum clock_event_mode mode,
145static struct clock_event_device clockevent_mpu_timer1 = { 145static struct clock_event_device clockevent_mpu_timer1 = {
146 .name = "mpu_timer1", 146 .name = "mpu_timer1",
147 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 147 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
148 .shift = 32,
149 .set_next_event = omap_mpu_set_next_event, 148 .set_next_event = omap_mpu_set_next_event,
150 .set_mode = omap_mpu_set_mode, 149 .set_mode = omap_mpu_set_mode,
151}; 150};
@@ -170,15 +169,9 @@ static __init void omap_init_mpu_timer(unsigned long rate)
170 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq); 169 setup_irq(INT_TIMER1, &omap_mpu_timer1_irq);
171 omap_mpu_timer_start(0, (rate / HZ) - 1, 1); 170 omap_mpu_timer_start(0, (rate / HZ) - 1, 1);
172 171
173 clockevent_mpu_timer1.mult = div_sc(rate, NSEC_PER_SEC,
174 clockevent_mpu_timer1.shift);
175 clockevent_mpu_timer1.max_delta_ns =
176 clockevent_delta2ns(-1, &clockevent_mpu_timer1);
177 clockevent_mpu_timer1.min_delta_ns =
178 clockevent_delta2ns(1, &clockevent_mpu_timer1);
179
180 clockevent_mpu_timer1.cpumask = cpumask_of(0); 172 clockevent_mpu_timer1.cpumask = cpumask_of(0);
181 clockevents_register_device(&clockevent_mpu_timer1); 173 clockevents_config_and_register(&clockevent_mpu_timer1, rate,
174 1, -1);
182} 175}
183 176
184 177
diff --git a/arch/arm/mach-omap1/timer32k.c b/arch/arm/mach-omap1/timer32k.c
index 41152fadd4c0..0b74246ba62c 100644
--- a/arch/arm/mach-omap1/timer32k.c
+++ b/arch/arm/mach-omap1/timer32k.c
@@ -140,7 +140,6 @@ static void omap_32k_timer_set_mode(enum clock_event_mode mode,
140static struct clock_event_device clockevent_32k_timer = { 140static struct clock_event_device clockevent_32k_timer = {
141 .name = "32k-timer", 141 .name = "32k-timer",
142 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 142 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
143 .shift = 32,
144 .set_next_event = omap_32k_timer_set_next_event, 143 .set_next_event = omap_32k_timer_set_next_event,
145 .set_mode = omap_32k_timer_set_mode, 144 .set_mode = omap_32k_timer_set_mode,
146}; 145};
@@ -165,16 +164,9 @@ static __init void omap_init_32k_timer(void)
165{ 164{
166 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq); 165 setup_irq(INT_OS_TIMER, &omap_32k_timer_irq);
167 166
168 clockevent_32k_timer.mult = div_sc(OMAP_32K_TICKS_PER_SEC,
169 NSEC_PER_SEC,
170 clockevent_32k_timer.shift);
171 clockevent_32k_timer.max_delta_ns =
172 clockevent_delta2ns(0xfffffffe, &clockevent_32k_timer);
173 clockevent_32k_timer.min_delta_ns =
174 clockevent_delta2ns(1, &clockevent_32k_timer);
175
176 clockevent_32k_timer.cpumask = cpumask_of(0); 167 clockevent_32k_timer.cpumask = cpumask_of(0);
177 clockevents_register_device(&clockevent_32k_timer); 168 clockevents_config_and_register(&clockevent_32k_timer,
169 OMAP_32K_TICKS_PER_SEC, 1, 0xfffffffe);
178} 170}
179 171
180/* 172/*
diff --git a/arch/arm/mach-omap2/timer.c b/arch/arm/mach-omap2/timer.c
index 691aa674665a..3e2ffdbce220 100644
--- a/arch/arm/mach-omap2/timer.c
+++ b/arch/arm/mach-omap2/timer.c
@@ -131,7 +131,6 @@ static void omap2_gp_timer_set_mode(enum clock_event_mode mode,
131static struct clock_event_device clockevent_gpt = { 131static struct clock_event_device clockevent_gpt = {
132 .name = "gp_timer", 132 .name = "gp_timer",
133 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 133 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
134 .shift = 32,
135 .rating = 300, 134 .rating = 300,
136 .set_next_event = omap2_gp_timer_set_next_event, 135 .set_next_event = omap2_gp_timer_set_next_event,
137 .set_mode = omap2_gp_timer_set_mode, 136 .set_mode = omap2_gp_timer_set_mode,
@@ -340,17 +339,11 @@ static void __init omap2_gp_clockevent_init(int gptimer_id,
340 339
341 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW); 340 __omap_dm_timer_int_enable(&clkev, OMAP_TIMER_INT_OVERFLOW);
342 341
343 clockevent_gpt.mult = div_sc(clkev.rate, NSEC_PER_SEC,
344 clockevent_gpt.shift);
345 clockevent_gpt.max_delta_ns =
346 clockevent_delta2ns(0xffffffff, &clockevent_gpt);
347 clockevent_gpt.min_delta_ns =
348 clockevent_delta2ns(3, &clockevent_gpt);
349 /* Timer internal resynch latency. */
350
351 clockevent_gpt.cpumask = cpu_possible_mask; 342 clockevent_gpt.cpumask = cpu_possible_mask;
352 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev); 343 clockevent_gpt.irq = omap_dm_timer_get_irq(&clkev);
353 clockevents_register_device(&clockevent_gpt); 344 clockevents_config_and_register(&clockevent_gpt, clkev.rate,
345 3, /* Timer internal resynch latency */
346 0xffffffff);
354 347
355 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n", 348 pr_info("OMAP clockevent source: GPTIMER%d at %lu Hz\n",
356 gptimer_id, clkev.rate); 349 gptimer_id, clkev.rate);
diff --git a/arch/arm/mach-prima2/timer.c b/arch/arm/mach-prima2/timer.c
index d95bf252f694..4f69e678e83c 100644
--- a/arch/arm/mach-prima2/timer.c
+++ b/arch/arm/mach-prima2/timer.c
@@ -175,15 +175,9 @@ static u32 notrace sirfsoc_read_sched_clock(void)
175 175
176static void __init sirfsoc_clockevent_init(void) 176static void __init sirfsoc_clockevent_init(void)
177{ 177{
178 clockevents_calc_mult_shift(&sirfsoc_clockevent, CLOCK_TICK_RATE, 60);
179
180 sirfsoc_clockevent.max_delta_ns =
181 clockevent_delta2ns(-2, &sirfsoc_clockevent);
182 sirfsoc_clockevent.min_delta_ns =
183 clockevent_delta2ns(2, &sirfsoc_clockevent);
184
185 sirfsoc_clockevent.cpumask = cpumask_of(0); 178 sirfsoc_clockevent.cpumask = cpumask_of(0);
186 clockevents_register_device(&sirfsoc_clockevent); 179 clockevents_config_and_register(&sirfsoc_clockevent, CLOCK_TICK_RATE,
180 2, -2);
187} 181}
188 182
189/* initialize the kernel jiffy timer source */ 183/* initialize the kernel jiffy timer source */
diff --git a/arch/arm/mach-pxa/time.c b/arch/arm/mach-pxa/time.c
index 4bc47d63698b..08cc47f6a79f 100644
--- a/arch/arm/mach-pxa/time.c
+++ b/arch/arm/mach-pxa/time.c
@@ -113,18 +113,14 @@ static void __init pxa_timer_init(void)
113 113
114 setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate); 114 setup_sched_clock(pxa_read_sched_clock, 32, clock_tick_rate);
115 115
116 clockevents_calc_mult_shift(&ckevt_pxa_osmr0, clock_tick_rate, 4);
117 ckevt_pxa_osmr0.max_delta_ns =
118 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
119 ckevt_pxa_osmr0.min_delta_ns =
120 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_pxa_osmr0) + 1;
121 ckevt_pxa_osmr0.cpumask = cpumask_of(0); 116 ckevt_pxa_osmr0.cpumask = cpumask_of(0);
122 117
123 setup_irq(IRQ_OST0, &pxa_ost0_irq); 118 setup_irq(IRQ_OST0, &pxa_ost0_irq);
124 119
125 clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32, 120 clocksource_mmio_init(OSCR, "oscr0", clock_tick_rate, 200, 32,
126 clocksource_mmio_readl_up); 121 clocksource_mmio_readl_up);
127 clockevents_register_device(&ckevt_pxa_osmr0); 122 clockevents_config_and_register(&ckevt_pxa_osmr0, clock_tick_rate,
123 MIN_OSCR_DELTA * 2, 0x7fffffff);
128} 124}
129 125
130#ifdef CONFIG_PM 126#ifdef CONFIG_PM
diff --git a/arch/arm/mach-sa1100/time.c b/arch/arm/mach-sa1100/time.c
index 80702c9ecc77..6e980da5ebfe 100644
--- a/arch/arm/mach-sa1100/time.c
+++ b/arch/arm/mach-sa1100/time.c
@@ -91,18 +91,14 @@ static void __init sa1100_timer_init(void)
91 91
92 setup_sched_clock(sa1100_read_sched_clock, 32, 3686400); 92 setup_sched_clock(sa1100_read_sched_clock, 32, 3686400);
93 93
94 clockevents_calc_mult_shift(&ckevt_sa1100_osmr0, 3686400, 4);
95 ckevt_sa1100_osmr0.max_delta_ns =
96 clockevent_delta2ns(0x7fffffff, &ckevt_sa1100_osmr0);
97 ckevt_sa1100_osmr0.min_delta_ns =
98 clockevent_delta2ns(MIN_OSCR_DELTA * 2, &ckevt_sa1100_osmr0) + 1;
99 ckevt_sa1100_osmr0.cpumask = cpumask_of(0); 94 ckevt_sa1100_osmr0.cpumask = cpumask_of(0);
100 95
101 setup_irq(IRQ_OST0, &sa1100_timer_irq); 96 setup_irq(IRQ_OST0, &sa1100_timer_irq);
102 97
103 clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32, 98 clocksource_mmio_init(OSCR, "oscr", CLOCK_TICK_RATE, 200, 32,
104 clocksource_mmio_readl_up); 99 clocksource_mmio_readl_up);
105 clockevents_register_device(&ckevt_sa1100_osmr0); 100 clockevents_config_and_register(&ckevt_sa1100_osmr0, 3686400,
101 MIN_OSCR_DELTA * 2, 0x7fffffff);
106} 102}
107 103
108#ifdef CONFIG_PM 104#ifdef CONFIG_PM
diff --git a/arch/arm/mach-tegra/timer.c b/arch/arm/mach-tegra/timer.c
index e4863f3e9ee7..bc86161759b6 100644
--- a/arch/arm/mach-tegra/timer.c
+++ b/arch/arm/mach-tegra/timer.c
@@ -259,14 +259,10 @@ static void __init tegra_init_timer(void)
259 BUG(); 259 BUG();
260 } 260 }
261 261
262 clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
263 tegra_clockevent.max_delta_ns =
264 clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
265 tegra_clockevent.min_delta_ns =
266 clockevent_delta2ns(0x1, &tegra_clockevent);
267 tegra_clockevent.cpumask = cpu_all_mask; 262 tegra_clockevent.cpumask = cpu_all_mask;
268 tegra_clockevent.irq = tegra_timer_irq.irq; 263 tegra_clockevent.irq = tegra_timer_irq.irq;
269 clockevents_register_device(&tegra_clockevent); 264 clockevents_config_and_register(&tegra_clockevent, 1000000,
265 0x1, 0x1fffffff);
270#ifdef CONFIG_HAVE_ARM_TWD 266#ifdef CONFIG_HAVE_ARM_TWD
271 twd_local_timer_of_register(); 267 twd_local_timer_of_register();
272#endif 268#endif
diff --git a/arch/arm/mach-vt8500/timer.c b/arch/arm/mach-vt8500/timer.c
index 3dd21a47881f..ed66cf07d3c6 100644
--- a/arch/arm/mach-vt8500/timer.c
+++ b/arch/arm/mach-vt8500/timer.c
@@ -168,17 +168,12 @@ void __init vt8500_timer_init(void)
168 pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n", 168 pr_err("%s: vt8500_timer_init: clocksource_register failed for %s\n",
169 __func__, clocksource.name); 169 __func__, clocksource.name);
170 170
171 clockevents_calc_mult_shift(&clockevent, VT8500_TIMER_HZ, 4);
172
173 /* copy-pasted from mach-msm; no idea */
174 clockevent.max_delta_ns =
175 clockevent_delta2ns(0xf0000000, &clockevent);
176 clockevent.min_delta_ns = clockevent_delta2ns(4, &clockevent);
177 clockevent.cpumask = cpumask_of(0); 171 clockevent.cpumask = cpumask_of(0);
178 172
179 if (setup_irq(timer_irq, &irq)) 173 if (setup_irq(timer_irq, &irq))
180 pr_err("%s: setup_irq failed for %s\n", __func__, 174 pr_err("%s: setup_irq failed for %s\n", __func__,
181 clockevent.name); 175 clockevent.name);
182 clockevents_register_device(&clockevent); 176 clockevents_config_and_register(&clockevent, VT8500_TIMER_HZ,
177 4, 0xf0000000);
183} 178}
184 179
diff --git a/arch/arm/mach-w90x900/time.c b/arch/arm/mach-w90x900/time.c
index fa27c498ac09..b61ab3ed361c 100644
--- a/arch/arm/mach-w90x900/time.c
+++ b/arch/arm/mach-w90x900/time.c
@@ -91,7 +91,6 @@ static int nuc900_clockevent_setnextevent(unsigned long evt,
91 91
92static struct clock_event_device nuc900_clockevent_device = { 92static struct clock_event_device nuc900_clockevent_device = {
93 .name = "nuc900-timer0", 93 .name = "nuc900-timer0",
94 .shift = 32,
95 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT, 94 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
96 .set_mode = nuc900_clockevent_setmode, 95 .set_mode = nuc900_clockevent_setmode,
97 .set_next_event = nuc900_clockevent_setnextevent, 96 .set_next_event = nuc900_clockevent_setnextevent,
@@ -133,15 +132,10 @@ static void __init nuc900_clockevents_init(void)
133 __raw_writel(RESETINT, REG_TISR); 132 __raw_writel(RESETINT, REG_TISR);
134 setup_irq(IRQ_TIMER0, &nuc900_timer0_irq); 133 setup_irq(IRQ_TIMER0, &nuc900_timer0_irq);
135 134
136 nuc900_clockevent_device.mult = div_sc(rate, NSEC_PER_SEC,
137 nuc900_clockevent_device.shift);
138 nuc900_clockevent_device.max_delta_ns = clockevent_delta2ns(0xffffffff,
139 &nuc900_clockevent_device);
140 nuc900_clockevent_device.min_delta_ns = clockevent_delta2ns(0xf,
141 &nuc900_clockevent_device);
142 nuc900_clockevent_device.cpumask = cpumask_of(0); 135 nuc900_clockevent_device.cpumask = cpumask_of(0);
143 136
144 clockevents_register_device(&nuc900_clockevent_device); 137 clockevents_config_and_register(&nuc900_clockevent_device, rate,
138 0xf, 0xffffffff);
145} 139}
146 140
147static void __init nuc900_clocksource_init(void) 141static void __init nuc900_clocksource_init(void)
diff --git a/arch/arm/plat-iop/time.c b/arch/arm/plat-iop/time.c
index cbfbbe461788..837a2d52e9db 100644
--- a/arch/arm/plat-iop/time.c
+++ b/arch/arm/plat-iop/time.c
@@ -156,14 +156,9 @@ void __init iop_init_time(unsigned long tick_rate)
156 write_tmr0(timer_ctl & ~IOP_TMR_EN); 156 write_tmr0(timer_ctl & ~IOP_TMR_EN);
157 write_tisr(1); 157 write_tisr(1);
158 setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq); 158 setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
159 clockevents_calc_mult_shift(&iop_clockevent,
160 tick_rate, IOP_MIN_RANGE);
161 iop_clockevent.max_delta_ns =
162 clockevent_delta2ns(0xfffffffe, &iop_clockevent);
163 iop_clockevent.min_delta_ns =
164 clockevent_delta2ns(0xf, &iop_clockevent);
165 iop_clockevent.cpumask = cpumask_of(0); 159 iop_clockevent.cpumask = cpumask_of(0);
166 clockevents_register_device(&iop_clockevent); 160 clockevents_config_and_register(&iop_clockevent, tick_rate,
161 0xf, 0xfffffffe);
167 162
168 /* 163 /*
169 * Set up free-running clocksource timer 1. 164 * Set up free-running clocksource timer 1.
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 0f4fa863dd55..5d5ac0f05422 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -156,7 +156,6 @@ orion_clkevt_mode(enum clock_event_mode mode, struct clock_event_device *dev)
156static struct clock_event_device orion_clkevt = { 156static struct clock_event_device orion_clkevt = {
157 .name = "orion_tick", 157 .name = "orion_tick",
158 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, 158 .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
159 .shift = 32,
160 .rating = 300, 159 .rating = 300,
161 .set_next_event = orion_clkevt_next_event, 160 .set_next_event = orion_clkevt_next_event,
162 .set_mode = orion_clkevt_mode, 161 .set_mode = orion_clkevt_mode,
@@ -221,9 +220,6 @@ orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
221 * Setup clockevent timer (interrupt-driven). 220 * Setup clockevent timer (interrupt-driven).
222 */ 221 */
223 setup_irq(irq, &orion_timer_irq); 222 setup_irq(irq, &orion_timer_irq);
224 orion_clkevt.mult = div_sc(tclk, NSEC_PER_SEC, orion_clkevt.shift);
225 orion_clkevt.max_delta_ns = clockevent_delta2ns(0xfffffffe, &orion_clkevt);
226 orion_clkevt.min_delta_ns = clockevent_delta2ns(1, &orion_clkevt);
227 orion_clkevt.cpumask = cpumask_of(0); 223 orion_clkevt.cpumask = cpumask_of(0);
228 clockevents_register_device(&orion_clkevt); 224 clockevents_config_and_register(&orion_clkevt, tclk, 1, 0xfffffffe);
229} 225}
diff --git a/arch/arm/plat-samsung/s5p-time.c b/arch/arm/plat-samsung/s5p-time.c
index 028b6e877eb9..798268b3159a 100644
--- a/arch/arm/plat-samsung/s5p-time.c
+++ b/arch/arm/plat-samsung/s5p-time.c
@@ -274,15 +274,8 @@ static void __init s5p_clockevent_init(void)
274 clock_rate = clk_get_rate(tin_event); 274 clock_rate = clk_get_rate(tin_event);
275 clock_count_per_tick = clock_rate / HZ; 275 clock_count_per_tick = clock_rate / HZ;
276 276
277 clockevents_calc_mult_shift(&time_event_device,
278 clock_rate, S5PTIMER_MIN_RANGE);
279 time_event_device.max_delta_ns =
280 clockevent_delta2ns(-1, &time_event_device);
281 time_event_device.min_delta_ns =
282 clockevent_delta2ns(1, &time_event_device);
283
284 time_event_device.cpumask = cpumask_of(0); 277 time_event_device.cpumask = cpumask_of(0);
285 clockevents_register_device(&time_event_device); 278 clockevents_config_and_register(&time_event_device, clock_rate, 1, -1);
286 279
287 irq_number = timer_source.event_id + IRQ_TIMER0; 280 irq_number = timer_source.event_id + IRQ_TIMER0;
288 setup_irq(irq_number, &s5p_clock_event_irq); 281 setup_irq(irq_number, &s5p_clock_event_irq);
diff --git a/arch/arm/plat-spear/time.c b/arch/arm/plat-spear/time.c
index 03321af5de9f..bd5c53cd6962 100644
--- a/arch/arm/plat-spear/time.c
+++ b/arch/arm/plat-spear/time.c
@@ -186,15 +186,9 @@ static void __init spear_clockevent_init(int irq)
186 tick_rate = clk_get_rate(gpt_clk); 186 tick_rate = clk_get_rate(gpt_clk);
187 tick_rate >>= CTRL_PRESCALER16; 187 tick_rate >>= CTRL_PRESCALER16;
188 188
189 clockevents_calc_mult_shift(&clkevt, tick_rate, SPEAR_MIN_RANGE);
190
191 clkevt.max_delta_ns = clockevent_delta2ns(0xfff0,
192 &clkevt);
193 clkevt.min_delta_ns = clockevent_delta2ns(3, &clkevt);
194
195 clkevt.cpumask = cpumask_of(0); 189 clkevt.cpumask = cpumask_of(0);
196 190
197 clockevents_register_device(&clkevt); 191 clockevents_config_and_register(&clkevt, tick_rate, 3, 0xfff0);
198 192
199 setup_irq(irq, &spear_timer_irq); 193 setup_irq(irq, &spear_timer_irq);
200} 194}