diff options
| -rw-r--r-- | arch/mips/kernel/cpu-probe.c | 28 |
1 files changed, 24 insertions, 4 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c index 5465dc183e5a..040b83de00ac 100644 --- a/arch/mips/kernel/cpu-probe.c +++ b/arch/mips/kernel/cpu-probe.c | |||
| @@ -376,13 +376,33 @@ static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) | |||
| 376 | __cpu_name[cpu] = "R4000PC"; | 376 | __cpu_name[cpu] = "R4000PC"; |
| 377 | } | 377 | } |
| 378 | } else { | 378 | } else { |
| 379 | int cca = read_c0_config() & CONF_CM_CMASK; | ||
| 380 | int mc; | ||
| 381 | |||
| 382 | /* | ||
| 383 | * SC and MC versions can't be reliably told apart, | ||
| 384 | * but only the latter support coherent caching | ||
| 385 | * modes so assume the firmware has set the KSEG0 | ||
| 386 | * coherency attribute reasonably (if uncached, we | ||
| 387 | * assume SC). | ||
| 388 | */ | ||
| 389 | switch (cca) { | ||
| 390 | case CONF_CM_CACHABLE_CE: | ||
| 391 | case CONF_CM_CACHABLE_COW: | ||
| 392 | case CONF_CM_CACHABLE_CUW: | ||
| 393 | mc = 1; | ||
| 394 | break; | ||
| 395 | default: | ||
| 396 | mc = 0; | ||
| 397 | break; | ||
| 398 | } | ||
| 379 | if ((c->processor_id & PRID_REV_MASK) >= | 399 | if ((c->processor_id & PRID_REV_MASK) >= |
| 380 | PRID_REV_R4400) { | 400 | PRID_REV_R4400) { |
| 381 | c->cputype = CPU_R4400SC; | 401 | c->cputype = mc ? CPU_R4400MC : CPU_R4400SC; |
| 382 | __cpu_name[cpu] = "R4400SC"; | 402 | __cpu_name[cpu] = mc ? "R4400MC" : "R4400SC"; |
| 383 | } else { | 403 | } else { |
| 384 | c->cputype = CPU_R4000SC; | 404 | c->cputype = mc ? CPU_R4000MC : CPU_R4000SC; |
| 385 | __cpu_name[cpu] = "R4000SC"; | 405 | __cpu_name[cpu] = mc ? "R4000MC" : "R4000SC"; |
| 386 | } | 406 | } |
| 387 | } | 407 | } |
| 388 | 408 | ||
