diff options
-rw-r--r-- | arch/powerpc/include/asm/cputable.h | 85 | ||||
-rw-r--r-- | arch/powerpc/include/asm/feature-fixups.h | 30 | ||||
-rw-r--r-- | arch/powerpc/include/asm/mmu.h | 41 | ||||
-rw-r--r-- | arch/powerpc/kernel/cputable.c | 113 | ||||
-rw-r--r-- | arch/powerpc/kernel/head_32.S | 8 | ||||
-rw-r--r-- | arch/powerpc/kernel/head_fsl_booke.S | 4 | ||||
-rw-r--r-- | arch/powerpc/kernel/module.c | 6 | ||||
-rw-r--r-- | arch/powerpc/kernel/setup_32.c | 4 | ||||
-rw-r--r-- | arch/powerpc/kernel/setup_64.c | 2 | ||||
-rw-r--r-- | arch/powerpc/kernel/swsusp_32.S | 6 | ||||
-rw-r--r-- | arch/powerpc/kernel/vdso.c | 10 | ||||
-rw-r--r-- | arch/powerpc/kernel/vdso32/vdso32.lds.S | 3 | ||||
-rw-r--r-- | arch/powerpc/kernel/vdso64/vdso64.lds.S | 3 | ||||
-rw-r--r-- | arch/powerpc/kernel/vmlinux.lds.S | 6 | ||||
-rw-r--r-- | arch/powerpc/mm/ppc_mmu_32.c | 2 | ||||
-rw-r--r-- | arch/powerpc/platforms/powermac/sleep.S | 5 |
16 files changed, 268 insertions, 60 deletions
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 31888322d76a..4911104791c3 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h | |||
@@ -82,6 +82,7 @@ struct cpu_spec { | |||
82 | char *cpu_name; | 82 | char *cpu_name; |
83 | unsigned long cpu_features; /* Kernel features */ | 83 | unsigned long cpu_features; /* Kernel features */ |
84 | unsigned int cpu_user_features; /* Userland features */ | 84 | unsigned int cpu_user_features; /* Userland features */ |
85 | unsigned int mmu_features; /* MMU features */ | ||
85 | 86 | ||
86 | /* cache line sizes */ | 87 | /* cache line sizes */ |
87 | unsigned int icache_bsize; | 88 | unsigned int icache_bsize; |
@@ -144,17 +145,14 @@ extern const char *powerpc_base_platform; | |||
144 | #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) | 145 | #define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040) |
145 | #define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080) | 146 | #define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080) |
146 | #define CPU_FTR_601 ASM_CONST(0x0000000000000100) | 147 | #define CPU_FTR_601 ASM_CONST(0x0000000000000100) |
147 | #define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200) | ||
148 | #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) | 148 | #define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400) |
149 | #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) | 149 | #define CPU_FTR_L3CR ASM_CONST(0x0000000000000800) |
150 | #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) | 150 | #define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000) |
151 | #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) | 151 | #define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000) |
152 | #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) | 152 | #define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000) |
153 | #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) | 153 | #define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000) |
154 | #define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000) | ||
155 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) | 154 | #define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000) |
156 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) | 155 | #define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000) |
157 | #define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000) | ||
158 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) | 156 | #define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000) |
159 | #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) | 157 | #define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000) |
160 | #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) | 158 | #define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000) |
@@ -266,107 +264,99 @@ extern const char *powerpc_base_platform; | |||
266 | !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ | 264 | !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \ |
267 | !defined(CONFIG_BOOKE)) | 265 | !defined(CONFIG_BOOKE)) |
268 | 266 | ||
269 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \ | 267 | #define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | \ |
270 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) | 268 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE) |
271 | #define CPU_FTRS_603 (CPU_FTR_COMMON | \ | 269 | #define CPU_FTRS_603 (CPU_FTR_COMMON | \ |
272 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ | 270 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
273 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) | 271 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
274 | #define CPU_FTRS_604 (CPU_FTR_COMMON | \ | 272 | #define CPU_FTRS_604 (CPU_FTR_COMMON | \ |
275 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE) | 273 | CPU_FTR_USE_TB | CPU_FTR_PPC_LE) |
276 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ | 274 | #define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \ |
277 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 275 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
278 | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) | 276 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
279 | #define CPU_FTRS_740 (CPU_FTR_COMMON | \ | 277 | #define CPU_FTRS_740 (CPU_FTR_COMMON | \ |
280 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 278 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
281 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 279 | CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ |
282 | CPU_FTR_PPC_LE) | 280 | CPU_FTR_PPC_LE) |
283 | #define CPU_FTRS_750 (CPU_FTR_COMMON | \ | 281 | #define CPU_FTRS_750 (CPU_FTR_COMMON | \ |
284 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 282 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
285 | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \ | 283 | CPU_FTR_TAU | CPU_FTR_MAYBE_CAN_NAP | \ |
286 | CPU_FTR_PPC_LE) | 284 | CPU_FTR_PPC_LE) |
287 | #define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS) | 285 | #define CPU_FTRS_750CL (CPU_FTRS_750) |
288 | #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) | 286 | #define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM) |
289 | #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) | 287 | #define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM) |
290 | #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \ | 288 | #define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX) |
291 | CPU_FTR_HAS_HIGH_BATS) | ||
292 | #define CPU_FTRS_750GX (CPU_FTRS_750FX) | 289 | #define CPU_FTRS_750GX (CPU_FTRS_750FX) |
293 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ | 290 | #define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \ |
294 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 291 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
295 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 292 | CPU_FTR_ALTIVEC_COMP | \ |
296 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) | 293 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
297 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ | 294 | #define CPU_FTRS_7400 (CPU_FTR_COMMON | \ |
298 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ | 295 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \ |
299 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \ | 296 | CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | \ |
300 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) | 297 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE) |
301 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ | 298 | #define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \ |
302 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 299 | CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
303 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 300 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
304 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) | 301 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
305 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ | 302 | #define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \ |
306 | CPU_FTR_USE_TB | \ | 303 | CPU_FTR_USE_TB | \ |
307 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 304 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
308 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 305 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
309 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 306 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
310 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) | 307 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
311 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ | 308 | #define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \ |
312 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ | 309 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ |
313 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 310 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
314 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 311 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
315 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | 312 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
316 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ | 313 | #define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \ |
317 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ | 314 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ |
318 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ | 315 | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \ |
319 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \ | 316 | CPU_FTR_SPEC7450 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
320 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) | ||
321 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ | 317 | #define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \ |
322 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ | 318 | CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \ |
323 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 319 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
324 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 320 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | \ |
325 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ | 321 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \ |
326 | CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE) | 322 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE) |
327 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ | 323 | #define CPU_FTRS_7455 (CPU_FTR_COMMON | \ |
328 | CPU_FTR_USE_TB | \ | 324 | CPU_FTR_USE_TB | \ |
329 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 325 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
330 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 326 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
331 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | ||
332 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) | 327 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
333 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ | 328 | #define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \ |
334 | CPU_FTR_USE_TB | \ | 329 | CPU_FTR_USE_TB | \ |
335 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 330 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
336 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 331 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
337 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | ||
338 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ | 332 | CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \ |
339 | CPU_FTR_NEED_PAIRED_STWCX) | 333 | CPU_FTR_NEED_PAIRED_STWCX) |
340 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ | 334 | #define CPU_FTRS_7447 (CPU_FTR_COMMON | \ |
341 | CPU_FTR_USE_TB | \ | 335 | CPU_FTR_USE_TB | \ |
342 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 336 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
343 | CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 337 | CPU_FTR_L3CR | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
344 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | ||
345 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) | 338 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
346 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ | 339 | #define CPU_FTRS_7447A (CPU_FTR_COMMON | \ |
347 | CPU_FTR_USE_TB | \ | 340 | CPU_FTR_USE_TB | \ |
348 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 341 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
349 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 342 | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
350 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | ||
351 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) | 343 | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
352 | #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ | 344 | #define CPU_FTRS_7448 (CPU_FTR_COMMON | \ |
353 | CPU_FTR_USE_TB | \ | 345 | CPU_FTR_USE_TB | \ |
354 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ | 346 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \ |
355 | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \ | 347 | CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR | \ |
356 | CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \ | ||
357 | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) | 348 | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX) |
358 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ | 349 | #define CPU_FTRS_82XX (CPU_FTR_COMMON | \ |
359 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) | 350 | CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB) |
360 | #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ | 351 | #define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \ |
361 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS) | 352 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP) |
362 | #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ | 353 | #define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \ |
363 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ | 354 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ |
364 | CPU_FTR_COMMON) | 355 | CPU_FTR_COMMON) |
365 | #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ | 356 | #define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \ |
366 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \ | 357 | CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | \ |
367 | CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) | 358 | CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE) |
368 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \ | 359 | #define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | CPU_FTR_USE_TB) |
369 | CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE) | ||
370 | #define CPU_FTRS_8XX (CPU_FTR_USE_TB) | 360 | #define CPU_FTRS_8XX (CPU_FTR_USE_TB) |
371 | #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) | 361 | #define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) |
372 | #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) | 362 | #define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) |
@@ -379,55 +369,54 @@ extern const char *powerpc_base_platform; | |||
379 | CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ | 369 | CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ |
380 | CPU_FTR_NOEXECUTE) | 370 | CPU_FTR_NOEXECUTE) |
381 | #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ | 371 | #define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
382 | CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \ | 372 | CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ |
383 | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) | 373 | CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) |
384 | #define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ | 374 | #define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \ |
385 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \ | 375 | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN | \ |
386 | CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE) | 376 | CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE) |
387 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) | 377 | #define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN) |
388 | 378 | ||
389 | /* 64-bit CPUs */ | 379 | /* 64-bit CPUs */ |
390 | #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 380 | #define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
391 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE) | 381 | CPU_FTR_IABR | CPU_FTR_PPC_LE) |
392 | #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 382 | #define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
393 | CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \ | 383 | CPU_FTR_IABR | \ |
394 | CPU_FTR_MMCRA | CPU_FTR_CTRL) | 384 | CPU_FTR_MMCRA | CPU_FTR_CTRL) |
395 | #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 385 | #define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
396 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 386 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
397 | CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ) | 387 | CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ) |
398 | #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 388 | #define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
399 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 389 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
400 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ | 390 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \ |
401 | CPU_FTR_CP_USE_DCBTZ) | 391 | CPU_FTR_CP_USE_DCBTZ) |
402 | #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 392 | #define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
403 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 393 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
404 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 394 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
405 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 395 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
406 | CPU_FTR_PURR) | 396 | CPU_FTR_PURR) |
407 | #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 397 | #define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
408 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 398 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
409 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 399 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
410 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 400 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
411 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ | 401 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
412 | CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD) | 402 | CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD) |
413 | #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 403 | #define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
414 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 404 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
415 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 405 | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
416 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ | 406 | CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \ |
417 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ | 407 | CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \ |
418 | CPU_FTR_DSCR | CPU_FTR_SAO) | 408 | CPU_FTR_DSCR | CPU_FTR_SAO) |
419 | #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 409 | #define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
420 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ | 410 | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \ |
421 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ | 411 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \ |
422 | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \ | 412 | CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | \ |
423 | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ | 413 | CPU_FTR_CELL_TB_BUG | CPU_FTR_CP_USE_DCBTZ | \ |
424 | CPU_FTR_UNALIGNED_LD_STD) | 414 | CPU_FTR_UNALIGNED_LD_STD) |
425 | #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ | 415 | #define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \ |
426 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \ | 416 | CPU_FTR_PPCAS_ARCH_V2 | \ |
427 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ | 417 | CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \ |
428 | CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B) | 418 | CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B) |
429 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \ | 419 | #define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2) |
430 | CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2) | ||
431 | 420 | ||
432 | #ifdef __powerpc64__ | 421 | #ifdef __powerpc64__ |
433 | #define CPU_FTRS_POSSIBLE \ | 422 | #define CPU_FTRS_POSSIBLE \ |
diff --git a/arch/powerpc/include/asm/feature-fixups.h b/arch/powerpc/include/asm/feature-fixups.h index a1029967620b..e4094a5cb05b 100644 --- a/arch/powerpc/include/asm/feature-fixups.h +++ b/arch/powerpc/include/asm/feature-fixups.h | |||
@@ -81,6 +81,36 @@ label##5: \ | |||
81 | #define ALT_FTR_SECTION_END_IFCLR(msk) \ | 81 | #define ALT_FTR_SECTION_END_IFCLR(msk) \ |
82 | ALT_FTR_SECTION_END_NESTED_IFCLR(msk, 97) | 82 | ALT_FTR_SECTION_END_NESTED_IFCLR(msk, 97) |
83 | 83 | ||
84 | /* MMU feature dependent sections */ | ||
85 | #define BEGIN_MMU_FTR_SECTION_NESTED(label) START_FTR_SECTION(label) | ||
86 | #define BEGIN_MMU_FTR_SECTION START_FTR_SECTION(97) | ||
87 | |||
88 | #define END_MMU_FTR_SECTION_NESTED(msk, val, label) \ | ||
89 | FTR_SECTION_ELSE_NESTED(label) \ | ||
90 | MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup) | ||
91 | |||
92 | #define END_MMU_FTR_SECTION(msk, val) \ | ||
93 | END_MMU_FTR_SECTION_NESTED(msk, val, 97) | ||
94 | |||
95 | #define END_MMU_FTR_SECTION_IFSET(msk) END_MMU_FTR_SECTION((msk), (msk)) | ||
96 | #define END_MMU_FTR_SECTION_IFCLR(msk) END_MMU_FTR_SECTION((msk), 0) | ||
97 | |||
98 | /* MMU feature sections with alternatives, use BEGIN_FTR_SECTION to start */ | ||
99 | #define MMU_FTR_SECTION_ELSE_NESTED(label) FTR_SECTION_ELSE_NESTED(label) | ||
100 | #define MMU_FTR_SECTION_ELSE MMU_FTR_SECTION_ELSE_NESTED(97) | ||
101 | #define ALT_MMU_FTR_SECTION_END_NESTED(msk, val, label) \ | ||
102 | MAKE_FTR_SECTION_ENTRY(msk, val, label, __mmu_ftr_fixup) | ||
103 | #define ALT_MMU_FTR_SECTION_END_NESTED_IFSET(msk, label) \ | ||
104 | ALT_MMU_FTR_SECTION_END_NESTED(msk, msk, label) | ||
105 | #define ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(msk, label) \ | ||
106 | ALT_MMU_FTR_SECTION_END_NESTED(msk, 0, label) | ||
107 | #define ALT_MMU_FTR_SECTION_END(msk, val) \ | ||
108 | ALT_MMU_FTR_SECTION_END_NESTED(msk, val, 97) | ||
109 | #define ALT_MMU_FTR_SECTION_END_IFSET(msk) \ | ||
110 | ALT_MMU_FTR_SECTION_END_NESTED_IFSET(msk, 97) | ||
111 | #define ALT_MMU_FTR_SECTION_END_IFCLR(msk) \ | ||
112 | ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(msk, 97) | ||
113 | |||
84 | /* Firmware feature dependent sections */ | 114 | /* Firmware feature dependent sections */ |
85 | #define BEGIN_FW_FTR_SECTION_NESTED(label) START_FTR_SECTION(label) | 115 | #define BEGIN_FW_FTR_SECTION_NESTED(label) START_FTR_SECTION(label) |
86 | #define BEGIN_FW_FTR_SECTION START_FTR_SECTION(97) | 116 | #define BEGIN_FW_FTR_SECTION START_FTR_SECTION(97) |
diff --git a/arch/powerpc/include/asm/mmu.h b/arch/powerpc/include/asm/mmu.h index 4c0e1b4f975c..dc8c0aef5e6c 100644 --- a/arch/powerpc/include/asm/mmu.h +++ b/arch/powerpc/include/asm/mmu.h | |||
@@ -2,6 +2,47 @@ | |||
2 | #define _ASM_POWERPC_MMU_H_ | 2 | #define _ASM_POWERPC_MMU_H_ |
3 | #ifdef __KERNEL__ | 3 | #ifdef __KERNEL__ |
4 | 4 | ||
5 | #include <asm/asm-compat.h> | ||
6 | #include <asm/feature-fixups.h> | ||
7 | |||
8 | /* | ||
9 | * MMU features bit definitions | ||
10 | */ | ||
11 | |||
12 | /* | ||
13 | * First half is MMU families | ||
14 | */ | ||
15 | #define MMU_FTR_HPTE_TABLE ASM_CONST(0x00000001) | ||
16 | #define MMU_FTR_TYPE_8xx ASM_CONST(0x00000002) | ||
17 | #define MMU_FTR_TYPE_40x ASM_CONST(0x00000004) | ||
18 | #define MMU_FTR_TYPE_44x ASM_CONST(0x00000008) | ||
19 | #define MMU_FTR_TYPE_FSL_E ASM_CONST(0x00000010) | ||
20 | |||
21 | /* | ||
22 | * This is individual features | ||
23 | */ | ||
24 | |||
25 | /* Enable use of high BAT registers */ | ||
26 | #define MMU_FTR_USE_HIGH_BATS ASM_CONST(0x00010000) | ||
27 | |||
28 | /* Enable >32-bit physical addresses on 32-bit processor, only used | ||
29 | * by CONFIG_6xx currently as BookE supports that from day 1 | ||
30 | */ | ||
31 | #define MMU_FTR_BIG_PHYS ASM_CONST(0x00020000) | ||
32 | |||
33 | #ifndef __ASSEMBLY__ | ||
34 | #include <asm/cputable.h> | ||
35 | |||
36 | static inline int mmu_has_feature(unsigned long feature) | ||
37 | { | ||
38 | return (cur_cpu_spec->mmu_features & feature); | ||
39 | } | ||
40 | |||
41 | extern unsigned int __start___mmu_ftr_fixup, __stop___mmu_ftr_fixup; | ||
42 | |||
43 | #endif /* !__ASSEMBLY__ */ | ||
44 | |||
45 | |||
5 | #ifdef CONFIG_PPC64 | 46 | #ifdef CONFIG_PPC64 |
6 | /* 64-bit classic hash table MMU */ | 47 | /* 64-bit classic hash table MMU */ |
7 | # include <asm/mmu-hash64.h> | 48 | # include <asm/mmu-hash64.h> |
diff --git a/arch/powerpc/kernel/cputable.c b/arch/powerpc/kernel/cputable.c index 921a2298d8e3..923f87aff20a 100644 --- a/arch/powerpc/kernel/cputable.c +++ b/arch/powerpc/kernel/cputable.c | |||
@@ -19,6 +19,7 @@ | |||
19 | #include <asm/oprofile_impl.h> | 19 | #include <asm/oprofile_impl.h> |
20 | #include <asm/cputable.h> | 20 | #include <asm/cputable.h> |
21 | #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */ | 21 | #include <asm/prom.h> /* for PTRRELOC on ARCH=ppc */ |
22 | #include <asm/mmu.h> | ||
22 | 23 | ||
23 | struct cpu_spec* cur_cpu_spec = NULL; | 24 | struct cpu_spec* cur_cpu_spec = NULL; |
24 | EXPORT_SYMBOL(cur_cpu_spec); | 25 | EXPORT_SYMBOL(cur_cpu_spec); |
@@ -94,6 +95,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
94 | .cpu_name = "POWER3 (630)", | 95 | .cpu_name = "POWER3 (630)", |
95 | .cpu_features = CPU_FTRS_POWER3, | 96 | .cpu_features = CPU_FTRS_POWER3, |
96 | .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE, | 97 | .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE, |
98 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
97 | .icache_bsize = 128, | 99 | .icache_bsize = 128, |
98 | .dcache_bsize = 128, | 100 | .dcache_bsize = 128, |
99 | .num_pmcs = 8, | 101 | .num_pmcs = 8, |
@@ -109,6 +111,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
109 | .cpu_name = "POWER3 (630+)", | 111 | .cpu_name = "POWER3 (630+)", |
110 | .cpu_features = CPU_FTRS_POWER3, | 112 | .cpu_features = CPU_FTRS_POWER3, |
111 | .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE, | 113 | .cpu_user_features = COMMON_USER_PPC64|PPC_FEATURE_PPC_LE, |
114 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
112 | .icache_bsize = 128, | 115 | .icache_bsize = 128, |
113 | .dcache_bsize = 128, | 116 | .dcache_bsize = 128, |
114 | .num_pmcs = 8, | 117 | .num_pmcs = 8, |
@@ -124,6 +127,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
124 | .cpu_name = "RS64-II (northstar)", | 127 | .cpu_name = "RS64-II (northstar)", |
125 | .cpu_features = CPU_FTRS_RS64, | 128 | .cpu_features = CPU_FTRS_RS64, |
126 | .cpu_user_features = COMMON_USER_PPC64, | 129 | .cpu_user_features = COMMON_USER_PPC64, |
130 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
127 | .icache_bsize = 128, | 131 | .icache_bsize = 128, |
128 | .dcache_bsize = 128, | 132 | .dcache_bsize = 128, |
129 | .num_pmcs = 8, | 133 | .num_pmcs = 8, |
@@ -139,6 +143,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
139 | .cpu_name = "RS64-III (pulsar)", | 143 | .cpu_name = "RS64-III (pulsar)", |
140 | .cpu_features = CPU_FTRS_RS64, | 144 | .cpu_features = CPU_FTRS_RS64, |
141 | .cpu_user_features = COMMON_USER_PPC64, | 145 | .cpu_user_features = COMMON_USER_PPC64, |
146 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
142 | .icache_bsize = 128, | 147 | .icache_bsize = 128, |
143 | .dcache_bsize = 128, | 148 | .dcache_bsize = 128, |
144 | .num_pmcs = 8, | 149 | .num_pmcs = 8, |
@@ -154,6 +159,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
154 | .cpu_name = "RS64-III (icestar)", | 159 | .cpu_name = "RS64-III (icestar)", |
155 | .cpu_features = CPU_FTRS_RS64, | 160 | .cpu_features = CPU_FTRS_RS64, |
156 | .cpu_user_features = COMMON_USER_PPC64, | 161 | .cpu_user_features = COMMON_USER_PPC64, |
162 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
157 | .icache_bsize = 128, | 163 | .icache_bsize = 128, |
158 | .dcache_bsize = 128, | 164 | .dcache_bsize = 128, |
159 | .num_pmcs = 8, | 165 | .num_pmcs = 8, |
@@ -169,6 +175,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
169 | .cpu_name = "RS64-IV (sstar)", | 175 | .cpu_name = "RS64-IV (sstar)", |
170 | .cpu_features = CPU_FTRS_RS64, | 176 | .cpu_features = CPU_FTRS_RS64, |
171 | .cpu_user_features = COMMON_USER_PPC64, | 177 | .cpu_user_features = COMMON_USER_PPC64, |
178 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
172 | .icache_bsize = 128, | 179 | .icache_bsize = 128, |
173 | .dcache_bsize = 128, | 180 | .dcache_bsize = 128, |
174 | .num_pmcs = 8, | 181 | .num_pmcs = 8, |
@@ -184,6 +191,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
184 | .cpu_name = "POWER4 (gp)", | 191 | .cpu_name = "POWER4 (gp)", |
185 | .cpu_features = CPU_FTRS_POWER4, | 192 | .cpu_features = CPU_FTRS_POWER4, |
186 | .cpu_user_features = COMMON_USER_POWER4, | 193 | .cpu_user_features = COMMON_USER_POWER4, |
194 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
187 | .icache_bsize = 128, | 195 | .icache_bsize = 128, |
188 | .dcache_bsize = 128, | 196 | .dcache_bsize = 128, |
189 | .num_pmcs = 8, | 197 | .num_pmcs = 8, |
@@ -199,6 +207,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
199 | .cpu_name = "POWER4+ (gq)", | 207 | .cpu_name = "POWER4+ (gq)", |
200 | .cpu_features = CPU_FTRS_POWER4, | 208 | .cpu_features = CPU_FTRS_POWER4, |
201 | .cpu_user_features = COMMON_USER_POWER4, | 209 | .cpu_user_features = COMMON_USER_POWER4, |
210 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
202 | .icache_bsize = 128, | 211 | .icache_bsize = 128, |
203 | .dcache_bsize = 128, | 212 | .dcache_bsize = 128, |
204 | .num_pmcs = 8, | 213 | .num_pmcs = 8, |
@@ -215,6 +224,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
215 | .cpu_features = CPU_FTRS_PPC970, | 224 | .cpu_features = CPU_FTRS_PPC970, |
216 | .cpu_user_features = COMMON_USER_POWER4 | | 225 | .cpu_user_features = COMMON_USER_POWER4 | |
217 | PPC_FEATURE_HAS_ALTIVEC_COMP, | 226 | PPC_FEATURE_HAS_ALTIVEC_COMP, |
227 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
218 | .icache_bsize = 128, | 228 | .icache_bsize = 128, |
219 | .dcache_bsize = 128, | 229 | .dcache_bsize = 128, |
220 | .num_pmcs = 8, | 230 | .num_pmcs = 8, |
@@ -233,6 +243,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
233 | .cpu_features = CPU_FTRS_PPC970, | 243 | .cpu_features = CPU_FTRS_PPC970, |
234 | .cpu_user_features = COMMON_USER_POWER4 | | 244 | .cpu_user_features = COMMON_USER_POWER4 | |
235 | PPC_FEATURE_HAS_ALTIVEC_COMP, | 245 | PPC_FEATURE_HAS_ALTIVEC_COMP, |
246 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
236 | .icache_bsize = 128, | 247 | .icache_bsize = 128, |
237 | .dcache_bsize = 128, | 248 | .dcache_bsize = 128, |
238 | .num_pmcs = 8, | 249 | .num_pmcs = 8, |
@@ -251,6 +262,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
251 | .cpu_features = CPU_FTRS_PPC970, | 262 | .cpu_features = CPU_FTRS_PPC970, |
252 | .cpu_user_features = COMMON_USER_POWER4 | | 263 | .cpu_user_features = COMMON_USER_POWER4 | |
253 | PPC_FEATURE_HAS_ALTIVEC_COMP, | 264 | PPC_FEATURE_HAS_ALTIVEC_COMP, |
265 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
254 | .icache_bsize = 128, | 266 | .icache_bsize = 128, |
255 | .dcache_bsize = 128, | 267 | .dcache_bsize = 128, |
256 | .num_pmcs = 8, | 268 | .num_pmcs = 8, |
@@ -269,6 +281,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
269 | .cpu_features = CPU_FTRS_PPC970, | 281 | .cpu_features = CPU_FTRS_PPC970, |
270 | .cpu_user_features = COMMON_USER_POWER4 | | 282 | .cpu_user_features = COMMON_USER_POWER4 | |
271 | PPC_FEATURE_HAS_ALTIVEC_COMP, | 283 | PPC_FEATURE_HAS_ALTIVEC_COMP, |
284 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
272 | .icache_bsize = 128, | 285 | .icache_bsize = 128, |
273 | .dcache_bsize = 128, | 286 | .dcache_bsize = 128, |
274 | .num_pmcs = 8, | 287 | .num_pmcs = 8, |
@@ -287,6 +300,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
287 | .cpu_features = CPU_FTRS_PPC970, | 300 | .cpu_features = CPU_FTRS_PPC970, |
288 | .cpu_user_features = COMMON_USER_POWER4 | | 301 | .cpu_user_features = COMMON_USER_POWER4 | |
289 | PPC_FEATURE_HAS_ALTIVEC_COMP, | 302 | PPC_FEATURE_HAS_ALTIVEC_COMP, |
303 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
290 | .icache_bsize = 128, | 304 | .icache_bsize = 128, |
291 | .dcache_bsize = 128, | 305 | .dcache_bsize = 128, |
292 | .num_pmcs = 8, | 306 | .num_pmcs = 8, |
@@ -303,6 +317,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
303 | .cpu_name = "POWER5 (gr)", | 317 | .cpu_name = "POWER5 (gr)", |
304 | .cpu_features = CPU_FTRS_POWER5, | 318 | .cpu_features = CPU_FTRS_POWER5, |
305 | .cpu_user_features = COMMON_USER_POWER5, | 319 | .cpu_user_features = COMMON_USER_POWER5, |
320 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
306 | .icache_bsize = 128, | 321 | .icache_bsize = 128, |
307 | .dcache_bsize = 128, | 322 | .dcache_bsize = 128, |
308 | .num_pmcs = 6, | 323 | .num_pmcs = 6, |
@@ -323,6 +338,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
323 | .cpu_name = "POWER5+ (gs)", | 338 | .cpu_name = "POWER5+ (gs)", |
324 | .cpu_features = CPU_FTRS_POWER5, | 339 | .cpu_features = CPU_FTRS_POWER5, |
325 | .cpu_user_features = COMMON_USER_POWER5_PLUS, | 340 | .cpu_user_features = COMMON_USER_POWER5_PLUS, |
341 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
326 | .icache_bsize = 128, | 342 | .icache_bsize = 128, |
327 | .dcache_bsize = 128, | 343 | .dcache_bsize = 128, |
328 | .num_pmcs = 6, | 344 | .num_pmcs = 6, |
@@ -339,6 +355,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
339 | .cpu_name = "POWER5+ (gs)", | 355 | .cpu_name = "POWER5+ (gs)", |
340 | .cpu_features = CPU_FTRS_POWER5, | 356 | .cpu_features = CPU_FTRS_POWER5, |
341 | .cpu_user_features = COMMON_USER_POWER5_PLUS, | 357 | .cpu_user_features = COMMON_USER_POWER5_PLUS, |
358 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
342 | .icache_bsize = 128, | 359 | .icache_bsize = 128, |
343 | .dcache_bsize = 128, | 360 | .dcache_bsize = 128, |
344 | .num_pmcs = 6, | 361 | .num_pmcs = 6, |
@@ -356,6 +373,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
356 | .cpu_name = "POWER5+", | 373 | .cpu_name = "POWER5+", |
357 | .cpu_features = CPU_FTRS_POWER5, | 374 | .cpu_features = CPU_FTRS_POWER5, |
358 | .cpu_user_features = COMMON_USER_POWER5_PLUS, | 375 | .cpu_user_features = COMMON_USER_POWER5_PLUS, |
376 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
359 | .icache_bsize = 128, | 377 | .icache_bsize = 128, |
360 | .dcache_bsize = 128, | 378 | .dcache_bsize = 128, |
361 | .machine_check = machine_check_generic, | 379 | .machine_check = machine_check_generic, |
@@ -369,6 +387,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
369 | .cpu_features = CPU_FTRS_POWER6, | 387 | .cpu_features = CPU_FTRS_POWER6, |
370 | .cpu_user_features = COMMON_USER_POWER6 | | 388 | .cpu_user_features = COMMON_USER_POWER6 | |
371 | PPC_FEATURE_POWER6_EXT, | 389 | PPC_FEATURE_POWER6_EXT, |
390 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
372 | .icache_bsize = 128, | 391 | .icache_bsize = 128, |
373 | .dcache_bsize = 128, | 392 | .dcache_bsize = 128, |
374 | .num_pmcs = 6, | 393 | .num_pmcs = 6, |
@@ -388,6 +407,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
388 | .cpu_name = "POWER6 (architected)", | 407 | .cpu_name = "POWER6 (architected)", |
389 | .cpu_features = CPU_FTRS_POWER6, | 408 | .cpu_features = CPU_FTRS_POWER6, |
390 | .cpu_user_features = COMMON_USER_POWER6, | 409 | .cpu_user_features = COMMON_USER_POWER6, |
410 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
391 | .icache_bsize = 128, | 411 | .icache_bsize = 128, |
392 | .dcache_bsize = 128, | 412 | .dcache_bsize = 128, |
393 | .machine_check = machine_check_generic, | 413 | .machine_check = machine_check_generic, |
@@ -400,6 +420,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
400 | .cpu_name = "POWER7 (architected)", | 420 | .cpu_name = "POWER7 (architected)", |
401 | .cpu_features = CPU_FTRS_POWER7, | 421 | .cpu_features = CPU_FTRS_POWER7, |
402 | .cpu_user_features = COMMON_USER_POWER7, | 422 | .cpu_user_features = COMMON_USER_POWER7, |
423 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
403 | .icache_bsize = 128, | 424 | .icache_bsize = 128, |
404 | .dcache_bsize = 128, | 425 | .dcache_bsize = 128, |
405 | .machine_check = machine_check_generic, | 426 | .machine_check = machine_check_generic, |
@@ -412,6 +433,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
412 | .cpu_name = "POWER7 (raw)", | 433 | .cpu_name = "POWER7 (raw)", |
413 | .cpu_features = CPU_FTRS_POWER7, | 434 | .cpu_features = CPU_FTRS_POWER7, |
414 | .cpu_user_features = COMMON_USER_POWER7, | 435 | .cpu_user_features = COMMON_USER_POWER7, |
436 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
415 | .icache_bsize = 128, | 437 | .icache_bsize = 128, |
416 | .dcache_bsize = 128, | 438 | .dcache_bsize = 128, |
417 | .num_pmcs = 6, | 439 | .num_pmcs = 6, |
@@ -434,6 +456,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
434 | .cpu_user_features = COMMON_USER_PPC64 | | 456 | .cpu_user_features = COMMON_USER_PPC64 | |
435 | PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP | | 457 | PPC_FEATURE_CELL | PPC_FEATURE_HAS_ALTIVEC_COMP | |
436 | PPC_FEATURE_SMT, | 458 | PPC_FEATURE_SMT, |
459 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
437 | .icache_bsize = 128, | 460 | .icache_bsize = 128, |
438 | .dcache_bsize = 128, | 461 | .dcache_bsize = 128, |
439 | .num_pmcs = 4, | 462 | .num_pmcs = 4, |
@@ -449,6 +472,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
449 | .cpu_name = "PA6T", | 472 | .cpu_name = "PA6T", |
450 | .cpu_features = CPU_FTRS_PA6T, | 473 | .cpu_features = CPU_FTRS_PA6T, |
451 | .cpu_user_features = COMMON_USER_PA6T, | 474 | .cpu_user_features = COMMON_USER_PA6T, |
475 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
452 | .icache_bsize = 64, | 476 | .icache_bsize = 64, |
453 | .dcache_bsize = 64, | 477 | .dcache_bsize = 64, |
454 | .num_pmcs = 6, | 478 | .num_pmcs = 6, |
@@ -466,6 +490,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
466 | .cpu_name = "POWER4 (compatible)", | 490 | .cpu_name = "POWER4 (compatible)", |
467 | .cpu_features = CPU_FTRS_COMPATIBLE, | 491 | .cpu_features = CPU_FTRS_COMPATIBLE, |
468 | .cpu_user_features = COMMON_USER_PPC64, | 492 | .cpu_user_features = COMMON_USER_PPC64, |
493 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
469 | .icache_bsize = 128, | 494 | .icache_bsize = 128, |
470 | .dcache_bsize = 128, | 495 | .dcache_bsize = 128, |
471 | .num_pmcs = 6, | 496 | .num_pmcs = 6, |
@@ -483,6 +508,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
483 | .cpu_features = CPU_FTRS_PPC601, | 508 | .cpu_features = CPU_FTRS_PPC601, |
484 | .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR | | 509 | .cpu_user_features = COMMON_USER | PPC_FEATURE_601_INSTR | |
485 | PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB, | 510 | PPC_FEATURE_UNIFIED_CACHE | PPC_FEATURE_NO_TB, |
511 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
486 | .icache_bsize = 32, | 512 | .icache_bsize = 32, |
487 | .dcache_bsize = 32, | 513 | .dcache_bsize = 32, |
488 | .machine_check = machine_check_generic, | 514 | .machine_check = machine_check_generic, |
@@ -494,6 +520,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
494 | .cpu_name = "603", | 520 | .cpu_name = "603", |
495 | .cpu_features = CPU_FTRS_603, | 521 | .cpu_features = CPU_FTRS_603, |
496 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 522 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
523 | .mmu_features = 0, | ||
497 | .icache_bsize = 32, | 524 | .icache_bsize = 32, |
498 | .dcache_bsize = 32, | 525 | .dcache_bsize = 32, |
499 | .cpu_setup = __setup_cpu_603, | 526 | .cpu_setup = __setup_cpu_603, |
@@ -506,6 +533,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
506 | .cpu_name = "603e", | 533 | .cpu_name = "603e", |
507 | .cpu_features = CPU_FTRS_603, | 534 | .cpu_features = CPU_FTRS_603, |
508 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 535 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
536 | .mmu_features = 0, | ||
509 | .icache_bsize = 32, | 537 | .icache_bsize = 32, |
510 | .dcache_bsize = 32, | 538 | .dcache_bsize = 32, |
511 | .cpu_setup = __setup_cpu_603, | 539 | .cpu_setup = __setup_cpu_603, |
@@ -518,6 +546,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
518 | .cpu_name = "603ev", | 546 | .cpu_name = "603ev", |
519 | .cpu_features = CPU_FTRS_603, | 547 | .cpu_features = CPU_FTRS_603, |
520 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 548 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
549 | .mmu_features = 0, | ||
521 | .icache_bsize = 32, | 550 | .icache_bsize = 32, |
522 | .dcache_bsize = 32, | 551 | .dcache_bsize = 32, |
523 | .cpu_setup = __setup_cpu_603, | 552 | .cpu_setup = __setup_cpu_603, |
@@ -530,6 +559,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
530 | .cpu_name = "604", | 559 | .cpu_name = "604", |
531 | .cpu_features = CPU_FTRS_604, | 560 | .cpu_features = CPU_FTRS_604, |
532 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 561 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
562 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
533 | .icache_bsize = 32, | 563 | .icache_bsize = 32, |
534 | .dcache_bsize = 32, | 564 | .dcache_bsize = 32, |
535 | .num_pmcs = 2, | 565 | .num_pmcs = 2, |
@@ -543,6 +573,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
543 | .cpu_name = "604e", | 573 | .cpu_name = "604e", |
544 | .cpu_features = CPU_FTRS_604, | 574 | .cpu_features = CPU_FTRS_604, |
545 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 575 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
576 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
546 | .icache_bsize = 32, | 577 | .icache_bsize = 32, |
547 | .dcache_bsize = 32, | 578 | .dcache_bsize = 32, |
548 | .num_pmcs = 4, | 579 | .num_pmcs = 4, |
@@ -556,6 +587,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
556 | .cpu_name = "604r", | 587 | .cpu_name = "604r", |
557 | .cpu_features = CPU_FTRS_604, | 588 | .cpu_features = CPU_FTRS_604, |
558 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 589 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
590 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
559 | .icache_bsize = 32, | 591 | .icache_bsize = 32, |
560 | .dcache_bsize = 32, | 592 | .dcache_bsize = 32, |
561 | .num_pmcs = 4, | 593 | .num_pmcs = 4, |
@@ -569,6 +601,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
569 | .cpu_name = "604ev", | 601 | .cpu_name = "604ev", |
570 | .cpu_features = CPU_FTRS_604, | 602 | .cpu_features = CPU_FTRS_604, |
571 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 603 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
604 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
572 | .icache_bsize = 32, | 605 | .icache_bsize = 32, |
573 | .dcache_bsize = 32, | 606 | .dcache_bsize = 32, |
574 | .num_pmcs = 4, | 607 | .num_pmcs = 4, |
@@ -582,6 +615,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
582 | .cpu_name = "740/750", | 615 | .cpu_name = "740/750", |
583 | .cpu_features = CPU_FTRS_740_NOTAU, | 616 | .cpu_features = CPU_FTRS_740_NOTAU, |
584 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 617 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
618 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
585 | .icache_bsize = 32, | 619 | .icache_bsize = 32, |
586 | .dcache_bsize = 32, | 620 | .dcache_bsize = 32, |
587 | .num_pmcs = 4, | 621 | .num_pmcs = 4, |
@@ -595,6 +629,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
595 | .cpu_name = "750CX", | 629 | .cpu_name = "750CX", |
596 | .cpu_features = CPU_FTRS_750, | 630 | .cpu_features = CPU_FTRS_750, |
597 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 631 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
632 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
598 | .icache_bsize = 32, | 633 | .icache_bsize = 32, |
599 | .dcache_bsize = 32, | 634 | .dcache_bsize = 32, |
600 | .num_pmcs = 4, | 635 | .num_pmcs = 4, |
@@ -608,6 +643,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
608 | .cpu_name = "750CX", | 643 | .cpu_name = "750CX", |
609 | .cpu_features = CPU_FTRS_750, | 644 | .cpu_features = CPU_FTRS_750, |
610 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 645 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
646 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
611 | .icache_bsize = 32, | 647 | .icache_bsize = 32, |
612 | .dcache_bsize = 32, | 648 | .dcache_bsize = 32, |
613 | .num_pmcs = 4, | 649 | .num_pmcs = 4, |
@@ -622,6 +658,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
622 | .cpu_name = "750CXe", | 658 | .cpu_name = "750CXe", |
623 | .cpu_features = CPU_FTRS_750, | 659 | .cpu_features = CPU_FTRS_750, |
624 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 660 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
661 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
625 | .icache_bsize = 32, | 662 | .icache_bsize = 32, |
626 | .dcache_bsize = 32, | 663 | .dcache_bsize = 32, |
627 | .num_pmcs = 4, | 664 | .num_pmcs = 4, |
@@ -636,6 +673,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
636 | .cpu_name = "750CXe", | 673 | .cpu_name = "750CXe", |
637 | .cpu_features = CPU_FTRS_750, | 674 | .cpu_features = CPU_FTRS_750, |
638 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 675 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
676 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
639 | .icache_bsize = 32, | 677 | .icache_bsize = 32, |
640 | .dcache_bsize = 32, | 678 | .dcache_bsize = 32, |
641 | .num_pmcs = 4, | 679 | .num_pmcs = 4, |
@@ -650,6 +688,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
650 | .cpu_name = "750CL", | 688 | .cpu_name = "750CL", |
651 | .cpu_features = CPU_FTRS_750CL, | 689 | .cpu_features = CPU_FTRS_750CL, |
652 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 690 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
691 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
653 | .icache_bsize = 32, | 692 | .icache_bsize = 32, |
654 | .dcache_bsize = 32, | 693 | .dcache_bsize = 32, |
655 | .num_pmcs = 4, | 694 | .num_pmcs = 4, |
@@ -664,6 +703,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
664 | .cpu_name = "745/755", | 703 | .cpu_name = "745/755", |
665 | .cpu_features = CPU_FTRS_750, | 704 | .cpu_features = CPU_FTRS_750, |
666 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 705 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
706 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
667 | .icache_bsize = 32, | 707 | .icache_bsize = 32, |
668 | .dcache_bsize = 32, | 708 | .dcache_bsize = 32, |
669 | .num_pmcs = 4, | 709 | .num_pmcs = 4, |
@@ -678,6 +718,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
678 | .cpu_name = "750FX", | 718 | .cpu_name = "750FX", |
679 | .cpu_features = CPU_FTRS_750FX1, | 719 | .cpu_features = CPU_FTRS_750FX1, |
680 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 720 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
721 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
681 | .icache_bsize = 32, | 722 | .icache_bsize = 32, |
682 | .dcache_bsize = 32, | 723 | .dcache_bsize = 32, |
683 | .num_pmcs = 4, | 724 | .num_pmcs = 4, |
@@ -692,6 +733,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
692 | .cpu_name = "750FX", | 733 | .cpu_name = "750FX", |
693 | .cpu_features = CPU_FTRS_750FX2, | 734 | .cpu_features = CPU_FTRS_750FX2, |
694 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 735 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
736 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
695 | .icache_bsize = 32, | 737 | .icache_bsize = 32, |
696 | .dcache_bsize = 32, | 738 | .dcache_bsize = 32, |
697 | .num_pmcs = 4, | 739 | .num_pmcs = 4, |
@@ -706,6 +748,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
706 | .cpu_name = "750FX", | 748 | .cpu_name = "750FX", |
707 | .cpu_features = CPU_FTRS_750FX, | 749 | .cpu_features = CPU_FTRS_750FX, |
708 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 750 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
751 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
709 | .icache_bsize = 32, | 752 | .icache_bsize = 32, |
710 | .dcache_bsize = 32, | 753 | .dcache_bsize = 32, |
711 | .num_pmcs = 4, | 754 | .num_pmcs = 4, |
@@ -720,6 +763,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
720 | .cpu_name = "750GX", | 763 | .cpu_name = "750GX", |
721 | .cpu_features = CPU_FTRS_750GX, | 764 | .cpu_features = CPU_FTRS_750GX, |
722 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 765 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
766 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
723 | .icache_bsize = 32, | 767 | .icache_bsize = 32, |
724 | .dcache_bsize = 32, | 768 | .dcache_bsize = 32, |
725 | .num_pmcs = 4, | 769 | .num_pmcs = 4, |
@@ -734,6 +778,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
734 | .cpu_name = "740/750", | 778 | .cpu_name = "740/750", |
735 | .cpu_features = CPU_FTRS_740, | 779 | .cpu_features = CPU_FTRS_740, |
736 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, | 780 | .cpu_user_features = COMMON_USER | PPC_FEATURE_PPC_LE, |
781 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
737 | .icache_bsize = 32, | 782 | .icache_bsize = 32, |
738 | .dcache_bsize = 32, | 783 | .dcache_bsize = 32, |
739 | .num_pmcs = 4, | 784 | .num_pmcs = 4, |
@@ -749,6 +794,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
749 | .cpu_features = CPU_FTRS_7400_NOTAU, | 794 | .cpu_features = CPU_FTRS_7400_NOTAU, |
750 | .cpu_user_features = COMMON_USER | | 795 | .cpu_user_features = COMMON_USER | |
751 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 796 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
797 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
752 | .icache_bsize = 32, | 798 | .icache_bsize = 32, |
753 | .dcache_bsize = 32, | 799 | .dcache_bsize = 32, |
754 | .num_pmcs = 4, | 800 | .num_pmcs = 4, |
@@ -764,6 +810,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
764 | .cpu_features = CPU_FTRS_7400, | 810 | .cpu_features = CPU_FTRS_7400, |
765 | .cpu_user_features = COMMON_USER | | 811 | .cpu_user_features = COMMON_USER | |
766 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 812 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
813 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
767 | .icache_bsize = 32, | 814 | .icache_bsize = 32, |
768 | .dcache_bsize = 32, | 815 | .dcache_bsize = 32, |
769 | .num_pmcs = 4, | 816 | .num_pmcs = 4, |
@@ -779,6 +826,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
779 | .cpu_features = CPU_FTRS_7400, | 826 | .cpu_features = CPU_FTRS_7400, |
780 | .cpu_user_features = COMMON_USER | | 827 | .cpu_user_features = COMMON_USER | |
781 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 828 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
829 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
782 | .icache_bsize = 32, | 830 | .icache_bsize = 32, |
783 | .dcache_bsize = 32, | 831 | .dcache_bsize = 32, |
784 | .num_pmcs = 4, | 832 | .num_pmcs = 4, |
@@ -794,6 +842,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
794 | .cpu_features = CPU_FTRS_7450_20, | 842 | .cpu_features = CPU_FTRS_7450_20, |
795 | .cpu_user_features = COMMON_USER | | 843 | .cpu_user_features = COMMON_USER | |
796 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 844 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
845 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
797 | .icache_bsize = 32, | 846 | .icache_bsize = 32, |
798 | .dcache_bsize = 32, | 847 | .dcache_bsize = 32, |
799 | .num_pmcs = 6, | 848 | .num_pmcs = 6, |
@@ -811,6 +860,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
811 | .cpu_features = CPU_FTRS_7450_21, | 860 | .cpu_features = CPU_FTRS_7450_21, |
812 | .cpu_user_features = COMMON_USER | | 861 | .cpu_user_features = COMMON_USER | |
813 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 862 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
863 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
814 | .icache_bsize = 32, | 864 | .icache_bsize = 32, |
815 | .dcache_bsize = 32, | 865 | .dcache_bsize = 32, |
816 | .num_pmcs = 6, | 866 | .num_pmcs = 6, |
@@ -828,6 +878,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
828 | .cpu_features = CPU_FTRS_7450_23, | 878 | .cpu_features = CPU_FTRS_7450_23, |
829 | .cpu_user_features = COMMON_USER | | 879 | .cpu_user_features = COMMON_USER | |
830 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 880 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
881 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
831 | .icache_bsize = 32, | 882 | .icache_bsize = 32, |
832 | .dcache_bsize = 32, | 883 | .dcache_bsize = 32, |
833 | .num_pmcs = 6, | 884 | .num_pmcs = 6, |
@@ -845,6 +896,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
845 | .cpu_features = CPU_FTRS_7455_1, | 896 | .cpu_features = CPU_FTRS_7455_1, |
846 | .cpu_user_features = COMMON_USER | | 897 | .cpu_user_features = COMMON_USER | |
847 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 898 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
899 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
848 | .icache_bsize = 32, | 900 | .icache_bsize = 32, |
849 | .dcache_bsize = 32, | 901 | .dcache_bsize = 32, |
850 | .num_pmcs = 6, | 902 | .num_pmcs = 6, |
@@ -862,6 +914,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
862 | .cpu_features = CPU_FTRS_7455_20, | 914 | .cpu_features = CPU_FTRS_7455_20, |
863 | .cpu_user_features = COMMON_USER | | 915 | .cpu_user_features = COMMON_USER | |
864 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 916 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
917 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
865 | .icache_bsize = 32, | 918 | .icache_bsize = 32, |
866 | .dcache_bsize = 32, | 919 | .dcache_bsize = 32, |
867 | .num_pmcs = 6, | 920 | .num_pmcs = 6, |
@@ -879,6 +932,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
879 | .cpu_features = CPU_FTRS_7455, | 932 | .cpu_features = CPU_FTRS_7455, |
880 | .cpu_user_features = COMMON_USER | | 933 | .cpu_user_features = COMMON_USER | |
881 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 934 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
935 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
882 | .icache_bsize = 32, | 936 | .icache_bsize = 32, |
883 | .dcache_bsize = 32, | 937 | .dcache_bsize = 32, |
884 | .num_pmcs = 6, | 938 | .num_pmcs = 6, |
@@ -896,6 +950,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
896 | .cpu_features = CPU_FTRS_7447_10, | 950 | .cpu_features = CPU_FTRS_7447_10, |
897 | .cpu_user_features = COMMON_USER | | 951 | .cpu_user_features = COMMON_USER | |
898 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 952 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
953 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
899 | .icache_bsize = 32, | 954 | .icache_bsize = 32, |
900 | .dcache_bsize = 32, | 955 | .dcache_bsize = 32, |
901 | .num_pmcs = 6, | 956 | .num_pmcs = 6, |
@@ -913,6 +968,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
913 | .cpu_features = CPU_FTRS_7447_10, | 968 | .cpu_features = CPU_FTRS_7447_10, |
914 | .cpu_user_features = COMMON_USER | | 969 | .cpu_user_features = COMMON_USER | |
915 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 970 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
971 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
916 | .icache_bsize = 32, | 972 | .icache_bsize = 32, |
917 | .dcache_bsize = 32, | 973 | .dcache_bsize = 32, |
918 | .num_pmcs = 6, | 974 | .num_pmcs = 6, |
@@ -929,6 +985,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
929 | .cpu_name = "7447/7457", | 985 | .cpu_name = "7447/7457", |
930 | .cpu_features = CPU_FTRS_7447, | 986 | .cpu_features = CPU_FTRS_7447, |
931 | .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 987 | .cpu_user_features = COMMON_USER | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
988 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
932 | .icache_bsize = 32, | 989 | .icache_bsize = 32, |
933 | .dcache_bsize = 32, | 990 | .dcache_bsize = 32, |
934 | .num_pmcs = 6, | 991 | .num_pmcs = 6, |
@@ -946,6 +1003,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
946 | .cpu_features = CPU_FTRS_7447A, | 1003 | .cpu_features = CPU_FTRS_7447A, |
947 | .cpu_user_features = COMMON_USER | | 1004 | .cpu_user_features = COMMON_USER | |
948 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 1005 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
1006 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
949 | .icache_bsize = 32, | 1007 | .icache_bsize = 32, |
950 | .dcache_bsize = 32, | 1008 | .dcache_bsize = 32, |
951 | .num_pmcs = 6, | 1009 | .num_pmcs = 6, |
@@ -963,6 +1021,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
963 | .cpu_features = CPU_FTRS_7448, | 1021 | .cpu_features = CPU_FTRS_7448, |
964 | .cpu_user_features = COMMON_USER | | 1022 | .cpu_user_features = COMMON_USER | |
965 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, | 1023 | PPC_FEATURE_HAS_ALTIVEC_COMP | PPC_FEATURE_PPC_LE, |
1024 | .mmu_features = MMU_FTR_HPTE_TABLE | MMU_FTR_USE_HIGH_BATS, | ||
966 | .icache_bsize = 32, | 1025 | .icache_bsize = 32, |
967 | .dcache_bsize = 32, | 1026 | .dcache_bsize = 32, |
968 | .num_pmcs = 6, | 1027 | .num_pmcs = 6, |
@@ -979,6 +1038,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
979 | .cpu_name = "82xx", | 1038 | .cpu_name = "82xx", |
980 | .cpu_features = CPU_FTRS_82XX, | 1039 | .cpu_features = CPU_FTRS_82XX, |
981 | .cpu_user_features = COMMON_USER, | 1040 | .cpu_user_features = COMMON_USER, |
1041 | .mmu_features = 0, | ||
982 | .icache_bsize = 32, | 1042 | .icache_bsize = 32, |
983 | .dcache_bsize = 32, | 1043 | .dcache_bsize = 32, |
984 | .cpu_setup = __setup_cpu_603, | 1044 | .cpu_setup = __setup_cpu_603, |
@@ -991,6 +1051,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
991 | .cpu_name = "G2_LE", | 1051 | .cpu_name = "G2_LE", |
992 | .cpu_features = CPU_FTRS_G2_LE, | 1052 | .cpu_features = CPU_FTRS_G2_LE, |
993 | .cpu_user_features = COMMON_USER, | 1053 | .cpu_user_features = COMMON_USER, |
1054 | .mmu_features = MMU_FTR_USE_HIGH_BATS, | ||
994 | .icache_bsize = 32, | 1055 | .icache_bsize = 32, |
995 | .dcache_bsize = 32, | 1056 | .dcache_bsize = 32, |
996 | .cpu_setup = __setup_cpu_603, | 1057 | .cpu_setup = __setup_cpu_603, |
@@ -1003,6 +1064,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1003 | .cpu_name = "e300c1", | 1064 | .cpu_name = "e300c1", |
1004 | .cpu_features = CPU_FTRS_E300, | 1065 | .cpu_features = CPU_FTRS_E300, |
1005 | .cpu_user_features = COMMON_USER, | 1066 | .cpu_user_features = COMMON_USER, |
1067 | .mmu_features = MMU_FTR_USE_HIGH_BATS, | ||
1006 | .icache_bsize = 32, | 1068 | .icache_bsize = 32, |
1007 | .dcache_bsize = 32, | 1069 | .dcache_bsize = 32, |
1008 | .cpu_setup = __setup_cpu_603, | 1070 | .cpu_setup = __setup_cpu_603, |
@@ -1015,6 +1077,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1015 | .cpu_name = "e300c2", | 1077 | .cpu_name = "e300c2", |
1016 | .cpu_features = CPU_FTRS_E300C2, | 1078 | .cpu_features = CPU_FTRS_E300C2, |
1017 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, | 1079 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, |
1080 | .mmu_features = MMU_FTR_USE_HIGH_BATS, | ||
1018 | .icache_bsize = 32, | 1081 | .icache_bsize = 32, |
1019 | .dcache_bsize = 32, | 1082 | .dcache_bsize = 32, |
1020 | .cpu_setup = __setup_cpu_603, | 1083 | .cpu_setup = __setup_cpu_603, |
@@ -1027,6 +1090,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1027 | .cpu_name = "e300c3", | 1090 | .cpu_name = "e300c3", |
1028 | .cpu_features = CPU_FTRS_E300, | 1091 | .cpu_features = CPU_FTRS_E300, |
1029 | .cpu_user_features = COMMON_USER, | 1092 | .cpu_user_features = COMMON_USER, |
1093 | .mmu_features = MMU_FTR_USE_HIGH_BATS, | ||
1030 | .icache_bsize = 32, | 1094 | .icache_bsize = 32, |
1031 | .dcache_bsize = 32, | 1095 | .dcache_bsize = 32, |
1032 | .cpu_setup = __setup_cpu_603, | 1096 | .cpu_setup = __setup_cpu_603, |
@@ -1041,6 +1105,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1041 | .cpu_name = "e300c4", | 1105 | .cpu_name = "e300c4", |
1042 | .cpu_features = CPU_FTRS_E300, | 1106 | .cpu_features = CPU_FTRS_E300, |
1043 | .cpu_user_features = COMMON_USER, | 1107 | .cpu_user_features = COMMON_USER, |
1108 | .mmu_features = MMU_FTR_USE_HIGH_BATS, | ||
1044 | .icache_bsize = 32, | 1109 | .icache_bsize = 32, |
1045 | .dcache_bsize = 32, | 1110 | .dcache_bsize = 32, |
1046 | .cpu_setup = __setup_cpu_603, | 1111 | .cpu_setup = __setup_cpu_603, |
@@ -1056,6 +1121,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1056 | .cpu_name = "(generic PPC)", | 1121 | .cpu_name = "(generic PPC)", |
1057 | .cpu_features = CPU_FTRS_CLASSIC32, | 1122 | .cpu_features = CPU_FTRS_CLASSIC32, |
1058 | .cpu_user_features = COMMON_USER, | 1123 | .cpu_user_features = COMMON_USER, |
1124 | .mmu_features = MMU_FTR_HPTE_TABLE, | ||
1059 | .icache_bsize = 32, | 1125 | .icache_bsize = 32, |
1060 | .dcache_bsize = 32, | 1126 | .dcache_bsize = 32, |
1061 | .machine_check = machine_check_generic, | 1127 | .machine_check = machine_check_generic, |
@@ -1071,6 +1137,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1071 | * if the 8xx code is there.... */ | 1137 | * if the 8xx code is there.... */ |
1072 | .cpu_features = CPU_FTRS_8XX, | 1138 | .cpu_features = CPU_FTRS_8XX, |
1073 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, | 1139 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, |
1140 | .mmu_features = MMU_FTR_TYPE_8xx, | ||
1074 | .icache_bsize = 16, | 1141 | .icache_bsize = 16, |
1075 | .dcache_bsize = 16, | 1142 | .dcache_bsize = 16, |
1076 | .platform = "ppc823", | 1143 | .platform = "ppc823", |
@@ -1083,6 +1150,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1083 | .cpu_name = "403GC", | 1150 | .cpu_name = "403GC", |
1084 | .cpu_features = CPU_FTRS_40X, | 1151 | .cpu_features = CPU_FTRS_40X, |
1085 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, | 1152 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, |
1153 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1086 | .icache_bsize = 16, | 1154 | .icache_bsize = 16, |
1087 | .dcache_bsize = 16, | 1155 | .dcache_bsize = 16, |
1088 | .machine_check = machine_check_4xx, | 1156 | .machine_check = machine_check_4xx, |
@@ -1095,6 +1163,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1095 | .cpu_features = CPU_FTRS_40X, | 1163 | .cpu_features = CPU_FTRS_40X, |
1096 | .cpu_user_features = PPC_FEATURE_32 | | 1164 | .cpu_user_features = PPC_FEATURE_32 | |
1097 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB, | 1165 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_NO_TB, |
1166 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1098 | .icache_bsize = 16, | 1167 | .icache_bsize = 16, |
1099 | .dcache_bsize = 16, | 1168 | .dcache_bsize = 16, |
1100 | .machine_check = machine_check_4xx, | 1169 | .machine_check = machine_check_4xx, |
@@ -1106,6 +1175,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1106 | .cpu_name = "403G ??", | 1175 | .cpu_name = "403G ??", |
1107 | .cpu_features = CPU_FTRS_40X, | 1176 | .cpu_features = CPU_FTRS_40X, |
1108 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, | 1177 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, |
1178 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1109 | .icache_bsize = 16, | 1179 | .icache_bsize = 16, |
1110 | .dcache_bsize = 16, | 1180 | .dcache_bsize = 16, |
1111 | .machine_check = machine_check_4xx, | 1181 | .machine_check = machine_check_4xx, |
@@ -1118,6 +1188,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1118 | .cpu_features = CPU_FTRS_40X, | 1188 | .cpu_features = CPU_FTRS_40X, |
1119 | .cpu_user_features = PPC_FEATURE_32 | | 1189 | .cpu_user_features = PPC_FEATURE_32 | |
1120 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1190 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1191 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1121 | .icache_bsize = 32, | 1192 | .icache_bsize = 32, |
1122 | .dcache_bsize = 32, | 1193 | .dcache_bsize = 32, |
1123 | .machine_check = machine_check_4xx, | 1194 | .machine_check = machine_check_4xx, |
@@ -1130,6 +1201,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1130 | .cpu_features = CPU_FTRS_40X, | 1201 | .cpu_features = CPU_FTRS_40X, |
1131 | .cpu_user_features = PPC_FEATURE_32 | | 1202 | .cpu_user_features = PPC_FEATURE_32 | |
1132 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1203 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1204 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1133 | .icache_bsize = 32, | 1205 | .icache_bsize = 32, |
1134 | .dcache_bsize = 32, | 1206 | .dcache_bsize = 32, |
1135 | .machine_check = machine_check_4xx, | 1207 | .machine_check = machine_check_4xx, |
@@ -1142,6 +1214,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1142 | .cpu_features = CPU_FTRS_40X, | 1214 | .cpu_features = CPU_FTRS_40X, |
1143 | .cpu_user_features = PPC_FEATURE_32 | | 1215 | .cpu_user_features = PPC_FEATURE_32 | |
1144 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1216 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1217 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1145 | .icache_bsize = 32, | 1218 | .icache_bsize = 32, |
1146 | .dcache_bsize = 32, | 1219 | .dcache_bsize = 32, |
1147 | .machine_check = machine_check_4xx, | 1220 | .machine_check = machine_check_4xx, |
@@ -1154,6 +1227,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1154 | .cpu_features = CPU_FTRS_40X, | 1227 | .cpu_features = CPU_FTRS_40X, |
1155 | .cpu_user_features = PPC_FEATURE_32 | | 1228 | .cpu_user_features = PPC_FEATURE_32 | |
1156 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1229 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1230 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1157 | .icache_bsize = 32, | 1231 | .icache_bsize = 32, |
1158 | .dcache_bsize = 32, | 1232 | .dcache_bsize = 32, |
1159 | .machine_check = machine_check_4xx, | 1233 | .machine_check = machine_check_4xx, |
@@ -1166,6 +1240,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1166 | .cpu_features = CPU_FTRS_40X, | 1240 | .cpu_features = CPU_FTRS_40X, |
1167 | .cpu_user_features = PPC_FEATURE_32 | | 1241 | .cpu_user_features = PPC_FEATURE_32 | |
1168 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1242 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1243 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1169 | .icache_bsize = 32, | 1244 | .icache_bsize = 32, |
1170 | .dcache_bsize = 32, | 1245 | .dcache_bsize = 32, |
1171 | .machine_check = machine_check_4xx, | 1246 | .machine_check = machine_check_4xx, |
@@ -1178,6 +1253,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1178 | .cpu_features = CPU_FTRS_40X, | 1253 | .cpu_features = CPU_FTRS_40X, |
1179 | .cpu_user_features = PPC_FEATURE_32 | | 1254 | .cpu_user_features = PPC_FEATURE_32 | |
1180 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1255 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1256 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1181 | .icache_bsize = 32, | 1257 | .icache_bsize = 32, |
1182 | .dcache_bsize = 32, | 1258 | .dcache_bsize = 32, |
1183 | .machine_check = machine_check_4xx, | 1259 | .machine_check = machine_check_4xx, |
@@ -1190,6 +1266,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1190 | .cpu_features = CPU_FTRS_40X, | 1266 | .cpu_features = CPU_FTRS_40X, |
1191 | .cpu_user_features = PPC_FEATURE_32 | | 1267 | .cpu_user_features = PPC_FEATURE_32 | |
1192 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1268 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1269 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1193 | .icache_bsize = 32, | 1270 | .icache_bsize = 32, |
1194 | .dcache_bsize = 32, | 1271 | .dcache_bsize = 32, |
1195 | .machine_check = machine_check_4xx, | 1272 | .machine_check = machine_check_4xx, |
@@ -1202,6 +1279,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1202 | .cpu_features = CPU_FTRS_40X, | 1279 | .cpu_features = CPU_FTRS_40X, |
1203 | .cpu_user_features = PPC_FEATURE_32 | | 1280 | .cpu_user_features = PPC_FEATURE_32 | |
1204 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1281 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1282 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1205 | .icache_bsize = 32, | 1283 | .icache_bsize = 32, |
1206 | .dcache_bsize = 32, | 1284 | .dcache_bsize = 32, |
1207 | .machine_check = machine_check_4xx, | 1285 | .machine_check = machine_check_4xx, |
@@ -1213,6 +1291,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1213 | .cpu_name = "405LP", | 1291 | .cpu_name = "405LP", |
1214 | .cpu_features = CPU_FTRS_40X, | 1292 | .cpu_features = CPU_FTRS_40X, |
1215 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, | 1293 | .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU, |
1294 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1216 | .icache_bsize = 32, | 1295 | .icache_bsize = 32, |
1217 | .dcache_bsize = 32, | 1296 | .dcache_bsize = 32, |
1218 | .machine_check = machine_check_4xx, | 1297 | .machine_check = machine_check_4xx, |
@@ -1225,6 +1304,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1225 | .cpu_features = CPU_FTRS_40X, | 1304 | .cpu_features = CPU_FTRS_40X, |
1226 | .cpu_user_features = PPC_FEATURE_32 | | 1305 | .cpu_user_features = PPC_FEATURE_32 | |
1227 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1306 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1307 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1228 | .icache_bsize = 32, | 1308 | .icache_bsize = 32, |
1229 | .dcache_bsize = 32, | 1309 | .dcache_bsize = 32, |
1230 | .machine_check = machine_check_4xx, | 1310 | .machine_check = machine_check_4xx, |
@@ -1237,6 +1317,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1237 | .cpu_features = CPU_FTRS_40X, | 1317 | .cpu_features = CPU_FTRS_40X, |
1238 | .cpu_user_features = PPC_FEATURE_32 | | 1318 | .cpu_user_features = PPC_FEATURE_32 | |
1239 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1319 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1320 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1240 | .icache_bsize = 32, | 1321 | .icache_bsize = 32, |
1241 | .dcache_bsize = 32, | 1322 | .dcache_bsize = 32, |
1242 | .machine_check = machine_check_4xx, | 1323 | .machine_check = machine_check_4xx, |
@@ -1249,6 +1330,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1249 | .cpu_features = CPU_FTRS_40X, | 1330 | .cpu_features = CPU_FTRS_40X, |
1250 | .cpu_user_features = PPC_FEATURE_32 | | 1331 | .cpu_user_features = PPC_FEATURE_32 | |
1251 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1332 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1333 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1252 | .icache_bsize = 32, | 1334 | .icache_bsize = 32, |
1253 | .dcache_bsize = 32, | 1335 | .dcache_bsize = 32, |
1254 | .machine_check = machine_check_4xx, | 1336 | .machine_check = machine_check_4xx, |
@@ -1261,6 +1343,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1261 | .cpu_features = CPU_FTRS_40X, | 1343 | .cpu_features = CPU_FTRS_40X, |
1262 | .cpu_user_features = PPC_FEATURE_32 | | 1344 | .cpu_user_features = PPC_FEATURE_32 | |
1263 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1345 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1346 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1264 | .icache_bsize = 32, | 1347 | .icache_bsize = 32, |
1265 | .dcache_bsize = 32, | 1348 | .dcache_bsize = 32, |
1266 | .machine_check = machine_check_4xx, | 1349 | .machine_check = machine_check_4xx, |
@@ -1273,6 +1356,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1273 | .cpu_features = CPU_FTRS_40X, | 1356 | .cpu_features = CPU_FTRS_40X, |
1274 | .cpu_user_features = PPC_FEATURE_32 | | 1357 | .cpu_user_features = PPC_FEATURE_32 | |
1275 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1358 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1359 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1276 | .icache_bsize = 32, | 1360 | .icache_bsize = 32, |
1277 | .dcache_bsize = 32, | 1361 | .dcache_bsize = 32, |
1278 | .machine_check = machine_check_4xx, | 1362 | .machine_check = machine_check_4xx, |
@@ -1286,6 +1370,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1286 | .cpu_features = CPU_FTRS_40X, | 1370 | .cpu_features = CPU_FTRS_40X, |
1287 | .cpu_user_features = PPC_FEATURE_32 | | 1371 | .cpu_user_features = PPC_FEATURE_32 | |
1288 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1372 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1373 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1289 | .icache_bsize = 32, | 1374 | .icache_bsize = 32, |
1290 | .dcache_bsize = 32, | 1375 | .dcache_bsize = 32, |
1291 | .machine_check = machine_check_4xx, | 1376 | .machine_check = machine_check_4xx, |
@@ -1298,6 +1383,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1298 | .cpu_features = CPU_FTRS_40X, | 1383 | .cpu_features = CPU_FTRS_40X, |
1299 | .cpu_user_features = PPC_FEATURE_32 | | 1384 | .cpu_user_features = PPC_FEATURE_32 | |
1300 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, | 1385 | PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC, |
1386 | .mmu_features = MMU_FTR_TYPE_40x, | ||
1301 | .icache_bsize = 32, | 1387 | .icache_bsize = 32, |
1302 | .dcache_bsize = 32, | 1388 | .dcache_bsize = 32, |
1303 | .machine_check = machine_check_4xx, | 1389 | .machine_check = machine_check_4xx, |
@@ -1312,6 +1398,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1312 | .cpu_name = "440GR Rev. A", | 1398 | .cpu_name = "440GR Rev. A", |
1313 | .cpu_features = CPU_FTRS_44X, | 1399 | .cpu_features = CPU_FTRS_44X, |
1314 | .cpu_user_features = COMMON_USER_BOOKE, | 1400 | .cpu_user_features = COMMON_USER_BOOKE, |
1401 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1315 | .icache_bsize = 32, | 1402 | .icache_bsize = 32, |
1316 | .dcache_bsize = 32, | 1403 | .dcache_bsize = 32, |
1317 | .machine_check = machine_check_4xx, | 1404 | .machine_check = machine_check_4xx, |
@@ -1323,6 +1410,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1323 | .cpu_name = "440EP Rev. A", | 1410 | .cpu_name = "440EP Rev. A", |
1324 | .cpu_features = CPU_FTRS_44X, | 1411 | .cpu_features = CPU_FTRS_44X, |
1325 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, | 1412 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, |
1413 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1326 | .icache_bsize = 32, | 1414 | .icache_bsize = 32, |
1327 | .dcache_bsize = 32, | 1415 | .dcache_bsize = 32, |
1328 | .cpu_setup = __setup_cpu_440ep, | 1416 | .cpu_setup = __setup_cpu_440ep, |
@@ -1335,6 +1423,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1335 | .cpu_name = "440GR Rev. B", | 1423 | .cpu_name = "440GR Rev. B", |
1336 | .cpu_features = CPU_FTRS_44X, | 1424 | .cpu_features = CPU_FTRS_44X, |
1337 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, | 1425 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, |
1426 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1338 | .icache_bsize = 32, | 1427 | .icache_bsize = 32, |
1339 | .dcache_bsize = 32, | 1428 | .dcache_bsize = 32, |
1340 | .machine_check = machine_check_4xx, | 1429 | .machine_check = machine_check_4xx, |
@@ -1346,6 +1435,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1346 | .cpu_name = "440EP Rev. C", | 1435 | .cpu_name = "440EP Rev. C", |
1347 | .cpu_features = CPU_FTRS_44X, | 1436 | .cpu_features = CPU_FTRS_44X, |
1348 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, | 1437 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, |
1438 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1349 | .icache_bsize = 32, | 1439 | .icache_bsize = 32, |
1350 | .dcache_bsize = 32, | 1440 | .dcache_bsize = 32, |
1351 | .cpu_setup = __setup_cpu_440ep, | 1441 | .cpu_setup = __setup_cpu_440ep, |
@@ -1358,6 +1448,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1358 | .cpu_name = "440EP Rev. B", | 1448 | .cpu_name = "440EP Rev. B", |
1359 | .cpu_features = CPU_FTRS_44X, | 1449 | .cpu_features = CPU_FTRS_44X, |
1360 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, | 1450 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, |
1451 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1361 | .icache_bsize = 32, | 1452 | .icache_bsize = 32, |
1362 | .dcache_bsize = 32, | 1453 | .dcache_bsize = 32, |
1363 | .cpu_setup = __setup_cpu_440ep, | 1454 | .cpu_setup = __setup_cpu_440ep, |
@@ -1370,6 +1461,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1370 | .cpu_name = "440GRX", | 1461 | .cpu_name = "440GRX", |
1371 | .cpu_features = CPU_FTRS_44X, | 1462 | .cpu_features = CPU_FTRS_44X, |
1372 | .cpu_user_features = COMMON_USER_BOOKE, | 1463 | .cpu_user_features = COMMON_USER_BOOKE, |
1464 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1373 | .icache_bsize = 32, | 1465 | .icache_bsize = 32, |
1374 | .dcache_bsize = 32, | 1466 | .dcache_bsize = 32, |
1375 | .cpu_setup = __setup_cpu_440grx, | 1467 | .cpu_setup = __setup_cpu_440grx, |
@@ -1382,6 +1474,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1382 | .cpu_name = "440EPX", | 1474 | .cpu_name = "440EPX", |
1383 | .cpu_features = CPU_FTRS_44X, | 1475 | .cpu_features = CPU_FTRS_44X, |
1384 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, | 1476 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, |
1477 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1385 | .icache_bsize = 32, | 1478 | .icache_bsize = 32, |
1386 | .dcache_bsize = 32, | 1479 | .dcache_bsize = 32, |
1387 | .cpu_setup = __setup_cpu_440epx, | 1480 | .cpu_setup = __setup_cpu_440epx, |
@@ -1394,6 +1487,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1394 | .cpu_name = "440GP Rev. B", | 1487 | .cpu_name = "440GP Rev. B", |
1395 | .cpu_features = CPU_FTRS_44X, | 1488 | .cpu_features = CPU_FTRS_44X, |
1396 | .cpu_user_features = COMMON_USER_BOOKE, | 1489 | .cpu_user_features = COMMON_USER_BOOKE, |
1490 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1397 | .icache_bsize = 32, | 1491 | .icache_bsize = 32, |
1398 | .dcache_bsize = 32, | 1492 | .dcache_bsize = 32, |
1399 | .machine_check = machine_check_4xx, | 1493 | .machine_check = machine_check_4xx, |
@@ -1405,6 +1499,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1405 | .cpu_name = "440GP Rev. C", | 1499 | .cpu_name = "440GP Rev. C", |
1406 | .cpu_features = CPU_FTRS_44X, | 1500 | .cpu_features = CPU_FTRS_44X, |
1407 | .cpu_user_features = COMMON_USER_BOOKE, | 1501 | .cpu_user_features = COMMON_USER_BOOKE, |
1502 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1408 | .icache_bsize = 32, | 1503 | .icache_bsize = 32, |
1409 | .dcache_bsize = 32, | 1504 | .dcache_bsize = 32, |
1410 | .machine_check = machine_check_4xx, | 1505 | .machine_check = machine_check_4xx, |
@@ -1416,6 +1511,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1416 | .cpu_name = "440GX Rev. A", | 1511 | .cpu_name = "440GX Rev. A", |
1417 | .cpu_features = CPU_FTRS_44X, | 1512 | .cpu_features = CPU_FTRS_44X, |
1418 | .cpu_user_features = COMMON_USER_BOOKE, | 1513 | .cpu_user_features = COMMON_USER_BOOKE, |
1514 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1419 | .icache_bsize = 32, | 1515 | .icache_bsize = 32, |
1420 | .dcache_bsize = 32, | 1516 | .dcache_bsize = 32, |
1421 | .cpu_setup = __setup_cpu_440gx, | 1517 | .cpu_setup = __setup_cpu_440gx, |
@@ -1428,6 +1524,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1428 | .cpu_name = "440GX Rev. B", | 1524 | .cpu_name = "440GX Rev. B", |
1429 | .cpu_features = CPU_FTRS_44X, | 1525 | .cpu_features = CPU_FTRS_44X, |
1430 | .cpu_user_features = COMMON_USER_BOOKE, | 1526 | .cpu_user_features = COMMON_USER_BOOKE, |
1527 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1431 | .icache_bsize = 32, | 1528 | .icache_bsize = 32, |
1432 | .dcache_bsize = 32, | 1529 | .dcache_bsize = 32, |
1433 | .cpu_setup = __setup_cpu_440gx, | 1530 | .cpu_setup = __setup_cpu_440gx, |
@@ -1440,6 +1537,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1440 | .cpu_name = "440GX Rev. C", | 1537 | .cpu_name = "440GX Rev. C", |
1441 | .cpu_features = CPU_FTRS_44X, | 1538 | .cpu_features = CPU_FTRS_44X, |
1442 | .cpu_user_features = COMMON_USER_BOOKE, | 1539 | .cpu_user_features = COMMON_USER_BOOKE, |
1540 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1443 | .icache_bsize = 32, | 1541 | .icache_bsize = 32, |
1444 | .dcache_bsize = 32, | 1542 | .dcache_bsize = 32, |
1445 | .cpu_setup = __setup_cpu_440gx, | 1543 | .cpu_setup = __setup_cpu_440gx, |
@@ -1452,6 +1550,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1452 | .cpu_name = "440GX Rev. F", | 1550 | .cpu_name = "440GX Rev. F", |
1453 | .cpu_features = CPU_FTRS_44X, | 1551 | .cpu_features = CPU_FTRS_44X, |
1454 | .cpu_user_features = COMMON_USER_BOOKE, | 1552 | .cpu_user_features = COMMON_USER_BOOKE, |
1553 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1455 | .icache_bsize = 32, | 1554 | .icache_bsize = 32, |
1456 | .dcache_bsize = 32, | 1555 | .dcache_bsize = 32, |
1457 | .cpu_setup = __setup_cpu_440gx, | 1556 | .cpu_setup = __setup_cpu_440gx, |
@@ -1464,6 +1563,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1464 | .cpu_name = "440SP Rev. A", | 1563 | .cpu_name = "440SP Rev. A", |
1465 | .cpu_features = CPU_FTRS_44X, | 1564 | .cpu_features = CPU_FTRS_44X, |
1466 | .cpu_user_features = COMMON_USER_BOOKE, | 1565 | .cpu_user_features = COMMON_USER_BOOKE, |
1566 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1467 | .icache_bsize = 32, | 1567 | .icache_bsize = 32, |
1468 | .dcache_bsize = 32, | 1568 | .dcache_bsize = 32, |
1469 | .machine_check = machine_check_4xx, | 1569 | .machine_check = machine_check_4xx, |
@@ -1475,6 +1575,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1475 | .cpu_name = "440SPe Rev. A", | 1575 | .cpu_name = "440SPe Rev. A", |
1476 | .cpu_features = CPU_FTRS_44X, | 1576 | .cpu_features = CPU_FTRS_44X, |
1477 | .cpu_user_features = COMMON_USER_BOOKE, | 1577 | .cpu_user_features = COMMON_USER_BOOKE, |
1578 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1478 | .icache_bsize = 32, | 1579 | .icache_bsize = 32, |
1479 | .dcache_bsize = 32, | 1580 | .dcache_bsize = 32, |
1480 | .cpu_setup = __setup_cpu_440spe, | 1581 | .cpu_setup = __setup_cpu_440spe, |
@@ -1487,6 +1588,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1487 | .cpu_name = "440SPe Rev. B", | 1588 | .cpu_name = "440SPe Rev. B", |
1488 | .cpu_features = CPU_FTRS_44X, | 1589 | .cpu_features = CPU_FTRS_44X, |
1489 | .cpu_user_features = COMMON_USER_BOOKE, | 1590 | .cpu_user_features = COMMON_USER_BOOKE, |
1591 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1490 | .icache_bsize = 32, | 1592 | .icache_bsize = 32, |
1491 | .dcache_bsize = 32, | 1593 | .dcache_bsize = 32, |
1492 | .cpu_setup = __setup_cpu_440spe, | 1594 | .cpu_setup = __setup_cpu_440spe, |
@@ -1499,6 +1601,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1499 | .cpu_name = "440 in Virtex-5 FXT", | 1601 | .cpu_name = "440 in Virtex-5 FXT", |
1500 | .cpu_features = CPU_FTRS_44X, | 1602 | .cpu_features = CPU_FTRS_44X, |
1501 | .cpu_user_features = COMMON_USER_BOOKE, | 1603 | .cpu_user_features = COMMON_USER_BOOKE, |
1604 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1502 | .icache_bsize = 32, | 1605 | .icache_bsize = 32, |
1503 | .dcache_bsize = 32, | 1606 | .dcache_bsize = 32, |
1504 | .cpu_setup = __setup_cpu_440x5, | 1607 | .cpu_setup = __setup_cpu_440x5, |
@@ -1511,6 +1614,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1511 | .cpu_name = "460EX", | 1614 | .cpu_name = "460EX", |
1512 | .cpu_features = CPU_FTRS_440x6, | 1615 | .cpu_features = CPU_FTRS_440x6, |
1513 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, | 1616 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, |
1617 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1514 | .icache_bsize = 32, | 1618 | .icache_bsize = 32, |
1515 | .dcache_bsize = 32, | 1619 | .dcache_bsize = 32, |
1516 | .cpu_setup = __setup_cpu_460ex, | 1620 | .cpu_setup = __setup_cpu_460ex, |
@@ -1523,6 +1627,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1523 | .cpu_name = "460GT", | 1627 | .cpu_name = "460GT", |
1524 | .cpu_features = CPU_FTRS_440x6, | 1628 | .cpu_features = CPU_FTRS_440x6, |
1525 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, | 1629 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, |
1630 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1526 | .icache_bsize = 32, | 1631 | .icache_bsize = 32, |
1527 | .dcache_bsize = 32, | 1632 | .dcache_bsize = 32, |
1528 | .cpu_setup = __setup_cpu_460gt, | 1633 | .cpu_setup = __setup_cpu_460gt, |
@@ -1535,6 +1640,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1535 | .cpu_name = "(generic 44x PPC)", | 1640 | .cpu_name = "(generic 44x PPC)", |
1536 | .cpu_features = CPU_FTRS_44X, | 1641 | .cpu_features = CPU_FTRS_44X, |
1537 | .cpu_user_features = COMMON_USER_BOOKE, | 1642 | .cpu_user_features = COMMON_USER_BOOKE, |
1643 | .mmu_features = MMU_FTR_TYPE_44x, | ||
1538 | .icache_bsize = 32, | 1644 | .icache_bsize = 32, |
1539 | .dcache_bsize = 32, | 1645 | .dcache_bsize = 32, |
1540 | .machine_check = machine_check_4xx, | 1646 | .machine_check = machine_check_4xx, |
@@ -1551,6 +1657,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1551 | .cpu_user_features = COMMON_USER_BOOKE | | 1657 | .cpu_user_features = COMMON_USER_BOOKE | |
1552 | PPC_FEATURE_HAS_EFP_SINGLE | | 1658 | PPC_FEATURE_HAS_EFP_SINGLE | |
1553 | PPC_FEATURE_UNIFIED_CACHE, | 1659 | PPC_FEATURE_UNIFIED_CACHE, |
1660 | .mmu_features = MMU_FTR_TYPE_FSL_E, | ||
1554 | .dcache_bsize = 32, | 1661 | .dcache_bsize = 32, |
1555 | .machine_check = machine_check_e200, | 1662 | .machine_check = machine_check_e200, |
1556 | .platform = "ppc5554", | 1663 | .platform = "ppc5554", |
@@ -1565,6 +1672,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1565 | PPC_FEATURE_HAS_SPE_COMP | | 1672 | PPC_FEATURE_HAS_SPE_COMP | |
1566 | PPC_FEATURE_HAS_EFP_SINGLE_COMP | | 1673 | PPC_FEATURE_HAS_EFP_SINGLE_COMP | |
1567 | PPC_FEATURE_UNIFIED_CACHE, | 1674 | PPC_FEATURE_UNIFIED_CACHE, |
1675 | .mmu_features = MMU_FTR_TYPE_FSL_E, | ||
1568 | .dcache_bsize = 32, | 1676 | .dcache_bsize = 32, |
1569 | .machine_check = machine_check_e200, | 1677 | .machine_check = machine_check_e200, |
1570 | .platform = "ppc5554", | 1678 | .platform = "ppc5554", |
@@ -1577,6 +1685,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1577 | .cpu_user_features = COMMON_USER_BOOKE | | 1685 | .cpu_user_features = COMMON_USER_BOOKE | |
1578 | PPC_FEATURE_HAS_EFP_SINGLE | | 1686 | PPC_FEATURE_HAS_EFP_SINGLE | |
1579 | PPC_FEATURE_UNIFIED_CACHE, | 1687 | PPC_FEATURE_UNIFIED_CACHE, |
1688 | .mmu_features = MMU_FTR_TYPE_FSL_E, | ||
1580 | .dcache_bsize = 32, | 1689 | .dcache_bsize = 32, |
1581 | .machine_check = machine_check_e200, | 1690 | .machine_check = machine_check_e200, |
1582 | .platform = "ppc5554", | 1691 | .platform = "ppc5554", |
@@ -1591,6 +1700,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1591 | .cpu_user_features = COMMON_USER_BOOKE | | 1700 | .cpu_user_features = COMMON_USER_BOOKE | |
1592 | PPC_FEATURE_HAS_SPE_COMP | | 1701 | PPC_FEATURE_HAS_SPE_COMP | |
1593 | PPC_FEATURE_HAS_EFP_SINGLE_COMP, | 1702 | PPC_FEATURE_HAS_EFP_SINGLE_COMP, |
1703 | .mmu_features = MMU_FTR_TYPE_FSL_E, | ||
1594 | .icache_bsize = 32, | 1704 | .icache_bsize = 32, |
1595 | .dcache_bsize = 32, | 1705 | .dcache_bsize = 32, |
1596 | .num_pmcs = 4, | 1706 | .num_pmcs = 4, |
@@ -1608,6 +1718,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1608 | PPC_FEATURE_HAS_SPE_COMP | | 1718 | PPC_FEATURE_HAS_SPE_COMP | |
1609 | PPC_FEATURE_HAS_EFP_SINGLE_COMP | | 1719 | PPC_FEATURE_HAS_EFP_SINGLE_COMP | |
1610 | PPC_FEATURE_HAS_EFP_DOUBLE_COMP, | 1720 | PPC_FEATURE_HAS_EFP_DOUBLE_COMP, |
1721 | .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS, | ||
1611 | .icache_bsize = 32, | 1722 | .icache_bsize = 32, |
1612 | .dcache_bsize = 32, | 1723 | .dcache_bsize = 32, |
1613 | .num_pmcs = 4, | 1724 | .num_pmcs = 4, |
@@ -1622,6 +1733,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1622 | .cpu_name = "e500mc", | 1733 | .cpu_name = "e500mc", |
1623 | .cpu_features = CPU_FTRS_E500MC, | 1734 | .cpu_features = CPU_FTRS_E500MC, |
1624 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, | 1735 | .cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU, |
1736 | .mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS, | ||
1625 | .icache_bsize = 64, | 1737 | .icache_bsize = 64, |
1626 | .dcache_bsize = 64, | 1738 | .dcache_bsize = 64, |
1627 | .num_pmcs = 4, | 1739 | .num_pmcs = 4, |
@@ -1638,6 +1750,7 @@ static struct cpu_spec __initdata cpu_specs[] = { | |||
1638 | .cpu_user_features = COMMON_USER_BOOKE | | 1750 | .cpu_user_features = COMMON_USER_BOOKE | |
1639 | PPC_FEATURE_HAS_SPE_COMP | | 1751 | PPC_FEATURE_HAS_SPE_COMP | |
1640 | PPC_FEATURE_HAS_EFP_SINGLE_COMP, | 1752 | PPC_FEATURE_HAS_EFP_SINGLE_COMP, |
1753 | .mmu_features = MMU_FTR_TYPE_FSL_E, | ||
1641 | .icache_bsize = 32, | 1754 | .icache_bsize = 32, |
1642 | .dcache_bsize = 32, | 1755 | .dcache_bsize = 32, |
1643 | .machine_check = machine_check_e500, | 1756 | .machine_check = machine_check_e500, |
diff --git a/arch/powerpc/kernel/head_32.S b/arch/powerpc/kernel/head_32.S index be9f9e5470e8..266061924654 100644 --- a/arch/powerpc/kernel/head_32.S +++ b/arch/powerpc/kernel/head_32.S | |||
@@ -990,12 +990,12 @@ load_up_mmu: | |||
990 | LOAD_BAT(1,r3,r4,r5) | 990 | LOAD_BAT(1,r3,r4,r5) |
991 | LOAD_BAT(2,r3,r4,r5) | 991 | LOAD_BAT(2,r3,r4,r5) |
992 | LOAD_BAT(3,r3,r4,r5) | 992 | LOAD_BAT(3,r3,r4,r5) |
993 | BEGIN_FTR_SECTION | 993 | BEGIN_MMU_FTR_SECTION |
994 | LOAD_BAT(4,r3,r4,r5) | 994 | LOAD_BAT(4,r3,r4,r5) |
995 | LOAD_BAT(5,r3,r4,r5) | 995 | LOAD_BAT(5,r3,r4,r5) |
996 | LOAD_BAT(6,r3,r4,r5) | 996 | LOAD_BAT(6,r3,r4,r5) |
997 | LOAD_BAT(7,r3,r4,r5) | 997 | LOAD_BAT(7,r3,r4,r5) |
998 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) | 998 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
999 | blr | 999 | blr |
1000 | 1000 | ||
1001 | /* | 1001 | /* |
@@ -1141,7 +1141,7 @@ clear_bats: | |||
1141 | mtspr SPRN_IBAT2L,r10 | 1141 | mtspr SPRN_IBAT2L,r10 |
1142 | mtspr SPRN_IBAT3U,r10 | 1142 | mtspr SPRN_IBAT3U,r10 |
1143 | mtspr SPRN_IBAT3L,r10 | 1143 | mtspr SPRN_IBAT3L,r10 |
1144 | BEGIN_FTR_SECTION | 1144 | BEGIN_MMU_FTR_SECTION |
1145 | /* Here's a tweak: at this point, CPU setup have | 1145 | /* Here's a tweak: at this point, CPU setup have |
1146 | * not been called yet, so HIGH_BAT_EN may not be | 1146 | * not been called yet, so HIGH_BAT_EN may not be |
1147 | * set in HID0 for the 745x processors. However, it | 1147 | * set in HID0 for the 745x processors. However, it |
@@ -1164,7 +1164,7 @@ BEGIN_FTR_SECTION | |||
1164 | mtspr SPRN_IBAT6L,r10 | 1164 | mtspr SPRN_IBAT6L,r10 |
1165 | mtspr SPRN_IBAT7U,r10 | 1165 | mtspr SPRN_IBAT7U,r10 |
1166 | mtspr SPRN_IBAT7L,r10 | 1166 | mtspr SPRN_IBAT7L,r10 |
1167 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) | 1167 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
1168 | blr | 1168 | blr |
1169 | 1169 | ||
1170 | flush_tlbs: | 1170 | flush_tlbs: |
diff --git a/arch/powerpc/kernel/head_fsl_booke.S b/arch/powerpc/kernel/head_fsl_booke.S index 9a4639c459e6..11b549acc034 100644 --- a/arch/powerpc/kernel/head_fsl_booke.S +++ b/arch/powerpc/kernel/head_fsl_booke.S | |||
@@ -767,10 +767,10 @@ finish_tlb_load: | |||
767 | rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */ | 767 | rlwimi r12, r13, 24, 0, 7 /* grab RPN[32:39] */ |
768 | rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */ | 768 | rlwimi r12, r11, 24, 8, 19 /* grab RPN[40:51] */ |
769 | mtspr SPRN_MAS3, r12 | 769 | mtspr SPRN_MAS3, r12 |
770 | BEGIN_FTR_SECTION | 770 | BEGIN_MMU_FTR_SECTION |
771 | srwi r10, r13, 8 /* grab RPN[8:31] */ | 771 | srwi r10, r13, 8 /* grab RPN[8:31] */ |
772 | mtspr SPRN_MAS7, r10 | 772 | mtspr SPRN_MAS7, r10 |
773 | END_FTR_SECTION_IFSET(CPU_FTR_BIG_PHYS) | 773 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_BIG_PHYS) |
774 | #else | 774 | #else |
775 | rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ | 775 | rlwimi r11, r12, 0, 20, 31 /* Extract RPN from PTE and merge with perms */ |
776 | mtspr SPRN_MAS3, r11 | 776 | mtspr SPRN_MAS3, r11 |
diff --git a/arch/powerpc/kernel/module.c b/arch/powerpc/kernel/module.c index 7ff292475269..43e7e3a7f130 100644 --- a/arch/powerpc/kernel/module.c +++ b/arch/powerpc/kernel/module.c | |||
@@ -78,6 +78,12 @@ int module_finalize(const Elf_Ehdr *hdr, | |||
78 | (void *)sect->sh_addr, | 78 | (void *)sect->sh_addr, |
79 | (void *)sect->sh_addr + sect->sh_size); | 79 | (void *)sect->sh_addr + sect->sh_size); |
80 | 80 | ||
81 | sect = find_section(hdr, sechdrs, "__mmu_ftr_fixup"); | ||
82 | if (sect != NULL) | ||
83 | do_feature_fixups(cur_cpu_spec->mmu_features, | ||
84 | (void *)sect->sh_addr, | ||
85 | (void *)sect->sh_addr + sect->sh_size); | ||
86 | |||
81 | #ifdef CONFIG_PPC64 | 87 | #ifdef CONFIG_PPC64 |
82 | sect = find_section(hdr, sechdrs, "__fw_ftr_fixup"); | 88 | sect = find_section(hdr, sechdrs, "__fw_ftr_fixup"); |
83 | if (sect != NULL) | 89 | if (sect != NULL) |
diff --git a/arch/powerpc/kernel/setup_32.c b/arch/powerpc/kernel/setup_32.c index 086c23c1ee5e..b14c2a3e2185 100644 --- a/arch/powerpc/kernel/setup_32.c +++ b/arch/powerpc/kernel/setup_32.c | |||
@@ -97,6 +97,10 @@ notrace unsigned long __init early_init(unsigned long dt_ptr) | |||
97 | PTRRELOC(&__start___ftr_fixup), | 97 | PTRRELOC(&__start___ftr_fixup), |
98 | PTRRELOC(&__stop___ftr_fixup)); | 98 | PTRRELOC(&__stop___ftr_fixup)); |
99 | 99 | ||
100 | do_feature_fixups(spec->mmu_features, | ||
101 | PTRRELOC(&__start___mmu_ftr_fixup), | ||
102 | PTRRELOC(&__stop___mmu_ftr_fixup)); | ||
103 | |||
100 | do_lwsync_fixups(spec->cpu_features, | 104 | do_lwsync_fixups(spec->cpu_features, |
101 | PTRRELOC(&__start___lwsync_fixup), | 105 | PTRRELOC(&__start___lwsync_fixup), |
102 | PTRRELOC(&__stop___lwsync_fixup)); | 106 | PTRRELOC(&__stop___lwsync_fixup)); |
diff --git a/arch/powerpc/kernel/setup_64.c b/arch/powerpc/kernel/setup_64.c index ce48f5c5c542..d8bd2161e738 100644 --- a/arch/powerpc/kernel/setup_64.c +++ b/arch/powerpc/kernel/setup_64.c | |||
@@ -361,6 +361,8 @@ void __init setup_system(void) | |||
361 | */ | 361 | */ |
362 | do_feature_fixups(cur_cpu_spec->cpu_features, | 362 | do_feature_fixups(cur_cpu_spec->cpu_features, |
363 | &__start___ftr_fixup, &__stop___ftr_fixup); | 363 | &__start___ftr_fixup, &__stop___ftr_fixup); |
364 | do_feature_fixups(cur_cpu_spec->mmu_features, | ||
365 | &__start___mmu_ftr_fixup, &__stop___mmu_ftr_fixup); | ||
364 | do_feature_fixups(powerpc_firmware_features, | 366 | do_feature_fixups(powerpc_firmware_features, |
365 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); | 367 | &__start___fw_ftr_fixup, &__stop___fw_ftr_fixup); |
366 | do_lwsync_fixups(cur_cpu_spec->cpu_features, | 368 | do_lwsync_fixups(cur_cpu_spec->cpu_features, |
diff --git a/arch/powerpc/kernel/swsusp_32.S b/arch/powerpc/kernel/swsusp_32.S index 77fc76607ab2..b47d8ceffb52 100644 --- a/arch/powerpc/kernel/swsusp_32.S +++ b/arch/powerpc/kernel/swsusp_32.S | |||
@@ -5,7 +5,7 @@ | |||
5 | #include <asm/thread_info.h> | 5 | #include <asm/thread_info.h> |
6 | #include <asm/ppc_asm.h> | 6 | #include <asm/ppc_asm.h> |
7 | #include <asm/asm-offsets.h> | 7 | #include <asm/asm-offsets.h> |
8 | 8 | #include <asm/mmu.h> | |
9 | 9 | ||
10 | /* | 10 | /* |
11 | * Structure for storing CPU registers on the save area. | 11 | * Structure for storing CPU registers on the save area. |
@@ -279,7 +279,7 @@ END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC) | |||
279 | mtibatl 3,r4 | 279 | mtibatl 3,r4 |
280 | #endif | 280 | #endif |
281 | 281 | ||
282 | BEGIN_FTR_SECTION | 282 | BEGIN_MMU_FTR_SECTION |
283 | li r4,0 | 283 | li r4,0 |
284 | mtspr SPRN_DBAT4U,r4 | 284 | mtspr SPRN_DBAT4U,r4 |
285 | mtspr SPRN_DBAT4L,r4 | 285 | mtspr SPRN_DBAT4L,r4 |
@@ -297,7 +297,7 @@ BEGIN_FTR_SECTION | |||
297 | mtspr SPRN_IBAT6L,r4 | 297 | mtspr SPRN_IBAT6L,r4 |
298 | mtspr SPRN_IBAT7U,r4 | 298 | mtspr SPRN_IBAT7U,r4 |
299 | mtspr SPRN_IBAT7L,r4 | 299 | mtspr SPRN_IBAT7L,r4 |
300 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) | 300 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
301 | 301 | ||
302 | /* Flush all TLBs */ | 302 | /* Flush all TLBs */ |
303 | lis r4,0x1000 | 303 | lis r4,0x1000 |
diff --git a/arch/powerpc/kernel/vdso.c b/arch/powerpc/kernel/vdso.c index 65639a43e644..e619d424f73d 100644 --- a/arch/powerpc/kernel/vdso.c +++ b/arch/powerpc/kernel/vdso.c | |||
@@ -567,6 +567,11 @@ static __init int vdso_fixup_features(struct lib32_elfinfo *v32, | |||
567 | do_feature_fixups(cur_cpu_spec->cpu_features, | 567 | do_feature_fixups(cur_cpu_spec->cpu_features, |
568 | start64, start64 + size64); | 568 | start64, start64 + size64); |
569 | 569 | ||
570 | start64 = find_section64(v64->hdr, "__mmu_ftr_fixup", &size64); | ||
571 | if (start64) | ||
572 | do_feature_fixups(cur_cpu_spec->mmu_features, | ||
573 | start64, start64 + size64); | ||
574 | |||
570 | start64 = find_section64(v64->hdr, "__fw_ftr_fixup", &size64); | 575 | start64 = find_section64(v64->hdr, "__fw_ftr_fixup", &size64); |
571 | if (start64) | 576 | if (start64) |
572 | do_feature_fixups(powerpc_firmware_features, | 577 | do_feature_fixups(powerpc_firmware_features, |
@@ -583,6 +588,11 @@ static __init int vdso_fixup_features(struct lib32_elfinfo *v32, | |||
583 | do_feature_fixups(cur_cpu_spec->cpu_features, | 588 | do_feature_fixups(cur_cpu_spec->cpu_features, |
584 | start32, start32 + size32); | 589 | start32, start32 + size32); |
585 | 590 | ||
591 | start32 = find_section32(v32->hdr, "__mmu_ftr_fixup", &size32); | ||
592 | if (start32) | ||
593 | do_feature_fixups(cur_cpu_spec->mmu_features, | ||
594 | start32, start32 + size32); | ||
595 | |||
586 | #ifdef CONFIG_PPC64 | 596 | #ifdef CONFIG_PPC64 |
587 | start32 = find_section32(v32->hdr, "__fw_ftr_fixup", &size32); | 597 | start32 = find_section32(v32->hdr, "__fw_ftr_fixup", &size32); |
588 | if (start32) | 598 | if (start32) |
diff --git a/arch/powerpc/kernel/vdso32/vdso32.lds.S b/arch/powerpc/kernel/vdso32/vdso32.lds.S index be3b6a41dc09..904ef1360dd7 100644 --- a/arch/powerpc/kernel/vdso32/vdso32.lds.S +++ b/arch/powerpc/kernel/vdso32/vdso32.lds.S | |||
@@ -34,6 +34,9 @@ SECTIONS | |||
34 | __ftr_fixup : { *(__ftr_fixup) } | 34 | __ftr_fixup : { *(__ftr_fixup) } |
35 | 35 | ||
36 | . = ALIGN(8); | 36 | . = ALIGN(8); |
37 | __mmu_ftr_fixup : { *(__mmu_ftr_fixup) } | ||
38 | |||
39 | . = ALIGN(8); | ||
37 | __lwsync_fixup : { *(__lwsync_fixup) } | 40 | __lwsync_fixup : { *(__lwsync_fixup) } |
38 | 41 | ||
39 | #ifdef CONFIG_PPC64 | 42 | #ifdef CONFIG_PPC64 |
diff --git a/arch/powerpc/kernel/vdso64/vdso64.lds.S b/arch/powerpc/kernel/vdso64/vdso64.lds.S index d0b2526dd38d..0e615404e247 100644 --- a/arch/powerpc/kernel/vdso64/vdso64.lds.S +++ b/arch/powerpc/kernel/vdso64/vdso64.lds.S | |||
@@ -35,6 +35,9 @@ SECTIONS | |||
35 | __ftr_fixup : { *(__ftr_fixup) } | 35 | __ftr_fixup : { *(__ftr_fixup) } |
36 | 36 | ||
37 | . = ALIGN(8); | 37 | . = ALIGN(8); |
38 | __mmu_ftr_fixup : { *(__mmu_ftr_fixup) } | ||
39 | |||
40 | . = ALIGN(8); | ||
38 | __lwsync_fixup : { *(__lwsync_fixup) } | 41 | __lwsync_fixup : { *(__lwsync_fixup) } |
39 | 42 | ||
40 | . = ALIGN(8); | 43 | . = ALIGN(8); |
diff --git a/arch/powerpc/kernel/vmlinux.lds.S b/arch/powerpc/kernel/vmlinux.lds.S index 2412c056baa4..47bf15cd2c9e 100644 --- a/arch/powerpc/kernel/vmlinux.lds.S +++ b/arch/powerpc/kernel/vmlinux.lds.S | |||
@@ -152,6 +152,12 @@ SECTIONS | |||
152 | __stop___ftr_fixup = .; | 152 | __stop___ftr_fixup = .; |
153 | } | 153 | } |
154 | . = ALIGN(8); | 154 | . = ALIGN(8); |
155 | __mmu_ftr_fixup : AT(ADDR(__mmu_ftr_fixup) - LOAD_OFFSET) { | ||
156 | __start___mmu_ftr_fixup = .; | ||
157 | *(__mmu_ftr_fixup) | ||
158 | __stop___mmu_ftr_fixup = .; | ||
159 | } | ||
160 | . = ALIGN(8); | ||
155 | __lwsync_fixup : AT(ADDR(__lwsync_fixup) - LOAD_OFFSET) { | 161 | __lwsync_fixup : AT(ADDR(__lwsync_fixup) - LOAD_OFFSET) { |
156 | __start___lwsync_fixup = .; | 162 | __start___lwsync_fixup = .; |
157 | *(__lwsync_fixup) | 163 | *(__lwsync_fixup) |
diff --git a/arch/powerpc/mm/ppc_mmu_32.c b/arch/powerpc/mm/ppc_mmu_32.c index 6aa120813775..9d97db7b7cf7 100644 --- a/arch/powerpc/mm/ppc_mmu_32.c +++ b/arch/powerpc/mm/ppc_mmu_32.c | |||
@@ -192,7 +192,7 @@ void __init MMU_init_hw(void) | |||
192 | extern unsigned int hash_page[]; | 192 | extern unsigned int hash_page[]; |
193 | extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[]; | 193 | extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[]; |
194 | 194 | ||
195 | if (!cpu_has_feature(CPU_FTR_HPTE_TABLE)) { | 195 | if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) { |
196 | /* | 196 | /* |
197 | * Put a blr (procedure return) instruction at the | 197 | * Put a blr (procedure return) instruction at the |
198 | * start of hash_page, since we can still get DSI | 198 | * start of hash_page, since we can still get DSI |
diff --git a/arch/powerpc/platforms/powermac/sleep.S b/arch/powerpc/platforms/powermac/sleep.S index adee28da353f..1c2802fabd57 100644 --- a/arch/powerpc/platforms/powermac/sleep.S +++ b/arch/powerpc/platforms/powermac/sleep.S | |||
@@ -17,6 +17,7 @@ | |||
17 | #include <asm/cache.h> | 17 | #include <asm/cache.h> |
18 | #include <asm/thread_info.h> | 18 | #include <asm/thread_info.h> |
19 | #include <asm/asm-offsets.h> | 19 | #include <asm/asm-offsets.h> |
20 | #include <asm/mmu.h> | ||
20 | 21 | ||
21 | #define MAGIC 0x4c617273 /* 'Lars' */ | 22 | #define MAGIC 0x4c617273 /* 'Lars' */ |
22 | 23 | ||
@@ -323,7 +324,7 @@ grackle_wake_up: | |||
323 | lwz r4,SL_IBAT3+4(r1) | 324 | lwz r4,SL_IBAT3+4(r1) |
324 | mtibatl 3,r4 | 325 | mtibatl 3,r4 |
325 | 326 | ||
326 | BEGIN_FTR_SECTION | 327 | BEGIN_MMU_FTR_SECTION |
327 | li r4,0 | 328 | li r4,0 |
328 | mtspr SPRN_DBAT4U,r4 | 329 | mtspr SPRN_DBAT4U,r4 |
329 | mtspr SPRN_DBAT4L,r4 | 330 | mtspr SPRN_DBAT4L,r4 |
@@ -341,7 +342,7 @@ BEGIN_FTR_SECTION | |||
341 | mtspr SPRN_IBAT6L,r4 | 342 | mtspr SPRN_IBAT6L,r4 |
342 | mtspr SPRN_IBAT7U,r4 | 343 | mtspr SPRN_IBAT7U,r4 |
343 | mtspr SPRN_IBAT7L,r4 | 344 | mtspr SPRN_IBAT7L,r4 |
344 | END_FTR_SECTION_IFSET(CPU_FTR_HAS_HIGH_BATS) | 345 | END_MMU_FTR_SECTION_IFSET(MMU_FTR_USE_HIGH_BATS) |
345 | 346 | ||
346 | /* Flush all TLBs */ | 347 | /* Flush all TLBs */ |
347 | lis r4,0x1000 | 348 | lis r4,0x1000 |