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-rw-r--r--drivers/gpu/drm/radeon/evergreen.c123
-rw-r--r--drivers/gpu/drm/radeon/evergreen_blit_kms.c242
-rw-r--r--drivers/gpu/drm/radeon/ni.c129
-rw-r--r--drivers/gpu/drm/radeon/r100.c149
-rw-r--r--drivers/gpu/drm/radeon/r200.c21
-rw-r--r--drivers/gpu/drm/radeon/r300.c127
-rw-r--r--drivers/gpu/drm/radeon/r420.c22
-rw-r--r--drivers/gpu/drm/radeon/r600.c201
-rw-r--r--drivers/gpu/drm/radeon/r600_blit_kms.c221
-rw-r--r--drivers/gpu/drm/radeon/radeon.h53
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.h28
-rw-r--r--drivers/gpu/drm/radeon/radeon_cs.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_fence.c2
-rw-r--r--drivers/gpu/drm/radeon/radeon_gem.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_pm.c13
-rw-r--r--drivers/gpu/drm/radeon/radeon_ring.c121
-rw-r--r--drivers/gpu/drm/radeon/radeon_semaphore.c4
-rw-r--r--drivers/gpu/drm/radeon/radeon_test.c3
-rw-r--r--drivers/gpu/drm/radeon/rv515.c81
-rw-r--r--drivers/gpu/drm/radeon/rv770.c11
20 files changed, 812 insertions, 745 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 233cbc0a2b59..fa11a04ae62e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1311,18 +1311,20 @@ void evergreen_mc_program(struct radeon_device *rdev)
1311 */ 1311 */
1312void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 1312void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1313{ 1313{
1314 struct radeon_cp *cp = &rdev->cp;
1315
1314 /* set to DX10/11 mode */ 1316 /* set to DX10/11 mode */
1315 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0)); 1317 radeon_ring_write(cp, PACKET3(PACKET3_MODE_CONTROL, 0));
1316 radeon_ring_write(rdev, 1); 1318 radeon_ring_write(cp, 1);
1317 /* FIXME: implement */ 1319 /* FIXME: implement */
1318 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1320 radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1319 radeon_ring_write(rdev, 1321 radeon_ring_write(cp,
1320#ifdef __BIG_ENDIAN 1322#ifdef __BIG_ENDIAN
1321 (2 << 0) | 1323 (2 << 0) |
1322#endif 1324#endif
1323 (ib->gpu_addr & 0xFFFFFFFC)); 1325 (ib->gpu_addr & 0xFFFFFFFC));
1324 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 1326 radeon_ring_write(cp, upper_32_bits(ib->gpu_addr) & 0xFF);
1325 radeon_ring_write(rdev, ib->length_dw); 1327 radeon_ring_write(cp, ib->length_dw);
1326} 1328}
1327 1329
1328 1330
@@ -1360,71 +1362,73 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1360 1362
1361static int evergreen_cp_start(struct radeon_device *rdev) 1363static int evergreen_cp_start(struct radeon_device *rdev)
1362{ 1364{
1365 struct radeon_cp *cp = &rdev->cp;
1363 int r, i; 1366 int r, i;
1364 uint32_t cp_me; 1367 uint32_t cp_me;
1365 1368
1366 r = radeon_ring_lock(rdev, 7); 1369 r = radeon_ring_lock(rdev, cp, 7);
1367 if (r) { 1370 if (r) {
1368 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1371 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1369 return r; 1372 return r;
1370 } 1373 }
1371 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1374 radeon_ring_write(cp, PACKET3(PACKET3_ME_INITIALIZE, 5));
1372 radeon_ring_write(rdev, 0x1); 1375 radeon_ring_write(cp, 0x1);
1373 radeon_ring_write(rdev, 0x0); 1376 radeon_ring_write(cp, 0x0);
1374 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1); 1377 radeon_ring_write(cp, rdev->config.evergreen.max_hw_contexts - 1);
1375 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1378 radeon_ring_write(cp, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1376 radeon_ring_write(rdev, 0); 1379 radeon_ring_write(cp, 0);
1377 radeon_ring_write(rdev, 0); 1380 radeon_ring_write(cp, 0);
1378 radeon_ring_unlock_commit(rdev); 1381 radeon_ring_unlock_commit(rdev, cp);
1379 1382
1380 cp_me = 0xff; 1383 cp_me = 0xff;
1381 WREG32(CP_ME_CNTL, cp_me); 1384 WREG32(CP_ME_CNTL, cp_me);
1382 1385
1383 r = radeon_ring_lock(rdev, evergreen_default_size + 19); 1386 r = radeon_ring_lock(rdev, cp, evergreen_default_size + 19);
1384 if (r) { 1387 if (r) {
1385 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1388 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1386 return r; 1389 return r;
1387 } 1390 }
1388 1391
1389 /* setup clear context state */ 1392 /* setup clear context state */
1390 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1393 radeon_ring_write(cp, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1391 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1394 radeon_ring_write(cp, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1392 1395
1393 for (i = 0; i < evergreen_default_size; i++) 1396 for (i = 0; i < evergreen_default_size; i++)
1394 radeon_ring_write(rdev, evergreen_default_state[i]); 1397 radeon_ring_write(cp, evergreen_default_state[i]);
1395 1398
1396 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1399 radeon_ring_write(cp, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1397 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); 1400 radeon_ring_write(cp, PACKET3_PREAMBLE_END_CLEAR_STATE);
1398 1401
1399 /* set clear context state */ 1402 /* set clear context state */
1400 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); 1403 radeon_ring_write(cp, PACKET3(PACKET3_CLEAR_STATE, 0));
1401 radeon_ring_write(rdev, 0); 1404 radeon_ring_write(cp, 0);
1402 1405
1403 /* SQ_VTX_BASE_VTX_LOC */ 1406 /* SQ_VTX_BASE_VTX_LOC */
1404 radeon_ring_write(rdev, 0xc0026f00); 1407 radeon_ring_write(cp, 0xc0026f00);
1405 radeon_ring_write(rdev, 0x00000000); 1408 radeon_ring_write(cp, 0x00000000);
1406 radeon_ring_write(rdev, 0x00000000); 1409 radeon_ring_write(cp, 0x00000000);
1407 radeon_ring_write(rdev, 0x00000000); 1410 radeon_ring_write(cp, 0x00000000);
1408 1411
1409 /* Clear consts */ 1412 /* Clear consts */
1410 radeon_ring_write(rdev, 0xc0036f00); 1413 radeon_ring_write(cp, 0xc0036f00);
1411 radeon_ring_write(rdev, 0x00000bc4); 1414 radeon_ring_write(cp, 0x00000bc4);
1412 radeon_ring_write(rdev, 0xffffffff); 1415 radeon_ring_write(cp, 0xffffffff);
1413 radeon_ring_write(rdev, 0xffffffff); 1416 radeon_ring_write(cp, 0xffffffff);
1414 radeon_ring_write(rdev, 0xffffffff); 1417 radeon_ring_write(cp, 0xffffffff);
1415 1418
1416 radeon_ring_write(rdev, 0xc0026900); 1419 radeon_ring_write(cp, 0xc0026900);
1417 radeon_ring_write(rdev, 0x00000316); 1420 radeon_ring_write(cp, 0x00000316);
1418 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1421 radeon_ring_write(cp, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1419 radeon_ring_write(rdev, 0x00000010); /* */ 1422 radeon_ring_write(cp, 0x00000010); /* */
1420 1423
1421 radeon_ring_unlock_commit(rdev); 1424 radeon_ring_unlock_commit(rdev, cp);
1422 1425
1423 return 0; 1426 return 0;
1424} 1427}
1425 1428
1426int evergreen_cp_resume(struct radeon_device *rdev) 1429int evergreen_cp_resume(struct radeon_device *rdev)
1427{ 1430{
1431 struct radeon_cp *cp = &rdev->cp;
1428 u32 tmp; 1432 u32 tmp;
1429 u32 rb_bufsz; 1433 u32 rb_bufsz;
1430 int r; 1434 int r;
@@ -1442,7 +1446,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
1442 RREG32(GRBM_SOFT_RESET); 1446 RREG32(GRBM_SOFT_RESET);
1443 1447
1444 /* Set ring buffer size */ 1448 /* Set ring buffer size */
1445 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 1449 rb_bufsz = drm_order(cp->ring_size / 8);
1446 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1450 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1447#ifdef __BIG_ENDIAN 1451#ifdef __BIG_ENDIAN
1448 tmp |= BUF_SWAP_32BIT; 1452 tmp |= BUF_SWAP_32BIT;
@@ -1456,8 +1460,8 @@ int evergreen_cp_resume(struct radeon_device *rdev)
1456 /* Initialize the ring buffer's read and write pointers */ 1460 /* Initialize the ring buffer's read and write pointers */
1457 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1461 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1458 WREG32(CP_RB_RPTR_WR, 0); 1462 WREG32(CP_RB_RPTR_WR, 0);
1459 rdev->cp.wptr = 0; 1463 cp->wptr = 0;
1460 WREG32(CP_RB_WPTR, rdev->cp.wptr); 1464 WREG32(CP_RB_WPTR, cp->wptr);
1461 1465
1462 /* set the wb address wether it's enabled or not */ 1466 /* set the wb address wether it's enabled or not */
1463 WREG32(CP_RB_RPTR_ADDR, 1467 WREG32(CP_RB_RPTR_ADDR,
@@ -1475,16 +1479,16 @@ int evergreen_cp_resume(struct radeon_device *rdev)
1475 mdelay(1); 1479 mdelay(1);
1476 WREG32(CP_RB_CNTL, tmp); 1480 WREG32(CP_RB_CNTL, tmp);
1477 1481
1478 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); 1482 WREG32(CP_RB_BASE, cp->gpu_addr >> 8);
1479 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 1483 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1480 1484
1481 rdev->cp.rptr = RREG32(CP_RB_RPTR); 1485 cp->rptr = RREG32(CP_RB_RPTR);
1482 1486
1483 evergreen_cp_start(rdev); 1487 evergreen_cp_start(rdev);
1484 rdev->cp.ready = true; 1488 cp->ready = true;
1485 r = radeon_ring_test(rdev); 1489 r = radeon_ring_test(rdev, cp);
1486 if (r) { 1490 if (r) {
1487 rdev->cp.ready = false; 1491 cp->ready = false;
1488 return r; 1492 return r;
1489 } 1493 }
1490 return 0; 1494 return 0;
@@ -2353,7 +2357,7 @@ int evergreen_mc_init(struct radeon_device *rdev)
2353 return 0; 2357 return 0;
2354} 2358}
2355 2359
2356bool evergreen_gpu_is_lockup(struct radeon_device *rdev) 2360bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
2357{ 2361{
2358 u32 srbm_status; 2362 u32 srbm_status;
2359 u32 grbm_status; 2363 u32 grbm_status;
@@ -2366,19 +2370,19 @@ bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
2366 grbm_status_se0 = RREG32(GRBM_STATUS_SE0); 2370 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2367 grbm_status_se1 = RREG32(GRBM_STATUS_SE1); 2371 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2368 if (!(grbm_status & GUI_ACTIVE)) { 2372 if (!(grbm_status & GUI_ACTIVE)) {
2369 r100_gpu_lockup_update(lockup, &rdev->cp); 2373 r100_gpu_lockup_update(lockup, cp);
2370 return false; 2374 return false;
2371 } 2375 }
2372 /* force CP activities */ 2376 /* force CP activities */
2373 r = radeon_ring_lock(rdev, 2); 2377 r = radeon_ring_lock(rdev, cp, 2);
2374 if (!r) { 2378 if (!r) {
2375 /* PACKET2 NOP */ 2379 /* PACKET2 NOP */
2376 radeon_ring_write(rdev, 0x80000000); 2380 radeon_ring_write(cp, 0x80000000);
2377 radeon_ring_write(rdev, 0x80000000); 2381 radeon_ring_write(cp, 0x80000000);
2378 radeon_ring_unlock_commit(rdev); 2382 radeon_ring_unlock_commit(rdev, cp);
2379 } 2383 }
2380 rdev->cp.rptr = RREG32(CP_RB_RPTR); 2384 cp->rptr = RREG32(CP_RB_RPTR);
2381 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); 2385 return r100_gpu_cp_is_lockup(rdev, lockup, cp);
2382} 2386}
2383 2387
2384static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 2388static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
@@ -3052,6 +3056,7 @@ restart_ih:
3052 3056
3053static int evergreen_startup(struct radeon_device *rdev) 3057static int evergreen_startup(struct radeon_device *rdev)
3054{ 3058{
3059 struct radeon_cp *cp = &rdev->cp;
3055 int r; 3060 int r;
3056 3061
3057 /* enable pcie gen2 link */ 3062 /* enable pcie gen2 link */
@@ -3115,7 +3120,7 @@ static int evergreen_startup(struct radeon_device *rdev)
3115 } 3120 }
3116 evergreen_irq_set(rdev); 3121 evergreen_irq_set(rdev);
3117 3122
3118 r = radeon_ring_init(rdev, rdev->cp.ring_size); 3123 r = radeon_ring_init(rdev, cp, cp->ring_size);
3119 if (r) 3124 if (r)
3120 return r; 3125 return r;
3121 r = evergreen_cp_load_microcode(rdev); 3126 r = evergreen_cp_load_microcode(rdev);
@@ -3150,7 +3155,7 @@ int evergreen_resume(struct radeon_device *rdev)
3150 return r; 3155 return r;
3151 } 3156 }
3152 3157
3153 r = r600_ib_test(rdev); 3158 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
3154 if (r) { 3159 if (r) {
3155 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 3160 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3156 return r; 3161 return r;
@@ -3162,9 +3167,11 @@ int evergreen_resume(struct radeon_device *rdev)
3162 3167
3163int evergreen_suspend(struct radeon_device *rdev) 3168int evergreen_suspend(struct radeon_device *rdev)
3164{ 3169{
3170 struct radeon_cp *cp = &rdev->cp;
3171
3165 /* FIXME: we should wait for ring to be empty */ 3172 /* FIXME: we should wait for ring to be empty */
3166 r700_cp_stop(rdev); 3173 r700_cp_stop(rdev);
3167 rdev->cp.ready = false; 3174 cp->ready = false;
3168 evergreen_irq_suspend(rdev); 3175 evergreen_irq_suspend(rdev);
3169 radeon_wb_disable(rdev); 3176 radeon_wb_disable(rdev);
3170 evergreen_pcie_gart_disable(rdev); 3177 evergreen_pcie_gart_disable(rdev);
@@ -3244,7 +3251,7 @@ int evergreen_init(struct radeon_device *rdev)
3244 return r; 3251 return r;
3245 3252
3246 rdev->cp.ring_obj = NULL; 3253 rdev->cp.ring_obj = NULL;
3247 r600_ring_init(rdev, 1024 * 1024); 3254 r600_ring_init(rdev, &rdev->cp, 1024 * 1024);
3248 3255
3249 rdev->ih.ring_obj = NULL; 3256 rdev->ih.ring_obj = NULL;
3250 r600_ih_ring_init(rdev, 64 * 1024); 3257 r600_ih_ring_init(rdev, 64 * 1024);
@@ -3270,7 +3277,7 @@ int evergreen_init(struct radeon_device *rdev)
3270 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 3277 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
3271 rdev->accel_working = false; 3278 rdev->accel_working = false;
3272 } 3279 }
3273 r = r600_ib_test(rdev); 3280 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
3274 if (r) { 3281 if (r) {
3275 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 3282 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3276 rdev->accel_working = false; 3283 rdev->accel_working = false;
diff --git a/drivers/gpu/drm/radeon/evergreen_blit_kms.c b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
index 914e5af84163..75d0a6f0a395 100644
--- a/drivers/gpu/drm/radeon/evergreen_blit_kms.c
+++ b/drivers/gpu/drm/radeon/evergreen_blit_kms.c
@@ -49,6 +49,7 @@ static void
49set_render_target(struct radeon_device *rdev, int format, 49set_render_target(struct radeon_device *rdev, int format,
50 int w, int h, u64 gpu_addr) 50 int w, int h, u64 gpu_addr)
51{ 51{
52 struct radeon_cp *cp = &rdev->cp;
52 u32 cb_color_info; 53 u32 cb_color_info;
53 int pitch, slice; 54 int pitch, slice;
54 55
@@ -62,23 +63,23 @@ set_render_target(struct radeon_device *rdev, int format,
62 pitch = (w / 8) - 1; 63 pitch = (w / 8) - 1;
63 slice = ((w * h) / 64) - 1; 64 slice = ((w * h) / 64) - 1;
64 65
65 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15)); 66 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 15));
66 radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2); 67 radeon_ring_write(cp, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2);
67 radeon_ring_write(rdev, gpu_addr >> 8); 68 radeon_ring_write(cp, gpu_addr >> 8);
68 radeon_ring_write(rdev, pitch); 69 radeon_ring_write(cp, pitch);
69 radeon_ring_write(rdev, slice); 70 radeon_ring_write(cp, slice);
70 radeon_ring_write(rdev, 0); 71 radeon_ring_write(cp, 0);
71 radeon_ring_write(rdev, cb_color_info); 72 radeon_ring_write(cp, cb_color_info);
72 radeon_ring_write(rdev, 0); 73 radeon_ring_write(cp, 0);
73 radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16)); 74 radeon_ring_write(cp, (w - 1) | ((h - 1) << 16));
74 radeon_ring_write(rdev, 0); 75 radeon_ring_write(cp, 0);
75 radeon_ring_write(rdev, 0); 76 radeon_ring_write(cp, 0);
76 radeon_ring_write(rdev, 0); 77 radeon_ring_write(cp, 0);
77 radeon_ring_write(rdev, 0); 78 radeon_ring_write(cp, 0);
78 radeon_ring_write(rdev, 0); 79 radeon_ring_write(cp, 0);
79 radeon_ring_write(rdev, 0); 80 radeon_ring_write(cp, 0);
80 radeon_ring_write(rdev, 0); 81 radeon_ring_write(cp, 0);
81 radeon_ring_write(rdev, 0); 82 radeon_ring_write(cp, 0);
82} 83}
83 84
84/* emits 5dw */ 85/* emits 5dw */
@@ -87,6 +88,7 @@ cp_set_surface_sync(struct radeon_device *rdev,
87 u32 sync_type, u32 size, 88 u32 sync_type, u32 size,
88 u64 mc_addr) 89 u64 mc_addr)
89{ 90{
91 struct radeon_cp *cp = &rdev->cp;
90 u32 cp_coher_size; 92 u32 cp_coher_size;
91 93
92 if (size == 0xffffffff) 94 if (size == 0xffffffff)
@@ -99,39 +101,40 @@ cp_set_surface_sync(struct radeon_device *rdev,
99 * to the RB directly. For IBs, the CP programs this as part of the 101 * to the RB directly. For IBs, the CP programs this as part of the
100 * surface_sync packet. 102 * surface_sync packet.
101 */ 103 */
102 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 104 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
103 radeon_ring_write(rdev, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2); 105 radeon_ring_write(cp, (0x85e8 - PACKET3_SET_CONFIG_REG_START) >> 2);
104 radeon_ring_write(rdev, 0); /* CP_COHER_CNTL2 */ 106 radeon_ring_write(cp, 0); /* CP_COHER_CNTL2 */
105 } 107 }
106 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); 108 radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
107 radeon_ring_write(rdev, sync_type); 109 radeon_ring_write(cp, sync_type);
108 radeon_ring_write(rdev, cp_coher_size); 110 radeon_ring_write(cp, cp_coher_size);
109 radeon_ring_write(rdev, mc_addr >> 8); 111 radeon_ring_write(cp, mc_addr >> 8);
110 radeon_ring_write(rdev, 10); /* poll interval */ 112 radeon_ring_write(cp, 10); /* poll interval */
111} 113}
112 114
113/* emits 11dw + 1 surface sync = 16dw */ 115/* emits 11dw + 1 surface sync = 16dw */
114static void 116static void
115set_shaders(struct radeon_device *rdev) 117set_shaders(struct radeon_device *rdev)
116{ 118{
119 struct radeon_cp *cp = &rdev->cp;
117 u64 gpu_addr; 120 u64 gpu_addr;
118 121
119 /* VS */ 122 /* VS */
120 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 123 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
121 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3)); 124 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 3));
122 radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2); 125 radeon_ring_write(cp, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2);
123 radeon_ring_write(rdev, gpu_addr >> 8); 126 radeon_ring_write(cp, gpu_addr >> 8);
124 radeon_ring_write(rdev, 2); 127 radeon_ring_write(cp, 2);
125 radeon_ring_write(rdev, 0); 128 radeon_ring_write(cp, 0);
126 129
127 /* PS */ 130 /* PS */
128 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; 131 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
129 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4)); 132 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 4));
130 radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2); 133 radeon_ring_write(cp, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2);
131 radeon_ring_write(rdev, gpu_addr >> 8); 134 radeon_ring_write(cp, gpu_addr >> 8);
132 radeon_ring_write(rdev, 1); 135 radeon_ring_write(cp, 1);
133 radeon_ring_write(rdev, 0); 136 radeon_ring_write(cp, 0);
134 radeon_ring_write(rdev, 2); 137 radeon_ring_write(cp, 2);
135 138
136 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 139 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
137 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); 140 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
@@ -141,6 +144,7 @@ set_shaders(struct radeon_device *rdev)
141static void 144static void
142set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) 145set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
143{ 146{
147 struct radeon_cp *cp = &rdev->cp;
144 u32 sq_vtx_constant_word2, sq_vtx_constant_word3; 148 u32 sq_vtx_constant_word2, sq_vtx_constant_word3;
145 149
146 /* high addr, stride */ 150 /* high addr, stride */
@@ -155,16 +159,16 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
155 SQ_VTCX_SEL_Z(SQ_SEL_Z) | 159 SQ_VTCX_SEL_Z(SQ_SEL_Z) |
156 SQ_VTCX_SEL_W(SQ_SEL_W); 160 SQ_VTCX_SEL_W(SQ_SEL_W);
157 161
158 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); 162 radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 8));
159 radeon_ring_write(rdev, 0x580); 163 radeon_ring_write(cp, 0x580);
160 radeon_ring_write(rdev, gpu_addr & 0xffffffff); 164 radeon_ring_write(cp, gpu_addr & 0xffffffff);
161 radeon_ring_write(rdev, 48 - 1); /* size */ 165 radeon_ring_write(cp, 48 - 1); /* size */
162 radeon_ring_write(rdev, sq_vtx_constant_word2); 166 radeon_ring_write(cp, sq_vtx_constant_word2);
163 radeon_ring_write(rdev, sq_vtx_constant_word3); 167 radeon_ring_write(cp, sq_vtx_constant_word3);
164 radeon_ring_write(rdev, 0); 168 radeon_ring_write(cp, 0);
165 radeon_ring_write(rdev, 0); 169 radeon_ring_write(cp, 0);
166 radeon_ring_write(rdev, 0); 170 radeon_ring_write(cp, 0);
167 radeon_ring_write(rdev, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER)); 171 radeon_ring_write(cp, S__SQ_CONSTANT_TYPE(SQ_TEX_VTX_VALID_BUFFER));
168 172
169 if ((rdev->family == CHIP_CEDAR) || 173 if ((rdev->family == CHIP_CEDAR) ||
170 (rdev->family == CHIP_PALM) || 174 (rdev->family == CHIP_PALM) ||
@@ -185,6 +189,7 @@ set_tex_resource(struct radeon_device *rdev,
185 int format, int w, int h, int pitch, 189 int format, int w, int h, int pitch,
186 u64 gpu_addr, u32 size) 190 u64 gpu_addr, u32 size)
187{ 191{
192 struct radeon_cp *cp = &rdev->cp;
188 u32 sq_tex_resource_word0, sq_tex_resource_word1; 193 u32 sq_tex_resource_word0, sq_tex_resource_word1;
189 u32 sq_tex_resource_word4, sq_tex_resource_word7; 194 u32 sq_tex_resource_word4, sq_tex_resource_word7;
190 195
@@ -208,16 +213,16 @@ set_tex_resource(struct radeon_device *rdev,
208 cp_set_surface_sync(rdev, 213 cp_set_surface_sync(rdev,
209 PACKET3_TC_ACTION_ENA, size, gpu_addr); 214 PACKET3_TC_ACTION_ENA, size, gpu_addr);
210 215
211 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); 216 radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 8));
212 radeon_ring_write(rdev, 0); 217 radeon_ring_write(cp, 0);
213 radeon_ring_write(rdev, sq_tex_resource_word0); 218 radeon_ring_write(cp, sq_tex_resource_word0);
214 radeon_ring_write(rdev, sq_tex_resource_word1); 219 radeon_ring_write(cp, sq_tex_resource_word1);
215 radeon_ring_write(rdev, gpu_addr >> 8); 220 radeon_ring_write(cp, gpu_addr >> 8);
216 radeon_ring_write(rdev, gpu_addr >> 8); 221 radeon_ring_write(cp, gpu_addr >> 8);
217 radeon_ring_write(rdev, sq_tex_resource_word4); 222 radeon_ring_write(cp, sq_tex_resource_word4);
218 radeon_ring_write(rdev, 0); 223 radeon_ring_write(cp, 0);
219 radeon_ring_write(rdev, 0); 224 radeon_ring_write(cp, 0);
220 radeon_ring_write(rdev, sq_tex_resource_word7); 225 radeon_ring_write(cp, sq_tex_resource_word7);
221} 226}
222 227
223/* emits 12 */ 228/* emits 12 */
@@ -225,6 +230,7 @@ static void
225set_scissors(struct radeon_device *rdev, int x1, int y1, 230set_scissors(struct radeon_device *rdev, int x1, int y1,
226 int x2, int y2) 231 int x2, int y2)
227{ 232{
233 struct radeon_cp *cp = &rdev->cp;
228 /* workaround some hw bugs */ 234 /* workaround some hw bugs */
229 if (x2 == 0) 235 if (x2 == 0)
230 x1 = 1; 236 x1 = 1;
@@ -235,43 +241,44 @@ set_scissors(struct radeon_device *rdev, int x1, int y1,
235 x2 = 2; 241 x2 = 2;
236 } 242 }
237 243
238 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 244 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
239 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); 245 radeon_ring_write(cp, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
240 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); 246 radeon_ring_write(cp, (x1 << 0) | (y1 << 16));
241 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); 247 radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
242 248
243 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 249 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
244 radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); 250 radeon_ring_write(cp, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
245 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); 251 radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
246 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); 252 radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
247 253
248 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 254 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
249 radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); 255 radeon_ring_write(cp, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2);
250 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); 256 radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
251 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); 257 radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
252} 258}
253 259
254/* emits 10 */ 260/* emits 10 */
255static void 261static void
256draw_auto(struct radeon_device *rdev) 262draw_auto(struct radeon_device *rdev)
257{ 263{
258 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 264 struct radeon_cp *cp = &rdev->cp;
259 radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2); 265 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
260 radeon_ring_write(rdev, DI_PT_RECTLIST); 266 radeon_ring_write(cp, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2);
267 radeon_ring_write(cp, DI_PT_RECTLIST);
261 268
262 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); 269 radeon_ring_write(cp, PACKET3(PACKET3_INDEX_TYPE, 0));
263 radeon_ring_write(rdev, 270 radeon_ring_write(cp,
264#ifdef __BIG_ENDIAN 271#ifdef __BIG_ENDIAN
265 (2 << 2) | 272 (2 << 2) |
266#endif 273#endif
267 DI_INDEX_SIZE_16_BIT); 274 DI_INDEX_SIZE_16_BIT);
268 275
269 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); 276 radeon_ring_write(cp, PACKET3(PACKET3_NUM_INSTANCES, 0));
270 radeon_ring_write(rdev, 1); 277 radeon_ring_write(cp, 1);
271 278
272 radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); 279 radeon_ring_write(cp, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
273 radeon_ring_write(rdev, 3); 280 radeon_ring_write(cp, 3);
274 radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); 281 radeon_ring_write(cp, DI_SRC_SEL_AUTO_INDEX);
275 282
276} 283}
277 284
@@ -279,6 +286,7 @@ draw_auto(struct radeon_device *rdev)
279static void 286static void
280set_default_state(struct radeon_device *rdev) 287set_default_state(struct radeon_device *rdev)
281{ 288{
289 struct radeon_cp *cp = &rdev->cp;
282 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; 290 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3;
283 u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; 291 u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2;
284 u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; 292 u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3;
@@ -292,8 +300,8 @@ set_default_state(struct radeon_device *rdev)
292 int dwords; 300 int dwords;
293 301
294 /* set clear context state */ 302 /* set clear context state */
295 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); 303 radeon_ring_write(cp, PACKET3(PACKET3_CLEAR_STATE, 0));
296 radeon_ring_write(rdev, 0); 304 radeon_ring_write(cp, 0);
297 305
298 if (rdev->family < CHIP_CAYMAN) { 306 if (rdev->family < CHIP_CAYMAN) {
299 switch (rdev->family) { 307 switch (rdev->family) {
@@ -550,60 +558,60 @@ set_default_state(struct radeon_device *rdev)
550 NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); 558 NUM_LS_STACK_ENTRIES(num_ls_stack_entries));
551 559
552 /* disable dyn gprs */ 560 /* disable dyn gprs */
553 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 561 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
554 radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); 562 radeon_ring_write(cp, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2);
555 radeon_ring_write(rdev, 0); 563 radeon_ring_write(cp, 0);
556 564
557 /* setup LDS */ 565 /* setup LDS */
558 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 566 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
559 radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2); 567 radeon_ring_write(cp, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2);
560 radeon_ring_write(rdev, 0x10001000); 568 radeon_ring_write(cp, 0x10001000);
561 569
562 /* SQ config */ 570 /* SQ config */
563 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); 571 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 11));
564 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); 572 radeon_ring_write(cp, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2);
565 radeon_ring_write(rdev, sq_config); 573 radeon_ring_write(cp, sq_config);
566 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); 574 radeon_ring_write(cp, sq_gpr_resource_mgmt_1);
567 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); 575 radeon_ring_write(cp, sq_gpr_resource_mgmt_2);
568 radeon_ring_write(rdev, sq_gpr_resource_mgmt_3); 576 radeon_ring_write(cp, sq_gpr_resource_mgmt_3);
569 radeon_ring_write(rdev, 0); 577 radeon_ring_write(cp, 0);
570 radeon_ring_write(rdev, 0); 578 radeon_ring_write(cp, 0);
571 radeon_ring_write(rdev, sq_thread_resource_mgmt); 579 radeon_ring_write(cp, sq_thread_resource_mgmt);
572 radeon_ring_write(rdev, sq_thread_resource_mgmt_2); 580 radeon_ring_write(cp, sq_thread_resource_mgmt_2);
573 radeon_ring_write(rdev, sq_stack_resource_mgmt_1); 581 radeon_ring_write(cp, sq_stack_resource_mgmt_1);
574 radeon_ring_write(rdev, sq_stack_resource_mgmt_2); 582 radeon_ring_write(cp, sq_stack_resource_mgmt_2);
575 radeon_ring_write(rdev, sq_stack_resource_mgmt_3); 583 radeon_ring_write(cp, sq_stack_resource_mgmt_3);
576 } 584 }
577 585
578 /* CONTEXT_CONTROL */ 586 /* CONTEXT_CONTROL */
579 radeon_ring_write(rdev, 0xc0012800); 587 radeon_ring_write(cp, 0xc0012800);
580 radeon_ring_write(rdev, 0x80000000); 588 radeon_ring_write(cp, 0x80000000);
581 radeon_ring_write(rdev, 0x80000000); 589 radeon_ring_write(cp, 0x80000000);
582 590
583 /* SQ_VTX_BASE_VTX_LOC */ 591 /* SQ_VTX_BASE_VTX_LOC */
584 radeon_ring_write(rdev, 0xc0026f00); 592 radeon_ring_write(cp, 0xc0026f00);
585 radeon_ring_write(rdev, 0x00000000); 593 radeon_ring_write(cp, 0x00000000);
586 radeon_ring_write(rdev, 0x00000000); 594 radeon_ring_write(cp, 0x00000000);
587 radeon_ring_write(rdev, 0x00000000); 595 radeon_ring_write(cp, 0x00000000);
588 596
589 /* SET_SAMPLER */ 597 /* SET_SAMPLER */
590 radeon_ring_write(rdev, 0xc0036e00); 598 radeon_ring_write(cp, 0xc0036e00);
591 radeon_ring_write(rdev, 0x00000000); 599 radeon_ring_write(cp, 0x00000000);
592 radeon_ring_write(rdev, 0x00000012); 600 radeon_ring_write(cp, 0x00000012);
593 radeon_ring_write(rdev, 0x00000000); 601 radeon_ring_write(cp, 0x00000000);
594 radeon_ring_write(rdev, 0x00000000); 602 radeon_ring_write(cp, 0x00000000);
595 603
596 /* set to DX10/11 mode */ 604 /* set to DX10/11 mode */
597 radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0)); 605 radeon_ring_write(cp, PACKET3(PACKET3_MODE_CONTROL, 0));
598 radeon_ring_write(rdev, 1); 606 radeon_ring_write(cp, 1);
599 607
600 /* emit an IB pointing at default state */ 608 /* emit an IB pointing at default state */
601 dwords = ALIGN(rdev->r600_blit.state_len, 0x10); 609 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
602 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; 610 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
603 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 611 radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
604 radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); 612 radeon_ring_write(cp, gpu_addr & 0xFFFFFFFC);
605 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); 613 radeon_ring_write(cp, upper_32_bits(gpu_addr) & 0xFF);
606 radeon_ring_write(rdev, dwords); 614 radeon_ring_write(cp, dwords);
607 615
608} 616}
609 617
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index ef749950db08..636b8c5f5797 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1049,63 +1049,64 @@ static int cayman_cp_load_microcode(struct radeon_device *rdev)
1049 1049
1050static int cayman_cp_start(struct radeon_device *rdev) 1050static int cayman_cp_start(struct radeon_device *rdev)
1051{ 1051{
1052 struct radeon_cp *cp = &rdev->cp;
1052 int r, i; 1053 int r, i;
1053 1054
1054 r = radeon_ring_lock(rdev, 7); 1055 r = radeon_ring_lock(rdev, cp, 7);
1055 if (r) { 1056 if (r) {
1056 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1057 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1057 return r; 1058 return r;
1058 } 1059 }
1059 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 1060 radeon_ring_write(cp, PACKET3(PACKET3_ME_INITIALIZE, 5));
1060 radeon_ring_write(rdev, 0x1); 1061 radeon_ring_write(cp, 0x1);
1061 radeon_ring_write(rdev, 0x0); 1062 radeon_ring_write(cp, 0x0);
1062 radeon_ring_write(rdev, rdev->config.cayman.max_hw_contexts - 1); 1063 radeon_ring_write(cp, rdev->config.cayman.max_hw_contexts - 1);
1063 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 1064 radeon_ring_write(cp, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1064 radeon_ring_write(rdev, 0); 1065 radeon_ring_write(cp, 0);
1065 radeon_ring_write(rdev, 0); 1066 radeon_ring_write(cp, 0);
1066 radeon_ring_unlock_commit(rdev); 1067 radeon_ring_unlock_commit(rdev, cp);
1067 1068
1068 cayman_cp_enable(rdev, true); 1069 cayman_cp_enable(rdev, true);
1069 1070
1070 r = radeon_ring_lock(rdev, cayman_default_size + 19); 1071 r = radeon_ring_lock(rdev, cp, cayman_default_size + 19);
1071 if (r) { 1072 if (r) {
1072 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 1073 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1073 return r; 1074 return r;
1074 } 1075 }
1075 1076
1076 /* setup clear context state */ 1077 /* setup clear context state */
1077 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1078 radeon_ring_write(cp, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1078 radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE); 1079 radeon_ring_write(cp, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1079 1080
1080 for (i = 0; i < cayman_default_size; i++) 1081 for (i = 0; i < cayman_default_size; i++)
1081 radeon_ring_write(rdev, cayman_default_state[i]); 1082 radeon_ring_write(cp, cayman_default_state[i]);
1082 1083
1083 radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0)); 1084 radeon_ring_write(cp, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1084 radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE); 1085 radeon_ring_write(cp, PACKET3_PREAMBLE_END_CLEAR_STATE);
1085 1086
1086 /* set clear context state */ 1087 /* set clear context state */
1087 radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); 1088 radeon_ring_write(cp, PACKET3(PACKET3_CLEAR_STATE, 0));
1088 radeon_ring_write(rdev, 0); 1089 radeon_ring_write(cp, 0);
1089 1090
1090 /* SQ_VTX_BASE_VTX_LOC */ 1091 /* SQ_VTX_BASE_VTX_LOC */
1091 radeon_ring_write(rdev, 0xc0026f00); 1092 radeon_ring_write(cp, 0xc0026f00);
1092 radeon_ring_write(rdev, 0x00000000); 1093 radeon_ring_write(cp, 0x00000000);
1093 radeon_ring_write(rdev, 0x00000000); 1094 radeon_ring_write(cp, 0x00000000);
1094 radeon_ring_write(rdev, 0x00000000); 1095 radeon_ring_write(cp, 0x00000000);
1095 1096
1096 /* Clear consts */ 1097 /* Clear consts */
1097 radeon_ring_write(rdev, 0xc0036f00); 1098 radeon_ring_write(cp, 0xc0036f00);
1098 radeon_ring_write(rdev, 0x00000bc4); 1099 radeon_ring_write(cp, 0x00000bc4);
1099 radeon_ring_write(rdev, 0xffffffff); 1100 radeon_ring_write(cp, 0xffffffff);
1100 radeon_ring_write(rdev, 0xffffffff); 1101 radeon_ring_write(cp, 0xffffffff);
1101 radeon_ring_write(rdev, 0xffffffff); 1102 radeon_ring_write(cp, 0xffffffff);
1102 1103
1103 radeon_ring_write(rdev, 0xc0026900); 1104 radeon_ring_write(cp, 0xc0026900);
1104 radeon_ring_write(rdev, 0x00000316); 1105 radeon_ring_write(cp, 0x00000316);
1105 radeon_ring_write(rdev, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */ 1106 radeon_ring_write(cp, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1106 radeon_ring_write(rdev, 0x00000010); /* */ 1107 radeon_ring_write(cp, 0x00000010); /* */
1107 1108
1108 radeon_ring_unlock_commit(rdev); 1109 radeon_ring_unlock_commit(rdev, cp);
1109 1110
1110 /* XXX init other rings */ 1111 /* XXX init other rings */
1111 1112
@@ -1115,11 +1116,12 @@ static int cayman_cp_start(struct radeon_device *rdev)
1115static void cayman_cp_fini(struct radeon_device *rdev) 1116static void cayman_cp_fini(struct radeon_device *rdev)
1116{ 1117{
1117 cayman_cp_enable(rdev, false); 1118 cayman_cp_enable(rdev, false);
1118 radeon_ring_fini(rdev); 1119 radeon_ring_fini(rdev, &rdev->cp);
1119} 1120}
1120 1121
1121int cayman_cp_resume(struct radeon_device *rdev) 1122int cayman_cp_resume(struct radeon_device *rdev)
1122{ 1123{
1124 struct radeon_cp *cp;
1123 u32 tmp; 1125 u32 tmp;
1124 u32 rb_bufsz; 1126 u32 rb_bufsz;
1125 int r; 1127 int r;
@@ -1145,7 +1147,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
1145 1147
1146 /* ring 0 - compute and gfx */ 1148 /* ring 0 - compute and gfx */
1147 /* Set ring buffer size */ 1149 /* Set ring buffer size */
1148 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 1150 cp = &rdev->cp;
1151 rb_bufsz = drm_order(cp->ring_size / 8);
1149 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1152 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1150#ifdef __BIG_ENDIAN 1153#ifdef __BIG_ENDIAN
1151 tmp |= BUF_SWAP_32BIT; 1154 tmp |= BUF_SWAP_32BIT;
@@ -1154,8 +1157,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
1154 1157
1155 /* Initialize the ring buffer's read and write pointers */ 1158 /* Initialize the ring buffer's read and write pointers */
1156 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); 1159 WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
1157 rdev->cp.wptr = 0; 1160 cp->wptr = 0;
1158 WREG32(CP_RB0_WPTR, rdev->cp.wptr); 1161 WREG32(CP_RB0_WPTR, cp->wptr);
1159 1162
1160 /* set the wb address wether it's enabled or not */ 1163 /* set the wb address wether it's enabled or not */
1161 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 1164 WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1172,13 +1175,14 @@ int cayman_cp_resume(struct radeon_device *rdev)
1172 mdelay(1); 1175 mdelay(1);
1173 WREG32(CP_RB0_CNTL, tmp); 1176 WREG32(CP_RB0_CNTL, tmp);
1174 1177
1175 WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); 1178 WREG32(CP_RB0_BASE, cp->gpu_addr >> 8);
1176 1179
1177 rdev->cp.rptr = RREG32(CP_RB0_RPTR); 1180 cp->rptr = RREG32(CP_RB0_RPTR);
1178 1181
1179 /* ring1 - compute only */ 1182 /* ring1 - compute only */
1180 /* Set ring buffer size */ 1183 /* Set ring buffer size */
1181 rb_bufsz = drm_order(rdev->cp1.ring_size / 8); 1184 cp = &rdev->cp1;
1185 rb_bufsz = drm_order(cp->ring_size / 8);
1182 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1186 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1183#ifdef __BIG_ENDIAN 1187#ifdef __BIG_ENDIAN
1184 tmp |= BUF_SWAP_32BIT; 1188 tmp |= BUF_SWAP_32BIT;
@@ -1187,8 +1191,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
1187 1191
1188 /* Initialize the ring buffer's read and write pointers */ 1192 /* Initialize the ring buffer's read and write pointers */
1189 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); 1193 WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
1190 rdev->cp1.wptr = 0; 1194 cp->wptr = 0;
1191 WREG32(CP_RB1_WPTR, rdev->cp1.wptr); 1195 WREG32(CP_RB1_WPTR, cp->wptr);
1192 1196
1193 /* set the wb address wether it's enabled or not */ 1197 /* set the wb address wether it's enabled or not */
1194 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); 1198 WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1197,13 +1201,14 @@ int cayman_cp_resume(struct radeon_device *rdev)
1197 mdelay(1); 1201 mdelay(1);
1198 WREG32(CP_RB1_CNTL, tmp); 1202 WREG32(CP_RB1_CNTL, tmp);
1199 1203
1200 WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); 1204 WREG32(CP_RB1_BASE, cp->gpu_addr >> 8);
1201 1205
1202 rdev->cp1.rptr = RREG32(CP_RB1_RPTR); 1206 cp->rptr = RREG32(CP_RB1_RPTR);
1203 1207
1204 /* ring2 - compute only */ 1208 /* ring2 - compute only */
1205 /* Set ring buffer size */ 1209 /* Set ring buffer size */
1206 rb_bufsz = drm_order(rdev->cp2.ring_size / 8); 1210 cp = &rdev->cp2;
1211 rb_bufsz = drm_order(cp->ring_size / 8);
1207 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 1212 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1208#ifdef __BIG_ENDIAN 1213#ifdef __BIG_ENDIAN
1209 tmp |= BUF_SWAP_32BIT; 1214 tmp |= BUF_SWAP_32BIT;
@@ -1212,8 +1217,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
1212 1217
1213 /* Initialize the ring buffer's read and write pointers */ 1218 /* Initialize the ring buffer's read and write pointers */
1214 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); 1219 WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
1215 rdev->cp2.wptr = 0; 1220 cp->wptr = 0;
1216 WREG32(CP_RB2_WPTR, rdev->cp2.wptr); 1221 WREG32(CP_RB2_WPTR, cp->wptr);
1217 1222
1218 /* set the wb address wether it's enabled or not */ 1223 /* set the wb address wether it's enabled or not */
1219 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); 1224 WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1222,9 +1227,9 @@ int cayman_cp_resume(struct radeon_device *rdev)
1222 mdelay(1); 1227 mdelay(1);
1223 WREG32(CP_RB2_CNTL, tmp); 1228 WREG32(CP_RB2_CNTL, tmp);
1224 1229
1225 WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); 1230 WREG32(CP_RB2_BASE, cp->gpu_addr >> 8);
1226 1231
1227 rdev->cp2.rptr = RREG32(CP_RB2_RPTR); 1232 cp->rptr = RREG32(CP_RB2_RPTR);
1228 1233
1229 /* start the rings */ 1234 /* start the rings */
1230 cayman_cp_start(rdev); 1235 cayman_cp_start(rdev);
@@ -1232,7 +1237,7 @@ int cayman_cp_resume(struct radeon_device *rdev)
1232 rdev->cp1.ready = true; 1237 rdev->cp1.ready = true;
1233 rdev->cp2.ready = true; 1238 rdev->cp2.ready = true;
1234 /* this only test cp0 */ 1239 /* this only test cp0 */
1235 r = radeon_ring_test(rdev); 1240 r = radeon_ring_test(rdev, &rdev->cp);
1236 if (r) { 1241 if (r) {
1237 rdev->cp.ready = false; 1242 rdev->cp.ready = false;
1238 rdev->cp1.ready = false; 1243 rdev->cp1.ready = false;
@@ -1243,7 +1248,7 @@ int cayman_cp_resume(struct radeon_device *rdev)
1243 return 0; 1248 return 0;
1244} 1249}
1245 1250
1246bool cayman_gpu_is_lockup(struct radeon_device *rdev) 1251bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
1247{ 1252{
1248 u32 srbm_status; 1253 u32 srbm_status;
1249 u32 grbm_status; 1254 u32 grbm_status;
@@ -1256,20 +1261,20 @@ bool cayman_gpu_is_lockup(struct radeon_device *rdev)
1256 grbm_status_se0 = RREG32(GRBM_STATUS_SE0); 1261 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
1257 grbm_status_se1 = RREG32(GRBM_STATUS_SE1); 1262 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
1258 if (!(grbm_status & GUI_ACTIVE)) { 1263 if (!(grbm_status & GUI_ACTIVE)) {
1259 r100_gpu_lockup_update(lockup, &rdev->cp); 1264 r100_gpu_lockup_update(lockup, cp);
1260 return false; 1265 return false;
1261 } 1266 }
1262 /* force CP activities */ 1267 /* force CP activities */
1263 r = radeon_ring_lock(rdev, 2); 1268 r = radeon_ring_lock(rdev, cp, 2);
1264 if (!r) { 1269 if (!r) {
1265 /* PACKET2 NOP */ 1270 /* PACKET2 NOP */
1266 radeon_ring_write(rdev, 0x80000000); 1271 radeon_ring_write(cp, 0x80000000);
1267 radeon_ring_write(rdev, 0x80000000); 1272 radeon_ring_write(cp, 0x80000000);
1268 radeon_ring_unlock_commit(rdev); 1273 radeon_ring_unlock_commit(rdev, cp);
1269 } 1274 }
1270 /* XXX deal with CP0,1,2 */ 1275 /* XXX deal with CP0,1,2 */
1271 rdev->cp.rptr = RREG32(CP_RB0_RPTR); 1276 cp->rptr = RREG32(CP_RB0_RPTR);
1272 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); 1277 return r100_gpu_cp_is_lockup(rdev, lockup, cp);
1273} 1278}
1274 1279
1275static int cayman_gpu_soft_reset(struct radeon_device *rdev) 1280static int cayman_gpu_soft_reset(struct radeon_device *rdev)
@@ -1338,6 +1343,7 @@ int cayman_asic_reset(struct radeon_device *rdev)
1338 1343
1339static int cayman_startup(struct radeon_device *rdev) 1344static int cayman_startup(struct radeon_device *rdev)
1340{ 1345{
1346 struct radeon_cp *cp = &rdev->cp;
1341 int r; 1347 int r;
1342 1348
1343 /* enable pcie gen2 link */ 1349 /* enable pcie gen2 link */
@@ -1387,7 +1393,7 @@ static int cayman_startup(struct radeon_device *rdev)
1387 } 1393 }
1388 evergreen_irq_set(rdev); 1394 evergreen_irq_set(rdev);
1389 1395
1390 r = radeon_ring_init(rdev, rdev->cp.ring_size); 1396 r = radeon_ring_init(rdev, cp, cp->ring_size);
1391 if (r) 1397 if (r)
1392 return r; 1398 return r;
1393 r = cayman_cp_load_microcode(rdev); 1399 r = cayman_cp_load_microcode(rdev);
@@ -1417,7 +1423,7 @@ int cayman_resume(struct radeon_device *rdev)
1417 return r; 1423 return r;
1418 } 1424 }
1419 1425
1420 r = r600_ib_test(rdev); 1426 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
1421 if (r) { 1427 if (r) {
1422 DRM_ERROR("radeon: failled testing IB (%d).\n", r); 1428 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1423 return r; 1429 return r;
@@ -1448,6 +1454,7 @@ int cayman_suspend(struct radeon_device *rdev)
1448 */ 1454 */
1449int cayman_init(struct radeon_device *rdev) 1455int cayman_init(struct radeon_device *rdev)
1450{ 1456{
1457 struct radeon_cp *cp = &rdev->cp;
1451 int r; 1458 int r;
1452 1459
1453 /* This don't do much */ 1460 /* This don't do much */
@@ -1500,8 +1507,8 @@ int cayman_init(struct radeon_device *rdev)
1500 if (r) 1507 if (r)
1501 return r; 1508 return r;
1502 1509
1503 rdev->cp.ring_obj = NULL; 1510 cp->ring_obj = NULL;
1504 r600_ring_init(rdev, 1024 * 1024); 1511 r600_ring_init(rdev, cp, 1024 * 1024);
1505 1512
1506 rdev->ih.ring_obj = NULL; 1513 rdev->ih.ring_obj = NULL;
1507 r600_ih_ring_init(rdev, 64 * 1024); 1514 r600_ih_ring_init(rdev, 64 * 1024);
@@ -1527,7 +1534,7 @@ int cayman_init(struct radeon_device *rdev)
1527 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r); 1534 DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
1528 rdev->accel_working = false; 1535 rdev->accel_working = false;
1529 } 1536 }
1530 r = r600_ib_test(rdev); 1537 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
1531 if (r) { 1538 if (r) {
1532 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 1539 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1533 rdev->accel_working = false; 1540 rdev->accel_working = false;
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 2f18163e5e32..271cee7f817c 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -811,30 +811,33 @@ u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
811void r100_fence_ring_emit(struct radeon_device *rdev, 811void r100_fence_ring_emit(struct radeon_device *rdev,
812 struct radeon_fence *fence) 812 struct radeon_fence *fence)
813{ 813{
814 struct radeon_cp *cp = &rdev->cp;
815
814 /* We have to make sure that caches are flushed before 816 /* We have to make sure that caches are flushed before
815 * CPU might read something from VRAM. */ 817 * CPU might read something from VRAM. */
816 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0)); 818 radeon_ring_write(cp, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
817 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL); 819 radeon_ring_write(cp, RADEON_RB3D_DC_FLUSH_ALL);
818 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0)); 820 radeon_ring_write(cp, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
819 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL); 821 radeon_ring_write(cp, RADEON_RB3D_ZC_FLUSH_ALL);
820 /* Wait until IDLE & CLEAN */ 822 /* Wait until IDLE & CLEAN */
821 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 823 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
822 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN); 824 radeon_ring_write(cp, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
823 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 825 radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
824 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl | 826 radeon_ring_write(cp, rdev->config.r100.hdp_cntl |
825 RADEON_HDP_READ_BUFFER_INVALIDATE); 827 RADEON_HDP_READ_BUFFER_INVALIDATE);
826 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 828 radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
827 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl); 829 radeon_ring_write(cp, rdev->config.r100.hdp_cntl);
828 /* Emit fence sequence & fire IRQ */ 830 /* Emit fence sequence & fire IRQ */
829 radeon_ring_write(rdev, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 831 radeon_ring_write(cp, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
830 radeon_ring_write(rdev, fence->seq); 832 radeon_ring_write(cp, fence->seq);
831 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 833 radeon_ring_write(cp, PACKET0(RADEON_GEN_INT_STATUS, 0));
832 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 834 radeon_ring_write(cp, RADEON_SW_INT_FIRE);
833} 835}
834 836
835void r100_semaphore_ring_emit(struct radeon_device *rdev, 837void r100_semaphore_ring_emit(struct radeon_device *rdev,
838 struct radeon_cp *cp,
836 struct radeon_semaphore *semaphore, 839 struct radeon_semaphore *semaphore,
837 unsigned ring, bool emit_wait) 840 bool emit_wait)
838{ 841{
839 /* Unused on older asics, since we don't have semaphores or multiple rings */ 842 /* Unused on older asics, since we don't have semaphores or multiple rings */
840 BUG(); 843 BUG();
@@ -846,6 +849,7 @@ int r100_copy_blit(struct radeon_device *rdev,
846 unsigned num_gpu_pages, 849 unsigned num_gpu_pages,
847 struct radeon_fence *fence) 850 struct radeon_fence *fence)
848{ 851{
852 struct radeon_cp *cp = &rdev->cp;
849 uint32_t cur_pages; 853 uint32_t cur_pages;
850 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE; 854 uint32_t stride_bytes = RADEON_GPU_PAGE_SIZE;
851 uint32_t pitch; 855 uint32_t pitch;
@@ -863,7 +867,7 @@ int r100_copy_blit(struct radeon_device *rdev,
863 867
864 /* Ask for enough room for blit + flush + fence */ 868 /* Ask for enough room for blit + flush + fence */
865 ndw = 64 + (10 * num_loops); 869 ndw = 64 + (10 * num_loops);
866 r = radeon_ring_lock(rdev, ndw); 870 r = radeon_ring_lock(rdev, cp, ndw);
867 if (r) { 871 if (r) {
868 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw); 872 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
869 return -EINVAL; 873 return -EINVAL;
@@ -877,8 +881,8 @@ int r100_copy_blit(struct radeon_device *rdev,
877 881
878 /* pages are in Y direction - height 882 /* pages are in Y direction - height
879 page width in X direction - width */ 883 page width in X direction - width */
880 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8)); 884 radeon_ring_write(cp, PACKET3(PACKET3_BITBLT_MULTI, 8));
881 radeon_ring_write(rdev, 885 radeon_ring_write(cp,
882 RADEON_GMC_SRC_PITCH_OFFSET_CNTL | 886 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
883 RADEON_GMC_DST_PITCH_OFFSET_CNTL | 887 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
884 RADEON_GMC_SRC_CLIPPING | 888 RADEON_GMC_SRC_CLIPPING |
@@ -890,26 +894,26 @@ int r100_copy_blit(struct radeon_device *rdev,
890 RADEON_DP_SRC_SOURCE_MEMORY | 894 RADEON_DP_SRC_SOURCE_MEMORY |
891 RADEON_GMC_CLR_CMP_CNTL_DIS | 895 RADEON_GMC_CLR_CMP_CNTL_DIS |
892 RADEON_GMC_WR_MSK_DIS); 896 RADEON_GMC_WR_MSK_DIS);
893 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10)); 897 radeon_ring_write(cp, (pitch << 22) | (src_offset >> 10));
894 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10)); 898 radeon_ring_write(cp, (pitch << 22) | (dst_offset >> 10));
895 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 899 radeon_ring_write(cp, (0x1fff) | (0x1fff << 16));
896 radeon_ring_write(rdev, 0); 900 radeon_ring_write(cp, 0);
897 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16)); 901 radeon_ring_write(cp, (0x1fff) | (0x1fff << 16));
898 radeon_ring_write(rdev, num_gpu_pages); 902 radeon_ring_write(cp, num_gpu_pages);
899 radeon_ring_write(rdev, num_gpu_pages); 903 radeon_ring_write(cp, num_gpu_pages);
900 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16)); 904 radeon_ring_write(cp, cur_pages | (stride_pixels << 16));
901 } 905 }
902 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0)); 906 radeon_ring_write(cp, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
903 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL); 907 radeon_ring_write(cp, RADEON_RB2D_DC_FLUSH_ALL);
904 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 908 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
905 radeon_ring_write(rdev, 909 radeon_ring_write(cp,
906 RADEON_WAIT_2D_IDLECLEAN | 910 RADEON_WAIT_2D_IDLECLEAN |
907 RADEON_WAIT_HOST_IDLECLEAN | 911 RADEON_WAIT_HOST_IDLECLEAN |
908 RADEON_WAIT_DMA_GUI_IDLE); 912 RADEON_WAIT_DMA_GUI_IDLE);
909 if (fence) { 913 if (fence) {
910 r = radeon_fence_emit(rdev, fence); 914 r = radeon_fence_emit(rdev, fence);
911 } 915 }
912 radeon_ring_unlock_commit(rdev); 916 radeon_ring_unlock_commit(rdev, cp);
913 return r; 917 return r;
914} 918}
915 919
@@ -930,19 +934,20 @@ static int r100_cp_wait_for_idle(struct radeon_device *rdev)
930 934
931void r100_ring_start(struct radeon_device *rdev) 935void r100_ring_start(struct radeon_device *rdev)
932{ 936{
937 struct radeon_cp *cp = &rdev->cp;
933 int r; 938 int r;
934 939
935 r = radeon_ring_lock(rdev, 2); 940 r = radeon_ring_lock(rdev, cp, 2);
936 if (r) { 941 if (r) {
937 return; 942 return;
938 } 943 }
939 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 944 radeon_ring_write(cp, PACKET0(RADEON_ISYNC_CNTL, 0));
940 radeon_ring_write(rdev, 945 radeon_ring_write(cp,
941 RADEON_ISYNC_ANY2D_IDLE3D | 946 RADEON_ISYNC_ANY2D_IDLE3D |
942 RADEON_ISYNC_ANY3D_IDLE2D | 947 RADEON_ISYNC_ANY3D_IDLE2D |
943 RADEON_ISYNC_WAIT_IDLEGUI | 948 RADEON_ISYNC_WAIT_IDLEGUI |
944 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 949 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
945 radeon_ring_unlock_commit(rdev); 950 radeon_ring_unlock_commit(rdev, cp);
946} 951}
947 952
948 953
@@ -1043,6 +1048,7 @@ static void r100_cp_load_microcode(struct radeon_device *rdev)
1043 1048
1044int r100_cp_init(struct radeon_device *rdev, unsigned ring_size) 1049int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1045{ 1050{
1051 struct radeon_cp *cp = &rdev->cp;
1046 unsigned rb_bufsz; 1052 unsigned rb_bufsz;
1047 unsigned rb_blksz; 1053 unsigned rb_blksz;
1048 unsigned max_fetch; 1054 unsigned max_fetch;
@@ -1068,7 +1074,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1068 rb_bufsz = drm_order(ring_size / 8); 1074 rb_bufsz = drm_order(ring_size / 8);
1069 ring_size = (1 << (rb_bufsz + 1)) * 4; 1075 ring_size = (1 << (rb_bufsz + 1)) * 4;
1070 r100_cp_load_microcode(rdev); 1076 r100_cp_load_microcode(rdev);
1071 r = radeon_ring_init(rdev, ring_size); 1077 r = radeon_ring_init(rdev, cp, ring_size);
1072 if (r) { 1078 if (r) {
1073 return r; 1079 return r;
1074 } 1080 }
@@ -1077,7 +1083,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1077 rb_blksz = 9; 1083 rb_blksz = 9;
1078 /* cp will read 128bytes at a time (4 dwords) */ 1084 /* cp will read 128bytes at a time (4 dwords) */
1079 max_fetch = 1; 1085 max_fetch = 1;
1080 rdev->cp.align_mask = 16 - 1; 1086 cp->align_mask = 16 - 1;
1081 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */ 1087 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
1082 pre_write_timer = 64; 1088 pre_write_timer = 64;
1083 /* Force CP_RB_WPTR write if written more than one time before the 1089 /* Force CP_RB_WPTR write if written more than one time before the
@@ -1107,13 +1113,13 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1107 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE); 1113 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_NO_UPDATE);
1108 1114
1109 /* Set ring address */ 1115 /* Set ring address */
1110 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr); 1116 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)cp->gpu_addr);
1111 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr); 1117 WREG32(RADEON_CP_RB_BASE, cp->gpu_addr);
1112 /* Force read & write ptr to 0 */ 1118 /* Force read & write ptr to 0 */
1113 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE); 1119 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA | RADEON_RB_NO_UPDATE);
1114 WREG32(RADEON_CP_RB_RPTR_WR, 0); 1120 WREG32(RADEON_CP_RB_RPTR_WR, 0);
1115 rdev->cp.wptr = 0; 1121 cp->wptr = 0;
1116 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 1122 WREG32(RADEON_CP_RB_WPTR, cp->wptr);
1117 1123
1118 /* set the wb address whether it's enabled or not */ 1124 /* set the wb address whether it's enabled or not */
1119 WREG32(R_00070C_CP_RB_RPTR_ADDR, 1125 WREG32(R_00070C_CP_RB_RPTR_ADDR,
@@ -1129,7 +1135,7 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1129 1135
1130 WREG32(RADEON_CP_RB_CNTL, tmp); 1136 WREG32(RADEON_CP_RB_CNTL, tmp);
1131 udelay(10); 1137 udelay(10);
1132 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 1138 cp->rptr = RREG32(RADEON_CP_RB_RPTR);
1133 /* Set cp mode to bus mastering & enable cp*/ 1139 /* Set cp mode to bus mastering & enable cp*/
1134 WREG32(RADEON_CP_CSQ_MODE, 1140 WREG32(RADEON_CP_CSQ_MODE,
1135 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 1141 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
@@ -1138,12 +1144,12 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
1138 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D); 1144 WREG32(RADEON_CP_CSQ_MODE, 0x00004D4D);
1139 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM); 1145 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
1140 radeon_ring_start(rdev); 1146 radeon_ring_start(rdev);
1141 r = radeon_ring_test(rdev); 1147 r = radeon_ring_test(rdev, cp);
1142 if (r) { 1148 if (r) {
1143 DRM_ERROR("radeon: cp isn't working (%d).\n", r); 1149 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
1144 return r; 1150 return r;
1145 } 1151 }
1146 rdev->cp.ready = true; 1152 cp->ready = true;
1147 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); 1153 radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
1148 return 0; 1154 return 0;
1149} 1155}
@@ -1155,7 +1161,7 @@ void r100_cp_fini(struct radeon_device *rdev)
1155 } 1161 }
1156 /* Disable ring */ 1162 /* Disable ring */
1157 r100_cp_disable(rdev); 1163 r100_cp_disable(rdev);
1158 radeon_ring_fini(rdev); 1164 radeon_ring_fini(rdev, &rdev->cp);
1159 DRM_INFO("radeon: cp finalized\n"); 1165 DRM_INFO("radeon: cp finalized\n");
1160} 1166}
1161 1167
@@ -1173,9 +1179,9 @@ void r100_cp_disable(struct radeon_device *rdev)
1173 } 1179 }
1174} 1180}
1175 1181
1176void r100_cp_commit(struct radeon_device *rdev) 1182void r100_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp)
1177{ 1183{
1178 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr); 1184 WREG32(RADEON_CP_RB_WPTR, cp->wptr);
1179 (void)RREG32(RADEON_CP_RB_WPTR); 1185 (void)RREG32(RADEON_CP_RB_WPTR);
1180} 1186}
1181 1187
@@ -2160,26 +2166,26 @@ bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *l
2160 return false; 2166 return false;
2161} 2167}
2162 2168
2163bool r100_gpu_is_lockup(struct radeon_device *rdev) 2169bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
2164{ 2170{
2165 u32 rbbm_status; 2171 u32 rbbm_status;
2166 int r; 2172 int r;
2167 2173
2168 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 2174 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
2169 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 2175 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
2170 r100_gpu_lockup_update(&rdev->config.r100.lockup, &rdev->cp); 2176 r100_gpu_lockup_update(&rdev->config.r100.lockup, cp);
2171 return false; 2177 return false;
2172 } 2178 }
2173 /* force CP activities */ 2179 /* force CP activities */
2174 r = radeon_ring_lock(rdev, 2); 2180 r = radeon_ring_lock(rdev, cp, 2);
2175 if (!r) { 2181 if (!r) {
2176 /* PACKET2 NOP */ 2182 /* PACKET2 NOP */
2177 radeon_ring_write(rdev, 0x80000000); 2183 radeon_ring_write(cp, 0x80000000);
2178 radeon_ring_write(rdev, 0x80000000); 2184 radeon_ring_write(cp, 0x80000000);
2179 radeon_ring_unlock_commit(rdev); 2185 radeon_ring_unlock_commit(rdev, cp);
2180 } 2186 }
2181 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 2187 cp->rptr = RREG32(RADEON_CP_RB_RPTR);
2182 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, &rdev->cp); 2188 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r100.lockup, cp);
2183} 2189}
2184 2190
2185void r100_bm_disable(struct radeon_device *rdev) 2191void r100_bm_disable(struct radeon_device *rdev)
@@ -2587,21 +2593,22 @@ static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2587 struct drm_info_node *node = (struct drm_info_node *) m->private; 2593 struct drm_info_node *node = (struct drm_info_node *) m->private;
2588 struct drm_device *dev = node->minor->dev; 2594 struct drm_device *dev = node->minor->dev;
2589 struct radeon_device *rdev = dev->dev_private; 2595 struct radeon_device *rdev = dev->dev_private;
2596 struct radeon_cp *cp = &rdev->cp;
2590 uint32_t rdp, wdp; 2597 uint32_t rdp, wdp;
2591 unsigned count, i, j; 2598 unsigned count, i, j;
2592 2599
2593 radeon_ring_free_size(rdev); 2600 radeon_ring_free_size(rdev, cp);
2594 rdp = RREG32(RADEON_CP_RB_RPTR); 2601 rdp = RREG32(RADEON_CP_RB_RPTR);
2595 wdp = RREG32(RADEON_CP_RB_WPTR); 2602 wdp = RREG32(RADEON_CP_RB_WPTR);
2596 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask; 2603 count = (rdp + cp->ring_size - wdp) & cp->ptr_mask;
2597 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT)); 2604 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2598 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp); 2605 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2599 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp); 2606 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2600 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 2607 seq_printf(m, "%u free dwords in ring\n", cp->ring_free_dw);
2601 seq_printf(m, "%u dwords in ring\n", count); 2608 seq_printf(m, "%u dwords in ring\n", count);
2602 for (j = 0; j <= count; j++) { 2609 for (j = 0; j <= count; j++) {
2603 i = (rdp + j) & rdev->cp.ptr_mask; 2610 i = (rdp + j) & cp->ptr_mask;
2604 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 2611 seq_printf(m, "r[%04d]=0x%08x\n", i, cp->ring[i]);
2605 } 2612 }
2606 return 0; 2613 return 0;
2607} 2614}
@@ -3643,7 +3650,7 @@ void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track
3643 } 3650 }
3644} 3651}
3645 3652
3646int r100_ring_test(struct radeon_device *rdev) 3653int r100_ring_test(struct radeon_device *rdev, struct radeon_cp *cp)
3647{ 3654{
3648 uint32_t scratch; 3655 uint32_t scratch;
3649 uint32_t tmp = 0; 3656 uint32_t tmp = 0;
@@ -3656,15 +3663,15 @@ int r100_ring_test(struct radeon_device *rdev)
3656 return r; 3663 return r;
3657 } 3664 }
3658 WREG32(scratch, 0xCAFEDEAD); 3665 WREG32(scratch, 0xCAFEDEAD);
3659 r = radeon_ring_lock(rdev, 2); 3666 r = radeon_ring_lock(rdev, cp, 2);
3660 if (r) { 3667 if (r) {
3661 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 3668 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3662 radeon_scratch_free(rdev, scratch); 3669 radeon_scratch_free(rdev, scratch);
3663 return r; 3670 return r;
3664 } 3671 }
3665 radeon_ring_write(rdev, PACKET0(scratch, 0)); 3672 radeon_ring_write(cp, PACKET0(scratch, 0));
3666 radeon_ring_write(rdev, 0xDEADBEEF); 3673 radeon_ring_write(cp, 0xDEADBEEF);
3667 radeon_ring_unlock_commit(rdev); 3674 radeon_ring_unlock_commit(rdev, cp);
3668 for (i = 0; i < rdev->usec_timeout; i++) { 3675 for (i = 0; i < rdev->usec_timeout; i++) {
3669 tmp = RREG32(scratch); 3676 tmp = RREG32(scratch);
3670 if (tmp == 0xDEADBEEF) { 3677 if (tmp == 0xDEADBEEF) {
@@ -3685,9 +3692,11 @@ int r100_ring_test(struct radeon_device *rdev)
3685 3692
3686void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 3693void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3687{ 3694{
3688 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1)); 3695 struct radeon_cp *cp = &rdev->cp;
3689 radeon_ring_write(rdev, ib->gpu_addr); 3696
3690 radeon_ring_write(rdev, ib->length_dw); 3697 radeon_ring_write(cp, PACKET0(RADEON_CP_IB_BASE, 1));
3698 radeon_ring_write(cp, ib->gpu_addr);
3699 radeon_ring_write(cp, ib->length_dw);
3691} 3700}
3692 3701
3693int r100_ib_test(struct radeon_device *rdev) 3702int r100_ib_test(struct radeon_device *rdev)
@@ -3704,7 +3713,7 @@ int r100_ib_test(struct radeon_device *rdev)
3704 return r; 3713 return r;
3705 } 3714 }
3706 WREG32(scratch, 0xCAFEDEAD); 3715 WREG32(scratch, 0xCAFEDEAD);
3707 r = radeon_ib_get(rdev, &ib); 3716 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &ib);
3708 if (r) { 3717 if (r) {
3709 return r; 3718 return r;
3710 } 3719 }
diff --git a/drivers/gpu/drm/radeon/r200.c b/drivers/gpu/drm/radeon/r200.c
index a1f3ba063c2d..d84e633f72fc 100644
--- a/drivers/gpu/drm/radeon/r200.c
+++ b/drivers/gpu/drm/radeon/r200.c
@@ -87,6 +87,7 @@ int r200_copy_dma(struct radeon_device *rdev,
87 unsigned num_gpu_pages, 87 unsigned num_gpu_pages,
88 struct radeon_fence *fence) 88 struct radeon_fence *fence)
89{ 89{
90 struct radeon_cp *cp = &rdev->cp;
90 uint32_t size; 91 uint32_t size;
91 uint32_t cur_size; 92 uint32_t cur_size;
92 int i, num_loops; 93 int i, num_loops;
@@ -95,33 +96,33 @@ int r200_copy_dma(struct radeon_device *rdev,
95 /* radeon pitch is /64 */ 96 /* radeon pitch is /64 */
96 size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT; 97 size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
97 num_loops = DIV_ROUND_UP(size, 0x1FFFFF); 98 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
98 r = radeon_ring_lock(rdev, num_loops * 4 + 64); 99 r = radeon_ring_lock(rdev, cp, num_loops * 4 + 64);
99 if (r) { 100 if (r) {
100 DRM_ERROR("radeon: moving bo (%d).\n", r); 101 DRM_ERROR("radeon: moving bo (%d).\n", r);
101 return r; 102 return r;
102 } 103 }
103 /* Must wait for 2D idle & clean before DMA or hangs might happen */ 104 /* Must wait for 2D idle & clean before DMA or hangs might happen */
104 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 105 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
105 radeon_ring_write(rdev, (1 << 16)); 106 radeon_ring_write(cp, (1 << 16));
106 for (i = 0; i < num_loops; i++) { 107 for (i = 0; i < num_loops; i++) {
107 cur_size = size; 108 cur_size = size;
108 if (cur_size > 0x1FFFFF) { 109 if (cur_size > 0x1FFFFF) {
109 cur_size = 0x1FFFFF; 110 cur_size = 0x1FFFFF;
110 } 111 }
111 size -= cur_size; 112 size -= cur_size;
112 radeon_ring_write(rdev, PACKET0(0x720, 2)); 113 radeon_ring_write(cp, PACKET0(0x720, 2));
113 radeon_ring_write(rdev, src_offset); 114 radeon_ring_write(cp, src_offset);
114 radeon_ring_write(rdev, dst_offset); 115 radeon_ring_write(cp, dst_offset);
115 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30)); 116 radeon_ring_write(cp, cur_size | (1 << 31) | (1 << 30));
116 src_offset += cur_size; 117 src_offset += cur_size;
117 dst_offset += cur_size; 118 dst_offset += cur_size;
118 } 119 }
119 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 120 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
120 radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE); 121 radeon_ring_write(cp, RADEON_WAIT_DMA_GUI_IDLE);
121 if (fence) { 122 if (fence) {
122 r = radeon_fence_emit(rdev, fence); 123 r = radeon_fence_emit(rdev, fence);
123 } 124 }
124 radeon_ring_unlock_commit(rdev); 125 radeon_ring_unlock_commit(rdev, cp);
125 return r; 126 return r;
126} 127}
127 128
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index b04731206460..cbb62fc3f2e9 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -175,37 +175,40 @@ void rv370_pcie_gart_fini(struct radeon_device *rdev)
175void r300_fence_ring_emit(struct radeon_device *rdev, 175void r300_fence_ring_emit(struct radeon_device *rdev,
176 struct radeon_fence *fence) 176 struct radeon_fence *fence)
177{ 177{
178 struct radeon_cp *cp = &rdev->cp;
179
178 /* Who ever call radeon_fence_emit should call ring_lock and ask 180 /* Who ever call radeon_fence_emit should call ring_lock and ask
179 * for enough space (today caller are ib schedule and buffer move) */ 181 * for enough space (today caller are ib schedule and buffer move) */
180 /* Write SC register so SC & US assert idle */ 182 /* Write SC register so SC & US assert idle */
181 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0)); 183 radeon_ring_write(cp, PACKET0(R300_RE_SCISSORS_TL, 0));
182 radeon_ring_write(rdev, 0); 184 radeon_ring_write(cp, 0);
183 radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0)); 185 radeon_ring_write(cp, PACKET0(R300_RE_SCISSORS_BR, 0));
184 radeon_ring_write(rdev, 0); 186 radeon_ring_write(cp, 0);
185 /* Flush 3D cache */ 187 /* Flush 3D cache */
186 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 188 radeon_ring_write(cp, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
187 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH); 189 radeon_ring_write(cp, R300_RB3D_DC_FLUSH);
188 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 190 radeon_ring_write(cp, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
189 radeon_ring_write(rdev, R300_ZC_FLUSH); 191 radeon_ring_write(cp, R300_ZC_FLUSH);
190 /* Wait until IDLE & CLEAN */ 192 /* Wait until IDLE & CLEAN */
191 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 193 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
192 radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN | 194 radeon_ring_write(cp, (RADEON_WAIT_3D_IDLECLEAN |
193 RADEON_WAIT_2D_IDLECLEAN | 195 RADEON_WAIT_2D_IDLECLEAN |
194 RADEON_WAIT_DMA_GUI_IDLE)); 196 RADEON_WAIT_DMA_GUI_IDLE));
195 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 197 radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
196 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl | 198 radeon_ring_write(cp, rdev->config.r300.hdp_cntl |
197 RADEON_HDP_READ_BUFFER_INVALIDATE); 199 RADEON_HDP_READ_BUFFER_INVALIDATE);
198 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0)); 200 radeon_ring_write(cp, PACKET0(RADEON_HOST_PATH_CNTL, 0));
199 radeon_ring_write(rdev, rdev->config.r300.hdp_cntl); 201 radeon_ring_write(cp, rdev->config.r300.hdp_cntl);
200 /* Emit fence sequence & fire IRQ */ 202 /* Emit fence sequence & fire IRQ */
201 radeon_ring_write(rdev, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0)); 203 radeon_ring_write(cp, PACKET0(rdev->fence_drv[fence->ring].scratch_reg, 0));
202 radeon_ring_write(rdev, fence->seq); 204 radeon_ring_write(cp, fence->seq);
203 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0)); 205 radeon_ring_write(cp, PACKET0(RADEON_GEN_INT_STATUS, 0));
204 radeon_ring_write(rdev, RADEON_SW_INT_FIRE); 206 radeon_ring_write(cp, RADEON_SW_INT_FIRE);
205} 207}
206 208
207void r300_ring_start(struct radeon_device *rdev) 209void r300_ring_start(struct radeon_device *rdev)
208{ 210{
211 struct radeon_cp *cp = &rdev->cp;
209 unsigned gb_tile_config; 212 unsigned gb_tile_config;
210 int r; 213 int r;
211 214
@@ -227,44 +230,44 @@ void r300_ring_start(struct radeon_device *rdev)
227 break; 230 break;
228 } 231 }
229 232
230 r = radeon_ring_lock(rdev, 64); 233 r = radeon_ring_lock(rdev, cp, 64);
231 if (r) { 234 if (r) {
232 return; 235 return;
233 } 236 }
234 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0)); 237 radeon_ring_write(cp, PACKET0(RADEON_ISYNC_CNTL, 0));
235 radeon_ring_write(rdev, 238 radeon_ring_write(cp,
236 RADEON_ISYNC_ANY2D_IDLE3D | 239 RADEON_ISYNC_ANY2D_IDLE3D |
237 RADEON_ISYNC_ANY3D_IDLE2D | 240 RADEON_ISYNC_ANY3D_IDLE2D |
238 RADEON_ISYNC_WAIT_IDLEGUI | 241 RADEON_ISYNC_WAIT_IDLEGUI |
239 RADEON_ISYNC_CPSCRATCH_IDLEGUI); 242 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
240 radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0)); 243 radeon_ring_write(cp, PACKET0(R300_GB_TILE_CONFIG, 0));
241 radeon_ring_write(rdev, gb_tile_config); 244 radeon_ring_write(cp, gb_tile_config);
242 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 245 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
243 radeon_ring_write(rdev, 246 radeon_ring_write(cp,
244 RADEON_WAIT_2D_IDLECLEAN | 247 RADEON_WAIT_2D_IDLECLEAN |
245 RADEON_WAIT_3D_IDLECLEAN); 248 RADEON_WAIT_3D_IDLECLEAN);
246 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); 249 radeon_ring_write(cp, PACKET0(R300_DST_PIPE_CONFIG, 0));
247 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); 250 radeon_ring_write(cp, R300_PIPE_AUTO_CONFIG);
248 radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0)); 251 radeon_ring_write(cp, PACKET0(R300_GB_SELECT, 0));
249 radeon_ring_write(rdev, 0); 252 radeon_ring_write(cp, 0);
250 radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0)); 253 radeon_ring_write(cp, PACKET0(R300_GB_ENABLE, 0));
251 radeon_ring_write(rdev, 0); 254 radeon_ring_write(cp, 0);
252 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 255 radeon_ring_write(cp, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
253 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 256 radeon_ring_write(cp, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
254 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 257 radeon_ring_write(cp, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
255 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 258 radeon_ring_write(cp, R300_ZC_FLUSH | R300_ZC_FREE);
256 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0)); 259 radeon_ring_write(cp, PACKET0(RADEON_WAIT_UNTIL, 0));
257 radeon_ring_write(rdev, 260 radeon_ring_write(cp,
258 RADEON_WAIT_2D_IDLECLEAN | 261 RADEON_WAIT_2D_IDLECLEAN |
259 RADEON_WAIT_3D_IDLECLEAN); 262 RADEON_WAIT_3D_IDLECLEAN);
260 radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0)); 263 radeon_ring_write(cp, PACKET0(R300_GB_AA_CONFIG, 0));
261 radeon_ring_write(rdev, 0); 264 radeon_ring_write(cp, 0);
262 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 265 radeon_ring_write(cp, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
263 radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE); 266 radeon_ring_write(cp, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
264 radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0)); 267 radeon_ring_write(cp, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
265 radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE); 268 radeon_ring_write(cp, R300_ZC_FLUSH | R300_ZC_FREE);
266 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0)); 269 radeon_ring_write(cp, PACKET0(R300_GB_MSPOS0, 0));
267 radeon_ring_write(rdev, 270 radeon_ring_write(cp,
268 ((6 << R300_MS_X0_SHIFT) | 271 ((6 << R300_MS_X0_SHIFT) |
269 (6 << R300_MS_Y0_SHIFT) | 272 (6 << R300_MS_Y0_SHIFT) |
270 (6 << R300_MS_X1_SHIFT) | 273 (6 << R300_MS_X1_SHIFT) |
@@ -273,8 +276,8 @@ void r300_ring_start(struct radeon_device *rdev)
273 (6 << R300_MS_Y2_SHIFT) | 276 (6 << R300_MS_Y2_SHIFT) |
274 (6 << R300_MSBD0_Y_SHIFT) | 277 (6 << R300_MSBD0_Y_SHIFT) |
275 (6 << R300_MSBD0_X_SHIFT))); 278 (6 << R300_MSBD0_X_SHIFT)));
276 radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0)); 279 radeon_ring_write(cp, PACKET0(R300_GB_MSPOS1, 0));
277 radeon_ring_write(rdev, 280 radeon_ring_write(cp,
278 ((6 << R300_MS_X3_SHIFT) | 281 ((6 << R300_MS_X3_SHIFT) |
279 (6 << R300_MS_Y3_SHIFT) | 282 (6 << R300_MS_Y3_SHIFT) |
280 (6 << R300_MS_X4_SHIFT) | 283 (6 << R300_MS_X4_SHIFT) |
@@ -282,16 +285,16 @@ void r300_ring_start(struct radeon_device *rdev)
282 (6 << R300_MS_X5_SHIFT) | 285 (6 << R300_MS_X5_SHIFT) |
283 (6 << R300_MS_Y5_SHIFT) | 286 (6 << R300_MS_Y5_SHIFT) |
284 (6 << R300_MSBD1_SHIFT))); 287 (6 << R300_MSBD1_SHIFT)));
285 radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0)); 288 radeon_ring_write(cp, PACKET0(R300_GA_ENHANCE, 0));
286 radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL); 289 radeon_ring_write(cp, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
287 radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0)); 290 radeon_ring_write(cp, PACKET0(R300_GA_POLY_MODE, 0));
288 radeon_ring_write(rdev, 291 radeon_ring_write(cp,
289 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE); 292 R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
290 radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0)); 293 radeon_ring_write(cp, PACKET0(R300_GA_ROUND_MODE, 0));
291 radeon_ring_write(rdev, 294 radeon_ring_write(cp,
292 R300_GEOMETRY_ROUND_NEAREST | 295 R300_GEOMETRY_ROUND_NEAREST |
293 R300_COLOR_ROUND_NEAREST); 296 R300_COLOR_ROUND_NEAREST);
294 radeon_ring_unlock_commit(rdev); 297 radeon_ring_unlock_commit(rdev, cp);
295} 298}
296 299
297void r300_errata(struct radeon_device *rdev) 300void r300_errata(struct radeon_device *rdev)
@@ -375,26 +378,26 @@ void r300_gpu_init(struct radeon_device *rdev)
375 rdev->num_gb_pipes, rdev->num_z_pipes); 378 rdev->num_gb_pipes, rdev->num_z_pipes);
376} 379}
377 380
378bool r300_gpu_is_lockup(struct radeon_device *rdev) 381bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
379{ 382{
380 u32 rbbm_status; 383 u32 rbbm_status;
381 int r; 384 int r;
382 385
383 rbbm_status = RREG32(R_000E40_RBBM_STATUS); 386 rbbm_status = RREG32(R_000E40_RBBM_STATUS);
384 if (!G_000E40_GUI_ACTIVE(rbbm_status)) { 387 if (!G_000E40_GUI_ACTIVE(rbbm_status)) {
385 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); 388 r100_gpu_lockup_update(&rdev->config.r300.lockup, cp);
386 return false; 389 return false;
387 } 390 }
388 /* force CP activities */ 391 /* force CP activities */
389 r = radeon_ring_lock(rdev, 2); 392 r = radeon_ring_lock(rdev, cp, 2);
390 if (!r) { 393 if (!r) {
391 /* PACKET2 NOP */ 394 /* PACKET2 NOP */
392 radeon_ring_write(rdev, 0x80000000); 395 radeon_ring_write(cp, 0x80000000);
393 radeon_ring_write(rdev, 0x80000000); 396 radeon_ring_write(cp, 0x80000000);
394 radeon_ring_unlock_commit(rdev); 397 radeon_ring_unlock_commit(rdev, cp);
395 } 398 }
396 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 399 cp->rptr = RREG32(RADEON_CP_RB_RPTR);
397 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); 400 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, cp);
398} 401}
399 402
400int r300_asic_reset(struct radeon_device *rdev) 403int r300_asic_reset(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 5dbc378d3c2e..4c0af4955f08 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -199,6 +199,8 @@ static void r420_clock_resume(struct radeon_device *rdev)
199 199
200static void r420_cp_errata_init(struct radeon_device *rdev) 200static void r420_cp_errata_init(struct radeon_device *rdev)
201{ 201{
202 struct radeon_cp *cp = &rdev->cp;
203
202 /* RV410 and R420 can lock up if CP DMA to host memory happens 204 /* RV410 and R420 can lock up if CP DMA to host memory happens
203 * while the 2D engine is busy. 205 * while the 2D engine is busy.
204 * 206 *
@@ -206,22 +208,24 @@ static void r420_cp_errata_init(struct radeon_device *rdev)
206 * of the CP init, apparently. 208 * of the CP init, apparently.
207 */ 209 */
208 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch); 210 radeon_scratch_get(rdev, &rdev->config.r300.resync_scratch);
209 radeon_ring_lock(rdev, 8); 211 radeon_ring_lock(rdev, cp, 8);
210 radeon_ring_write(rdev, PACKET0(R300_CP_RESYNC_ADDR, 1)); 212 radeon_ring_write(cp, PACKET0(R300_CP_RESYNC_ADDR, 1));
211 radeon_ring_write(rdev, rdev->config.r300.resync_scratch); 213 radeon_ring_write(cp, rdev->config.r300.resync_scratch);
212 radeon_ring_write(rdev, 0xDEADBEEF); 214 radeon_ring_write(cp, 0xDEADBEEF);
213 radeon_ring_unlock_commit(rdev); 215 radeon_ring_unlock_commit(rdev, cp);
214} 216}
215 217
216static void r420_cp_errata_fini(struct radeon_device *rdev) 218static void r420_cp_errata_fini(struct radeon_device *rdev)
217{ 219{
220 struct radeon_cp *cp = &rdev->cp;
221
218 /* Catch the RESYNC we dispatched all the way back, 222 /* Catch the RESYNC we dispatched all the way back,
219 * at the very beginning of the CP init. 223 * at the very beginning of the CP init.
220 */ 224 */
221 radeon_ring_lock(rdev, 8); 225 radeon_ring_lock(rdev, cp, 8);
222 radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0)); 226 radeon_ring_write(cp, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
223 radeon_ring_write(rdev, R300_RB3D_DC_FINISH); 227 radeon_ring_write(cp, R300_RB3D_DC_FINISH);
224 radeon_ring_unlock_commit(rdev); 228 radeon_ring_unlock_commit(rdev, cp);
225 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch); 229 radeon_scratch_free(rdev, rdev->config.r300.resync_scratch);
226} 230}
227 231
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index bd2b3d087b16..eaf57cc75828 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1344,7 +1344,7 @@ int r600_gpu_soft_reset(struct radeon_device *rdev)
1344 return 0; 1344 return 0;
1345} 1345}
1346 1346
1347bool r600_gpu_is_lockup(struct radeon_device *rdev) 1347bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp)
1348{ 1348{
1349 u32 srbm_status; 1349 u32 srbm_status;
1350 u32 grbm_status; 1350 u32 grbm_status;
@@ -1361,19 +1361,19 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
1361 grbm_status = RREG32(R_008010_GRBM_STATUS); 1361 grbm_status = RREG32(R_008010_GRBM_STATUS);
1362 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 1362 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1363 if (!G_008010_GUI_ACTIVE(grbm_status)) { 1363 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1364 r100_gpu_lockup_update(lockup, &rdev->cp); 1364 r100_gpu_lockup_update(lockup, cp);
1365 return false; 1365 return false;
1366 } 1366 }
1367 /* force CP activities */ 1367 /* force CP activities */
1368 r = radeon_ring_lock(rdev, 2); 1368 r = radeon_ring_lock(rdev, cp, 2);
1369 if (!r) { 1369 if (!r) {
1370 /* PACKET2 NOP */ 1370 /* PACKET2 NOP */
1371 radeon_ring_write(rdev, 0x80000000); 1371 radeon_ring_write(cp, 0x80000000);
1372 radeon_ring_write(rdev, 0x80000000); 1372 radeon_ring_write(cp, 0x80000000);
1373 radeon_ring_unlock_commit(rdev); 1373 radeon_ring_unlock_commit(rdev, cp);
1374 } 1374 }
1375 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); 1375 cp->rptr = RREG32(R600_CP_RB_RPTR);
1376 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp); 1376 return r100_gpu_cp_is_lockup(rdev, lockup, cp);
1377} 1377}
1378 1378
1379int r600_asic_reset(struct radeon_device *rdev) 1379int r600_asic_reset(struct radeon_device *rdev)
@@ -2144,27 +2144,28 @@ static int r600_cp_load_microcode(struct radeon_device *rdev)
2144 2144
2145int r600_cp_start(struct radeon_device *rdev) 2145int r600_cp_start(struct radeon_device *rdev)
2146{ 2146{
2147 struct radeon_cp *cp = &rdev->cp;
2147 int r; 2148 int r;
2148 uint32_t cp_me; 2149 uint32_t cp_me;
2149 2150
2150 r = radeon_ring_lock(rdev, 7); 2151 r = radeon_ring_lock(rdev, cp, 7);
2151 if (r) { 2152 if (r) {
2152 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2153 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2153 return r; 2154 return r;
2154 } 2155 }
2155 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5)); 2156 radeon_ring_write(cp, PACKET3(PACKET3_ME_INITIALIZE, 5));
2156 radeon_ring_write(rdev, 0x1); 2157 radeon_ring_write(cp, 0x1);
2157 if (rdev->family >= CHIP_RV770) { 2158 if (rdev->family >= CHIP_RV770) {
2158 radeon_ring_write(rdev, 0x0); 2159 radeon_ring_write(cp, 0x0);
2159 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1); 2160 radeon_ring_write(cp, rdev->config.rv770.max_hw_contexts - 1);
2160 } else { 2161 } else {
2161 radeon_ring_write(rdev, 0x3); 2162 radeon_ring_write(cp, 0x3);
2162 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1); 2163 radeon_ring_write(cp, rdev->config.r600.max_hw_contexts - 1);
2163 } 2164 }
2164 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1)); 2165 radeon_ring_write(cp, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2165 radeon_ring_write(rdev, 0); 2166 radeon_ring_write(cp, 0);
2166 radeon_ring_write(rdev, 0); 2167 radeon_ring_write(cp, 0);
2167 radeon_ring_unlock_commit(rdev); 2168 radeon_ring_unlock_commit(rdev, cp);
2168 2169
2169 cp_me = 0xff; 2170 cp_me = 0xff;
2170 WREG32(R_0086D8_CP_ME_CNTL, cp_me); 2171 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
@@ -2173,6 +2174,7 @@ int r600_cp_start(struct radeon_device *rdev)
2173 2174
2174int r600_cp_resume(struct radeon_device *rdev) 2175int r600_cp_resume(struct radeon_device *rdev)
2175{ 2176{
2177 struct radeon_cp *cp = &rdev->cp;
2176 u32 tmp; 2178 u32 tmp;
2177 u32 rb_bufsz; 2179 u32 rb_bufsz;
2178 int r; 2180 int r;
@@ -2184,7 +2186,7 @@ int r600_cp_resume(struct radeon_device *rdev)
2184 WREG32(GRBM_SOFT_RESET, 0); 2186 WREG32(GRBM_SOFT_RESET, 0);
2185 2187
2186 /* Set ring buffer size */ 2188 /* Set ring buffer size */
2187 rb_bufsz = drm_order(rdev->cp.ring_size / 8); 2189 rb_bufsz = drm_order(cp->ring_size / 8);
2188 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; 2190 tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2189#ifdef __BIG_ENDIAN 2191#ifdef __BIG_ENDIAN
2190 tmp |= BUF_SWAP_32BIT; 2192 tmp |= BUF_SWAP_32BIT;
@@ -2198,8 +2200,8 @@ int r600_cp_resume(struct radeon_device *rdev)
2198 /* Initialize the ring buffer's read and write pointers */ 2200 /* Initialize the ring buffer's read and write pointers */
2199 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 2201 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2200 WREG32(CP_RB_RPTR_WR, 0); 2202 WREG32(CP_RB_RPTR_WR, 0);
2201 rdev->cp.wptr = 0; 2203 cp->wptr = 0;
2202 WREG32(CP_RB_WPTR, rdev->cp.wptr); 2204 WREG32(CP_RB_WPTR, cp->wptr);
2203 2205
2204 /* set the wb address whether it's enabled or not */ 2206 /* set the wb address whether it's enabled or not */
2205 WREG32(CP_RB_RPTR_ADDR, 2207 WREG32(CP_RB_RPTR_ADDR,
@@ -2217,42 +2219,42 @@ int r600_cp_resume(struct radeon_device *rdev)
2217 mdelay(1); 2219 mdelay(1);
2218 WREG32(CP_RB_CNTL, tmp); 2220 WREG32(CP_RB_CNTL, tmp);
2219 2221
2220 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8); 2222 WREG32(CP_RB_BASE, cp->gpu_addr >> 8);
2221 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 2223 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2222 2224
2223 rdev->cp.rptr = RREG32(CP_RB_RPTR); 2225 cp->rptr = RREG32(CP_RB_RPTR);
2224 2226
2225 r600_cp_start(rdev); 2227 r600_cp_start(rdev);
2226 rdev->cp.ready = true; 2228 cp->ready = true;
2227 r = radeon_ring_test(rdev); 2229 r = radeon_ring_test(rdev, cp);
2228 if (r) { 2230 if (r) {
2229 rdev->cp.ready = false; 2231 cp->ready = false;
2230 return r; 2232 return r;
2231 } 2233 }
2232 return 0; 2234 return 0;
2233} 2235}
2234 2236
2235void r600_cp_commit(struct radeon_device *rdev) 2237void r600_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp)
2236{ 2238{
2237 WREG32(CP_RB_WPTR, rdev->cp.wptr); 2239 WREG32(CP_RB_WPTR, cp->wptr);
2238 (void)RREG32(CP_RB_WPTR); 2240 (void)RREG32(CP_RB_WPTR);
2239} 2241}
2240 2242
2241void r600_ring_init(struct radeon_device *rdev, unsigned ring_size) 2243void r600_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size)
2242{ 2244{
2243 u32 rb_bufsz; 2245 u32 rb_bufsz;
2244 2246
2245 /* Align ring size */ 2247 /* Align ring size */
2246 rb_bufsz = drm_order(ring_size / 8); 2248 rb_bufsz = drm_order(ring_size / 8);
2247 ring_size = (1 << (rb_bufsz + 1)) * 4; 2249 ring_size = (1 << (rb_bufsz + 1)) * 4;
2248 rdev->cp.ring_size = ring_size; 2250 cp->ring_size = ring_size;
2249 rdev->cp.align_mask = 16 - 1; 2251 cp->align_mask = 16 - 1;
2250} 2252}
2251 2253
2252void r600_cp_fini(struct radeon_device *rdev) 2254void r600_cp_fini(struct radeon_device *rdev)
2253{ 2255{
2254 r600_cp_stop(rdev); 2256 r600_cp_stop(rdev);
2255 radeon_ring_fini(rdev); 2257 radeon_ring_fini(rdev, &rdev->cp);
2256} 2258}
2257 2259
2258 2260
@@ -2271,7 +2273,7 @@ void r600_scratch_init(struct radeon_device *rdev)
2271 } 2273 }
2272} 2274}
2273 2275
2274int r600_ring_test(struct radeon_device *rdev) 2276int r600_ring_test(struct radeon_device *rdev, struct radeon_cp *cp)
2275{ 2277{
2276 uint32_t scratch; 2278 uint32_t scratch;
2277 uint32_t tmp = 0; 2279 uint32_t tmp = 0;
@@ -2284,16 +2286,16 @@ int r600_ring_test(struct radeon_device *rdev)
2284 return r; 2286 return r;
2285 } 2287 }
2286 WREG32(scratch, 0xCAFEDEAD); 2288 WREG32(scratch, 0xCAFEDEAD);
2287 r = radeon_ring_lock(rdev, 3); 2289 r = radeon_ring_lock(rdev, cp, 3);
2288 if (r) { 2290 if (r) {
2289 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r); 2291 DRM_ERROR("radeon: cp failed to lock ring %p (%d).\n", cp, r);
2290 radeon_scratch_free(rdev, scratch); 2292 radeon_scratch_free(rdev, scratch);
2291 return r; 2293 return r;
2292 } 2294 }
2293 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2295 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2294 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2296 radeon_ring_write(cp, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2295 radeon_ring_write(rdev, 0xDEADBEEF); 2297 radeon_ring_write(cp, 0xDEADBEEF);
2296 radeon_ring_unlock_commit(rdev); 2298 radeon_ring_unlock_commit(rdev, cp);
2297 for (i = 0; i < rdev->usec_timeout; i++) { 2299 for (i = 0; i < rdev->usec_timeout; i++) {
2298 tmp = RREG32(scratch); 2300 tmp = RREG32(scratch);
2299 if (tmp == 0xDEADBEEF) 2301 if (tmp == 0xDEADBEEF)
@@ -2301,10 +2303,10 @@ int r600_ring_test(struct radeon_device *rdev)
2301 DRM_UDELAY(1); 2303 DRM_UDELAY(1);
2302 } 2304 }
2303 if (i < rdev->usec_timeout) { 2305 if (i < rdev->usec_timeout) {
2304 DRM_INFO("ring test succeeded in %d usecs\n", i); 2306 DRM_INFO("ring test on %p succeeded in %d usecs\n", cp, i);
2305 } else { 2307 } else {
2306 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n", 2308 DRM_ERROR("radeon: ring %p test failed (scratch(0x%04X)=0x%08X)\n",
2307 scratch, tmp); 2309 cp, scratch, tmp);
2308 r = -EINVAL; 2310 r = -EINVAL;
2309 } 2311 }
2310 radeon_scratch_free(rdev, scratch); 2312 radeon_scratch_free(rdev, scratch);
@@ -2314,59 +2316,62 @@ int r600_ring_test(struct radeon_device *rdev)
2314void r600_fence_ring_emit(struct radeon_device *rdev, 2316void r600_fence_ring_emit(struct radeon_device *rdev,
2315 struct radeon_fence *fence) 2317 struct radeon_fence *fence)
2316{ 2318{
2319 struct radeon_cp *cp = &rdev->cp;
2320
2317 if (rdev->wb.use_event) { 2321 if (rdev->wb.use_event) {
2318 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET + 2322 u64 addr = rdev->wb.gpu_addr + R600_WB_EVENT_OFFSET +
2319 (u64)(rdev->fence_drv[fence->ring].scratch_reg - rdev->scratch.reg_base); 2323 (u64)(rdev->fence_drv[fence->ring].scratch_reg - rdev->scratch.reg_base);
2320 /* flush read cache over gart */ 2324 /* flush read cache over gart */
2321 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2325 radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
2322 radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA | 2326 radeon_ring_write(cp, PACKET3_TC_ACTION_ENA |
2323 PACKET3_VC_ACTION_ENA | 2327 PACKET3_VC_ACTION_ENA |
2324 PACKET3_SH_ACTION_ENA); 2328 PACKET3_SH_ACTION_ENA);
2325 radeon_ring_write(rdev, 0xFFFFFFFF); 2329 radeon_ring_write(cp, 0xFFFFFFFF);
2326 radeon_ring_write(rdev, 0); 2330 radeon_ring_write(cp, 0);
2327 radeon_ring_write(rdev, 10); /* poll interval */ 2331 radeon_ring_write(cp, 10); /* poll interval */
2328 /* EVENT_WRITE_EOP - flush caches, send int */ 2332 /* EVENT_WRITE_EOP - flush caches, send int */
2329 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE_EOP, 4)); 2333 radeon_ring_write(cp, PACKET3(PACKET3_EVENT_WRITE_EOP, 4));
2330 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5)); 2334 radeon_ring_write(cp, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT_TS) | EVENT_INDEX(5));
2331 radeon_ring_write(rdev, addr & 0xffffffff); 2335 radeon_ring_write(cp, addr & 0xffffffff);
2332 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); 2336 radeon_ring_write(cp, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2));
2333 radeon_ring_write(rdev, fence->seq); 2337 radeon_ring_write(cp, fence->seq);
2334 radeon_ring_write(rdev, 0); 2338 radeon_ring_write(cp, 0);
2335 } else { 2339 } else {
2336 /* flush read cache over gart */ 2340 /* flush read cache over gart */
2337 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); 2341 radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
2338 radeon_ring_write(rdev, PACKET3_TC_ACTION_ENA | 2342 radeon_ring_write(cp, PACKET3_TC_ACTION_ENA |
2339 PACKET3_VC_ACTION_ENA | 2343 PACKET3_VC_ACTION_ENA |
2340 PACKET3_SH_ACTION_ENA); 2344 PACKET3_SH_ACTION_ENA);
2341 radeon_ring_write(rdev, 0xFFFFFFFF); 2345 radeon_ring_write(cp, 0xFFFFFFFF);
2342 radeon_ring_write(rdev, 0); 2346 radeon_ring_write(cp, 0);
2343 radeon_ring_write(rdev, 10); /* poll interval */ 2347 radeon_ring_write(cp, 10); /* poll interval */
2344 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0)); 2348 radeon_ring_write(cp, PACKET3(PACKET3_EVENT_WRITE, 0));
2345 radeon_ring_write(rdev, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0)); 2349 radeon_ring_write(cp, EVENT_TYPE(CACHE_FLUSH_AND_INV_EVENT) | EVENT_INDEX(0));
2346 /* wait for 3D idle clean */ 2350 /* wait for 3D idle clean */
2347 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2351 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2348 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 2352 radeon_ring_write(cp, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2349 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit); 2353 radeon_ring_write(cp, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2350 /* Emit fence sequence & fire IRQ */ 2354 /* Emit fence sequence & fire IRQ */
2351 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 2355 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2352 radeon_ring_write(rdev, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2)); 2356 radeon_ring_write(cp, ((rdev->fence_drv[fence->ring].scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2353 radeon_ring_write(rdev, fence->seq); 2357 radeon_ring_write(cp, fence->seq);
2354 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */ 2358 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2355 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0)); 2359 radeon_ring_write(cp, PACKET0(CP_INT_STATUS, 0));
2356 radeon_ring_write(rdev, RB_INT_STAT); 2360 radeon_ring_write(cp, RB_INT_STAT);
2357 } 2361 }
2358} 2362}
2359 2363
2360void r600_semaphore_ring_emit(struct radeon_device *rdev, 2364void r600_semaphore_ring_emit(struct radeon_device *rdev,
2365 struct radeon_cp *cp,
2361 struct radeon_semaphore *semaphore, 2366 struct radeon_semaphore *semaphore,
2362 unsigned ring, bool emit_wait) 2367 bool emit_wait)
2363{ 2368{
2364 uint64_t addr = semaphore->gpu_addr; 2369 uint64_t addr = semaphore->gpu_addr;
2365 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL; 2370 unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
2366 2371
2367 radeon_ring_write(rdev, PACKET3(PACKET3_MEM_SEMAPHORE, 1)); 2372 radeon_ring_write(cp, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
2368 radeon_ring_write(rdev, addr & 0xffffffff); 2373 radeon_ring_write(cp, addr & 0xffffffff);
2369 radeon_ring_write(rdev, (upper_32_bits(addr) & 0xff) | sel); 2374 radeon_ring_write(cp, (upper_32_bits(addr) & 0xff) | sel);
2370} 2375}
2371 2376
2372int r600_copy_blit(struct radeon_device *rdev, 2377int r600_copy_blit(struct radeon_device *rdev,
@@ -2421,6 +2426,7 @@ void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2421 2426
2422int r600_startup(struct radeon_device *rdev) 2427int r600_startup(struct radeon_device *rdev)
2423{ 2428{
2429 struct radeon_cp *cp = &rdev->cp;
2424 int r; 2430 int r;
2425 2431
2426 /* enable pcie gen2 link */ 2432 /* enable pcie gen2 link */
@@ -2468,7 +2474,7 @@ int r600_startup(struct radeon_device *rdev)
2468 } 2474 }
2469 r600_irq_set(rdev); 2475 r600_irq_set(rdev);
2470 2476
2471 r = radeon_ring_init(rdev, rdev->cp.ring_size); 2477 r = radeon_ring_init(rdev, cp, cp->ring_size);
2472 if (r) 2478 if (r)
2473 return r; 2479 return r;
2474 r = r600_cp_load_microcode(rdev); 2480 r = r600_cp_load_microcode(rdev);
@@ -2512,7 +2518,7 @@ int r600_resume(struct radeon_device *rdev)
2512 return r; 2518 return r;
2513 } 2519 }
2514 2520
2515 r = r600_ib_test(rdev); 2521 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
2516 if (r) { 2522 if (r) {
2517 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 2523 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2518 return r; 2524 return r;
@@ -2608,7 +2614,7 @@ int r600_init(struct radeon_device *rdev)
2608 return r; 2614 return r;
2609 2615
2610 rdev->cp.ring_obj = NULL; 2616 rdev->cp.ring_obj = NULL;
2611 r600_ring_init(rdev, 1024 * 1024); 2617 r600_ring_init(rdev, &rdev->cp, 1024 * 1024);
2612 2618
2613 rdev->ih.ring_obj = NULL; 2619 rdev->ih.ring_obj = NULL;
2614 r600_ih_ring_init(rdev, 64 * 1024); 2620 r600_ih_ring_init(rdev, 64 * 1024);
@@ -2634,7 +2640,7 @@ int r600_init(struct radeon_device *rdev)
2634 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 2640 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2635 rdev->accel_working = false; 2641 rdev->accel_working = false;
2636 } else { 2642 } else {
2637 r = r600_ib_test(rdev); 2643 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
2638 if (r) { 2644 if (r) {
2639 dev_err(rdev->dev, "IB test failed (%d).\n", r); 2645 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2640 rdev->accel_working = false; 2646 rdev->accel_working = false;
@@ -2675,18 +2681,20 @@ void r600_fini(struct radeon_device *rdev)
2675 */ 2681 */
2676void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib) 2682void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2677{ 2683{
2684 struct radeon_cp *cp = &rdev->cp;
2685
2678 /* FIXME: implement */ 2686 /* FIXME: implement */
2679 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 2687 radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2680 radeon_ring_write(rdev, 2688 radeon_ring_write(cp,
2681#ifdef __BIG_ENDIAN 2689#ifdef __BIG_ENDIAN
2682 (2 << 0) | 2690 (2 << 0) |
2683#endif 2691#endif
2684 (ib->gpu_addr & 0xFFFFFFFC)); 2692 (ib->gpu_addr & 0xFFFFFFFC));
2685 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 2693 radeon_ring_write(cp, upper_32_bits(ib->gpu_addr) & 0xFF);
2686 radeon_ring_write(rdev, ib->length_dw); 2694 radeon_ring_write(cp, ib->length_dw);
2687} 2695}
2688 2696
2689int r600_ib_test(struct radeon_device *rdev) 2697int r600_ib_test(struct radeon_device *rdev, int ring)
2690{ 2698{
2691 struct radeon_ib *ib; 2699 struct radeon_ib *ib;
2692 uint32_t scratch; 2700 uint32_t scratch;
@@ -2700,7 +2708,7 @@ int r600_ib_test(struct radeon_device *rdev)
2700 return r; 2708 return r;
2701 } 2709 }
2702 WREG32(scratch, 0xCAFEDEAD); 2710 WREG32(scratch, 0xCAFEDEAD);
2703 r = radeon_ib_get(rdev, &ib); 2711 r = radeon_ib_get(rdev, ring, &ib);
2704 if (r) { 2712 if (r) {
2705 DRM_ERROR("radeon: failed to get ib (%d).\n", r); 2713 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2706 return r; 2714 return r;
@@ -2741,7 +2749,7 @@ int r600_ib_test(struct radeon_device *rdev)
2741 DRM_UDELAY(1); 2749 DRM_UDELAY(1);
2742 } 2750 }
2743 if (i < rdev->usec_timeout) { 2751 if (i < rdev->usec_timeout) {
2744 DRM_INFO("ib test succeeded in %u usecs\n", i); 2752 DRM_INFO("ib test on ring %d succeeded in %u usecs\n", ib->fence->ring, i);
2745 } else { 2753 } else {
2746 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n", 2754 DRM_ERROR("radeon: ib test failed (scratch(0x%04X)=0x%08X)\n",
2747 scratch, tmp); 2755 scratch, tmp);
@@ -3514,21 +3522,22 @@ static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3514 struct drm_info_node *node = (struct drm_info_node *) m->private; 3522 struct drm_info_node *node = (struct drm_info_node *) m->private;
3515 struct drm_device *dev = node->minor->dev; 3523 struct drm_device *dev = node->minor->dev;
3516 struct radeon_device *rdev = dev->dev_private; 3524 struct radeon_device *rdev = dev->dev_private;
3525 struct radeon_cp *cp = &rdev->cp;
3517 unsigned count, i, j; 3526 unsigned count, i, j;
3518 3527
3519 radeon_ring_free_size(rdev); 3528 radeon_ring_free_size(rdev, cp);
3520 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw; 3529 count = (cp->ring_size / 4) - cp->ring_free_dw;
3521 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT)); 3530 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3522 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR)); 3531 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3523 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR)); 3532 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3524 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr); 3533 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", cp->wptr);
3525 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr); 3534 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", cp->rptr);
3526 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw); 3535 seq_printf(m, "%u free dwords in ring\n", cp->ring_free_dw);
3527 seq_printf(m, "%u dwords in ring\n", count); 3536 seq_printf(m, "%u dwords in ring\n", count);
3528 i = rdev->cp.rptr; 3537 i = cp->rptr;
3529 for (j = 0; j <= count; j++) { 3538 for (j = 0; j <= count; j++) {
3530 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]); 3539 seq_printf(m, "r[%04d]=0x%08x\n", i, cp->ring[i]);
3531 i = (i + 1) & rdev->cp.ptr_mask; 3540 i = (i + 1) & cp->ptr_mask;
3532 } 3541 }
3533 return 0; 3542 return 0;
3534} 3543}
diff --git a/drivers/gpu/drm/radeon/r600_blit_kms.c b/drivers/gpu/drm/radeon/r600_blit_kms.c
index e09d2818f949..39ae19d38c2f 100644
--- a/drivers/gpu/drm/radeon/r600_blit_kms.c
+++ b/drivers/gpu/drm/radeon/r600_blit_kms.c
@@ -50,6 +50,7 @@ static void
50set_render_target(struct radeon_device *rdev, int format, 50set_render_target(struct radeon_device *rdev, int format,
51 int w, int h, u64 gpu_addr) 51 int w, int h, u64 gpu_addr)
52{ 52{
53 struct radeon_cp *cp = &rdev->cp;
53 u32 cb_color_info; 54 u32 cb_color_info;
54 int pitch, slice; 55 int pitch, slice;
55 56
@@ -63,38 +64,38 @@ set_render_target(struct radeon_device *rdev, int format,
63 pitch = (w / 8) - 1; 64 pitch = (w / 8) - 1;
64 slice = ((w * h) / 64) - 1; 65 slice = ((w * h) / 64) - 1;
65 66
66 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 67 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
67 radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 68 radeon_ring_write(cp, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
68 radeon_ring_write(rdev, gpu_addr >> 8); 69 radeon_ring_write(cp, gpu_addr >> 8);
69 70
70 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) { 71 if (rdev->family > CHIP_R600 && rdev->family < CHIP_RV770) {
71 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0)); 72 radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_BASE_UPDATE, 0));
72 radeon_ring_write(rdev, 2 << 0); 73 radeon_ring_write(cp, 2 << 0);
73 } 74 }
74 75
75 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 76 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
76 radeon_ring_write(rdev, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 77 radeon_ring_write(cp, (CB_COLOR0_SIZE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
77 radeon_ring_write(rdev, (pitch << 0) | (slice << 10)); 78 radeon_ring_write(cp, (pitch << 0) | (slice << 10));
78 79
79 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 80 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
80 radeon_ring_write(rdev, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 81 radeon_ring_write(cp, (CB_COLOR0_VIEW - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
81 radeon_ring_write(rdev, 0); 82 radeon_ring_write(cp, 0);
82 83
83 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 84 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
84 radeon_ring_write(rdev, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 85 radeon_ring_write(cp, (CB_COLOR0_INFO - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
85 radeon_ring_write(rdev, cb_color_info); 86 radeon_ring_write(cp, cb_color_info);
86 87
87 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 88 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
88 radeon_ring_write(rdev, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 89 radeon_ring_write(cp, (CB_COLOR0_TILE - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
89 radeon_ring_write(rdev, 0); 90 radeon_ring_write(cp, 0);
90 91
91 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 92 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
92 radeon_ring_write(rdev, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 93 radeon_ring_write(cp, (CB_COLOR0_FRAG - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
93 radeon_ring_write(rdev, 0); 94 radeon_ring_write(cp, 0);
94 95
95 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 96 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
96 radeon_ring_write(rdev, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 97 radeon_ring_write(cp, (CB_COLOR0_MASK - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
97 radeon_ring_write(rdev, 0); 98 radeon_ring_write(cp, 0);
98} 99}
99 100
100/* emits 5dw */ 101/* emits 5dw */
@@ -103,6 +104,7 @@ cp_set_surface_sync(struct radeon_device *rdev,
103 u32 sync_type, u32 size, 104 u32 sync_type, u32 size,
104 u64 mc_addr) 105 u64 mc_addr)
105{ 106{
107 struct radeon_cp *cp = &rdev->cp;
106 u32 cp_coher_size; 108 u32 cp_coher_size;
107 109
108 if (size == 0xffffffff) 110 if (size == 0xffffffff)
@@ -110,17 +112,18 @@ cp_set_surface_sync(struct radeon_device *rdev,
110 else 112 else
111 cp_coher_size = ((size + 255) >> 8); 113 cp_coher_size = ((size + 255) >> 8);
112 114
113 radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); 115 radeon_ring_write(cp, PACKET3(PACKET3_SURFACE_SYNC, 3));
114 radeon_ring_write(rdev, sync_type); 116 radeon_ring_write(cp, sync_type);
115 radeon_ring_write(rdev, cp_coher_size); 117 radeon_ring_write(cp, cp_coher_size);
116 radeon_ring_write(rdev, mc_addr >> 8); 118 radeon_ring_write(cp, mc_addr >> 8);
117 radeon_ring_write(rdev, 10); /* poll interval */ 119 radeon_ring_write(cp, 10); /* poll interval */
118} 120}
119 121
120/* emits 21dw + 1 surface sync = 26dw */ 122/* emits 21dw + 1 surface sync = 26dw */
121static void 123static void
122set_shaders(struct radeon_device *rdev) 124set_shaders(struct radeon_device *rdev)
123{ 125{
126 struct radeon_cp *cp = &rdev->cp;
124 u64 gpu_addr; 127 u64 gpu_addr;
125 u32 sq_pgm_resources; 128 u32 sq_pgm_resources;
126 129
@@ -129,35 +132,35 @@ set_shaders(struct radeon_device *rdev)
129 132
130 /* VS */ 133 /* VS */
131 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 134 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
132 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 135 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
133 radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 136 radeon_ring_write(cp, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
134 radeon_ring_write(rdev, gpu_addr >> 8); 137 radeon_ring_write(cp, gpu_addr >> 8);
135 138
136 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 139 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
137 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 140 radeon_ring_write(cp, (SQ_PGM_RESOURCES_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
138 radeon_ring_write(rdev, sq_pgm_resources); 141 radeon_ring_write(cp, sq_pgm_resources);
139 142
140 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 143 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
141 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 144 radeon_ring_write(cp, (SQ_PGM_CF_OFFSET_VS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
142 radeon_ring_write(rdev, 0); 145 radeon_ring_write(cp, 0);
143 146
144 /* PS */ 147 /* PS */
145 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; 148 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset;
146 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 149 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
147 radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 150 radeon_ring_write(cp, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
148 radeon_ring_write(rdev, gpu_addr >> 8); 151 radeon_ring_write(cp, gpu_addr >> 8);
149 152
150 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 153 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
151 radeon_ring_write(rdev, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 154 radeon_ring_write(cp, (SQ_PGM_RESOURCES_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
152 radeon_ring_write(rdev, sq_pgm_resources | (1 << 28)); 155 radeon_ring_write(cp, sq_pgm_resources | (1 << 28));
153 156
154 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 157 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
155 radeon_ring_write(rdev, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 158 radeon_ring_write(cp, (SQ_PGM_EXPORTS_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
156 radeon_ring_write(rdev, 2); 159 radeon_ring_write(cp, 2);
157 160
158 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 1)); 161 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
159 radeon_ring_write(rdev, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 162 radeon_ring_write(cp, (SQ_PGM_CF_OFFSET_PS - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
160 radeon_ring_write(rdev, 0); 163 radeon_ring_write(cp, 0);
161 164
162 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; 165 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset;
163 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); 166 cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr);
@@ -167,6 +170,7 @@ set_shaders(struct radeon_device *rdev)
167static void 170static void
168set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) 171set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
169{ 172{
173 struct radeon_cp *cp = &rdev->cp;
170 u32 sq_vtx_constant_word2; 174 u32 sq_vtx_constant_word2;
171 175
172 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) | 176 sq_vtx_constant_word2 = SQ_VTXC_BASE_ADDR_HI(upper_32_bits(gpu_addr) & 0xff) |
@@ -175,15 +179,15 @@ set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr)
175 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32); 179 sq_vtx_constant_word2 |= SQ_VTXC_ENDIAN_SWAP(SQ_ENDIAN_8IN32);
176#endif 180#endif
177 181
178 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); 182 radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 7));
179 radeon_ring_write(rdev, 0x460); 183 radeon_ring_write(cp, 0x460);
180 radeon_ring_write(rdev, gpu_addr & 0xffffffff); 184 radeon_ring_write(cp, gpu_addr & 0xffffffff);
181 radeon_ring_write(rdev, 48 - 1); 185 radeon_ring_write(cp, 48 - 1);
182 radeon_ring_write(rdev, sq_vtx_constant_word2); 186 radeon_ring_write(cp, sq_vtx_constant_word2);
183 radeon_ring_write(rdev, 1 << 0); 187 radeon_ring_write(cp, 1 << 0);
184 radeon_ring_write(rdev, 0); 188 radeon_ring_write(cp, 0);
185 radeon_ring_write(rdev, 0); 189 radeon_ring_write(cp, 0);
186 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); 190 radeon_ring_write(cp, SQ_TEX_VTX_VALID_BUFFER << 30);
187 191
188 if ((rdev->family == CHIP_RV610) || 192 if ((rdev->family == CHIP_RV610) ||
189 (rdev->family == CHIP_RV620) || 193 (rdev->family == CHIP_RV620) ||
@@ -203,6 +207,7 @@ set_tex_resource(struct radeon_device *rdev,
203 int format, int w, int h, int pitch, 207 int format, int w, int h, int pitch,
204 u64 gpu_addr, u32 size) 208 u64 gpu_addr, u32 size)
205{ 209{
210 struct radeon_cp *cp = &rdev->cp;
206 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4; 211 uint32_t sq_tex_resource_word0, sq_tex_resource_word1, sq_tex_resource_word4;
207 212
208 if (h < 1) 213 if (h < 1)
@@ -225,15 +230,15 @@ set_tex_resource(struct radeon_device *rdev,
225 cp_set_surface_sync(rdev, 230 cp_set_surface_sync(rdev,
226 PACKET3_TC_ACTION_ENA, size, gpu_addr); 231 PACKET3_TC_ACTION_ENA, size, gpu_addr);
227 232
228 radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 7)); 233 radeon_ring_write(cp, PACKET3(PACKET3_SET_RESOURCE, 7));
229 radeon_ring_write(rdev, 0); 234 radeon_ring_write(cp, 0);
230 radeon_ring_write(rdev, sq_tex_resource_word0); 235 radeon_ring_write(cp, sq_tex_resource_word0);
231 radeon_ring_write(rdev, sq_tex_resource_word1); 236 radeon_ring_write(cp, sq_tex_resource_word1);
232 radeon_ring_write(rdev, gpu_addr >> 8); 237 radeon_ring_write(cp, gpu_addr >> 8);
233 radeon_ring_write(rdev, gpu_addr >> 8); 238 radeon_ring_write(cp, gpu_addr >> 8);
234 radeon_ring_write(rdev, sq_tex_resource_word4); 239 radeon_ring_write(cp, sq_tex_resource_word4);
235 radeon_ring_write(rdev, 0); 240 radeon_ring_write(cp, 0);
236 radeon_ring_write(rdev, SQ_TEX_VTX_VALID_TEXTURE << 30); 241 radeon_ring_write(cp, SQ_TEX_VTX_VALID_TEXTURE << 30);
237} 242}
238 243
239/* emits 12 */ 244/* emits 12 */
@@ -241,43 +246,45 @@ static void
241set_scissors(struct radeon_device *rdev, int x1, int y1, 246set_scissors(struct radeon_device *rdev, int x1, int y1,
242 int x2, int y2) 247 int x2, int y2)
243{ 248{
244 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 249 struct radeon_cp *cp = &rdev->cp;
245 radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 250 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
246 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); 251 radeon_ring_write(cp, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
247 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); 252 radeon_ring_write(cp, (x1 << 0) | (y1 << 16));
248 253 radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
249 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 254
250 radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 255 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
251 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); 256 radeon_ring_write(cp, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
252 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); 257 radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
253 258 radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
254 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); 259
255 radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2); 260 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
256 radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); 261 radeon_ring_write(cp, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_OFFSET) >> 2);
257 radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); 262 radeon_ring_write(cp, (x1 << 0) | (y1 << 16) | (1 << 31));
263 radeon_ring_write(cp, (x2 << 0) | (y2 << 16));
258} 264}
259 265
260/* emits 10 */ 266/* emits 10 */
261static void 267static void
262draw_auto(struct radeon_device *rdev) 268draw_auto(struct radeon_device *rdev)
263{ 269{
264 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 270 struct radeon_cp *cp = &rdev->cp;
265 radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 271 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 1));
266 radeon_ring_write(rdev, DI_PT_RECTLIST); 272 radeon_ring_write(cp, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
273 radeon_ring_write(cp, DI_PT_RECTLIST);
267 274
268 radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); 275 radeon_ring_write(cp, PACKET3(PACKET3_INDEX_TYPE, 0));
269 radeon_ring_write(rdev, 276 radeon_ring_write(cp,
270#ifdef __BIG_ENDIAN 277#ifdef __BIG_ENDIAN
271 (2 << 2) | 278 (2 << 2) |
272#endif 279#endif
273 DI_INDEX_SIZE_16_BIT); 280 DI_INDEX_SIZE_16_BIT);
274 281
275 radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); 282 radeon_ring_write(cp, PACKET3(PACKET3_NUM_INSTANCES, 0));
276 radeon_ring_write(rdev, 1); 283 radeon_ring_write(cp, 1);
277 284
278 radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); 285 radeon_ring_write(cp, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1));
279 radeon_ring_write(rdev, 3); 286 radeon_ring_write(cp, 3);
280 radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); 287 radeon_ring_write(cp, DI_SRC_SEL_AUTO_INDEX);
281 288
282} 289}
283 290
@@ -285,6 +292,7 @@ draw_auto(struct radeon_device *rdev)
285static void 292static void
286set_default_state(struct radeon_device *rdev) 293set_default_state(struct radeon_device *rdev)
287{ 294{
295 struct radeon_cp *cp = &rdev->cp;
288 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2; 296 u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2;
289 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2; 297 u32 sq_thread_resource_mgmt, sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2;
290 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs; 298 int num_ps_gprs, num_vs_gprs, num_temp_gprs, num_gs_gprs, num_es_gprs;
@@ -440,24 +448,24 @@ set_default_state(struct radeon_device *rdev)
440 /* emit an IB pointing at default state */ 448 /* emit an IB pointing at default state */
441 dwords = ALIGN(rdev->r600_blit.state_len, 0x10); 449 dwords = ALIGN(rdev->r600_blit.state_len, 0x10);
442 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; 450 gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset;
443 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 451 radeon_ring_write(cp, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
444 radeon_ring_write(rdev, 452 radeon_ring_write(cp,
445#ifdef __BIG_ENDIAN 453#ifdef __BIG_ENDIAN
446 (2 << 0) | 454 (2 << 0) |
447#endif 455#endif
448 (gpu_addr & 0xFFFFFFFC)); 456 (gpu_addr & 0xFFFFFFFC));
449 radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); 457 radeon_ring_write(cp, upper_32_bits(gpu_addr) & 0xFF);
450 radeon_ring_write(rdev, dwords); 458 radeon_ring_write(cp, dwords);
451 459
452 /* SQ config */ 460 /* SQ config */
453 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 6)); 461 radeon_ring_write(cp, PACKET3(PACKET3_SET_CONFIG_REG, 6));
454 radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2); 462 radeon_ring_write(cp, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
455 radeon_ring_write(rdev, sq_config); 463 radeon_ring_write(cp, sq_config);
456 radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); 464 radeon_ring_write(cp, sq_gpr_resource_mgmt_1);
457 radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); 465 radeon_ring_write(cp, sq_gpr_resource_mgmt_2);
458 radeon_ring_write(rdev, sq_thread_resource_mgmt); 466 radeon_ring_write(cp, sq_thread_resource_mgmt);
459 radeon_ring_write(rdev, sq_stack_resource_mgmt_1); 467 radeon_ring_write(cp, sq_stack_resource_mgmt_1);
460 radeon_ring_write(rdev, sq_stack_resource_mgmt_2); 468 radeon_ring_write(cp, sq_stack_resource_mgmt_2);
461} 469}
462 470
463static uint32_t i2f(uint32_t input) 471static uint32_t i2f(uint32_t input)
@@ -614,7 +622,7 @@ void r600_blit_fini(struct radeon_device *rdev)
614static int r600_vb_ib_get(struct radeon_device *rdev) 622static int r600_vb_ib_get(struct radeon_device *rdev)
615{ 623{
616 int r; 624 int r;
617 r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); 625 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->r600_blit.vb_ib);
618 if (r) { 626 if (r) {
619 DRM_ERROR("failed to get IB for vertex buffer\n"); 627 DRM_ERROR("failed to get IB for vertex buffer\n");
620 return r; 628 return r;
@@ -679,6 +687,7 @@ static unsigned r600_blit_create_rect(unsigned num_gpu_pages,
679 687
680int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages) 688int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages)
681{ 689{
690 struct radeon_cp *cp = &rdev->cp;
682 int r; 691 int r;
683 int ring_size; 692 int ring_size;
684 int num_loops = 0; 693 int num_loops = 0;
@@ -699,7 +708,7 @@ int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages)
699 /* calculate number of loops correctly */ 708 /* calculate number of loops correctly */
700 ring_size = num_loops * dwords_per_loop; 709 ring_size = num_loops * dwords_per_loop;
701 ring_size += rdev->r600_blit.ring_size_common; 710 ring_size += rdev->r600_blit.ring_size_common;
702 r = radeon_ring_lock(rdev, ring_size); 711 r = radeon_ring_lock(rdev, cp, ring_size);
703 if (r) 712 if (r)
704 return r; 713 return r;
705 714
@@ -718,7 +727,7 @@ void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence)
718 if (fence) 727 if (fence)
719 r = radeon_fence_emit(rdev, fence); 728 r = radeon_fence_emit(rdev, fence);
720 729
721 radeon_ring_unlock_commit(rdev); 730 radeon_ring_unlock_commit(rdev, &rdev->cp);
722} 731}
723 732
724void r600_kms_blit_copy(struct radeon_device *rdev, 733void r600_kms_blit_copy(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 6d84c64759e9..5bf8603f3956 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -230,6 +230,8 @@ void radeon_fence_unref(struct radeon_fence **fence);
230/* 230/*
231 * Semaphores. 231 * Semaphores.
232 */ 232 */
233struct radeon_cp;
234
233struct radeon_semaphore_driver { 235struct radeon_semaphore_driver {
234 rwlock_t lock; 236 rwlock_t lock;
235 struct list_head free; 237 struct list_head free;
@@ -585,7 +587,7 @@ struct r600_blit {
585 587
586void r600_blit_suspend(struct radeon_device *rdev); 588void r600_blit_suspend(struct radeon_device *rdev);
587 589
588int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 590int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib);
589void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 591void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
590int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 592int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
591int radeon_ib_pool_init(struct radeon_device *rdev); 593int radeon_ib_pool_init(struct radeon_device *rdev);
@@ -593,15 +595,15 @@ void radeon_ib_pool_fini(struct radeon_device *rdev);
593int radeon_ib_test(struct radeon_device *rdev); 595int radeon_ib_test(struct radeon_device *rdev);
594extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); 596extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
595/* Ring access between begin & end cannot sleep */ 597/* Ring access between begin & end cannot sleep */
596void radeon_ring_free_size(struct radeon_device *rdev); 598void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_cp *cp);
597int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); 599int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw);
598int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); 600int radeon_ring_lock(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw);
599void radeon_ring_commit(struct radeon_device *rdev); 601void radeon_ring_commit(struct radeon_device *rdev, struct radeon_cp *cp);
600void radeon_ring_unlock_commit(struct radeon_device *rdev); 602void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_cp *cp);
601void radeon_ring_unlock_undo(struct radeon_device *rdev); 603void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_cp *cp);
602int radeon_ring_test(struct radeon_device *rdev); 604int radeon_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
603int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); 605int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size);
604void radeon_ring_fini(struct radeon_device *rdev); 606void radeon_ring_fini(struct radeon_device *rdev, struct radeon_cp *cp);
605 607
606 608
607/* 609/*
@@ -930,24 +932,25 @@ struct radeon_asic {
930 int (*resume)(struct radeon_device *rdev); 932 int (*resume)(struct radeon_device *rdev);
931 int (*suspend)(struct radeon_device *rdev); 933 int (*suspend)(struct radeon_device *rdev);
932 void (*vga_set_state)(struct radeon_device *rdev, bool state); 934 void (*vga_set_state)(struct radeon_device *rdev, bool state);
933 bool (*gpu_is_lockup)(struct radeon_device *rdev); 935 bool (*gpu_is_lockup)(struct radeon_device *rdev, struct radeon_cp *cp);
934 int (*asic_reset)(struct radeon_device *rdev); 936 int (*asic_reset)(struct radeon_device *rdev);
935 void (*gart_tlb_flush)(struct radeon_device *rdev); 937 void (*gart_tlb_flush)(struct radeon_device *rdev);
936 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); 938 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
937 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); 939 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
938 void (*cp_fini)(struct radeon_device *rdev); 940 void (*cp_fini)(struct radeon_device *rdev);
939 void (*cp_disable)(struct radeon_device *rdev); 941 void (*cp_disable)(struct radeon_device *rdev);
940 void (*cp_commit)(struct radeon_device *rdev); 942 void (*cp_commit)(struct radeon_device *rdev, struct radeon_cp *cp);
941 void (*ring_start)(struct radeon_device *rdev); 943 void (*ring_start)(struct radeon_device *rdev);
942 int (*ring_test)(struct radeon_device *rdev); 944 int (*ring_test)(struct radeon_device *rdev, struct radeon_cp *cp);
943 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); 945 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
944 int (*irq_set)(struct radeon_device *rdev); 946 int (*irq_set)(struct radeon_device *rdev);
945 int (*irq_process)(struct radeon_device *rdev); 947 int (*irq_process)(struct radeon_device *rdev);
946 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); 948 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
947 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); 949 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
948 void (*semaphore_ring_emit)(struct radeon_device *rdev, 950 void (*semaphore_ring_emit)(struct radeon_device *rdev,
951 struct radeon_cp *cp,
949 struct radeon_semaphore *semaphore, 952 struct radeon_semaphore *semaphore,
950 unsigned ring, bool emit_wait); 953 bool emit_wait);
951 int (*cs_parse)(struct radeon_cs_parser *p); 954 int (*cs_parse)(struct radeon_cs_parser *p);
952 int (*copy_blit)(struct radeon_device *rdev, 955 int (*copy_blit)(struct radeon_device *rdev,
953 uint64_t src_offset, 956 uint64_t src_offset,
@@ -1279,7 +1282,6 @@ struct radeon_device {
1279 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; 1282 struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS];
1280 struct radeon_semaphore_driver semaphore_drv; 1283 struct radeon_semaphore_driver semaphore_drv;
1281 struct radeon_cp cp; 1284 struct radeon_cp cp;
1282 /* cayman compute rings */
1283 struct radeon_cp cp1; 1285 struct radeon_cp cp1;
1284 struct radeon_cp cp2; 1286 struct radeon_cp cp2;
1285 struct radeon_ib_pool ib_pool; 1287 struct radeon_ib_pool ib_pool;
@@ -1463,18 +1465,17 @@ void radeon_atombios_fini(struct radeon_device *rdev);
1463/* 1465/*
1464 * RING helpers. 1466 * RING helpers.
1465 */ 1467 */
1466
1467#if DRM_DEBUG_CODE == 0 1468#if DRM_DEBUG_CODE == 0
1468static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 1469static inline void radeon_ring_write(struct radeon_cp *cp, uint32_t v)
1469{ 1470{
1470 rdev->cp.ring[rdev->cp.wptr++] = v; 1471 cp->ring[cp->wptr++] = v;
1471 rdev->cp.wptr &= rdev->cp.ptr_mask; 1472 cp->wptr &= cp->ptr_mask;
1472 rdev->cp.count_dw--; 1473 cp->count_dw--;
1473 rdev->cp.ring_free_dw--; 1474 cp->ring_free_dw--;
1474} 1475}
1475#else 1476#else
1476/* With debugging this is just too big to inline */ 1477/* With debugging this is just too big to inline */
1477void radeon_ring_write(struct radeon_device *rdev, uint32_t v); 1478void radeon_ring_write(struct radeon_cp *cp, uint32_t v);
1478#endif 1479#endif
1479 1480
1480/* 1481/*
@@ -1486,19 +1487,19 @@ void radeon_ring_write(struct radeon_device *rdev, uint32_t v);
1486#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) 1487#define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1487#define radeon_cs_parse(p) rdev->asic->cs_parse((p)) 1488#define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1488#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) 1489#define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1489#define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) 1490#define radeon_gpu_is_lockup(rdev, cp) (rdev)->asic->gpu_is_lockup((rdev), (cp))
1490#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) 1491#define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1491#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) 1492#define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1492#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) 1493#define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1493#define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) 1494#define radeon_cp_commit(rdev, cp) (rdev)->asic->cp_commit((rdev), (cp))
1494#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) 1495#define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1495#define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) 1496#define radeon_ring_test(rdev, cp) (rdev)->asic->ring_test((rdev), (cp))
1496#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) 1497#define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1497#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) 1498#define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1498#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) 1499#define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1499#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) 1500#define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1500#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) 1501#define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1501#define radeon_semaphore_ring_emit(rdev, semaphore, ring, emit_wait) (rdev)->asic->semaphore_ring_emit((rdev), (semaphore), (ring), (emit_wait)) 1502#define radeon_semaphore_ring_emit(rdev, cp, semaphore, emit_wait) (rdev)->asic->semaphore_ring_emit((rdev), (cp), (semaphore), (emit_wait))
1502#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) 1503#define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1503#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) 1504#define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1504#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) 1505#define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 6b589d5ae436..4f8447557298 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -58,20 +58,21 @@ void r100_fini(struct radeon_device *rdev);
58int r100_suspend(struct radeon_device *rdev); 58int r100_suspend(struct radeon_device *rdev);
59int r100_resume(struct radeon_device *rdev); 59int r100_resume(struct radeon_device *rdev);
60void r100_vga_set_state(struct radeon_device *rdev, bool state); 60void r100_vga_set_state(struct radeon_device *rdev, bool state);
61bool r100_gpu_is_lockup(struct radeon_device *rdev); 61bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
62int r100_asic_reset(struct radeon_device *rdev); 62int r100_asic_reset(struct radeon_device *rdev);
63u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc); 63u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
64void r100_pci_gart_tlb_flush(struct radeon_device *rdev); 64void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
65int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr); 65int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
66void r100_cp_commit(struct radeon_device *rdev); 66void r100_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp);
67void r100_ring_start(struct radeon_device *rdev); 67void r100_ring_start(struct radeon_device *rdev);
68int r100_irq_set(struct radeon_device *rdev); 68int r100_irq_set(struct radeon_device *rdev);
69int r100_irq_process(struct radeon_device *rdev); 69int r100_irq_process(struct radeon_device *rdev);
70void r100_fence_ring_emit(struct radeon_device *rdev, 70void r100_fence_ring_emit(struct radeon_device *rdev,
71 struct radeon_fence *fence); 71 struct radeon_fence *fence);
72void r100_semaphore_ring_emit(struct radeon_device *rdev, 72void r100_semaphore_ring_emit(struct radeon_device *rdev,
73 struct radeon_cp *cp,
73 struct radeon_semaphore *semaphore, 74 struct radeon_semaphore *semaphore,
74 unsigned ring, bool emit_wait); 75 bool emit_wait);
75int r100_cs_parse(struct radeon_cs_parser *p); 76int r100_cs_parse(struct radeon_cs_parser *p);
76void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 77void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
77uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg); 78uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
@@ -86,7 +87,7 @@ int r100_set_surface_reg(struct radeon_device *rdev, int reg,
86void r100_clear_surface_reg(struct radeon_device *rdev, int reg); 87void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
87void r100_bandwidth_update(struct radeon_device *rdev); 88void r100_bandwidth_update(struct radeon_device *rdev);
88void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 89void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
89int r100_ring_test(struct radeon_device *rdev); 90int r100_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
90void r100_hpd_init(struct radeon_device *rdev); 91void r100_hpd_init(struct radeon_device *rdev);
91void r100_hpd_fini(struct radeon_device *rdev); 92void r100_hpd_fini(struct radeon_device *rdev);
92bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd); 93bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
@@ -157,7 +158,7 @@ extern int r300_init(struct radeon_device *rdev);
157extern void r300_fini(struct radeon_device *rdev); 158extern void r300_fini(struct radeon_device *rdev);
158extern int r300_suspend(struct radeon_device *rdev); 159extern int r300_suspend(struct radeon_device *rdev);
159extern int r300_resume(struct radeon_device *rdev); 160extern int r300_resume(struct radeon_device *rdev);
160extern bool r300_gpu_is_lockup(struct radeon_device *rdev); 161extern bool r300_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
161extern int r300_asic_reset(struct radeon_device *rdev); 162extern int r300_asic_reset(struct radeon_device *rdev);
162extern void r300_ring_start(struct radeon_device *rdev); 163extern void r300_ring_start(struct radeon_device *rdev);
163extern void r300_fence_ring_emit(struct radeon_device *rdev, 164extern void r300_fence_ring_emit(struct radeon_device *rdev,
@@ -296,7 +297,7 @@ int r600_resume(struct radeon_device *rdev);
296void r600_vga_set_state(struct radeon_device *rdev, bool state); 297void r600_vga_set_state(struct radeon_device *rdev, bool state);
297int r600_wb_init(struct radeon_device *rdev); 298int r600_wb_init(struct radeon_device *rdev);
298void r600_wb_fini(struct radeon_device *rdev); 299void r600_wb_fini(struct radeon_device *rdev);
299void r600_cp_commit(struct radeon_device *rdev); 300void r600_cp_commit(struct radeon_device *rdev, struct radeon_cp *cp);
300void r600_pcie_gart_tlb_flush(struct radeon_device *rdev); 301void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
301uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg); 302uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
302void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); 303void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
@@ -304,17 +305,18 @@ int r600_cs_parse(struct radeon_cs_parser *p);
304void r600_fence_ring_emit(struct radeon_device *rdev, 305void r600_fence_ring_emit(struct radeon_device *rdev,
305 struct radeon_fence *fence); 306 struct radeon_fence *fence);
306void r600_semaphore_ring_emit(struct radeon_device *rdev, 307void r600_semaphore_ring_emit(struct radeon_device *rdev,
308 struct radeon_cp *cp,
307 struct radeon_semaphore *semaphore, 309 struct radeon_semaphore *semaphore,
308 unsigned ring, bool emit_wait); 310 bool emit_wait);
309bool r600_gpu_is_lockup(struct radeon_device *rdev); 311bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
310int r600_asic_reset(struct radeon_device *rdev); 312int r600_asic_reset(struct radeon_device *rdev);
311int r600_set_surface_reg(struct radeon_device *rdev, int reg, 313int r600_set_surface_reg(struct radeon_device *rdev, int reg,
312 uint32_t tiling_flags, uint32_t pitch, 314 uint32_t tiling_flags, uint32_t pitch,
313 uint32_t offset, uint32_t obj_size); 315 uint32_t offset, uint32_t obj_size);
314void r600_clear_surface_reg(struct radeon_device *rdev, int reg); 316void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
315int r600_ib_test(struct radeon_device *rdev); 317int r600_ib_test(struct radeon_device *rdev, int ring);
316void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 318void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
317int r600_ring_test(struct radeon_device *rdev); 319int r600_ring_test(struct radeon_device *rdev, struct radeon_cp *cp);
318int r600_copy_blit(struct radeon_device *rdev, 320int r600_copy_blit(struct radeon_device *rdev,
319 uint64_t src_offset, uint64_t dst_offset, 321 uint64_t src_offset, uint64_t dst_offset,
320 unsigned num_gpu_pages, struct radeon_fence *fence); 322 unsigned num_gpu_pages, struct radeon_fence *fence);
@@ -334,7 +336,7 @@ extern int r600_get_pcie_lanes(struct radeon_device *rdev);
334bool r600_card_posted(struct radeon_device *rdev); 336bool r600_card_posted(struct radeon_device *rdev);
335void r600_cp_stop(struct radeon_device *rdev); 337void r600_cp_stop(struct radeon_device *rdev);
336int r600_cp_start(struct radeon_device *rdev); 338int r600_cp_start(struct radeon_device *rdev);
337void r600_ring_init(struct radeon_device *rdev, unsigned ring_size); 339void r600_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size);
338int r600_cp_resume(struct radeon_device *rdev); 340int r600_cp_resume(struct radeon_device *rdev);
339void r600_cp_fini(struct radeon_device *rdev); 341void r600_cp_fini(struct radeon_device *rdev);
340int r600_count_pipe_bits(uint32_t val); 342int r600_count_pipe_bits(uint32_t val);
@@ -403,7 +405,7 @@ int evergreen_init(struct radeon_device *rdev);
403void evergreen_fini(struct radeon_device *rdev); 405void evergreen_fini(struct radeon_device *rdev);
404int evergreen_suspend(struct radeon_device *rdev); 406int evergreen_suspend(struct radeon_device *rdev);
405int evergreen_resume(struct radeon_device *rdev); 407int evergreen_resume(struct radeon_device *rdev);
406bool evergreen_gpu_is_lockup(struct radeon_device *rdev); 408bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
407int evergreen_asic_reset(struct radeon_device *rdev); 409int evergreen_asic_reset(struct radeon_device *rdev);
408void evergreen_bandwidth_update(struct radeon_device *rdev); 410void evergreen_bandwidth_update(struct radeon_device *rdev);
409void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib); 411void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
@@ -434,7 +436,7 @@ int cayman_init(struct radeon_device *rdev);
434void cayman_fini(struct radeon_device *rdev); 436void cayman_fini(struct radeon_device *rdev);
435int cayman_suspend(struct radeon_device *rdev); 437int cayman_suspend(struct radeon_device *rdev);
436int cayman_resume(struct radeon_device *rdev); 438int cayman_resume(struct radeon_device *rdev);
437bool cayman_gpu_is_lockup(struct radeon_device *rdev); 439bool cayman_gpu_is_lockup(struct radeon_device *rdev, struct radeon_cp *cp);
438int cayman_asic_reset(struct radeon_device *rdev); 440int cayman_asic_reset(struct radeon_device *rdev);
439 441
440#endif 442#endif
diff --git a/drivers/gpu/drm/radeon/radeon_cs.c b/drivers/gpu/drm/radeon/radeon_cs.c
index aaacadc86ae7..09ef48636e53 100644
--- a/drivers/gpu/drm/radeon/radeon_cs.c
+++ b/drivers/gpu/drm/radeon/radeon_cs.c
@@ -246,7 +246,7 @@ int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
246 radeon_mutex_unlock(&rdev->cs_mutex); 246 radeon_mutex_unlock(&rdev->cs_mutex);
247 return r; 247 return r;
248 } 248 }
249 r = radeon_ib_get(rdev, &parser.ib); 249 r = radeon_ib_get(rdev, RADEON_RING_TYPE_GFX_INDEX, &parser.ib);
250 if (r) { 250 if (r) {
251 DRM_ERROR("Failed to get ib !\n"); 251 DRM_ERROR("Failed to get ib !\n");
252 radeon_cs_parser_fini(&parser, r); 252 radeon_cs_parser_fini(&parser, r);
diff --git a/drivers/gpu/drm/radeon/radeon_fence.c b/drivers/gpu/drm/radeon/radeon_fence.c
index 086b8a399118..9ed0bb100bcb 100644
--- a/drivers/gpu/drm/radeon/radeon_fence.c
+++ b/drivers/gpu/drm/radeon/radeon_fence.c
@@ -269,7 +269,7 @@ retry:
269 * if we experiencing a lockup the value doesn't change 269 * if we experiencing a lockup the value doesn't change
270 */ 270 */
271 if (seq == rdev->fence_drv[fence->ring].last_seq && 271 if (seq == rdev->fence_drv[fence->ring].last_seq &&
272 radeon_gpu_is_lockup(rdev)) { 272 radeon_gpu_is_lockup(rdev, &rdev->cp)) {
273 /* good news we believe it's a lockup */ 273 /* good news we believe it's a lockup */
274 printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n", 274 printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
275 fence->seq, seq); 275 fence->seq, seq);
diff --git a/drivers/gpu/drm/radeon/radeon_gem.c b/drivers/gpu/drm/radeon/radeon_gem.c
index aa1ca2dea42f..136772ccfe72 100644
--- a/drivers/gpu/drm/radeon/radeon_gem.c
+++ b/drivers/gpu/drm/radeon/radeon_gem.c
@@ -160,8 +160,8 @@ int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
160 if (rdev->stollen_vga_memory) 160 if (rdev->stollen_vga_memory)
161 args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory); 161 args->vram_visible -= radeon_bo_size(rdev->stollen_vga_memory);
162 args->vram_visible -= radeon_fbdev_total_size(rdev); 162 args->vram_visible -= radeon_fbdev_total_size(rdev);
163 args->gart_size = rdev->mc.gtt_size - rdev->cp.ring_size - 4096 - 163 args->gart_size = rdev->mc.gtt_size - 4096 - RADEON_IB_POOL_SIZE*64*1024;
164 RADEON_IB_POOL_SIZE*64*1024; 164 args->gart_size -= rdev->cp.ring_size;
165 return 0; 165 return 0;
166} 166}
167 167
diff --git a/drivers/gpu/drm/radeon/radeon_pm.c b/drivers/gpu/drm/radeon/radeon_pm.c
index 19ed2c6c424a..73b6714d615b 100644
--- a/drivers/gpu/drm/radeon/radeon_pm.c
+++ b/drivers/gpu/drm/radeon/radeon_pm.c
@@ -252,7 +252,8 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
252 252
253 mutex_lock(&rdev->ddev->struct_mutex); 253 mutex_lock(&rdev->ddev->struct_mutex);
254 mutex_lock(&rdev->vram_mutex); 254 mutex_lock(&rdev->vram_mutex);
255 mutex_lock(&rdev->cp.mutex); 255 if (rdev->cp.ring_obj)
256 mutex_lock(&rdev->cp.mutex);
256 257
257 /* gui idle int has issues on older chips it seems */ 258 /* gui idle int has issues on older chips it seems */
258 if (rdev->family >= CHIP_R600) { 259 if (rdev->family >= CHIP_R600) {
@@ -268,12 +269,13 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
268 radeon_irq_set(rdev); 269 radeon_irq_set(rdev);
269 } 270 }
270 } else { 271 } else {
271 if (rdev->cp.ready) { 272 struct radeon_cp *cp = &rdev->cp;
273 if (cp->ready) {
272 struct radeon_fence *fence; 274 struct radeon_fence *fence;
273 radeon_ring_alloc(rdev, 64); 275 radeon_ring_alloc(rdev, cp, 64);
274 radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 276 radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX);
275 radeon_fence_emit(rdev, fence); 277 radeon_fence_emit(rdev, fence);
276 radeon_ring_commit(rdev); 278 radeon_ring_commit(rdev, cp);
277 radeon_fence_wait(fence, false); 279 radeon_fence_wait(fence, false);
278 radeon_fence_unref(&fence); 280 radeon_fence_unref(&fence);
279 } 281 }
@@ -307,7 +309,8 @@ static void radeon_pm_set_clocks(struct radeon_device *rdev)
307 309
308 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE; 310 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
309 311
310 mutex_unlock(&rdev->cp.mutex); 312 if (rdev->cp.ring_obj)
313 mutex_unlock(&rdev->cp.mutex);
311 mutex_unlock(&rdev->vram_mutex); 314 mutex_unlock(&rdev->vram_mutex);
312 mutex_unlock(&rdev->ddev->struct_mutex); 315 mutex_unlock(&rdev->ddev->struct_mutex);
313} 316}
diff --git a/drivers/gpu/drm/radeon/radeon_ring.c b/drivers/gpu/drm/radeon/radeon_ring.c
index c232317b1dd2..bc8a5807f1a4 100644
--- a/drivers/gpu/drm/radeon/radeon_ring.c
+++ b/drivers/gpu/drm/radeon/radeon_ring.c
@@ -60,17 +60,17 @@ u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
60 return idx_value; 60 return idx_value;
61} 61}
62 62
63void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 63void radeon_ring_write(struct radeon_cp *cp, uint32_t v)
64{ 64{
65#if DRM_DEBUG_CODE 65#if DRM_DEBUG_CODE
66 if (rdev->cp.count_dw <= 0) { 66 if (cp->count_dw <= 0) {
67 DRM_ERROR("radeon: writting more dword to ring than expected !\n"); 67 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
68 } 68 }
69#endif 69#endif
70 rdev->cp.ring[rdev->cp.wptr++] = v; 70 cp->ring[cp->wptr++] = v;
71 rdev->cp.wptr &= rdev->cp.ptr_mask; 71 cp->wptr &= cp->ptr_mask;
72 rdev->cp.count_dw--; 72 cp->count_dw--;
73 rdev->cp.ring_free_dw--; 73 cp->ring_free_dw--;
74} 74}
75 75
76void radeon_ib_bogus_cleanup(struct radeon_device *rdev) 76void radeon_ib_bogus_cleanup(struct radeon_device *rdev)
@@ -106,14 +106,14 @@ void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib)
106/* 106/*
107 * IB. 107 * IB.
108 */ 108 */
109int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) 109int radeon_ib_get(struct radeon_device *rdev, int ring, struct radeon_ib **ib)
110{ 110{
111 struct radeon_fence *fence; 111 struct radeon_fence *fence;
112 struct radeon_ib *nib; 112 struct radeon_ib *nib;
113 int r = 0, i, c; 113 int r = 0, i, c;
114 114
115 *ib = NULL; 115 *ib = NULL;
116 r = radeon_fence_create(rdev, &fence, RADEON_RING_TYPE_GFX_INDEX); 116 r = radeon_fence_create(rdev, &fence, ring);
117 if (r) { 117 if (r) {
118 dev_err(rdev->dev, "failed to create fence for new IB\n"); 118 dev_err(rdev->dev, "failed to create fence for new IB\n");
119 return r; 119 return r;
@@ -178,16 +178,17 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
178 178
179int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) 179int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
180{ 180{
181 struct radeon_cp *cp = &rdev->cp;
181 int r = 0; 182 int r = 0;
182 183
183 if (!ib->length_dw || !rdev->cp.ready) { 184 if (!ib->length_dw || !cp->ready) {
184 /* TODO: Nothings in the ib we should report. */ 185 /* TODO: Nothings in the ib we should report. */
185 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx); 186 DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
186 return -EINVAL; 187 return -EINVAL;
187 } 188 }
188 189
189 /* 64 dwords should be enough for fence too */ 190 /* 64 dwords should be enough for fence too */
190 r = radeon_ring_lock(rdev, 64); 191 r = radeon_ring_lock(rdev, cp, 64);
191 if (r) { 192 if (r) {
192 DRM_ERROR("radeon: scheduling IB failed (%d).\n", r); 193 DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
193 return r; 194 return r;
@@ -198,7 +199,7 @@ int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
198 /* once scheduled IB is considered free and protected by the fence */ 199 /* once scheduled IB is considered free and protected by the fence */
199 ib->free = true; 200 ib->free = true;
200 mutex_unlock(&rdev->ib_pool.mutex); 201 mutex_unlock(&rdev->ib_pool.mutex);
201 radeon_ring_unlock_commit(rdev); 202 radeon_ring_unlock_commit(rdev, cp);
202 return 0; 203 return 0;
203} 204}
204 205
@@ -283,7 +284,7 @@ void radeon_ib_pool_fini(struct radeon_device *rdev)
283/* 284/*
284 * Ring. 285 * Ring.
285 */ 286 */
286void radeon_ring_free_size(struct radeon_device *rdev) 287void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_cp *cp)
287{ 288{
288 if (rdev->wb.enabled) 289 if (rdev->wb.enabled)
289 rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]); 290 rdev->cp.rptr = le32_to_cpu(rdev->wb.wb[RADEON_WB_CP_RPTR_OFFSET/4]);
@@ -294,122 +295,123 @@ void radeon_ring_free_size(struct radeon_device *rdev)
294 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 295 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
295 } 296 }
296 /* This works because ring_size is a power of 2 */ 297 /* This works because ring_size is a power of 2 */
297 rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); 298 cp->ring_free_dw = (cp->rptr + (cp->ring_size / 4));
298 rdev->cp.ring_free_dw -= rdev->cp.wptr; 299 cp->ring_free_dw -= cp->wptr;
299 rdev->cp.ring_free_dw &= rdev->cp.ptr_mask; 300 cp->ring_free_dw &= cp->ptr_mask;
300 if (!rdev->cp.ring_free_dw) { 301 if (!cp->ring_free_dw) {
301 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; 302 cp->ring_free_dw = cp->ring_size / 4;
302 } 303 }
303} 304}
304 305
305int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw) 306
307int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw)
306{ 308{
307 int r; 309 int r;
308 310
309 /* Align requested size with padding so unlock_commit can 311 /* Align requested size with padding so unlock_commit can
310 * pad safely */ 312 * pad safely */
311 ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask; 313 ndw = (ndw + cp->align_mask) & ~cp->align_mask;
312 while (ndw > (rdev->cp.ring_free_dw - 1)) { 314 while (ndw > (cp->ring_free_dw - 1)) {
313 radeon_ring_free_size(rdev); 315 radeon_ring_free_size(rdev, cp);
314 if (ndw < rdev->cp.ring_free_dw) { 316 if (ndw < cp->ring_free_dw) {
315 break; 317 break;
316 } 318 }
317 r = radeon_fence_wait_next(rdev, RADEON_RING_TYPE_GFX_INDEX); 319 r = radeon_fence_wait_next(rdev, RADEON_RING_TYPE_GFX_INDEX);
318 if (r) 320 if (r)
319 return r; 321 return r;
320 } 322 }
321 rdev->cp.count_dw = ndw; 323 cp->count_dw = ndw;
322 rdev->cp.wptr_old = rdev->cp.wptr; 324 cp->wptr_old = cp->wptr;
323 return 0; 325 return 0;
324} 326}
325 327
326int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw) 328int radeon_ring_lock(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ndw)
327{ 329{
328 int r; 330 int r;
329 331
330 mutex_lock(&rdev->cp.mutex); 332 mutex_lock(&cp->mutex);
331 r = radeon_ring_alloc(rdev, ndw); 333 r = radeon_ring_alloc(rdev, cp, ndw);
332 if (r) { 334 if (r) {
333 mutex_unlock(&rdev->cp.mutex); 335 mutex_unlock(&cp->mutex);
334 return r; 336 return r;
335 } 337 }
336 return 0; 338 return 0;
337} 339}
338 340
339void radeon_ring_commit(struct radeon_device *rdev) 341void radeon_ring_commit(struct radeon_device *rdev, struct radeon_cp *cp)
340{ 342{
341 unsigned count_dw_pad; 343 unsigned count_dw_pad;
342 unsigned i; 344 unsigned i;
343 345
344 /* We pad to match fetch size */ 346 /* We pad to match fetch size */
345 count_dw_pad = (rdev->cp.align_mask + 1) - 347 count_dw_pad = (cp->align_mask + 1) -
346 (rdev->cp.wptr & rdev->cp.align_mask); 348 (cp->wptr & cp->align_mask);
347 for (i = 0; i < count_dw_pad; i++) { 349 for (i = 0; i < count_dw_pad; i++) {
348 radeon_ring_write(rdev, 2 << 30); 350 radeon_ring_write(cp, 2 << 30);
349 } 351 }
350 DRM_MEMORYBARRIER(); 352 DRM_MEMORYBARRIER();
351 radeon_cp_commit(rdev); 353 radeon_cp_commit(rdev, cp);
352} 354}
353 355
354void radeon_ring_unlock_commit(struct radeon_device *rdev) 356void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_cp *cp)
355{ 357{
356 radeon_ring_commit(rdev); 358 radeon_ring_commit(rdev, cp);
357 mutex_unlock(&rdev->cp.mutex); 359 mutex_unlock(&cp->mutex);
358} 360}
359 361
360void radeon_ring_unlock_undo(struct radeon_device *rdev) 362void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_cp *cp)
361{ 363{
362 rdev->cp.wptr = rdev->cp.wptr_old; 364 cp->wptr = cp->wptr_old;
363 mutex_unlock(&rdev->cp.mutex); 365 mutex_unlock(&cp->mutex);
364} 366}
365 367
366int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) 368int radeon_ring_init(struct radeon_device *rdev, struct radeon_cp *cp, unsigned ring_size)
367{ 369{
368 int r; 370 int r;
369 371
370 rdev->cp.ring_size = ring_size; 372 cp->ring_size = ring_size;
371 /* Allocate ring buffer */ 373 /* Allocate ring buffer */
372 if (rdev->cp.ring_obj == NULL) { 374 if (cp->ring_obj == NULL) {
373 r = radeon_bo_create(rdev, rdev->cp.ring_size, PAGE_SIZE, true, 375 r = radeon_bo_create(rdev, cp->ring_size, PAGE_SIZE, true,
374 RADEON_GEM_DOMAIN_GTT, 376 RADEON_GEM_DOMAIN_GTT,
375 &rdev->cp.ring_obj); 377 &cp->ring_obj);
376 if (r) { 378 if (r) {
377 dev_err(rdev->dev, "(%d) ring create failed\n", r); 379 dev_err(rdev->dev, "(%d) ring create failed\n", r);
378 return r; 380 return r;
379 } 381 }
380 r = radeon_bo_reserve(rdev->cp.ring_obj, false); 382 r = radeon_bo_reserve(cp->ring_obj, false);
381 if (unlikely(r != 0)) 383 if (unlikely(r != 0))
382 return r; 384 return r;
383 r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT, 385 r = radeon_bo_pin(cp->ring_obj, RADEON_GEM_DOMAIN_GTT,
384 &rdev->cp.gpu_addr); 386 &cp->gpu_addr);
385 if (r) { 387 if (r) {
386 radeon_bo_unreserve(rdev->cp.ring_obj); 388 radeon_bo_unreserve(cp->ring_obj);
387 dev_err(rdev->dev, "(%d) ring pin failed\n", r); 389 dev_err(rdev->dev, "(%d) ring pin failed\n", r);
388 return r; 390 return r;
389 } 391 }
390 r = radeon_bo_kmap(rdev->cp.ring_obj, 392 r = radeon_bo_kmap(cp->ring_obj,
391 (void **)&rdev->cp.ring); 393 (void **)&cp->ring);
392 radeon_bo_unreserve(rdev->cp.ring_obj); 394 radeon_bo_unreserve(cp->ring_obj);
393 if (r) { 395 if (r) {
394 dev_err(rdev->dev, "(%d) ring map failed\n", r); 396 dev_err(rdev->dev, "(%d) ring map failed\n", r);
395 return r; 397 return r;
396 } 398 }
397 } 399 }
398 rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1; 400 cp->ptr_mask = (cp->ring_size / 4) - 1;
399 rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; 401 cp->ring_free_dw = cp->ring_size / 4;
400 return 0; 402 return 0;
401} 403}
402 404
403void radeon_ring_fini(struct radeon_device *rdev) 405void radeon_ring_fini(struct radeon_device *rdev, struct radeon_cp *cp)
404{ 406{
405 int r; 407 int r;
406 struct radeon_bo *ring_obj; 408 struct radeon_bo *ring_obj;
407 409
408 mutex_lock(&rdev->cp.mutex); 410 mutex_lock(&cp->mutex);
409 ring_obj = rdev->cp.ring_obj; 411 ring_obj = cp->ring_obj;
410 rdev->cp.ring = NULL; 412 cp->ring = NULL;
411 rdev->cp.ring_obj = NULL; 413 cp->ring_obj = NULL;
412 mutex_unlock(&rdev->cp.mutex); 414 mutex_unlock(&cp->mutex);
413 415
414 if (ring_obj) { 416 if (ring_obj) {
415 r = radeon_bo_reserve(ring_obj, false); 417 r = radeon_bo_reserve(ring_obj, false);
@@ -422,7 +424,6 @@ void radeon_ring_fini(struct radeon_device *rdev)
422 } 424 }
423} 425}
424 426
425
426/* 427/*
427 * Debugfs info 428 * Debugfs info
428 */ 429 */
diff --git a/drivers/gpu/drm/radeon/radeon_semaphore.c b/drivers/gpu/drm/radeon/radeon_semaphore.c
index f7d3104de6d4..064694a67824 100644
--- a/drivers/gpu/drm/radeon/radeon_semaphore.c
+++ b/drivers/gpu/drm/radeon/radeon_semaphore.c
@@ -121,13 +121,13 @@ int radeon_semaphore_create(struct radeon_device *rdev,
121void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, 121void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
122 struct radeon_semaphore *semaphore) 122 struct radeon_semaphore *semaphore)
123{ 123{
124 radeon_semaphore_ring_emit(rdev, semaphore, ring, false); 124 radeon_semaphore_ring_emit(rdev, &rdev->cp, semaphore, false);
125} 125}
126 126
127void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 127void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
128 struct radeon_semaphore *semaphore) 128 struct radeon_semaphore *semaphore)
129{ 129{
130 radeon_semaphore_ring_emit(rdev, semaphore, ring, true); 130 radeon_semaphore_ring_emit(rdev, &rdev->cp, semaphore, true);
131} 131}
132 132
133void radeon_semaphore_free(struct radeon_device *rdev, 133void radeon_semaphore_free(struct radeon_device *rdev,
diff --git a/drivers/gpu/drm/radeon/radeon_test.c b/drivers/gpu/drm/radeon/radeon_test.c
index 37f7acb6d5f7..ee6c160ffae9 100644
--- a/drivers/gpu/drm/radeon/radeon_test.c
+++ b/drivers/gpu/drm/radeon/radeon_test.c
@@ -42,7 +42,8 @@ void radeon_test_moves(struct radeon_device *rdev)
42 /* Number of tests = 42 /* Number of tests =
43 * (Total GTT - IB pool - writeback page - ring buffers) / test size 43 * (Total GTT - IB pool - writeback page - ring buffers) / test size
44 */ 44 */
45 n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024 - rdev->cp.ring_size; 45 n = rdev->mc.gtt_size - RADEON_IB_POOL_SIZE*64*1024;
46 n -= rdev->cp.ring_size;
46 if (rdev->wb.wb_obj) 47 if (rdev->wb.wb_obj)
47 n -= RADEON_GPU_PAGE_SIZE; 48 n -= RADEON_GPU_PAGE_SIZE;
48 if (rdev->ih.ring_obj) 49 if (rdev->ih.ring_obj)
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index fd8da02e1ca5..8fe13ba8143a 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -55,44 +55,45 @@ void rv515_debugfs(struct radeon_device *rdev)
55 55
56void rv515_ring_start(struct radeon_device *rdev) 56void rv515_ring_start(struct radeon_device *rdev)
57{ 57{
58 struct radeon_cp *cp = &rdev->cp;
58 int r; 59 int r;
59 60
60 r = radeon_ring_lock(rdev, 64); 61 r = radeon_ring_lock(rdev, cp, 64);
61 if (r) { 62 if (r) {
62 return; 63 return;
63 } 64 }
64 radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0)); 65 radeon_ring_write(cp, PACKET0(ISYNC_CNTL, 0));
65 radeon_ring_write(rdev, 66 radeon_ring_write(cp,
66 ISYNC_ANY2D_IDLE3D | 67 ISYNC_ANY2D_IDLE3D |
67 ISYNC_ANY3D_IDLE2D | 68 ISYNC_ANY3D_IDLE2D |
68 ISYNC_WAIT_IDLEGUI | 69 ISYNC_WAIT_IDLEGUI |
69 ISYNC_CPSCRATCH_IDLEGUI); 70 ISYNC_CPSCRATCH_IDLEGUI);
70 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); 71 radeon_ring_write(cp, PACKET0(WAIT_UNTIL, 0));
71 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 72 radeon_ring_write(cp, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
72 radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0)); 73 radeon_ring_write(cp, PACKET0(R300_DST_PIPE_CONFIG, 0));
73 radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG); 74 radeon_ring_write(cp, R300_PIPE_AUTO_CONFIG);
74 radeon_ring_write(rdev, PACKET0(GB_SELECT, 0)); 75 radeon_ring_write(cp, PACKET0(GB_SELECT, 0));
75 radeon_ring_write(rdev, 0); 76 radeon_ring_write(cp, 0);
76 radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0)); 77 radeon_ring_write(cp, PACKET0(GB_ENABLE, 0));
77 radeon_ring_write(rdev, 0); 78 radeon_ring_write(cp, 0);
78 radeon_ring_write(rdev, PACKET0(R500_SU_REG_DEST, 0)); 79 radeon_ring_write(cp, PACKET0(R500_SU_REG_DEST, 0));
79 radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1); 80 radeon_ring_write(cp, (1 << rdev->num_gb_pipes) - 1);
80 radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0)); 81 radeon_ring_write(cp, PACKET0(VAP_INDEX_OFFSET, 0));
81 radeon_ring_write(rdev, 0); 82 radeon_ring_write(cp, 0);
82 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 83 radeon_ring_write(cp, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
83 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); 84 radeon_ring_write(cp, RB3D_DC_FLUSH | RB3D_DC_FREE);
84 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 85 radeon_ring_write(cp, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
85 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); 86 radeon_ring_write(cp, ZC_FLUSH | ZC_FREE);
86 radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0)); 87 radeon_ring_write(cp, PACKET0(WAIT_UNTIL, 0));
87 radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN); 88 radeon_ring_write(cp, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
88 radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0)); 89 radeon_ring_write(cp, PACKET0(GB_AA_CONFIG, 0));
89 radeon_ring_write(rdev, 0); 90 radeon_ring_write(cp, 0);
90 radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0)); 91 radeon_ring_write(cp, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
91 radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE); 92 radeon_ring_write(cp, RB3D_DC_FLUSH | RB3D_DC_FREE);
92 radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0)); 93 radeon_ring_write(cp, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
93 radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE); 94 radeon_ring_write(cp, ZC_FLUSH | ZC_FREE);
94 radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0)); 95 radeon_ring_write(cp, PACKET0(GB_MSPOS0, 0));
95 radeon_ring_write(rdev, 96 radeon_ring_write(cp,
96 ((6 << MS_X0_SHIFT) | 97 ((6 << MS_X0_SHIFT) |
97 (6 << MS_Y0_SHIFT) | 98 (6 << MS_Y0_SHIFT) |
98 (6 << MS_X1_SHIFT) | 99 (6 << MS_X1_SHIFT) |
@@ -101,8 +102,8 @@ void rv515_ring_start(struct radeon_device *rdev)
101 (6 << MS_Y2_SHIFT) | 102 (6 << MS_Y2_SHIFT) |
102 (6 << MSBD0_Y_SHIFT) | 103 (6 << MSBD0_Y_SHIFT) |
103 (6 << MSBD0_X_SHIFT))); 104 (6 << MSBD0_X_SHIFT)));
104 radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0)); 105 radeon_ring_write(cp, PACKET0(GB_MSPOS1, 0));
105 radeon_ring_write(rdev, 106 radeon_ring_write(cp,
106 ((6 << MS_X3_SHIFT) | 107 ((6 << MS_X3_SHIFT) |
107 (6 << MS_Y3_SHIFT) | 108 (6 << MS_Y3_SHIFT) |
108 (6 << MS_X4_SHIFT) | 109 (6 << MS_X4_SHIFT) |
@@ -110,15 +111,15 @@ void rv515_ring_start(struct radeon_device *rdev)
110 (6 << MS_X5_SHIFT) | 111 (6 << MS_X5_SHIFT) |
111 (6 << MS_Y5_SHIFT) | 112 (6 << MS_Y5_SHIFT) |
112 (6 << MSBD1_SHIFT))); 113 (6 << MSBD1_SHIFT)));
113 radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0)); 114 radeon_ring_write(cp, PACKET0(GA_ENHANCE, 0));
114 radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL); 115 radeon_ring_write(cp, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
115 radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0)); 116 radeon_ring_write(cp, PACKET0(GA_POLY_MODE, 0));
116 radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE); 117 radeon_ring_write(cp, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
117 radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0)); 118 radeon_ring_write(cp, PACKET0(GA_ROUND_MODE, 0));
118 radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST); 119 radeon_ring_write(cp, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
119 radeon_ring_write(rdev, PACKET0(0x20C8, 0)); 120 radeon_ring_write(cp, PACKET0(0x20C8, 0));
120 radeon_ring_write(rdev, 0); 121 radeon_ring_write(cp, 0);
121 radeon_ring_unlock_commit(rdev); 122 radeon_ring_unlock_commit(rdev, cp);
122} 123}
123 124
124int rv515_mc_wait_for_idle(struct radeon_device *rdev) 125int rv515_mc_wait_for_idle(struct radeon_device *rdev)
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index be02bee41213..0d0d811fc80b 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -357,7 +357,7 @@ static int rv770_cp_load_microcode(struct radeon_device *rdev)
357void r700_cp_fini(struct radeon_device *rdev) 357void r700_cp_fini(struct radeon_device *rdev)
358{ 358{
359 r700_cp_stop(rdev); 359 r700_cp_stop(rdev);
360 radeon_ring_fini(rdev); 360 radeon_ring_fini(rdev, &rdev->cp);
361} 361}
362 362
363/* 363/*
@@ -1043,6 +1043,7 @@ int rv770_mc_init(struct radeon_device *rdev)
1043 1043
1044static int rv770_startup(struct radeon_device *rdev) 1044static int rv770_startup(struct radeon_device *rdev)
1045{ 1045{
1046 struct radeon_cp *cp = &rdev->cp;
1046 int r; 1047 int r;
1047 1048
1048 /* enable pcie gen2 link */ 1049 /* enable pcie gen2 link */
@@ -1091,7 +1092,7 @@ static int rv770_startup(struct radeon_device *rdev)
1091 } 1092 }
1092 r600_irq_set(rdev); 1093 r600_irq_set(rdev);
1093 1094
1094 r = radeon_ring_init(rdev, rdev->cp.ring_size); 1095 r = radeon_ring_init(rdev, cp, cp->ring_size);
1095 if (r) 1096 if (r)
1096 return r; 1097 return r;
1097 r = rv770_cp_load_microcode(rdev); 1098 r = rv770_cp_load_microcode(rdev);
@@ -1121,7 +1122,7 @@ int rv770_resume(struct radeon_device *rdev)
1121 return r; 1122 return r;
1122 } 1123 }
1123 1124
1124 r = r600_ib_test(rdev); 1125 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
1125 if (r) { 1126 if (r) {
1126 DRM_ERROR("radeon: failed testing IB (%d).\n", r); 1127 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
1127 return r; 1128 return r;
@@ -1216,7 +1217,7 @@ int rv770_init(struct radeon_device *rdev)
1216 return r; 1217 return r;
1217 1218
1218 rdev->cp.ring_obj = NULL; 1219 rdev->cp.ring_obj = NULL;
1219 r600_ring_init(rdev, 1024 * 1024); 1220 r600_ring_init(rdev, &rdev->cp, 1024 * 1024);
1220 1221
1221 rdev->ih.ring_obj = NULL; 1222 rdev->ih.ring_obj = NULL;
1222 r600_ih_ring_init(rdev, 64 * 1024); 1223 r600_ih_ring_init(rdev, 64 * 1024);
@@ -1242,7 +1243,7 @@ int rv770_init(struct radeon_device *rdev)
1242 dev_err(rdev->dev, "IB initialization failed (%d).\n", r); 1243 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1243 rdev->accel_working = false; 1244 rdev->accel_working = false;
1244 } else { 1245 } else {
1245 r = r600_ib_test(rdev); 1246 r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
1246 if (r) { 1247 if (r) {
1247 dev_err(rdev->dev, "IB test failed (%d).\n", r); 1248 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1248 rdev->accel_working = false; 1249 rdev->accel_working = false;
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-28 13:39:00 -0500