38 files changed, 1298 insertions, 506 deletions

diff --git a/arch/blackfin/Kconfig b/arch/blackfin/Kconfig
index fef96f47876c..9b765107e15c 100644
--- a/arch/blackfin/Kconfig
+++ b/arch/blackfin/Kconfig
@@ -352,6 +352,11 @@ config MEM_MT48H32M16LFCJ_75
         depends on (BFIN526_EZBRD)
         default y
 
+config MEM_MT47H64M16
+        bool
+        depends on (BFIN609_EZKIT)
+        default y
+
 source "arch/blackfin/mach-bf518/Kconfig"
 source "arch/blackfin/mach-bf527/Kconfig"
 source "arch/blackfin/mach-bf533/Kconfig"
@@ -399,8 +404,9 @@ config ROM_BASE
         hex "Kernel ROM Base"
         depends on ROMKERNEL
         default "0x20040040"
-        range 0x20000000 0x20400000 if !(BF54x || BF561)
+        range 0x20000000 0x20400000 if !(BF54x || BF561 || BF60x)
         range 0x20000000 0x30000000 if (BF54x || BF561)
+        range 0xB0000000 0xC0000000 if (BF60x)
         help
           Make sure your ROM base does not include any file-header
           information that is prepended to the kernel.
@@ -1009,6 +1015,12 @@ config HAVE_PWM
 choice
         prompt "Uncached DMA region"
         default DMA_UNCACHED_1M
+config DMA_UNCACHED_32M
+        bool "Enable 32M DMA region"
+config DMA_UNCACHED_16M
+        bool "Enable 16M DMA region"
+config DMA_UNCACHED_8M
+        bool "Enable 8M DMA region"
 config DMA_UNCACHED_4M
         bool "Enable 4M DMA region"
 config DMA_UNCACHED_2M
@@ -1038,7 +1050,7 @@ config BFIN_EXTMEM_ICACHEABLE
 config BFIN_L2_ICACHEABLE
         bool "Enable ICACHE for L2 SRAM"
         depends on BFIN_ICACHE
-        depends on BF54x || BF561
+        depends on (BF54x || BF561 || BF60x) && !SMP
         default n
 
 config BFIN_DCACHE
diff --git a/arch/blackfin/configs/BF609-EZKIT_defconfig b/arch/blackfin/configs/BF609-EZKIT_defconfig
index be9526bee4fb..f4b02350e415 100644
--- a/arch/blackfin/configs/BF609-EZKIT_defconfig
+++ b/arch/blackfin/configs/BF609-EZKIT_defconfig
@@ -90,6 +90,7 @@ CONFIG_INPUT_BFIN_ROTARY=y
 # CONFIG_SERIO is not set
 # CONFIG_LEGACY_PTYS is not set
 CONFIG_BFIN_SIMPLE_TIMER=m
+# CONFIG_BFIN_CRC is not set
 CONFIG_BFIN_LINKPORT=y
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_BFIN=y
@@ -153,3 +154,4 @@ CONFIG_CRYPTO_MD4=y
 CONFIG_CRYPTO_MD5=y
 CONFIG_CRYPTO_ARC4=y
 # CONFIG_CRYPTO_ANSI_CPRNG is not set
+CONFIG_CRYPTO_DEV_BFIN_CRC=y
diff --git a/arch/blackfin/include/asm/bfin-global.h b/arch/blackfin/include/asm/bfin-global.h
index 608be5e6d25c..dc47d79287f9 100644
--- a/arch/blackfin/include/asm/bfin-global.h
+++ b/arch/blackfin/include/asm/bfin-global.h
@@ -14,7 +14,13 @@
 #include <linux/linkage.h>
 #include <linux/types.h>
 
-#if defined(CONFIG_DMA_UNCACHED_4M)
+#if defined(CONFIG_DMA_UNCACHED_32M)
+# define DMA_UNCACHED_REGION (32 * 1024 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_16M)
+# define DMA_UNCACHED_REGION (16 * 1024 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_8M)
+# define DMA_UNCACHED_REGION (8 * 1024 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_4M)
 # define DMA_UNCACHED_REGION (4 * 1024 * 1024)
 #elif defined(CONFIG_DMA_UNCACHED_2M)
 # define DMA_UNCACHED_REGION (2 * 1024 * 1024)
diff --git a/arch/blackfin/include/asm/bfin_crc.h b/arch/blackfin/include/asm/bfin_crc.h
index 3deb4452ceed..75cef4dc85a1 100644
--- a/arch/blackfin/include/asm/bfin_crc.h
+++ b/arch/blackfin/include/asm/bfin_crc.h
@@ -79,20 +79,6 @@ struct crc_register {
         u32 revid;
 };
 
-struct bfin_crc {
-        struct miscdevice mdev;
-        struct list_head list;
-        int irq;
-        int dma_ch_src;
-        int dma_ch_dest;
-        volatile struct crc_register *regs;
-        struct crc_info *info;
-        struct mutex mutex;
-        struct completion c;
-        unsigned short opmode;
-        char name[20];
-};
-
 /* CRC_STATUS Masks */
 #define CMPERR                  0x00000002      /* Compare error */
 #define DCNTEXP                 0x00000010      /* datacnt register expired */
diff --git a/arch/blackfin/include/asm/bfin_serial.h b/arch/blackfin/include/asm/bfin_serial.h
index 8597158010b5..2d90d62edc97 100644
--- a/arch/blackfin/include/asm/bfin_serial.h
+++ b/arch/blackfin/include/asm/bfin_serial.h
@@ -282,7 +282,7 @@ struct bfin_uart_regs {
 #define UART_GET_GCTL(p)      UART_GET_CTL(p)
 #define UART_GET_LCR(p)       UART_GET_CTL(p)
 #define UART_GET_MCR(p)       UART_GET_CTL(p)
-#if ANOMALY_05001001
+#if ANOMALY_16000030
 #define UART_GET_STAT(p) \
 ({ \
         u32 __ret; \
diff --git a/arch/blackfin/include/asm/bfin_simple_timer.h b/arch/blackfin/include/asm/bfin_simple_timer.h
index aadfb1ad1fac..b2d5e733079e 100644
--- a/arch/blackfin/include/asm/bfin_simple_timer.h
+++ b/arch/blackfin/include/asm/bfin_simple_timer.h
@@ -17,5 +17,11 @@
 #define BFIN_SIMPLE_TIMER_START      _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  6)
 #define BFIN_SIMPLE_TIMER_STOP       _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  8)
 #define BFIN_SIMPLE_TIMER_READ       _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
+#define BFIN_SIMPLE_TIMER_READ_COUNTER _IO(BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 11)
+
+#define BFIN_SIMPLE_TIMER_MODE_PWM_ONESHOT              0
+#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT              1
+#define BFIN_SIMPLE_TIMER_MODE_WDTH_CAP                 2
+#define BFIN_SIMPLE_TIMER_MODE_PWMOUT_CONT_NOIRQ        3
 
 #endif
diff --git a/arch/blackfin/include/asm/bfin_twi.h b/arch/blackfin/include/asm/bfin_twi.h
index 2f3339a47626..f4a072787436 100644
--- a/arch/blackfin/include/asm/bfin_twi.h
+++ b/arch/blackfin/include/asm/bfin_twi.h
@@ -66,9 +66,9 @@ struct bfin_twi_iface {
 
 #define DEFINE_TWI_REG(reg_name, reg) \
 static inline u16 read_##reg_name(struct bfin_twi_iface *iface) \
-        { return iface->regs_base->reg; } \
+        { return bfin_read16(&iface->regs_base->reg); } \
 static inline void write_##reg_name(struct bfin_twi_iface *iface, u16 v) \
-        { iface->regs_base->reg = v; }
+        { bfin_write16(&iface->regs_base->reg, v); }
 
 DEFINE_TWI_REG(CLKDIV, clkdiv)
 DEFINE_TWI_REG(CONTROL, control)
@@ -84,7 +84,7 @@ DEFINE_TWI_REG(FIFO_CTL, fifo_ctl)
 DEFINE_TWI_REG(FIFO_STAT, fifo_stat)
 DEFINE_TWI_REG(XMT_DATA8, xmt_data8)
 DEFINE_TWI_REG(XMT_DATA16, xmt_data16)
-#if !ANOMALY_05001001
+#if !ANOMALY_16000030
 DEFINE_TWI_REG(RCV_DATA8, rcv_data8)
 DEFINE_TWI_REG(RCV_DATA16, rcv_data16)
 #else
@@ -94,7 +94,7 @@ static inline u16 read_RCV_DATA8(struct bfin_twi_iface *iface)
         unsigned long flags;
 
         flags = hard_local_irq_save();
-        ret = iface->regs_base->rcv_data8;
+        ret = bfin_read16(&iface->regs_base->rcv_data8);
         hard_local_irq_restore(flags);
 
         return ret;
@@ -106,7 +106,7 @@ static inline u16 read_RCV_DATA16(struct bfin_twi_iface *iface)
         unsigned long flags;
 
         flags = hard_local_irq_save();
-        ret = iface->regs_base->rcv_data16;
+        ret = bfin_read16(&iface->regs_base->rcv_data16);
         hard_local_irq_restore(flags);
 
         return ret;
diff --git a/arch/blackfin/include/asm/context.S b/arch/blackfin/include/asm/context.S
index 1f9060395a0a..507e7aa6a561 100644
--- a/arch/blackfin/include/asm/context.S
+++ b/arch/blackfin/include/asm/context.S
@@ -396,3 +396,12 @@
         call \func;
 #endif
 .endm
+
+#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
+# define EX_SCRATCH_REG RETN
+#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
+# define EX_SCRATCH_REG RETE
+#else
+# define EX_SCRATCH_REG CYCLES
+#endif
+
diff --git a/arch/blackfin/include/asm/dpmc.h b/arch/blackfin/include/asm/dpmc.h
index e91eae8330a6..2673b11376f4 100644
--- a/arch/blackfin/include/asm/dpmc.h
+++ b/arch/blackfin/include/asm/dpmc.h
@@ -280,7 +280,7 @@
         PM_POP_SYNC(9)
 #endif
 
-#ifdef EBIU_AMBCTL
+#ifdef EBIU_AMGCTL
         PM_SYS_POP(9, EBIU_AMBCTL1)
         PM_SYS_POP(8, EBIU_AMBCTL0)
         PM_SYS_POP16(7, EBIU_AMGCTL)
diff --git a/arch/blackfin/include/asm/gpio.h b/arch/blackfin/include/asm/gpio.h
index 3d84d96f7c2c..98d0133346b5 100644
--- a/arch/blackfin/include/asm/gpio.h
+++ b/arch/blackfin/include/asm/gpio.h
@@ -141,6 +141,8 @@ static inline void bfin_pm_standby_restore(void)
 
 void bfin_gpio_pm_hibernate_restore(void);
 void bfin_gpio_pm_hibernate_suspend(void);
+void bfin_pint_suspend(void);
+void bfin_pint_resume(void);
 
 # if !BFIN_GPIO_PINT
 int gpio_pm_wakeup_ctrl(unsigned gpio, unsigned ctrl);
diff --git a/arch/blackfin/include/asm/irq.h b/arch/blackfin/include/asm/irq.h
index 89de539ed010..4ae1144a4578 100644
--- a/arch/blackfin/include/asm/irq.h
+++ b/arch/blackfin/include/asm/irq.h
@@ -20,6 +20,16 @@
 /* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
 #include <mach/irq.h>
 
+/*
+ * pm save bfin pint registers
+ */
+struct bfin_pm_pint_save {
+        u32 mask_set;
+        u32 assign;
+        u32 edge_set;
+        u32 invert_set;
+};
+
 #if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
 # define NOP_PAD_ANOMALY_05000244 "nop; nop;"
 #else
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h
index 237579935e29..f019e9bcefe9 100644
--- a/arch/blackfin/include/asm/mem_init.h
+++ b/arch/blackfin/include/asm/mem_init.h
@@ -6,6 +6,9 @@
  * Licensed under the GPL-2 or later.
  */
 
+#ifndef __MEM_INIT_H__
+#define __MEM_INIT_H__
+
 #if defined(EBIU_SDGCTL)
 #if defined(CONFIG_MEM_MT48LC16M16A2TG_75) || \
     defined(CONFIG_MEM_MT48LC64M4A2FB_7E) || \
@@ -277,3 +280,212 @@
 #else
 #define PLL_BYPASS       0
 #endif
+
+#ifdef CONFIG_BF60x
+
+/* DMC status bits */
+#define IDLE                    0x1
+#define MEMINITDONE             0x4
+#define SRACK                   0x8
+#define PDACK                   0x10
+#define DPDACK                  0x20
+#define DLLCALDONE              0x2000
+#define PENDREF                 0xF0000
+#define PHYRDPHASE              0xF00000
+#define PHYRDPHASE_OFFSET       20
+
+/* DMC control bits */
+#define LPDDR                   0x2
+#define INIT                    0x4
+#define SRREQ                   0x8
+#define PDREQ                   0x10
+#define DPDREQ                  0x20
+#define PREC                    0x40
+#define ADDRMODE                0x100
+#define RDTOWR                  0xE00
+#define PPREF                   0x1000
+#define DLLCAL                  0x2000
+
+/* DMC DLL control bits */
+#define DLLCALRDCNT             0xFF
+#define DATACYC                 0xF00
+#define DATACYC_OFFSET          8
+
+/* CGU Divisor bits */
+#define CSEL_OFFSET             0
+#define S0SEL_OFFSET            5
+#define SYSSEL_OFFSET           8
+#define S1SEL_OFFSET            13
+#define DSEL_OFFSET             16
+#define OSEL_OFFSET             22
+#define ALGN                    0x20000000
+#define UPDT                    0x40000000
+#define LOCK                    0x80000000
+
+/* CGU Status bits */
+#define PLLEN                   0x1
+#define PLLBP                   0x2
+#define PLOCK                   0x4
+#define CLKSALGN                0x8
+
+/* CGU Control bits */
+#define MSEL_MASK               0x7F00
+#define DF_MASK                 0x1
+
+struct ddr_config {
+        u32 ddr_clk;
+        u32 dmc_ddrctl;
+        u32 dmc_ddrcfg;
+        u32 dmc_ddrtr0;
+        u32 dmc_ddrtr1;
+        u32 dmc_ddrtr2;
+        u32 dmc_ddrmr;
+        u32 dmc_ddrmr1;
+};
+
+#if defined(CONFIG_MEM_MT47H64M16)
+static struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
+        [0] = {
+                .ddr_clk    = 125,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20705212,
+                .dmc_ddrtr1 = 0x201003CF,
+                .dmc_ddrtr2 = 0x00320107,
+                .dmc_ddrmr  = 0x00000422,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [1] = {
+                .ddr_clk    = 133,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20806313,
+                .dmc_ddrtr1 = 0x2013040D,
+                .dmc_ddrtr2 = 0x00320108,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [2] = {
+                .ddr_clk    = 150,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20A07323,
+                .dmc_ddrtr1 = 0x20160492,
+                .dmc_ddrtr2 = 0x00320209,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [3] = {
+                .ddr_clk    = 166,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20A07323,
+                .dmc_ddrtr1 = 0x2016050E,
+                .dmc_ddrtr2 = 0x00320209,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [4] = {
+                .ddr_clk    = 200,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20a07323,
+                .dmc_ddrtr1 = 0x2016050f,
+                .dmc_ddrtr2 = 0x00320509,
+                .dmc_ddrmr  = 0x00000632,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [5] = {
+                .ddr_clk    = 225,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20E0A424,
+                .dmc_ddrtr1 = 0x302006DB,
+                .dmc_ddrtr2 = 0x0032020D,
+                .dmc_ddrmr  = 0x00000842,
+                .dmc_ddrmr1 = 0x4,
+        },
+        [6] = {
+                .ddr_clk    = 250,
+                .dmc_ddrctl = 0x00000904,
+                .dmc_ddrcfg = 0x00000422,
+                .dmc_ddrtr0 = 0x20E0A424,
+                .dmc_ddrtr1 = 0x3020079E,
+                .dmc_ddrtr2 = 0x0032020D,
+                .dmc_ddrmr  = 0x00000842,
+                .dmc_ddrmr1 = 0x4,
+        },
+};
+#endif
+
+static inline void dmc_enter_self_refresh(void)
+{
+        if (bfin_read_DMC0_STAT() & MEMINITDONE) {
+                bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
+                while (!(bfin_read_DMC0_STAT() & SRACK))
+                        continue;
+        }
+}
+
+static inline void dmc_exit_self_refresh(void)
+{
+        if (bfin_read_DMC0_STAT() & MEMINITDONE) {
+                bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
+                while (bfin_read_DMC0_STAT() & SRACK)
+                        continue;
+        }
+}
+
+static inline void init_cgu(u32 cgu_div, u32 cgu_ctl)
+{
+        dmc_enter_self_refresh();
+
+        /* Don't set the same value of MSEL and DF to CGU_CTL */
+        if ((bfin_read32(CGU0_CTL) & (MSEL_MASK | DF_MASK))
+                != cgu_ctl) {
+                bfin_write32(CGU0_DIV, cgu_div);
+                bfin_write32(CGU0_CTL, cgu_ctl);
+                while ((bfin_read32(CGU0_STAT) & (CLKSALGN | PLLBP)) ||
+                        !(bfin_read32(CGU0_STAT) & PLOCK))
+                        continue;
+        }
+
+        bfin_write32(CGU0_DIV, cgu_div | UPDT);
+        while (bfin_read32(CGU0_STAT) & CLKSALGN)
+                continue;
+
+        dmc_exit_self_refresh();
+}
+
+static inline void init_dmc(u32 dmc_clk)
+{
+        int i, dlldatacycle, dll_ctl;
+
+        for (i = 0; i < 7; i++) {
+                if (ddr_config_table[i].ddr_clk == dmc_clk) {
+                        bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
+                        bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
+                        bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
+                        bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
+                        bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
+                        bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
+                        bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
+                        break;
+                }
+        }
+
+        while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
+                continue;
+
+        dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >> PHYRDPHASE_OFFSET;
+        dll_ctl = bfin_read_DMC0_DLLCTL();
+        dll_ctl &= ~DATACYC;
+        bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
+
+        while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
+                continue;
+}
+#endif
+
+#endif /*__MEM_INIT_H__*/
+
diff --git a/arch/blackfin/include/asm/traps.h b/arch/blackfin/include/asm/traps.h
index 70c4e511cae6..cec771b8100c 100644
--- a/arch/blackfin/include/asm/traps.h
+++ b/arch/blackfin/include/asm/traps.h
@@ -125,5 +125,7 @@
         level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
         level "   only instructions.\n"
 
+extern void double_fault_c(struct pt_regs *fp);
+
 #endif                          /* __ASSEMBLY__ */
 #endif                          /* _BFIN_TRAPS_H */
diff --git a/arch/blackfin/kernel/bfin_dma.c b/arch/blackfin/kernel/bfin_dma.c
index c166939ffb2b..4a32f2dd5ddc 100644
--- a/arch/blackfin/kernel/bfin_dma.c
+++ b/arch/blackfin/kernel/bfin_dma.c
@@ -45,7 +45,7 @@ static int __init blackfin_dma_init(void)
                 atomic_set(&dma_ch[i].chan_status, 0);
                 dma_ch[i].regs = dma_io_base_addr[i];
         }
-#ifdef CH_MEM_STREAM3_SRC
+#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
         /* Mark MEMDMA Channel 3 as requested since we're using it internally */
         request_dma(CH_MEM_STREAM3_DEST, "Blackfin dma_memcpy");
         request_dma(CH_MEM_STREAM3_SRC, "Blackfin dma_memcpy");
@@ -361,7 +361,7 @@ void __init early_dma_memcpy_done(void)
         __builtin_bfin_ssync();
 }
 
-#ifdef CH_MEM_STREAM3_SRC
+#if defined(CH_MEM_STREAM3_SRC) && defined(CONFIG_BF60x)
 #define bfin_read_MDMA_S_CONFIG bfin_read_MDMA_S3_CONFIG
 #define bfin_write_MDMA_S_CONFIG bfin_write_MDMA_S3_CONFIG
 #define bfin_write_MDMA_S_START_ADDR bfin_write_MDMA_S3_START_ADDR
diff --git a/arch/blackfin/kernel/cplb-nompu/cplbinit.c b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
index 3e366dc2d6e1..34e96ce02aa9 100644
--- a/arch/blackfin/kernel/cplb-nompu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-nompu/cplbinit.c
@@ -58,12 +58,20 @@ void __init generate_cplb_tables_cpu(unsigned int cpu)
 
 #ifdef CONFIG_ROMKERNEL
         /* Cover kernel XIP flash area */
+#ifdef CONFIG_BF60x
+        addr = CONFIG_ROM_BASE & ~(16 * 1024 * 1024 - 1);
+        d_tbl[i_d].addr = addr;
+        d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_16MB;
+        i_tbl[i_i].addr = addr;
+        i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_16MB;
+#else
         addr = CONFIG_ROM_BASE & ~(4 * 1024 * 1024 - 1);
         d_tbl[i_d].addr = addr;
         d_tbl[i_d++].data = SDRAM_DGENERIC | PAGE_SIZE_4MB;
         i_tbl[i_i].addr = addr;
         i_tbl[i_i++].data = SDRAM_IGENERIC | PAGE_SIZE_4MB;
 #endif
+#endif
 
         /* Cover L1 memory.  One 4M area for code and data each is enough.  */
         if (cpu == 0) {
diff --git a/arch/blackfin/kernel/dma-mapping.c b/arch/blackfin/kernel/dma-mapping.c
index f0d1118f1825..e7be6532d6a0 100644
--- a/arch/blackfin/kernel/dma-mapping.c
+++ b/arch/blackfin/kernel/dma-mapping.c
@@ -122,12 +122,13 @@ void __dma_sync(dma_addr_t addr, size_t size,
 EXPORT_SYMBOL(__dma_sync);
 
 int
-dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+dma_map_sg(struct device *dev, struct scatterlist *sg_list, int nents,
            enum dma_data_direction direction)
 {
+        struct scatterlist *sg;
         int i;
 
-        for (i = 0; i < nents; i++, sg++) {
+        for_each_sg(sg_list, sg, nents, i) {
                 sg->dma_address = (dma_addr_t) sg_virt(sg);
                 __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
         }
@@ -136,12 +137,13 @@ dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
 }
 EXPORT_SYMBOL(dma_map_sg);
 
-void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
+void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg_list,
                             int nelems, enum dma_data_direction direction)
 {
+        struct scatterlist *sg;
         int i;
 
-        for (i = 0; i < nelems; i++, sg++) {
+        for_each_sg(sg_list, sg, nelems, i) {
                 sg->dma_address = (dma_addr_t) sg_virt(sg);
                 __dma_sync(sg_dma_address(sg), sg_dma_len(sg), direction);
         }
diff --git a/arch/blackfin/mach-bf527/boards/ezkit.c b/arch/blackfin/mach-bf527/boards/ezkit.c
index af732eb3a687..fc179ca07799 100644
--- a/arch/blackfin/mach-bf527/boards/ezkit.c
+++ b/arch/blackfin/mach-bf527/boards/ezkit.c
@@ -114,9 +114,9 @@ static struct musb_hdrc_config musb_config = {
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
+#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
         .mode           = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
+#elif defined(CONFIG_USB_MUSB_HDRC)
         .mode           = MUSB_HOST,
 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
         .mode           = MUSB_PERIPHERAL,
diff --git a/arch/blackfin/mach-bf548/boards/ezkit.c b/arch/blackfin/mach-bf548/boards/ezkit.c
index 3bd75bae750d..c4d07f040947 100644
--- a/arch/blackfin/mach-bf548/boards/ezkit.c
+++ b/arch/blackfin/mach-bf548/boards/ezkit.c
@@ -635,9 +635,9 @@ static struct musb_hdrc_config musb_config = {
 };
 
 static struct musb_hdrc_platform_data musb_plat = {
-#if defined(CONFIG_USB_MUSB_OTG)
+#if defined(CONFIG_USB_MUSB_HDRC) && defined(CONFIG_USB_GADGET_MUSB_HDRC)
         .mode           = MUSB_OTG,
-#elif defined(CONFIG_USB_MUSB_HDRC_HCD)
+#elif defined(CONFIG_USB_MUSB_HDRC)
         .mode           = MUSB_HOST,
 #elif defined(CONFIG_USB_GADGET_MUSB_HDRC)
         .mode           = MUSB_PERIPHERAL,
diff --git a/arch/blackfin/mach-bf548/include/mach/gpio.h b/arch/blackfin/mach-bf548/include/mach/gpio.h
index 35c8ced46158..be9edb28f96b 100644
--- a/arch/blackfin/mach-bf548/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf548/include/mach/gpio.h
@@ -171,6 +171,8 @@
 #define MAX_BLACKFIN_GPIOS 160
 
 #define BFIN_GPIO_PINT 1
+#define NR_PINT_SYS_IRQS        4
+#define NR_PINTS                160
 
 #ifndef __ASSEMBLY__
 
diff --git a/arch/blackfin/mach-bf561/boards/ezkit.c b/arch/blackfin/mach-bf561/boards/ezkit.c
index 838978808a15..7c36777c6455 100644
--- a/arch/blackfin/mach-bf561/boards/ezkit.c
+++ b/arch/blackfin/mach-bf561/boards/ezkit.c
@@ -452,18 +452,21 @@ static struct v4l2_input adv7183_inputs[] = {
                 .name = "Composite",
                 .type = V4L2_INPUT_TYPE_CAMERA,
                 .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
         },
         {
                 .index = 1,
                 .name = "S-Video",
                 .type = V4L2_INPUT_TYPE_CAMERA,
                 .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
         },
         {
                 .index = 2,
                 .name = "Component",
                 .type = V4L2_INPUT_TYPE_CAMERA,
                 .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
         },
 };
 
diff --git a/arch/blackfin/mach-bf609/Kconfig b/arch/blackfin/mach-bf609/Kconfig
index 2cb727243778..101b33ee9bba 100644
--- a/arch/blackfin/mach-bf609/Kconfig
+++ b/arch/blackfin/mach-bf609/Kconfig
@@ -51,6 +51,14 @@ config PINT5_ASSIGN
 
 endmenu
 
+config SEC_IRQ_PRIORITY_LEVELS
+        int "SEC interrupt priority levels"
+        default 7
+        range 0 7
+        help
+          Devide the total number of interrupt priority levels into sub-levels.
+          There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
+
 endmenu
 
 endif
diff --git a/arch/blackfin/mach-bf609/Makefile b/arch/blackfin/mach-bf609/Makefile
index 2a27f8174543..234fe1b4bb0e 100644
--- a/arch/blackfin/mach-bf609/Makefile
+++ b/arch/blackfin/mach-bf609/Makefile
@@ -2,5 +2,5 @@
 # arch/blackfin/mach-bf609/Makefile
 #
 
-obj-y := dma.o clock.o
-obj-$(CONFIG_PM) += pm.o hibernate.o
+obj-y := dma.o clock.o ints-priority.o
+obj-$(CONFIG_PM) += pm.o dpm.o
diff --git a/arch/blackfin/mach-bf609/boards/ezkit.c b/arch/blackfin/mach-bf609/boards/ezkit.c
index ac64f47217c1..c2cf1ae31189 100644
--- a/arch/blackfin/mach-bf609/boards/ezkit.c
+++ b/arch/blackfin/mach-bf609/boards/ezkit.c
@@ -677,11 +677,28 @@ int bf609_nor_flash_init(struct platform_device *dev)
         return 0;
 }
 
+void bf609_nor_flash_exit(struct platform_device *dev)
+{
+        const unsigned short pins[] = {
+                P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
+                P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
+                P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
+        };
+
+        peripheral_free_list(pins);
+
+        bfin_write32(SMC_GCTL, 0);
+}
+
 static struct physmap_flash_data ezkit_flash_data = {
         .width      = 2,
         .parts      = ezkit_partitions,
-        .init       = bf609_nor_flash_init,
+        .init       = bf609_nor_flash_init,
+        .exit       = bf609_nor_flash_exit,
         .nr_parts   = ARRAY_SIZE(ezkit_partitions),
+#ifdef CONFIG_ROMKERNEL
+        .probe_type = "map_rom",
+#endif
 };
 
 static struct resource ezkit_flash_resource = {
@@ -739,7 +756,7 @@ static struct bfin6xx_spi_chip spidev_chip_info = {
 };
 #endif
 
-#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
 static struct platform_device bfin_i2s_pcm = {
         .name = "bfin-i2s-pcm-audio",
         .id = -1,
@@ -825,6 +842,12 @@ static struct adau1761_platform_data adau1761_info = {
 static const unsigned short ppi_req[] = {
         P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
         P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+        P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+        P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+#if !defined(CONFIG_VIDEO_VS6624) && !defined(CONFIG_VIDEO_VS6624_MODULE)
+        P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
+        P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
+#endif
         P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
         0,
 };
@@ -855,7 +878,7 @@ static struct bcap_route vs6624_routes[] = {
         },
 };
 
-static const unsigned vs6624_ce_pin = GPIO_PD1;
+static const unsigned vs6624_ce_pin = GPIO_PE4;
 
 static struct bfin_capture_config bfin_capture_data = {
         .card_name = "BF609",
@@ -871,7 +894,128 @@ static struct bfin_capture_config bfin_capture_data = {
         .ppi_info = &ppi_info,
         .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FS1HI_FS2HI
                         | EPPI_CTL_POLC3 | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
-        .blank_clocks = 8,
+        .blank_pixels = 4,
+};
+#endif
+
+#if defined(CONFIG_VIDEO_ADV7842) \
+        || defined(CONFIG_VIDEO_ADV7842_MODULE)
+#include <media/adv7842.h>
+
+static struct v4l2_input adv7842_inputs[] = {
+        {
+                .index = 0,
+                .name = "Composite",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
+        },
+        {
+                .index = 1,
+                .name = "S-Video",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .std = V4L2_STD_ALL,
+                .capabilities = V4L2_IN_CAP_STD,
+        },
+        {
+                .index = 2,
+                .name = "Component",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+        },
+        {
+                .index = 3,
+                .name = "VGA",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+        },
+        {
+                .index = 4,
+                .name = "HDMI",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .capabilities = V4L2_IN_CAP_CUSTOM_TIMINGS,
+        },
+};
+
+static struct bcap_route adv7842_routes[] = {
+        {
+                .input = 3,
+                .output = 0,
+                .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
+                                | EPPI_CTL_ACTIVE656),
+        },
+        {
+                .input = 4,
+                .output = 0,
+        },
+        {
+                .input = 2,
+                .output = 0,
+        },
+        {
+                .input = 1,
+                .output = 0,
+        },
+        {
+                .input = 0,
+                .output = 1,
+                .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
+                                | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC2
+                                | EPPI_CTL_SYNC2 | EPPI_CTL_NON656),
+        },
+};
+
+static struct adv7842_output_format adv7842_opf[] = {
+        {
+                .op_ch_sel = ADV7842_OP_CH_SEL_BRG,
+                .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_8,
+                .op_656_range = 1,
+                .blank_data = 1,
+                .insert_av_codes = 1,
+        },
+        {
+                .op_ch_sel = ADV7842_OP_CH_SEL_RGB,
+                .op_format_sel = ADV7842_OP_FORMAT_SEL_SDR_ITU656_16,
+                .op_656_range = 1,
+                .blank_data = 1,
+        },
+};
+
+static struct adv7842_platform_data adv7842_data = {
+        .opf = adv7842_opf,
+        .num_opf = ARRAY_SIZE(adv7842_opf),
+        .ain_sel = ADV7842_AIN10_11_12_NC_SYNC_4_1,
+        .prim_mode = ADV7842_PRIM_MODE_SDP,
+        .vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1,
+        .inp_color_space = ADV7842_INP_COLOR_SPACE_AUTO,
+        .i2c_sdp_io = 0x40,
+        .i2c_sdp = 0x41,
+        .i2c_cp = 0x42,
+        .i2c_vdp = 0x43,
+        .i2c_afe = 0x44,
+        .i2c_hdmi = 0x45,
+        .i2c_repeater = 0x46,
+        .i2c_edid = 0x47,
+        .i2c_infoframe = 0x48,
+        .i2c_cec = 0x49,
+        .i2c_avlink = 0x4a,
+        .i2c_ex = 0x26,
+};
+
+static struct bfin_capture_config bfin_capture_data = {
+        .card_name = "BF609",
+        .inputs = adv7842_inputs,
+        .num_inputs = ARRAY_SIZE(adv7842_inputs),
+        .routes = adv7842_routes,
+        .i2c_adapter_id = 0,
+        .board_info = {
+                .type = "adv7842",
+                .addr = 0x20,
+                .platform_data = (void *)&adv7842_data,
+        },
+        .ppi_info = &ppi_info,
+        .ppi_control = (PACK_EN | DLEN_8 | EPPI_CTL_FLDSEL
+                        | EPPI_CTL_ACTIVE656),
 };
 #endif
 
@@ -883,6 +1027,80 @@ static struct platform_device bfin_capture_device = {
 };
 #endif
 
+#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
+        || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
+#include <linux/videodev2.h>
+#include <media/blackfin/bfin_display.h>
+#include <media/blackfin/ppi.h>
+
+static const unsigned short ppi_req_disp[] = {
+        P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
+        P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
+        P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
+        P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
+        P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
+        0,
+};
+
+static const struct ppi_info ppi_info = {
+        .type = PPI_TYPE_EPPI3,
+        .dma_ch = CH_EPPI0_CH0,
+        .irq_err = IRQ_EPPI0_STAT,
+        .base = (void __iomem *)EPPI0_STAT,
+        .pin_req = ppi_req_disp,
+};
+
+#if defined(CONFIG_VIDEO_ADV7511) \
+        || defined(CONFIG_VIDEO_ADV7511_MODULE)
+#include <media/adv7511.h>
+
+static struct v4l2_output adv7511_outputs[] = {
+        {
+                .index = 0,
+                .name = "HDMI",
+                .type = V4L2_INPUT_TYPE_CAMERA,
+                .capabilities = V4L2_OUT_CAP_CUSTOM_TIMINGS,
+        },
+};
+
+static struct disp_route adv7511_routes[] = {
+        {
+                .output = 0,
+        },
+};
+
+static struct adv7511_platform_data adv7511_data = {
+        .edid_addr = 0x7e,
+        .i2c_ex = 0x25,
+};
+
+static struct bfin_display_config bfin_display_data = {
+        .card_name = "BF609",
+        .outputs = adv7511_outputs,
+        .num_outputs = ARRAY_SIZE(adv7511_outputs),
+        .routes = adv7511_routes,
+        .i2c_adapter_id = 0,
+        .board_info = {
+                .type = "adv7511",
+                .addr = 0x39,
+                .platform_data = (void *)&adv7511_data,
+        },
+        .ppi_info = &ppi_info,
+        .ppi_control = (EPPI_CTL_SPLTWRD | PACK_EN | DLEN_16
+                        | EPPI_CTL_FS1LO_FS2LO | EPPI_CTL_POLC3
+                        | EPPI_CTL_IFSGEN | EPPI_CTL_SYNC2
+                        | EPPI_CTL_NON656 | EPPI_CTL_DIR),
+};
+#endif
+
+static struct platform_device bfin_display_device = {
+        .name = "bfin_display",
+        .dev = {
+                .platform_data = &bfin_display_data,
+        },
+};
+#endif
+
 #if defined(CONFIG_BFIN_CRC)
 #define BFIN_CRC_NAME "bfin-crc"
 
@@ -947,6 +1165,39 @@ static struct platform_device bfin_crc1_device = {
 };
 #endif
 
+#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
+#define BFIN_CRYPTO_CRC_NAME            "bfin-hmac-crc"
+#define BFIN_CRYPTO_CRC_POLY_DATA       0x5c5c5c5c
+
+static struct resource bfin_crypto_crc_resources[] = {
+        {
+                .start = REG_CRC0_CTL,
+                .end = REG_CRC0_REVID+4,
+                .flags = IORESOURCE_MEM,
+        },
+        {
+                .start = IRQ_CRC0_DCNTEXP,
+                .end = IRQ_CRC0_DCNTEXP,
+                .flags = IORESOURCE_IRQ,
+        },
+        {
+                .start = CH_MEM_STREAM0_SRC_CRC0,
+                .end = CH_MEM_STREAM0_SRC_CRC0,
+                .flags = IORESOURCE_DMA,
+        },
+};
+
+static struct platform_device bfin_crypto_crc_device = {
+        .name = BFIN_CRYPTO_CRC_NAME,
+        .id = 0,
+        .num_resources = ARRAY_SIZE(bfin_crypto_crc_resources),
+        .resource = bfin_crypto_crc_resources,
+        .dev = {
+                .platform_data = (void *)BFIN_CRYPTO_CRC_POLY_DATA,
+        },
+};
+#endif
+
 #if defined(CONFIG_TOUCHSCREEN_AD7877) || defined(CONFIG_TOUCHSCREEN_AD7877_MODULE)
 static const struct ad7877_platform_data bfin_ad7877_ts_info = {
         .model                  = 7877,
@@ -963,6 +1214,28 @@ static const struct ad7877_platform_data bfin_ad7877_ts_info = {
 };
 #endif
 
+#if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
+#include <linux/input.h>
+#include <linux/gpio_keys.h>
+
+static struct gpio_keys_button bfin_gpio_keys_table[] = {
+        {BTN_0, GPIO_PB10, 1, "gpio-keys: BTN0"},
+        {BTN_1, GPIO_PE1, 1, "gpio-keys: BTN1"},
+};
+
+static struct gpio_keys_platform_data bfin_gpio_keys_data = {
+        .buttons        = bfin_gpio_keys_table,
+        .nbuttons       = ARRAY_SIZE(bfin_gpio_keys_table),
+};
+
+static struct platform_device bfin_device_gpiokeys = {
+        .name      = "gpio-keys",
+        .dev = {
+                .platform_data = &bfin_gpio_keys_data,
+        },
+};
+#endif
+
 static struct spi_board_info bfin_spi_board_info[] __initdata = {
 #if defined(CONFIG_MTD_M25P80) \
         || defined(CONFIG_MTD_M25P80_MODULE)
@@ -981,10 +1254,10 @@ static struct spi_board_info bfin_spi_board_info[] __initdata = {
         {
                 .modalias               = "ad7877",
                 .platform_data          = &bfin_ad7877_ts_info,
-                .irq                    = IRQ_PB4,      /* old boards (<=Rev 1.3) use IRQ_PJ11 */
+                .irq                    = IRQ_PD9,
                 .max_speed_hz           = 12500000,     /* max spi clock (SCK) speed in HZ */
                 .bus_num                = 0,
-                .chip_select            = 2,
+                .chip_select            = 4,
         },
 #endif
 #if defined(CONFIG_SPI_SPIDEV) || defined(CONFIG_SPI_SPIDEV_MODULE)
@@ -1050,7 +1323,7 @@ static struct resource bfin_spi1_resource[] = {
 
 /* SPI controller data */
 static struct bfin6xx_spi_master bf60x_spi_master_info0 = {
-        .num_chipselect = 4,
+        .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
         .pin_req = {P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0},
 };
 
@@ -1065,7 +1338,7 @@ static struct platform_device bf60x_spi_master0 = {
 };
 
 static struct bfin6xx_spi_master bf60x_spi_master_info1 = {
-        .num_chipselect = 4,
+        .num_chipselect = MAX_CTRL_CS + MAX_BLACKFIN_GPIOS,
         .pin_req = {P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0},
 };
 
@@ -1146,6 +1419,11 @@ static struct i2c_board_info __initdata bfin_i2c_board_info0[] = {
                 .platform_data = (void *)&adau1761_info
         },
 #endif
+#if defined(CONFIG_SND_SOC_SSM2602) || defined(CONFIG_SND_SOC_SSM2602_MODULE)
+        {
+                I2C_BOARD_INFO("ssm2602", 0x1b),
+        },
+#endif
 };
 
 static struct i2c_board_info __initdata bfin_i2c_board_info1[] = {
@@ -1261,6 +1539,9 @@ static struct platform_device *ezkit_devices[] __initdata = {
         &bfin_crc0_device,
         &bfin_crc1_device,
 #endif
+#if defined(CONFIG_CRYPTO_DEV_BFIN_CRC)
+        &bfin_crypto_crc_device,
+#endif
 
 #if defined(CONFIG_KEYBOARD_GPIO) || defined(CONFIG_KEYBOARD_GPIO_MODULE)
         &bfin_device_gpiokeys,
@@ -1269,7 +1550,7 @@ static struct platform_device *ezkit_devices[] __initdata = {
 #if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
         &ezkit_flash_device,
 #endif
-#if defined(CONFIG_SND_BF6XX_I2S) || defined(CONFIG_SND_BF6XX_I2S_MODULE)
+#if defined(CONFIG_SND_BF5XX_I2S) || defined(CONFIG_SND_BF5XX_I2S_MODULE)
         &bfin_i2s_pcm,
 #endif
 #if defined(CONFIG_SND_BF6XX_SOC_I2S) || \
@@ -1284,6 +1565,11 @@ static struct platform_device *ezkit_devices[] __initdata = {
         || defined(CONFIG_VIDEO_BLACKFIN_CAPTURE_MODULE)
         &bfin_capture_device,
 #endif
+#if defined(CONFIG_VIDEO_BLACKFIN_DISPLAY) \
+        || defined(CONFIG_VIDEO_BLACKFIN_DISPLAY_MODULE)
+        &bfin_display_device,
+#endif
+
 };
 
 static int __init ezkit_init(void)
diff --git a/arch/blackfin/mach-bf609/clock.c b/arch/blackfin/mach-bf609/clock.c
index 7f8f529693ae..437d56c82281 100644
--- a/arch/blackfin/mach-bf609/clock.c
+++ b/arch/blackfin/mach-bf609/clock.c
@@ -97,9 +97,10 @@ int wait_for_pll_align(void)
         while (i-- && (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN));
 
         if (bfin_read32(CGU0_STAT) & CGU0_STAT_CLKSALGN) {
-                printk(KERN_DEBUG "fail to align clk\n");
+                printk(KERN_CRIT "fail to align clk\n");
                 return -1;
         }
+
         return 0;
 }
 
diff --git a/arch/blackfin/mach-bf609/dpm.S b/arch/blackfin/mach-bf609/dpm.S
new file mode 100644
index 000000000000..54d50c689db1
--- /dev/null
+++ b/arch/blackfin/mach-bf609/dpm.S
@@ -0,0 +1,157 @@
+#include <linux/linkage.h>
+#include <asm/blackfin.h>
+#include <asm/dpmc.h>
+
+#include <asm/context.S>
+
+#define PM_STACK   (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
+
+.section .l1.text
+ENTRY(_enter_hibernate)
+        /* switch stack to L1 scratch, prepare for ddr srfr */
+        P0.H = HI(PM_STACK);
+        P0.L = LO(PM_STACK);
+        SP = P0;
+
+        call _bf609_ddr_sr;
+        call _bfin_hibernate_syscontrol;
+
+        P0.H = HI(DPM0_RESTORE4);
+        P0.L = LO(DPM0_RESTORE4);
+        P1.H = _bf609_pm_data;
+        P1.L = _bf609_pm_data;
+        [P0] = P1;
+
+        P0.H = HI(DPM0_CTL);
+        P0.L = LO(DPM0_CTL);
+        R3.H = HI(0x00000010);
+        R3.L = LO(0x00000010);
+
+        bfin_init_pm_bench_cycles;
+
+        [P0] = R3;
+
+        SSYNC;
+ENDPROC(_enter_hibernate)
+
+/* DPM wake up interrupt won't wake up core on bf60x if its core IMASK
+ * is disabled. This behavior differ from bf5xx serial processor.
+ */
+ENTRY(_dummy_deepsleep)
+        [--sp] = SYSCFG;
+        [--sp] = (R7:0,P5:0);
+        cli r0;
+
+        /* get wake up interrupt ID */
+        P0.l = LO(SEC_SCI_BASE + SEC_CSID);
+        P0.h = HI(SEC_SCI_BASE + SEC_CSID);
+        R0 = [P0];
+
+        /* ACK wake up interrupt in SEC */
+        P1.l = LO(SEC_END);
+        P1.h = HI(SEC_END);
+
+        [P1] = R0;
+        SSYNC;
+
+        /* restore EVT 11 entry */
+        p0.h = hi(EVT11);
+        p0.l = lo(EVT11);
+        p1.h = _evt_evt11;
+        p1.l = _evt_evt11;
+
+        [p0] = p1;
+        SSYNC;
+
+        (R7:0,P5:0) = [sp++];
+        SYSCFG = [sp++];
+        RTI;
+ENDPROC(_dummy_deepsleep)
+
+ENTRY(_enter_deepsleep)
+        LINK 0xC;
+        [--sp] = (R7:0,P5:0);
+
+        /* Change EVT 11 entry to dummy handler for wake up event */
+        p0.h = hi(EVT11);
+        p0.l = lo(EVT11);
+        p1.h = _dummy_deepsleep;
+        p1.l = _dummy_deepsleep;
+
+        [p0] = p1;
+
+        P0.H = HI(PM_STACK);
+        P0.L = LO(PM_STACK);
+
+        EX_SCRATCH_REG = SP;
+        SP = P0;
+
+        SSYNC;
+
+        /* should put ddr to self refresh mode before sleep */
+        call _bf609_ddr_sr;
+
+        /* Set DPM controller to deep sleep mode */
+        P0.H = HI(DPM0_CTL);
+        P0.L = LO(DPM0_CTL);
+        R3.H = HI(0x00000008);
+        R3.L = LO(0x00000008);
+        [P0] = R3;
+        CSYNC;
+
+        /* Enable evt 11 in IMASK before idle, otherwise core doesn't wake up. */
+        r0.l = 0x800;
+        r0.h = 0;
+        sti r0;
+        SSYNC;
+
+        bfin_init_pm_bench_cycles;
+
+        /* Fall into deep sleep in idle*/
+        idle;
+        SSYNC;
+
+        /* Restore PLL after wake up from deep sleep */
+        call _bf609_resume_ccbuf;
+
+        /* turn ddr out of self refresh mode */
+        call _bf609_ddr_sr_exit;
+
+        SP = EX_SCRATCH_REG;
+
+        (R7:0,P5:0) = [SP++];
+        UNLINK;
+        RTS;
+ENDPROC(_enter_deepsleep)
+
+.section .text
+ENTRY(_bf609_hibernate)
+        bfin_cpu_reg_save;
+        bfin_core_mmr_save;
+
+        P0.H = _bf609_pm_data;
+        P0.L = _bf609_pm_data;
+        R1.H = 0xDEAD;
+        R1.L = 0xBEEF;
+        R2.H = .Lpm_resume_here;
+        R2.L = .Lpm_resume_here;
+        [P0++] = R1;
+        [P0++] = R2;
+        [P0++] = SP;
+
+        P1.H = _enter_hibernate;
+        P1.L = _enter_hibernate;
+
+        call (P1);
+.Lpm_resume_here:
+
+        bfin_core_mmr_restore;
+        bfin_cpu_reg_restore;
+
+        [--sp] = RETI;  /* Clear Global Interrupt Disable */
+        SP += 4;
+
+        RTS;
+
+ENDPROC(_bf609_hibernate)
+
diff --git a/arch/blackfin/mach-bf609/hibernate.S b/arch/blackfin/mach-bf609/hibernate.S
deleted file mode 100644
index d37a532519c8..000000000000
--- a/arch/blackfin/mach-bf609/hibernate.S
+++ /dev/null
@@ -1,65 +0,0 @@
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-#include <asm/dpmc.h>
-
-#define PM_STACK   (COREA_L1_SCRATCH_START + L1_SCRATCH_LENGTH - 12)
-
-.section .l1.text
-ENTRY(_enter_hibernate)
-        /* switch stack to L1 scratch, prepare for ddr srfr */
-        P0.H = HI(PM_STACK);
-        P0.L = LO(PM_STACK);
-        SP = P0;
-
-        call _bf609_ddr_sr;
-        call _bfin_hibernate_syscontrol;
-
-        P0.H = HI(DPM0_RESTORE4);
-        P0.L = LO(DPM0_RESTORE4);
-        P1.H = _bf609_pm_data;
-        P1.L = _bf609_pm_data;
-        [P0] = P1;
-
-        P0.H = HI(DPM0_CTL);
-        P0.L = LO(DPM0_CTL);
-        R3.H = HI(0x00000010);
-        R3.L = LO(0x00000010);
-
-        bfin_init_pm_bench_cycles;
-
-        [P0] = R3;
-
-        SSYNC;
-ENDPROC(_enter_hibernate_mode)
-
-.section .text
-ENTRY(_bf609_hibernate)
-        bfin_cpu_reg_save;
-        bfin_core_mmr_save;
-
-        P0.H = _bf609_pm_data;
-        P0.L = _bf609_pm_data;
-        R1.H = 0xDEAD;
-        R1.L = 0xBEEF;
-        R2.H = .Lpm_resume_here;
-        R2.L = .Lpm_resume_here;
-        [P0++] = R1;
-        [P0++] = R2;
-        [P0++] = SP;
-
-        P1.H = _enter_hibernate;
-        P1.L = _enter_hibernate;
-
-        call (P1);
-.Lpm_resume_here:
-
-        bfin_core_mmr_restore;
-        bfin_cpu_reg_restore;
-
-        [--sp] = RETI;  /* Clear Global Interrupt Disable */
-        SP += 4;
-
-        RTS;
-
-ENDPROC(_bf609_hibernate)
-
diff --git a/arch/blackfin/mach-bf609/include/mach/anomaly.h b/arch/blackfin/mach-bf609/include/mach/anomaly.h
index bdd39aefb565..7a07374308ac 100644
--- a/arch/blackfin/mach-bf609/include/mach/anomaly.h
+++ b/arch/blackfin/mach-bf609/include/mach/anomaly.h
@@ -5,126 +5,99 @@
  * and can be replaced with that version at any time
  * DO NOT EDIT THIS FILE
  *
- * Copyright 2004-2011 Analog Devices Inc.
+ * Copyright 2004-2012 Analog Devices Inc.
  * Licensed under the Clear BSD license.
  */
 
 /* This file should be up to date with:
+ *  - Revision A, 15/06/2012; ADSP-BF609 Blackfin Processor Anomaly List
  */
 
 #if __SILICON_REVISION__ < 0
-# error will not work on BF506 silicon version
+# error will not work on BF609 silicon version
 #endif
 
 #ifndef _MACH_ANOMALY_H_
 #define _MACH_ANOMALY_H_
 
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
+/* TRU_STAT.ADDRERR and TRU_ERRADDR.ADDR May Not Reflect the Correct Status */
+#define ANOMALY_16000003 (1)
+/* The EPPI Data Enable (DEN) Signal is Not Functional */
+#define ANOMALY_16000004 (1)
+/* Using L1 Instruction Cache with Parity Enabled is Unreliable */
+#define ANOMALY_16000005 (1)
+/* SEQSTAT.SYSNMI Clears Upon Entering the NMI ISR */
+#define ANOMALY_16000006 (1)
+/* DDR2 Memory Reads May Fail Intermittently */
+#define ANOMALY_16000007 (1)
+/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
+#define ANOMALY_16000008 (1)
+/* TestSET Instruction Cannot Be Interrupted */
+#define ANOMALY_16000009 (1)
 /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
+#define ANOMALY_16000010 (1)
 /* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* IFLUSH sucks at life */
-#define ANOMALY_05000491 (1)
-/* Tempopary anomaly ID for data loss in MMR read operation if interrupted */
-#define ANOMALY_05001001 (__SILICON_REVISION__ < 1)
+#define ANOMALY_16000011 (1)
+/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
+#define ANOMALY_16000012 (1)
+/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
+#define ANOMALY_16000013 (1)
+/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
+#define ANOMALY_16000014 (1)
+/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
+#define ANOMALY_16000015 (1)
+/* Speculative Fetches Can Cause Undesired External FIFO Operations */
+#define ANOMALY_16000017 (1)
+/* RSI Boot Cleanup Routine Does Not Clear Registers */
+#define ANOMALY_16000018 (1)
+/* SPI Master Boot Device Auto-detection Frequency is Set Incorrectly */
+#define ANOMALY_16000019 (1)
+/* rom_SysControl() Fails to Set DDR0_CTL.INIT for Wakeup From Hibernate */
+#define ANOMALY_16000020 (1)
+/* rom_SysControl() Fails to Save and Restore DDR0_PHYCTL3 for Hibernate/Wakeup Sequence */
+#define ANOMALY_16000021 (1)
+/* Boot Code Fails to Enable Parity Fault Detection */
+#define ANOMALY_16000022 (1)
+/* USB DMA interrupt status do not show the DMA channel interrupt in the DMA ISR */
+#define ANOMALY_16000027 (1)
+/* Interrupted Core Reads of MMRs May Cause Data Loss */
+#define ANOMALY_16000030 (1)
 
 /* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
 #define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
 #define ANOMALY_05000189 (0)
 #define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
 #define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
 #define ANOMALY_05000230 (0)
 #define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
 #define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
 #define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
 #define ANOMALY_05000273 (0)
 #define ANOMALY_05000274 (0)
 #define ANOMALY_05000278 (0)
 #define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
 #define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
 #define ANOMALY_05000311 (0)
 #define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
 #define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
 #define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
 #define ANOMALY_05000380 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000440 (0)
 #define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
 #define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
+#define ANOMALY_05000456 (0)
 #define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
+#define ANOMALY_05000481 (1)
+
+/* Reuse BF5xx anomalies IDs for the same anomaly in BF60x */
+#define ANOMALY_05000491 ANOMALY_16000008
+#define ANOMALY_05000477 ANOMALY_16000009
+#define ANOMALY_05000443 ANOMALY_16000010
+#define ANOMALY_05000461 ANOMALY_16000011
+#define ANOMALY_05000426 ANOMALY_16000012
+#define ANOMALY_05000310 ANOMALY_16000013
+#define ANOMALY_05000245 ANOMALY_16000014
+#define ANOMALY_05000074 ANOMALY_16000015
+#define ANOMALY_05000416 ANOMALY_16000017
+
 
 #endif
diff --git a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
index 6aac38544cc9..f1a6afae1a71 100644
--- a/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
+++ b/arch/blackfin/mach-bf609/include/mach/defBF60x_base.h
@@ -2665,7 +2665,6 @@
 #define DEVSZ_1G                0x400         /* DMC External Bank Size = 1Gbit */
 #define DEVSZ_2G                0x500         /* DMC External Bank Size = 2Gbit */
 
-
 /* =========================
         L2CTL Registers
    ========================= */
diff --git a/arch/blackfin/mach-bf609/include/mach/gpio.h b/arch/blackfin/mach-bf609/include/mach/gpio.h
index 127586b1e04a..c32c8cc8db2e 100644
--- a/arch/blackfin/mach-bf609/include/mach/gpio.h
+++ b/arch/blackfin/mach-bf609/include/mach/gpio.h
@@ -123,6 +123,8 @@
 
 
 #define BFIN_GPIO_PINT 1
+#define NR_PINT_SYS_IRQS        6
+#define NR_PINTS                112
 
 
 #ifndef __ASSEMBLY__
diff --git a/arch/blackfin/mach-bf609/include/mach/irq.h b/arch/blackfin/mach-bf609/include/mach/irq.h
index 0004552433b2..23e74cdeeee8 100644
--- a/arch/blackfin/mach-bf609/include/mach/irq.h
+++ b/arch/blackfin/mach-bf609/include/mach/irq.h
@@ -293,9 +293,13 @@
 
 #define NR_MACH_IRQS            (IRQ_PG15 + 1)
 
+#define SEC_SCTL_PRIO_OFFSET    8
+
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
 
+extern u8 sec_int_priority[];
+
 /*
  * bfin pint registers layout
  */
diff --git a/arch/blackfin/mach-bf609/include/mach/pm.h b/arch/blackfin/mach-bf609/include/mach/pm.h
index 036d9bdc889e..3ca0fb965636 100644
--- a/arch/blackfin/mach-bf609/include/mach/pm.h
+++ b/arch/blackfin/mach-bf609/include/mach/pm.h
@@ -11,11 +11,14 @@
 
 #include <linux/suspend.h>
 
-int bfin609_pm_enter(suspend_state_t state);
-int bf609_pm_prepare(void);
-void bf609_pm_finish(void);
+extern int bfin609_pm_enter(suspend_state_t state);
+extern int bf609_pm_prepare(void);
+extern void bf609_pm_finish(void);
 
 void bf609_hibernate(void);
 void bfin_sec_raise_irq(unsigned int sid);
 void coreb_enable(void);
+
+int bf609_nor_flash_init(void);
+void bf609_nor_flash_exit(void);
 #endif
diff --git a/arch/blackfin/mach-bf609/ints-priority.c b/arch/blackfin/mach-bf609/ints-priority.c
new file mode 100644
index 000000000000..f68abb9aa79e
--- /dev/null
+++ b/arch/blackfin/mach-bf609/ints-priority.c
@@ -0,0 +1,156 @@
+/*
+ * Copyright 2007-2008 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ *
+ * Set up the interrupt priorities
+ */
+
+#include <linux/module.h>
+#include <linux/irq.h>
+#include <asm/blackfin.h>
+
+u8 sec_int_priority[] = {
+        255,    /* IRQ_SEC_ERR */
+        255,    /* IRQ_CGU_EVT */
+        254,    /* IRQ_WATCH0 */
+        254,    /* IRQ_WATCH1 */
+        253,    /* IRQ_L2CTL0_ECC_ERR */
+        253,    /* IRQ_L2CTL0_ECC_WARN */
+        253,    /* IRQ_C0_DBL_FAULT */
+        253,    /* IRQ_C1_DBL_FAULT */
+        252,    /* IRQ_C0_HW_ERR */
+        252,    /* IRQ_C1_HW_ERR */
+        255,    /* IRQ_C0_NMI_L1_PARITY_ERR */
+        255,    /* IRQ_C1_NMI_L1_PARITY_ERR */
+
+        50,     /* IRQ_TIMER0 */
+        50,     /* IRQ_TIMER1 */
+        50,     /* IRQ_TIMER2 */
+        50,     /* IRQ_TIMER3 */
+        50,     /* IRQ_TIMER4 */
+        50,     /* IRQ_TIMER5 */
+        50,     /* IRQ_TIMER6 */
+        50,     /* IRQ_TIMER7 */
+        50,     /* IRQ_TIMER_STAT */
+        0,      /* IRQ_PINT0 */
+        0,      /* IRQ_PINT1 */
+        0,      /* IRQ_PINT2 */
+        0,      /* IRQ_PINT3 */
+        0,      /* IRQ_PINT4 */
+        0,      /* IRQ_PINT5 */
+        0,      /* IRQ_CNT */
+        50,     /* RQ_PWM0_TRIP */
+        50,     /* IRQ_PWM0_SYNC */
+        50,     /* IRQ_PWM1_TRIP */
+        50,     /* IRQ_PWM1_SYNC */
+        0,      /* IRQ_TWI0 */
+        0,      /* IRQ_TWI1 */
+        10,     /* IRQ_SOFT0 */
+        10,     /* IRQ_SOFT1 */
+        10,     /* IRQ_SOFT2 */
+        10,     /* IRQ_SOFT3 */
+        0,      /* IRQ_ACM_EVT_MISS */
+        0,      /* IRQ_ACM_EVT_COMPLETE */
+        0,      /* IRQ_CAN0_RX */
+        0,      /* IRQ_CAN0_TX */
+        0,      /* IRQ_CAN0_STAT */
+        100,    /* IRQ_SPORT0_TX */
+        100,    /* IRQ_SPORT0_TX_STAT */
+        100,    /* IRQ_SPORT0_RX */
+        100,    /* IRQ_SPORT0_RX_STAT */
+        100,    /* IRQ_SPORT1_TX */
+        100,    /* IRQ_SPORT1_TX_STAT */
+        100,    /* IRQ_SPORT1_RX */
+        100,    /* IRQ_SPORT1_RX_STAT */
+        100,    /* IRQ_SPORT2_TX */
+        100,    /* IRQ_SPORT2_TX_STAT */
+        100,    /* IRQ_SPORT2_RX */
+        100,    /* IRQ_SPORT2_RX_STAT */
+        0,      /* IRQ_SPI0_TX */
+        0,      /* IRQ_SPI0_RX */
+        0,      /* IRQ_SPI0_STAT */
+        0,      /* IRQ_SPI1_TX */
+        0,      /* IRQ_SPI1_RX */
+        0,      /* IRQ_SPI1_STAT */
+        0,      /* IRQ_RSI */
+        0,      /* IRQ_RSI_INT0 */
+        0,      /* IRQ_RSI_INT1 */
+        0,      /* DMA11 Data (SDU) */
+        0,      /* DMA12 Data (Reserved) */
+        0,      /* Reserved */
+        0,      /* Reserved */
+        30,     /* IRQ_EMAC0_STAT */
+        0,      /* EMAC0 Power (Reserved) */
+        30,     /* IRQ_EMAC1_STAT */
+        0,      /* EMAC1 Power (Reserved) */
+        0,      /* IRQ_LP0 */
+        0,      /* IRQ_LP0_STAT */
+        0,      /* IRQ_LP1 */
+        0,      /* IRQ_LP1_STAT */
+        0,      /* IRQ_LP2 */
+        0,      /* IRQ_LP2_STAT */
+        0,      /* IRQ_LP3 */
+        0,      /* IRQ_LP3_STAT */
+        0,      /* IRQ_UART0_TX */
+        0,      /* IRQ_UART0_RX */
+        0,      /* IRQ_UART0_STAT */
+        0,      /* IRQ_UART1_TX */
+        0,      /* IRQ_UART1_RX */
+        0,      /* IRQ_UART1_STAT */
+        0,      /* IRQ_MDMA0_SRC_CRC0 */
+        0,      /* IRQ_MDMA0_DEST_CRC0 */
+        0,      /* IRQ_CRC0_DCNTEXP */
+        0,      /* IRQ_CRC0_ERR */
+        0,      /* IRQ_MDMA1_SRC_CRC1 */
+        0,      /* IRQ_MDMA1_DEST_CRC1 */
+        0,      /* IRQ_CRC1_DCNTEXP */
+        0,      /* IRQ_CRC1_ERR */
+        0,      /* IRQ_MDMA2_SRC */
+        0,      /* IRQ_MDMA2_DEST */
+        0,      /* IRQ_MDMA3_SRC */
+        0,      /* IRQ_MDMA3_DEST */
+        120,    /* IRQ_EPPI0_CH0 */
+        120,    /* IRQ_EPPI0_CH1 */
+        120,    /* IRQ_EPPI0_STAT */
+        120,    /* IRQ_EPPI2_CH0 */
+        120,    /* IRQ_EPPI2_CH1 */
+        120,    /* IRQ_EPPI2_STAT */
+        120,    /* IRQ_EPPI1_CH0 */
+        120,    /* IRQ_EPPI1_CH1 */
+        120,    /* IRQ_EPPI1_STAT */
+        120,    /* IRQ_PIXC_CH0 */
+        120,    /* IRQ_PIXC_CH1 */
+        120,    /* IRQ_PIXC_CH2 */
+        120,    /* IRQ_PIXC_STAT */
+        120,    /* IRQ_PVP_CPDOB */
+        120,    /* IRQ_PVP_CPDOC */
+        120,    /* IRQ_PVP_CPSTAT */
+        120,    /* IRQ_PVP_CPCI */
+        120,    /* IRQ_PVP_STAT0 */
+        120,    /* IRQ_PVP_MPDO */
+        120,    /* IRQ_PVP_MPDI */
+        120,    /* IRQ_PVP_MPSTAT */
+        120,    /* IRQ_PVP_MPCI */
+        120,    /* IRQ_PVP_CPDOA */
+        120,    /* IRQ_PVP_STAT1 */
+        0,      /* IRQ_USB_STAT */
+        0,      /* IRQ_USB_DMA */
+        0,      /* IRQ_TRU_INT0 */
+        0,      /* IRQ_TRU_INT1 */
+        0,      /* IRQ_TRU_INT2 */
+        0,      /* IRQ_TRU_INT3 */
+        0,      /* IRQ_DMAC0_ERROR */
+        0,      /* IRQ_CGU0_ERROR */
+        0,      /* Reserved */
+        0,      /* IRQ_DPM */
+        0,      /* Reserved */
+        0,      /* IRQ_SWU0 */
+        0,      /* IRQ_SWU1 */
+        0,      /* IRQ_SWU2 */
+        0,      /* IRQ_SWU3 */
+        0,      /* IRQ_SWU4 */
+        0,      /* IRQ_SWU4 */
+        0,      /* IRQ_SWU6 */
+};
+
diff --git a/arch/blackfin/mach-bf609/pm.c b/arch/blackfin/mach-bf609/pm.c
index b76966eb16ad..dacafc163f76 100644
--- a/arch/blackfin/mach-bf609/pm.c
+++ b/arch/blackfin/mach-bf609/pm.c
@@ -11,13 +11,14 @@
 #include <linux/interrupt.h>
 #include <linux/gpio.h>
 #include <linux/irq.h>
-
 #include <linux/delay.h>
+#include <linux/syscore_ops.h>
 
 #include <asm/dpmc.h>
 #include <asm/pm.h>
 #include <mach/pm.h>
 #include <asm/blackfin.h>
+#include <asm/mem_init.h>
 
 /***********************************************************/
 /*                                                         */
@@ -132,60 +133,30 @@ void bfin_cpu_suspend(void)
 }
 
 __attribute__((l1_text))
-void bfin_deepsleep(unsigned long mask)
+void bf609_ddr_sr(void)
 {
-        uint32_t dpm0_ctl;
-
-        bfin_write32(DPM0_WAKE_EN, 0x10);
-        bfin_write32(DPM0_WAKE_POL, 0x10);
-        dpm0_ctl = 0x00000008;
-        bfin_write32(DPM0_CTL, dpm0_ctl);
-        SSYNC();
-        __asm__ __volatile__( \
-                        ".align 8;" \
-                        "idle;" \
-                        : : \
-                        );
-#ifdef CONFIG_BFIN_PM_WAKEUP_TIME_BENCH
-        __asm__ __volatile__(
-                "R0 = 0;"
-                "CYCLES = R0;"
-                "CYCLES2 = R0;"
-                "R0 = SYSCFG;"
-                "BITSET(R0, 1);"
-                "SYSCFG = R0;"
-                : : : "R0"
-        );
-#endif
-
+        dmc_enter_self_refresh();
 }
 
 __attribute__((l1_text))
-void bf609_ddr_sr(void)
+void bf609_ddr_sr_exit(void)
 {
-        uint32_t reg;
-
-        reg = bfin_read_DMC0_CTL();
-        reg |= 0x8;
-        bfin_write_DMC0_CTL(reg);
+        dmc_exit_self_refresh();
 
-        while (!(bfin_read_DMC0_STAT() & 0x8))
+        /* After wake up from deep sleep and exit DDR from self refress mode,
+         * should wait till CGU PLL is locked.
+         */
+        while (bfin_read32(CGU0_STAT) & CLKSALGN)
                 continue;
 }
 
 __attribute__((l1_text))
-void bf609_ddr_sr_exit(void)
+void bf609_resume_ccbuf(void)
 {
-        uint32_t reg;
-        while (!(bfin_read_DMC0_STAT() & 0x1))
-                continue;
+        bfin_write32(DPM0_CCBF_EN, 3);
+        bfin_write32(DPM0_CTL, 2);
 
-        reg = bfin_read_DMC0_CTL();
-        reg &= ~0x8;
-        bfin_write_DMC0_CTL(reg);
-
-        while ((bfin_read_DMC0_STAT() & 0x8))
-                continue;
+        while ((bfin_read32(DPM0_STAT) & 0xf) != 1);
 }
 
 __attribute__((l1_text))
@@ -203,20 +174,25 @@ void bfin_hibernate_syscontrol(void)
         bfin_write32(DPM0_RESTORE5, bfin_read32(DPM0_RESTORE5) | 4);
 }
 
-#ifndef CONFIG_BF60x
-# define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
-#else
-# define SIC_SYSIRQ(irq)        ((irq) - IVG15)
-#endif
-void bfin_hibernate(unsigned long mask)
+#define IRQ_SID(irq)   ((irq) - IVG15)
+asmlinkage void enter_deepsleep(void);
+
+__attribute__((l1_text))
+void bfin_deepsleep(unsigned long mask, unsigned long pol_mask)
 {
-        bfin_write32(DPM0_WAKE_EN, 0x10);
-        bfin_write32(DPM0_WAKE_POL, 0x10);
+        bfin_write32(DPM0_WAKE_EN, mask);
+        bfin_write32(DPM0_WAKE_POL, pol_mask);
+        SSYNC();
+        enter_deepsleep();
+}
+
+void bfin_hibernate(unsigned long mask, unsigned long pol_mask)
+{
+        bfin_write32(DPM0_WAKE_EN, mask);
+        bfin_write32(DPM0_WAKE_POL, pol_mask);
         bfin_write32(DPM0_PGCNTR, 0x0000FFFF);
         bfin_write32(DPM0_HIB_DIS, 0xFFFF);
 
-        printk(KERN_DEBUG "hibernate: restore %x pgcnt %x\n", bfin_read32(DPM0_RESTORE0), bfin_read32(DPM0_PGCNTR));
-
         bf609_hibernate();
 }
 
@@ -290,10 +266,11 @@ void bf609_cpu_pm_enter(suspend_state_t state)
                 printk(KERN_DEBUG "Unable to get irq wake\n");
 
         if (state == PM_SUSPEND_STANDBY)
-                bfin_deepsleep(wakeup);
+                bfin_deepsleep(wakeup, wakeup_pol);
         else {
-                bfin_hibernate(wakeup);
+                bfin_hibernate(wakeup, wakeup_pol);
         }
+
 }
 
 int bf609_cpu_pm_prepare(void)
@@ -312,20 +289,36 @@ static struct bfin_cpu_pm_fns bf609_cpu_pm = {
         .finish         = bf609_cpu_pm_finish,
 };
 
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+static int smc_pm_syscore_suspend(void)
+{
+        bf609_nor_flash_exit();
+        return 0;
+}
+
+static void smc_pm_syscore_resume(void)
+{
+        bf609_nor_flash_init();
+}
+
+static struct syscore_ops smc_pm_syscore_ops = {
+        .suspend        = smc_pm_syscore_suspend,
+        .resume         = smc_pm_syscore_resume,
+};
+#endif
+
 static irqreturn_t test_isr(int irq, void *dev_id)
 {
         printk(KERN_DEBUG "gpio irq %d\n", irq);
+        if (irq == 231)
+                bfin_sec_raise_irq(IRQ_SID(IRQ_SOFT1));
         return IRQ_HANDLED;
 }
 
 static irqreturn_t dpm0_isr(int irq, void *dev_id)
 {
-        uint32_t wake_stat;
-
-        wake_stat = bfin_read32(DPM0_WAKE_STAT);
-        printk(KERN_DEBUG "enter %s wake stat %08x\n", __func__, wake_stat);
-
-        bfin_write32(DPM0_WAKE_STAT, wake_stat);
+        bfin_write32(DPM0_WAKE_STAT, bfin_read32(DPM0_WAKE_STAT));
+        bfin_write32(CGU0_STAT, bfin_read32(CGU0_STAT));
         return IRQ_HANDLED;
 }
 
@@ -334,7 +327,11 @@ static int __init bf609_init_pm(void)
         int irq;
         int error;
 
-#if CONFIG_PM_BFIN_WAKE_PE12
+#if defined(CONFIG_MTD_PHYSMAP) || defined(CONFIG_MTD_PHYSMAP_MODULE)
+        register_syscore_ops(&smc_pm_syscore_ops);
+#endif
+
+#ifdef CONFIG_PM_BFIN_WAKE_PE12
         irq = gpio_to_irq(GPIO_PE12);
         if (irq < 0) {
                 error = irq;
@@ -342,16 +339,19 @@ static int __init bf609_init_pm(void)
                                 GPIO_PE12, error);
         }
 
-        error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND, "gpiope12", NULL);
+        error = request_irq(irq, test_isr, IRQF_TRIGGER_RISING | IRQF_NO_SUSPEND
+                                | IRQF_FORCE_RESUME, "gpiope12", NULL);
         if(error < 0)
                 printk(KERN_DEBUG "Unable to get irq\n");
 #endif
 
-        error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND, "cgu0 event", NULL);
+        error = request_irq(IRQ_CGU_EVT, dpm0_isr, IRQF_NO_SUSPEND |
+                                IRQF_FORCE_RESUME, "cgu0 event", NULL);
         if(error < 0)
                 printk(KERN_DEBUG "Unable to get irq\n");
 
-        error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND, "dpm0 event", NULL);
+        error = request_irq(IRQ_DPM, dpm0_isr, IRQF_NO_SUSPEND |
+                                IRQF_FORCE_RESUME, "dpm0 event", NULL);
         if (error < 0)
                 printk(KERN_DEBUG "Unable to get irq\n");
 
diff --git a/arch/blackfin/mach-common/clocks-init.c b/arch/blackfin/mach-common/clocks-init.c
index 7ad2407d1571..2308ce52f849 100644
--- a/arch/blackfin/mach-common/clocks-init.c
+++ b/arch/blackfin/mach-common/clocks-init.c
@@ -16,23 +16,14 @@
 #include <asm/dpmc.h>
 
 #ifdef CONFIG_BF60x
-#define CSEL_P                  0
-#define S0SEL_P                 5
-#define SYSSEL_P                8
-#define S1SEL_P                 13
-#define DSEL_P                  16
-#define OSEL_P                  22
-#define ALGN_P                  29
-#define UPDT_P                  30
-#define LOCK_P                  31
 
 #define CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CLKIN_HALF)
 #define CGU_DIV_VAL \
-        ((CONFIG_CCLK_DIV   << CSEL_P)   | \
-        (CONFIG_SCLK_DIV << SYSSEL_P)   | \
-        (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
-        (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
-        (CONFIG_DCLK_DIV   << DSEL_P))
+        ((CONFIG_CCLK_DIV   << CSEL_OFFSET)   | \
+        (CONFIG_SCLK_DIV << SYSSEL_OFFSET)   | \
+        (CONFIG_SCLK0_DIV  << S0SEL_OFFSET)  | \
+        (CONFIG_SCLK1_DIV  << S1SEL_OFFSET)  | \
+        (CONFIG_DCLK_DIV   << DSEL_OFFSET))
 
 #define CONFIG_BFIN_DCLK (((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_DCLK_DIV) / 1000000)
 #if ((CONFIG_BFIN_DCLK != 125) && \
@@ -41,89 +32,7 @@
         (CONFIG_BFIN_DCLK != 225) && (CONFIG_BFIN_DCLK != 250))
 #error "DCLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
 #endif
-struct ddr_config {
-        u32 ddr_clk;
-        u32 dmc_ddrctl;
-        u32 dmc_ddrcfg;
-        u32 dmc_ddrtr0;
-        u32 dmc_ddrtr1;
-        u32 dmc_ddrtr2;
-        u32 dmc_ddrmr;
-        u32 dmc_ddrmr1;
-};
 
-struct ddr_config ddr_config_table[] __attribute__((section(".data_l1"))) = {
-        [0] = {
-                .ddr_clk    = 125,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20705212,
-                .dmc_ddrtr1 = 0x201003CF,
-                .dmc_ddrtr2 = 0x00320107,
-                .dmc_ddrmr  = 0x00000422,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [1] = {
-                .ddr_clk    = 133,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20806313,
-                .dmc_ddrtr1 = 0x2013040D,
-                .dmc_ddrtr2 = 0x00320108,
-                .dmc_ddrmr  = 0x00000632,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [2] = {
-                .ddr_clk    = 150,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20A07323,
-                .dmc_ddrtr1 = 0x20160492,
-                .dmc_ddrtr2 = 0x00320209,
-                .dmc_ddrmr  = 0x00000632,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [3] = {
-                .ddr_clk    = 166,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20A07323,
-                .dmc_ddrtr1 = 0x2016050E,
-                .dmc_ddrtr2 = 0x00320209,
-                .dmc_ddrmr  = 0x00000632,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [4] = {
-                .ddr_clk    = 200,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20a07323,
-                .dmc_ddrtr1 = 0x2016050f,
-                .dmc_ddrtr2 = 0x00320509,
-                .dmc_ddrmr  = 0x00000632,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [5] = {
-                .ddr_clk    = 225,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20E0A424,
-                .dmc_ddrtr1 = 0x302006DB,
-                .dmc_ddrtr2 = 0x0032020D,
-                .dmc_ddrmr  = 0x00000842,
-                .dmc_ddrmr1 = 0x4,
-        },
-        [6] = {
-                .ddr_clk    = 250,
-                .dmc_ddrctl = 0x00000904,
-                .dmc_ddrcfg = 0x00000422,
-                .dmc_ddrtr0 = 0x20E0A424,
-                .dmc_ddrtr1 = 0x3020079E,
-                .dmc_ddrtr2 = 0x0032020D,
-                .dmc_ddrmr  = 0x00000842,
-                .dmc_ddrmr1 = 0x4,
-        },
-};
 #else
 #define SDGCTL_WIDTH (1 << 31)  /* SDRAM external data path width */
 #define PLL_CTL_VAL \
@@ -144,43 +53,9 @@ void init_clocks(void)
          * in the middle of reprogramming things, and that'll screw us up.
          * For example, any automatic DMAs left by U-Boot for splash screens.
          */
-
 #ifdef CONFIG_BF60x
-        int i, dlldatacycle, dll_ctl;
-        bfin_write32(CGU0_DIV, CGU_DIV_VAL);
-        bfin_write32(CGU0_CTL, CGU_CTL_VAL);
-        while ((bfin_read32(CGU0_STAT) & 0x8) || !(bfin_read32(CGU0_STAT) & 0x4))
-                continue;
-
-        bfin_write32(CGU0_DIV, CGU_DIV_VAL | (1 << UPDT_P));
-        while (bfin_read32(CGU0_STAT) & (1 << 3))
-                continue;
-
-        for (i = 0; i < 7; i++) {
-                if (ddr_config_table[i].ddr_clk == CONFIG_BFIN_DCLK) {
-                        bfin_write_DDR0_CFG(ddr_config_table[i].dmc_ddrcfg);
-                        bfin_write_DDR0_TR0(ddr_config_table[i].dmc_ddrtr0);
-                        bfin_write_DDR0_TR1(ddr_config_table[i].dmc_ddrtr1);
-                        bfin_write_DDR0_TR2(ddr_config_table[i].dmc_ddrtr2);
-                        bfin_write_DDR0_MR(ddr_config_table[i].dmc_ddrmr);
-                        bfin_write_DDR0_EMR1(ddr_config_table[i].dmc_ddrmr1);
-                        bfin_write_DDR0_CTL(ddr_config_table[i].dmc_ddrctl);
-                        break;
-                }
-        }
-
-        do_sync();
-        while (!(bfin_read_DDR0_STAT() & 0x4))
-                continue;
-
-        dlldatacycle = (bfin_read_DDR0_STAT() & 0x00f00000) >> 20;
-        dll_ctl = bfin_read_DDR0_DLLCTL();
-        dll_ctl &= 0x0ff;
-        bfin_write_DDR0_DLLCTL(dll_ctl | (dlldatacycle << 8));
-
-        do_sync();
-        while (!(bfin_read_DDR0_STAT() & 0x2000))
-                continue;
+        init_cgu(CGU_DIV_VAL, CGU_CTL_VAL);
+        init_dmc(CONFIG_BFIN_DCLK);
 #else
         size_t i;
         for (i = 0; i < MAX_DMA_CHANNELS; ++i) {
diff --git a/arch/blackfin/mach-common/cpufreq.c b/arch/blackfin/mach-common/cpufreq.c
index 6e87dc13f6bf..c854a27cbeab 100644
--- a/arch/blackfin/mach-common/cpufreq.c
+++ b/arch/blackfin/mach-common/cpufreq.c
@@ -64,7 +64,8 @@ static void __init bfin_init_tables(unsigned long cclk, unsigned long sclk)
 
         /* Anomaly 273 seems to still exist on non-BF54x w/dcache turned on */
 #if ANOMALY_05000273 || ANOMALY_05000274 || \
-        (!defined(CONFIG_BF54x) && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
+        (!(defined(CONFIG_BF54x) || defined(CONFIG_BF60x)) \
+        && defined(CONFIG_BFIN_EXTMEM_DCACHEABLE))
         min_cclk = sclk * 2;
 #else
         min_cclk = sclk;
@@ -173,7 +174,7 @@ static int bfin_target(struct cpufreq_policy *poli,
 #else
                         ret = cpu_set_cclk(cpu, freqs.new * 1000);
                         if (ret != 0) {
-                                pr_debug("cpufreq set freq failed %d\n", ret);
+                                WARN_ONCE(ret, "cpufreq set freq failed %d\n", ret);
                                 break;
                         }
 #endif
diff --git a/arch/blackfin/mach-common/entry.S b/arch/blackfin/mach-common/entry.S
index 04c2fbe41a7f..1c3d2c5bb0bb 100644
--- a/arch/blackfin/mach-common/entry.S
+++ b/arch/blackfin/mach-common/entry.S
@@ -25,13 +25,6 @@
 
 #include <asm/context.S>
 
-#if defined(CONFIG_BFIN_SCRATCH_REG_RETN)
-# define EX_SCRATCH_REG RETN
-#elif defined(CONFIG_BFIN_SCRATCH_REG_RETE)
-# define EX_SCRATCH_REG RETE
-#else
-# define EX_SCRATCH_REG CYCLES
-#endif
 
 #ifdef CONFIG_EXCPT_IRQ_SYSC_L1
 .section .l1.text
diff --git a/arch/blackfin/mach-common/ints-priority.c b/arch/blackfin/mach-common/ints-priority.c
index 2729cba715b0..7ca09ec2ca53 100644
--- a/arch/blackfin/mach-common/ints-priority.c
+++ b/arch/blackfin/mach-common/ints-priority.c
@@ -26,8 +26,9 @@
 #include <asm/gpio.h>
 #include <asm/irq_handler.h>
 #include <asm/dpmc.h>
+#include <asm/traps.h>
 
-#ifndef CONFIG_BF60x
+#ifndef SEC_GCTL
 # define SIC_SYSIRQ(irq)        (irq - (IRQ_CORETMR + 1))
 #else
 # define SIC_SYSIRQ(irq)        ((irq) - IVG15)
@@ -56,7 +57,7 @@ unsigned long bfin_sic_iwr[3];	/* Up to 3 SIC_IWRx registers */
 unsigned vr_wakeup;
 #endif
 
-#ifndef CONFIG_BF60x
+#ifndef SEC_GCTL
 static struct ivgx {
         /* irq number for request_irq, available in mach-bf5xx/irq.h */
         unsigned int irqno;
@@ -143,7 +144,7 @@ static void bfin_core_unmask_irq(struct irq_data *d)
 void bfin_internal_mask_irq(unsigned int irq)
 {
         unsigned long flags = hard_local_irq_save();
-#ifndef CONFIG_BF60x
+#ifndef SEC_GCTL
 #ifdef SIC_IMASK0
         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
@@ -175,7 +176,7 @@ void bfin_internal_unmask_irq(unsigned int irq)
 {
         unsigned long flags = hard_local_irq_save();
 
-#ifndef CONFIG_BF60x
+#ifndef SEC_GCTL
 #ifdef SIC_IMASK0
         unsigned mask_bank = SIC_SYSIRQ(irq) / 32;
         unsigned mask_bit = SIC_SYSIRQ(irq) % 32;
@@ -199,7 +200,7 @@ void bfin_internal_unmask_irq(unsigned int irq)
         hard_local_irq_restore(flags);
 }
 
-#ifdef CONFIG_BF60x
+#ifdef SEC_GCTL
 static void bfin_sec_preflow_handler(struct irq_data *d)
 {
         unsigned long flags = hard_local_irq_save();
@@ -310,7 +311,24 @@ static void bfin_sec_disable(struct irq_data *d)
         hard_local_irq_restore(flags);
 }
 
-static void bfin_sec_raise_irq(unsigned int sid)
+static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority)
+{
+        unsigned long flags = hard_local_irq_save();
+        uint32_t reg_sctl;
+        int i;
+
+        bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels);
+
+        for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) {
+                reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO;
+                reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET;
+                bfin_write_SEC_SCTL(i, reg_sctl);
+        }
+
+        hard_local_irq_restore(flags);
+}
+
+void bfin_sec_raise_irq(unsigned int sid)
 {
         unsigned long flags = hard_local_irq_save();
 
@@ -396,24 +414,34 @@ void handle_sec_fault(unsigned int irq, struct irq_desc *desc)
         raw_spin_unlock(&desc->lock);
 }
 
-static int sec_suspend(void)
+void handle_core_fault(unsigned int irq, struct irq_desc *desc)
 {
-        return 0;
-}
+        struct pt_regs *fp = get_irq_regs();
 
-static void sec_resume(void)
-{
-        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
-        udelay(100);
-        bfin_write_SEC_GCTL(SEC_GCTL_EN);
-        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-}
+        raw_spin_lock(&desc->lock);
 
-static struct syscore_ops sec_pm_syscore_ops = {
-        .suspend = sec_suspend,
-        .resume = sec_resume,
-};
+        switch (irq) {
+        case IRQ_C0_DBL_FAULT:
+                double_fault_c(fp);
+                break;
+        case IRQ_C0_HW_ERR:
+                dump_bfin_process(fp);
+                dump_bfin_mem(fp);
+                show_regs(fp);
+                printk(KERN_NOTICE "Kernel Stack\n");
+                show_stack(current, NULL);
+                print_modules();
+                panic("Kernel core hardware error");
+                break;
+        case IRQ_C0_NMI_L1_PARITY_ERR:
+                panic("NMI occurs unexpectedly");
+                break;
+        default:
+                panic("Core 1 fault occurs unexpectedly");
+        }
 
+        raw_spin_unlock(&desc->lock);
+}
 #endif
 
 #ifdef CONFIG_SMP
@@ -437,7 +465,7 @@ static void bfin_internal_unmask_irq_chip(struct irq_data *d)
 }
 #endif
 
-#if defined(CONFIG_PM) && !defined(CONFIG_BF60x)
+#if defined(CONFIG_PM) && !defined(SEC_GCTL)
 int bfin_internal_set_wake(unsigned int irq, unsigned int state)
 {
         u32 bank, bit, wakeup = 0;
@@ -496,7 +524,10 @@ static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state)
         return bfin_internal_set_wake(d->irq, state);
 }
 #else
-# define bfin_internal_set_wake(irq, state)
+inline int bfin_internal_set_wake(unsigned int irq, unsigned int state)
+{
+        return 0;
+}
 # define bfin_internal_set_wake_chip NULL
 #endif
 
@@ -518,7 +549,7 @@ static struct irq_chip bfin_internal_irqchip = {
         .irq_set_wake = bfin_internal_set_wake_chip,
 };
 
-#ifdef CONFIG_BF60x
+#ifdef SEC_GCTL
 static struct irq_chip bfin_sec_irqchip = {
         .name = "SEC",
         .irq_mask_ack = bfin_sec_mask_ack_irq,
@@ -868,14 +899,6 @@ void bfin_demux_gpio_irq(unsigned int inta_irq,
 
 #else
 
-# ifndef CONFIG_BF60x
-#define NR_PINT_SYS_IRQS        4
-#define NR_PINTS                160
-# else
-#define NR_PINT_SYS_IRQS        6
-#define NR_PINTS                112
-#endif
-
 #define NR_PINT_BITS            32
 #define IRQ_NOT_AVAIL           0xFF
 
@@ -897,29 +920,21 @@ static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = {
 #endif
 };
 
-#ifndef CONFIG_BF60x
 inline unsigned int get_irq_base(u32 bank, u8 bmap)
 {
         unsigned int irq_base;
 
+#ifndef CONFIG_BF60x
         if (bank < 2) {         /*PA-PB */
                 irq_base = IRQ_PA0 + bmap * 16;
         } else {                /*PC-PJ */
                 irq_base = IRQ_PC0 + bmap * 16;
         }
-
-        return irq_base;
-}
 #else
-inline unsigned int get_irq_base(u32 bank, u8 bmap)
-{
-        unsigned int irq_base;
-
         irq_base = IRQ_PA0 + bank * 16 + bmap * 16;
-
+#endif
         return irq_base;
 }
-#endif
 
         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
 void init_pint_lut(void)
@@ -1089,6 +1104,9 @@ static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type)
 }
 
 #ifdef CONFIG_PM
+static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS];
+static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS];
+
 static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 {
         u32 pint_irq;
@@ -1124,6 +1142,59 @@ static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state)
 
         return 0;
 }
+
+void bfin_pint_suspend(void)
+{
+        u32 bank;
+
+        for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
+                save_pint_reg[bank].mask_set = pint[bank]->mask_set;
+                save_pint_reg[bank].assign = pint[bank]->assign;
+                save_pint_reg[bank].edge_set = pint[bank]->edge_set;
+                save_pint_reg[bank].invert_set = pint[bank]->invert_set;
+        }
+}
+
+void bfin_pint_resume(void)
+{
+        u32 bank;
+
+        for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) {
+                pint[bank]->mask_set = save_pint_reg[bank].mask_set;
+                pint[bank]->assign = save_pint_reg[bank].assign;
+                pint[bank]->edge_set = save_pint_reg[bank].edge_set;
+                pint[bank]->invert_set = save_pint_reg[bank].invert_set;
+        }
+}
+
+#ifdef SEC_GCTL
+static int sec_suspend(void)
+{
+        u32 bank;
+
+        for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
+                save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0));
+        return 0;
+}
+
+static void sec_resume(void)
+{
+        u32 bank;
+
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+
+        for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++)
+                bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]);
+}
+
+static struct syscore_ops sec_pm_syscore_ops = {
+        .suspend = sec_suspend,
+        .resume = sec_resume,
+};
+#endif
 #else
 # define bfin_gpio_set_wake NULL
 #endif
@@ -1230,6 +1301,7 @@ void __cpuinit init_exception_vectors(void)
         CSYNC();
 }
 
+#ifndef SEC_GCTL
 /*
  * This function should be called during kernel startup to initialize
  * the BFin IRQ handling routines.
@@ -1240,7 +1312,6 @@ int __init init_arch_irq(void)
         int irq;
         unsigned long ilat = 0;
 
-#ifndef CONFIG_BF60x
         /*  Disable all the peripheral intrs  - page 4-29 HW Ref manual */
 #ifdef SIC_IMASK0
         bfin_write_SIC_IMASK0(SIC_UNMASK_ALL);
@@ -1255,9 +1326,6 @@ int __init init_arch_irq(void)
 #else
         bfin_write_SIC_IMASK(SIC_UNMASK_ALL);
 #endif
-#else /* CONFIG_BF60x */
-        bfin_write_SEC_GCTL(SEC_GCTL_RESET);
-#endif
 
         local_irq_disable();
 
@@ -1267,10 +1335,6 @@ int __init init_arch_irq(void)
         pint[1]->assign = CONFIG_PINT1_ASSIGN;
         pint[2]->assign = CONFIG_PINT2_ASSIGN;
         pint[3]->assign = CONFIG_PINT3_ASSIGN;
-# ifdef CONFIG_BF60x
-        pint[4]->assign = CONFIG_PINT4_ASSIGN;
-        pint[5]->assign = CONFIG_PINT5_ASSIGN;
-# endif
 # endif
         /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
         init_pint_lut();
@@ -1283,7 +1347,6 @@ int __init init_arch_irq(void)
                         irq_set_chip(irq, &bfin_internal_irqchip);
 
                 switch (irq) {
-#ifndef CONFIG_BF60x
 #if BFIN_GPIO_PINT
                 case IRQ_PINT0:
                 case IRQ_PINT1:
@@ -1319,7 +1382,6 @@ int __init init_arch_irq(void)
                         irq_set_handler(irq, handle_percpu_irq);
                         break;
 #endif
-#endif
 
 #ifdef CONFIG_TICKSOURCE_CORETMR
                 case IRQ_CORETMR:
@@ -1349,8 +1411,7 @@ int __init init_arch_irq(void)
 
         init_mach_irq();
 
-#ifndef CONFIG_BF60x
-#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) && !defined(CONFIG_BF60x)
+#if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE))
         for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++)
                 irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip,
                                          handle_level_irq);
@@ -1360,28 +1421,6 @@ int __init init_arch_irq(void)
                 irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
                 irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
                                          handle_level_irq);
-#else
-        for (irq = BFIN_IRQ(0); irq <= SYS_IRQS; irq++) {
-                if (irq < CORE_IRQS) {
-                        irq_set_chip(irq, &bfin_sec_irqchip);
-                        __irq_set_handler(irq, handle_sec_fault, 0, NULL);
-                } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
-                        irq_set_chip(irq, &bfin_sec_irqchip);
-                        irq_set_chained_handler(irq, bfin_demux_gpio_irq);
-                } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
-                        irq_set_chip(irq, &bfin_sec_irqchip);
-                        irq_set_handler(irq, handle_percpu_irq);
-                } else {
-                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
-                                        handle_fasteoi_irq);
-                        __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
-                }
-        }
-        for (irq = GPIO_IRQ_BASE;
-                irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
-                irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
-                                        handle_level_irq);
-#endif
         bfin_write_IMASK(0);
         CSYNC();
         ilat = bfin_read_ILAT();
@@ -1393,7 +1432,6 @@ int __init init_arch_irq(void)
         /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx,
          * local_irq_enable()
          */
-#ifndef CONFIG_BF60x
         program_IAR();
         /* Therefore it's better to setup IARs before interrupts enabled */
         search_IAR();
@@ -1427,23 +1465,6 @@ int __init init_arch_irq(void)
 #else
         bfin_write_SIC_IWR(IWR_DISABLE_ALL);
 #endif
-#else  /* CONFIG_BF60x */
-        /* Enable interrupts IVG7-15 */
-        bfin_irq_flags |= IMASK_IVG15 |
-            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
-            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
-
-
-        bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
-        bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
-        bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
-        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
-        udelay(100);
-        bfin_write_SEC_GCTL(SEC_GCTL_EN);
-        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
-        init_software_driven_irq();
-        register_syscore_ops(&sec_pm_syscore_ops);
-#endif
         return 0;
 }
 
@@ -1452,14 +1473,11 @@ __attribute__((l1_text))
 #endif
 static int vec_to_irq(int vec)
 {
-#ifndef CONFIG_BF60x
         struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst;
         struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop;
         unsigned long sic_status[3];
-#endif
         if (likely(vec == EVT_IVTMR_P))
                 return IRQ_CORETMR;
-#ifndef CONFIG_BF60x
 #ifdef SIC_ISR
         sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR();
 #else
@@ -1488,11 +1506,119 @@ static int vec_to_irq(int vec)
 #endif
                         return ivg->irqno;
         }
-#else
-        /* for bf60x read */
+}
+
+#else /* SEC_GCTL */
+
+/*
+ * This function should be called during kernel startup to initialize
+ * the BFin IRQ handling routines.
+ */
+
+int __init init_arch_irq(void)
+{
+        int irq;
+        unsigned long ilat = 0;
+
+        bfin_write_SEC_GCTL(SEC_GCTL_RESET);
+
+        local_irq_disable();
+
+#if BFIN_GPIO_PINT
+# ifdef CONFIG_PINTx_REASSIGN
+        pint[0]->assign = CONFIG_PINT0_ASSIGN;
+        pint[1]->assign = CONFIG_PINT1_ASSIGN;
+        pint[2]->assign = CONFIG_PINT2_ASSIGN;
+        pint[3]->assign = CONFIG_PINT3_ASSIGN;
+        pint[4]->assign = CONFIG_PINT4_ASSIGN;
+        pint[5]->assign = CONFIG_PINT5_ASSIGN;
+# endif
+        /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */
+        init_pint_lut();
+#endif
+
+        for (irq = 0; irq <= SYS_IRQS; irq++) {
+                if (irq <= IRQ_CORETMR) {
+                        irq_set_chip(irq, &bfin_core_irqchip);
+#ifdef CONFIG_TICKSOURCE_CORETMR
+                        if (irq == IRQ_CORETMR)
+# ifdef CONFIG_SMP
+                                irq_set_handler(irq, handle_percpu_irq);
+# else
+                                irq_set_handler(irq, handle_simple_irq);
+# endif
+#endif
+                } else if (irq < BFIN_IRQ(0)) {
+                        irq_set_chip_and_handler(irq, &bfin_internal_irqchip,
+                                        handle_simple_irq);
+                } else if (irq == IRQ_SEC_ERR) {
+                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
+                                        handle_sec_fault);
+                } else if (irq < CORE_IRQS && irq >= IRQ_C0_DBL_FAULT) {
+                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
+                                        handle_core_fault);
+                } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        irq_set_chained_handler(irq, bfin_demux_gpio_irq);
+                } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) {
+                        irq_set_chip(irq, &bfin_sec_irqchip);
+                        irq_set_handler(irq, handle_percpu_irq);
+                } else {
+                        irq_set_chip_and_handler(irq, &bfin_sec_irqchip,
+                                        handle_fasteoi_irq);
+                        __irq_set_preflow_handler(irq, bfin_sec_preflow_handler);
+                }
+        }
+        for (irq = GPIO_IRQ_BASE;
+                irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++)
+                irq_set_chip_and_handler(irq, &bfin_gpio_irqchip,
+                                        handle_level_irq);
+
+        bfin_write_IMASK(0);
+        CSYNC();
+        ilat = bfin_read_ILAT();
+        CSYNC();
+        bfin_write_ILAT(ilat);
+        CSYNC();
+
+        printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n");
+
+        bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
+
+        bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority);
+
+        /* Enable interrupts IVG7-15 */
+        bfin_irq_flags |= IMASK_IVG15 |
+            IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 |
+            IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW;
+
+
+        bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN);
+        bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0));
+        bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0));
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET);
+        udelay(100);
+        bfin_write_SEC_GCTL(SEC_GCTL_EN);
+        bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+        bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN);
+
+        init_software_driven_irq();
+        register_syscore_ops(&sec_pm_syscore_ops);
+
+        return 0;
+}
+
+#ifdef CONFIG_DO_IRQ_L1
+__attribute__((l1_text))
+#endif
+static int vec_to_irq(int vec)
+{
+        if (likely(vec == EVT_IVTMR_P))
+                return IRQ_CORETMR;
+
         return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID));
-#endif  /* end of CONFIG_BF60x */
 }
+#endif  /* SEC_GCTL */
 
 #ifdef CONFIG_DO_IRQ_L1
 __attribute__((l1_text))
@@ -1514,6 +1640,10 @@ int __ipipe_get_irq_priority(unsigned irq)
         if (irq <= IRQ_CORETMR)
                 return irq;
 
+#ifdef SEC_GCTL
+        if (irq >= BFIN_IRQ(0))
+                return IVG11;
+#else
         for (ient = 0; ient < NR_PERI_INTS; ient++) {
                 struct ivgx *ivg = ivg_table + ient;
                 if (ivg->irqno == irq) {
@@ -1524,6 +1654,7 @@ int __ipipe_get_irq_priority(unsigned irq)
                         }
                 }
         }
+#endif
 
         return IVG15;
 }
@@ -1536,8 +1667,6 @@ asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs)
 {
         struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr();
         struct ipipe_domain *this_domain = __ipipe_current_domain;
-        struct ivgx *ivg_stop = ivg7_13[vec-IVG7].istop;
-        struct ivgx *ivg = ivg7_13[vec-IVG7].ifirst;
         int irq, s = 0;
 
         irq = vec_to_irq(vec);
diff --git a/arch/blackfin/mach-common/pm.c b/arch/blackfin/mach-common/pm.c
index ca6655e0d653..87bfe549ad3f 100644
--- a/arch/blackfin/mach-common/pm.c
+++ b/arch/blackfin/mach-common/pm.c
@@ -172,6 +172,10 @@ int bfin_pm_suspend_mem_enter(void)
 
         bfin_gpio_pm_hibernate_suspend();
 
+#if BFIN_GPIO_PINT
+        bfin_pint_suspend();
+#endif
+
 #if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
         flushinv_all_dcache();
 #endif
@@ -190,6 +194,10 @@ int bfin_pm_suspend_mem_enter(void)
         _enable_icplb();
         _enable_dcplb();
 
+#if BFIN_GPIO_PINT
+        bfin_pint_resume();
+#endif
+
         bfin_gpio_pm_hibernate_restore();
         blackfin_dma_resume();