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-rw-r--r--arch/arm/mach-exynos4/cpu.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/arch/arm/mach-exynos4/cpu.c b/arch/arm/mach-exynos4/cpu.c
index 02ec52a99274..35fe8421bc34 100644
--- a/arch/arm/mach-exynos4/cpu.c
+++ b/arch/arm/mach-exynos4/cpu.c
@@ -198,20 +198,25 @@ void __init exynos4_init_clocks(int xtal)
198 exynos4_setup_clocks(); 198 exynos4_setup_clocks();
199} 199}
200 200
201static void exynos4_gic_irq_eoi(struct irq_data *d) 201static void exynos4_gic_irq_fix_base(struct irq_data *d)
202{ 202{
203 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 203 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
204 204
205 gic_data->cpu_base = S5P_VA_GIC_CPU + 205 gic_data->cpu_base = S5P_VA_GIC_CPU +
206 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id()); 206 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
207
208 gic_data->dist_base = S5P_VA_GIC_DIST +
209 (EXYNOS4_GIC_BANK_OFFSET * smp_processor_id());
207} 210}
208 211
209void __init exynos4_init_irq(void) 212void __init exynos4_init_irq(void)
210{ 213{
211 int irq; 214 int irq;
212 215
213 gic_init(0, IRQ_SPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU); 216 gic_init(0, IRQ_PPI(0), S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
214 gic_arch_extn.irq_eoi = exynos4_gic_irq_eoi; 217 gic_arch_extn.irq_eoi = exynos4_gic_irq_fix_base;
218 gic_arch_extn.irq_unmask = exynos4_gic_irq_fix_base;
219 gic_arch_extn.irq_mask = exynos4_gic_irq_fix_base;
215 220
216 for (irq = 0; irq < MAX_COMBINER_NR; irq++) { 221 for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
217 222