1 files changed, 0 insertions, 6 deletions

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index b15597400105..0404ccbb8aa3 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -148,10 +148,6 @@ ENDPROC(cpu_v7_do_resume)
  *      Initialise TLB, Caches, and MMU state ready to switch the MMU
  *      on.  Return in r0 the new CP15 C1 control register setting.
  *
- *      We automatically detect if we have a Harvard cache, and use the
- *      Harvard cache control instructions insead of the unified cache
- *      control instructions.
- *
  *      This should be able to cover all ARMv7 cores.
  *
  *      It is assumed that:
@@ -251,9 +247,7 @@ __v7_setup:
 #endif
 
 3:      mov     r10, #0
-#ifdef HARVARD_CACHE
         mcr     p15, 0, r10, c7, c5, 0          @ I+BTB cache invalidate
-#endif
         dsb
 #ifdef CONFIG_MMU
         mcr     p15, 0, r10, c8, c7, 0          @ invalidate I + D TLBs