150 files changed, 8269 insertions, 885 deletions

diff --git a/Documentation/devicetree/bindings/crypto/mv_cesa.txt b/Documentation/devicetree/bindings/crypto/mv_cesa.txt
new file mode 100644
index 000000000000..47229b1a594b
--- /dev/null
+++ b/Documentation/devicetree/bindings/crypto/mv_cesa.txt
@@ -0,0 +1,20 @@
+Marvell Cryptographic Engines And Security Accelerator
+
+Required properties:
+- compatible : should be "marvell,orion-crypto"
+- reg : base physical address of the engine and length of memory mapped
+        region, followed by base physical address of sram and its memory
+        length
+- reg-names : "regs" , "sram";
+- interrupts : interrupt number
+
+Examples:
+
+        crypto@30000 {
+                compatible = "marvell,orion-crypto";
+                reg = <0x30000 0x10000>,
+                      <0x4000000 0x800>;
+                reg-names = "regs" , "sram";
+                interrupts = <22>;
+                status = "okay";
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-fan.txt b/Documentation/devicetree/bindings/gpio/gpio-fan.txt
new file mode 100644
index 000000000000..2dd457a3469a
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-fan.txt
@@ -0,0 +1,25 @@
+Bindings for fan connected to GPIO lines
+
+Required properties:
+- compatible : "gpio-fan"
+- gpios: Specifies the pins that map to bits in the control value,
+  ordered MSB-->LSB.
+- gpio-fan,speed-map: A mapping of possible fan RPM speeds and the
+  control value that should be set to achieve them. This array
+  must have the RPM values in ascending order.
+
+Optional properties:
+- alarm-gpios: This pin going active indicates something is wrong with
+  the fan, and a udev event will be fired.
+
+Examples:
+
+        gpio_fan {
+                compatible = "gpio-fan";
+                gpios = <&gpio1 14 1
+                         &gpio1 13 1>;
+                gpio-fan,speed-map = <0    0
+                                      3000 1
+                                      6000 2>;
+                alarm-gpios = <&gpio1 15 1>;
+        };
diff --git a/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
new file mode 100644
index 000000000000..a6f3bec1da7d
--- /dev/null
+++ b/Documentation/devicetree/bindings/gpio/gpio-mvebu.txt
@@ -0,0 +1,53 @@
+* Marvell EBU GPIO controller
+
+Required properties:
+
+- compatible : Should be "marvell,orion-gpio", "marvell,mv78200-gpio"
+  or "marvell,armadaxp-gpio". "marvell,orion-gpio" should be used for
+  Orion, Kirkwood, Dove, Discovery (except MV78200) and Armada
+  370. "marvell,mv78200-gpio" should be used for the Discovery
+  MV78200. "marvel,armadaxp-gpio" should be used for all Armada XP
+  SoCs (MV78230, MV78260, MV78460).
+
+- reg: Address and length of the register set for the device. Only one
+  entry is expected, except for the "marvell,armadaxp-gpio" variant
+  for which two entries are expected: one for the general registers,
+  one for the per-cpu registers.
+
+- interrupts: The list of interrupts that are used for all the pins
+  managed by this GPIO bank. There can be more than one interrupt
+  (example: 1 interrupt per 8 pins on Armada XP, which means 4
+  interrupts per bank of 32 GPIOs).
+
+- interrupt-controller: identifies the node as an interrupt controller
+
+- #interrupt-cells: specifies the number of cells needed to encode an
+  interrupt source. Should be two.
+  The first cell is the GPIO number.
+  The second cell is used to specify flags:
+    bits[3:0] trigger type and level flags:
+      1 = low-to-high edge triggered.
+      2 = high-to-low edge triggered.
+      4 = active high level-sensitive.
+      8 = active low level-sensitive.
+
+- gpio-controller: marks the device node as a gpio controller
+
+- ngpios: number of GPIOs this controller has
+
+- #gpio-cells: Should be two. The first cell is the pin number. The
+  second cell is reserved for flags, unused at the moment.
+
+Example:
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupt-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
new file mode 100644
index 000000000000..01ef408e205f
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-370-pinctrl.txt
@@ -0,0 +1,95 @@
+* Marvell Armada 370 SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6710-pinctrl"
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, uart0(rxd)
+mpp1          1        gpo, uart0(txd)
+mpp2          2        gpio, i2c0(sck), uart0(txd)
+mpp3          3        gpio, i2c0(sda), uart0(rxd)
+mpp4          4        gpio, cpu_pd(vdd)
+mpp5          5        gpo, ge0(txclko), uart1(txd), spi1(clk), audio(mclk)
+mpp6          6        gpio, ge0(txd0), sata0(prsnt), tdm(rst), audio(sdo)
+mpp7          7        gpo, ge0(txd1), tdm(tdx), audio(lrclk)
+mpp8          8        gpio, ge0(txd2), uart0(rts), tdm(drx), audio(bclk)
+mpp9          9        gpo, ge0(txd3), uart1(txd), sd0(clk), audio(spdifo)
+mpp10         10       gpio, ge0(txctl), uart0(cts), tdm(fsync), audio(sdi)
+mpp11         11       gpio, ge0(rxd0), uart1(rxd), sd0(cmd), spi0(cs1),
+                       sata1(prsnt), spi1(cs1)
+mpp12         12       gpio, ge0(rxd1), i2c1(sda), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp13         13       gpio, ge0(rxd2), i2c1(sck), sd0(d1), tdm(pclk),
+                       audio(rmclk)
+mpp14         14       gpio, ge0(rxd3), pcie(clkreq0), sd0(d2), spi1(mosi),
+                       spi0(cs2)
+mpp15         15       gpio, ge0(rxctl), pcie(clkreq1), sd0(d3), spi1(miso),
+                       spi0(cs3)
+mpp16         16       gpio, ge0(rxclk), uart1(rxd), tdm(int), audio(extclk)
+mpp17         17       gpo, ge(mdc)
+mpp18         18       gpio, ge(mdio)
+mpp19         19       gpio, ge0(txclk), ge1(txclkout), tdm(pclk)
+mpp20         20       gpo, ge0(txd4), ge1(txd0)
+mpp21         21       gpo, ge0(txd5), ge1(txd1), uart1(txd)
+mpp22         22       gpo, ge0(txd6), ge1(txd2), uart0(rts)
+mpp23         23       gpo, ge0(txd7), ge1(txd3), spi1(mosi)
+mpp24         24       gpio, ge0(col), ge1(txctl), spi1(cs0)
+mpp25         25       gpio, ge0(rxerr), ge1(rxd0), uart1(rxd)
+mpp26         26       gpio, ge0(crs), ge1(rxd1), spi1(miso)
+mpp27         27       gpio, ge0(rxd4), ge1(rxd2), uart0(cts)
+mpp28         28       gpio, ge0(rxd5), ge1(rxd3)
+mpp29         29       gpio, ge0(rxd6), ge1(rxctl), i2c1(sda)
+mpp30         30       gpio, ge0(rxd7), ge1(rxclk), i2c1(sck)
+mpp31         31       gpio, tclk, ge0(txerr)
+mpp32         32       gpio, spi0(cs0)
+mpp33         33       gpio, dev(bootcs), spi0(cs0)
+mpp34         34       gpo, dev(wen0), spi0(mosi)
+mpp35         35       gpo, dev(oen), spi0(sck)
+mpp36         36       gpo, dev(a1), spi0(miso)
+mpp37         37       gpo, dev(a0), sata0(prsnt)
+mpp38         38       gpio, dev(ready), uart1(cts), uart0(cts)
+mpp39         39       gpo, dev(ad0), audio(spdifo)
+mpp40         40       gpio, dev(ad1), uart1(rts), uart0(rts)
+mpp41         41       gpio, dev(ad2), uart1(rxd)
+mpp42         42       gpo, dev(ad3), uart1(txd)
+mpp43         43       gpo, dev(ad4), audio(bclk)
+mpp44         44       gpo, dev(ad5), audio(mclk)
+mpp45         45       gpo, dev(ad6), audio(lrclk)
+mpp46         46       gpo, dev(ad7), audio(sdo)
+mpp47         47       gpo, dev(ad8), sd0(clk), audio(spdifo)
+mpp48         48       gpio, dev(ad9), uart0(rts), sd0(cmd), sata1(prsnt),
+                       spi0(cs1)
+mpp49         49       gpio, dev(ad10), pcie(clkreq1), sd0(d0), spi1(cs0),
+                       audio(spdifi)
+mpp50         50       gpio, dev(ad11), uart0(cts), sd0(d1), spi1(miso),
+                       audio(rmclk)
+mpp51         51       gpio, dev(ad12), i2c1(sda), sd0(d2), spi1(mosi)
+mpp52         52       gpio, dev(ad13), i2c1(sck), sd0(d3), spi1(sck)
+mpp53         53       gpio, dev(ad14), sd0(clk), tdm(pclk), spi0(cs2),
+                       pcie(clkreq1)
+mpp54         54       gpo, dev(ad15), tdm(dtx)
+mpp55         55       gpio, dev(cs1), uart1(txd), tdm(rst), sata1(prsnt),
+                       sata0(prsnt)
+mpp56         56       gpio, dev(cs2), uart1(cts), uart0(cts), spi0(cs3),
+                       pcie(clkreq0), spi1(cs1)
+mpp57         57       gpio, dev(cs3), uart1(rxd), tdm(fsync), sata0(prsnt),
+                       audio(sdo)
+mpp58         58       gpio, dev(cs0), uart1(rts), tdm(int), audio(extclk),
+                       uart0(rts)
+mpp59         59       gpo, dev(ale0), uart1(rts), uart0(rts), audio(bclk)
+mpp60         60       gpio, dev(ale1), uart1(rxd), sata0(prsnt), pcie(rst-out),
+                       audio(sdi)
+mpp61         61       gpo, dev(wen1), uart1(txd), audio(rclk)
+mpp62         62       gpio, dev(a2), uart1(cts), tdm(drx), pcie(clkreq0),
+                       audio(mclk), uart0(cts)
+mpp63         63       gpo, spi0(sck), tclk
+mpp64         64       gpio, spi0(miso), spi0-1(cs1)
+mpp65         65       gpio, spi0(mosi), spi0-1(cs2)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
new file mode 100644
index 000000000000..bfa0a2e5e0cb
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,armada-xp-pinctrl.txt
@@ -0,0 +1,100 @@
+* Marvell Armada XP SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,mv78230-pinctrl", "marvell,mv78260-pinctrl",
+              "marvell,mv78460-pinctrl"
+
+This driver supports all Armada XP variants, i.e. mv78230, mv78260, and mv78460.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Armada XP (all variants)
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, ge0(txclko), lcd(d0)
+mpp1          1        gpio, ge0(txd0), lcd(d1)
+mpp2          2        gpio, ge0(txd1), lcd(d2)
+mpp3          3        gpio, ge0(txd2), lcd(d3)
+mpp4          4        gpio, ge0(txd3), lcd(d4)
+mpp5          5        gpio, ge0(txctl), lcd(d5)
+mpp6          6        gpio, ge0(rxd0), lcd(d6)
+mpp7          7        gpio, ge0(rxd1), lcd(d7)
+mpp8          8        gpio, ge0(rxd2), lcd(d8)
+mpp9          9        gpio, ge0(rxd3), lcd(d9)
+mpp10         10       gpio, ge0(rxctl), lcd(d10)
+mpp11         11       gpio, ge0(rxclk), lcd(d11)
+mpp12         12       gpio, ge0(txd4), ge1(txd0), lcd(d12)
+mpp13         13       gpio, ge0(txd5), ge1(txd1), lcd(d13)
+mpp14         14       gpio, ge0(txd6), ge1(txd2), lcd(d15)
+mpp15         15       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp16         16       gpio, ge0(txd7), ge1(txd3), lcd(d16)
+mpp17         17       gpio, ge0(col), ge1(txctl), lcd(d17)
+mpp18         18       gpio, ge0(rxerr), ge1(rxd0), lcd(d18), ptp(trig)
+mpp19         19       gpio, ge0(crs), ge1(rxd1), lcd(d19), ptp(evreq)
+mpp20         20       gpio, ge0(rxd4), ge1(rxd2), lcd(d20), ptp(clk)
+mpp21         21       gpio, ge0(rxd5), ge1(rxd3), lcd(d21), mem(bat)
+mpp22         22       gpio, ge0(rxd6), ge1(rxctl), lcd(d22), sata0(prsnt)
+mpp23         23       gpio, ge0(rxd7), ge1(rxclk), lcd(d23), sata1(prsnt)
+mpp24         24       gpio, lcd(hsync), sata1(prsnt), nf(bootcs-re), tdm(rst)
+mpp25         25       gpio, lcd(vsync), sata0(prsnt), nf(bootcs-we), tdm(pclk)
+mpp26         26       gpio, lcd(clk), tdm(fsync), vdd(cpu1-pd)
+mpp27         27       gpio, lcd(e), tdm(dtx), ptp(trig)
+mpp28         28       gpio, lcd(pwm), tdm(drx), ptp(evreq)
+mpp29         29       gpio, lcd(ref-clk), tdm(int0), ptp(clk), vdd(cpu0-pd)
+mpp30         30       gpio, tdm(int1), sd0(clk)
+mpp31         31       gpio, tdm(int2), sd0(cmd), vdd(cpu0-pd)
+mpp32         32       gpio, tdm(int3), sd0(d0), vdd(cpu1-pd)
+mpp33         33       gpio, tdm(int4), sd0(d1), mem(bat)
+mpp34         34       gpio, tdm(int5), sd0(d2), sata0(prsnt)
+mpp35         35       gpio, tdm(int6), sd0(d3), sata1(prsnt)
+mpp36         36       gpio, spi(mosi)
+mpp37         37       gpio, spi(miso)
+mpp38         38       gpio, spi(sck)
+mpp39         39       gpio, spi(cs0)
+mpp40         40       gpio, spi(cs1), uart2(cts), lcd(vga-hsync), vdd(cpu1-pd),
+                       pcie(clkreq0)
+mpp41         41       gpio, spi(cs2), uart2(rts), lcd(vga-vsync), sata1(prsnt),
+                       pcie(clkreq1)
+mpp42         42       gpio, uart2(rxd), uart0(cts), tdm(int7), tdm-1(timer),
+                       vdd(cpu0-pd)
+mpp43         43       gpio, uart2(txd), uart0(rts), spi(cs3), pcie(rstout),
+                       vdd(cpu2-3-pd){1}
+mpp44         44       gpio, uart2(cts), uart3(rxd), spi(cs4), pcie(clkreq2),
+                       mem(bat)
+mpp45         45       gpio, uart2(rts), uart3(txd), spi(cs5), sata1(prsnt)
+mpp46         46       gpio, uart3(rts), uart1(rts), spi(cs6), sata0(prsnt)
+mpp47         47       gpio, uart3(cts), uart1(cts), spi(cs7), pcie(clkreq3),
+                       ref(clkout)
+mpp48         48       gpio, tclk, dev(burst/last)
+
+* Marvell Armada XP (mv78260 and mv78460 only)
+
+name          pins     functions
+================================================================================
+mpp49         49       gpio, dev(we3)
+mpp50         50       gpio, dev(we2)
+mpp51         51       gpio, dev(ad16)
+mpp52         52       gpio, dev(ad17)
+mpp53         53       gpio, dev(ad18)
+mpp54         54       gpio, dev(ad19)
+mpp55         55       gpio, dev(ad20), vdd(cpu0-pd)
+mpp56         56       gpio, dev(ad21), vdd(cpu1-pd)
+mpp57         57       gpio, dev(ad22), vdd(cpu2-3-pd){1}
+mpp58         58       gpio, dev(ad23)
+mpp59         59       gpio, dev(ad24)
+mpp60         60       gpio, dev(ad25)
+mpp61         61       gpio, dev(ad26)
+mpp62         62       gpio, dev(ad27)
+mpp63         63       gpio, dev(ad28)
+mpp64         64       gpio, dev(ad29)
+mpp65         65       gpio, dev(ad30)
+mpp66         66       gpio, dev(ad31)
+
+Notes:
+* {1} vdd(cpu2-3-pd) only available on mv78460.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
new file mode 100644
index 000000000000..a648aaad6110
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,dove-pinctrl.txt
@@ -0,0 +1,72 @@
+* Marvell Dove SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,dove-pinctrl"
+- clocks: (optional) phandle of pdma clock
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, pmu, uart2(rts), sdio0(cd), lcd0(pwm)
+mpp1          1        gpio, pmu, uart2(cts), sdio0(wp), lcd1(pwm)
+mpp2          2        gpio, pmu, uart2(txd), sdio0(buspwr), sata(prsnt),
+                       uart1(rts)
+mpp3          3        gpio, pmu, uart2(rxd), sdio0(ledctrl), sata(act),
+                       uart1(cts), lcd-spi(cs1)
+mpp4          4        gpio, pmu, uart3(rts), sdio1(cd), spi1(miso)
+mpp5          5        gpio, pmu, uart3(cts), sdio1(wp), spi1(cs)
+mpp6          6        gpio, pmu, uart3(txd), sdio1(buspwr), spi1(mosi)
+mpp7          7        gpio, pmu, uart3(rxd), sdio1(ledctrl), spi1(sck)
+mpp8          8        gpio, pmu, watchdog(rstout)
+mpp9          9        gpio, pmu, pex1(clkreq)
+mpp10         10       gpio, pmu, ssp(sclk)
+mpp11         11       gpio, pmu, sata(prsnt), sata-1(act), sdio0(ledctrl),
+                       sdio1(ledctrl), pex0(clkreq)
+mpp12         12       gpio, pmu, uart2(rts), audio0(extclk), sdio1(cd), sata(act)
+mpp13         13       gpio, pmu, uart2(cts), audio1(extclk), sdio1(wp),
+                       ssp(extclk)
+mpp14         14       gpio, pmu, uart2(txd), sdio1(buspwr), ssp(rxd)
+mpp15         15       gpio, pmu, uart2(rxd), sdio1(ledctrl), ssp(sfrm)
+mpp16         16       gpio, uart3(rts), sdio0(cd), ac97(sdi1), lcd-spi(cs1)
+mpp17         17       gpio, uart3(cts), sdio0(wp), ac97(sdi2), twsi(sda),
+                       ac97-1(sysclko)
+mpp18         18       gpio, uart3(txd), sdio0(buspwr), ac97(sdi3), lcd0(pwm)
+mpp19         19       gpio, uart3(rxd), sdio0(ledctrl), twsi(sck)
+mpp20         20       gpio, sdio0(cd), sdio1(cd), spi1(miso), lcd-spi(miso),
+                       ac97(sysclko)
+mpp21         21       gpio, sdio0(wp), sdio1(wp), spi1(cs), lcd-spi(cs0),
+                       uart1(cts), ssp(sfrm)
+mpp22         22       gpio, sdio0(buspwr), sdio1(buspwr), spi1(mosi),
+                       lcd-spi(mosi), uart1(cts), ssp(txd)
+mpp23         23       gpio, sdio0(ledctrl), sdio1(ledctrl), spi1(sck),
+                       lcd-spi(sck), ssp(sclk)
+mpp_camera    24-39    gpio, camera
+mpp_sdio0     40-45    gpio, sdio0
+mpp_sdio1     46-51    gpio, sdio1
+mpp_audio1    52-57    gpio, i2s1/spdifo, i2s1, spdifo, twsi, ssp/spdifo, ssp,
+                       ssp/twsi
+mpp_spi0      58-61    gpio, spi0
+mpp_uart1     62-63    gpio, uart1
+mpp_nand      64-71    gpo, nand
+audio0        -        i2s, ac97
+twsi          -        none, opt1, opt2, opt3
+
+Notes:
+* group "mpp_audio1" allows the following functions and gpio pins:
+  - gpio          : gpio on pins 52-57
+  - i2s1/spdifo   : audio1 i2s on pins 52-55 and spdifo on 57, no gpios
+  - i2s1          : audio1 i2s on pins 52-55, gpio on pins 56,57
+  - spdifo        : spdifo on pin 57, gpio on pins 52-55
+  - twsi          : twsi on pins 56,57, gpio on pins 52-55
+  - ssp/spdifo    : ssp on pins 52-55, spdifo on pin 57, no gpios
+  - ssp           : ssp on pins 52-55, gpio on pins 56,57
+  - ssp/twsi      : ssp on pins 52-55, twsi on pins 56,57, no gpios
+* group "audio0" internally muxes i2s0 or ac97 controller to the dedicated
+  audio0 pins.
+* group "twsi" internally muxes twsi controller to the dedicated or option pins.
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
new file mode 100644
index 000000000000..361bccb7ec89
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,kirkwood-pinctrl.txt
@@ -0,0 +1,279 @@
+* Marvell Kirkwood SoC pinctrl driver for mpp
+
+Please refer to marvell,mvebu-pinctrl.txt in this directory for common binding
+part and usage.
+
+Required properties:
+- compatible: "marvell,88f6180-pinctrl",
+              "marvell,88f6190-pinctrl", "marvell,88f6192-pinctrl",
+              "marvell,88f6281-pinctrl", "marvell,88f6282-pinctrl"
+
+This driver supports all kirkwood variants, i.e. 88f6180, 88f619x, and 88f628x.
+
+Available mpp pins/groups and functions:
+Note: brackets (x) are not part of the mpp name for marvell,function and given
+only for more detailed description in this document.
+
+* Marvell Kirkwood 88f6180
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, mii(rxerr)
+mpp21         21       gpio, audio(spdifi)
+mpp22         22       gpio, audio(spdifo)
+mpp23         23       gpio, audio(rmclk)
+mpp24         24       gpio, audio(bclk)
+mpp25         25       gpio, audio(sdo)
+mpp26         26       gpio, audio(lrclk)
+mpp27         27       gpio, audio(mclk)
+mpp28         28       gpio, audio(sdi)
+mpp29         29       gpio, audio(extclk)
+
+* Marvell Kirkwood 88f6190
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0)
+mpp21         21       gpio, ge1(txd1), sata0(act)
+mpp22         22       gpio, ge1(txd2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt)
+mpp24         24       gpio, ge1(rxd0)
+mpp25         25       gpio, ge1(rxd1)
+mpp26         26       gpio, ge1(rxd2)
+mpp27         27       gpio, ge1(rxd3)
+mpp28         28       gpio, ge1(col)
+mpp29         29       gpio, ge1(txclk)
+mpp30         30       gpio, ge1(rxclk)
+mpp31         31       gpio, ge1(rxclk)
+mpp32         32       gpio, ge1(txclko)
+mpp33         33       gpo, ge1(txclk)
+mpp34         34       gpio, ge1(txen)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr)
+
+* Marvell Kirkwood 88f6192
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpo, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+
+* Marvell Kirkwood 88f6281
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), ptp(clk), sata1(act)
+mpp5          5        gpo, nand(io7), uart0(txd), ptp(trig), sata0(act)
+mpp6          6        sysrst(out), spi(mosi), ptp(trig)
+mpp7          7        gpo, pex(rsto), spi(cs), ptp(trig)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), ptp(clk),
+                       mii(col), mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), ptp(evreq),
+                       mii(crs), sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), ptp(trig), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), ptp(clk), ptp-1(evreq),
+                       ptp-2(trig), sata0(act)
+mpp12         12       gpio, sdio(clk)
+mpp13         13       gpio, sdio(cmd), uart1(txd)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act)
+mpp17         17       gpio, sdio(d3), sata0(prsnt)
+mpp18         18       gpo, nand(io0)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx)
+mpp33         33       gpo, ge1(txclk), tdm(drx)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk)
+mpp45         45       gpio, ts(mp9), tdm(pclk)
+mpp46         46       gpio, ts(mp10), tdm(fs)
+mpp47         47       gpio, ts(mp11), tdm(drx)
+mpp48         48       gpio, ts(mp12), tdm(dtx)
+mpp49         49       gpio, ts(mp9), tdm(rx0ql), ptp(clk)
+
+* Marvell Kirkwood 88f6282
+
+name          pins     functions
+================================================================================
+mpp0          0        gpio, nand(io2), spi(cs)
+mpp1          1        gpo, nand(io3), spi(mosi)
+mpp2          2        gpo, nand(io4), spi(sck)
+mpp3          3        gpo, nand(io5), spi(miso)
+mpp4          4        gpio, nand(io6), uart0(rxd), sata1(act), lcd(hsync)
+mpp5          5        gpo, nand(io7), uart0(txd), sata0(act), lcd(vsync)
+mpp6          6        sysrst(out), spi(mosi)
+mpp7          7        gpo, spi(cs), lcd(pwm)
+mpp8          8        gpio, twsi0(sda), uart0(rts), uart1(rts), mii(col),
+                       mii-1(rxerr), sata1(prsnt)
+mpp9          9        gpio, twsi(sck), uart0(cts), uart1(cts), mii(crs),
+                       sata0(prsnt)
+mpp10         10       gpo, spi(sck), uart0(txd), sata1(act)
+mpp11         11       gpio, spi(miso), uart0(rxd), sata0(act)
+mpp12         12       gpo, sdio(clk), audio(spdifo), spi(mosi), twsi(sda)
+mpp13         13       gpio, sdio(cmd), uart1(txd), audio(rmclk), lcd(pwm)
+mpp14         14       gpio, sdio(d0), uart1(rxd), mii(col), sata1(prsnt),
+                       audio(spdifi), audio-1(sdi)
+mpp15         15       gpio, sdio(d1), uart0(rts), uart1(txd), sata0(act),
+                       spi(cs)
+mpp16         16       gpio, sdio(d2), uart0(cts), uart1(rxd), mii(crs),
+                       sata1(act), lcd(extclk)
+mpp17         17       gpio, sdio(d3), sata0(prsnt), sata1(act), twsi1(sck)
+mpp18         18       gpo, nand(io0), pex(clkreq)
+mpp19         19       gpo, nand(io1)
+mpp20         20       gpio, ge1(txd0), ts(mp0), tdm(tx0ql), audio(spdifi),
+                       sata1(act), lcd(d0)
+mpp21         21       gpio, ge1(txd1), sata0(act), ts(mp1), tdm(rx0ql),
+                       audio(spdifo), lcd(d1)
+mpp22         22       gpio, ge1(txd2), ts(mp2), tdm(tx2ql), audio(rmclk),
+                       sata1(prsnt), lcd(d2)
+mpp23         23       gpio, ge1(txd3), sata0(prsnt), ts(mp3), tdm(rx2ql),
+                       audio(bclk), lcd(d3)
+mpp24         24       gpio, ge1(rxd0), ts(mp4), tdm(spi-cs0), audio(sdo),
+                       lcd(d4)
+mpp25         25       gpio, ge1(rxd1), ts(mp5), tdm(spi-sck), audio(lrclk),
+                       lcd(d5)
+mpp26         26       gpio, ge1(rxd2), ts(mp6), tdm(spi-miso), audio(mclk),
+                       lcd(d6)
+mpp27         27       gpio, ge1(rxd3), ts(mp7), tdm(spi-mosi), audio(sdi),
+                       lcd(d7)
+mpp28         28       gpio, ge1(col), ts(mp8), tdm(int), audio(extclk),
+                       lcd(d8)
+mpp29         29       gpio, ge1(txclk), ts(mp9), tdm(rst), lcd(d9)
+mpp30         30       gpio, ge1(rxclk), ts(mp10), tdm(pclk), lcd(d10)
+mpp31         31       gpio, ge1(rxclk), ts(mp11), tdm(fs), lcd(d11)
+mpp32         32       gpio, ge1(txclko), ts(mp12), tdm(drx), lcd(d12)
+mpp33         33       gpo, ge1(txclk), tdm(drx), lcd(d13)
+mpp34         34       gpio, ge1(txen), tdm(spi-cs1), sata1(act), lcd(d14)
+mpp35         35       gpio, ge1(rxerr), sata0(act), mii(rxerr), tdm(tx0ql),
+                       lcd(d15)
+mpp36         36       gpio, ts(mp0), tdm(spi-cs1), audio(spdifi), twsi1(sda)
+mpp37         37       gpio, ts(mp1), tdm(tx2ql), audio(spdifo), twsi1(sck)
+mpp38         38       gpio, ts(mp2), tdm(rx2ql), audio(rmclk), lcd(d18)
+mpp39         39       gpio, ts(mp3), tdm(spi-cs0), audio(bclk), lcd(d19)
+mpp40         40       gpio, ts(mp4), tdm(spi-sck), audio(sdo), lcd(d20)
+mpp41         41       gpio, ts(mp5), tdm(spi-miso), audio(lrclk), lcd(d21)
+mpp42         42       gpio, ts(mp6), tdm(spi-mosi), audio(mclk), lcd(d22)
+mpp43         43       gpio, ts(mp7), tdm(int), audio(sdi), lcd(d23)
+mpp44         44       gpio, ts(mp8), tdm(rst), audio(extclk), lcd(clk)
+mpp45         45       gpio, ts(mp9), tdm(pclk), lcd(e)
+mpp46         46       gpio, ts(mp10), tdm(fs), lcd(hsync)
+mpp47         47       gpio, ts(mp11), tdm(drx), lcd(vsync)
+mpp48         48       gpio, ts(mp12), tdm(dtx), lcd(d16)
+mpp49         49       gpo, tdm(rx0ql), pex(clkreq), lcd(d17)
diff --git a/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
new file mode 100644
index 000000000000..0a26c3aa4e6d
--- /dev/null
+++ b/Documentation/devicetree/bindings/pinctrl/marvell,mvebu-pinctrl.txt
@@ -0,0 +1,46 @@
+* Marvell SoC pinctrl core driver for mpp
+
+The pinctrl driver enables Marvell SoCs to configure the multi-purpose pins
+(mpp) to a specific function. For each SoC family there is a SoC specific
+driver using this core driver.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+A Marvell SoC pin configuration node is a node of a group of pins which can
+be used for a specific device or function. Each node requires one or more
+mpp pins or group of pins and a mpp function common to all pins.
+
+Required properties for pinctrl driver:
+- compatible: "marvell,<soc>-pinctrl"
+  Please refer to each marvell,<soc>-pinctrl.txt binding doc for supported SoCs.
+
+Required properties for pin configuration node:
+- marvell,pins: string array of mpp pins or group of pins to be muxed.
+- marvell,function: string representing a function to mux to for all
+    marvell,pins given in this pin configuration node. The function has to be
+    common for all marvell,pins. Please refer to marvell,<soc>-pinctrl.txt for
+    valid pin/pin group names and available function names for each SoC.
+
+Examples:
+
+uart1: serial@12100 {
+        compatible = "ns16550a";
+        reg = <0x12100 0x100>;
+        reg-shift = <2>;
+        interrupts = <7>;
+
+        pinctrl-0 = <&pmx_uart1_sw>;
+        pinctrl-names = "default";
+};
+
+pinctrl: pinctrl@d0200 {
+        compatible = "marvell,dove-pinctrl";
+        reg = <0xd0200 0x20>;
+
+        pmx_uart1_sw: pmx-uart1-sw {
+                marvell,pins = "mpp_uart1";
+                marvell,function = "uart1";
+        };
+};
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 3975d10cb3ed..8ac460a8f4ca 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -529,10 +529,11 @@ config ARCH_IXP4XX
 config ARCH_DOVE
         bool "Marvell Dove"
         select CPU_V7
-        select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select PLAT_ORION
+        select MIGHT_HAVE_PCI
+        select PLAT_ORION_LEGACY
+        select USB_ARCH_HAS_EHCI
         help
           Support for the Marvell Dove SoC 88AP510
 
@@ -542,7 +543,7 @@ config ARCH_KIRKWOOD
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
         help
           Support for the following Marvell Kirkwood series SoCs:
           88F6180, 88F6192 and 88F6281.
@@ -568,7 +569,7 @@ config ARCH_MV78XX0
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
         help
           Support for the following Marvell MV78xx0 series SoCs:
           MV781x0, MV782x0.
@@ -580,7 +581,7 @@ config ARCH_ORION5X
         select PCI
         select ARCH_REQUIRE_GPIOLIB
         select GENERIC_CLOCKEVENTS
-        select PLAT_ORION
+        select PLAT_ORION_LEGACY
         help
           Support for the following Marvell Orion 5x series SoCs:
           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
@@ -1138,6 +1139,10 @@ config PLAT_ORION
         select IRQ_DOMAIN
         select COMMON_CLK
 
+config PLAT_ORION_LEGACY
+        bool
+        select PLAT_ORION
+
 config PLAT_PXA
         bool
 
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 4745c1f68b49..29f541f0e653 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -17,6 +17,9 @@ dtb-$(CONFIG_ARCH_AT91) += aks-cdu.dtb \
         usb_a9263.dtb \
         usb_a9g20.dtb
 dtb-$(CONFIG_ARCH_BCM2835) += bcm2835-rpi-b.dtb
+dtb-$(CONFIG_ARCH_DOVE) += dove-cm-a510.dtb \
+        dove-cubox.dtb \
+        dove-dove-db.dtb
 dtb-$(CONFIG_ARCH_EXYNOS) += exynos4210-origen.dtb \
         exynos4210-smdkv310.dtb \
         exynos4210-trats.dtb \
@@ -33,10 +36,13 @@ dtb-$(CONFIG_SOC_IMX6Q) += imx6q-arm2.dtb \
 dtb-$(CONFIG_ARCH_LPC32XX) += ea3250.dtb phy3250.dtb
 dtb-$(CONFIG_ARCH_KIRKWOOD) += kirkwood-dns320.dtb \
         kirkwood-dns325.dtb \
+        kirkwood-dockstar.dtb \
         kirkwood-dreamplug.dtb \
         kirkwood-goflexnet.dtb \
         kirkwood-ib62x0.dtb \
         kirkwood-iconnect.dtb \
+        kirkwood-iomega_ix2_200.dtb \
+        kirkwood-km_kirkwood.dtb \
         kirkwood-lschlv2.dtb \
         kirkwood-lsxhl.dtb \
         kirkwood-ts219-6281.dtb \
diff --git a/arch/arm/boot/dts/armada-370-xp.dtsi b/arch/arm/boot/dts/armada-370-xp.dtsi
index 6b6b932a5a7d..16cc82cdaa81 100644
--- a/arch/arm/boot/dts/armada-370-xp.dtsi
+++ b/arch/arm/boot/dts/armada-370-xp.dtsi
@@ -63,6 +63,11 @@
                                reg = <0xd0020300 0x30>;
                                interrupts = <37>, <38>, <39>, <40>;
                 };
+
+                addr-decoding@d0020000 {
+                        compatible = "marvell,armada-addr-decoding-controller";
+                        reg = <0xd0020000 0x258>;
+                };
         };
 };
 
diff --git a/arch/arm/boot/dts/armada-370.dtsi b/arch/arm/boot/dts/armada-370.dtsi
index 3228ccc83332..2069151afe01 100644
--- a/arch/arm/boot/dts/armada-370.dtsi
+++ b/arch/arm/boot/dts/armada-370.dtsi
@@ -21,6 +21,12 @@
         model = "Marvell Armada 370 family SoC";
         compatible = "marvell,armada370", "marvell,armada-370-xp";
 
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+
         mpic: interrupt-controller@d0020000 {
               reg = <0xd0020a00 0x1d0>,
                     <0xd0021870 0x58>;
@@ -31,5 +37,43 @@
                                 compatible = "marvell,armada-370-xp-system-controller";
                                 reg = <0xd0018200 0x100>;
                 };
+
+                pinctrl {
+                        compatible = "marvell,mv88f6710-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018100 0x40>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <82>, <83>, <84>, <85>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018140 0x40>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <87>, <88>, <89>, <90>;
+                };
+
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,orion-gpio";
+                        reg = <0xd0018180 0x40>;
+                        ngpios = <2>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <91>;
+                };
         };
 };
diff --git a/arch/arm/boot/dts/armada-xp-db.dts b/arch/arm/boot/dts/armada-xp-db.dts
index f97040d4258d..b1fc728515e9 100644
--- a/arch/arm/boot/dts/armada-xp-db.dts
+++ b/arch/arm/boot/dts/armada-xp-db.dts
@@ -14,11 +14,11 @@
  */
 
 /dts-v1/;
-/include/ "armada-xp.dtsi"
+/include/ "armada-xp-mv78460.dtsi"
 
 / {
         model = "Marvell Armada XP Evaluation Board";
-        compatible = "marvell,axp-db", "marvell,armadaxp", "marvell,armada-370-xp";
+        compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
 
         chosen {
                 bootargs = "console=ttyS0,115200 earlyprintk";
diff --git a/arch/arm/boot/dts/armada-xp-mv78230.dtsi b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
new file mode 100644
index 000000000000..ea355192be6f
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78230.dtsi
@@ -0,0 +1,57 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78230 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP MV78230 SoC";
+        compatible = "marvell,armadaxp-mv78230", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+        };
+
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78230-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <17>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78260.dtsi b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
new file mode 100644
index 000000000000..2057863f3dfa
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78260.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78260 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP MV78260 SoC";
+        compatible = "marvell,armadaxp-mv78260", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78260-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>, <23>;
+                };
+
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018180 0x40>,
+                            <0xd0018870 0x30>;
+                        ngpios = <3>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <24>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/armada-xp-mv78460.dtsi b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
new file mode 100644
index 000000000000..ffac98373792
--- /dev/null
+++ b/arch/arm/boot/dts/armada-xp-mv78460.dtsi
@@ -0,0 +1,70 @@
+/*
+ * Device Tree Include file for Marvell Armada XP family SoC
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Contains definitions specific to the Armada XP MV78460 SoC that are not
+ * common to all Armada XP SoCs.
+ */
+
+/include/ "armada-xp.dtsi"
+
+/ {
+        model = "Marvell Armada XP MV78460 SoC";
+        compatible = "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp";
+
+        aliases {
+                gpio0 = &gpio0;
+                gpio1 = &gpio1;
+                gpio2 = &gpio2;
+        };
+
+        soc {
+                pinctrl {
+                        compatible = "marvell,mv78460-pinctrl";
+                        reg = <0xd0018000 0x38>;
+                };
+
+                gpio0: gpio@d0018100 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018100 0x40>,
+                            <0xd0018800 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <16>, <17>, <18>, <19>;
+                };
+
+                gpio1: gpio@d0018140 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018140 0x40>,
+                            <0xd0018840 0x30>;
+                        ngpios = <32>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <20>, <21>, <22>, <23>;
+                };
+
+                gpio2: gpio@d0018180 {
+                        compatible = "marvell,armadaxp-gpio";
+                        reg = <0xd0018180 0x40>,
+                            <0xd0018870 0x30>;
+                        ngpios = <3>;
+                        gpio-controller;
+                        #gpio-cells = <2>;
+                        interrupt-controller;
+                        #interrupts-cells = <2>;
+                        interrupts = <24>;
+                };
+        };
+ };
diff --git a/arch/arm/boot/dts/dove-cm-a510.dts b/arch/arm/boot/dts/dove-cm-a510.dts
new file mode 100644
index 000000000000..61a8062e56de
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cm-a510.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+        model = "Compulab CM-A510";
+        compatible = "compulab,cm-a510", "marvell,dove";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+        status = "okay";
+
+        /* spi0.0: 4M Flash Winbond W25Q32BV */
+        spi-flash@0 {
+                compatible = "st,w25q32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+          status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove-cubox.dts b/arch/arm/boot/dts/dove-cubox.dts
new file mode 100644
index 000000000000..0adbd5a38095
--- /dev/null
+++ b/arch/arm/boot/dts/dove-cubox.dts
@@ -0,0 +1,42 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+        model = "SolidRun CuBox";
+        compatible = "solidrun,cubox", "marvell,dove";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        leds {
+                compatible = "gpio-leds";
+                power {
+                        label = "Power";
+                        gpios = <&gpio0 18 1>;
+                        linux,default-trigger = "default-on";
+                };
+        };
+};
+
+&uart0 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sata0 { status = "okay"; };
+&i2c0 { status = "okay"; };
+
+&spi0 {
+        status = "okay";
+
+        /* spi0.0: 4M Flash Winbond W25Q32BV */
+        spi-flash@0 {
+                compatible = "st,w25q32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
diff --git a/arch/arm/boot/dts/dove-dove-db.dts b/arch/arm/boot/dts/dove-dove-db.dts
new file mode 100644
index 000000000000..e5a920beab45
--- /dev/null
+++ b/arch/arm/boot/dts/dove-dove-db.dts
@@ -0,0 +1,38 @@
+/dts-v1/;
+
+/include/ "dove.dtsi"
+
+/ {
+        model = "Marvell DB-MV88AP510-BP Development Board";
+        compatible = "marvell,dove-db", "marvell,dove";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x40000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+};
+
+&uart0 { status = "okay"; };
+&uart1 { status = "okay"; };
+&sdio0 { status = "okay"; };
+&sdio1 { status = "okay"; };
+&sata0 { status = "okay"; };
+
+&spi0 {
+        status = "okay";
+
+        /* spi0.0: 4M Flash ST-M25P32-VMF6P */
+        spi-flash@0 {
+                compatible = "st,m25p32";
+                spi-max-frequency = <20000000>;
+                reg = <0>;
+        };
+};
+
+&i2c0 {
+          status = "okay";
+};
diff --git a/arch/arm/boot/dts/dove.dtsi b/arch/arm/boot/dts/dove.dtsi
new file mode 100644
index 000000000000..96fb824b5e6e
--- /dev/null
+++ b/arch/arm/boot/dts/dove.dtsi
@@ -0,0 +1,143 @@
+/include/ "skeleton.dtsi"
+
+/ {
+        compatible = "marvell,dove";
+        model = "Marvell Armada 88AP510 SoC";
+
+        interrupt-parent = <&intc>;
+
+        intc: interrupt-controller {
+                compatible = "marvell,orion-intc";
+                interrupt-controller;
+                #interrupt-cells = <1>;
+                reg = <0xf1020204 0x04>,
+                      <0xf1020214 0x04>;
+        };
+
+        mbus@f1000000 {
+                compatible = "simple-bus";
+                ranges = <0 0xf1000000 0x4000000>;
+                #address-cells = <1>;
+                #size-cells = <1>;
+
+                uart0: serial@12000 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <7>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                uart1: serial@12100 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <8>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                uart2: serial@12200 {
+                        compatible = "ns16550a";
+                        reg = <0x12000 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <9>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                uart3: serial@12300 {
+                        compatible = "ns16550a";
+                        reg = <0x12100 0x100>;
+                        reg-shift = <2>;
+                        interrupts = <10>;
+                        clock-frequency = <166666667>;
+                        status = "disabled";
+                };
+
+                wdt: wdt@20300 {
+                        compatible = "marvell,orion-wdt";
+                        reg = <0x20300 0x28>;
+                };
+
+                gpio0: gpio@d0400 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xd0400 0x20>;
+                        ngpio = <32>;
+                        interrupts = <12>, <13>, <14>, <60>;
+                };
+
+                gpio1: gpio@d0420 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xd0420 0x20>;
+                        ngpio = <32>;
+                        interrupts = <61>;
+                };
+
+                gpio2: gpio@e8400 {
+                        compatible = "marvell,orion-gpio";
+                        #gpio-cells = <2>;
+                        gpio-controller;
+                        reg = <0xe8400 0x0c>;
+                        ngpio = <8>;
+                };
+
+                spi0: spi@10600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <0>;
+                        interrupts = <6>;
+                        reg = <0x10600 0x28>;
+                        status = "disabled";
+                };
+
+                spi1: spi@14600 {
+                        compatible = "marvell,orion-spi";
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        cell-index = <1>;
+                        interrupts = <5>;
+                        reg = <0x14600 0x28>;
+                        status = "disabled";
+                };
+
+                i2c0: i2c@11000 {
+                        compatible = "marvell,mv64xxx-i2c";
+                        reg = <0x11000 0x20>;
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+                        interrupts = <11>;
+                        clock-frequency = <400000>;
+                        timeout-ms = <1000>;
+                        status = "disabled";
+                };
+
+                sdio0: sdio@92000 {
+                        compatible = "marvell,dove-sdhci";
+                        reg = <0x92000 0x100>;
+                        interrupts = <35>, <37>;
+                        status = "disabled";
+                };
+
+                sdio1: sdio@90000 {
+                        compatible = "marvell,dove-sdhci";
+                        reg = <0x90000 0x100>;
+                        interrupts = <36>, <38>;
+                        status = "disabled";
+                };
+
+                sata0: sata@a0000 {
+                        compatible = "marvell,orion-sata";
+                        reg = <0xa0000 0x2400>;
+                        interrupts = <62>;
+                        nr-ports = <1>;
+                        status = "disabled";
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-dnskw.dtsi b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
index 7408655f91b5..9b32d0272825 100644
--- a/arch/arm/boot/dts/kirkwood-dnskw.dtsi
+++ b/arch/arm/boot/dts/kirkwood-dnskw.dtsi
@@ -25,6 +25,16 @@
                 };
         };
 
+        gpio_fan {
+                /* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
+                compatible = "gpio-fan";
+                gpios = <&gpio1 14 1
+                         &gpio1 13 1>;
+                gpio-fan,speed-map = <0    0
+                                      3000 1
+                                      6000 2>;
+        };
+
         ocp@f1000000 {
                 sata@80000 {
                         status = "okay";
diff --git a/arch/arm/boot/dts/kirkwood-dockstar.dts b/arch/arm/boot/dts/kirkwood-dockstar.dts
new file mode 100644
index 000000000000..08a582414b88
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-dockstar.dts
@@ -0,0 +1,57 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Seagate FreeAgent Dockstar";
+        compatible = "seagate,dockstar", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x8000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk root=/dev/sda1 rootdelay=10";
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x0100000 0x400000>;
+                        };
+
+                        partition@500000 {
+                                label = "data";
+                                reg = <0x0500000 0xfb00000>;
+                        };
+                };
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                health {
+                        label = "status:green:health";
+                        gpios = <&gpio1 14 1>;
+                        linux,default-trigger = "default-on";
+                };
+                fault {
+                        label = "status:orange:fault";
+                        gpios = <&gpio1 15 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-iconnect.dts b/arch/arm/boot/dts/kirkwood-iconnect.dts
index f8ca6fa88192..d97cd9d4753e 100644
--- a/arch/arm/boot/dts/kirkwood-iconnect.dts
+++ b/arch/arm/boot/dts/kirkwood-iconnect.dts
@@ -12,7 +12,7 @@
         };
 
         chosen {
-                bootargs = "console=ttyS0,115200n8 earlyprintk mtdparts=orion_nand:0xc0000@0x0(uboot),0x20000@0xa0000(env),0x300000@0x100000(zImage),0x300000@0x540000(initrd),0x1f400000@0x980000(boot)";
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
                 linux,initrd-start = <0x4500040>;
                 linux,initrd-end   = <0x4800000>;
         };
@@ -30,7 +30,37 @@
                         clock-frequency = <200000000>;
                         status = "ok";
                 };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "uboot";
+                                reg = <0x0000000 0xc0000>;
+                        };
+
+                        partition@a0000 {
+                                label = "env";
+                                reg = <0xa0000 0x20000>;
+                        };
+
+                        partition@100000 {
+                                label = "zImage";
+                                reg = <0x100000 0x300000>;
+                        };
+
+                        partition@540000 {
+                                label = "initrd";
+                                reg = <0x540000 0x300000>;
+                        };
+
+                        partition@980000 {
+                                label = "boot";
+                                reg = <0x980000 0x1f400000>;
+                        };
+                };
         };
+
         gpio-leds {
                 compatible = "gpio-leds";
 
@@ -69,4 +99,22 @@
                         gpios = <&gpio1 16 0>;
                 };
         };
+
+        gpio_keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                button@1 {
+                        label = "OTB Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 3 1>;
+                        debounce-interval = <100>;
+                };
+                button@2 {
+                        label = "Reset";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 12 1>;
+                        debounce-interval = <100>;
+                };
+        };
 };
diff --git a/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
new file mode 100644
index 000000000000..865aeec40a26
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-iomega_ix2_200.dts
@@ -0,0 +1,105 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Iomega StorCenter ix2-200";
+        compatible = "iom,ix2-200", "marvell,kirkwood-88f6281", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x10000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                i2c@11000 {
+                        status = "okay";
+
+                        lm63: lm63@4c {
+                                compatible = "national,lm63";
+                                reg = <0x4c>;
+                        };
+                };
+
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "okay";
+
+                        partition@0 {
+                                label = "u-boot";
+                                reg = <0x0000000 0x100000>;
+                                read-only;
+                        };
+
+                        partition@a0000 {
+                                label = "env";
+                                reg = <0xa0000 0x20000>;
+                                read-only;
+                        };
+
+                        partition@100000 {
+                                label = "uImage";
+                                reg = <0x100000 0x300000>;
+                        };
+
+                        partition@400000 {
+                                label = "uInitrd";
+                                reg = <0x540000 0x1000000>;
+                        };
+                };
+                sata@80000 {
+                        status = "okay";
+                        nr-ports = <2>;
+                };
+
+        };
+        gpio-leds {
+                compatible = "gpio-leds";
+
+                power_led {
+                        label = "status:white:power_led";
+                        gpios = <&gpio0 16 0>;
+                        linux,default-trigger = "default-on";
+                };
+                health_led1 {
+                        label = "status:red:health_led";
+                        gpios = <&gpio1 5 0>;
+                };
+                health_led2 {
+                        label = "status:white:health_led";
+                        gpios = <&gpio1 4 0>;
+                };
+                backup_led {
+                        label = "status:blue:backup_led";
+                        gpios = <&gpio0 15 0>;
+                };
+        };
+        gpio-keys {
+                compatible = "gpio-keys";
+                #address-cells = <1>;
+                #size-cells = <0>;
+                Power {
+                        label = "Power Button";
+                        linux,code = <116>;
+                        gpios = <&gpio0 14 1>;
+                };
+                Reset {
+                        label = "Reset Button";
+                        linux,code = <0x198>;
+                        gpios = <&gpio0 12 1>;
+                };
+                OTB {
+                        label = "OTB Button";
+                        linux,code = <133>;
+                        gpios = <&gpio1 3 1>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood-km_kirkwood.dts b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
new file mode 100644
index 000000000000..75bdb93fed26
--- /dev/null
+++ b/arch/arm/boot/dts/kirkwood-km_kirkwood.dts
@@ -0,0 +1,29 @@
+/dts-v1/;
+
+/include/ "kirkwood.dtsi"
+
+/ {
+        model = "Keymile Kirkwood Reference Design";
+        compatible = "keymile,km_kirkwood", "marvell,kirkwood-98DX4122", "marvell,kirkwood";
+
+        memory {
+                device_type = "memory";
+                reg = <0x00000000 0x08000000>;
+        };
+
+        chosen {
+                bootargs = "console=ttyS0,115200n8 earlyprintk";
+        };
+
+        ocp@f1000000 {
+                serial@12000 {
+                        clock-frequency = <200000000>;
+                        status = "ok";
+                };
+
+                nand@3000000 {
+                        status = "ok";
+                        chip-delay = <25>;
+                };
+        };
+};
diff --git a/arch/arm/boot/dts/kirkwood.dtsi b/arch/arm/boot/dts/kirkwood.dtsi
index cef9616f330a..4e5b8154a5be 100644
--- a/arch/arm/boot/dts/kirkwood.dtsi
+++ b/arch/arm/boot/dts/kirkwood.dtsi
@@ -14,7 +14,8 @@
 
         ocp@f1000000 {
                 compatible = "simple-bus";
-                ranges = <0 0xf1000000 0x4000000>;
+                ranges = <0x00000000 0xf1000000 0x4000000
+                          0xf5000000 0xf5000000 0x0000400>;
                 #address-cells = <1>;
                 #size-cells = <1>;
 
@@ -105,5 +106,14 @@
                         clock-frequency = <100000>;
                         status = "disabled";
                 };
+
+                crypto@30000 {
+                        compatible = "marvell,orion-crypto";
+                        reg = <0x30000 0x10000>,
+                              <0xf5000000 0x800>;
+                        reg-names = "regs", "sram";
+                        interrupts = <22>;
+                        status = "okay";
+                };
         };
 };
diff --git a/arch/arm/configs/kirkwood_defconfig b/arch/arm/configs/kirkwood_defconfig
index aeb3af541fed..74eee0c78f28 100644
--- a/arch/arm/configs/kirkwood_defconfig
+++ b/arch/arm/configs/kirkwood_defconfig
@@ -1,5 +1,7 @@
 CONFIG_EXPERIMENTAL=y
 CONFIG_SYSVIPC=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
 CONFIG_LOG_BUF_SHIFT=19
 CONFIG_PROFILING=y
 CONFIG_OPROFILE=y
@@ -15,9 +17,19 @@ CONFIG_MACH_MV88F6281GTW_GE=y
 CONFIG_MACH_SHEEVAPLUG=y
 CONFIG_MACH_ESATA_SHEEVAPLUG=y
 CONFIG_MACH_GURUPLUG=y
-CONFIG_MACH_DOCKSTAR=y
+CONFIG_MACH_DREAMPLUG_DT=y
+CONFIG_MACH_ICONNECT_DT=y
+CONFIG_MACH_DLINK_KIRKWOOD_DT=y
+CONFIG_MACH_IB62X0_DT=y
+CONFIG_MACH_TS219_DT=y
+CONFIG_MACH_DOCKSTAR_DT=y
+CONFIG_MACH_GOFLEXNET_DT=y
+CONFIG_MACH_LSXL_DT=y
+CONFIG_MACH_IOMEGA_IX2_200_DT=y
+CONFIG_MACH_KM_KIRKWOOD_DT=y
 CONFIG_MACH_TS219=y
 CONFIG_MACH_TS41X=y
+CONFIG_MACH_DOCKSTAR=y
 CONFIG_MACH_OPENRD_BASE=y
 CONFIG_MACH_OPENRD_CLIENT=y
 CONFIG_MACH_OPENRD_ULTIMATE=y
@@ -29,8 +41,6 @@ CONFIG_MACH_NET2BIG_V2=y
 CONFIG_MACH_NET5BIG_V2=y
 CONFIG_MACH_T5325=y
 # CONFIG_CPU_FEROCEON_OLD_ID is not set
-CONFIG_NO_HZ=y
-CONFIG_HIGH_RES_TIMERS=y
 CONFIG_PREEMPT=y
 CONFIG_AEABI=y
 # CONFIG_OABI_COMPAT is not set
@@ -47,13 +57,11 @@ CONFIG_IP_PNP_DHCP=y
 CONFIG_IP_PNP_BOOTP=y
 # CONFIG_IPV6 is not set
 CONFIG_NET_DSA=y
-CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_NET_PKTGEN=m
 CONFIG_CFG80211=y
 CONFIG_MAC80211=y
 CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_MTD=y
-CONFIG_MTD_PARTITIONS=y
 CONFIG_MTD_CMDLINE_PARTS=y
 CONFIG_MTD_CHAR=y
 CONFIG_MTD_BLOCK=y
@@ -69,7 +77,6 @@ CONFIG_MTD_M25P80=y
 CONFIG_MTD_NAND=y
 CONFIG_MTD_NAND_ORION=y
 CONFIG_BLK_DEV_LOOP=y
-# CONFIG_MISC_DEVICES is not set
 # CONFIG_SCSI_PROC_FS is not set
 CONFIG_BLK_DEV_SD=y
 CONFIG_BLK_DEV_SR=m
@@ -78,22 +85,21 @@ CONFIG_ATA=y
 CONFIG_SATA_AHCI=y
 CONFIG_SATA_MV=y
 CONFIG_NETDEVICES=y
-CONFIG_MARVELL_PHY=y
-CONFIG_NET_ETHERNET=y
 CONFIG_MII=y
-CONFIG_NET_PCI=y
+CONFIG_NET_DSA_MV88E6123_61_65=y
 CONFIG_MV643XX_ETH=y
-# CONFIG_NETDEV_10000 is not set
+CONFIG_MARVELL_PHY=y
 CONFIG_LIBERTAS=y
 CONFIG_LIBERTAS_SDIO=y
 CONFIG_INPUT_EVDEV=y
 CONFIG_KEYBOARD_GPIO=y
 # CONFIG_INPUT_MOUSE is not set
+CONFIG_LEGACY_PTY_COUNT=16
 # CONFIG_DEVKMEM is not set
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_8250_RUNTIME_UARTS=2
-CONFIG_LEGACY_PTY_COUNT=16
+CONFIG_SERIAL_OF_PLATFORM=y
 # CONFIG_HW_RANDOM is not set
 CONFIG_I2C=y
 # CONFIG_I2C_COMPAT is not set
@@ -103,7 +109,8 @@ CONFIG_SPI=y
 CONFIG_SPI_ORION=y
 CONFIG_GPIO_SYSFS=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_CONSOLE is not set
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
 CONFIG_HID_DRAGONRISE=y
 CONFIG_HID_GYRATION=y
 CONFIG_HID_TWINHAN=y
@@ -119,10 +126,8 @@ CONFIG_HID_TOPSEED=y
 CONFIG_HID_THRUSTMASTER=y
 CONFIG_HID_ZEROPLUS=y
 CONFIG_USB=y
-CONFIG_USB_DEVICEFS=y
 CONFIG_USB_EHCI_HCD=y
 CONFIG_USB_EHCI_ROOT_HUB_TT=y
-CONFIG_USB_EHCI_TT_NEWSCHED=y
 CONFIG_USB_PRINTER=m
 CONFIG_USB_STORAGE=y
 CONFIG_USB_STORAGE_DATAFAB=y
@@ -148,7 +153,6 @@ CONFIG_MV_XOR=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
-CONFIG_INOTIFY=y
 CONFIG_ISO9660_FS=m
 CONFIG_JOLIET=y
 CONFIG_UDF_FS=m
@@ -158,7 +162,6 @@ CONFIG_TMPFS=y
 CONFIG_JFFS2_FS=y
 CONFIG_CRAMFS=y
 CONFIG_NFS_FS=y
-CONFIG_NFS_V3=y
 CONFIG_ROOT_NFS=y
 CONFIG_NLS_CODEPAGE_437=y
 CONFIG_NLS_CODEPAGE_850=y
@@ -171,11 +174,8 @@ CONFIG_DEBUG_KERNEL=y
 # CONFIG_SCHED_DEBUG is not set
 # CONFIG_DEBUG_PREEMPT is not set
 CONFIG_DEBUG_INFO=y
-# CONFIG_RCU_CPU_STALL_DETECTOR is not set
-CONFIG_SYSCTL_SYSCALL_CHECK=y
 # CONFIG_FTRACE is not set
 CONFIG_DEBUG_USER=y
-CONFIG_DEBUG_ERRORS=y
 CONFIG_DEBUG_LL=y
 CONFIG_CRYPTO_CBC=m
 CONFIG_CRYPTO_PCBC=m
diff --git a/arch/arm/configs/mvebu_defconfig b/arch/arm/configs/mvebu_defconfig
index 2e86b31c33cf..7bcf850eddcd 100644
--- a/arch/arm/configs/mvebu_defconfig
+++ b/arch/arm/configs/mvebu_defconfig
@@ -21,6 +21,8 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 CONFIG_SERIAL_8250=y
 CONFIG_SERIAL_8250_CONSOLE=y
 CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_SYSFS=y
 CONFIG_EXT2_FS=y
 CONFIG_EXT3_FS=y
 # CONFIG_EXT3_FS_XATTR is not set
diff --git a/arch/arm/mach-dove/Kconfig b/arch/arm/mach-dove/Kconfig
index dd937c526a45..00154e74ce6b 100644
--- a/arch/arm/mach-dove/Kconfig
+++ b/arch/arm/mach-dove/Kconfig
@@ -15,6 +15,13 @@ config MACH_CM_A510
           Say 'Y' here if you want your kernel to support the
           CompuLab CM-A510 Board.
 
+config MACH_DOVE_DT
+        bool "Marvell Dove Flattened Device Tree"
+        select USE_OF
+        help
+          Say 'Y' here if you want your kernel to support the
+          Marvell Dove using flattened device tree.
+
 endmenu
 
 endif
diff --git a/arch/arm/mach-dove/Makefile b/arch/arm/mach-dove/Makefile
index fa0f01856060..5e683baf96cf 100644
--- a/arch/arm/mach-dove/Makefile
+++ b/arch/arm/mach-dove/Makefile
@@ -1,4 +1,4 @@
-obj-y                           += common.o addr-map.o irq.o pcie.o mpp.o
-
+obj-y                           += common.o addr-map.o irq.o mpp.o
+obj-$(CONFIG_PCI)               += pcie.o
 obj-$(CONFIG_MACH_DOVE_DB)      += dove-db-setup.o
 obj-$(CONFIG_MACH_CM_A510)      += cm-a510.o
diff --git a/arch/arm/mach-dove/common.c b/arch/arm/mach-dove/common.c
index 950ad9533d19..b37bef1d5ffa 100644
--- a/arch/arm/mach-dove/common.c
+++ b/arch/arm/mach-dove/common.c
@@ -16,6 +16,8 @@
 #include <linux/clk-provider.h>
 #include <linux/ata_platform.h>
 #include <linux/gpio.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
 #include <asm/page.h>
 #include <asm/setup.h>
 #include <asm/timex.h>
@@ -24,6 +26,7 @@
 #include <asm/mach/time.h>
 #include <asm/mach/pci.h>
 #include <mach/dove.h>
+#include <mach/pm.h>
 #include <mach/bridge-regs.h>
 #include <asm/mach/arch.h>
 #include <linux/irq.h>
@@ -33,19 +36,17 @@
 #include <plat/addr-map.h>
 #include "common.h"
 
-static int get_tclk(void);
-
 /*****************************************************************************
  * I/O Address Mapping
  ****************************************************************************/
 static struct map_desc dove_io_desc[] __initdata = {
         {
-                .virtual        = DOVE_SB_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) DOVE_SB_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(DOVE_SB_REGS_PHYS_BASE),
                 .length         = DOVE_SB_REGS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = DOVE_NB_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) DOVE_NB_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(DOVE_NB_REGS_PHYS_BASE),
                 .length         = DOVE_NB_REGS_SIZE,
                 .type           = MT_DEVICE,
@@ -60,14 +61,69 @@ void __init dove_map_io(void)
 /*****************************************************************************
  * CLK tree
  ****************************************************************************/
+static int dove_tclk;
+
+static DEFINE_SPINLOCK(gating_lock);
 static struct clk *tclk;
 
-static void __init clk_init(void)
+static struct clk __init *dove_register_gate(const char *name,
+                                             const char *parent, u8 bit_idx)
 {
-        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
-                                       get_tclk());
+        return clk_register_gate(NULL, name, parent, 0,
+                                 (void __iomem *)CLOCK_GATING_CONTROL,
+                                 bit_idx, 0, &gating_lock);
+}
+
+static void __init dove_clk_init(void)
+{
+        struct clk *usb0, *usb1, *sata, *pex0, *pex1, *sdio0, *sdio1;
+        struct clk *nand, *camera, *i2s0, *i2s1, *crypto, *ac97, *pdma;
+        struct clk *xor0, *xor1, *ge, *gephy;
 
-        orion_clkdev_init(tclk);
+        tclk = clk_register_fixed_rate(NULL, "tclk", NULL, CLK_IS_ROOT,
+                                       dove_tclk);
+
+        usb0 = dove_register_gate("usb0", "tclk", CLOCK_GATING_BIT_USB0);
+        usb1 = dove_register_gate("usb1", "tclk", CLOCK_GATING_BIT_USB1);
+        sata = dove_register_gate("sata", "tclk", CLOCK_GATING_BIT_SATA);
+        pex0 = dove_register_gate("pex0", "tclk", CLOCK_GATING_BIT_PCIE0);
+        pex1 = dove_register_gate("pex1", "tclk", CLOCK_GATING_BIT_PCIE1);
+        sdio0 = dove_register_gate("sdio0", "tclk", CLOCK_GATING_BIT_SDIO0);
+        sdio1 = dove_register_gate("sdio1", "tclk", CLOCK_GATING_BIT_SDIO1);
+        nand = dove_register_gate("nand", "tclk", CLOCK_GATING_BIT_NAND);
+        camera = dove_register_gate("camera", "tclk", CLOCK_GATING_BIT_CAMERA);
+        i2s0 = dove_register_gate("i2s0", "tclk", CLOCK_GATING_BIT_I2S0);
+        i2s1 = dove_register_gate("i2s1", "tclk", CLOCK_GATING_BIT_I2S1);
+        crypto = dove_register_gate("crypto", "tclk", CLOCK_GATING_BIT_CRYPTO);
+        ac97 = dove_register_gate("ac97", "tclk", CLOCK_GATING_BIT_AC97);
+        pdma = dove_register_gate("pdma", "tclk", CLOCK_GATING_BIT_PDMA);
+        xor0 = dove_register_gate("xor0", "tclk", CLOCK_GATING_BIT_XOR0);
+        xor1 = dove_register_gate("xor1", "tclk", CLOCK_GATING_BIT_XOR1);
+        gephy = dove_register_gate("gephy", "tclk", CLOCK_GATING_BIT_GIGA_PHY);
+        ge = dove_register_gate("ge", "gephy", CLOCK_GATING_BIT_GBE);
+
+        orion_clkdev_add(NULL, "orion_spi.0", tclk);
+        orion_clkdev_add(NULL, "orion_spi.1", tclk);
+        orion_clkdev_add(NULL, "orion_wdt", tclk);
+        orion_clkdev_add(NULL, "mv64xxx_i2c.0", tclk);
+
+        orion_clkdev_add(NULL, "orion-ehci.0", usb0);
+        orion_clkdev_add(NULL, "orion-ehci.1", usb1);
+        orion_clkdev_add(NULL, "mv643xx_eth.0", ge);
+        orion_clkdev_add("0", "sata_mv.0", sata);
+        orion_clkdev_add("0", "pcie", pex0);
+        orion_clkdev_add("1", "pcie", pex1);
+        orion_clkdev_add(NULL, "sdhci-dove.0", sdio0);
+        orion_clkdev_add(NULL, "sdhci-dove.1", sdio1);
+        orion_clkdev_add(NULL, "orion_nand", nand);
+        orion_clkdev_add(NULL, "cafe1000-ccic.0", camera);
+        orion_clkdev_add(NULL, "kirkwood-i2s.0", i2s0);
+        orion_clkdev_add(NULL, "kirkwood-i2s.1", i2s1);
+        orion_clkdev_add(NULL, "mv_crypto", crypto);
+        orion_clkdev_add(NULL, "dove-ac97", ac97);
+        orion_clkdev_add(NULL, "dove-pdma", pdma);
+        orion_clkdev_add(NULL, "mv_xor_shared.0", xor0);
+        orion_clkdev_add(NULL, "mv_xor_shared.1", xor1);
 }
 
 /*****************************************************************************
@@ -178,16 +234,16 @@ void __init dove_init_early(void)
         orion_time_set_base(TIMER_VIRT_BASE);
 }
 
-static int get_tclk(void)
+static int __init dove_find_tclk(void)
 {
-        /* use DOVE_RESET_SAMPLE_HI/LO to detect tclk */
         return 166666667;
 }
 
 static void __init dove_timer_init(void)
 {
+        dove_tclk = dove_find_tclk();
         orion_time_init(BRIDGE_VIRT_BASE, BRIDGE_INT_TIMER1_CLR,
-                        IRQ_DOVE_BRIDGE, get_tclk());
+                        IRQ_DOVE_BRIDGE, dove_tclk);
 }
 
 struct sys_timer dove_timer = {
@@ -195,6 +251,15 @@ struct sys_timer dove_timer = {
 };
 
 /*****************************************************************************
+ * Cryptographic Engines and Security Accelerator (CESA)
+ ****************************************************************************/
+void __init dove_crypto_init(void)
+{
+        orion_crypto_init(DOVE_CRYPT_PHYS_BASE, DOVE_CESA_PHYS_BASE,
+                          DOVE_CESA_SIZE, IRQ_DOVE_CRYPTO);
+}
+
+/*****************************************************************************
  * XOR 0
  ****************************************************************************/
 void __init dove_xor0_init(void)
@@ -275,8 +340,8 @@ void __init dove_sdio1_init(void)
 
 void __init dove_init(void)
 {
-        printk(KERN_INFO "Dove 88AP510 SoC, ");
-        printk(KERN_INFO "TCLK = %dMHz\n", (get_tclk() + 499999) / 1000000);
+        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+                (dove_tclk + 499999) / 1000000);
 
 #ifdef CONFIG_CACHE_TAUROS2
         tauros2_init(0);
@@ -284,7 +349,7 @@ void __init dove_init(void)
         dove_setup_cpu_mbus();
 
         /* Setup root of clk tree */
-        clk_init();
+        dove_clk_init();
 
         /* internal devices that every board has */
         dove_rtc_init();
@@ -307,3 +372,67 @@ void dove_restart(char mode, const char *cmd)
         while (1)
                 ;
 }
+
+#if defined(CONFIG_MACH_DOVE_DT)
+/*
+ * Auxdata required until real OF clock provider
+ */
+struct of_dev_auxdata dove_auxdata_lookup[] __initdata = {
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1010600, "orion_spi.0", NULL),
+        OF_DEV_AUXDATA("marvell,orion-spi", 0xf1014600, "orion_spi.1", NULL),
+        OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
+        OF_DEV_AUXDATA("marvell,mv64xxx-i2c", 0xf1011000, "mv64xxx_i2c.0",
+                       NULL),
+        OF_DEV_AUXDATA("marvell,orion-sata", 0xf10a0000, "sata_mv.0", NULL),
+        OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1092000, "sdhci-dove.0", NULL),
+        OF_DEV_AUXDATA("marvell,dove-sdhci", 0xf1090000, "sdhci-dove.1", NULL),
+        {},
+};
+
+static struct mv643xx_eth_platform_data dove_dt_ge00_data = {
+        .phy_addr = MV643XX_ETH_PHY_ADDR_DEFAULT,
+};
+
+static void __init dove_dt_init(void)
+{
+        pr_info("Dove 88AP510 SoC, TCLK = %d MHz.\n",
+                (dove_tclk + 499999) / 1000000);
+
+#ifdef CONFIG_CACHE_TAUROS2
+        tauros2_init();
+#endif
+        dove_setup_cpu_mbus();
+
+        /* Setup root of clk tree */
+        dove_clk_init();
+
+        /* Internal devices not ported to DT yet */
+        dove_rtc_init();
+        dove_xor0_init();
+        dove_xor1_init();
+
+        dove_ge00_init(&dove_dt_ge00_data);
+        dove_ehci0_init();
+        dove_ehci1_init();
+        dove_pcie_init(1, 1);
+        dove_crypto_init();
+
+        of_platform_populate(NULL, of_default_bus_match_table,
+                             dove_auxdata_lookup, NULL);
+}
+
+static const char * const dove_dt_board_compat[] = {
+        "marvell,dove",
+        NULL
+};
+
+DT_MACHINE_START(DOVE_DT, "Marvell Dove (Flattened Device Tree)")
+        .map_io         = dove_map_io,
+        .init_early     = dove_init_early,
+        .init_irq       = orion_dt_init_irq,
+        .timer          = &dove_timer,
+        .init_machine   = dove_dt_init,
+        .restart        = dove_restart,
+        .dt_compat      = dove_dt_board_compat,
+MACHINE_END
+#endif
diff --git a/arch/arm/mach-dove/common.h b/arch/arm/mach-dove/common.h
index 6432a3ba864b..1a233404b735 100644
--- a/arch/arm/mach-dove/common.h
+++ b/arch/arm/mach-dove/common.h
@@ -26,7 +26,11 @@ void dove_init_irq(void);
 void dove_setup_cpu_mbus(void);
 void dove_ge00_init(struct mv643xx_eth_platform_data *eth_data);
 void dove_sata_init(struct mv_sata_platform_data *sata_data);
+#ifdef CONFIG_PCI
 void dove_pcie_init(int init_port0, int init_port1);
+#else
+static inline void dove_pcie_init(int init_port0, int init_port1) { }
+#endif
 void dove_ehci0_init(void);
 void dove_ehci1_init(void);
 void dove_uart0_init(void);
diff --git a/arch/arm/mach-dove/include/mach/bridge-regs.h b/arch/arm/mach-dove/include/mach/bridge-regs.h
index f953bb54aa9d..99f259e8cf33 100644
--- a/arch/arm/mach-dove/include/mach/bridge-regs.h
+++ b/arch/arm/mach-dove/include/mach/bridge-regs.h
@@ -13,22 +13,22 @@
 
 #include <mach/dove.h>
 
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0000)
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0000)
 
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define  CPU_CTRL_PCIE0_LINK    0x00000001
 #define  CPU_RESET              0x00000002
 #define  CPU_CTRL_PCIE1_LINK    0x00000008
 
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define  SOFT_RESET_OUT_EN      0x00000004
 
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define  SOFT_RESET             0x00000001
 
 #define  BRIDGE_INT_TIMER1_CLR  (~0x0004)
 
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF       0x0000
 #define IRQ_MASK_LOW_OFF        0x0004
 #define FIQ_MASK_LOW_OFF        0x0008
@@ -47,9 +47,9 @@
 #define ENDPOINT_MASK_HIGH      (IRQ_VIRT_BASE + ENDPOINT_MASK_HIGH_OFF)
 #define PCIE_INTERRUPT_MASK     (IRQ_VIRT_BASE + PCIE_INTERRUPT_MASK_OFF)
 
-#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE | 0x011c)
+#define POWER_MANAGEMENT        (BRIDGE_VIRT_BASE + 0x011c)
 
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
 #endif
diff --git a/arch/arm/mach-dove/include/mach/dove.h b/arch/arm/mach-dove/include/mach/dove.h
index c91e3004a47b..661725e3115a 100644
--- a/arch/arm/mach-dove/include/mach/dove.h
+++ b/arch/arm/mach-dove/include/mach/dove.h
@@ -25,7 +25,7 @@
  */
 
 #define DOVE_CESA_PHYS_BASE             0xc8000000
-#define DOVE_CESA_VIRT_BASE             0xfdb00000
+#define DOVE_CESA_VIRT_BASE             IOMEM(0xfdb00000)
 #define DOVE_CESA_SIZE                  SZ_1M
 
 #define DOVE_PCIE0_MEM_PHYS_BASE        0xe0000000
@@ -38,15 +38,15 @@
 #define DOVE_BOOTROM_SIZE               SZ_128M
 
 #define DOVE_SCRATCHPAD_PHYS_BASE       0xf0000000
-#define DOVE_SCRATCHPAD_VIRT_BASE       0xfdd00000
+#define DOVE_SCRATCHPAD_VIRT_BASE       IOMEM(0xfdd00000)
 #define DOVE_SCRATCHPAD_SIZE            SZ_1M
 
 #define DOVE_SB_REGS_PHYS_BASE          0xf1000000
-#define DOVE_SB_REGS_VIRT_BASE          0xfde00000
+#define DOVE_SB_REGS_VIRT_BASE          IOMEM(0xfde00000)
 #define DOVE_SB_REGS_SIZE               SZ_8M
 
 #define DOVE_NB_REGS_PHYS_BASE          0xf1800000
-#define DOVE_NB_REGS_VIRT_BASE          0xfe600000
+#define DOVE_NB_REGS_VIRT_BASE          IOMEM(0xfe600000)
 #define DOVE_NB_REGS_SIZE               SZ_8M
 
 #define DOVE_PCIE0_IO_PHYS_BASE         0xf2000000
@@ -62,75 +62,75 @@
  */
 
 /* SPI, I2C, UART */
-#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x11000)
-#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12000)
-#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12000)
-#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12100)
-#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12100)
-#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12200)
-#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12200)
-#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x12300)
-#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x12300)
-#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x10600)
-#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x14600)
+#define DOVE_I2C_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x11000)
+#define DOVE_UART0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12000)
+#define DOVE_UART0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12000)
+#define DOVE_UART1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12100)
+#define DOVE_UART1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12100)
+#define DOVE_UART2_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12200)
+#define DOVE_UART2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12200)
+#define DOVE_UART3_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x12300)
+#define DOVE_UART3_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x12300)
+#define DOVE_SPI0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x10600)
+#define DOVE_SPI1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x14600)
 
 /* North-South Bridge */
-#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x20000)
-#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x20000)
+#define BRIDGE_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x20000)
+#define BRIDGE_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x20000)
 
 /* Cryptographic Engine */
-#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_CRYPT_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x30000)
 
 /* PCIe 0 */
-#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x40000)
+#define DOVE_PCIE0_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x40000)
 
 /* USB */
-#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x50000)
-#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x51000)
+#define DOVE_USB0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x50000)
+#define DOVE_USB1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x51000)
 
 /* XOR 0 Engine */
-#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60800)
-#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60800)
-#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60A00)
-#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60A00)
+#define DOVE_XOR0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60800)
+#define DOVE_XOR0_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60800)
+#define DOVE_XOR0_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60A00)
+#define DOVE_XOR0_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60A00)
 
 /* XOR 1 Engine */
-#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x60900)
-#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0x60900)
-#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE | 0x60B00)
-#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE | 0x60B00)
+#define DOVE_XOR1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x60900)
+#define DOVE_XOR1_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0x60900)
+#define DOVE_XOR1_HIGH_PHYS_BASE        (DOVE_SB_REGS_PHYS_BASE + 0x60B00)
+#define DOVE_XOR1_HIGH_VIRT_BASE        (DOVE_SB_REGS_VIRT_BASE + 0x60B00)
 
 /* Gigabit Ethernet */
-#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0x70000)
+#define DOVE_GE00_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0x70000)
 
 /* PCIe 1 */
-#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0x80000)
+#define DOVE_PCIE1_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0x80000)
 
 /* CAFE */
-#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x92000)
-#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE | 0x90000)
-#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0x94000)
-#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE | 0x98000)
+#define DOVE_SDIO0_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x92000)
+#define DOVE_SDIO1_PHYS_BASE    (DOVE_SB_REGS_PHYS_BASE + 0x90000)
+#define DOVE_CAM_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0x94000)
+#define DOVE_CAFE_WIN_PHYS_BASE (DOVE_SB_REGS_PHYS_BASE + 0x98000)
 
 /* SATA */
-#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xa0000)
+#define DOVE_SATA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xa0000)
 
 /* I2S/SPDIF */
-#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb0000)
-#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xb4000)
+#define DOVE_AUD0_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb0000)
+#define DOVE_AUD1_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xb4000)
 
 /* NAND Flash Controller */
-#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xc0000)
+#define DOVE_NFC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xc0000)
 
 /* MPP, GPIO, Reset Sampling */
-#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_MPP_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0200)
 #define DOVE_PMU_MPP_GENERAL_CTRL (DOVE_MPP_VIRT_BASE + 0x10)
-#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE | 0x014)
-#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE | 0x018)
-#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
-#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE | 0xd0420)
-#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE | 0xe8400)
-#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define DOVE_RESET_SAMPLE_LO    (DOVE_MPP_VIRT_BASE + 0x014)
+#define DOVE_RESET_SAMPLE_HI    (DOVE_MPP_VIRT_BASE + 0x018)
+#define DOVE_GPIO_LO_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0400)
+#define DOVE_GPIO_HI_VIRT_BASE  (DOVE_SB_REGS_VIRT_BASE + 0xd0420)
+#define DOVE_GPIO2_VIRT_BASE    (DOVE_SB_REGS_VIRT_BASE + 0xe8400)
+#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xe803c)
 #define  DOVE_AU1_SPDIFO_GPIO_EN        (1 << 1)
 #define  DOVE_NAND_GPIO_EN              (1 << 0)
 #define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_LO_VIRT_BASE + 0x40)
@@ -142,44 +142,44 @@
 #define  DOVE_SD0_GPIO_SEL              (1 << 0)
 
 /* Power Management */
-#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xd0000)
+#define DOVE_PMU_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE + 0xd0000)
 #define DOVE_PMU_SIG_CTRL       (DOVE_PMU_VIRT_BASE + 0x802c)
 
 /* Real Time Clock */
-#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xd8500)
+#define DOVE_RTC_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xd8500)
 
 /* AC97 */
-#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe0000)
-#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe0000)
+#define DOVE_AC97_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe0000)
+#define DOVE_AC97_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe0000)
 
 /* Peripheral DMA */
-#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE | 0xe4000)
-#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE | 0xe4000)
+#define DOVE_PDMA_PHYS_BASE     (DOVE_SB_REGS_PHYS_BASE + 0xe4000)
+#define DOVE_PDMA_VIRT_BASE     (DOVE_SB_REGS_VIRT_BASE + 0xe4000)
 
-#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define DOVE_GLOBAL_CONFIG_1    (DOVE_SB_REGS_VIRT_BASE + 0xe802C)
 #define  DOVE_TWSI_ENABLE_OPTION1       (1 << 7)
-#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define DOVE_GLOBAL_CONFIG_2    (DOVE_SB_REGS_VIRT_BASE + 0xe8030)
 #define  DOVE_TWSI_ENABLE_OPTION2       (1 << 20)
 #define  DOVE_TWSI_ENABLE_OPTION3       (1 << 21)
 #define  DOVE_TWSI_OPTION3_GPIO         (1 << 22)
-#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE | 0xec000)
-#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define DOVE_SSP_PHYS_BASE      (DOVE_SB_REGS_PHYS_BASE + 0xec000)
+#define DOVE_SSP_CTRL_STATUS_1  (DOVE_SB_REGS_VIRT_BASE + 0xe8034)
 #define  DOVE_SSP_ON_AU1                (1 << 0)
 #define  DOVE_SSP_CLOCK_ENABLE          (1 << 1)
 #define  DOVE_SSP_BPB_CLOCK_SRC_SSP     (1 << 11)
 /* Memory Controller */
-#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE | 0x00000)
+#define DOVE_MC_VIRT_BASE       (DOVE_NB_REGS_VIRT_BASE + 0x00000)
 
 /* LCD Controller */
-#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x10000)
-#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x20000)
-#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE | 0x10000)
-#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE | 0x30000)
+#define DOVE_LCD_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x10000)
+#define DOVE_LCD1_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x20000)
+#define DOVE_LCD2_PHYS_BASE     (DOVE_NB_REGS_PHYS_BASE + 0x10000)
+#define DOVE_LCD_DCON_PHYS_BASE (DOVE_NB_REGS_PHYS_BASE + 0x30000)
 
 /* Graphic Engine */
-#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x40000)
+#define DOVE_GPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x40000)
 
 /* Video Engine */
-#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE | 0x400000)
+#define DOVE_VPU_PHYS_BASE      (DOVE_NB_REGS_PHYS_BASE + 0x400000)
 
 #endif
diff --git a/arch/arm/mach-dove/include/mach/pm.h b/arch/arm/mach-dove/include/mach/pm.h
index 3ad9f946a9e8..7bcd0dfce4b1 100644
--- a/arch/arm/mach-dove/include/mach/pm.h
+++ b/arch/arm/mach-dove/include/mach/pm.h
@@ -13,24 +13,42 @@
 #include <mach/irqs.h>
 
 #define CLOCK_GATING_CONTROL    (DOVE_PMU_VIRT_BASE + 0x38)
-#define  CLOCK_GATING_USB0_MASK         (1 << 0)
-#define  CLOCK_GATING_USB1_MASK         (1 << 1)
-#define  CLOCK_GATING_GBE_MASK          (1 << 2)
-#define  CLOCK_GATING_SATA_MASK         (1 << 3)
-#define  CLOCK_GATING_PCIE0_MASK        (1 << 4)
-#define  CLOCK_GATING_PCIE1_MASK        (1 << 5)
-#define  CLOCK_GATING_SDIO0_MASK        (1 << 8)
-#define  CLOCK_GATING_SDIO1_MASK        (1 << 9)
-#define  CLOCK_GATING_NAND_MASK         (1 << 10)
-#define  CLOCK_GATING_CAMERA_MASK       (1 << 11)
-#define  CLOCK_GATING_I2S0_MASK         (1 << 12)
-#define  CLOCK_GATING_I2S1_MASK         (1 << 13)
-#define  CLOCK_GATING_CRYPTO_MASK       (1 << 15)
-#define  CLOCK_GATING_AC97_MASK         (1 << 21)
-#define  CLOCK_GATING_PDMA_MASK         (1 << 22)
-#define  CLOCK_GATING_XOR0_MASK         (1 << 23)
-#define  CLOCK_GATING_XOR1_MASK         (1 << 24)
-#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << 30)
+#define  CLOCK_GATING_BIT_USB0          0
+#define  CLOCK_GATING_BIT_USB1          1
+#define  CLOCK_GATING_BIT_GBE           2
+#define  CLOCK_GATING_BIT_SATA          3
+#define  CLOCK_GATING_BIT_PCIE0         4
+#define  CLOCK_GATING_BIT_PCIE1         5
+#define  CLOCK_GATING_BIT_SDIO0         8
+#define  CLOCK_GATING_BIT_SDIO1         9
+#define  CLOCK_GATING_BIT_NAND          10
+#define  CLOCK_GATING_BIT_CAMERA        11
+#define  CLOCK_GATING_BIT_I2S0          12
+#define  CLOCK_GATING_BIT_I2S1          13
+#define  CLOCK_GATING_BIT_CRYPTO        15
+#define  CLOCK_GATING_BIT_AC97          21
+#define  CLOCK_GATING_BIT_PDMA          22
+#define  CLOCK_GATING_BIT_XOR0          23
+#define  CLOCK_GATING_BIT_XOR1          24
+#define  CLOCK_GATING_BIT_GIGA_PHY      30
+#define  CLOCK_GATING_USB0_MASK         (1 << CLOCK_GATING_BIT_USB0)
+#define  CLOCK_GATING_USB1_MASK         (1 << CLOCK_GATING_BIT_USB1)
+#define  CLOCK_GATING_GBE_MASK          (1 << CLOCK_GATING_BIT_GBE)
+#define  CLOCK_GATING_SATA_MASK         (1 << CLOCK_GATING_BIT_SATA)
+#define  CLOCK_GATING_PCIE0_MASK        (1 << CLOCK_GATING_BIT_PCIE0)
+#define  CLOCK_GATING_PCIE1_MASK        (1 << CLOCK_GATING_BIT_PCIE1)
+#define  CLOCK_GATING_SDIO0_MASK        (1 << CLOCK_GATING_BIT_SDIO0)
+#define  CLOCK_GATING_SDIO1_MASK        (1 << CLOCK_GATING_BIT_SDIO1)
+#define  CLOCK_GATING_NAND_MASK         (1 << CLOCK_GATING_BIT_NAND)
+#define  CLOCK_GATING_CAMERA_MASK       (1 << CLOCK_GATING_BIT_CAMERA)
+#define  CLOCK_GATING_I2S0_MASK         (1 << CLOCK_GATING_BIT_I2S0)
+#define  CLOCK_GATING_I2S1_MASK         (1 << CLOCK_GATING_BIT_I2S1)
+#define  CLOCK_GATING_CRYPTO_MASK       (1 << CLOCK_GATING_BIT_CRYPTO)
+#define  CLOCK_GATING_AC97_MASK         (1 << CLOCK_GATING_BIT_AC97)
+#define  CLOCK_GATING_PDMA_MASK         (1 << CLOCK_GATING_BIT_PDMA)
+#define  CLOCK_GATING_XOR0_MASK         (1 << CLOCK_GATING_BIT_XOR0)
+#define  CLOCK_GATING_XOR1_MASK         (1 << CLOCK_GATING_BIT_XOR1)
+#define  CLOCK_GATING_GIGA_PHY_MASK     (1 << CLOCK_GATING_BIT_GIGA_PHY)
 
 #define PMU_INTERRUPT_CAUSE     (DOVE_PMU_VIRT_BASE + 0x50)
 #define PMU_INTERRUPT_MASK      (DOVE_PMU_VIRT_BASE + 0x54)
diff --git a/arch/arm/mach-dove/irq.c b/arch/arm/mach-dove/irq.c
index 186357f3b4db..087711524e8a 100644
--- a/arch/arm/mach-dove/irq.c
+++ b/arch/arm/mach-dove/irq.c
@@ -100,19 +100,19 @@ void __init dove_init_irq(void)
 {
         int i;
 
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
         /*
          * Initialize gpiolib for GPIOs 0-71.
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)DOVE_GPIO_LO_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START, gpio0_irqs);
 
-        orion_gpio_init(NULL, 32, 32, (void __iomem *)DOVE_GPIO_HI_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START + 32, gpio1_irqs);
 
-        orion_gpio_init(NULL, 64, 8, (void __iomem *)DOVE_GPIO2_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 64, 8, DOVE_GPIO2_VIRT_BASE, 0,
                         IRQ_DOVE_GPIO_START + 64, gpio2_irqs);
 
         /*
diff --git a/arch/arm/mach-dove/pcie.c b/arch/arm/mach-dove/pcie.c
index 355332d502cb..bb15b26041cb 100644
--- a/arch/arm/mach-dove/pcie.c
+++ b/arch/arm/mach-dove/pcie.c
@@ -182,18 +182,18 @@ static struct hw_pci dove_pci __initdata = {
         .map_irq        = dove_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
         printk(KERN_INFO "Dove PCIe port %d: ", index);
 
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
 
                 printk(KERN_INFO "link up\n");
 
                 pp->index = index;
                 pp->root_bus_nr = -1;
-                pp->base = (void __iomem *)base;
+                pp->base = base;
                 spin_lock_init(&pp->conf_lock);
                 memset(&pp->res, 0, sizeof(pp->res));
         } else {
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index ca5c15a4e626..50bca5032b7e 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -94,6 +94,13 @@ config MACH_TS219_DT
           or MV6282. If you have the wrong one, the buttons will not
           work.
 
+config MACH_DOCKSTAR_DT
+        bool "Seagate FreeAgent Dockstar (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Seagate FreeAgent Dockstar (Flattened Device Tree).
+
 config MACH_GOFLEXNET_DT
         bool "Seagate GoFlex Net (Flattened Device Tree)"
         select ARCH_KIRKWOOD_DT
@@ -109,6 +116,20 @@ config MACH_LSXL_DT
           Buffalo Linkstation LS-XHL & LS-CHLv2 devices, using
           Flattened Device Tree.
 
+config MACH_IOMEGA_IX2_200_DT
+        bool "Iomega StorCenter ix2-200 (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Iomega StorCenter ix2-200 (Flattened Device Tree).
+
+config MACH_KM_KIRKWOOD_DT
+        bool "Keymile Kirkwood Reference Design (Flattened Device Tree)"
+        select ARCH_KIRKWOOD_DT
+        help
+          Say 'Y' here if you want your kernel to support the
+          Keymile Kirkwood Reference Desgin, using Flattened Device Tree.
+
 config MACH_TS219
         bool "QNAP TS-110, TS-119, TS-119P+, TS-210, TS-219, TS-219P and TS-219P+ Turbo NAS"
         help
diff --git a/arch/arm/mach-kirkwood/Makefile b/arch/arm/mach-kirkwood/Makefile
index 055c85a1cc46..294779f892d9 100644
--- a/arch/arm/mach-kirkwood/Makefile
+++ b/arch/arm/mach-kirkwood/Makefile
@@ -26,5 +26,8 @@ obj-$(CONFIG_MACH_ICONNECT_DT)		+= board-iconnect.o
 obj-$(CONFIG_MACH_DLINK_KIRKWOOD_DT)    += board-dnskw.o
 obj-$(CONFIG_MACH_IB62X0_DT)            += board-ib62x0.o
 obj-$(CONFIG_MACH_TS219_DT)             += board-ts219.o tsx1x-common.o
+obj-$(CONFIG_MACH_DOCKSTAR_DT)          += board-dockstar.o
 obj-$(CONFIG_MACH_GOFLEXNET_DT)         += board-goflexnet.o
 obj-$(CONFIG_MACH_LSXL_DT)              += board-lsxl.o
+obj-$(CONFIG_MACH_IOMEGA_IX2_200_DT)    += board-iomega_ix2_200.o
+obj-$(CONFIG_MACH_KM_KIRKWOOD_DT)       += board-km_kirkwood.o
diff --git a/arch/arm/mach-kirkwood/addr-map.c b/arch/arm/mach-kirkwood/addr-map.c
index e9a7180863d9..8f0d162a1e1d 100644
--- a/arch/arm/mach-kirkwood/addr-map.c
+++ b/arch/arm/mach-kirkwood/addr-map.c
@@ -86,5 +86,6 @@ void __init kirkwood_setup_cpu_mbus(void)
         /*
          * Setup MBUS dram target info.
          */
-        orion_setup_cpu_mbus_target(&addr_map_cfg, DDR_WINDOW_CPU_BASE);
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    (void __iomem *) DDR_WINDOW_CPU_BASE);
 }
diff --git a/arch/arm/mach-kirkwood/board-dnskw.c b/arch/arm/mach-kirkwood/board-dnskw.c
index 4ab35065a144..43d16d6714b8 100644
--- a/arch/arm/mach-kirkwood/board-dnskw.c
+++ b/arch/arm/mach-kirkwood/board-dnskw.c
@@ -14,18 +14,8 @@
 #include <linux/kernel.h>
 #include <linux/init.h>
 #include <linux/platform_device.h>
-#include <linux/ata_platform.h>
 #include <linux/mv643xx_eth.h>
-#include <linux/of.h>
 #include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio-fan.h>
-#include <linux/leds.h>
-#include <asm/mach-types.h>
-#include <asm/mach/arch.h>
-#include <asm/mach/map.h>
-#include <mach/kirkwood.h>
-#include <mach/bridge-regs.h>
 #include "common.h"
 #include "mpp.h"
 
@@ -67,29 +57,6 @@ static unsigned int dnskw_mpp_config[] __initdata = {
         0
 };
 
-/* Fan: ADDA AD045HB-G73 40mm 6000rpm@5v */
-static struct gpio_fan_speed dnskw_fan_speed[] = {
-        {    0,  0 },
-        { 3000,  1 },
-        { 6000,  2 },
-};
-static unsigned dnskw_fan_pins[] = {46, 45};
-
-static struct gpio_fan_platform_data dnskw_fan_data = {
-        .num_ctrl       = ARRAY_SIZE(dnskw_fan_pins),
-        .ctrl           = dnskw_fan_pins,
-        .num_speed      = ARRAY_SIZE(dnskw_fan_speed),
-        .speed          = dnskw_fan_speed,
-};
-
-static struct platform_device dnskw_fan_device = {
-        .name   = "gpio-fan",
-        .id     = -1,
-        .dev    = {
-                .platform_data  = &dnskw_fan_data,
-        },
-};
-
 static void dnskw_power_off(void)
 {
         gpio_set_value(36, 1);
@@ -114,8 +81,6 @@ void __init dnskw_init(void)
         kirkwood_ehci_init();
         kirkwood_ge00_init(&dnskw_ge00_data);
 
-        platform_device_register(&dnskw_fan_device);
-
         /* Register power-off GPIO. */
         if (gpio_request(36, "dnskw:power:off") == 0
             && gpio_direction_output(36, 0) == 0)
diff --git a/arch/arm/mach-kirkwood/board-dockstar.c b/arch/arm/mach-kirkwood/board-dockstar.c
new file mode 100644
index 000000000000..f2fbb023e679
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-dockstar.c
@@ -0,0 +1,61 @@
+/*
+ * arch/arm/mach-kirkwood/board-dockstar.c
+ *
+ * Seagate FreeAgent Dockstar Board Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * Copied and modified for Seagate GoFlex Net support by
+ * Joshua Coombs <josh.coombs@gmail.com> based on ArchLinux ARM's
+ * GoFlex kernel patches.
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/ata_platform.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_fdt.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/gpio.h>
+#include <asm/mach-types.h>
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <mach/kirkwood.h>
+#include <mach/bridge-regs.h>
+#include <linux/platform_data/mmc-mvsdio.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data dockstar_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int dockstar_mpp_config[] __initdata = {
+        MPP29_GPIO,     /* USB Power Enable */
+        MPP46_GPIO,     /* LED green */
+        MPP47_GPIO,     /* LED orange */
+        0
+};
+
+void __init dockstar_dt_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(dockstar_mpp_config);
+
+        if (gpio_request(29, "USB Power Enable") != 0 ||
+            gpio_direction_output(29, 1) != 0)
+                pr_err("can't setup GPIO 29 (USB Power Enable)\n");
+        kirkwood_ehci_init();
+
+        kirkwood_ge00_init(&dockstar_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-dt.c b/arch/arm/mach-kirkwood/board-dt.c
index e4eb450de301..70c5a2882409 100644
--- a/arch/arm/mach-kirkwood/board-dt.c
+++ b/arch/arm/mach-kirkwood/board-dt.c
@@ -33,6 +33,7 @@ struct of_dev_auxdata kirkwood_auxdata_lookup[] __initdata = {
         OF_DEV_AUXDATA("marvell,orion-wdt", 0xf1020300, "orion_wdt", NULL),
         OF_DEV_AUXDATA("marvell,orion-sata", 0xf1080000, "sata_mv.0", NULL),
         OF_DEV_AUXDATA("marvell,orion-nand", 0xf4000000, "orion_nand", NULL),
+        OF_DEV_AUXDATA("marvell,orion-crypto", 0xf1030000, "mv_crypto", NULL),
         {},
 };
 
@@ -60,7 +61,6 @@ static void __init kirkwood_dt_init(void)
         /* internal devices that every board has */
         kirkwood_xor0_init();
         kirkwood_xor1_init();
-        kirkwood_crypto_init();
 
 #ifdef CONFIG_KEXEC
         kexec_reinit = kirkwood_enable_pcie;
@@ -81,12 +81,21 @@ static void __init kirkwood_dt_init(void)
         if (of_machine_is_compatible("qnap,ts219"))
                 qnap_dt_ts219_init();
 
+        if (of_machine_is_compatible("seagate,dockstar"))
+                dockstar_dt_init();
+
         if (of_machine_is_compatible("seagate,goflexnet"))
                 goflexnet_init();
 
         if (of_machine_is_compatible("buffalo,lsxl"))
                 lsxl_init();
 
+        if (of_machine_is_compatible("iom,ix2-200"))
+                iomega_ix2_200_init();
+
+        if (of_machine_is_compatible("keymile,km_kirkwood"))
+                km_kirkwood_init();
+
         of_platform_populate(NULL, kirkwood_dt_match_table,
                              kirkwood_auxdata_lookup, NULL);
 }
@@ -98,8 +107,11 @@ static const char *kirkwood_dt_board_compat[] = {
         "iom,iconnect",
         "raidsonic,ib-nas62x0",
         "qnap,ts219",
+        "seagate,dockstar",
         "seagate,goflexnet",
         "buffalo,lsxl",
+        "iom,ix2-200",
+        "keymile,km_kirkwood",
         NULL
 };
 
diff --git a/arch/arm/mach-kirkwood/board-iconnect.c b/arch/arm/mach-kirkwood/board-iconnect.c
index d7a9198ed300..d084b1e2943a 100644
--- a/arch/arm/mach-kirkwood/board-iconnect.c
+++ b/arch/arm/mach-kirkwood/board-iconnect.c
@@ -16,11 +16,8 @@
 #include <linux/of_fdt.h>
 #include <linux/of_irq.h>
 #include <linux/of_platform.h>
-#include <linux/mtd/partitions.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/gpio.h>
-#include <linux/input.h>
-#include <linux/gpio_keys.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
 #include "common.h"
@@ -44,57 +41,12 @@ static unsigned int iconnect_mpp_config[] __initdata = {
         0
 };
 
-static struct mtd_partition iconnect_nand_parts[] = {
-        {
-                .name = "flash",
-                .offset = 0,
-                .size = MTDPART_SIZ_FULL,
-        },
-};
-
-/* yikes... theses are the original input buttons */
-/* but I'm not convinced by the sw event choices  */
-static struct gpio_keys_button iconnect_buttons[] = {
-        {
-                .type           = EV_SW,
-                .code           = SW_LID,
-                .gpio           = 12,
-                .desc           = "Reset Button",
-                .active_low     = 1,
-                .debounce_interval = 100,
-        }, {
-                .type           = EV_SW,
-                .code           = SW_TABLET_MODE,
-                .gpio           = 35,
-                .desc           = "OTB Button",
-                .active_low     = 1,
-                .debounce_interval = 100,
-        },
-};
-
-static struct gpio_keys_platform_data iconnect_button_data = {
-        .buttons        = iconnect_buttons,
-        .nbuttons       = ARRAY_SIZE(iconnect_buttons),
-};
-
-static struct platform_device iconnect_button_device = {
-        .name           = "gpio-keys",
-        .id             = -1,
-        .num_resources  = 0,
-        .dev        = {
-                .platform_data  = &iconnect_button_data,
-        },
-};
-
 void __init iconnect_init(void)
 {
         kirkwood_mpp_conf(iconnect_mpp_config);
-        kirkwood_nand_init(ARRAY_AND_SIZE(iconnect_nand_parts), 25);
 
         kirkwood_ehci_init();
         kirkwood_ge00_init(&iconnect_ge00_data);
-
-        platform_device_register(&iconnect_button_device);
 }
 
 static int __init iconnect_pci_init(void)
diff --git a/arch/arm/mach-kirkwood/board-iomega_ix2_200.c b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
new file mode 100644
index 000000000000..158fb97d0397
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-iomega_ix2_200.c
@@ -0,0 +1,57 @@
+/*
+ * arch/arm/mach-kirkwood/board-iomega_ix2_200.c
+ *
+ * Iomega StorCenter ix2-200
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/platform_device.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/ethtool.h>
+#include <mach/kirkwood.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data iomega_ix2_200_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_NONE,
+        .speed          = SPEED_1000,
+        .duplex         = DUPLEX_FULL,
+};
+
+static unsigned int iomega_ix2_200_mpp_config[] __initdata = {
+        MPP12_GPIO,                     /* Reset Button */
+        MPP14_GPIO,                     /* Power Button */
+        MPP15_GPIO,                     /* Backup LED (blue) */
+        MPP16_GPIO,                     /* Power LED (white) */
+        MPP35_GPIO,                     /* OTB Button */
+        MPP36_GPIO,                     /* Rebuild LED (white) */
+        MPP37_GPIO,                     /* Health LED (red) */
+        MPP38_GPIO,                     /* SATA LED brightness control 1 */
+        MPP39_GPIO,                     /* SATA LED brightness control 2 */
+        MPP40_GPIO,                     /* Backup LED brightness control 1 */
+        MPP41_GPIO,                     /* Backup LED brightness control 2 */
+        MPP42_GPIO,                     /* Power LED brightness control 1 */
+        MPP43_GPIO,                     /* Power LED brightness control 2 */
+        MPP44_GPIO,                     /* Health LED brightness control 1 */
+        MPP45_GPIO,                     /* Health LED brightness control 2 */
+        MPP46_GPIO,                     /* Rebuild LED brightness control 1 */
+        MPP47_GPIO,                     /* Rebuild LED brightness control 2 */
+        0
+};
+
+void __init iomega_ix2_200_init(void)
+{
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(iomega_ix2_200_mpp_config);
+
+        kirkwood_ehci_init();
+
+        kirkwood_ge01_init(&iomega_ix2_200_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/board-km_kirkwood.c b/arch/arm/mach-kirkwood/board-km_kirkwood.c
new file mode 100644
index 000000000000..f7d32834b757
--- /dev/null
+++ b/arch/arm/mach-kirkwood/board-km_kirkwood.c
@@ -0,0 +1,57 @@
+/*
+ * Copyright 2012 2012 KEYMILE AG, CH-3097 Bern
+ * Valentin Longchamp <valentin.longchamp@keymile.com>
+ *
+ * arch/arm/mach-kirkwood/board-km_kirkwood.c
+ *
+ * Keymile km_kirkwood Reference Desing Init for drivers not converted to
+ * flattened device tree yet.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mv643xx_eth.h>
+#include <linux/clk.h>
+#include <linux/clk-private.h>
+#include "common.h"
+#include "mpp.h"
+
+static struct mv643xx_eth_platform_data km_kirkwood_ge00_data = {
+        .phy_addr       = MV643XX_ETH_PHY_ADDR(0),
+};
+
+static unsigned int km_kirkwood_mpp_config[] __initdata = {
+        MPP8_GPIO,      /* I2C SDA */
+        MPP9_GPIO,      /* I2C SCL */
+        0
+};
+
+void __init km_kirkwood_init(void)
+{
+        struct clk *sata_clk;
+        /*
+         * Basic setup. Needs to be called early.
+         */
+        kirkwood_mpp_conf(km_kirkwood_mpp_config);
+
+        /*
+         * Our variant of kirkwood (integrated in the Bobcat) hangs on accessing
+         * SATA bits (14-15) of the Clock Gating Control Register. Since these
+         * devices are also not present in this variant, their clocks get
+         * disabled because unused when clk_disable_unused() gets called.
+         * That's why we change the flags to these clocks to CLK_IGNORE_UNUSED
+         */
+        sata_clk = clk_get_sys("sata_mv.0", "0");
+        if (!IS_ERR(sata_clk))
+                sata_clk->flags |= CLK_IGNORE_UNUSED;
+        sata_clk = clk_get_sys("sata_mv.0", "1");
+        if (!IS_ERR(sata_clk))
+                sata_clk->flags |= CLK_IGNORE_UNUSED;
+
+        kirkwood_ehci_init();
+        kirkwood_ge00_init(&km_kirkwood_ge00_data);
+}
diff --git a/arch/arm/mach-kirkwood/common.c b/arch/arm/mach-kirkwood/common.c
index 5c38c94b79a2..3991077f58a2 100644
--- a/arch/arm/mach-kirkwood/common.c
+++ b/arch/arm/mach-kirkwood/common.c
@@ -42,7 +42,7 @@
  ****************************************************************************/
 static struct map_desc kirkwood_io_desc[] __initdata = {
         {
-                .virtual        = KIRKWOOD_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) KIRKWOOD_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(KIRKWOOD_REGS_PHYS_BASE),
                 .length         = KIRKWOOD_REGS_SIZE,
                 .type           = MT_DEVICE,
@@ -205,8 +205,7 @@ static struct clk *tclk;
 
 static struct clk __init *kirkwood_register_gate(const char *name, u8 bit_idx)
 {
-        return clk_register_gate(NULL, name, "tclk", 0,
-                                 (void __iomem *)CLOCK_GATING_CTRL,
+        return clk_register_gate(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
                                  bit_idx, 0, &gating_lock);
 }
 
@@ -215,8 +214,7 @@ static struct clk __init *kirkwood_register_gate_fn(const char *name,
                                                     void (*fn_en)(void),
                                                     void (*fn_dis)(void))
 {
-        return clk_register_gate_fn(NULL, name, "tclk", 0,
-                                    (void __iomem *)CLOCK_GATING_CTRL,
+        return clk_register_gate_fn(NULL, name, "tclk", 0, CLOCK_GATING_CTRL,
                                     bit_idx, 0, &gating_lock, fn_en, fn_dis);
 }
 
diff --git a/arch/arm/mach-kirkwood/common.h b/arch/arm/mach-kirkwood/common.h
index 304dd1abfdca..bcffd7ca1ca2 100644
--- a/arch/arm/mach-kirkwood/common.h
+++ b/arch/arm/mach-kirkwood/common.h
@@ -82,6 +82,12 @@ void ib62x0_init(void);
 static inline void ib62x0_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_DOCKSTAR_DT
+void dockstar_dt_init(void);
+#else
+static inline void dockstar_dt_init(void) {};
+#endif
+
 #ifdef CONFIG_MACH_GOFLEXNET_DT
 void goflexnet_init(void);
 #else
@@ -94,6 +100,18 @@ void lsxl_init(void);
 static inline void lsxl_init(void) {};
 #endif
 
+#ifdef CONFIG_MACH_IOMEGA_IX2_200_DT
+void iomega_ix2_200_init(void);
+#else
+static inline void iomega_ix2_200_init(void) {};
+#endif
+
+#ifdef CONFIG_MACH_KM_KIRKWOOD_DT
+void km_kirkwood_init(void);
+#else
+static inline void km_kirkwood_init(void) {};
+#endif
+
 /* early init functions not converted to fdt yet */
 char *kirkwood_id(void);
 void kirkwood_l2_init(void);
diff --git a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
index a115142f8690..5c82b7dce4e2 100644
--- a/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
+++ b/arch/arm/mach-kirkwood/include/mach/bridge-regs.h
@@ -13,37 +13,37 @@
 
 #include <mach/kirkwood.h>
 
-#define CPU_CONFIG              (BRIDGE_VIRT_BASE | 0x0100)
+#define CPU_CONFIG              (BRIDGE_VIRT_BASE + 0x0100)
 #define CPU_CONFIG_ERROR_PROP   0x00000004
 
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define CPU_RESET               0x00000002
 
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define WDT_RESET_OUT_EN        0x00000002
 #define SOFT_RESET_OUT_EN       0x00000004
 
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
 
-#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE | 0x0110)
+#define BRIDGE_CAUSE            (BRIDGE_VIRT_BASE + 0x0110)
 #define WDT_INT_REQ             0x0008
 
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_LOW_OFF       0x0000
 #define IRQ_MASK_LOW_OFF        0x0004
 #define IRQ_CAUSE_HIGH_OFF      0x0010
 #define IRQ_MASK_HIGH_OFF       0x0014
 
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
-#define L2_CONFIG_REG           (BRIDGE_VIRT_BASE | 0x0128)
+#define L2_CONFIG_REG           (BRIDGE_VIRT_BASE + 0x0128)
 #define L2_WRITETHROUGH         0x00000010
 
-#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE | 0x11c)
+#define CLOCK_GATING_CTRL       (BRIDGE_VIRT_BASE + 0x11c)
 #define CGC_BIT_GE0             (0)
 #define CGC_BIT_PEX0            (2)
 #define CGC_BIT_USB0            (3)
diff --git a/arch/arm/mach-kirkwood/include/mach/kirkwood.h b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
index af4f0000dcef..041653a04a9c 100644
--- a/arch/arm/mach-kirkwood/include/mach/kirkwood.h
+++ b/arch/arm/mach-kirkwood/include/mach/kirkwood.h
@@ -45,7 +45,7 @@
 #define KIRKWOOD_PCIE_IO_SIZE           SZ_64K
 
 #define KIRKWOOD_REGS_PHYS_BASE         0xf1000000
-#define KIRKWOOD_REGS_VIRT_BASE         0xfed00000
+#define KIRKWOOD_REGS_VIRT_BASE         IOMEM(0xfed00000)
 #define KIRKWOOD_REGS_SIZE              SZ_1M
 
 #define KIRKWOOD_PCIE_MEM_PHYS_BASE     0xe0000000
@@ -59,61 +59,61 @@
 /*
  * Register Map
  */
-#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE | 0x1500)
-#define DDR_OPERATION_BASE      (DDR_VIRT_BASE | 0x1418)
-
-#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE | 0x0030)
-#define  DEVICE_ID              (DEV_BUS_VIRT_BASE | 0x0034)
-#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE | 0x0100)
-#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE | 0x0140)
-#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0300)
-#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x0600)
-#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
-
-#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE | 0x20000)
-#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE | 0x20000)
-
-#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE | 0x30000)
-
-#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x40000)
-#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE | 0x70)
-#define PCIE_STATUS             (PCIE_VIRT_BASE | 0x1a04)
-#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0x44000)
-#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE | 0x70)
-#define PCIE1_STATUS            (PCIE1_VIRT_BASE | 0x1a04)
-
-#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE | 0x50000)
-
-#define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60800)
-#define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60800)
-#define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x60900)
-#define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x60900)
-#define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60A00)
-#define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60A00)
-#define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE | 0x60B00)
-#define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE | 0x60B00)
-
-#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x74000)
-
-#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x80000)
-#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE | 0x80000)
-#define SATA0_IF_CTRL           (SATA_VIRT_BASE | 0x2050)
-#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE | 0x2330)
-#define SATA1_IF_CTRL           (SATA_VIRT_BASE | 0x4050)
-#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE | 0x4330)
-
-#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE | 0x90000)
-
-#define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE | 0xA0000)
-#define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE | 0xA0000)
+#define DDR_VIRT_BASE           (KIRKWOOD_REGS_VIRT_BASE + 0x00000)
+#define  DDR_WINDOW_CPU_BASE    (DDR_VIRT_BASE + 0x1500)
+#define DDR_OPERATION_BASE      (DDR_VIRT_BASE + 0x1418)
+
+#define DEV_BUS_PHYS_BASE       (KIRKWOOD_REGS_PHYS_BASE + 0x10000)
+#define DEV_BUS_VIRT_BASE       (KIRKWOOD_REGS_VIRT_BASE + 0x10000)
+#define  SAMPLE_AT_RESET        (DEV_BUS_VIRT_BASE + 0x0030)
+#define  DEVICE_ID              (DEV_BUS_VIRT_BASE + 0x0034)
+#define  GPIO_LOW_VIRT_BASE     (DEV_BUS_VIRT_BASE + 0x0100)
+#define  GPIO_HIGH_VIRT_BASE    (DEV_BUS_VIRT_BASE + 0x0140)
+#define  RTC_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0300)
+#define  SPI_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x0600)
+#define  I2C_PHYS_BASE          (DEV_BUS_PHYS_BASE + 0x1000)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
+
+#define BRIDGE_VIRT_BASE        (KIRKWOOD_REGS_VIRT_BASE + 0x20000)
+#define BRIDGE_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x20000)
+
+#define CRYPTO_PHYS_BASE        (KIRKWOOD_REGS_PHYS_BASE + 0x30000)
+
+#define PCIE_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x40000)
+#define PCIE_LINK_CTRL          (PCIE_VIRT_BASE + 0x70)
+#define PCIE_STATUS             (PCIE_VIRT_BASE + 0x1a04)
+#define PCIE1_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0x44000)
+#define PCIE1_LINK_CTRL         (PCIE1_VIRT_BASE + 0x70)
+#define PCIE1_STATUS            (PCIE1_VIRT_BASE + 0x1a04)
+
+#define USB_PHYS_BASE           (KIRKWOOD_REGS_PHYS_BASE + 0x50000)
+
+#define XOR0_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60800)
+#define XOR0_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60800)
+#define XOR1_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x60900)
+#define XOR1_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x60900)
+#define XOR0_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60A00)
+#define XOR0_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60A00)
+#define XOR1_HIGH_PHYS_BASE     (KIRKWOOD_REGS_PHYS_BASE + 0x60B00)
+#define XOR1_HIGH_VIRT_BASE     (KIRKWOOD_REGS_VIRT_BASE + 0x60B00)
+
+#define GE00_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x70000)
+#define GE01_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x74000)
+
+#define SATA_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x80000)
+#define SATA_VIRT_BASE          (KIRKWOOD_REGS_VIRT_BASE + 0x80000)
+#define SATA0_IF_CTRL           (SATA_VIRT_BASE + 0x2050)
+#define SATA0_PHY_MODE_2        (SATA_VIRT_BASE + 0x2330)
+#define SATA1_IF_CTRL           (SATA_VIRT_BASE + 0x4050)
+#define SATA1_PHY_MODE_2        (SATA_VIRT_BASE + 0x4330)
+
+#define SDIO_PHYS_BASE          (KIRKWOOD_REGS_PHYS_BASE + 0x90000)
+
+#define AUDIO_PHYS_BASE         (KIRKWOOD_REGS_PHYS_BASE + 0xA0000)
+#define AUDIO_VIRT_BASE         (KIRKWOOD_REGS_VIRT_BASE + 0xA0000)
 
 /*
  * Supported devices and revisions.
diff --git a/arch/arm/mach-kirkwood/irq.c b/arch/arm/mach-kirkwood/irq.c
index 20149a7fd280..884703535a0a 100644
--- a/arch/arm/mach-kirkwood/irq.c
+++ b/arch/arm/mach-kirkwood/irq.c
@@ -10,6 +10,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
@@ -30,14 +31,14 @@ static int __initdata gpio1_irqs[4] = {
 
 void __init kirkwood_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
 
         /*
          * Initialize gpiolib for GPIOs 0-49.
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_LOW_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, GPIO_LOW_VIRT_BASE, 0,
                         IRQ_KIRKWOOD_GPIO_START, gpio0_irqs);
-        orion_gpio_init(NULL, 32, 18, (void __iomem *)GPIO_HIGH_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 32, 18, GPIO_HIGH_VIRT_BASE, 0,
                         IRQ_KIRKWOOD_GPIO_START + 32, gpio1_irqs);
 }
diff --git a/arch/arm/mach-kirkwood/pcie.c b/arch/arm/mach-kirkwood/pcie.c
index 532d8acb38f9..ec544918b12c 100644
--- a/arch/arm/mach-kirkwood/pcie.c
+++ b/arch/arm/mach-kirkwood/pcie.c
@@ -47,8 +47,8 @@ void kirkwood_enable_pcie(void)
 void kirkwood_pcie_id(u32 *dev, u32 *rev)
 {
         kirkwood_enable_pcie();
-        *dev = orion_pcie_dev_id((void __iomem *)PCIE_VIRT_BASE);
-        *rev = orion_pcie_rev((void __iomem *)PCIE_VIRT_BASE);
+        *dev = orion_pcie_dev_id(PCIE_VIRT_BASE);
+        *rev = orion_pcie_rev(PCIE_VIRT_BASE);
 }
 
 struct pcie_port {
@@ -133,7 +133,7 @@ static struct pci_ops pcie_ops = {
 
 static void __init pcie0_ioresources_init(struct pcie_port *pp)
 {
-        pp->base = (void __iomem *)PCIE_VIRT_BASE;
+        pp->base = PCIE_VIRT_BASE;
         pp->irq = IRQ_KIRKWOOD_PCIE;
 
         /*
@@ -147,7 +147,7 @@ static void __init pcie0_ioresources_init(struct pcie_port *pp)
 
 static void __init pcie1_ioresources_init(struct pcie_port *pp)
 {
-        pp->base = (void __iomem *)PCIE1_VIRT_BASE;
+        pp->base = PCIE1_VIRT_BASE;
         pp->irq = IRQ_KIRKWOOD_PCIE1;
 
         /*
@@ -255,11 +255,11 @@ static struct hw_pci kirkwood_pci __initdata = {
         .map_irq        = kirkwood_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int index, unsigned long base)
+static void __init add_pcie_port(int index, void __iomem *base)
 {
         printk(KERN_INFO "Kirkwood PCIe port %d: ", index);
 
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                 printk(KERN_INFO "link up\n");
                 pcie_port_map[num_pcie_ports++] = index;
         } else
diff --git a/arch/arm/mach-kirkwood/ts41x-setup.c b/arch/arm/mach-kirkwood/ts41x-setup.c
index 5bbca2680442..367a9400f532 100644
--- a/arch/arm/mach-kirkwood/ts41x-setup.c
+++ b/arch/arm/mach-kirkwood/ts41x-setup.c
@@ -20,6 +20,7 @@
 #include <linux/gpio.h>
 #include <linux/gpio_keys.h>
 #include <linux/input.h>
+#include <linux/io.h>
 #include <asm/mach-types.h>
 #include <asm/mach/arch.h>
 #include <mach/kirkwood.h>
@@ -161,7 +162,7 @@ static int __init ts41x_pci_init(void)
                  * (Marvell 88sx7042/sata_mv) is known to stop working
                  * after a few minutes.
                  */
-                orion_pcie_reset((void __iomem *)PCIE_VIRT_BASE);
+                orion_pcie_reset(PCIE_VIRT_BASE);
 
                 kirkwood_pcie_id(&dev, &rev);
                 if (dev == MV88F6282_DEV_ID)
diff --git a/arch/arm/mach-mv78xx0/addr-map.c b/arch/arm/mach-mv78xx0/addr-map.c
index 137e479d15a0..343c435b4176 100644
--- a/arch/arm/mach-mv78xx0/addr-map.c
+++ b/arch/arm/mach-mv78xx0/addr-map.c
@@ -48,7 +48,7 @@ static void __init __iomem *win_cfg_base(const struct orion_addr_map_cfg *cfg, i
          * so we don't need to take that into account here.
          */
 
-        return (void __iomem *)((win < 8) ? WIN0_OFF(win) : WIN8_OFF(win));
+        return (win < 8) ? WIN0_OFF(win) : WIN8_OFF(win);
 }
 
 /*
@@ -72,10 +72,10 @@ void __init mv78xx0_setup_cpu_mbus(void)
          */
         if (mv78xx0_core_index() == 0)
                 orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            DDR_WINDOW_CPU0_BASE);
+                                            (void __iomem *) DDR_WINDOW_CPU0_BASE);
         else
                 orion_setup_cpu_mbus_target(&addr_map_cfg,
-                                            DDR_WINDOW_CPU1_BASE);
+                                            (void __iomem *) DDR_WINDOW_CPU1_BASE);
 }
 
 void __init mv78xx0_setup_pcie_io_win(int window, u32 base, u32 size,
diff --git a/arch/arm/mach-mv78xx0/common.c b/arch/arm/mach-mv78xx0/common.c
index a6f3cd21e8c2..131cd4883f3d 100644
--- a/arch/arm/mach-mv78xx0/common.c
+++ b/arch/arm/mach-mv78xx0/common.c
@@ -130,12 +130,12 @@ static int get_tclk(void)
  ****************************************************************************/
 static struct map_desc mv78xx0_io_desc[] __initdata = {
         {
-                .virtual        = MV78XX0_CORE_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) MV78XX0_CORE_REGS_VIRT_BASE,
                 .pfn            = 0,
                 .length         = MV78XX0_CORE_REGS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = MV78XX0_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) MV78XX0_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
                 .length         = MV78XX0_REGS_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
index eb187e0e059b..5f03484584d4 100644
--- a/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
+++ b/arch/arm/mach-mv78xx0/include/mach/bridge-regs.h
@@ -11,18 +11,18 @@
 
 #include <mach/mv78xx0.h>
 
-#define CPU_CONTROL             (BRIDGE_VIRT_BASE | 0x0104)
+#define CPU_CONTROL             (BRIDGE_VIRT_BASE + 0x0104)
 #define L2_WRITETHROUGH         0x00020000
 
-#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE | 0x0108)
+#define RSTOUTn_MASK            (BRIDGE_VIRT_BASE + 0x0108)
 #define SOFT_RESET_OUT_EN       0x00000004
 
-#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE | 0x010c)
+#define SYSTEM_SOFT_RESET       (BRIDGE_VIRT_BASE + 0x010c)
 #define SOFT_RESET              0x00000001
 
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
-#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE | 0x0200)
+#define IRQ_VIRT_BASE           (BRIDGE_VIRT_BASE + 0x0200)
 #define IRQ_CAUSE_ERR_OFF       0x0000
 #define IRQ_CAUSE_LOW_OFF       0x0004
 #define IRQ_CAUSE_HIGH_OFF      0x0008
@@ -30,7 +30,7 @@
 #define IRQ_MASK_LOW_OFF        0x0010
 #define IRQ_MASK_HIGH_OFF       0x0014
 
-#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE | 0x0300)
-#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE | 0x0300)
+#define TIMER_VIRT_BASE         (BRIDGE_VIRT_BASE + 0x0300)
+#define TIMER_PHYS_BASE         (BRIDGE_PHYS_BASE + 0x0300)
 
 #endif
diff --git a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
index bd03fed1128e..46200a183cf2 100644
--- a/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
+++ b/arch/arm/mach-mv78xx0/include/mach/mv78xx0.h
@@ -41,7 +41,7 @@
  */
 #define MV78XX0_CORE0_REGS_PHYS_BASE    0xf1020000
 #define MV78XX0_CORE1_REGS_PHYS_BASE    0xf1024000
-#define MV78XX0_CORE_REGS_VIRT_BASE     0xfe400000
+#define MV78XX0_CORE_REGS_VIRT_BASE     IOMEM(0xfe400000)
 #define MV78XX0_CORE_REGS_PHYS_BASE     0xfe400000
 #define MV78XX0_CORE_REGS_SIZE          SZ_16K
 
@@ -49,7 +49,7 @@
 #define MV78XX0_PCIE_IO_SIZE            SZ_1M
 
 #define MV78XX0_REGS_PHYS_BASE          0xf1000000
-#define MV78XX0_REGS_VIRT_BASE          0xfd000000
+#define MV78XX0_REGS_VIRT_BASE          IOMEM(0xfd000000)
 #define MV78XX0_REGS_SIZE               SZ_1M
 
 #define MV78XX0_PCIE_MEM_PHYS_BASE      0xc0000000
@@ -64,47 +64,47 @@
 /*
  * Register Map
  */
-#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE | 0x00000)
-#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE | 0x1500)
-#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE | 0x1570)
-
-#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE | 0x10000)
-#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE | 0x10000)
-#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE | 0x0030)
-#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE | 0x0034)
-#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE | 0x0100)
-#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1000)
-#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x1100)
-#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2100)
-#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2200)
-#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2200)
-#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE | 0x2300)
-#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE | 0x2300)
-
-#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x30000)
-#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x34000)
-
-#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x40000)
-#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x44000)
-#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x48000)
-#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x4c000)
-
-#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x50000)
-#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x51000)
-#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x52000)
-
-#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x70000)
-#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0x74000)
-
-#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x80000)
-#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x84000)
-#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x88000)
-#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE | 0x8c000)
-
-#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE | 0xa0000)
+#define DDR_VIRT_BASE           (MV78XX0_REGS_VIRT_BASE + 0x00000)
+#define  DDR_WINDOW_CPU0_BASE   (DDR_VIRT_BASE + 0x1500)
+#define  DDR_WINDOW_CPU1_BASE   (DDR_VIRT_BASE + 0x1570)
+
+#define DEV_BUS_PHYS_BASE       (MV78XX0_REGS_PHYS_BASE + 0x10000)
+#define DEV_BUS_VIRT_BASE       (MV78XX0_REGS_VIRT_BASE + 0x10000)
+#define  SAMPLE_AT_RESET_LOW    (DEV_BUS_VIRT_BASE + 0x0030)
+#define  SAMPLE_AT_RESET_HIGH   (DEV_BUS_VIRT_BASE + 0x0034)
+#define  GPIO_VIRT_BASE         (DEV_BUS_VIRT_BASE + 0x0100)
+#define  I2C_0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1000)
+#define  I2C_1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x1100)
+#define  UART0_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2100)
+#define  UART2_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2200)
+#define  UART2_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2200)
+#define  UART3_PHYS_BASE        (DEV_BUS_PHYS_BASE + 0x2300)
+#define  UART3_VIRT_BASE        (DEV_BUS_VIRT_BASE + 0x2300)
+
+#define GE10_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x30000)
+#define GE11_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x34000)
+
+#define PCIE00_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x40000)
+#define PCIE01_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x44000)
+#define PCIE02_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x48000)
+#define PCIE03_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x4c000)
+
+#define USB0_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x50000)
+#define USB1_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x51000)
+#define USB2_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x52000)
+
+#define GE00_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x70000)
+#define GE01_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0x74000)
+
+#define PCIE10_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x80000)
+#define PCIE11_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x84000)
+#define PCIE12_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x88000)
+#define PCIE13_VIRT_BASE        (MV78XX0_REGS_VIRT_BASE + 0x8c000)
+
+#define SATA_PHYS_BASE          (MV78XX0_REGS_PHYS_BASE + 0xa0000)
 
 /*
  * Supported devices and revisions.
diff --git a/arch/arm/mach-mv78xx0/irq.c b/arch/arm/mach-mv78xx0/irq.c
index 4d720f2aedba..32073444024b 100644
--- a/arch/arm/mach-mv78xx0/irq.c
+++ b/arch/arm/mach-mv78xx0/irq.c
@@ -10,6 +10,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
@@ -24,16 +25,16 @@ static int __initdata gpio0_irqs[4] = {
 
 void __init mv78xx0_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF));
-        orion_irq_init(32, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF));
-        orion_irq_init(64, (void __iomem *)(IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF));
+        orion_irq_init(0, IRQ_VIRT_BASE + IRQ_MASK_LOW_OFF);
+        orion_irq_init(32, IRQ_VIRT_BASE + IRQ_MASK_HIGH_OFF);
+        orion_irq_init(64, IRQ_VIRT_BASE + IRQ_MASK_ERR_OFF);
 
         /*
          * Initialize gpiolib for GPIOs 0-31.  (The GPIO interrupt mask
          * registers for core #1 are at an offset of 0x18 from those of
          * core #0.)
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE,
+        orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE,
                         mv78xx0_core_index() ? 0x18 : 0,
                         IRQ_MV78XX0_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-mv78xx0/pcie.c b/arch/arm/mach-mv78xx0/pcie.c
index 26a059b4f472..a9a154a646dd 100644
--- a/arch/arm/mach-mv78xx0/pcie.c
+++ b/arch/arm/mach-mv78xx0/pcie.c
@@ -34,8 +34,8 @@ static struct resource pcie_io_space;
 
 void __init mv78xx0_pcie_id(u32 *dev, u32 *rev)
 {
-        *dev = orion_pcie_dev_id((void __iomem *)PCIE00_VIRT_BASE);
-        *rev = orion_pcie_rev((void __iomem *)PCIE00_VIRT_BASE);
+        *dev = orion_pcie_dev_id(PCIE00_VIRT_BASE);
+        *rev = orion_pcie_rev(PCIE00_VIRT_BASE);
 }
 
 u32 pcie_port_size[8] = {
@@ -223,11 +223,11 @@ static struct hw_pci mv78xx0_pci __initdata = {
         .map_irq        = mv78xx0_pcie_map_irq,
 };
 
-static void __init add_pcie_port(int maj, int min, unsigned long base)
+static void __init add_pcie_port(int maj, int min, void __iomem *base)
 {
         printk(KERN_INFO "MV78xx0 PCIe port %d.%d: ", maj, min);
 
-        if (orion_pcie_link_up((void __iomem *)base)) {
+        if (orion_pcie_link_up(base)) {
                 struct pcie_port *pp = &pcie_port[num_pcie_ports++];
 
                 printk("link up\n");
@@ -235,7 +235,7 @@ static void __init add_pcie_port(int maj, int min, unsigned long base)
                 pp->maj = maj;
                 pp->min = min;
                 pp->root_bus_nr = -1;
-                pp->base = (void __iomem *)base;
+                pp->base = base;
                 spin_lock_init(&pp->conf_lock);
                 memset(&pp->res, 0, sizeof(pp->res));
         } else {
@@ -249,7 +249,7 @@ void __init mv78xx0_pcie_init(int init_port0, int init_port1)
 
         if (init_port0) {
                 add_pcie_port(0, 0, PCIE00_VIRT_BASE);
-                if (!orion_pcie_x4_mode((void __iomem *)PCIE00_VIRT_BASE)) {
+                if (!orion_pcie_x4_mode(PCIE00_VIRT_BASE)) {
                         add_pcie_port(0, 1, PCIE01_VIRT_BASE);
                         add_pcie_port(0, 2, PCIE02_VIRT_BASE);
                         add_pcie_port(0, 3, PCIE03_VIRT_BASE);
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index 7b270358536e..416d46ef7ebd 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -6,6 +6,8 @@ config ARCH_MVEBU
         select GENERIC_IRQ_CHIP
         select IRQ_DOMAIN
         select MULTI_IRQ_HANDLER
+        select PINCTRL
+        select PLAT_ORION
         select SPARSE_IRQ
 
 if ARCH_MVEBU
@@ -13,13 +15,25 @@ if ARCH_MVEBU
 menu "Marvell SOC with device tree"
 
 config MACH_ARMADA_370_XP
-        bool "Marvell Armada 370 and Aramada XP boards"
+        bool
         select ARMADA_370_XP_TIMER
         select CPU_V7
+
+config MACH_ARMADA_370
+        bool "Marvell Armada 370 boards"
+        select MACH_ARMADA_370_XP
+        select PINCTRL_ARMADA_370
         help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada 370 SoC with device tree.
 
-          Say 'Y' here if you want your kernel to support boards based on
-          Marvell Armada 370 or Armada XP with device tree.
+config MACH_ARMADA_XP
+        bool "Marvell Armada XP boards"
+        select MACH_ARMADA_370_XP
+        select PINCTRL_ARMADA_XP
+        help
+          Say 'Y' here if you want your kernel to support boards based
+          on the Marvell Armada XP SoC with device tree.
 
 endmenu
 
diff --git a/arch/arm/mach-mvebu/Makefile b/arch/arm/mach-mvebu/Makefile
index 6ea8998ab8f1..57f996b6aa0e 100644
--- a/arch/arm/mach-mvebu/Makefile
+++ b/arch/arm/mach-mvebu/Makefile
@@ -1,4 +1,5 @@
-ccflags-$(ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include \
+        -I$(srctree)/arch/arm/plat-orion/include
 
 obj-y += system-controller.o
-obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o
+obj-$(CONFIG_MACH_ARMADA_370_XP) += armada-370-xp.o irq-armada-370-xp.o addr-map.o
diff --git a/arch/arm/mach-mvebu/addr-map.c b/arch/arm/mach-mvebu/addr-map.c
new file mode 100644
index 000000000000..fe454a4430be
--- /dev/null
+++ b/arch/arm/mach-mvebu/addr-map.c
@@ -0,0 +1,134 @@
+/*
+ * Address map functions for Marvell 370 / XP SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mbus.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <plat/addr-map.h>
+
+/*
+ * Generic Address Decode Windows bit settings
+ */
+#define ARMADA_XP_TARGET_DEV_BUS        1
+#define   ARMADA_XP_ATTR_DEV_BOOTROM    0x1D
+#define ARMADA_XP_TARGET_ETH1           3
+#define ARMADA_XP_TARGET_PCIE_0_2       4
+#define ARMADA_XP_TARGET_ETH0           7
+#define ARMADA_XP_TARGET_PCIE_1_3       8
+
+#define ARMADA_370_TARGET_DEV_BUS       1
+#define   ARMADA_370_ATTR_DEV_BOOTROM   0x1D
+#define ARMADA_370_TARGET_PCIE_0        4
+#define ARMADA_370_TARGET_PCIE_1        8
+
+#define ARMADA_WINDOW_8_PLUS_OFFSET       0x90
+#define ARMADA_SDRAM_ADDR_DECODING_OFFSET 0x180
+
+static const struct __initdata orion_addr_map_info
+armada_xp_addr_map_info[] = {
+        /*
+         * Window for the BootROM, needed for SMP on Armada XP
+         */
+        { 0, 0xfff00000, SZ_1M, ARMADA_XP_TARGET_DEV_BUS,
+          ARMADA_XP_ATTR_DEV_BOOTROM, -1 },
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 },
+};
+
+static const struct __initdata orion_addr_map_info
+armada_370_addr_map_info[] = {
+        /* End marker */
+        { -1, 0, 0, 0, 0, 0 },
+};
+
+static struct of_device_id of_addr_decoding_controller_table[] = {
+        { .compatible = "marvell,armada-addr-decoding-controller" },
+        { /* end of list */ },
+};
+
+static void __iomem *
+armada_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
+{
+        unsigned int offset;
+
+        /* The register layout is a bit annoying and the below code
+         * tries to cope with it.
+         * - At offset 0x0, there are the registers for the first 8
+         *   windows, with 4 registers of 32 bits per window (ctrl,
+         *   base, remap low, remap high)
+         * - Then at offset 0x80, there is a hole of 0x10 bytes for
+         *   the internal registers base address and internal units
+         *   sync barrier register.
+         * - Then at offset 0x90, there the registers for 12
+         *   windows, with only 2 registers of 32 bits per window
+         *   (ctrl, base).
+         */
+        if (win < 8)
+                offset = (win << 4);
+        else
+                offset = ARMADA_WINDOW_8_PLUS_OFFSET + (win << 3);
+
+        return cfg->bridge_virt_base + offset;
+}
+
+static struct __initdata orion_addr_map_cfg addr_map_cfg = {
+        .num_wins = 20,
+        .remappable_wins = 8,
+        .win_cfg_base = armada_cfg_base,
+};
+
+static int __init armada_setup_cpu_mbus(void)
+{
+        struct device_node *np;
+        void __iomem *mbus_unit_addr_decoding_base;
+        void __iomem *sdram_addr_decoding_base;
+
+        np = of_find_matching_node(NULL, of_addr_decoding_controller_table);
+        if (!np)
+                return -ENODEV;
+
+        mbus_unit_addr_decoding_base = of_iomap(np, 0);
+        BUG_ON(!mbus_unit_addr_decoding_base);
+
+        sdram_addr_decoding_base =
+                mbus_unit_addr_decoding_base +
+                ARMADA_SDRAM_ADDR_DECODING_OFFSET;
+
+        addr_map_cfg.bridge_virt_base = mbus_unit_addr_decoding_base;
+
+        /*
+         * Disable, clear and configure windows.
+         */
+        if (of_machine_is_compatible("marvell,armadaxp"))
+                orion_config_wins(&addr_map_cfg, armada_xp_addr_map_info);
+        else if (of_machine_is_compatible("marvell,armada370"))
+                orion_config_wins(&addr_map_cfg, armada_370_addr_map_info);
+        else {
+                pr_err("Unsupported SoC\n");
+                return -EINVAL;
+        }
+
+        /*
+         * Setup MBUS dram target info.
+         */
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    sdram_addr_decoding_base);
+        return 0;
+}
+
+/* Using a early_initcall is needed so that this initialization gets
+ * done before the SMP initialization, which requires the BootROM to
+ * be remapped. */
+early_initcall(armada_setup_cpu_mbus);
diff --git a/arch/arm/mach-mvebu/armada-370-xp.c b/arch/arm/mach-mvebu/armada-370-xp.c
index b46418a8b352..49d791548ad6 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.c
+++ b/arch/arm/mach-mvebu/armada-370-xp.c
@@ -25,7 +25,7 @@
 
 static struct map_desc armada_370_xp_io_desc[] __initdata = {
         {
-                .virtual        = ARMADA_370_XP_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) ARMADA_370_XP_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ARMADA_370_XP_REGS_PHYS_BASE),
                 .length         = ARMADA_370_XP_REGS_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-mvebu/armada-370-xp.h b/arch/arm/mach-mvebu/armada-370-xp.h
index 25f0ca8d7820..aac9bebc6b03 100644
--- a/arch/arm/mach-mvebu/armada-370-xp.h
+++ b/arch/arm/mach-mvebu/armada-370-xp.h
@@ -16,7 +16,7 @@
 #define __MACH_ARMADA_370_XP_H
 
 #define ARMADA_370_XP_REGS_PHYS_BASE    0xd0000000
-#define ARMADA_370_XP_REGS_VIRT_BASE    0xfeb00000
+#define ARMADA_370_XP_REGS_VIRT_BASE    IOMEM(0xfeb00000)
 #define ARMADA_370_XP_REGS_SIZE         SZ_1M
 
 #endif /* __MACH_ARMADA_370_XP_H */
diff --git a/arch/arm/mach-mvebu/include/mach/gpio.h b/arch/arm/mach-mvebu/include/mach/gpio.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/arch/arm/mach-mvebu/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-omap1/devices.c b/arch/arm/mach-omap1/devices.c
index 0cc54dd553e3..726c02c9c0cd 100644
--- a/arch/arm/mach-omap1/devices.c
+++ b/arch/arm/mach-omap1/devices.c
@@ -357,6 +357,33 @@ static inline void omap_init_uwire(void) {}
 #endif
 
 
+#define OMAP1_RNG_BASE          0xfffe5000
+
+static struct resource omap1_rng_resources[] = {
+        {
+                .start          = OMAP1_RNG_BASE,
+                .end            = OMAP1_RNG_BASE + 0x4f,
+                .flags          = IORESOURCE_MEM,
+        },
+};
+
+static struct platform_device omap1_rng_device = {
+        .name           = "omap_rng",
+        .id             = -1,
+        .num_resources  = ARRAY_SIZE(omap1_rng_resources),
+        .resource       = omap1_rng_resources,
+};
+
+static void omap1_init_rng(void)
+{
+        if (!cpu_is_omap16xx())
+                return;
+
+        (void) platform_device_register(&omap1_rng_device);
+}
+
+/*-------------------------------------------------------------------------*/
+
 /*
  * This gets called after board-specific INIT_MACHINE, and initializes most
  * on-chip peripherals accessible on this board (except for few like USB):
@@ -395,6 +422,7 @@ static int __init omap1_init_devices(void)
         omap_init_spi100k();
         omap_init_sti();
         omap_init_uwire();
+        omap1_init_rng();
 
         return 0;
 }
diff --git a/arch/arm/mach-omap1/timer.c b/arch/arm/mach-omap1/timer.c
index aa81593db1af..cdeb9d3ef640 100644
--- a/arch/arm/mach-omap1/timer.c
+++ b/arch/arm/mach-omap1/timer.c
@@ -141,7 +141,7 @@ static int __init omap1_dm_timer_init(void)
 
                 pdata->set_timer_src = omap1_dm_timer_set_src;
                 pdata->timer_capability = OMAP_TIMER_ALWON |
-                                OMAP_TIMER_NEEDS_RESET;
+                                OMAP_TIMER_NEEDS_RESET | OMAP_TIMER_HAS_DSP_IRQ;
 
                 ret = platform_device_add_data(pdev, pdata, sizeof(*pdata));
                 if (ret) {
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 7d6abda3b74e..fe40d9e488c9 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -179,6 +179,7 @@ obj-$(CONFIG_ARCH_OMAP4)		+= omap_hwmod_44xx_data.o
 
 # EMU peripherals
 obj-$(CONFIG_OMAP3_EMU)                 += emu.o
+obj-$(CONFIG_HW_PERF_EVENTS)            += pmu.o
 
 obj-$(CONFIG_OMAP_MBOX_FWK)             += mailbox_mach.o
 mailbox_mach-objs                       := mailbox.o
diff --git a/arch/arm/mach-omap2/board-apollon.c b/arch/arm/mach-omap2/board-apollon.c
index 3e2d76f05af4..cea3abace815 100644
--- a/arch/arm/mach-omap2/board-apollon.c
+++ b/arch/arm/mach-omap2/board-apollon.c
@@ -202,7 +202,7 @@ static inline void __init apollon_init_smc91x(void)
                 return;
         }
 
-        clk_enable(gpmc_fck);
+        clk_prepare_enable(gpmc_fck);
         rate = clk_get_rate(gpmc_fck);
 
         eth_cs = APOLLON_ETH_CS;
@@ -246,7 +246,7 @@ static inline void __init apollon_init_smc91x(void)
                 gpmc_cs_free(APOLLON_ETH_CS);
         }
 out:
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
         clk_put(gpmc_fck);
 }
 
diff --git a/arch/arm/mach-omap2/board-h4.c b/arch/arm/mach-omap2/board-h4.c
index f6c48dd764fe..8d04bf851af4 100644
--- a/arch/arm/mach-omap2/board-h4.c
+++ b/arch/arm/mach-omap2/board-h4.c
@@ -265,9 +265,9 @@ static inline void __init h4_init_debug(void)
                 return;
         }
 
-        clk_enable(gpmc_fck);
+        clk_prepare_enable(gpmc_fck);
         rate = clk_get_rate(gpmc_fck);
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
         clk_put(gpmc_fck);
 
         if (is_gpmc_muxed())
@@ -311,7 +311,7 @@ static inline void __init h4_init_debug(void)
                 gpmc_cs_free(eth_cs);
 
 out:
-        clk_disable(gpmc_fck);
+        clk_disable_unprepare(gpmc_fck);
         clk_put(gpmc_fck);
 }
 
diff --git a/arch/arm/mach-omap2/board-omap4panda.c b/arch/arm/mach-omap2/board-omap4panda.c
index e0dd70b9d917..2b012f9d6925 100644
--- a/arch/arm/mach-omap2/board-omap4panda.c
+++ b/arch/arm/mach-omap2/board-omap4panda.c
@@ -171,7 +171,7 @@ static void __init omap4_ehci_init(void)
                 return;
         }
         clk_set_rate(phy_ref_clk, 19200000);
-        clk_enable(phy_ref_clk);
+        clk_prepare_enable(phy_ref_clk);
 
         /* disable the power to the usb hub prior to init and reset phy+hub */
         ret = gpio_request_array(panda_ehci_gpios,
diff --git a/arch/arm/mach-omap2/clkt2xxx_apll.c b/arch/arm/mach-omap2/clkt2xxx_apll.c
index b19a1f7234ae..c2d15212d64d 100644
--- a/arch/arm/mach-omap2/clkt2xxx_apll.c
+++ b/arch/arm/mach-omap2/clkt2xxx_apll.c
@@ -59,7 +59,7 @@ static int omap2_clk_apll_enable(struct clk *clk, u32 status_mask)
         omap2_cm_write_mod_reg(cval, PLL_MOD, CM_CLKEN);
 
         omap2_cm_wait_idlest(cm_idlest_pll, status_mask,
-                             OMAP24XX_CM_IDLEST_VAL, clk->name);
+                             OMAP24XX_CM_IDLEST_VAL, __clk_get_name(clk));
 
         /*
          * REVISIT: Should we return an error code if omap2_wait_clock_ready()
diff --git a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
index cabcfdba5246..3524f0e7b6d5 100644
--- a/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
+++ b/arch/arm/mach-omap2/clkt2xxx_virt_prcm_set.c
@@ -68,14 +68,15 @@ unsigned long omap2_table_mpu_recalc(struct clk *clk)
 long omap2_round_to_table_rate(struct clk *clk, unsigned long rate)
 {
         const struct prcm_config *ptr;
-        long highest_rate;
+        long highest_rate, sys_clk_rate;
 
         highest_rate = -EINVAL;
+        sys_clk_rate = __clk_get_rate(sclk);
 
         for (ptr = rate_table; ptr->mpu_speed; ptr++) {
                 if (!(ptr->flags & cpu_mask))
                         continue;
-                if (ptr->xtal_speed != sclk->rate)
+                if (ptr->xtal_speed != sys_clk_rate)
                         continue;
 
                 highest_rate = ptr->mpu_speed;
@@ -94,12 +95,15 @@ int omap2_select_table_rate(struct clk *clk, unsigned long rate)
         const struct prcm_config *prcm;
         unsigned long found_speed = 0;
         unsigned long flags;
+        long sys_clk_rate;
+
+        sys_clk_rate = __clk_get_rate(sclk);
 
         for (prcm = rate_table; prcm->mpu_speed; prcm++) {
                 if (!(prcm->flags & cpu_mask))
                         continue;
 
-                if (prcm->xtal_speed != sclk->rate)
+                if (prcm->xtal_speed != sys_clk_rate)
                         continue;
 
                 if (prcm->mpu_speed <= rate) {
diff --git a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
index 298887b5bf66..7c6da2f731dc 100644
--- a/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
+++ b/arch/arm/mach-omap2/clkt34xx_dpll3m2.c
@@ -56,6 +56,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         struct omap_sdrc_params *sdrc_cs0;
         struct omap_sdrc_params *sdrc_cs1;
         int ret;
+        unsigned long clkrate;
 
         if (!clk || !rate)
                 return -EINVAL;
@@ -64,11 +65,12 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         if (validrate != rate)
                 return -EINVAL;
 
-        sdrcrate = sdrc_ick_p->rate;
-        if (rate > clk->rate)
-                sdrcrate <<= ((rate / clk->rate) >> 1);
+        sdrcrate = __clk_get_rate(sdrc_ick_p);
+        clkrate = __clk_get_rate(clk);
+        if (rate > clkrate)
+                sdrcrate <<= ((rate / clkrate) >> 1);
         else
-                sdrcrate >>= ((clk->rate / rate) >> 1);
+                sdrcrate >>= ((clkrate / rate) >> 1);
 
         ret = omap2_sdrc_get_params(sdrcrate, &sdrc_cs0, &sdrc_cs1);
         if (ret)
@@ -82,7 +84,7 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         /*
          * XXX This only needs to be done when the CPU frequency changes
          */
-        _mpurate = arm_fck_p->rate / CYCLES_PER_MHZ;
+        _mpurate = __clk_get_rate(arm_fck_p) / CYCLES_PER_MHZ;
         c = (_mpurate << SDRC_MPURATE_SCALE) >> SDRC_MPURATE_BASE_SHIFT;
         c += 1;  /* for safety */
         c *= SDRC_MPURATE_LOOPS;
@@ -90,8 +92,8 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
         if (c == 0)
                 c = 1;
 
-        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n", clk->rate,
-                 validrate);
+        pr_debug("clock: changing CORE DPLL rate from %lu to %lu\n",
+                 clkrate, validrate);
         pr_debug("clock: SDRC CS0 timing params used: RFR %08x CTRLA %08x CTRLB %08x MR %08x\n",
                  sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                  sdrc_cs0->actim_ctrlb, sdrc_cs0->mr);
@@ -102,14 +104,14 @@ int omap3_core_dpll_m2_set_rate(struct clk *clk, unsigned long rate)
 
         if (sdrc_cs1)
                 omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  new_div, unlock_dll, c, rate > clkrate,
                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                   sdrc_cs1->rfr_ctrl, sdrc_cs1->actim_ctrla,
                                   sdrc_cs1->actim_ctrlb, sdrc_cs1->mr);
         else
                 omap3_configure_core_dpll(
-                                  new_div, unlock_dll, c, rate > clk->rate,
+                                  new_div, unlock_dll, c, rate > clkrate,
                                   sdrc_cs0->rfr_ctrl, sdrc_cs0->actim_ctrla,
                                   sdrc_cs0->actim_ctrlb, sdrc_cs0->mr,
                                   0, 0, 0, 0);
diff --git a/arch/arm/mach-omap2/clkt_clksel.c b/arch/arm/mach-omap2/clkt_clksel.c
index 19a980956d44..eaed3900a83c 100644
--- a/arch/arm/mach-omap2/clkt_clksel.c
+++ b/arch/arm/mach-omap2/clkt_clksel.c
@@ -72,7 +72,7 @@ static const struct clksel *_get_clksel_by_parent(struct clk *clk,
         if (!clks->parent) {
                 /* This indicates a data problem */
                 WARN(1, "clock: %s: could not find parent clock %s in clksel array\n",
-                     clk->name, src_clk->name);
+                     __clk_get_name(clk), __clk_get_name(src_clk));
                 return NULL;
         }
 
@@ -127,7 +127,8 @@ static u8 _get_div_and_fieldval(struct clk *src_clk, struct clk *clk,
         if (max_div == 0) {
                 /* This indicates an error in the clksel data */
                 WARN(1, "clock: %s: could not find divisor for parent %s\n",
-                     clk->name, src_clk->parent->name);
+                     __clk_get_name(clk),
+                     __clk_get_name(__clk_get_parent(src_clk)));
                 return 0;
         }
 
@@ -176,8 +177,10 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 {
         const struct clksel *clks;
         const struct clksel_rate *clkr;
+        struct clk *parent;
 
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        parent = __clk_get_parent(clk);
+        clks = _get_clksel_by_parent(clk, parent);
         if (!clks)
                 return 0;
 
@@ -191,8 +194,8 @@ static u32 _clksel_to_divisor(struct clk *clk, u32 field_val)
 
         if (!clkr->div) {
                 /* This indicates a data error */
-                WARN(1, "clock: %s: could not find fieldval %d parent %s\n",
-                     clk->name, field_val, clk->parent->name);
+                WARN(1, "clock: %s: could not find fieldval %d for parent %s\n",
+                     __clk_get_name(clk), field_val, __clk_get_name(parent));
                 return 0;
         }
 
@@ -213,11 +216,13 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
 {
         const struct clksel *clks;
         const struct clksel_rate *clkr;
+        struct clk *parent;
 
         /* should never happen */
         WARN_ON(div == 0);
 
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        parent = __clk_get_parent(clk);
+        clks = _get_clksel_by_parent(clk, parent);
         if (!clks)
                 return ~0;
 
@@ -230,8 +235,8 @@ static u32 _divisor_to_clksel(struct clk *clk, u32 div)
         }
 
         if (!clkr->div) {
-                pr_err("clock: %s: could not find divisor %d parent %s\n",
-                       clk->name, div, clk->parent->name);
+                pr_err("clock: %s: could not find divisor %d for parent %s\n",
+                       __clk_get_name(clk), div, __clk_get_name(parent));
                 return ~0;
         }
 
@@ -281,16 +286,23 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
         const struct clksel *clks;
         const struct clksel_rate *clkr;
         u32 last_div = 0;
+        struct clk *parent;
+        unsigned long parent_rate;
+        const char *clk_name;
+
+        parent = __clk_get_parent(clk);
+        parent_rate = __clk_get_rate(parent);
+        clk_name = __clk_get_name(clk);
 
         if (!clk->clksel || !clk->clksel_mask)
                 return ~0;
 
         pr_debug("clock: clksel_round_rate_div: %s target_rate %ld\n",
-                 clk->name, target_rate);
+                 clk_name, target_rate);
 
         *new_div = 1;
 
-        clks = _get_clksel_by_parent(clk, clk->parent);
+        clks = _get_clksel_by_parent(clk, parent);
         if (!clks)
                 return ~0;
 
@@ -300,29 +312,29 @@ u32 omap2_clksel_round_rate_div(struct clk *clk, unsigned long target_rate,
 
                 /* Sanity check */
                 if (clkr->div <= last_div)
-                        pr_err("clock: %s: clksel_rate table not sorted",
-                               clk->name);
+                        pr_err("clock: %s: clksel_rate table not sorted\n",
+                               clk_name);
 
                 last_div = clkr->div;
 
-                test_rate = clk->parent->rate / clkr->div;
+                test_rate = parent_rate / clkr->div;
 
                 if (test_rate <= target_rate)
                         break; /* found it */
         }
 
         if (!clkr->div) {
-                pr_err("clock: %s: could not find divisor for target rate %ld parent %s\n",
-                       clk->name, target_rate, clk->parent->name);
+                pr_err("clock: %s: could not find divisor for target rate %ld for parent %s\n",
+                       clk_name, target_rate, __clk_get_name(parent));
                 return ~0;
         }
 
         *new_div = clkr->div;
 
         pr_debug("clock: new_div = %d, new_rate = %ld\n", *new_div,
-                 (clk->parent->rate / clkr->div));
+                 (parent_rate / clkr->div));
 
-        return clk->parent->rate / clkr->div;
+        return parent_rate / clkr->div;
 }
 
 /*
@@ -344,10 +356,15 @@ void omap2_init_clksel_parent(struct clk *clk)
         const struct clksel *clks;
         const struct clksel_rate *clkr;
         u32 r, found = 0;
+        struct clk *parent;
+        const char *clk_name;
 
         if (!clk->clksel || !clk->clksel_mask)
                 return;
 
+        parent = __clk_get_parent(clk);
+        clk_name = __clk_get_name(clk);
+
         r = __raw_readl(clk->clksel_reg) & clk->clksel_mask;
         r >>= __ffs(clk->clksel_mask);
 
@@ -357,11 +374,13 @@ void omap2_init_clksel_parent(struct clk *clk)
                                 continue;
 
                         if (clkr->val == r) {
-                                if (clk->parent != clks->parent) {
+                                if (parent != clks->parent) {
                                         pr_debug("clock: %s: inited parent to %s (was %s)\n",
-                                                 clk->name, clks->parent->name,
-                                                 ((clk->parent) ?
-                                                  clk->parent->name : "NULL"));
+                                                 clk_name,
+                                                 __clk_get_name(clks->parent),
+                                                 ((parent) ?
+                                                  __clk_get_name(parent) :
+                                                 "NULL"));
                                         clk_reparent(clk, clks->parent);
                                 };
                                 found = 1;
@@ -371,7 +390,7 @@ void omap2_init_clksel_parent(struct clk *clk)
 
         /* This indicates a data error */
         WARN(!found, "clock: %s: init parent: could not find regval %0x\n",
-             clk->name, r);
+             clk_name, r);
 
         return;
 }
@@ -389,15 +408,17 @@ unsigned long omap2_clksel_recalc(struct clk *clk)
 {
         unsigned long rate;
         u32 div = 0;
+        struct clk *parent;
 
         div = _read_divisor(clk);
         if (div == 0)
-                return clk->rate;
+                return __clk_get_rate(clk);
 
-        rate = clk->parent->rate / div;
+        parent = __clk_get_parent(clk);
+        rate = __clk_get_rate(parent) / div;
 
-        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n", clk->name,
-                 rate, div);
+        pr_debug("clock: %s: recalc'd rate is %ld (div %d)\n",
+                 __clk_get_name(clk), rate, div);
 
         return rate;
 }
@@ -452,9 +473,10 @@ int omap2_clksel_set_rate(struct clk *clk, unsigned long rate)
 
         _write_clksel_reg(clk, field_val);
 
-        clk->rate = clk->parent->rate / new_div;
+        clk->rate = __clk_get_rate(__clk_get_parent(clk)) / new_div;
 
-        pr_debug("clock: %s: set rate to %ld\n", clk->name, clk->rate);
+        pr_debug("clock: %s: set rate to %ld\n", __clk_get_name(clk),
+                 __clk_get_rate(clk));
 
         return 0;
 }
@@ -496,13 +518,15 @@ int omap2_clksel_set_parent(struct clk *clk, struct clk *new_parent)
         clk_reparent(clk, new_parent);
 
         /* CLKSEL clocks follow their parents' rates, divided by a divisor */
-        clk->rate = new_parent->rate;
+        clk->rate = __clk_get_rate(new_parent);
 
         if (parent_div > 0)
-                clk->rate /= parent_div;
+                __clk_get_rate(clk) /= parent_div;
 
         pr_debug("clock: %s: set parent to %s (new rate %ld)\n",
-                 clk->name, clk->parent->name, clk->rate);
+                 __clk_get_name(clk),
+                 __clk_get_name(__clk_get_parent(clk)),
+                 __clk_get_rate(clk));
 
         return 0;
 }
diff --git a/arch/arm/mach-omap2/clkt_dpll.c b/arch/arm/mach-omap2/clkt_dpll.c
index 83b658bf385a..80411142f482 100644
--- a/arch/arm/mach-omap2/clkt_dpll.c
+++ b/arch/arm/mach-omap2/clkt_dpll.c
@@ -87,7 +87,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
         dd = clk->dpll_data;
 
         /* DPLL divider must result in a valid jitter correction val */
-        fint = clk->parent->rate / n;
+        fint = __clk_get_rate(__clk_get_parent(clk)) / n;
 
         if (cpu_is_omap24xx()) {
                 /* Should not be called for OMAP2, so warn if it is called */
@@ -252,16 +252,16 @@ u32 omap2_get_dpll_rate(struct clk *clk)
         if (cpu_is_omap24xx()) {
                 if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP2XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
         } else if (cpu_is_omap34xx()) {
                 if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP3XXX_EN_DPLL_FRBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
         } else if (soc_is_am33xx() || cpu_is_omap44xx()) {
                 if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
                     v == OMAP4XXX_EN_DPLL_FRBYPASS ||
                     v == OMAP4XXX_EN_DPLL_MNBYPASS)
-                        return dd->clk_bypass->rate;
+                        return __clk_get_rate(dd->clk_bypass);
         }
 
         v = __raw_readl(dd->mult_div1_reg);
@@ -270,7 +270,7 @@ u32 omap2_get_dpll_rate(struct clk *clk)
         dpll_div = v & dd->div1_mask;
         dpll_div >>= __ffs(dd->div1_mask);
 
-        dpll_clk = (long long)dd->clk_ref->rate * dpll_mult;
+        dpll_clk = (long long) __clk_get_rate(dd->clk_ref) * dpll_mult;
         do_div(dpll_clk, dpll_div + 1);
 
         return dpll_clk;
@@ -296,16 +296,20 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
         unsigned long scaled_rt_rp;
         unsigned long new_rate = 0;
         struct dpll_data *dd;
+        unsigned long ref_rate;
+        const char *clk_name;
 
         if (!clk || !clk->dpll_data)
                 return ~0;
 
         dd = clk->dpll_data;
 
+        ref_rate = __clk_get_rate(dd->clk_ref);
+        clk_name = __clk_get_name(clk);
         pr_debug("clock: %s: starting DPLL round_rate, target rate %ld\n",
-                 clk->name, target_rate);
+                 clk_name, target_rate);
 
-        scaled_rt_rp = target_rate / (dd->clk_ref->rate / DPLL_SCALE_FACTOR);
+        scaled_rt_rp = target_rate / (ref_rate / DPLL_SCALE_FACTOR);
         scaled_max_m = dd->max_multiplier * DPLL_SCALE_FACTOR;
 
         dd->last_rounded_rate = 0;
@@ -332,14 +336,14 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
                         break;
 
                 r = _dpll_test_mult(&m, n, &new_rate, target_rate,
-                                    dd->clk_ref->rate);
+                                    ref_rate);
 
                 /* m can't be set low enough for this n - try with a larger n */
                 if (r == DPLL_MULT_UNDERFLOW)
                         continue;
 
                 pr_debug("clock: %s: m = %d: n = %d: new_rate = %ld\n",
-                         clk->name, m, n, new_rate);
+                         clk_name, m, n, new_rate);
 
                 if (target_rate == new_rate) {
                         dd->last_rounded_m = m;
@@ -350,8 +354,8 @@ long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate)
         }
 
         if (target_rate != new_rate) {
-                pr_debug("clock: %s: cannot round to rate %ld\n", clk->name,
-                         target_rate);
+                pr_debug("clock: %s: cannot round to rate %ld\n",
+                         clk_name, target_rate);
                 return ~0;
         }
 
diff --git a/arch/arm/mach-omap2/clock.c b/arch/arm/mach-omap2/clock.c
index e97f98ffe8b2..961ac8f7e13d 100644
--- a/arch/arm/mach-omap2/clock.c
+++ b/arch/arm/mach-omap2/clock.c
@@ -78,7 +78,7 @@ static void _omap2_module_wait_ready(struct clk *clk)
         clk->ops->find_idlest(clk, &idlest_reg, &idlest_bit, &idlest_val);
 
         omap2_cm_wait_idlest(idlest_reg, (1 << idlest_bit), idlest_val,
-                             clk->name);
+                             __clk_get_name(clk));
 }
 
 /* Public functions */
@@ -94,18 +94,21 @@ static void _omap2_module_wait_ready(struct clk *clk)
 void omap2_init_clk_clkdm(struct clk *clk)
 {
         struct clockdomain *clkdm;
+        const char *clk_name;
 
         if (!clk->clkdm_name)
                 return;
 
+        clk_name = __clk_get_name(clk);
+
         clkdm = clkdm_lookup(clk->clkdm_name);
         if (clkdm) {
                 pr_debug("clock: associated clk %s to clkdm %s\n",
-                         clk->name, clk->clkdm_name);
+                         clk_name, clk->clkdm_name);
                 clk->clkdm = clkdm;
         } else {
                 pr_debug("clock: could not associate clk %s to clkdm %s\n",
-                         clk->name, clk->clkdm_name);
+                         clk_name, clk->clkdm_name);
         }
 }
 
diff --git a/arch/arm/mach-omap2/clock2420_data.c b/arch/arm/mach-omap2/clock2420_data.c
index 12c178dbc9f5..c3cde1a2b6de 100644
--- a/arch/arm/mach-omap2/clock2420_data.c
+++ b/arch/arm/mach-omap2/clock2420_data.c
@@ -1804,6 +1804,7 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gfx_ick",      &gfx_ick,       CK_242X),
         /* DSS domain clocks */
         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_242X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_242X),
         CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_242X),
         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_242X),
         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_242X),
@@ -1843,12 +1844,16 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_242X),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_242X),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_242X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_242X),
         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_242X),
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_242X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_242X),
         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_242X),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_242X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_242X),
         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_242X),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_242X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_242X),
         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_242X),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_242X),
         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_242X),
@@ -1859,12 +1864,15 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_242X),
         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_242X),
         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_242X),
+        CLK(NULL,       "mpu_wdt_ick",          &mpu_wdt_ick,   CK_242X),
         CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_242X),
         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_242X),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_242X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_242X),
         CLK("omap24xxcam", "fck",       &cam_fck,       CK_242X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_242X),
         CLK("omap24xxcam", "ick",       &cam_ick,       CK_242X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_242X),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_242X),
         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_242X),
         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_242X),
@@ -1873,16 +1881,22 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_242X),
         CLK(NULL,       "mspro_fck",    &mspro_fck,     CK_242X),
         CLK("mmci-omap.0", "ick",       &mmc_ick,       CK_242X),
+        CLK(NULL,       "mmc_ick",      &mmc_ick,       CK_242X),
         CLK("mmci-omap.0", "fck",       &mmc_fck,       CK_242X),
+        CLK(NULL,       "mmc_fck",      &mmc_fck,       CK_242X),
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_242X),
         CLK(NULL,       "fac_fck",      &fac_fck,       CK_242X),
         CLK(NULL,       "eac_ick",      &eac_ick,       CK_242X),
         CLK(NULL,       "eac_fck",      &eac_fck,       CK_242X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_242X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_242X),
         CLK("omap_hdq.0", "fck",        &hdq_fck,       CK_242X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_242X),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_242X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_242X),
         CLK(NULL,       "i2c1_fck",     &i2c1_fck,      CK_242X),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_242X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_242X),
         CLK(NULL,       "i2c2_fck",     &i2c2_fck,      CK_242X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_242X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_242X),
@@ -1892,14 +1906,18 @@ static struct omap_clk omap2420_clks[] = {
         CLK(NULL,       "vlynq_fck",    &vlynq_fck,     CK_242X),
         CLK(NULL,       "des_ick",      &des_ick,       CK_242X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_242X),
+        CLK(NULL,       "sha_ick",      &sha_ick,       CK_242X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_242X),
+        CLK(NULL,       "rng_ick",              &rng_ick,       CK_242X),
         CLK("omap-aes", "ick",  &aes_ick,       CK_242X),
+        CLK(NULL,       "aes_ick",      &aes_ick,       CK_242X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_242X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_242X),
         CLK("musb-hdrc",        "fck",  &osc_ck,        CK_242X),
-        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_243X),
-        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
-        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
+        CLK(NULL,       "timer_32k_ck", &func_32k_ck,   CK_242X),
+        CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_242X),
+        CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_242X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_242X),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/clock2430_data.c b/arch/arm/mach-omap2/clock2430_data.c
index 7ea91398217a..22404fe435e7 100644
--- a/arch/arm/mach-omap2/clock2430_data.c
+++ b/arch/arm/mach-omap2/clock2430_data.c
@@ -1888,6 +1888,7 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "mdm_osc_ck",   &mdm_osc_ck,    CK_243X),
         /* DSS domain clocks */
         CLK("omapdss_dss",      "ick",          &dss_ick,       CK_243X),
+        CLK(NULL,       "dss_ick",              &dss_ick,       CK_243X),
         CLK(NULL,       "dss1_fck",             &dss1_fck,      CK_243X),
         CLK(NULL,       "dss2_fck",     &dss2_fck,      CK_243X),
         CLK(NULL,       "dss_54m_fck",  &dss_54m_fck,   CK_243X),
@@ -1927,20 +1928,28 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "gpt12_ick",    &gpt12_ick,     CK_243X),
         CLK(NULL,       "gpt12_fck",    &gpt12_fck,     CK_243X),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_243X),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_243X),
         CLK(NULL,       "mcbsp1_fck",   &mcbsp1_fck,    CK_243X),
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_243X),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp2_ick,    CK_243X),
         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_243X),
         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_243X),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_243X),
         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_243X),
         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_243X),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp4_ick,    CK_243X),
         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_243X),
         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_243X),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_243X),
         CLK(NULL,       "mcbsp5_fck",   &mcbsp5_fck,    CK_243X),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_243X),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_243X),
         CLK(NULL,       "mcspi1_fck",   &mcspi1_fck,    CK_243X),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_243X),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_243X),
         CLK(NULL,       "mcspi2_fck",   &mcspi2_fck,    CK_243X),
         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_243X),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_243X),
         CLK(NULL,       "mcspi3_fck",   &mcspi3_fck,    CK_243X),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_243X),
         CLK(NULL,       "uart1_fck",    &uart1_fck,     CK_243X),
@@ -1951,13 +1960,16 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "gpios_ick",    &gpios_ick,     CK_243X),
         CLK(NULL,       "gpios_fck",    &gpios_fck,     CK_243X),
         CLK("omap_wdt", "ick",          &mpu_wdt_ick,   CK_243X),
+        CLK(NULL,       "mpu_wdt_ick",  &mpu_wdt_ick,   CK_243X),
         CLK(NULL,       "mpu_wdt_fck",  &mpu_wdt_fck,   CK_243X),
         CLK(NULL,       "sync_32k_ick", &sync_32k_ick,  CK_243X),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_243X),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_243X),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_243X),
         CLK("omap24xxcam", "fck",       &cam_fck,       CK_243X),
+        CLK(NULL,       "cam_fck",      &cam_fck,       CK_243X),
         CLK("omap24xxcam", "ick",       &cam_ick,       CK_243X),
+        CLK(NULL,       "cam_ick",      &cam_ick,       CK_243X),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick,        CK_243X),
         CLK(NULL,       "wdt4_ick",     &wdt4_ick,      CK_243X),
         CLK(NULL,       "wdt4_fck",     &wdt4_fck,      CK_243X),
@@ -1966,10 +1978,14 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_243X),
         CLK(NULL,       "fac_fck",      &fac_fck,       CK_243X),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_243X),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_243X),
         CLK("omap_hdq.1", "fck",        &hdq_fck,       CK_243X),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_243X),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_243X),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_243X),
         CLK(NULL,       "i2chs1_fck",   &i2chs1_fck,    CK_243X),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_243X),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_243X),
         CLK(NULL,       "i2chs2_fck",   &i2chs2_fck,    CK_243X),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_243X),
         CLK(NULL,       "sdma_fck",     &sdma_fck,      CK_243X),
@@ -1978,22 +1994,29 @@ static struct omap_clk omap2430_clks[] = {
         CLK(NULL,       "des_ick",      &des_ick,       CK_243X),
         CLK("omap-sham",        "ick",  &sha_ick,       CK_243X),
         CLK("omap_rng", "ick",          &rng_ick,       CK_243X),
+        CLK(NULL,       "rng_ick",      &rng_ick,       CK_243X),
         CLK("omap-aes", "ick",  &aes_ick,       CK_243X),
         CLK(NULL,       "pka_ick",      &pka_ick,       CK_243X),
         CLK(NULL,       "usb_fck",      &usb_fck,       CK_243X),
         CLK("musb-omap2430",    "ick",  &usbhs_ick,     CK_243X),
+        CLK(NULL,       "usbhs_ick",    &usbhs_ick,     CK_243X),
         CLK("omap_hsmmc.0", "ick",      &mmchs1_ick,    CK_243X),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_243X),
         CLK(NULL,       "mmchs1_fck",   &mmchs1_fck,    CK_243X),
         CLK("omap_hsmmc.1", "ick",      &mmchs2_ick,    CK_243X),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_243X),
         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_243X),
         CLK(NULL,       "gpio5_ick",    &gpio5_ick,     CK_243X),
         CLK(NULL,       "gpio5_fck",    &gpio5_fck,     CK_243X),
         CLK(NULL,       "mdm_intc_ick", &mdm_intc_ick,  CK_243X),
         CLK("omap_hsmmc.0", "mmchsdb_fck",      &mmchsdb1_fck,  CK_243X),
+        CLK(NULL,       "mmchsdb1_fck",         &mmchsdb1_fck,  CK_243X),
         CLK("omap_hsmmc.1", "mmchsdb_fck",      &mmchsdb2_fck,  CK_243X),
+        CLK(NULL,       "mmchsdb2_fck",         &mmchsdb2_fck,  CK_243X),
         CLK(NULL,       "timer_32k_ck",  &func_32k_ck,   CK_243X),
         CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_243X),
         CLK(NULL,       "timer_ext_ck", &alt_ck,        CK_243X),
+        CLK(NULL,       "cpufreq_ck",   &virt_prcm_set, CK_243X),
 };
 
 /*
diff --git a/arch/arm/mach-omap2/clock33xx_data.c b/arch/arm/mach-omap2/clock33xx_data.c
index 2026311a4ff6..b87b88c2638b 100644
--- a/arch/arm/mach-omap2/clock33xx_data.c
+++ b/arch/arm/mach-omap2/clock33xx_data.c
@@ -1013,6 +1013,7 @@ static struct omap_clk am33xx_clks[] = {
         CLK(NULL,       "dpll_core_m5_ck",      &dpll_core_m5_ck,       CK_AM33XX),
         CLK(NULL,       "dpll_core_m6_ck",      &dpll_core_m6_ck,       CK_AM33XX),
         CLK(NULL,       "dpll_mpu_ck",          &dpll_mpu_ck,   CK_AM33XX),
+        CLK("cpu0",     NULL,                   &dpll_mpu_ck,           CK_AM33XX),
         CLK(NULL,       "dpll_mpu_m2_ck",       &dpll_mpu_m2_ck,        CK_AM33XX),
         CLK(NULL,       "dpll_ddr_ck",          &dpll_ddr_ck,   CK_AM33XX),
         CLK(NULL,       "dpll_ddr_m2_ck",       &dpll_ddr_m2_ck,        CK_AM33XX),
diff --git a/arch/arm/mach-omap2/clock3xxx.c b/arch/arm/mach-omap2/clock3xxx.c
index 15cdc6471737..83bb01427d40 100644
--- a/arch/arm/mach-omap2/clock3xxx.c
+++ b/arch/arm/mach-omap2/clock3xxx.c
@@ -63,15 +63,15 @@ void __init omap3_clk_lock_dpll5(void)
 
         dpll5_clk = clk_get(NULL, "dpll5_ck");
         clk_set_rate(dpll5_clk, DPLL5_FREQ_FOR_USBHOST);
-        clk_enable(dpll5_clk);
+        clk_prepare_enable(dpll5_clk);
 
         /* Program dpll5_m2_clk divider for no division */
         dpll5_m2_clk = clk_get(NULL, "dpll5_m2_ck");
-        clk_enable(dpll5_m2_clk);
+        clk_prepare_enable(dpll5_m2_clk);
         clk_set_rate(dpll5_m2_clk, DPLL5_FREQ_FOR_USBHOST);
 
-        clk_disable(dpll5_m2_clk);
-        clk_disable(dpll5_clk);
+        clk_disable_unprepare(dpll5_m2_clk);
+        clk_disable_unprepare(dpll5_clk);
         return;
 }
 
diff --git a/arch/arm/mach-omap2/clock3xxx_data.c b/arch/arm/mach-omap2/clock3xxx_data.c
index 700317a1bd16..1f42c9d5ecf3 100644
--- a/arch/arm/mach-omap2/clock3xxx_data.c
+++ b/arch/arm/mach-omap2/clock3xxx_data.c
@@ -3215,7 +3215,6 @@ static struct clk dummy_apb_pclk = {
  * clkdev
  */
 
-/* XXX At some point we should rename this file to clock3xxx_data.c */
 static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "apb_pclk",     &dummy_apb_pclk,        CK_3XXX),
         CLK(NULL,       "omap_32k_fck", &omap_32k_fck,  CK_3XXX),
@@ -3243,11 +3242,13 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll3_m2x2_ck", &dpll3_m2x2_ck, CK_3XXX),
         CLK(NULL,       "dpll3_m3_ck",  &dpll3_m3_ck,   CK_3XXX),
         CLK(NULL,       "dpll3_m3x2_ck", &dpll3_m3x2_ck, CK_3XXX),
+        CLK(NULL,       "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
         CLK("etb",      "emu_core_alwon_ck", &emu_core_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll4_ck",     &dpll4_ck,      CK_3XXX),
         CLK(NULL,       "dpll4_x2_ck",  &dpll4_x2_ck,   CK_3XXX),
         CLK(NULL,       "omap_192m_alwon_fck", &omap_192m_alwon_fck, CK_36XX),
         CLK(NULL,       "omap_96m_alwon_fck", &omap_96m_alwon_fck, CK_3XXX),
+        CLK(NULL,       "omap_96m_alwon_fck_3630", &omap_96m_alwon_fck_3630, CK_36XX),
         CLK(NULL,       "omap_96m_fck", &omap_96m_fck,  CK_3XXX),
         CLK(NULL,       "cm_96m_fck",   &cm_96m_fck,    CK_3XXX),
         CLK(NULL,       "omap_54m_fck", &omap_54m_fck,  CK_3XXX),
@@ -3263,6 +3264,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll4_m5x2_ck", &dpll4_m5x2_ck, CK_3XXX),
         CLK(NULL,       "dpll4_m6_ck",  &dpll4_m6_ck,   CK_3XXX),
         CLK(NULL,       "dpll4_m6x2_ck", &dpll4_m6x2_ck, CK_3XXX),
+        CLK(NULL,       "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
         CLK("etb",      "emu_per_alwon_ck", &emu_per_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll5_ck",     &dpll5_ck,      CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "dpll5_m2_ck",  &dpll5_m2_ck,   CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
@@ -3272,6 +3274,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dpll1_fck",    &dpll1_fck,     CK_3XXX),
         CLK(NULL,       "mpu_ck",       &mpu_ck,        CK_3XXX),
         CLK(NULL,       "arm_fck",      &arm_fck,       CK_3XXX),
+        CLK(NULL,       "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
         CLK("etb",      "emu_mpu_alwon_ck", &emu_mpu_alwon_ck, CK_3XXX),
         CLK(NULL,       "dpll2_fck",    &dpll2_fck,     CK_34XX | CK_36XX),
         CLK(NULL,       "iva2_ck",      &iva2_ck,       CK_34XX | CK_36XX),
@@ -3295,6 +3298,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ts_fck",       &ts_fck,        CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_fck",   &usbtll_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "core_96m_fck", &core_96m_fck,  CK_3XXX),
         CLK(NULL,       "mmchs3_fck",   &mmchs3_fck,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "mmchs2_fck",   &mmchs2_fck,    CK_3XXX),
@@ -3315,6 +3319,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "fshostusb_fck", &fshostusb_fck, CK_3430ES1),
         CLK(NULL,       "core_12m_fck", &core_12m_fck,  CK_3XXX),
         CLK("omap_hdq.0",       "fck",  &hdq_fck,       CK_3XXX),
+        CLK(NULL,       "hdq_fck",      &hdq_fck,       CK_3XXX),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es1,   CK_3430ES1),
         CLK(NULL,       "ssi_ssr_fck",  &ssi_ssr_fck_3430es2,   CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "ssi_sst_fck",  &ssi_sst_fck_3430es1,   CK_3430ES1),
@@ -3322,6 +3327,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "core_l3_ick",  &core_l3_ick,   CK_3XXX),
         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es1,  CK_3430ES1),
         CLK("musb-omap2430",    "ick",  &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es1,  CK_3430ES1),
+        CLK(NULL,       "hsotgusb_ick", &hsotgusb_ick_3430es2,  CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "sdrc_ick",     &sdrc_ick,      CK_3XXX),
         CLK(NULL,       "gpmc_fck",     &gpmc_fck,      CK_3XXX),
         CLK(NULL,       "security_l3_ick", &security_l3_ick, CK_34XX | CK_36XX),
@@ -3329,28 +3336,42 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "core_l4_ick",  &core_l4_ick,   CK_3XXX),
         CLK(NULL,       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("usbhs_omap",       "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK("usbhs_tll",        "usbtll_ick",   &usbtll_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK("omap_hsmmc.2",     "ick",  &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "mmchs3_ick",   &mmchs3_ick,    CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "icr_ick",      &icr_ick,       CK_34XX | CK_36XX),
         CLK("omap-aes", "ick",  &aes2_ick,      CK_34XX | CK_36XX),
         CLK("omap-sham",        "ick",  &sha12_ick,     CK_34XX | CK_36XX),
         CLK(NULL,       "des2_ick",     &des2_ick,      CK_34XX | CK_36XX),
         CLK("omap_hsmmc.1",     "ick",  &mmchs2_ick,    CK_3XXX),
         CLK("omap_hsmmc.0",     "ick",  &mmchs1_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs2_ick",   &mmchs2_ick,    CK_3XXX),
+        CLK(NULL,       "mmchs1_ick",   &mmchs1_ick,    CK_3XXX),
         CLK(NULL,       "mspro_ick",    &mspro_ick,     CK_34XX | CK_36XX),
         CLK("omap_hdq.0", "ick",        &hdq_ick,       CK_3XXX),
+        CLK(NULL,       "hdq_ick",      &hdq_ick,       CK_3XXX),
         CLK("omap2_mcspi.4", "ick",     &mcspi4_ick,    CK_3XXX),
         CLK("omap2_mcspi.3", "ick",     &mcspi3_ick,    CK_3XXX),
         CLK("omap2_mcspi.2", "ick",     &mcspi2_ick,    CK_3XXX),
         CLK("omap2_mcspi.1", "ick",     &mcspi1_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi4_ick",   &mcspi4_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi3_ick",   &mcspi3_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi2_ick",   &mcspi2_ick,    CK_3XXX),
+        CLK(NULL,       "mcspi1_ick",   &mcspi1_ick,    CK_3XXX),
         CLK("omap_i2c.3", "ick",        &i2c3_ick,      CK_3XXX),
         CLK("omap_i2c.2", "ick",        &i2c2_ick,      CK_3XXX),
         CLK("omap_i2c.1", "ick",        &i2c1_ick,      CK_3XXX),
+        CLK(NULL,       "i2c3_ick",     &i2c3_ick,      CK_3XXX),
+        CLK(NULL,       "i2c2_ick",     &i2c2_ick,      CK_3XXX),
+        CLK(NULL,       "i2c1_ick",     &i2c1_ick,      CK_3XXX),
         CLK(NULL,       "uart2_ick",    &uart2_ick,     CK_3XXX),
         CLK(NULL,       "uart1_ick",    &uart1_ick,     CK_3XXX),
         CLK(NULL,       "gpt11_ick",    &gpt11_ick,     CK_3XXX),
         CLK(NULL,       "gpt10_ick",    &gpt10_ick,     CK_3XXX),
         CLK("omap-mcbsp.5", "ick",      &mcbsp5_ick,    CK_3XXX),
         CLK("omap-mcbsp.1", "ick",      &mcbsp1_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp5_ick",   &mcbsp5_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp1_ick",   &mcbsp1_ick,    CK_3XXX),
         CLK(NULL,       "fac_ick",      &fac_ick,       CK_3430ES1),
         CLK(NULL,       "mailboxes_ick", &mailboxes_ick, CK_34XX | CK_36XX),
         CLK(NULL,       "omapctrl_ick", &omapctrl_ick,  CK_3XXX),
@@ -3369,7 +3390,9 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "dss_96m_fck",  &dss_96m_fck,   CK_3XXX),
         CLK(NULL,       "dss2_alwon_fck",       &dss2_alwon_fck, CK_3XXX),
         CLK("omapdss_dss",      "ick",          &dss_ick_3430es1,       CK_3430ES1),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es1,       CK_3430ES1),
         CLK("omapdss_dss",      "ick",          &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
+        CLK(NULL,       "dss_ick",              &dss_ick_3430es2,       CK_3430ES2PLUS | CK_AM35XX | CK_36XX),
         CLK(NULL,       "cam_mclk",     &cam_mclk,      CK_34XX | CK_36XX),
         CLK(NULL,       "cam_ick",      &cam_ick,       CK_34XX | CK_36XX),
         CLK(NULL,       "csi2_96m_fck", &csi2_96m_fck,  CK_34XX | CK_36XX),
@@ -3385,6 +3408,8 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "usb_host_hs_utmi_p2_clk",      &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
         CLK("usbhs_omap",       "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch0_clk",       &dummy_ck,      CK_3XXX),
+        CLK("usbhs_tll",        "usb_tll_hs_usb_ch1_clk",       &dummy_ck,      CK_3XXX),
         CLK(NULL,       "init_60m_fclk",        &dummy_ck,      CK_3XXX),
         CLK(NULL,       "usim_fck",     &usim_fck,      CK_3430ES2PLUS | CK_36XX),
         CLK(NULL,       "gpt1_fck",     &gpt1_fck,      CK_3XXX),
@@ -3394,6 +3419,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "wkup_l4_ick",  &wkup_l4_ick,   CK_34XX | CK_36XX),
         CLK(NULL,       "usim_ick",     &usim_ick,      CK_3430ES2PLUS | CK_36XX),
         CLK("omap_wdt", "ick",          &wdt2_ick,      CK_3XXX),
+        CLK(NULL,       "wdt2_ick",     &wdt2_ick,      CK_3XXX),
         CLK(NULL,       "wdt1_ick",     &wdt1_ick,      CK_3XXX),
         CLK(NULL,       "gpio1_ick",    &gpio1_ick,     CK_3XXX),
         CLK(NULL,       "omap_32ksync_ick", &omap_32ksync_ick, CK_3XXX),
@@ -3439,9 +3465,13 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK("omap-mcbsp.2", "ick",      &mcbsp2_ick,    CK_3XXX),
         CLK("omap-mcbsp.3", "ick",      &mcbsp3_ick,    CK_3XXX),
         CLK("omap-mcbsp.4", "ick",      &mcbsp4_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp4_ick",   &mcbsp2_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp3_ick",   &mcbsp3_ick,    CK_3XXX),
+        CLK(NULL,       "mcbsp2_ick",   &mcbsp4_ick,    CK_3XXX),
         CLK(NULL,       "mcbsp2_fck",   &mcbsp2_fck,    CK_3XXX),
         CLK(NULL,       "mcbsp3_fck",   &mcbsp3_fck,    CK_3XXX),
         CLK(NULL,       "mcbsp4_fck",   &mcbsp4_fck,    CK_3XXX),
+        CLK(NULL,       "emu_src_ck",   &emu_src_ck,    CK_3XXX),
         CLK("etb",      "emu_src_ck",   &emu_src_ck,    CK_3XXX),
         CLK(NULL,       "pclk_fck",     &pclk_fck,      CK_3XXX),
         CLK(NULL,       "pclkx2_fck",   &pclkx2_fck,    CK_3XXX),
@@ -3457,8 +3487,12 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "ipss_ick",     &ipss_ick,      CK_AM35XX),
         CLK(NULL,       "rmii_ck",      &rmii_ck,       CK_AM35XX),
         CLK(NULL,       "pclk_ck",      &pclk_ck,       CK_AM35XX),
+        CLK(NULL,       "emac_ick",     &emac_ick,      CK_AM35XX),
+        CLK(NULL,       "emac_fck",     &emac_fck,      CK_AM35XX),
         CLK("davinci_emac.0",   NULL,   &emac_ick,      CK_AM35XX),
         CLK("davinci_mdio.0",   NULL,   &emac_fck,      CK_AM35XX),
+        CLK(NULL,       "vpfe_ick",     &emac_ick,      CK_AM35XX),
+        CLK(NULL,       "vpfe_fck",     &emac_fck,      CK_AM35XX),
         CLK("vpfe-capture",     "master",       &vpfe_ick,      CK_AM35XX),
         CLK("vpfe-capture",     "slave",        &vpfe_fck,      CK_AM35XX),
         CLK(NULL,       "hsotgusb_ick",         &hsotgusb_ick_am35xx,   CK_AM35XX),
@@ -3467,6 +3501,7 @@ static struct omap_clk omap3xxx_clks[] = {
         CLK(NULL,       "uart4_ick",    &uart4_ick_am35xx,      CK_AM35XX),
         CLK(NULL,       "timer_32k_ck", &omap_32k_fck,  CK_3XXX),
         CLK(NULL,       "timer_sys_ck", &sys_ck,        CK_3XXX),
+        CLK(NULL,       "cpufreq_ck",   &dpll1_ck,      CK_3XXX),
 };
 
 
diff --git a/arch/arm/mach-omap2/clock44xx_data.c b/arch/arm/mach-omap2/clock44xx_data.c
index 500682c051c1..d661d138f270 100644
--- a/arch/arm/mach-omap2/clock44xx_data.c
+++ b/arch/arm/mach-omap2/clock44xx_data.c
@@ -3156,6 +3156,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "dss_tv_clk",                   &dss_tv_clk,    CK_443X),
         CLK(NULL,       "dss_48mhz_clk",                &dss_48mhz_clk, CK_443X),
         CLK(NULL,       "dss_dss_clk",                  &dss_dss_clk,   CK_443X),
+        CLK(NULL,       "dss_fck",                      &dss_fck,       CK_443X),
         CLK("omapdss_dss",      "ick",                          &dss_fck,       CK_443X),
         CLK(NULL,       "efuse_ctrl_cust_fck",          &efuse_ctrl_cust_fck,   CK_443X),
         CLK(NULL,       "emif1_fck",                    &emif1_fck,     CK_443X),
@@ -3212,6 +3213,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "ocp2scp_usb_phy_phy_48m",      &ocp2scp_usb_phy_phy_48m,       CK_443X),
         CLK(NULL,       "ocp2scp_usb_phy_ick",          &ocp2scp_usb_phy_ick,   CK_443X),
         CLK(NULL,       "ocp_wp_noc_ick",               &ocp_wp_noc_ick,        CK_443X),
+        CLK(NULL,       "rng_ick",                      &rng_ick,       CK_443X),
         CLK("omap_rng", "ick",                          &rng_ick,       CK_443X),
         CLK(NULL,       "sha2md5_fck",                  &sha2md5_fck,   CK_443X),
         CLK(NULL,       "sl2if_ick",                    &sl2if_ick,     CK_443X),
@@ -3243,6 +3245,7 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart3_fck",                    &uart3_fck,     CK_443X),
         CLK(NULL,       "uart4_fck",                    &uart4_fck,     CK_443X),
         CLK("usbhs_omap",       "fs_fck",               &usb_host_fs_fck,       CK_443X),
+        CLK(NULL,       "usb_host_fs_fck",              &usb_host_fs_fck,       CK_443X),
         CLK(NULL,       "utmi_p1_gfclk",                &utmi_p1_gfclk, CK_443X),
         CLK(NULL,       "usb_host_hs_utmi_p1_clk",      &usb_host_hs_utmi_p1_clk,       CK_443X),
         CLK(NULL,       "utmi_p2_gfclk",                &utmi_p2_gfclk, CK_443X),
@@ -3253,15 +3256,19 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "usb_host_hs_hsic60m_p2_clk",   &usb_host_hs_hsic60m_p2_clk,    CK_443X),
         CLK(NULL,       "usb_host_hs_hsic480m_p2_clk",  &usb_host_hs_hsic480m_p2_clk,   CK_443X),
         CLK(NULL,       "usb_host_hs_func48mclk",       &usb_host_hs_func48mclk,        CK_443X),
+        CLK(NULL,       "usb_host_hs_fck",              &usb_host_hs_fck,       CK_443X),
         CLK("usbhs_omap",       "hs_fck",               &usb_host_hs_fck,       CK_443X),
         CLK(NULL,       "otg_60m_gfclk",                &otg_60m_gfclk, CK_443X),
         CLK(NULL,       "usb_otg_hs_xclk",              &usb_otg_hs_xclk,       CK_443X),
+        CLK(NULL,       "usb_otg_hs_ick",               &usb_otg_hs_ick,        CK_443X),
         CLK("musb-omap2430",    "ick",                          &usb_otg_hs_ick,        CK_443X),
         CLK(NULL,       "usb_phy_cm_clk32k",            &usb_phy_cm_clk32k,     CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch2_clk",       &usb_tll_hs_usb_ch2_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch0_clk",       &usb_tll_hs_usb_ch0_clk,        CK_443X),
         CLK(NULL,       "usb_tll_hs_usb_ch1_clk",       &usb_tll_hs_usb_ch1_clk,        CK_443X),
+        CLK(NULL,       "usb_tll_hs_ick",               &usb_tll_hs_ick,        CK_443X),
         CLK("usbhs_omap",       "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
+        CLK("usbhs_tll",        "usbtll_ick",           &usb_tll_hs_ick,        CK_443X),
         CLK(NULL,       "usim_ck",                      &usim_ck,       CK_443X),
         CLK(NULL,       "usim_fclk",                    &usim_fclk,     CK_443X),
         CLK(NULL,       "usim_fck",                     &usim_fck,      CK_443X),
@@ -3312,8 +3319,10 @@ static struct omap_clk omap44xx_clks[] = {
         CLK(NULL,       "uart4_ick",                    &dummy_ck,      CK_443X),
         CLK("usbhs_omap",       "usbhost_ick",          &dummy_ck,              CK_443X),
         CLK("usbhs_omap",       "usbtll_fck",           &dummy_ck,      CK_443X),
+        CLK("usbhs_tll",        "usbtll_fck",           &dummy_ck,      CK_443X),
         CLK("omap_wdt", "ick",                          &dummy_ck,      CK_443X),
         CLK(NULL,       "timer_32k_ck", &sys_32k_ck,    CK_443X),
+        /* TODO: Remove "omap_timer.X" aliases once DT migration is complete */
         CLK("omap_timer.1",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
         CLK("omap_timer.2",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
         CLK("omap_timer.3",     "timer_sys_ck", &sys_clkin_ck,  CK_443X),
@@ -3325,6 +3334,18 @@ static struct omap_clk omap44xx_clks[] = {
         CLK("omap_timer.6",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
         CLK("omap_timer.7",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
         CLK("omap_timer.8",     "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4a318000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48032000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48034000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48036000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("4803e000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48086000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("48088000.timer",   "timer_sys_ck", &sys_clkin_ck,  CK_443X),
+        CLK("49038000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903a000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903c000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK("4903e000.timer",   "timer_sys_ck", &syc_clk_div_ck,        CK_443X),
+        CLK(NULL,       "cpufreq_ck",   &dpll_mpu_ck,   CK_443X),
 };
 
 int __init omap4xxx_clk_init(void)
diff --git a/arch/arm/mach-omap2/clockdomain.c b/arch/arm/mach-omap2/clockdomain.c
index a1555627ad97..cbb879139c51 100644
--- a/arch/arm/mach-omap2/clockdomain.c
+++ b/arch/arm/mach-omap2/clockdomain.c
@@ -899,6 +899,23 @@ bool clkdm_in_hwsup(struct clockdomain *clkdm)
         return ret;
 }
 
+/**
+ * clkdm_missing_idle_reporting - can @clkdm enter autoidle even if in use?
+ * @clkdm: struct clockdomain *
+ *
+ * Returns true if clockdomain @clkdm has the
+ * CLKDM_MISSING_IDLE_REPORTING flag set, or false if not or @clkdm is
+ * null.  More information is available in the documentation for the
+ * CLKDM_MISSING_IDLE_REPORTING macro.
+ */
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm)
+{
+        if (!clkdm)
+                return false;
+
+        return (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) ? true : false;
+}
+
 /* Clockdomain-to-clock/hwmod framework interface code */
 
 static int _clkdm_clk_hwmod_enable(struct clockdomain *clkdm)
diff --git a/arch/arm/mach-omap2/clockdomain.h b/arch/arm/mach-omap2/clockdomain.h
index 5601dc13785e..629576be7444 100644
--- a/arch/arm/mach-omap2/clockdomain.h
+++ b/arch/arm/mach-omap2/clockdomain.h
@@ -1,9 +1,7 @@
 /*
- * arch/arm/plat-omap/include/mach/clockdomain.h
- *
  * OMAP2/3 clockdomain framework functions
  *
- * Copyright (C) 2008 Texas Instruments, Inc.
+ * Copyright (C) 2008, 2012 Texas Instruments, Inc.
  * Copyright (C) 2008-2011 Nokia Corporation
  *
  * Paul Walmsley
@@ -34,6 +32,20 @@
  * CLKDM_ACTIVE_WITH_MPU: The PRCM guarantees that this clockdomain is
  *     active whenever the MPU is active.  True for interconnects and
  *     the WKUP clockdomains.
+ * CLKDM_MISSING_IDLE_REPORTING: The idle status of the IP blocks and
+ *     clocks inside this clockdomain are not taken into account by
+ *     the PRCM when determining whether the clockdomain is idle.
+ *     Without this flag, if the clockdomain is set to
+ *     hardware-supervised idle mode, the PRCM may transition the
+ *     enclosing powerdomain to a low power state, even when devices
+ *     inside the clockdomain and powerdomain are in use.  (An example
+ *     of such a clockdomain is the EMU clockdomain on OMAP3/4.)  If
+ *     this flag is set, and the clockdomain does not support the
+ *     force-sleep mode, then the HW_AUTO mode will be used to put the
+ *     clockdomain to sleep.  Similarly, if the clockdomain supports
+ *     the force-wakeup mode, then it will be used whenever a clock or
+ *     IP block inside the clockdomain is active, rather than the
+ *     HW_AUTO mode.
  */
 #define CLKDM_CAN_FORCE_SLEEP                   (1 << 0)
 #define CLKDM_CAN_FORCE_WAKEUP                  (1 << 1)
@@ -41,6 +53,7 @@
 #define CLKDM_CAN_DISABLE_AUTO                  (1 << 3)
 #define CLKDM_NO_AUTODEPS                       (1 << 4)
 #define CLKDM_ACTIVE_WITH_MPU                   (1 << 5)
+#define CLKDM_MISSING_IDLE_REPORTING            (1 << 6)
 
 #define CLKDM_CAN_HWSUP         (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_DISABLE_AUTO)
 #define CLKDM_CAN_SWSUP         (CLKDM_CAN_FORCE_SLEEP | CLKDM_CAN_FORCE_WAKEUP)
@@ -187,6 +200,7 @@ int clkdm_clear_all_sleepdeps(struct clockdomain *clkdm);
 void clkdm_allow_idle(struct clockdomain *clkdm);
 void clkdm_deny_idle(struct clockdomain *clkdm);
 bool clkdm_in_hwsup(struct clockdomain *clkdm);
+bool clkdm_missing_idle_reporting(struct clockdomain *clkdm);
 
 int clkdm_wakeup(struct clockdomain *clkdm);
 int clkdm_sleep(struct clockdomain *clkdm);
diff --git a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
index f99e65cfb862..9a7792aec673 100644
--- a/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/clockdomain2xxx_3xxx.c
@@ -162,6 +162,19 @@ static void _disable_hwsup(struct clockdomain *clkdm)
                                                 clkdm->clktrctrl_mask);
 }
 
+static int omap3_clkdm_sleep(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
+
+static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
+{
+        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
+                                clkdm->clktrctrl_mask);
+        return 0;
+}
 
 static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
 {
@@ -170,6 +183,17 @@ static int omap2_clkdm_clk_enable(struct clockdomain *clkdm)
         if (!clkdm->clktrctrl_mask)
                 return 0;
 
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                _enable_hwsup(clkdm);
+                return 0;
+        }
+
         hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                 clkdm->clktrctrl_mask);
 
@@ -193,6 +217,17 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
         if (!clkdm->clktrctrl_mask)
                 return 0;
 
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if ((clkdm->flags & CLKDM_MISSING_IDLE_REPORTING) &&
+            (clkdm->flags & CLKDM_CAN_FORCE_WAKEUP)) {
+                omap3_clkdm_wakeup(clkdm);
+                return 0;
+        }
+
         hwsup = omap2_cm_is_clkdm_in_hwsup(clkdm->pwrdm.ptr->prcm_offs,
                                 clkdm->clktrctrl_mask);
 
@@ -209,20 +244,6 @@ static int omap2_clkdm_clk_disable(struct clockdomain *clkdm)
         return 0;
 }
 
-static int omap3_clkdm_sleep(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_sleep(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
-
-static int omap3_clkdm_wakeup(struct clockdomain *clkdm)
-{
-        omap3xxx_cm_clkdm_force_wakeup(clkdm->pwrdm.ptr->prcm_offs,
-                                clkdm->clktrctrl_mask);
-        return 0;
-}
-
 static void omap3_clkdm_allow_idle(struct clockdomain *clkdm)
 {
         if (atomic_read(&clkdm->usecount) > 0)
diff --git a/arch/arm/mach-omap2/clockdomain44xx.c b/arch/arm/mach-omap2/clockdomain44xx.c
index 762f2cc542ce..6fc6155625bc 100644
--- a/arch/arm/mach-omap2/clockdomain44xx.c
+++ b/arch/arm/mach-omap2/clockdomain44xx.c
@@ -113,6 +113,17 @@ static int omap4_clkdm_clk_disable(struct clockdomain *clkdm)
         if (!clkdm->prcm_partition)
                 return 0;
 
+        /*
+         * The CLKDM_MISSING_IDLE_REPORTING flag documentation has
+         * more details on the unpleasant problem this is working
+         * around
+         */
+        if (clkdm->flags & CLKDM_MISSING_IDLE_REPORTING &&
+            !(clkdm->flags & CLKDM_CAN_FORCE_SLEEP)) {
+                omap4_clkdm_allow_idle(clkdm);
+                return 0;
+        }
+
         hwsup = omap4_cminst_is_clkdm_in_hwsup(clkdm->prcm_partition,
                                         clkdm->cm_inst, clkdm->clkdm_offs);
 
diff --git a/arch/arm/mach-omap2/clockdomains3xxx_data.c b/arch/arm/mach-omap2/clockdomains3xxx_data.c
index 56089c49142a..933a35cd124a 100644
--- a/arch/arm/mach-omap2/clockdomains3xxx_data.c
+++ b/arch/arm/mach-omap2/clockdomains3xxx_data.c
@@ -387,14 +387,11 @@ static struct clockdomain per_am35x_clkdm = {
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_PER_MASK,
 };
 
-/*
- * Disable hw supervised mode for emu_clkdm, because emu_pwrdm is
- * switched of even if sdti is in use
- */
 static struct clockdomain emu_clkdm = {
         .name           = "emu_clkdm",
         .pwrdm          = { .name = "emu_pwrdm" },
-        .flags          = /* CLKDM_CAN_ENABLE_AUTO |  */CLKDM_CAN_SWSUP,
+        .flags          = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_SWSUP |
+                           CLKDM_MISSING_IDLE_REPORTING),
         .clktrctrl_mask = OMAP3430_CLKTRCTRL_EMU_MASK,
 };
 
diff --git a/arch/arm/mach-omap2/clockdomains44xx_data.c b/arch/arm/mach-omap2/clockdomains44xx_data.c
index 63d60a773d3b..b56d06b48782 100644
--- a/arch/arm/mach-omap2/clockdomains44xx_data.c
+++ b/arch/arm/mach-omap2/clockdomains44xx_data.c
@@ -390,7 +390,8 @@ static struct clockdomain emu_sys_44xx_clkdm = {
         .prcm_partition   = OMAP4430_PRM_PARTITION,
         .cm_inst          = OMAP4430_PRM_EMU_CM_INST,
         .clkdm_offs       = OMAP4430_PRM_EMU_CM_EMU_CDOFFS,
-        .flags            = CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP,
+        .flags            = (CLKDM_CAN_ENABLE_AUTO | CLKDM_CAN_FORCE_WAKEUP |
+                             CLKDM_MISSING_IDLE_REPORTING),
 };
 
 static struct clockdomain l3_dma_44xx_clkdm = {
diff --git a/arch/arm/mach-omap2/cm-regbits-33xx.h b/arch/arm/mach-omap2/cm-regbits-33xx.h
index 532027ee3d8d..adf7bb79b18f 100644
--- a/arch/arm/mach-omap2/cm-regbits-33xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-33xx.h
@@ -25,263 +25,328 @@
  * CM_AUTOIDLE_DPLL_MPU, CM_AUTOIDLE_DPLL_PER
  */
 #define AM33XX_AUTO_DPLL_MODE_SHIFT                     0
+#define AM33XX_AUTO_DPLL_MODE_WIDTH                     3
 #define AM33XX_AUTO_DPLL_MODE_MASK                      (0x7 << 0)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_ADC_FCLK_SHIFT               14
+#define AM33XX_CLKACTIVITY_ADC_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_ADC_FCLK_MASK                (1 << 16)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CAN_CLK_SHIFT                11
+#define AM33XX_CLKACTIVITY_CAN_CLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_CAN_CLK_MASK                 (1 << 11)
 
 /* Used by CM_PER_CLK_24MHZ_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_CLK_24MHZ_GCLK_MASK          (1 << 4)
 
 /* Used by CM_PER_CPSW_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_CPSW_125MHZ_GCLK_MASK        (1 << 4)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_CPSW_250MHZ_GCLK_MASK        (1 << 4)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_SHIFT        5
+#define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_CPSW_50MHZ_GCLK_MASK         (1 << 5)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_SHIFT         6
+#define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_CPSW_5MHZ_GCLK_MASK          (1 << 6)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_SHIFT          6
+#define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_CPTS_RFT_GCLK_MASK           (1 << 6)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT     9
+#define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH     1
 #define AM33XX_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK      (1 << 9)
 
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_DBGSYSCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_DBGSYSCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_DBGSYSCLK_MASK               (1 << 2)
 
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_SHIFT             4
+#define AM33XX_CLKACTIVITY_DEBUG_CLKA_WIDTH             1
 #define AM33XX_CLKACTIVITY_DEBUG_CLKA_MASK              (1 << 4)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_EMIF_GCLK_SHIFT              2
+#define AM33XX_CLKACTIVITY_EMIF_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_EMIF_GCLK_MASK               (1 << 2)
 
 /* Used by CM_GFX_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GFX_FCLK_SHIFT               9
+#define AM33XX_CLKACTIVITY_GFX_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_GFX_FCLK_MASK                (1 << 9)
 
 /* Used by CM_GFX_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_GFX_L3_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_GFX_L3_GCLK_MASK             (1 << 8)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_SHIFT           8
+#define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_WIDTH           1
 #define AM33XX_CLKACTIVITY_GPIO0_GDBCLK_MASK            (1 << 8)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_SHIFT          19
+#define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_1_GDBCLK_MASK           (1 << 19)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_SHIFT          20
+#define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_2_GDBCLK_MASK           (1 << 20)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_SHIFT          21
+#define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_3_GDBCLK_MASK           (1 << 21)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_SHIFT          22
+#define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_4_GDBCLK_MASK           (1 << 22)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_SHIFT          26
+#define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_5_GDBCLK_MASK           (1 << 26)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_SHIFT          18
+#define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_GPIO_6_GDBCLK_MASK           (1 << 18)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_SHIFT             11
+#define AM33XX_CLKACTIVITY_I2C0_GFCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_I2C0_GFCLK_MASK              (1 << 11)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_I2C_FCLK_SHIFT               24
+#define AM33XX_CLKACTIVITY_I2C_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_I2C_FCLK_MASK                (1 << 24)
 
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_SHIFT         5
+#define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_PRUSS_IEP_GCLK_MASK          (1 << 5)
 
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_SHIFT         4
+#define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_WIDTH         1
 #define AM33XX_CLKACTIVITY_PRUSS_OCP_GCLK_MASK          (1 << 4)
 
 /* Used by CM_PER_PRUSS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_SHIFT        6
+#define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_PRUSS_UART_GCLK_MASK         (1 << 6)
 
 /* Used by CM_PER_L3S_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3S_GCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_L3S_GCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_L3S_GCLK_MASK                (1 << 3)
 
 /* Used by CM_L3_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_SHIFT            3
+#define AM33XX_CLKACTIVITY_L3_AON_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_L3_AON_GCLK_MASK             (1 << 3)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L3_GCLK_SHIFT                4
+#define AM33XX_CLKACTIVITY_L3_GCLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_L3_GCLK_MASK                 (1 << 4)
 
 /* Used by CM_PER_L4FW_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4FW_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4FW_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4FW_GCLK_MASK               (1 << 8)
 
 /* Used by CM_PER_L4HS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4HS_GCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_L4HS_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4HS_GCLK_MASK               (1 << 3)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4LS_GCLK_SHIFT              8
+#define AM33XX_CLKACTIVITY_L4LS_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_L4LS_GCLK_MASK               (1 << 8)
 
 /* Used by CM_GFX_L4LS_GFX_CLKSTCTRL__1 */
 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_SHIFT          8
+#define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_L4LS_GFX_GCLK_MASK           (1 << 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT        8
+#define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH        1
 #define AM33XX_CLKACTIVITY_L4_CEFUSE_GICLK_MASK         (1 << 8)
 
 /* Used by CM_RTC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_SHIFT            8
+#define AM33XX_CLKACTIVITY_L4_RTC_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_L4_RTC_GCLK_MASK             (1 << 8)
 
 /* Used by CM_L4_WKUP_AON_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_SHIFT       2
+#define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_L4_WKUP_AON_GCLK_MASK        (1 << 2)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_SHIFT           2
+#define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_WIDTH           1
 #define AM33XX_CLKACTIVITY_L4_WKUP_GCLK_MASK            (1 << 2)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_GCLK_SHIFT              17
+#define AM33XX_CLKACTIVITY_LCDC_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_LCDC_GCLK_MASK               (1 << 17)
 
 /* Used by CM_PER_LCDC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_SHIFT       4
+#define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_LCDC_L3_OCP_GCLK_MASK        (1 << 4)
 
 /* Used by CM_PER_LCDC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_SHIFT       5
+#define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_WIDTH       1
 #define AM33XX_CLKACTIVITY_LCDC_L4_OCP_GCLK_MASK        (1 << 5)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MCASP_GCLK_SHIFT             7
+#define AM33XX_CLKACTIVITY_MCASP_GCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_MCASP_GCLK_MASK              (1 << 7)
 
 /* Used by CM_PER_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MMC_FCLK_SHIFT               3
+#define AM33XX_CLKACTIVITY_MMC_FCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_MMC_FCLK_MASK                (1 << 3)
 
 /* Used by CM_MPU_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_MPU_CLK_SHIFT                2
+#define AM33XX_CLKACTIVITY_MPU_CLK_WIDTH                1
 #define AM33XX_CLKACTIVITY_MPU_CLK_MASK                 (1 << 2)
 
 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_SHIFT          4
+#define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_OCPWP_L3_GCLK_MASK           (1 << 4)
 
 /* Used by CM_PER_OCPWP_L3_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_SHIFT          5
+#define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_WIDTH          1
 #define AM33XX_CLKACTIVITY_OCPWP_L4_GCLK_MASK           (1 << 5)
 
 /* Used by CM_RTC_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_RTC_32KCLK_SHIFT             9
+#define AM33XX_CLKACTIVITY_RTC_32KCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_RTC_32KCLK_MASK              (1 << 9)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_SPI_GCLK_SHIFT               25
+#define AM33XX_CLKACTIVITY_SPI_GCLK_WIDTH               1
 #define AM33XX_CLKACTIVITY_SPI_GCLK_MASK                (1 << 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_SR_SYSCLK_SHIFT              3
+#define AM33XX_CLKACTIVITY_SR_SYSCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_SR_SYSCLK_MASK               (1 << 3)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_SHIFT            10
+#define AM33XX_CLKACTIVITY_TIMER0_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER0_GCLK_MASK             (1 << 10)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER1_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER1_GCLK_MASK             (1 << 13)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_SHIFT            14
+#define AM33XX_CLKACTIVITY_TIMER2_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER2_GCLK_MASK             (1 << 14)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_SHIFT            15
+#define AM33XX_CLKACTIVITY_TIMER3_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER3_GCLK_MASK             (1 << 15)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_SHIFT            16
+#define AM33XX_CLKACTIVITY_TIMER4_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER4_GCLK_MASK             (1 << 16)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_SHIFT            27
+#define AM33XX_CLKACTIVITY_TIMER5_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER5_GCLK_MASK             (1 << 27)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_SHIFT            28
+#define AM33XX_CLKACTIVITY_TIMER6_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER6_GCLK_MASK             (1 << 28)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_SHIFT            13
+#define AM33XX_CLKACTIVITY_TIMER7_GCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_TIMER7_GCLK_MASK             (1 << 13)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_UART0_GFCLK_SHIFT            12
+#define AM33XX_CLKACTIVITY_UART0_GFCLK_WIDTH            1
 #define AM33XX_CLKACTIVITY_UART0_GFCLK_MASK             (1 << 12)
 
 /* Used by CM_PER_L4LS_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_UART_GFCLK_SHIFT             10
+#define AM33XX_CLKACTIVITY_UART_GFCLK_WIDTH             1
 #define AM33XX_CLKACTIVITY_UART_GFCLK_MASK              (1 << 10)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_WDT0_GCLK_SHIFT              9
+#define AM33XX_CLKACTIVITY_WDT0_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_WDT0_GCLK_MASK               (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define AM33XX_CLKACTIVITY_WDT1_GCLK_SHIFT              4
+#define AM33XX_CLKACTIVITY_WDT1_GCLK_WIDTH              1
 #define AM33XX_CLKACTIVITY_WDT1_GCLK_MASK               (1 << 4)
 
 /* Used by CLKSEL_GFX_FCLK */
 #define AM33XX_CLKDIV_SEL_GFX_FCLK_SHIFT                0
+#define AM33XX_CLKDIV_SEL_GFX_FCLK_WIDTH                1
 #define AM33XX_CLKDIV_SEL_GFX_FCLK_MASK                 (1 << 0)
 
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2DIV_SHIFT                         3
-#define AM33XX_CLKOUT2DIV_MASK                          (0x05 << 3)
+#define AM33XX_CLKOUT2DIV_WIDTH                         3
+#define AM33XX_CLKOUT2DIV_MASK                          (0x7 << 3)
 
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2EN_SHIFT                          7
+#define AM33XX_CLKOUT2EN_WIDTH                          1
 #define AM33XX_CLKOUT2EN_MASK                           (1 << 7)
 
 /* Used by CM_CLKOUT_CTRL */
 #define AM33XX_CLKOUT2SOURCE_SHIFT                      0
-#define AM33XX_CLKOUT2SOURCE_MASK                       (0x02 << 0)
+#define AM33XX_CLKOUT2SOURCE_WIDTH                      3
+#define AM33XX_CLKOUT2SOURCE_MASK                       (0x7 << 0)
 
 /*
  * Used by CLKSEL_GPIO0_DBCLK, CLKSEL_LCDC_PIXEL_CLK, CLKSEL_TIMER2_CLK,
@@ -289,6 +354,7 @@
  * CLKSEL_TIMER7_CLK
  */
 #define AM33XX_CLKSEL_SHIFT                             0
+#define AM33XX_CLKSEL_WIDTH                             1
 #define AM33XX_CLKSEL_MASK                              (0x01 << 0)
 
 /*
@@ -296,17 +362,21 @@
  * CM_CPTS_RFT_CLKSEL
  */
 #define AM33XX_CLKSEL_0_0_SHIFT                         0
+#define AM33XX_CLKSEL_0_0_WIDTH                         1
 #define AM33XX_CLKSEL_0_0_MASK                          (1 << 0)
 
 #define AM33XX_CLKSEL_0_1_SHIFT                         0
+#define AM33XX_CLKSEL_0_1_WIDTH                         2
 #define AM33XX_CLKSEL_0_1_MASK                          (3 << 0)
 
 /* Renamed from CLKSEL Used by CLKSEL_TIMER1MS_CLK */
 #define AM33XX_CLKSEL_0_2_SHIFT                         0
+#define AM33XX_CLKSEL_0_2_WIDTH                         3
 #define AM33XX_CLKSEL_0_2_MASK                          (7 << 0)
 
 /* Used by CLKSEL_GFX_FCLK */
 #define AM33XX_CLKSEL_GFX_FCLK_SHIFT                    1
+#define AM33XX_CLKSEL_GFX_FCLK_WIDTH                    1
 #define AM33XX_CLKSEL_GFX_FCLK_MASK                     (1 << 1)
 
 /*
@@ -318,6 +388,7 @@
  * CM_GFX_L3_CLKSTCTRL, CM_GFX_L4LS_GFX_CLKSTCTRL__1, CM_CEFUSE_CLKSTCTRL
  */
 #define AM33XX_CLKTRCTRL_SHIFT                          0
+#define AM33XX_CLKTRCTRL_WIDTH                          2
 #define AM33XX_CLKTRCTRL_MASK                           (0x3 << 0)
 
 /*
@@ -326,34 +397,42 @@
  * CM_SSC_DELTAMSTEP_DPLL_PER
  */
 #define AM33XX_DELTAMSTEP_SHIFT                         0
-#define AM33XX_DELTAMSTEP_MASK                          (0x19 << 0)
+#define AM33XX_DELTAMSTEP_WIDTH                         20
+#define AM33XX_DELTAMSTEP_MASK                          (0xfffff << 0)
 
 /* Used by CM_CLKSEL_DPLL_DDR, CM_CLKSEL_DPLL_DISP, CM_CLKSEL_DPLL_MPU */
 #define AM33XX_DPLL_BYP_CLKSEL_SHIFT                    23
+#define AM33XX_DPLL_BYP_CLKSEL_WIDTH                    1
 #define AM33XX_DPLL_BYP_CLKSEL_MASK                     (1 << 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT           8
+#define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH           1
 #define AM33XX_DPLL_CLKDCOLDO_GATE_CTRL_MASK            (1 << 8)
 
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_DPLL_CLKDCOLDO_PWDN_SHIFT                12
+#define AM33XX_DPLL_CLKDCOLDO_PWDN_WIDTH                1
 #define AM33XX_DPLL_CLKDCOLDO_PWDN_MASK                 (1 << 12)
 
 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 #define AM33XX_DPLL_CLKOUT_DIV_SHIFT                    0
+#define AM33XX_DPLL_CLKOUT_DIV_WIDTH                    5
 #define AM33XX_DPLL_CLKOUT_DIV_MASK                     (0x1f << 0)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_PER */
 #define AM33XX_DPLL_CLKOUT_DIV_0_6_SHIFT                0
-#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x06 << 0)
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_WIDTH                7
+#define AM33XX_DPLL_CLKOUT_DIV_0_6_MASK                 (0x7f << 0)
 
 /* Used by CM_DIV_M2_DPLL_DDR, CM_DIV_M2_DPLL_DISP, CM_DIV_M2_DPLL_MPU */
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_SHIFT               5
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_WIDTH               1
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_MASK                (1 << 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_PER */
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_SHIFT        7
+#define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_WIDTH        1
 #define AM33XX_DPLL_CLKOUT_DIVCHACK_M2_PER_MASK         (1 << 7)
 
 /*
@@ -361,6 +440,7 @@
  * CM_DIV_M2_DPLL_PER
  */
 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_SHIFT              8
+#define AM33XX_DPLL_CLKOUT_GATE_CTRL_WIDTH              1
 #define AM33XX_DPLL_CLKOUT_GATE_CTRL_MASK               (1 << 8)
 
 /*
@@ -368,19 +448,22 @@
  * CM_CLKSEL_DPLL_MPU
  */
 #define AM33XX_DPLL_DIV_SHIFT                           0
+#define AM33XX_DPLL_DIV_WIDTH                           7
 #define AM33XX_DPLL_DIV_MASK                            (0x7f << 0)
 
 #define AM33XX_DPLL_PER_DIV_MASK                        (0xff << 0)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_DIV_0_7_SHIFT                       0
-#define AM33XX_DPLL_DIV_0_7_MASK                        (0x07 << 0)
+#define AM33XX_DPLL_DIV_0_7_WIDTH                       8
+#define AM33XX_DPLL_DIV_0_7_MASK                        (0xff << 0)
 
 /*
  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
  * CM_CLKMODE_DPLL_MPU
  */
 #define AM33XX_DPLL_DRIFTGUARD_EN_SHIFT                 8
+#define AM33XX_DPLL_DRIFTGUARD_EN_WIDTH                 1
 #define AM33XX_DPLL_DRIFTGUARD_EN_MASK                  (1 << 8)
 
 /*
@@ -388,6 +471,7 @@
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_EN_SHIFT                            0
+#define AM33XX_DPLL_EN_WIDTH                            3
 #define AM33XX_DPLL_EN_MASK                             (0x7 << 0)
 
 /*
@@ -395,6 +479,7 @@
  * CM_CLKMODE_DPLL_MPU
  */
 #define AM33XX_DPLL_LPMODE_EN_SHIFT                     10
+#define AM33XX_DPLL_LPMODE_EN_WIDTH                     1
 #define AM33XX_DPLL_LPMODE_EN_MASK                      (1 << 10)
 
 /*
@@ -402,10 +487,12 @@
  * CM_CLKSEL_DPLL_MPU
  */
 #define AM33XX_DPLL_MULT_SHIFT                          8
+#define AM33XX_DPLL_MULT_WIDTH                          11
 #define AM33XX_DPLL_MULT_MASK                           (0x7ff << 8)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_MULT_PERIPH_SHIFT                   8
+#define AM33XX_DPLL_MULT_PERIPH_WIDTH                   12
 #define AM33XX_DPLL_MULT_PERIPH_MASK                    (0xfff << 8)
 
 /*
@@ -413,17 +500,20 @@
  * CM_CLKMODE_DPLL_MPU
  */
 #define AM33XX_DPLL_REGM4XEN_SHIFT                      11
+#define AM33XX_DPLL_REGM4XEN_WIDTH                      1
 #define AM33XX_DPLL_REGM4XEN_MASK                       (1 << 11)
 
 /* Used by CM_CLKSEL_DPLL_PERIPH */
 #define AM33XX_DPLL_SD_DIV_SHIFT                        24
-#define AM33XX_DPLL_SD_DIV_MASK                         (24, 31)
+#define AM33XX_DPLL_SD_DIV_WIDTH                        8
+#define AM33XX_DPLL_SD_DIV_MASK                         (0xff << 24)
 
 /*
  * Used by CM_CLKMODE_DPLL_CORE, CM_CLKMODE_DPLL_DDR, CM_CLKMODE_DPLL_DISP,
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_SSC_ACK_SHIFT                       13
+#define AM33XX_DPLL_SSC_ACK_WIDTH                       1
 #define AM33XX_DPLL_SSC_ACK_MASK                        (1 << 13)
 
 /*
@@ -431,6 +521,7 @@
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_SSC_DOWNSPREAD_SHIFT                14
+#define AM33XX_DPLL_SSC_DOWNSPREAD_WIDTH                1
 #define AM33XX_DPLL_SSC_DOWNSPREAD_MASK                 (1 << 14)
 
 /*
@@ -438,54 +529,67 @@
  * CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define AM33XX_DPLL_SSC_EN_SHIFT                        12
+#define AM33XX_DPLL_SSC_EN_WIDTH                        1
 #define AM33XX_DPLL_SSC_EN_MASK                         (1 << 12)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT1_DIV_WIDTH              5
 #define AM33XX_HSDIVIDER_CLKOUT1_DIV_MASK               (0x1f << 0)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT1_DIVCHACK_MASK          (1 << 5)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK         (1 << 8)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT1_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT1_PWDN_MASK              (1 << 12)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_SHIFT              0
+#define AM33XX_HSDIVIDER_CLKOUT2_DIV_WIDTH              5
 #define AM33XX_HSDIVIDER_CLKOUT2_DIV_MASK               (0x1f << 0)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT2_DIVCHACK_MASK          (1 << 5)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK         (1 << 8)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT2_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT2_PWDN_MASK              (1 << 12)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_DIV_SHIFT              0
-#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x04 << 0)
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_WIDTH              5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIV_MASK               (0x1f << 0)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT         5
+#define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH         1
 #define AM33XX_HSDIVIDER_CLKOUT3_DIVCHACK_MASK          (1 << 5)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT        8
+#define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH        1
 #define AM33XX_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK         (1 << 8)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_SHIFT             12
+#define AM33XX_HSDIVIDER_CLKOUT3_PWDN_WIDTH             1
 #define AM33XX_HSDIVIDER_CLKOUT3_PWDN_MASK              (1 << 12)
 
 /*
@@ -522,11 +626,12 @@
  * CM_GFX_MMUCFG_CLKCTRL, CM_GFX_MMUDATA_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL
  */
 #define AM33XX_IDLEST_SHIFT                             16
+#define AM33XX_IDLEST_WIDTH                             2
 #define AM33XX_IDLEST_MASK                              (0x3 << 16)
-#define AM33XX_IDLEST_VAL                               0x3
 
 /* Used by CM_MAC_CLKSEL */
 #define AM33XX_MII_CLK_SEL_SHIFT                        2
+#define AM33XX_MII_CLK_SEL_WIDTH                        1
 #define AM33XX_MII_CLK_SEL_MASK                         (1 << 2)
 
 /*
@@ -535,7 +640,8 @@
  * CM_SSC_MODFREQDIV_DPLL_PER
  */
 #define AM33XX_MODFREQDIV_EXPONENT_SHIFT                8
-#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x10 << 8)
+#define AM33XX_MODFREQDIV_EXPONENT_WIDTH                3
+#define AM33XX_MODFREQDIV_EXPONENT_MASK                 (0x7 << 8)
 
 /*
  * Used by CM_SSC_MODFREQDIV_DPLL_CORE, CM_SSC_MODFREQDIV_DPLL_DDR,
@@ -543,7 +649,8 @@
  * CM_SSC_MODFREQDIV_DPLL_PER
  */
 #define AM33XX_MODFREQDIV_MANTISSA_SHIFT                0
-#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x06 << 0)
+#define AM33XX_MODFREQDIV_MANTISSA_WIDTH                7
+#define AM33XX_MODFREQDIV_MANTISSA_MASK                 (0x7f << 0)
 
 /*
  * Used by CM_MPU_MPU_CLKCTRL, CM_RTC_RTC_CLKCTRL, CM_PER_AES0_CLKCTRL,
@@ -580,42 +687,52 @@
  * CM_CEFUSE_CEFUSE_CLKCTRL
  */
 #define AM33XX_MODULEMODE_SHIFT                         0
+#define AM33XX_MODULEMODE_WIDTH                         2
 #define AM33XX_MODULEMODE_MASK                          (0x3 << 0)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTCLK_DEBUG_CLKA_SHIFT                  30
+#define AM33XX_OPTCLK_DEBUG_CLKA_WIDTH                  1
 #define AM33XX_OPTCLK_DEBUG_CLKA_MASK                   (1 << 30)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_OPTFCLKEN_DBGSYSCLK_SHIFT                19
+#define AM33XX_OPTFCLKEN_DBGSYSCLK_WIDTH                1
 #define AM33XX_OPTFCLKEN_DBGSYSCLK_MASK                 (1 << 19)
 
 /* Used by CM_WKUP_GPIO0_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_SHIFT             18
+#define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_WIDTH             1
 #define AM33XX_OPTFCLKEN_GPIO0_GDBCLK_MASK              (1 << 18)
 
 /* Used by CM_PER_GPIO1_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_1_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO2_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_2_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO3_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_3_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO4_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_4_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO5_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_5_GDBCLK_MASK             (1 << 18)
 
 /* Used by CM_PER_GPIO6_CLKCTRL */
 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_SHIFT            18
+#define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_WIDTH            1
 #define AM33XX_OPTFCLKEN_GPIO_6_GDBCLK_MASK             (1 << 18)
 
 /*
@@ -627,25 +744,30 @@
  * CM_WKUP_WKUP_M3_CLKCTRL, CM_GFX_BITBLT_CLKCTRL, CM_GFX_GFX_CLKCTRL
  */
 #define AM33XX_STBYST_SHIFT                             18
+#define AM33XX_STBYST_WIDTH                             1
 #define AM33XX_STBYST_MASK                              (1 << 18)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKDIVSEL_SHIFT                  27
-#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x29 << 27)
+#define AM33XX_STM_PMD_CLKDIVSEL_WIDTH                  3
+#define AM33XX_STM_PMD_CLKDIVSEL_MASK                   (0x7 << 27)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_STM_PMD_CLKSEL_SHIFT                     22
-#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x23 << 22)
+#define AM33XX_STM_PMD_CLKSEL_WIDTH                     2
+#define AM33XX_STM_PMD_CLKSEL_MASK                      (0x3 << 22)
 
 /*
  * Used by CM_IDLEST_DPLL_CORE, CM_IDLEST_DPLL_DDR, CM_IDLEST_DPLL_DISP,
  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
  */
 #define AM33XX_ST_DPLL_CLK_SHIFT                        0
+#define AM33XX_ST_DPLL_CLK_WIDTH                        1
 #define AM33XX_ST_DPLL_CLK_MASK                         (1 << 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_PER */
 #define AM33XX_ST_DPLL_CLKDCOLDO_SHIFT                  8
+#define AM33XX_ST_DPLL_CLKDCOLDO_WIDTH                  1
 #define AM33XX_ST_DPLL_CLKDCOLDO_MASK                   (1 << 8)
 
 /*
@@ -653,18 +775,22 @@
  * CM_DIV_M2_DPLL_PER
  */
 #define AM33XX_ST_DPLL_CLKOUT_SHIFT                     9
+#define AM33XX_ST_DPLL_CLKOUT_WIDTH                     1
 #define AM33XX_ST_DPLL_CLKOUT_MASK                      (1 << 9)
 
 /* Used by CM_DIV_M4_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT1_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT1_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT1_MASK                (1 << 9)
 
 /* Used by CM_DIV_M5_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT2_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT2_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT2_MASK                (1 << 9)
 
 /* Used by CM_DIV_M6_DPLL_CORE */
 #define AM33XX_ST_HSDIVIDER_CLKOUT3_SHIFT               9
+#define AM33XX_ST_HSDIVIDER_CLKOUT3_WIDTH               1
 #define AM33XX_ST_HSDIVIDER_CLKOUT3_MASK                (1 << 9)
 
 /*
@@ -672,16 +798,20 @@
  * CM_IDLEST_DPLL_MPU, CM_IDLEST_DPLL_PER
  */
 #define AM33XX_ST_MN_BYPASS_SHIFT                       8
+#define AM33XX_ST_MN_BYPASS_WIDTH                       1
 #define AM33XX_ST_MN_BYPASS_MASK                        (1 << 8)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKDIVSEL_SHIFT                  24
-#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x26 << 24)
+#define AM33XX_TRC_PMD_CLKDIVSEL_WIDTH                  3
+#define AM33XX_TRC_PMD_CLKDIVSEL_MASK                   (0x7 << 24)
 
 /* Used by CM_WKUP_DEBUGSS_CLKCTRL */
 #define AM33XX_TRC_PMD_CLKSEL_SHIFT                     20
-#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x21 << 20)
+#define AM33XX_TRC_PMD_CLKSEL_WIDTH                     2
+#define AM33XX_TRC_PMD_CLKSEL_MASK                      (0x3 << 20)
 
 /* Used by CONTROL_SEC_CLK_CTRL */
+#define AM33XX_TIMER0_CLKSEL_WIDTH                      2
 #define AM33XX_TIMER0_CLKSEL_MASK                       (0x3 << 4)
 #endif
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h
index 975f6bda0e0b..59598ffd8783 100644
--- a/arch/arm/mach-omap2/cm-regbits-34xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-34xx.h
@@ -218,6 +218,8 @@
 #define OMAP3430_ST_MAILBOXES_MASK                      (1 << 7)
 #define OMAP3430_ST_OMAPCTRL_SHIFT                      6
 #define OMAP3430_ST_OMAPCTRL_MASK                       (1 << 6)
+#define OMAP3430_ST_SAD2D_SHIFT                         3
+#define OMAP3430_ST_SAD2D_MASK                          (1 << 3)
 #define OMAP3430_ST_SDMA_SHIFT                          2
 #define OMAP3430_ST_SDMA_MASK                           (1 << 2)
 #define OMAP3430_ST_SDRC_SHIFT                          1
diff --git a/arch/arm/mach-omap2/cm-regbits-44xx.h b/arch/arm/mach-omap2/cm-regbits-44xx.h
index 65597a745638..4c6c2f7de65b 100644
--- a/arch/arm/mach-omap2/cm-regbits-44xx.h
+++ b/arch/arm/mach-omap2/cm-regbits-44xx.h
@@ -1,7 +1,7 @@
 /*
  * OMAP44xx Clock Management register bits
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2012 Texas Instruments, Inc.
  * Copyright (C) 2009-2010 Nokia Corporation
  *
  * Paul Walmsley (paul@pwsan.com)
@@ -24,6 +24,7 @@
 
 /* Used by CM_L3_1_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_ABE_DYNDEP_SHIFT                               3
+#define OMAP4430_ABE_DYNDEP_WIDTH                               0x1
 #define OMAP4430_ABE_DYNDEP_MASK                                (1 << 3)
 
 /*
@@ -31,14 +32,17 @@
  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_ABE_STATDEP_SHIFT                              3
+#define OMAP4430_ABE_STATDEP_WIDTH                              0x1
 #define OMAP4430_ABE_STATDEP_MASK                               (1 << 3)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ALWONCORE_DYNDEP_SHIFT                         16
+#define OMAP4430_ALWONCORE_DYNDEP_WIDTH                         0x1
 #define OMAP4430_ALWONCORE_DYNDEP_MASK                          (1 << 16)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_ALWONCORE_STATDEP_SHIFT                        16
+#define OMAP4430_ALWONCORE_STATDEP_WIDTH                        0x1
 #define OMAP4430_ALWONCORE_STATDEP_MASK                         (1 << 16)
 
 /*
@@ -47,294 +51,367 @@
  * CM_AUTOIDLE_DPLL_PER, CM_AUTOIDLE_DPLL_UNIPRO, CM_AUTOIDLE_DPLL_USB
  */
 #define OMAP4430_AUTO_DPLL_MODE_SHIFT                           0
+#define OMAP4430_AUTO_DPLL_MODE_WIDTH                           0x3
 #define OMAP4430_AUTO_DPLL_MODE_MASK                            (0x7 << 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_CEFUSE_DYNDEP_SHIFT                            17
+#define OMAP4430_CEFUSE_DYNDEP_WIDTH                            0x1
 #define OMAP4430_CEFUSE_DYNDEP_MASK                             (1 << 17)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_TESLA_STATICDEP */
 #define OMAP4430_CEFUSE_STATDEP_SHIFT                           17
+#define OMAP4430_CEFUSE_STATDEP_WIDTH                           0x1
 #define OMAP4430_CEFUSE_STATDEP_MASK                            (1 << 17)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_SHIFT                13
+#define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_ABE_24M_GFCLK_MASK                 (1 << 13)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_SHIFT            12
+#define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_ABE_ALWON_32K_CLK_MASK             (1 << 12)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_SHIFT                   9
+#define OMAP4430_CLKACTIVITY_ABE_LP_CLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_LP_CLK_MASK                    (1 << 9)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_SHIFT                   11
+#define OMAP4430_CLKACTIVITY_ABE_SYSCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_SYSCLK_MASK                    (1 << 11)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_ABE_X2_CLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_ABE_X2_CLK_MASK                    (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_SHIFT                11
+#define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_DLL_CLK_MASK                 (1 << 11)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_SHIFT               12
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY1_CLK_MASK                (1 << 12)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_SHIFT               13
+#define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_ASYNC_PHY2_CLK_MASK                (1 << 13)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_SHIFT            9
+#define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_CAM_PHY_CTRL_GCLK_MASK             (1 << 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_SHIFT         12
+#define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_WIDTH         0x1
 #define OMAP4430_CLKACTIVITY_CORE_ALWON_32K_GFCLK_MASK          (1 << 12)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_SHIFT            9
+#define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_CORE_DPLL_EMU_CLK_MASK             (1 << 9)
 
 /* Used by CM_L4CFG_CLKSTCTRL */
 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_SHIFT                9
+#define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_WIDTH                0x1
 #define OMAP4460_CLKACTIVITY_CORE_TS_GFCLK_MASK                 (1 << 9)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_SHIFT           9
+#define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_CUST_EFUSE_SYS_CLK_MASK            (1 << 9)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DLL_CLK_SHIFT                      9
+#define OMAP4430_CLKACTIVITY_DLL_CLK_WIDTH                      0x1
 #define OMAP4430_CLKACTIVITY_DLL_CLK_MASK                       (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_SHIFT                  9
+#define OMAP4430_CLKACTIVITY_DMT10_GFCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DMT10_GFCLK_MASK                   (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_SHIFT                  10
+#define OMAP4430_CLKACTIVITY_DMT11_GFCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DMT11_GFCLK_MASK                   (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_SHIFT                   11
+#define OMAP4430_CLKACTIVITY_DMT2_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT2_GFCLK_MASK                    (1 << 11)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_SHIFT                   12
+#define OMAP4430_CLKACTIVITY_DMT3_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT3_GFCLK_MASK                    (1 << 12)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_SHIFT                   13
+#define OMAP4430_CLKACTIVITY_DMT4_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT4_GFCLK_MASK                    (1 << 13)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_SHIFT                   14
+#define OMAP4430_CLKACTIVITY_DMT9_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_DMT9_GFCLK_MASK                    (1 << 14)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_SHIFT            10
+#define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_DSS_ALWON_SYS_CLK_MASK             (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_SHIFT                     9
+#define OMAP4430_CLKACTIVITY_DSS_FCLK_WIDTH                     0x1
 #define OMAP4430_CLKACTIVITY_DSS_FCLK_MASK                      (1 << 9)
 
 /* Used by CM_DUCATI_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_SHIFT                  8
+#define OMAP4430_CLKACTIVITY_DUCATI_GCLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_DUCATI_GCLK_MASK                   (1 << 8)
 
 /* Used by CM_EMU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_SHIFT                  8
+#define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_WIDTH                  0x1
 #define OMAP4430_CLKACTIVITY_EMU_SYS_CLK_MASK                   (1 << 8)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_SHIFT                   10
+#define OMAP4430_CLKACTIVITY_FDIF_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_FDIF_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_SHIFT               15
+#define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_FUNC_12M_GFCLK_MASK                (1 << 15)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_FUNC_24M_GFCLK_MASK                (1 << 10)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_SHIFT         11
+#define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_WIDTH         0x1
 #define OMAP4430_CLKACTIVITY_HDMI_PHY_48MHZ_GFCLK_MASK          (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_SHIFT           20
+#define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P1_480M_GFCLK_MASK            (1 << 20)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_SHIFT                26
+#define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P1_GFCLK_MASK                 (1 << 26)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_SHIFT           21
+#define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_WIDTH           0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P2_480M_GFCLK_MASK            (1 << 21)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_SHIFT                27
+#define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_HSIC_P2_GFCLK_MASK                 (1 << 27)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_SHIFT              13
+#define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_INIT_48MC_GFCLK_MASK               (1 << 13)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_SHIFT               12
+#define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_48M_GFCLK_MASK                (1 << 12)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_SHIFT            28
+#define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_60M_P1_GFCLK_MASK             (1 << 28)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_SHIFT            29
+#define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_60M_P2_GFCLK_MASK             (1 << 29)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_96M_GFCLK_MASK                (1 << 11)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_SHIFT               16
+#define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSI_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_SHIFT            17
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC1_GFCLK_MASK             (1 << 17)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_SHIFT            18
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC2_GFCLK_MASK             (1 << 18)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_SHIFT            19
+#define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_INIT_HSMMC6_GFCLK_MASK             (1 << 19)
 
 /* Used by CM_CAM_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_SHIFT                     8
+#define OMAP4430_CLKACTIVITY_ISS_GCLK_WIDTH                     0x1
 #define OMAP4430_CLKACTIVITY_ISS_GCLK_MASK                      (1 << 8)
 
 /* Used by CM_IVAHD_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_IVAHD_ROOT_CLK_MASK                (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_SHIFT               10
+#define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_L3X2_D2D_GICLK_MASK                (1 << 10)
 
 /* Used by CM_L3_1_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L3_1_GICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L3_1_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_L3_2_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L3_2_GICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L3_2_GICLK_MASK                    (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_D2D_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_SDMA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_DMA_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_DSS_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_DSS_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_SHIFT                8
+#define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L3_EMIF_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L3_GFX_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_SHIFT                8
+#define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L3_INIT_GICLK_MASK                 (1 << 8)
 
 /* Used by CM_L3INSTR_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_L3_INSTR_GICLK_MASK                (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_SHIFT              8
+#define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L3_SECURE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_SHIFT                   8
+#define OMAP4430_CLKACTIVITY_L4_AO_ICLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_L4_AO_ICLK_MASK                    (1 << 8)
 
 /* Used by CM_CEFUSE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_SHIFT              8
+#define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L4_CEFUSE_GICLK_MASK               (1 << 8)
 
 /* Used by CM_L4CFG_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_CFG_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_D2D_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_SHIFT                 9
+#define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_D2D_GICLK_MASK                  (1 << 9)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L4_INIT_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_L4_PER_GICLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_L4_PER_GICLK_MASK                  (1 << 8)
 
 /* Used by CM_L4SEC_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_SHIFT              9
+#define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_L4_SECURE_GICLK_MASK               (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_SHIFT                12
+#define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_L4_WKUP_GICLK_MASK                 (1 << 12)
 
 /* Used by CM_MPU_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_SHIFT                 8
+#define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_MPU_DPLL_CLK_MASK                  (1 << 8)
 
 /* Used by CM1_ABE_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_OCP_ABE_GICLK_MASK                 (1 << 9)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_SHIFT               16
+#define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_PER_24MC_GFCLK_MASK                (1 << 16)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_SHIFT                17
+#define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_32K_GFCLK_MASK                 (1 << 17)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_SHIFT                18
+#define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_48M_GFCLK_MASK                 (1 << 18)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_SHIFT                19
+#define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_96M_GFCLK_MASK                 (1 << 19)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_SHIFT            25
+#define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_WIDTH            0x1
 #define OMAP4430_CLKACTIVITY_PER_ABE_24M_GFCLK_MASK             (1 << 25)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_SHIFT             20
+#define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_WIDTH             0x1
 #define OMAP4430_CLKACTIVITY_PER_MCASP2_GFCLK_MASK              (1 << 20)
 
 /* Used by CM_L4PER_CLKSTCTRL */
@@ -343,94 +420,114 @@
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_SHIFT             22
+#define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_WIDTH             0x1
 #define OMAP4430_CLKACTIVITY_PER_MCBSP4_GFCLK_MASK              (1 << 22)
 
 /* Used by CM_L4PER_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_SHIFT                24
+#define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_PER_SYS_GFCLK_MASK                 (1 << 24)
 
 /* Used by CM_MEMIF_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_SHIFT                 10
+#define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_PHY_ROOT_CLK_MASK                  (1 << 10)
 
 /* Used by CM_GFX_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_SHIFT                    9
+#define OMAP4430_CLKACTIVITY_SGX_GFCLK_WIDTH                    0x1
 #define OMAP4430_CLKACTIVITY_SGX_GFCLK_MASK                     (1 << 9)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_SR_CORE_SYSCLK_MASK                (1 << 11)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_SHIFT                10
+#define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_SR_IVA_SYSCLK_MASK                 (1 << 10)
 
 /* Used by CM_ALWON_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_SHIFT                9
+#define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_SR_MPU_SYSCLK_MASK                 (1 << 9)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_SYS_CLK_SHIFT                      8
+#define OMAP4430_CLKACTIVITY_SYS_CLK_WIDTH                      0x1
 #define OMAP4430_CLKACTIVITY_SYS_CLK_MASK                       (1 << 8)
 
 /* Used by CM_TESLA_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_SHIFT               8
+#define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_TESLA_ROOT_CLK_MASK                (1 << 8)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_SHIFT                22
+#define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH0_GFCLK_MASK                 (1 << 22)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_SHIFT                23
+#define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH1_GFCLK_MASK                 (1 << 23)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_SHIFT                24
+#define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_TLL_CH2_GFCLK_MASK                 (1 << 24)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_SHIFT              10
+#define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_UNIPRO_DPLL_CLK_MASK               (1 << 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_SHIFT                 14
+#define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_WIDTH                 0x1
 #define OMAP4430_CLKACTIVITY_USB_DPLL_CLK_MASK                  (1 << 14)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_SHIFT              15
+#define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_USB_DPLL_HS_CLK_MASK               (1 << 15)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_SHIFT                   10
+#define OMAP4430_CLKACTIVITY_USIM_GFCLK_WIDTH                   0x1
 #define OMAP4430_CLKACTIVITY_USIM_GFCLK_MASK                    (1 << 10)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_SHIFT                30
+#define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_WIDTH                0x1
 #define OMAP4430_CLKACTIVITY_UTMI_P3_GFCLK_MASK                 (1 << 30)
 
 /* Used by CM_L3INIT_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_SHIFT              25
+#define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_WIDTH              0x1
 #define OMAP4430_CLKACTIVITY_UTMI_ROOT_GFCLK_MASK               (1 << 25)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_SHIFT               11
+#define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_WIDTH               0x1
 #define OMAP4430_CLKACTIVITY_WKUP_32K_GFCLK_MASK                (1 << 11)
 
 /* Used by CM_WKUP_CLKSTCTRL */
 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_SHIFT                13
+#define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_WIDTH                0x1
 #define OMAP4460_CLKACTIVITY_WKUP_TS_GFCLK_MASK                 (1 << 13)
 
 /*
  * Used by CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL,
  * CM1_ABE_TIMER7_CLKCTRL, CM1_ABE_TIMER8_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
- * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_MMC6_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L4PER_DMTIMER10_CLKCTRL,
  * CM_L4PER_DMTIMER11_CLKCTRL, CM_L4PER_DMTIMER2_CLKCTRL,
  * CM_L4PER_DMTIMER3_CLKCTRL, CM_L4PER_DMTIMER4_CLKCTRL,
- * CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL, CM_L4PER_MCASP3_CLKCTRL,
- * CM_WKUP_TIMER1_CLKCTRL
+ * CM_L4PER_DMTIMER9_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SHIFT                                   24
+#define OMAP4430_CLKSEL_WIDTH                                   0x1
 #define OMAP4430_CLKSEL_MASK                                    (1 << 24)
 
 /*
@@ -438,50 +535,62 @@
  * CM_CLKSEL_DUCATI_ISS_ROOT, CM_CLKSEL_USB_60MHZ, CM_L4_WKUP_CLKSEL
  */
 #define OMAP4430_CLKSEL_0_0_SHIFT                               0
+#define OMAP4430_CLKSEL_0_0_WIDTH                               0x1
 #define OMAP4430_CLKSEL_0_0_MASK                                (1 << 0)
 
 /* Renamed from CLKSEL Used by CM_BYPCLK_DPLL_IVA, CM_BYPCLK_DPLL_MPU */
 #define OMAP4430_CLKSEL_0_1_SHIFT                               0
+#define OMAP4430_CLKSEL_0_1_WIDTH                               0x2
 #define OMAP4430_CLKSEL_0_1_MASK                                (0x3 << 0)
 
 /* Renamed from CLKSEL Used by CM_L3INIT_HSI_CLKCTRL */
 #define OMAP4430_CLKSEL_24_25_SHIFT                             24
+#define OMAP4430_CLKSEL_24_25_WIDTH                             0x2
 #define OMAP4430_CLKSEL_24_25_MASK                              (0x3 << 24)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_CLKSEL_60M_SHIFT                               24
+#define OMAP4430_CLKSEL_60M_WIDTH                               0x1
 #define OMAP4430_CLKSEL_60M_MASK                                (1 << 24)
 
 /* Used by CM_MPU_MPU_CLKCTRL */
 #define OMAP4460_CLKSEL_ABE_DIV_MODE_SHIFT                      25
+#define OMAP4460_CLKSEL_ABE_DIV_MODE_WIDTH                      0x1
 #define OMAP4460_CLKSEL_ABE_DIV_MODE_MASK                       (1 << 25)
 
 /* Used by CM1_ABE_AESS_CLKCTRL */
 #define OMAP4430_CLKSEL_AESS_FCLK_SHIFT                         24
+#define OMAP4430_CLKSEL_AESS_FCLK_WIDTH                         0x1
 #define OMAP4430_CLKSEL_AESS_FCLK_MASK                          (1 << 24)
 
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_CORE_SHIFT                              0
+#define OMAP4430_CLKSEL_CORE_WIDTH                              0x1
 #define OMAP4430_CLKSEL_CORE_MASK                               (1 << 0)
 
 /* Renamed from CLKSEL_CORE Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_CORE_1_1_SHIFT                          1
+#define OMAP4430_CLKSEL_CORE_1_1_WIDTH                          0x1
 #define OMAP4430_CLKSEL_CORE_1_1_MASK                           (1 << 1)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_CLKSEL_DIV_SHIFT                               24
+#define OMAP4430_CLKSEL_DIV_WIDTH                               0x1
 #define OMAP4430_CLKSEL_DIV_MASK                                (1 << 24)
 
 /* Used by CM_MPU_MPU_CLKCTRL */
 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_SHIFT                     24
+#define OMAP4460_CLKSEL_EMIF_DIV_MODE_WIDTH                     0x1
 #define OMAP4460_CLKSEL_EMIF_DIV_MODE_MASK                      (1 << 24)
 
 /* Used by CM_CAM_FDIF_CLKCTRL */
 #define OMAP4430_CLKSEL_FCLK_SHIFT                              24
+#define OMAP4430_CLKSEL_FCLK_WIDTH                              0x2
 #define OMAP4430_CLKSEL_FCLK_MASK                               (0x3 << 24)
 
 /* Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_SHIFT                   25
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_WIDTH                   0x1
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_MASK                    (1 << 25)
 
 /*
@@ -490,34 +599,42 @@
  * CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_SHIFT      26
+#define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_WIDTH      0x2
 #define OMAP4430_CLKSEL_INTERNAL_SOURCE_CM1_ABE_DMIC_MASK       (0x3 << 26)
 
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L3_SHIFT                                4
+#define OMAP4430_CLKSEL_L3_WIDTH                                0x1
 #define OMAP4430_CLKSEL_L3_MASK                                 (1 << 4)
 
 /* Renamed from CLKSEL_L3 Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_CLKSEL_L3_SHADOW_SHIFT                         2
+#define OMAP4430_CLKSEL_L3_SHADOW_WIDTH                         0x1
 #define OMAP4430_CLKSEL_L3_SHADOW_MASK                          (1 << 2)
 
 /* Used by CM_CLKSEL_CORE */
 #define OMAP4430_CLKSEL_L4_SHIFT                                8
+#define OMAP4430_CLKSEL_L4_WIDTH                                0x1
 #define OMAP4430_CLKSEL_L4_MASK                                 (1 << 8)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_CLKSEL_OPP_SHIFT                               0
+#define OMAP4430_CLKSEL_OPP_WIDTH                               0x2
 #define OMAP4430_CLKSEL_OPP_MASK                                (0x3 << 0)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_STM_CLK_SHIFT                       27
+#define OMAP4430_CLKSEL_PMD_STM_CLK_WIDTH                       0x3
 #define OMAP4430_CLKSEL_PMD_STM_CLK_MASK                        (0x7 << 27)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_SHIFT                     24
+#define OMAP4430_CLKSEL_PMD_TRACE_CLK_WIDTH                     0x3
 #define OMAP4430_CLKSEL_PMD_TRACE_CLK_MASK                      (0x7 << 24)
 
 /* Used by CM_GFX_GFX_CLKCTRL */
 #define OMAP4430_CLKSEL_SGX_FCLK_SHIFT                          24
+#define OMAP4430_CLKSEL_SGX_FCLK_WIDTH                          0x1
 #define OMAP4430_CLKSEL_SGX_FCLK_MASK                           (1 << 24)
 
 /*
@@ -525,18 +642,22 @@
  * CM1_ABE_MCBSP2_CLKCTRL, CM1_ABE_MCBSP3_CLKCTRL
  */
 #define OMAP4430_CLKSEL_SOURCE_SHIFT                            24
+#define OMAP4430_CLKSEL_SOURCE_WIDTH                            0x2
 #define OMAP4430_CLKSEL_SOURCE_MASK                             (0x3 << 24)
 
 /* Renamed from CLKSEL_SOURCE Used by CM_L4PER_MCBSP4_CLKCTRL */
 #define OMAP4430_CLKSEL_SOURCE_24_24_SHIFT                      24
+#define OMAP4430_CLKSEL_SOURCE_24_24_WIDTH                      0x1
 #define OMAP4430_CLKSEL_SOURCE_24_24_MASK                       (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P1_SHIFT                           24
+#define OMAP4430_CLKSEL_UTMI_P1_WIDTH                           0x1
 #define OMAP4430_CLKSEL_UTMI_P1_MASK                            (1 << 24)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_CLKSEL_UTMI_P2_SHIFT                           25
+#define OMAP4430_CLKSEL_UTMI_P2_WIDTH                           0x1
 #define OMAP4430_CLKSEL_UTMI_P2_MASK                            (1 << 25)
 
 /*
@@ -549,30 +670,37 @@
  * CM_TESLA_CLKSTCTRL, CM_WKUP_CLKSTCTRL
  */
 #define OMAP4430_CLKTRCTRL_SHIFT                                0
+#define OMAP4430_CLKTRCTRL_WIDTH                                0x2
 #define OMAP4430_CLKTRCTRL_MASK                                 (0x3 << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_DIV_SHIFT                        0
+#define OMAP4430_CORE_DPLL_EMU_DIV_WIDTH                        0x7
 #define OMAP4430_CORE_DPLL_EMU_DIV_MASK                         (0x7f << 0)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_CORE_DPLL_EMU_MULT_SHIFT                       8
+#define OMAP4430_CORE_DPLL_EMU_MULT_WIDTH                       0xb
 #define OMAP4430_CORE_DPLL_EMU_MULT_MASK                        (0x7ff << 8)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_CUSTOM_SHIFT                                   6
+#define OMAP4430_CUSTOM_WIDTH                                   0x2
 #define OMAP4430_CUSTOM_MASK                                    (0x3 << 6)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_D2D_DYNDEP_SHIFT                               18
+#define OMAP4430_D2D_DYNDEP_WIDTH                               0x1
 #define OMAP4430_D2D_DYNDEP_MASK                                (1 << 18)
 
 /* Used by CM_MPU_STATICDEP */
 #define OMAP4430_D2D_STATDEP_SHIFT                              18
+#define OMAP4430_D2D_STATDEP_WIDTH                              0x1
 #define OMAP4430_D2D_STATDEP_MASK                               (1 << 18)
 
 /* Used by CM_CLKSEL_DPLL_MPU */
 #define OMAP4460_DCC_COUNT_MAX_SHIFT                            24
+#define OMAP4460_DCC_COUNT_MAX_WIDTH                            0x8
 #define OMAP4460_DCC_COUNT_MAX_MASK                             (0xff << 24)
 
 /* Used by CM_CLKSEL_DPLL_MPU */
@@ -586,22 +714,27 @@
  * CM_SSC_DELTAMSTEP_DPLL_UNIPRO, CM_SSC_DELTAMSTEP_DPLL_USB
  */
 #define OMAP4430_DELTAMSTEP_SHIFT                               0
+#define OMAP4430_DELTAMSTEP_WIDTH                               0x14
 #define OMAP4430_DELTAMSTEP_MASK                                (0xfffff << 0)
 
 /* Renamed from DELTAMSTEP Used by CM_SSC_DELTAMSTEP_DPLL_USB */
 #define OMAP4460_DELTAMSTEP_0_20_SHIFT                          0
+#define OMAP4460_DELTAMSTEP_0_20_WIDTH                          0x15
 #define OMAP4460_DELTAMSTEP_0_20_MASK                           (0x1fffff << 0)
 
 /* Used by CM_DLL_CTRL */
 #define OMAP4430_DLL_OVERRIDE_SHIFT                             0
+#define OMAP4430_DLL_OVERRIDE_WIDTH                             0x1
 #define OMAP4430_DLL_OVERRIDE_MASK                              (1 << 0)
 
 /* Renamed from DLL_OVERRIDE Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DLL_OVERRIDE_2_2_SHIFT                         2
+#define OMAP4430_DLL_OVERRIDE_2_2_WIDTH                         0x1
 #define OMAP4430_DLL_OVERRIDE_2_2_MASK                          (1 << 2)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DLL_RESET_SHIFT                                3
+#define OMAP4430_DLL_RESET_WIDTH                                0x1
 #define OMAP4430_DLL_RESET_MASK                                 (1 << 3)
 
 /*
@@ -610,30 +743,37 @@
  * CM_CLKSEL_DPLL_UNIPRO, CM_CLKSEL_DPLL_USB
  */
 #define OMAP4430_DPLL_BYP_CLKSEL_SHIFT                          23
+#define OMAP4430_DPLL_BYP_CLKSEL_WIDTH                          0x1
 #define OMAP4430_DPLL_BYP_CLKSEL_MASK                           (1 << 23)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_SHIFT                 8
+#define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_WIDTH                 0x1
 #define OMAP4430_DPLL_CLKDCOLDO_GATE_CTRL_MASK                  (1 << 8)
 
 /* Used by CM_CLKSEL_DPLL_CORE */
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_SHIFT                    20
+#define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_WIDTH                    0x1
 #define OMAP4430_DPLL_CLKOUTHIF_CLKSEL_MASK                     (1 << 20)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_SHIFT                       0
+#define OMAP4430_DPLL_CLKOUTHIF_DIV_WIDTH                       0x5
 #define OMAP4430_DPLL_CLKOUTHIF_DIV_MASK                        (0x1f << 0)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_SHIFT                  5
+#define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_WIDTH                  0x1
 #define OMAP4430_DPLL_CLKOUTHIF_DIVCHACK_MASK                   (1 << 5)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_SHIFT                 8
+#define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_WIDTH                 0x1
 #define OMAP4430_DPLL_CLKOUTHIF_GATE_CTRL_MASK                  (1 << 8)
 
 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_SHIFT                  10
+#define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_WIDTH                  0x1
 #define OMAP4430_DPLL_CLKOUTX2_GATE_CTRL_MASK                   (1 << 10)
 
 /*
@@ -641,10 +781,12 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIV_SHIFT                          0
+#define OMAP4430_DPLL_CLKOUT_DIV_WIDTH                          0x5
 #define OMAP4430_DPLL_CLKOUT_DIV_MASK                           (0x1f << 0)
 
 /* Renamed from DPLL_CLKOUT_DIV Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_SHIFT                      0
+#define OMAP4430_DPLL_CLKOUT_DIV_0_6_WIDTH                      0x7
 #define OMAP4430_DPLL_CLKOUT_DIV_0_6_MASK                       (0x7f << 0)
 
 /*
@@ -652,10 +794,12 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_SHIFT                     5
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_WIDTH                     0x1
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_MASK                      (1 << 5)
 
 /* Renamed from DPLL_CLKOUT_DIVCHACK Used by CM_DIV_M2_DPLL_USB */
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_SHIFT              7
+#define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_WIDTH              0x1
 #define OMAP4430_DPLL_CLKOUT_DIVCHACK_M2_USB_MASK               (1 << 7)
 
 /*
@@ -663,18 +807,22 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_SHIFT                    8
+#define OMAP4430_DPLL_CLKOUT_GATE_CTRL_WIDTH                    0x1
 #define OMAP4430_DPLL_CLKOUT_GATE_CTRL_MASK                     (1 << 8)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_DPLL_EN_SHIFT                        8
+#define OMAP4430_DPLL_CORE_DPLL_EN_WIDTH                        0x3
 #define OMAP4430_DPLL_CORE_DPLL_EN_MASK                         (0x7 << 8)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_DPLL_CORE_M2_DIV_SHIFT                         11
+#define OMAP4430_DPLL_CORE_M2_DIV_WIDTH                         0x5
 #define OMAP4430_DPLL_CORE_M2_DIV_MASK                          (0x1f << 11)
 
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_DPLL_CORE_M5_DIV_SHIFT                         3
+#define OMAP4430_DPLL_CORE_M5_DIV_WIDTH                         0x5
 #define OMAP4430_DPLL_CORE_M5_DIV_MASK                          (0x1f << 3)
 
 /*
@@ -683,10 +831,12 @@
  * CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_DIV_SHIFT                                 0
+#define OMAP4430_DPLL_DIV_WIDTH                                 0x7
 #define OMAP4430_DPLL_DIV_MASK                                  (0x7f << 0)
 
 /* Renamed from DPLL_DIV Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_DIV_0_7_SHIFT                             0
+#define OMAP4430_DPLL_DIV_0_7_WIDTH                             0x8
 #define OMAP4430_DPLL_DIV_0_7_MASK                              (0xff << 0)
 
 /*
@@ -694,10 +844,12 @@
  * CM_CLKMODE_DPLL_IVA, CM_CLKMODE_DPLL_MPU, CM_CLKMODE_DPLL_PER
  */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_SHIFT                       8
+#define OMAP4430_DPLL_DRIFTGUARD_EN_WIDTH                       0x1
 #define OMAP4430_DPLL_DRIFTGUARD_EN_MASK                        (1 << 8)
 
 /* Renamed from DPLL_DRIFTGUARD_EN Used by CM_CLKMODE_DPLL_UNIPRO */
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_SHIFT                   3
+#define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_WIDTH                   0x1
 #define OMAP4430_DPLL_DRIFTGUARD_EN_3_3_MASK                    (1 << 3)
 
 /*
@@ -706,6 +858,7 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_EN_SHIFT                                  0
+#define OMAP4430_DPLL_EN_WIDTH                                  0x3
 #define OMAP4430_DPLL_EN_MASK                                   (0x7 << 0)
 
 /*
@@ -714,6 +867,7 @@
  * CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_LPMODE_EN_SHIFT                           10
+#define OMAP4430_DPLL_LPMODE_EN_WIDTH                           0x1
 #define OMAP4430_DPLL_LPMODE_EN_MASK                            (1 << 10)
 
 /*
@@ -722,10 +876,12 @@
  * CM_CLKSEL_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_MULT_SHIFT                                8
+#define OMAP4430_DPLL_MULT_WIDTH                                0xb
 #define OMAP4430_DPLL_MULT_MASK                                 (0x7ff << 8)
 
 /* Renamed from DPLL_MULT Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_MULT_USB_SHIFT                            8
+#define OMAP4430_DPLL_MULT_USB_WIDTH                            0xc
 #define OMAP4430_DPLL_MULT_USB_MASK                             (0xfff << 8)
 
 /*
@@ -734,10 +890,12 @@
  * CM_CLKMODE_DPLL_UNIPRO
  */
 #define OMAP4430_DPLL_REGM4XEN_SHIFT                            11
+#define OMAP4430_DPLL_REGM4XEN_WIDTH                            0x1
 #define OMAP4430_DPLL_REGM4XEN_MASK                             (1 << 11)
 
 /* Used by CM_CLKSEL_DPLL_USB */
 #define OMAP4430_DPLL_SD_DIV_SHIFT                              24
+#define OMAP4430_DPLL_SD_DIV_WIDTH                              0x8
 #define OMAP4430_DPLL_SD_DIV_MASK                               (0xff << 24)
 
 /*
@@ -746,6 +904,7 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_ACK_SHIFT                             13
+#define OMAP4430_DPLL_SSC_ACK_WIDTH                             0x1
 #define OMAP4430_DPLL_SSC_ACK_MASK                              (1 << 13)
 
 /*
@@ -754,6 +913,7 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_SHIFT                      14
+#define OMAP4430_DPLL_SSC_DOWNSPREAD_WIDTH                      0x1
 #define OMAP4430_DPLL_SSC_DOWNSPREAD_MASK                       (1 << 14)
 
 /*
@@ -762,42 +922,52 @@
  * CM_CLKMODE_DPLL_UNIPRO, CM_CLKMODE_DPLL_USB
  */
 #define OMAP4430_DPLL_SSC_EN_SHIFT                              12
+#define OMAP4430_DPLL_SSC_EN_WIDTH                              0x1
 #define OMAP4430_DPLL_SSC_EN_MASK                               (1 << 12)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_DSS_DYNDEP_SHIFT                               8
+#define OMAP4430_DSS_DYNDEP_WIDTH                               0x1
 #define OMAP4430_DSS_DYNDEP_MASK                                (1 << 8)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DSS_STATDEP_SHIFT                              8
+#define OMAP4430_DSS_STATDEP_WIDTH                              0x1
 #define OMAP4430_DSS_STATDEP_MASK                               (1 << 8)
 
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_DUCATI_DYNDEP_SHIFT                            0
+#define OMAP4430_DUCATI_DYNDEP_WIDTH                            0x1
 #define OMAP4430_DUCATI_DYNDEP_MASK                             (1 << 0)
 
 /* Used by CM_MPU_STATICDEP, CM_SDMA_STATICDEP */
 #define OMAP4430_DUCATI_STATDEP_SHIFT                           0
+#define OMAP4430_DUCATI_STATDEP_WIDTH                           0x1
 #define OMAP4430_DUCATI_STATDEP_MASK                            (1 << 0)
 
 /* Used by CM_SHADOW_FREQ_CONFIG1 */
 #define OMAP4430_FREQ_UPDATE_SHIFT                              0
+#define OMAP4430_FREQ_UPDATE_WIDTH                              0x1
 #define OMAP4430_FREQ_UPDATE_MASK                               (1 << 0)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_FUNC_SHIFT                                     16
+#define OMAP4430_FUNC_WIDTH                                     0xc
 #define OMAP4430_FUNC_MASK                                      (0xfff << 16)
 
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_GFX_DYNDEP_SHIFT                               10
+#define OMAP4430_GFX_DYNDEP_WIDTH                               0x1
 #define OMAP4430_GFX_DYNDEP_MASK                                (1 << 10)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_GFX_STATDEP_SHIFT                              10
+#define OMAP4430_GFX_STATDEP_WIDTH                              0x1
 #define OMAP4430_GFX_STATDEP_MASK                               (1 << 10)
 
 /* Used by CM_SHADOW_FREQ_CONFIG2 */
 #define OMAP4430_GPMC_FREQ_UPDATE_SHIFT                         0
+#define OMAP4430_GPMC_FREQ_UPDATE_WIDTH                         0x1
 #define OMAP4430_GPMC_FREQ_UPDATE_MASK                          (1 << 0)
 
 /*
@@ -805,6 +975,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIV_MASK                     (0x1f << 0)
 
 /*
@@ -812,6 +983,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_DIVCHACK_MASK                (1 << 5)
 
 /*
@@ -819,6 +991,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_GATE_CTRL_MASK               (1 << 8)
 
 /*
@@ -826,6 +999,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT1_PWDN_MASK                    (1 << 12)
 
 /*
@@ -833,6 +1007,7 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIV_MASK                     (0x1f << 0)
 
 /*
@@ -840,6 +1015,7 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_DIVCHACK_MASK                (1 << 5)
 
 /*
@@ -847,6 +1023,7 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_GATE_CTRL_MASK               (1 << 8)
 
 /*
@@ -854,38 +1031,47 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT2_PWDN_MASK                    (1 << 12)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIV_MASK                     (0x1f << 0)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_DIVCHACK_MASK                (1 << 5)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_GATE_CTRL_MASK               (1 << 8)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT3_PWDN_MASK                    (1 << 12)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_SHIFT                    0
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIV_WIDTH                    0x5
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIV_MASK                     (0x1f << 0)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_SHIFT               5
+#define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_WIDTH               0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_DIVCHACK_MASK                (1 << 5)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_SHIFT              8
+#define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_WIDTH              0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_GATE_CTRL_MASK               (1 << 8)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_SHIFT                   12
+#define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_WIDTH                   0x1
 #define OMAP4430_HSDIVIDER_CLKOUT4_PWDN_MASK                    (1 << 12)
 
 /*
@@ -893,53 +1079,48 @@
  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
- * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
+ * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
+ * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
+ * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
- * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
- * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
- * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
- * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
- * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
- * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
- * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
- * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
- * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
- * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
- * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
+ * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_IDLEST_SHIFT                                   16
+#define OMAP4430_IDLEST_WIDTH                                   0x2
 #define OMAP4430_IDLEST_MASK                                    (0x3 << 16)
 
 /* Used by CM_DUCATI_DYNAMICDEP, CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_ISS_DYNDEP_SHIFT                               9
+#define OMAP4430_ISS_DYNDEP_WIDTH                               0x1
 #define OMAP4430_ISS_DYNDEP_MASK                                (1 << 9)
 
 /*
@@ -947,10 +1128,12 @@
  * CM_TESLA_STATICDEP
  */
 #define OMAP4430_ISS_STATDEP_SHIFT                              9
+#define OMAP4430_ISS_STATDEP_WIDTH                              0x1
 #define OMAP4430_ISS_STATDEP_MASK                               (1 << 9)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_TESLA_DYNAMICDEP */
 #define OMAP4430_IVAHD_DYNDEP_SHIFT                             2
+#define OMAP4430_IVAHD_DYNDEP_WIDTH                             0x1
 #define OMAP4430_IVAHD_DYNDEP_MASK                              (1 << 2)
 
 /*
@@ -959,10 +1142,12 @@
  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_IVAHD_STATDEP_SHIFT                            2
+#define OMAP4430_IVAHD_STATDEP_WIDTH                            0x1
 #define OMAP4430_IVAHD_STATDEP_MASK                             (1 << 2)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4CFG_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L3INIT_DYNDEP_SHIFT                            7
+#define OMAP4430_L3INIT_DYNDEP_WIDTH                            0x1
 #define OMAP4430_L3INIT_DYNDEP_MASK                             (1 << 7)
 
 /*
@@ -970,6 +1155,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3INIT_STATDEP_SHIFT                           7
+#define OMAP4430_L3INIT_STATDEP_WIDTH                           0x1
 #define OMAP4430_L3INIT_STATDEP_MASK                            (1 << 7)
 
 /*
@@ -977,6 +1163,7 @@
  * CM_L4CFG_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_L3_1_DYNDEP_SHIFT                              5
+#define OMAP4430_L3_1_DYNDEP_WIDTH                              0x1
 #define OMAP4430_L3_1_DYNDEP_MASK                               (1 << 5)
 
 /*
@@ -986,6 +1173,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_1_STATDEP_SHIFT                             5
+#define OMAP4430_L3_1_STATDEP_WIDTH                             0x1
 #define OMAP4430_L3_1_STATDEP_MASK                              (1 << 5)
 
 /*
@@ -995,6 +1183,7 @@
  * CM_L4SEC_DYNAMICDEP, CM_SDMA_DYNAMICDEP
  */
 #define OMAP4430_L3_2_DYNDEP_SHIFT                              6
+#define OMAP4430_L3_2_DYNDEP_WIDTH                              0x1
 #define OMAP4430_L3_2_DYNDEP_MASK                               (1 << 6)
 
 /*
@@ -1004,10 +1193,12 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L3_2_STATDEP_SHIFT                             6
+#define OMAP4430_L3_2_STATDEP_WIDTH                             0x1
 #define OMAP4430_L3_2_STATDEP_MASK                              (1 << 6)
 
 /* Used by CM_L3_1_DYNAMICDEP */
 #define OMAP4430_L4CFG_DYNDEP_SHIFT                             12
+#define OMAP4430_L4CFG_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4CFG_DYNDEP_MASK                              (1 << 12)
 
 /*
@@ -1015,10 +1206,12 @@
  * CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4CFG_STATDEP_SHIFT                            12
+#define OMAP4430_L4CFG_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4CFG_STATDEP_MASK                             (1 << 12)
 
 /* Used by CM_L3_2_DYNAMICDEP */
 #define OMAP4430_L4PER_DYNDEP_SHIFT                             13
+#define OMAP4430_L4PER_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4PER_DYNDEP_MASK                              (1 << 13)
 
 /*
@@ -1026,10 +1219,12 @@
  * CM_L4SEC_STATICDEP, CM_MPU_STATICDEP, CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4PER_STATDEP_SHIFT                            13
+#define OMAP4430_L4PER_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4PER_STATDEP_MASK                             (1 << 13)
 
 /* Used by CM_L3_2_DYNAMICDEP, CM_L4PER_DYNAMICDEP */
 #define OMAP4430_L4SEC_DYNDEP_SHIFT                             14
+#define OMAP4430_L4SEC_DYNDEP_WIDTH                             0x1
 #define OMAP4430_L4SEC_DYNDEP_MASK                              (1 << 14)
 
 /*
@@ -1037,10 +1232,12 @@
  * CM_SDMA_STATICDEP
  */
 #define OMAP4430_L4SEC_STATDEP_SHIFT                            14
+#define OMAP4430_L4SEC_STATDEP_WIDTH                            0x1
 #define OMAP4430_L4SEC_STATDEP_MASK                             (1 << 14)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_L4WKUP_DYNDEP_SHIFT                            15
+#define OMAP4430_L4WKUP_DYNDEP_WIDTH                            0x1
 #define OMAP4430_L4WKUP_DYNDEP_MASK                             (1 << 15)
 
 /*
@@ -1048,6 +1245,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_L4WKUP_STATDEP_SHIFT                           15
+#define OMAP4430_L4WKUP_STATDEP_WIDTH                           0x1
 #define OMAP4430_L4WKUP_STATDEP_MASK                            (1 << 15)
 
 /*
@@ -1055,6 +1253,7 @@
  * CM_MPU_DYNAMICDEP
  */
 #define OMAP4430_MEMIF_DYNDEP_SHIFT                             4
+#define OMAP4430_MEMIF_DYNDEP_WIDTH                             0x1
 #define OMAP4430_MEMIF_DYNDEP_MASK                              (1 << 4)
 
 /*
@@ -1064,6 +1263,7 @@
  * CM_SDMA_STATICDEP, CM_TESLA_STATICDEP
  */
 #define OMAP4430_MEMIF_STATDEP_SHIFT                            4
+#define OMAP4430_MEMIF_STATDEP_WIDTH                            0x1
 #define OMAP4430_MEMIF_STATDEP_MASK                             (1 << 4)
 
 /*
@@ -1073,6 +1273,7 @@
  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_EXPONENT_SHIFT                      8
+#define OMAP4430_MODFREQDIV_EXPONENT_WIDTH                      0x3
 #define OMAP4430_MODFREQDIV_EXPONENT_MASK                       (0x7 << 8)
 
 /*
@@ -1082,6 +1283,7 @@
  * CM_SSC_MODFREQDIV_DPLL_UNIPRO, CM_SSC_MODFREQDIV_DPLL_USB
  */
 #define OMAP4430_MODFREQDIV_MANTISSA_SHIFT                      0
+#define OMAP4430_MODFREQDIV_MANTISSA_WIDTH                      0x7
 #define OMAP4430_MODFREQDIV_MANTISSA_MASK                       (0x7f << 0)
 
 /*
@@ -1089,69 +1291,68 @@
  * CM1_ABE_MCASP_CLKCTRL, CM1_ABE_MCBSP1_CLKCTRL, CM1_ABE_MCBSP2_CLKCTRL,
  * CM1_ABE_MCBSP3_CLKCTRL, CM1_ABE_PDM_CLKCTRL, CM1_ABE_SLIMBUS_CLKCTRL,
  * CM1_ABE_TIMER5_CLKCTRL, CM1_ABE_TIMER6_CLKCTRL, CM1_ABE_TIMER7_CLKCTRL,
- * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_MDMINTC_CLKCTRL,
- * CM_ALWON_SR_CORE_CLKCTRL, CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL,
- * CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL,
- * CM_CM1_PROFILING_CLKCTRL, CM_CM2_PROFILING_CLKCTRL,
- * CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL, CM_D2D_SAD2D_FW_CLKCTRL,
- * CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM1_ABE_TIMER8_CLKCTRL, CM1_ABE_WDT3_CLKCTRL, CM_ALWON_SR_CORE_CLKCTRL,
+ * CM_ALWON_SR_IVA_CLKCTRL, CM_ALWON_SR_MPU_CLKCTRL, CM_CAM_FDIF_CLKCTRL,
+ * CM_CAM_ISS_CLKCTRL, CM_CEFUSE_CEFUSE_CLKCTRL, CM_CM1_PROFILING_CLKCTRL,
+ * CM_CM2_PROFILING_CLKCTRL, CM_D2D_MODEM_ICR_CLKCTRL, CM_D2D_SAD2D_CLKCTRL,
+ * CM_D2D_SAD2D_FW_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
  * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
- * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
- * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
- * CM_L3INIT_USBPHYOCP2SCP_CLKCTRL, CM_L3INIT_USB_HOST_CLKCTRL,
- * CM_L3INIT_USB_HOST_FS_CLKCTRL, CM_L3INIT_USB_OTG_CLKCTRL,
- * CM_L3INIT_USB_TLL_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL, CM_L3INSTR_L3_3_CLKCTRL,
- * CM_L3INSTR_L3_INSTR_CLKCTRL, CM_L3INSTR_OCP_WP1_CLKCTRL,
- * CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL, CM_L3_2_L3_2_CLKCTRL,
- * CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL, CM_L4CFG_L4_CFG_CLKCTRL,
- * CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL, CM_L4PER_ADC_CLKCTRL,
+ * CM_IVAHD_SL2_CLKCTRL, CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL,
+ * CM_L3INIT_MMC2_CLKCTRL, CM_L3INIT_USBPHYOCP2SCP_CLKCTRL,
+ * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL,
+ * CM_L3INSTR_L3_3_CLKCTRL, CM_L3INSTR_L3_INSTR_CLKCTRL,
+ * CM_L3INSTR_OCP_WP1_CLKCTRL, CM_L3_1_L3_1_CLKCTRL, CM_L3_2_GPMC_CLKCTRL,
+ * CM_L3_2_L3_2_CLKCTRL, CM_L3_2_OCMC_RAM_CLKCTRL, CM_L4CFG_HW_SEM_CLKCTRL,
+ * CM_L4CFG_L4_CFG_CLKCTRL, CM_L4CFG_MAILBOX_CLKCTRL, CM_L4CFG_SAR_ROM_CLKCTRL,
  * CM_L4PER_DMTIMER10_CLKCTRL, CM_L4PER_DMTIMER11_CLKCTRL,
  * CM_L4PER_DMTIMER2_CLKCTRL, CM_L4PER_DMTIMER3_CLKCTRL,
  * CM_L4PER_DMTIMER4_CLKCTRL, CM_L4PER_DMTIMER9_CLKCTRL, CM_L4PER_ELM_CLKCTRL,
  * CM_L4PER_GPIO2_CLKCTRL, CM_L4PER_GPIO3_CLKCTRL, CM_L4PER_GPIO4_CLKCTRL,
  * CM_L4PER_GPIO5_CLKCTRL, CM_L4PER_GPIO6_CLKCTRL, CM_L4PER_HDQ1W_CLKCTRL,
- * CM_L4PER_HECC1_CLKCTRL, CM_L4PER_HECC2_CLKCTRL, CM_L4PER_I2C1_CLKCTRL,
- * CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL, CM_L4PER_I2C4_CLKCTRL,
- * CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL, CM_L4PER_MCASP2_CLKCTRL,
- * CM_L4PER_MCASP3_CLKCTRL, CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL,
- * CM_L4PER_MCSPI2_CLKCTRL, CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL,
- * CM_L4PER_MGATE_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL, CM_L4PER_MMCSD4_CLKCTRL,
- * CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_MSPROHG_CLKCTRL,
- * CM_L4PER_SLIMBUS2_CLKCTRL, CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL,
- * CM_L4PER_UART3_CLKCTRL, CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL,
- * CM_L4SEC_AES2_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
+ * CM_L4PER_I2C1_CLKCTRL, CM_L4PER_I2C2_CLKCTRL, CM_L4PER_I2C3_CLKCTRL,
+ * CM_L4PER_I2C4_CLKCTRL, CM_L4PER_I2C5_CLKCTRL, CM_L4PER_L4PER_CLKCTRL,
+ * CM_L4PER_MCBSP4_CLKCTRL, CM_L4PER_MCSPI1_CLKCTRL, CM_L4PER_MCSPI2_CLKCTRL,
+ * CM_L4PER_MCSPI3_CLKCTRL, CM_L4PER_MCSPI4_CLKCTRL, CM_L4PER_MMCSD3_CLKCTRL,
+ * CM_L4PER_MMCSD4_CLKCTRL, CM_L4PER_MMCSD5_CLKCTRL, CM_L4PER_SLIMBUS2_CLKCTRL,
+ * CM_L4PER_UART1_CLKCTRL, CM_L4PER_UART2_CLKCTRL, CM_L4PER_UART3_CLKCTRL,
+ * CM_L4PER_UART4_CLKCTRL, CM_L4SEC_AES1_CLKCTRL, CM_L4SEC_AES2_CLKCTRL,
+ * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_L4SEC_DES3DES_CLKCTRL,
  * CM_L4SEC_PKAEIP29_CLKCTRL, CM_L4SEC_RNG_CLKCTRL, CM_L4SEC_SHA2MD51_CLKCTRL,
  * CM_MEMIF_DMM_CLKCTRL, CM_MEMIF_EMIF_1_CLKCTRL, CM_MEMIF_EMIF_2_CLKCTRL,
- * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MEMIF_EMIF_H1_CLKCTRL,
- * CM_MEMIF_EMIF_H2_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
+ * CM_MEMIF_EMIF_FW_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
  * CM_TESLA_TESLA_CLKCTRL, CM_WKUP_GPIO1_CLKCTRL, CM_WKUP_KEYBOARD_CLKCTRL,
- * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_RTC_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL,
- * CM_WKUP_SYNCTIMER_CLKCTRL, CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL,
- * CM_WKUP_USIM_CLKCTRL, CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
+ * CM_WKUP_L4WKUP_CLKCTRL, CM_WKUP_SARRAM_CLKCTRL, CM_WKUP_SYNCTIMER_CLKCTRL,
+ * CM_WKUP_TIMER12_CLKCTRL, CM_WKUP_TIMER1_CLKCTRL, CM_WKUP_USIM_CLKCTRL,
+ * CM_WKUP_WDT1_CLKCTRL, CM_WKUP_WDT2_CLKCTRL
  */
 #define OMAP4430_MODULEMODE_SHIFT                               0
+#define OMAP4430_MODULEMODE_WIDTH                               0x2
 #define OMAP4430_MODULEMODE_MASK                                (0x3 << 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4460_MPU_DYNDEP_SHIFT                               19
+#define OMAP4460_MPU_DYNDEP_WIDTH                               0x1
 #define OMAP4460_MPU_DYNDEP_MASK                                (1 << 19)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_SHIFT                      9
+#define OMAP4430_OPTFCLKEN_48MHZ_CLK_WIDTH                      0x1
 #define OMAP4430_OPTFCLKEN_48MHZ_CLK_MASK                       (1 << 9)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_BGAP_32K_SHIFT                       8
+#define OMAP4430_OPTFCLKEN_BGAP_32K_WIDTH                       0x1
 #define OMAP4430_OPTFCLKEN_BGAP_32K_MASK                        (1 << 8)
 
 /* Used by CM_ALWON_USBPHY_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CLK32K_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_CLK32K_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_CLK32K_MASK                          (1 << 8)
 
 /* Used by CM_CAM_ISS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_CTRLCLK_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_CTRLCLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_CTRLCLK_MASK                         (1 << 8)
 
 /*
@@ -1160,126 +1361,157 @@
  * CM_WKUP_GPIO1_CLKCTRL
  */
 #define OMAP4430_OPTFCLKEN_DBCLK_SHIFT                          8
+#define OMAP4430_OPTFCLKEN_DBCLK_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_DBCLK_MASK                           (1 << 8)
 
 /* Used by CM_MEMIF_DLL_CLKCTRL, CM_MEMIF_DLL_H_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DLL_CLK_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_DLL_CLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_DLL_CLK_MASK                         (1 << 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_DSSCLK_SHIFT                         8
+#define OMAP4430_OPTFCLKEN_DSSCLK_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_DSSCLK_MASK                          (1 << 8)
 
 /* Used by CM_WKUP_USIM_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_FCLK_WIDTH                           0x1
 #define OMAP4430_OPTFCLKEN_FCLK_MASK                            (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK0_SHIFT                          8
+#define OMAP4430_OPTFCLKEN_FCLK0_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK0_MASK                           (1 << 8)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK1_SHIFT                          9
+#define OMAP4430_OPTFCLKEN_FCLK1_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK1_MASK                           (1 << 9)
 
 /* Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FCLK2_SHIFT                          10
+#define OMAP4430_OPTFCLKEN_FCLK2_WIDTH                          0x1
 #define OMAP4430_OPTFCLKEN_FCLK2_MASK                           (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_SHIFT                     15
+#define OMAP4430_OPTFCLKEN_FUNC48MCLK_WIDTH                     0x1
 #define OMAP4430_OPTFCLKEN_FUNC48MCLK_MASK                      (1 << 15)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_SHIFT                13
+#define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_HSIC480M_P1_CLK_MASK                 (1 << 13)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_SHIFT                14
+#define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_HSIC480M_P2_CLK_MASK                 (1 << 14)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_SHIFT                 11
+#define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_WIDTH                 0x1
 #define OMAP4430_OPTFCLKEN_HSIC60M_P1_CLK_MASK                  (1 << 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_SHIFT                 12
+#define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_WIDTH                 0x1
 #define OMAP4430_OPTFCLKEN_HSIC60M_P2_CLK_MASK                  (1 << 12)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_SHIFT                  8
+#define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_WIDTH                  0x1
 #define OMAP4430_OPTFCLKEN_PER24MC_GFCLK_MASK                   (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_SHIFT                9
+#define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_WIDTH                0x1
 #define OMAP4430_OPTFCLKEN_PERABE24M_GFCLK_MASK                 (1 << 9)
 
 /* Used by CM_L3INIT_USBPHYOCP2SCP_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_PHY_48M_SHIFT                        8
+#define OMAP4430_OPTFCLKEN_PHY_48M_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_PHY_48M_MASK                         (1 << 8)
 
 /* Used by CM_L4PER_SLIMBUS2_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_MASK                     (1 << 10)
 
 /* Renamed from OPTFCLKEN_SLIMBUS_CLK Used by CM1_ABE_SLIMBUS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_SHIFT              11
+#define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_WIDTH              0x1
 #define OMAP4430_OPTFCLKEN_SLIMBUS_CLK_11_11_MASK               (1 << 11)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_SYS_CLK_SHIFT                        10
+#define OMAP4430_OPTFCLKEN_SYS_CLK_WIDTH                        0x1
 #define OMAP4430_OPTFCLKEN_SYS_CLK_MASK                         (1 << 10)
 
 /* Used by CM_WKUP_BANDGAP_CLKCTRL */
 #define OMAP4460_OPTFCLKEN_TS_FCLK_SHIFT                        8
+#define OMAP4460_OPTFCLKEN_TS_FCLK_WIDTH                        0x1
 #define OMAP4460_OPTFCLKEN_TS_FCLK_MASK                         (1 << 8)
 
 /* Used by CM_DSS_DSS_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TV_CLK_SHIFT                         11
+#define OMAP4430_OPTFCLKEN_TV_CLK_WIDTH                         0x1
 #define OMAP4430_OPTFCLKEN_TV_CLK_MASK                          (1 << 11)
 
 /* Used by CM_L3INIT_UNIPRO1_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_SHIFT                       8
+#define OMAP4430_OPTFCLKEN_TXPHYCLK_WIDTH                       0x1
 #define OMAP4430_OPTFCLKEN_TXPHYCLK_MASK                        (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_SHIFT                    8
+#define OMAP4430_OPTFCLKEN_USB_CH0_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH0_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_SHIFT                    9
+#define OMAP4430_OPTFCLKEN_USB_CH1_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH1_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_USB_CH2_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_USB_CH2_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_SHIFT                    8
+#define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P1_CLK_MASK                     (1 << 8)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_SHIFT                    9
+#define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P2_CLK_MASK                     (1 << 9)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_SHIFT                    10
+#define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_WIDTH                    0x1
 #define OMAP4430_OPTFCLKEN_UTMI_P3_CLK_MASK                     (1 << 10)
 
 /* Used by CM_L3INIT_USB_OTG_CLKCTRL */
 #define OMAP4430_OPTFCLKEN_XCLK_SHIFT                           8
+#define OMAP4430_OPTFCLKEN_XCLK_WIDTH                           0x1
 #define OMAP4430_OPTFCLKEN_XCLK_MASK                            (1 << 8)
 
 /* Used by CM_EMU_OVERRIDE_DPLL_CORE */
 #define OMAP4430_OVERRIDE_ENABLE_SHIFT                          19
+#define OMAP4430_OVERRIDE_ENABLE_WIDTH                          0x1
 #define OMAP4430_OVERRIDE_ENABLE_MASK                           (1 << 19)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_PAD_CLKS_GATE_SHIFT                            8
+#define OMAP4430_PAD_CLKS_GATE_WIDTH                            0x1
 #define OMAP4430_PAD_CLKS_GATE_MASK                             (1 << 8)
 
 /* Used by CM_CORE_DVFS_CURRENT, CM_IVA_DVFS_CURRENT */
 #define OMAP4430_PERF_CURRENT_SHIFT                             0
+#define OMAP4430_PERF_CURRENT_WIDTH                             0x8
 #define OMAP4430_PERF_CURRENT_MASK                              (0xff << 0)
 
 /*
@@ -1288,74 +1520,85 @@
  * CM_IVA_DVFS_PERF_TESLA
  */
 #define OMAP4430_PERF_REQ_SHIFT                                 0
+#define OMAP4430_PERF_REQ_WIDTH                                 0x8
 #define OMAP4430_PERF_REQ_MASK                                  (0xff << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE1_COMPLETED_SHIFT                         0
+#define OMAP4430_PHASE1_COMPLETED_WIDTH                         0x1
 #define OMAP4430_PHASE1_COMPLETED_MASK                          (1 << 0)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2A_COMPLETED_SHIFT                        1
+#define OMAP4430_PHASE2A_COMPLETED_WIDTH                        0x1
 #define OMAP4430_PHASE2A_COMPLETED_MASK                         (1 << 1)
 
 /* Used by CM_RESTORE_ST */
 #define OMAP4430_PHASE2B_COMPLETED_SHIFT                        2
+#define OMAP4430_PHASE2B_COMPLETED_WIDTH                        0x1
 #define OMAP4430_PHASE2B_COMPLETED_MASK                         (1 << 2)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_STM_MUX_CTRL_SHIFT                         20
+#define OMAP4430_PMD_STM_MUX_CTRL_WIDTH                         0x2
 #define OMAP4430_PMD_STM_MUX_CTRL_MASK                          (0x3 << 20)
 
 /* Used by CM_EMU_DEBUGSS_CLKCTRL */
 #define OMAP4430_PMD_TRACE_MUX_CTRL_SHIFT                       22
+#define OMAP4430_PMD_TRACE_MUX_CTRL_WIDTH                       0x2
 #define OMAP4430_PMD_TRACE_MUX_CTRL_MASK                        (0x3 << 22)
 
 /* Used by CM_DYN_DEP_PRESCAL */
 #define OMAP4430_PRESCAL_SHIFT                                  0
+#define OMAP4430_PRESCAL_WIDTH                                  0x6
 #define OMAP4430_PRESCAL_MASK                                   (0x3f << 0)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_R_RTL_SHIFT                                    11
+#define OMAP4430_R_RTL_WIDTH                                    0x5
 #define OMAP4430_R_RTL_MASK                                     (0x1f << 11)
 
 /* Used by CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_TLL_CLKCTRL */
 #define OMAP4430_SAR_MODE_SHIFT                                 4
+#define OMAP4430_SAR_MODE_WIDTH                                 0x1
 #define OMAP4430_SAR_MODE_MASK                                  (1 << 4)
 
 /* Used by CM_SCALE_FCLK */
 #define OMAP4430_SCALE_FCLK_SHIFT                               0
+#define OMAP4430_SCALE_FCLK_WIDTH                               0x1
 #define OMAP4430_SCALE_FCLK_MASK                                (1 << 0)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_SCHEME_SHIFT                                   30
+#define OMAP4430_SCHEME_WIDTH                                   0x2
 #define OMAP4430_SCHEME_MASK                                    (0x3 << 30)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_SDMA_DYNDEP_SHIFT                              11
+#define OMAP4430_SDMA_DYNDEP_WIDTH                              0x1
 #define OMAP4430_SDMA_DYNDEP_MASK                               (1 << 11)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_SDMA_STATDEP_SHIFT                             11
+#define OMAP4430_SDMA_STATDEP_WIDTH                             0x1
 #define OMAP4430_SDMA_STATDEP_MASK                              (1 << 11)
 
 /* Used by CM_CLKSEL_ABE */
 #define OMAP4430_SLIMBUS_CLK_GATE_SHIFT                         10
+#define OMAP4430_SLIMBUS_CLK_GATE_WIDTH                         0x1
 #define OMAP4430_SLIMBUS_CLK_GATE_MASK                          (1 << 10)
 
 /*
  * Used by CM1_ABE_AESS_CLKCTRL, CM_CAM_FDIF_CLKCTRL, CM_CAM_ISS_CLKCTRL,
- * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DEISS_CLKCTRL, CM_DSS_DSS_CLKCTRL,
- * CM_DUCATI_DUCATI_CLKCTRL, CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL,
- * CM_IVAHD_IVAHD_CLKCTRL, CM_L3INIT_CCPTX_CLKCTRL, CM_L3INIT_EMAC_CLKCTRL,
+ * CM_D2D_SAD2D_CLKCTRL, CM_DSS_DSS_CLKCTRL, CM_DUCATI_DUCATI_CLKCTRL,
+ * CM_EMU_DEBUGSS_CLKCTRL, CM_GFX_GFX_CLKCTRL, CM_IVAHD_IVAHD_CLKCTRL,
  * CM_L3INIT_HSI_CLKCTRL, CM_L3INIT_MMC1_CLKCTRL, CM_L3INIT_MMC2_CLKCTRL,
- * CM_L3INIT_MMC6_CLKCTRL, CM_L3INIT_P1500_CLKCTRL, CM_L3INIT_PCIESS_CLKCTRL,
- * CM_L3INIT_SATA_CLKCTRL, CM_L3INIT_TPPSS_CLKCTRL, CM_L3INIT_UNIPRO1_CLKCTRL,
  * CM_L3INIT_USB_HOST_CLKCTRL, CM_L3INIT_USB_HOST_FS_CLKCTRL,
- * CM_L3INIT_USB_OTG_CLKCTRL, CM_L3INIT_XHPI_CLKCTRL,
- * CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL, CM_SDMA_SDMA_CLKCTRL,
- * CM_TESLA_TESLA_CLKCTRL
+ * CM_L3INIT_USB_OTG_CLKCTRL, CM_L4SEC_CRYPTODMA_CLKCTRL, CM_MPU_MPU_CLKCTRL,
+ * CM_SDMA_SDMA_CLKCTRL, CM_TESLA_TESLA_CLKCTRL
  */
 #define OMAP4430_STBYST_SHIFT                                   18
+#define OMAP4430_STBYST_WIDTH                                   0x1
 #define OMAP4430_STBYST_MASK                                    (1 << 18)
 
 /*
@@ -1364,10 +1607,12 @@
  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLK_SHIFT                              0
+#define OMAP4430_ST_DPLL_CLK_WIDTH                              0x1
 #define OMAP4430_ST_DPLL_CLK_MASK                               (1 << 0)
 
 /* Used by CM_CLKDCOLDO_DPLL_USB */
 #define OMAP4430_ST_DPLL_CLKDCOLDO_SHIFT                        9
+#define OMAP4430_ST_DPLL_CLKDCOLDO_WIDTH                        0x1
 #define OMAP4430_ST_DPLL_CLKDCOLDO_MASK                         (1 << 9)
 
 /*
@@ -1375,14 +1620,17 @@
  * CM_DIV_M2_DPLL_MPU, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_USB
  */
 #define OMAP4430_ST_DPLL_CLKOUT_SHIFT                           9
+#define OMAP4430_ST_DPLL_CLKOUT_WIDTH                           0x1
 #define OMAP4430_ST_DPLL_CLKOUT_MASK                            (1 << 9)
 
 /* Used by CM_DIV_M3_DPLL_ABE, CM_DIV_M3_DPLL_CORE, CM_DIV_M3_DPLL_PER */
 #define OMAP4430_ST_DPLL_CLKOUTHIF_SHIFT                        9
+#define OMAP4430_ST_DPLL_CLKOUTHIF_WIDTH                        0x1
 #define OMAP4430_ST_DPLL_CLKOUTHIF_MASK                         (1 << 9)
 
 /* Used by CM_DIV_M2_DPLL_ABE, CM_DIV_M2_DPLL_PER, CM_DIV_M2_DPLL_UNIPRO */
 #define OMAP4430_ST_DPLL_CLKOUTX2_SHIFT                         11
+#define OMAP4430_ST_DPLL_CLKOUTX2_WIDTH                         0x1
 #define OMAP4430_ST_DPLL_CLKOUTX2_MASK                          (1 << 11)
 
 /*
@@ -1390,6 +1638,7 @@
  * CM_DIV_M4_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT1_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT1_MASK                      (1 << 9)
 
 /*
@@ -1397,14 +1646,17 @@
  * CM_DIV_M5_DPLL_PER
  */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT2_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT2_MASK                      (1 << 9)
 
 /* Used by CM_DIV_M6_DPLL_CORE, CM_DIV_M6_DPLL_DDRPHY, CM_DIV_M6_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT3_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT3_MASK                      (1 << 9)
 
 /* Used by CM_DIV_M7_DPLL_CORE, CM_DIV_M7_DPLL_PER */
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_SHIFT                     9
+#define OMAP4430_ST_HSDIVIDER_CLKOUT4_WIDTH                     0x1
 #define OMAP4430_ST_HSDIVIDER_CLKOUT4_MASK                      (1 << 9)
 
 /*
@@ -1413,18 +1665,22 @@
  * CM_IDLEST_DPLL_UNIPRO, CM_IDLEST_DPLL_USB
  */
 #define OMAP4430_ST_MN_BYPASS_SHIFT                             8
+#define OMAP4430_ST_MN_BYPASS_WIDTH                             0x1
 #define OMAP4430_ST_MN_BYPASS_MASK                              (1 << 8)
 
 /* Used by CM_SYS_CLKSEL */
 #define OMAP4430_SYS_CLKSEL_SHIFT                               0
+#define OMAP4430_SYS_CLKSEL_WIDTH                               0x3
 #define OMAP4430_SYS_CLKSEL_MASK                                (0x7 << 0)
 
 /* Used by CM_L4CFG_DYNAMICDEP */
 #define OMAP4430_TESLA_DYNDEP_SHIFT                             1
+#define OMAP4430_TESLA_DYNDEP_WIDTH                             0x1
 #define OMAP4430_TESLA_DYNDEP_MASK                              (1 << 1)
 
 /* Used by CM_DUCATI_STATICDEP, CM_MPU_STATICDEP */
 #define OMAP4430_TESLA_STATDEP_SHIFT                            1
+#define OMAP4430_TESLA_STATDEP_WIDTH                            0x1
 #define OMAP4430_TESLA_STATDEP_MASK                             (1 << 1)
 
 /*
@@ -1433,13 +1689,16 @@
  * CM_L4PER_DYNAMICDEP, CM_MPU_DYNAMICDEP, CM_TESLA_DYNAMICDEP
  */
 #define OMAP4430_WINDOWSIZE_SHIFT                               24
+#define OMAP4430_WINDOWSIZE_WIDTH                               0x4
 #define OMAP4430_WINDOWSIZE_MASK                                (0xf << 24)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_X_MAJOR_SHIFT                                  8
+#define OMAP4430_X_MAJOR_WIDTH                                  0x3
 #define OMAP4430_X_MAJOR_MASK                                   (0x7 << 8)
 
 /* Used by REVISION_CM1, REVISION_CM2 */
 #define OMAP4430_Y_MINOR_SHIFT                                  0
+#define OMAP4430_Y_MINOR_WIDTH                                  0x6
 #define OMAP4430_Y_MINOR_MASK                                   (0x3f << 0)
 #endif
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.c b/arch/arm/mach-omap2/cm2xxx_3xxx.c
index a911e76b4ecf..7f07ab02a5b3 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.c
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.c
@@ -35,7 +35,7 @@
 #define OMAP2XXX_APLL_AUTOIDLE_LOW_POWER_STOP           0x3
 
 static const u8 cm_idlest_offs[] = {
-        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3
+        CM_IDLEST1, CM_IDLEST2, OMAP2430_CM_IDLEST3, OMAP24XX_CM_IDLEST4
 };
 
 u32 omap2_cm_read_mod_reg(s16 module, u16 idx)
diff --git a/arch/arm/mach-omap2/cm2xxx_3xxx.h b/arch/arm/mach-omap2/cm2xxx_3xxx.h
index 088bbad73db5..57b2f3c2fbf3 100644
--- a/arch/arm/mach-omap2/cm2xxx_3xxx.h
+++ b/arch/arm/mach-omap2/cm2xxx_3xxx.h
@@ -71,6 +71,7 @@
 #define OMAP24XX_CM_FCLKEN2                             0x0004
 #define OMAP24XX_CM_ICLKEN4                             0x001c
 #define OMAP24XX_CM_AUTOIDLE4                           0x003c
+#define OMAP24XX_CM_IDLEST4                             0x002c
 
 #define OMAP2430_CM_IDLEST3                             0x0028
 
diff --git a/arch/arm/mach-omap2/control.h b/arch/arm/mach-omap2/control.h
index 123186ac7d2e..a89e8256fd0e 100644
--- a/arch/arm/mach-omap2/control.h
+++ b/arch/arm/mach-omap2/control.h
@@ -354,6 +354,7 @@
 
 /* AM33XX CONTROL_STATUS bitfields (partial) */
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_SHIFT            22
+#define AM33XX_CONTROL_STATUS_SYSBOOT1_WIDTH            0x2
 #define AM33XX_CONTROL_STATUS_SYSBOOT1_MASK             (0x3 << 22)
 
 /* CONTROL OMAP STATUS register to identify OMAP3 features */
diff --git a/arch/arm/mach-omap2/devices.c b/arch/arm/mach-omap2/devices.c
index d092d2a89ee0..c8c211731d26 100644
--- a/arch/arm/mach-omap2/devices.c
+++ b/arch/arm/mach-omap2/devices.c
@@ -433,35 +433,24 @@ static void omap_init_mcspi(void)
 static inline void omap_init_mcspi(void) {}
 #endif
 
-static struct resource omap2_pmu_resource = {
-        .start  = 3 + OMAP_INTC_START,
-        .flags  = IORESOURCE_IRQ,
-};
-
-static struct resource omap3_pmu_resource = {
-        .start  = 3 + OMAP_INTC_START,
-        .flags  = IORESOURCE_IRQ,
-};
-
-static struct platform_device omap_pmu_device = {
-        .name           = "arm-pmu",
-        .id             = -1,
-        .num_resources  = 1,
-};
-
-static void omap_init_pmu(void)
+/**
+ * omap_init_rng - bind the RNG hwmod to the RNG omap_device
+ *
+ * Bind the RNG hwmod to the RNG omap_device.  No return value.
+ */
+static void omap_init_rng(void)
 {
-        if (cpu_is_omap24xx())
-                omap_pmu_device.resource = &omap2_pmu_resource;
-        else if (cpu_is_omap34xx())
-                omap_pmu_device.resource = &omap3_pmu_resource;
-        else
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+
+        oh = omap_hwmod_lookup("rng");
+        if (!oh)
                 return;
 
-        platform_device_register(&omap_pmu_device);
+        pdev = omap_device_build("omap_rng", -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "Can't build omap_device for omap_rng\n");
 }
 
-
 #if defined(CONFIG_CRYPTO_DEV_OMAP_SHAM) || defined(CONFIG_CRYPTO_DEV_OMAP_SHAM_MODULE)
 
 #ifdef CONFIG_ARCH_OMAP2
@@ -646,8 +635,8 @@ static int __init omap2_init_devices(void)
                 omap_init_mcpdm();
                 omap_init_mcspi();
         }
-        omap_init_pmu();
         omap_init_sti();
+        omap_init_rng();
         omap_init_sham();
         omap_init_aes();
         omap_init_vout();
diff --git a/arch/arm/mach-omap2/display.c b/arch/arm/mach-omap2/display.c
index e470c6e50acd..7012068ccbf6 100644
--- a/arch/arm/mach-omap2/display.c
+++ b/arch/arm/mach-omap2/display.c
@@ -488,7 +488,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk)
-                        clk_enable(oc->_clk);
+                        clk_prepare_enable(oc->_clk);
 
         dispc_disable_outputs();
 
@@ -515,7 +515,7 @@ int omap_dss_reset(struct omap_hwmod *oh)
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk)
-                        clk_disable(oc->_clk);
+                        clk_disable_unprepare(oc->_clk);
 
         r = (c == MAX_MODULE_SOFTRESET_WAIT) ? -ETIMEDOUT : 0;
 
diff --git a/arch/arm/mach-omap2/dpll3xxx.c b/arch/arm/mach-omap2/dpll3xxx.c
index 27d79deb4ba2..814e1808e158 100644
--- a/arch/arm/mach-omap2/dpll3xxx.c
+++ b/arch/arm/mach-omap2/dpll3xxx.c
@@ -63,8 +63,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
         const struct dpll_data *dd;
         int i = 0;
         int ret = -EINVAL;
+        const char *clk_name;
 
         dd = clk->dpll_data;
+        clk_name = __clk_get_name(clk);
 
         state <<= __ffs(dd->idlest_mask);
 
@@ -76,10 +78,10 @@ static int _omap3_wait_dpll_status(struct clk *clk, u8 state)
 
         if (i == MAX_DPLL_WAIT_TRIES) {
                 printk(KERN_ERR "clock: %s failed transition to '%s'\n",
-                       clk->name, (state) ? "locked" : "bypassed");
+                       clk_name, (state) ? "locked" : "bypassed");
         } else {
                 pr_debug("clock: %s transition to '%s' in %d loops\n",
-                         clk->name, (state) ? "locked" : "bypassed", i);
+                         clk_name, (state) ? "locked" : "bypassed", i);
 
                 ret = 0;
         }
@@ -93,7 +95,7 @@ static u16 _omap3_dpll_compute_freqsel(struct clk *clk, u8 n)
         unsigned long fint;
         u16 f = 0;
 
-        fint = clk->dpll_data->clk_ref->rate / n;
+        fint = __clk_get_rate(clk->dpll_data->clk_ref) / n;
 
         pr_debug("clock: fint is %lu\n", fint);
 
@@ -140,7 +142,7 @@ static int _omap3_noncore_dpll_lock(struct clk *clk)
         u8 state = 1;
         int r = 0;
 
-        pr_debug("clock: locking DPLL %s\n", clk->name);
+        pr_debug("clock: locking DPLL %s\n", __clk_get_name(clk));
 
         dd = clk->dpll_data;
         state <<= __ffs(dd->idlest_mask);
@@ -187,7 +189,7 @@ static int _omap3_noncore_dpll_bypass(struct clk *clk)
                 return -EINVAL;
 
         pr_debug("clock: configuring DPLL %s for low-power bypass\n",
-                 clk->name);
+                 __clk_get_name(clk));
 
         ai = omap3_dpll_autoidle_read(clk);
 
@@ -217,7 +219,7 @@ static int _omap3_noncore_dpll_stop(struct clk *clk)
         if (!(clk->dpll_data->modes & (1 << DPLL_LOW_POWER_STOP)))
                 return -EINVAL;
 
-        pr_debug("clock: stopping DPLL %s\n", clk->name);
+        pr_debug("clock: stopping DPLL %s\n", __clk_get_name(clk));
 
         ai = omap3_dpll_autoidle_read(clk);
 
@@ -245,7 +247,7 @@ static void _lookup_dco(struct clk *clk, u8 *dco, u16 m, u8 n)
 {
         unsigned long fint, clkinp; /* watch out for overflow */
 
-        clkinp = clk->parent->rate;
+        clkinp = __clk_get_rate(__clk_get_parent(clk));
         fint = (clkinp / n) * m;
 
         if (fint < 1000000000)
@@ -271,7 +273,7 @@ static void _lookup_sddiv(struct clk *clk, u8 *sd_div, u16 m, u8 n)
         unsigned long clkinp, sd; /* watch out for overflow */
         int mod1, mod2;
 
-        clkinp = clk->parent->rate;
+        clkinp = __clk_get_rate(__clk_get_parent(clk));
 
         /*
          * target sigma-delta to near 250MHz
@@ -380,16 +382,19 @@ int omap3_noncore_dpll_enable(struct clk *clk)
 {
         int r;
         struct dpll_data *dd;
+        struct clk *parent;
 
         dd = clk->dpll_data;
         if (!dd)
                 return -EINVAL;
 
-        if (clk->rate == dd->clk_bypass->rate) {
-                WARN_ON(clk->parent != dd->clk_bypass);
+        parent = __clk_get_parent(clk);
+
+        if (__clk_get_rate(clk) == __clk_get_rate(dd->clk_bypass)) {
+                WARN_ON(parent != dd->clk_bypass);
                 r = _omap3_noncore_dpll_bypass(clk);
         } else {
-                WARN_ON(clk->parent != dd->clk_ref);
+                WARN_ON(parent != dd->clk_ref);
                 r = _omap3_noncore_dpll_lock(clk);
         }
         /*
@@ -432,7 +437,7 @@ void omap3_noncore_dpll_disable(struct clk *clk)
 int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
 {
         struct clk *new_parent = NULL;
-        unsigned long hw_rate;
+        unsigned long hw_rate, bypass_rate;
         u16 freqsel = 0;
         struct dpll_data *dd;
         int ret;
@@ -456,7 +461,8 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
         omap2_clk_enable(dd->clk_bypass);
         omap2_clk_enable(dd->clk_ref);
 
-        if (dd->clk_bypass->rate == rate &&
+        bypass_rate = __clk_get_rate(dd->clk_bypass);
+        if (bypass_rate == rate &&
             (clk->dpll_data->modes & (1 << DPLL_LOW_POWER_BYPASS))) {
                 pr_debug("clock: %s: set rate: entering bypass.\n", clk->name);
 
@@ -479,7 +485,7 @@ int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate)
                 }
 
                 pr_debug("clock: %s: set rate: locking rate to %lu.\n",
-                         clk->name, rate);
+                         __clk_get_name(clk), rate);
 
                 ret = omap3_noncore_dpll_program(clk, dd->last_rounded_m,
                                                  dd->last_rounded_n, freqsel);
@@ -557,7 +563,7 @@ void omap3_dpll_allow_idle(struct clk *clk)
 
         if (!dd->autoidle_reg) {
                 pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        clk->name);
+                        __clk_get_name(clk));
                 return;
         }
 
@@ -591,7 +597,7 @@ void omap3_dpll_deny_idle(struct clk *clk)
 
         if (!dd->autoidle_reg) {
                 pr_debug("clock: DPLL %s: autoidle not supported\n",
-                        clk->name);
+                        __clk_get_name(clk));
                 return;
         }
 
@@ -617,11 +623,12 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
         unsigned long rate;
         u32 v;
         struct clk *pclk;
+        unsigned long parent_rate;
 
         /* Walk up the parents of clk, looking for a DPLL */
-        pclk = clk->parent;
+        pclk = __clk_get_parent(clk);
         while (pclk && !pclk->dpll_data)
-                pclk = pclk->parent;
+                pclk = __clk_get_parent(pclk);
 
         /* clk does not have a DPLL as a parent?  error in the clock data */
         if (!pclk) {
@@ -633,12 +640,13 @@ unsigned long omap3_clkoutx2_recalc(struct clk *clk)
 
         WARN_ON(!dd->enable_mask);
 
+        parent_rate = __clk_get_rate(__clk_get_parent(clk));
         v = __raw_readl(dd->control_reg) & dd->enable_mask;
         v >>= __ffs(dd->enable_mask);
         if ((v != OMAP3XXX_EN_DPLL_LOCKED) || (dd->flags & DPLL_J_TYPE))
-                rate = clk->parent->rate;
+                rate = parent_rate;
         else
-                rate = clk->parent->rate * 2;
+                rate = parent_rate * 2;
         return rate;
 }
 
diff --git a/arch/arm/mach-omap2/gpmc.c b/arch/arm/mach-omap2/gpmc.c
index 72428bd45efc..8ab1e1bde5e9 100644
--- a/arch/arm/mach-omap2/gpmc.c
+++ b/arch/arm/mach-omap2/gpmc.c
@@ -24,6 +24,7 @@
 #include <linux/io.h>
 #include <linux/module.h>
 #include <linux/interrupt.h>
+#include <linux/platform_device.h>
 
 #include <asm/mach-types.h>
 #include <plat/gpmc.h>
@@ -31,10 +32,13 @@
 #include <plat/cpu.h>
 #include <plat/gpmc.h>
 #include <plat/sdrc.h>
+#include <plat/omap_device.h>
 
 #include "soc.h"
 #include "common.h"
 
+#define DEVICE_NAME             "omap-gpmc"
+
 /* GPMC register offsets */
 #define GPMC_REVISION           0x00
 #define GPMC_SYSCONFIG          0x10
@@ -83,6 +87,12 @@
 #define ENABLE_PREFETCH         (0x1 << 7)
 #define DMA_MPU_MODE            2
 
+#define GPMC_REVISION_MAJOR(l)          ((l >> 4) & 0xf)
+#define GPMC_REVISION_MINOR(l)          (l & 0xf)
+
+#define GPMC_HAS_WR_ACCESS              0x1
+#define GPMC_HAS_WR_DATA_MUX_BUS        0x2
+
 /* XXX: Only NAND irq has been considered,currently these are the only ones used
  */
 #define GPMC_NR_IRQ             2
@@ -128,7 +138,10 @@ static struct resource	gpmc_cs_mem[GPMC_CS_NUM];
 static DEFINE_SPINLOCK(gpmc_mem_lock);
 static unsigned int gpmc_cs_map;        /* flag for cs which are initialized */
 static int gpmc_ecc_used = -EINVAL;     /* cs using ecc engine */
-
+static struct device *gpmc_dev;
+static int gpmc_irq;
+static resource_size_t phys_base, mem_size;
+static unsigned gpmc_capability;
 static void __iomem *gpmc_base;
 
 static struct clk *gpmc_l3_clk;
@@ -318,10 +331,10 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
 
         GPMC_SET_ONE(GPMC_CS_CONFIG5, 24, 27, page_burst_access);
 
-        if (cpu_is_omap34xx()) {
+        if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 16, 19, wr_data_mux_bus);
+        if (gpmc_capability & GPMC_HAS_WR_ACCESS)
                 GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
-        }
 
         /* caller is expected to have initialized CONFIG1 to cover
          * at least sync vs async
@@ -431,6 +444,20 @@ static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
         return r;
 }
 
+static int gpmc_cs_delete_mem(int cs)
+{
+        struct resource *res = &gpmc_cs_mem[cs];
+        int r;
+
+        spin_lock(&gpmc_mem_lock);
+        r = release_resource(&gpmc_cs_mem[cs]);
+        res->start = 0;
+        res->end = 0;
+        spin_unlock(&gpmc_mem_lock);
+
+        return r;
+}
+
 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 {
         struct resource *res = &gpmc_cs_mem[cs];
@@ -767,7 +794,7 @@ static void gpmc_irq_noop(struct irq_data *data) { }
 
 static unsigned int gpmc_irq_noop_ret(struct irq_data *data) { return 0; }
 
-static int gpmc_setup_irq(int gpmc_irq)
+static int gpmc_setup_irq(void)
 {
         int i;
         u32 regval;
@@ -811,7 +838,37 @@ static int gpmc_setup_irq(int gpmc_irq)
         return request_irq(gpmc_irq, gpmc_handle_irq, 0, "gpmc", NULL);
 }
 
-static void __init gpmc_mem_init(void)
+static __exit int gpmc_free_irq(void)
+{
+        int i;
+
+        if (gpmc_irq)
+                free_irq(gpmc_irq, NULL);
+
+        for (i = 0; i < GPMC_NR_IRQ; i++) {
+                irq_set_handler(gpmc_client_irq[i].irq, NULL);
+                irq_set_chip(gpmc_client_irq[i].irq, &no_irq_chip);
+                irq_modify_status(gpmc_client_irq[i].irq, 0, 0);
+        }
+
+        irq_free_descs(gpmc_irq_start, GPMC_NR_IRQ);
+
+        return 0;
+}
+
+static void __devexit gpmc_mem_exit(void)
+{
+        int cs;
+
+        for (cs = 0; cs < GPMC_CS_NUM; cs++) {
+                if (!gpmc_cs_mem_enabled(cs))
+                        continue;
+                gpmc_cs_delete_mem(cs);
+        }
+
+}
+
+static void __devinit gpmc_mem_init(void)
 {
         int cs;
         unsigned long boot_rom_space = 0;
@@ -838,65 +895,104 @@ static void __init gpmc_mem_init(void)
         }
 }
 
-static int __init gpmc_init(void)
+static __devinit int gpmc_probe(struct platform_device *pdev)
 {
         u32 l;
-        int ret = -EINVAL;
-        int gpmc_irq;
-        char *ck = NULL;
-
-        if (cpu_is_omap24xx()) {
-                ck = "core_l3_ck";
-                if (cpu_is_omap2420())
-                        l = OMAP2420_GPMC_BASE;
-                else
-                        l = OMAP34XX_GPMC_BASE;
-                gpmc_irq = 20 + OMAP_INTC_START;
-        } else if (cpu_is_omap34xx()) {
-                ck = "gpmc_fck";
-                l = OMAP34XX_GPMC_BASE;
-                gpmc_irq = 20 + OMAP_INTC_START;
-        } else if (cpu_is_omap44xx() || soc_is_omap54xx()) {
-                /* Base address and irq number are same for OMAP4/5 */
-                ck = "gpmc_ck";
-                l = OMAP44XX_GPMC_BASE;
-                gpmc_irq = 20 + OMAP44XX_IRQ_GIC_START;
+        struct resource *res;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (res == NULL)
+                return -ENOENT;
+
+        phys_base = res->start;
+        mem_size = resource_size(res);
+
+        gpmc_base = devm_request_and_ioremap(&pdev->dev, res);
+        if (!gpmc_base) {
+                dev_err(&pdev->dev, "error: request memory / ioremap\n");
+                return -EADDRNOTAVAIL;
         }
 
-        if (WARN_ON(!ck))
-                return ret;
+        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
+        if (res == NULL)
+                dev_warn(&pdev->dev, "Failed to get resource: irq\n");
+        else
+                gpmc_irq = res->start;
 
-        gpmc_l3_clk = clk_get(NULL, ck);
+        gpmc_l3_clk = clk_get(&pdev->dev, "fck");
         if (IS_ERR(gpmc_l3_clk)) {
-                printk(KERN_ERR "Could not get GPMC clock %s\n", ck);
-                BUG();
+                dev_err(&pdev->dev, "error: clk_get\n");
+                gpmc_irq = 0;
+                return PTR_ERR(gpmc_l3_clk);
         }
 
-        gpmc_base = ioremap(l, SZ_4K);
-        if (!gpmc_base) {
-                clk_put(gpmc_l3_clk);
-                printk(KERN_ERR "Could not get GPMC register memory\n");
-                BUG();
-        }
+        clk_prepare_enable(gpmc_l3_clk);
 
-        clk_enable(gpmc_l3_clk);
+        gpmc_dev = &pdev->dev;
 
         l = gpmc_read_reg(GPMC_REVISION);
-        printk(KERN_INFO "GPMC revision %d.%d\n", (l >> 4) & 0x0f, l & 0x0f);
-        /* Set smart idle mode and automatic L3 clock gating */
-        l = gpmc_read_reg(GPMC_SYSCONFIG);
-        l &= 0x03 << 3;
-        l |= (0x02 << 3) | (1 << 0);
-        gpmc_write_reg(GPMC_SYSCONFIG, l);
+        if (GPMC_REVISION_MAJOR(l) > 0x4)
+                gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
+        dev_info(gpmc_dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
+                 GPMC_REVISION_MINOR(l));
+
         gpmc_mem_init();
 
-        ret = gpmc_setup_irq(gpmc_irq);
-        if (ret)
-                pr_err("gpmc: irq-%d could not claim: err %d\n",
-                                                gpmc_irq, ret);
-        return ret;
+        if (IS_ERR_VALUE(gpmc_setup_irq()))
+                dev_warn(gpmc_dev, "gpmc_setup_irq failed\n");
+
+        return 0;
 }
+
+static __exit int gpmc_remove(struct platform_device *pdev)
+{
+        gpmc_free_irq();
+        gpmc_mem_exit();
+        gpmc_dev = NULL;
+        return 0;
+}
+
+static struct platform_driver gpmc_driver = {
+        .probe          = gpmc_probe,
+        .remove         = __devexit_p(gpmc_remove),
+        .driver         = {
+                .name   = DEVICE_NAME,
+                .owner  = THIS_MODULE,
+        },
+};
+
+static __init int gpmc_init(void)
+{
+        return platform_driver_register(&gpmc_driver);
+}
+
+static __exit void gpmc_exit(void)
+{
+        platform_driver_unregister(&gpmc_driver);
+
+}
+
 postcore_initcall(gpmc_init);
+module_exit(gpmc_exit);
+
+static int __init omap_gpmc_init(void)
+{
+        struct omap_hwmod *oh;
+        struct platform_device *pdev;
+        char *oh_name = "gpmc";
+
+        oh = omap_hwmod_lookup(oh_name);
+        if (!oh) {
+                pr_err("Could not look up %s\n", oh_name);
+                return -ENODEV;
+        }
+
+        pdev = omap_device_build(DEVICE_NAME, -1, oh, NULL, 0, NULL, 0, 0);
+        WARN(IS_ERR(pdev), "could not build omap_device for %s\n", oh_name);
+
+        return IS_ERR(pdev) ? PTR_ERR(pdev) : 0;
+}
+postcore_initcall(omap_gpmc_init);
 
 static irqreturn_t gpmc_handle_irq(int irq, void *dev)
 {
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 00c006686b0d..299ca2821ad1 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -679,16 +679,25 @@ static int _init_main_clk(struct omap_hwmod *oh)
         if (!oh->main_clk)
                 return 0;
 
-        oh->_clk = omap_clk_get_by_name(oh->main_clk);
-        if (!oh->_clk) {
+        oh->_clk = clk_get(NULL, oh->main_clk);
+        if (IS_ERR(oh->_clk)) {
                 pr_warning("omap_hwmod: %s: cannot clk_get main_clk %s\n",
                            oh->name, oh->main_clk);
                 return -EINVAL;
         }
+        /*
+         * HACK: This needs a re-visit once clk_prepare() is implemented
+         * to do something meaningful. Today its just a no-op.
+         * If clk_prepare() is used at some point to do things like
+         * voltage scaling etc, then this would have to be moved to
+         * some point where subsystems like i2c and pmic become
+         * available.
+         */
+        clk_prepare(oh->_clk);
 
         if (!oh->_clk->clkdm)
-                pr_warning("omap_hwmod: %s: missing clockdomain for %s.\n",
-                           oh->main_clk, oh->_clk->name);
+                pr_debug("omap_hwmod: %s: missing clockdomain for %s.\n",
+                           oh->name, oh->main_clk);
 
         return ret;
 }
@@ -715,13 +724,22 @@ static int _init_interface_clks(struct omap_hwmod *oh)
                 if (!os->clk)
                         continue;
 
-                c = omap_clk_get_by_name(os->clk);
-                if (!c) {
+                c = clk_get(NULL, os->clk);
+                if (IS_ERR(c)) {
                         pr_warning("omap_hwmod: %s: cannot clk_get interface_clk %s\n",
                                    oh->name, os->clk);
                         ret = -EINVAL;
                 }
                 os->_clk = c;
+                /*
+                 * HACK: This needs a re-visit once clk_prepare() is implemented
+                 * to do something meaningful. Today its just a no-op.
+                 * If clk_prepare() is used at some point to do things like
+                 * voltage scaling etc, then this would have to be moved to
+                 * some point where subsystems like i2c and pmic become
+                 * available.
+                 */
+                clk_prepare(os->_clk);
         }
 
         return ret;
@@ -742,13 +760,22 @@ static int _init_opt_clks(struct omap_hwmod *oh)
         int ret = 0;
 
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++) {
-                c = omap_clk_get_by_name(oc->clk);
-                if (!c) {
+                c = clk_get(NULL, oc->clk);
+                if (IS_ERR(c)) {
                         pr_warning("omap_hwmod: %s: cannot clk_get opt_clk %s\n",
                                    oh->name, oc->clk);
                         ret = -EINVAL;
                 }
                 oc->_clk = c;
+                /*
+                 * HACK: This needs a re-visit once clk_prepare() is implemented
+                 * to do something meaningful. Today its just a no-op.
+                 * If clk_prepare() is used at some point to do things like
+                 * voltage scaling etc, then this would have to be moved to
+                 * some point where subsystems like i2c and pmic become
+                 * available.
+                 */
+                clk_prepare(oc->_clk);
         }
 
         return ret;
@@ -827,7 +854,7 @@ static void _enable_optional_clocks(struct omap_hwmod *oh)
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk) {
                         pr_debug("omap_hwmod: enable %s:%s\n", oc->role,
-                                 oc->_clk->name);
+                                 __clk_get_name(oc->_clk));
                         clk_enable(oc->_clk);
                 }
 }
@@ -842,7 +869,7 @@ static void _disable_optional_clocks(struct omap_hwmod *oh)
         for (i = oh->opt_clks_cnt, oc = oh->opt_clks; i > 0; i--, oc++)
                 if (oc->_clk) {
                         pr_debug("omap_hwmod: disable %s:%s\n", oc->role,
-                                 oc->_clk->name);
+                                 __clk_get_name(oc->_clk));
                         clk_disable(oc->_clk);
                 }
 }
@@ -900,10 +927,10 @@ static void _am33xx_enable_module(struct omap_hwmod *oh)
  */
 static int _omap4_wait_target_disable(struct omap_hwmod *oh)
 {
-        if (!oh || !oh->clkdm)
+        if (!oh)
                 return -EINVAL;
 
-        if (oh->_int_flags & _HWMOD_NO_MPU_PORT)
+        if (oh->_int_flags & _HWMOD_NO_MPU_PORT || !oh->clkdm)
                 return 0;
 
         if (oh->flags & HWMOD_NO_IDLEST)
@@ -1427,8 +1454,10 @@ static struct omap_hwmod *_lookup(const char *name)
  */
 static int _init_clkdm(struct omap_hwmod *oh)
 {
-        if (!oh->clkdm_name)
+        if (!oh->clkdm_name) {
+                pr_debug("omap_hwmod: %s: missing clockdomain\n", oh->name);
                 return 0;
+        }
 
         oh->clkdm = clkdm_lookup(oh->clkdm_name);
         if (!oh->clkdm) {
@@ -1556,6 +1585,7 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
 {
         struct omap_hwmod_rst_info ohri;
         int ret = -EINVAL;
+        int hwsup = 0;
 
         if (!oh)
                 return -EINVAL;
@@ -1567,10 +1597,46 @@ static int _deassert_hardreset(struct omap_hwmod *oh, const char *name)
         if (IS_ERR_VALUE(ret))
                 return ret;
 
+        if (oh->clkdm) {
+                /*
+                 * A clockdomain must be in SW_SUP otherwise reset
+                 * might not be completed. The clockdomain can be set
+                 * in HW_AUTO only when the module become ready.
+                 */
+                hwsup = clkdm_in_hwsup(oh->clkdm);
+                ret = clkdm_hwmod_enable(oh->clkdm, oh);
+                if (ret) {
+                        WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
+                             oh->name, oh->clkdm->name, ret);
+                        return ret;
+                }
+        }
+
+        _enable_clocks(oh);
+        if (soc_ops.enable_module)
+                soc_ops.enable_module(oh);
+
         ret = soc_ops.deassert_hardreset(oh, &ohri);
+
+        if (soc_ops.disable_module)
+                soc_ops.disable_module(oh);
+        _disable_clocks(oh);
+
         if (ret == -EBUSY)
                 pr_warning("omap_hwmod: %s: failed to hardreset\n", oh->name);
 
+        if (!ret) {
+                /*
+                 * Set the clockdomain to HW_AUTO, assuming that the
+                 * previous state was HW_AUTO.
+                 */
+                if (oh->clkdm && hwsup)
+                        clkdm_allow_idle(oh->clkdm);
+        } else {
+                if (oh->clkdm)
+                        clkdm_hwmod_disable(oh->clkdm, oh);
+        }
+
         return ret;
 }
 
@@ -1605,25 +1671,28 @@ static int _read_hardreset(struct omap_hwmod *oh, const char *name)
 }
 
 /**
- * _are_any_hardreset_lines_asserted - return true if part of @oh is hard-reset
+ * _are_all_hardreset_lines_asserted - return true if the @oh is hard-reset
  * @oh: struct omap_hwmod *
  *
- * If any hardreset line associated with @oh is asserted, then return true.
- * Otherwise, if @oh has no hardreset lines associated with it, or if
- * no hardreset lines associated with @oh are asserted, then return false.
+ * If all hardreset lines associated with @oh are asserted, then return true.
+ * Otherwise, if part of @oh is out hardreset or if no hardreset lines
+ * associated with @oh are asserted, then return false.
  * This function is used to avoid executing some parts of the IP block
- * enable/disable sequence if a hardreset line is set.
+ * enable/disable sequence if its hardreset line is set.
  */
-static bool _are_any_hardreset_lines_asserted(struct omap_hwmod *oh)
+static bool _are_all_hardreset_lines_asserted(struct omap_hwmod *oh)
 {
-        int i;
+        int i, rst_cnt = 0;
 
         if (oh->rst_lines_cnt == 0)
                 return false;
 
         for (i = 0; i < oh->rst_lines_cnt; i++)
                 if (_read_hardreset(oh, oh->rst_lines[i].name) > 0)
-                        return true;
+                        rst_cnt++;
+
+        if (oh->rst_lines_cnt == rst_cnt)
+                return true;
 
         return false;
 }
@@ -1642,6 +1711,13 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
         if (!oh->clkdm || !oh->prcm.omap4.modulemode)
                 return -EINVAL;
 
+        /*
+         * Since integration code might still be doing something, only
+         * disable if all lines are under hardreset.
+         */
+        if (!_are_all_hardreset_lines_asserted(oh))
+                return 0;
+
         pr_debug("omap_hwmod: %s: %s\n", oh->name, __func__);
 
         omap4_cminst_module_disable(oh->clkdm->prcm_partition,
@@ -1649,9 +1725,6 @@ static int _omap4_disable_module(struct omap_hwmod *oh)
                                     oh->clkdm->clkdm_offs,
                                     oh->prcm.omap4.clkctrl_offs);
 
-        if (_are_any_hardreset_lines_asserted(oh))
-                return 0;
-
         v = _omap4_wait_target_disable(oh);
         if (v)
                 pr_warn("omap_hwmod: %s: _wait_target_disable failed\n",
@@ -1679,7 +1752,7 @@ static int _am33xx_disable_module(struct omap_hwmod *oh)
         am33xx_cm_module_disable(oh->clkdm->cm_inst, oh->clkdm->clkdm_offs,
                                  oh->prcm.omap4.clkctrl_offs);
 
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         v = _am33xx_wait_target_disable(oh);
@@ -1907,7 +1980,7 @@ static int _enable(struct omap_hwmod *oh)
         }
 
         /*
-         * If an IP block contains HW reset lines and any of them are
+         * If an IP block contains HW reset lines and all of them are
          * asserted, we let integration code associated with that
          * block handle the enable.  We've received very little
          * information on what those driver authors need, and until
@@ -1915,7 +1988,7 @@ static int _enable(struct omap_hwmod *oh)
          * posted to the public lists, this is probably the best we
          * can do.
          */
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         /* Mux pins for device runtime if populated */
@@ -1934,7 +2007,8 @@ static int _enable(struct omap_hwmod *oh)
                  * completely the module. The clockdomain can be set
                  * in HW_AUTO only when the module become ready.
                  */
-                hwsup = clkdm_in_hwsup(oh->clkdm);
+                hwsup = clkdm_in_hwsup(oh->clkdm) &&
+                        !clkdm_missing_idle_reporting(oh->clkdm);
                 r = clkdm_hwmod_enable(oh->clkdm, oh);
                 if (r) {
                         WARN(1, "omap_hwmod: %s: could not enable clockdomain %s: %d\n",
@@ -1996,7 +2070,7 @@ static int _idle(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         if (oh->class->sysc)
@@ -2084,7 +2158,7 @@ static int _shutdown(struct omap_hwmod *oh)
                 return -EINVAL;
         }
 
-        if (_are_any_hardreset_lines_asserted(oh))
+        if (_are_all_hardreset_lines_asserted(oh))
                 return 0;
 
         pr_debug("omap_hwmod: %s: disabling\n", oh->name);
@@ -2608,10 +2682,10 @@ static int _omap2_wait_target_ready(struct omap_hwmod *oh)
  */
 static int _omap4_wait_target_ready(struct omap_hwmod *oh)
 {
-        if (!oh || !oh->clkdm)
+        if (!oh)
                 return -EINVAL;
 
-        if (oh->flags & HWMOD_NO_IDLEST)
+        if (oh->flags & HWMOD_NO_IDLEST || !oh->clkdm)
                 return 0;
 
         if (!_find_mpu_rt_port(oh))
diff --git a/arch/arm/mach-omap2/omap_hwmod_2420_data.c b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
index 10575a1bc1f1..b5db6007c523 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2420_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2420_data.c
@@ -536,6 +536,15 @@ static struct omap_hwmod_addr_space omap2420_counter_32k_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2420_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6800a000,
+                .pa_end         = 0x6800afff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_counter_32k_hwmod,
@@ -544,6 +553,14 @@ static struct omap_hwmod_ocp_if omap2420_l4_wkup__counter_32k = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if omap2420_l3__gpmc = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2xxx_gpmc_hwmod,
+        .clk            = "core_l3_ck",
+        .addr           = omap2420_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
         &omap2xxx_l3_main__l4_core,
         &omap2xxx_mpu__l3_main,
@@ -585,8 +602,10 @@ static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = {
         &omap2420_l4_core__mcbsp1,
         &omap2420_l4_core__mcbsp2,
         &omap2420_l4_core__msdi1,
+        &omap2xxx_l4_core__rng,
         &omap2420_l4_core__hdq1w,
         &omap2420_l4_wkup__counter_32k,
+        &omap2420_l3__gpmc,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2430_data.c b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
index 60de70feeae5..c455e41b0237 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2430_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2430_data.c
@@ -888,6 +888,15 @@ static struct omap_hwmod_addr_space omap2430_counter_32k_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2430_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6e000000,
+                .pa_end         = 0x6e000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
         .master         = &omap2xxx_l4_wkup_hwmod,
         .slave          = &omap2xxx_counter_32k_hwmod,
@@ -896,6 +905,14 @@ static struct omap_hwmod_ocp_if omap2430_l4_wkup__counter_32k = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_ocp_if omap2430_l3__gpmc = {
+        .master         = &omap2xxx_l3_main_hwmod,
+        .slave          = &omap2xxx_gpmc_hwmod,
+        .clk            = "core_l3_ck",
+        .addr           = omap2430_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
         &omap2xxx_l3_main__l4_core,
         &omap2xxx_mpu__l3_main,
@@ -945,7 +962,9 @@ static struct omap_hwmod_ocp_if *omap2430_hwmod_ocp_ifs[] __initdata = {
         &omap2430_l4_core__mcbsp4,
         &omap2430_l4_core__mcbsp5,
         &omap2430_l4_core__hdq1w,
+        &omap2xxx_l4_core__rng,
         &omap2430_l4_wkup__counter_32k,
+        &omap2430_l3__gpmc,
         NULL,
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
index f853a0b1d5ca..1a1287d62648 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_interconnect_data.c
@@ -129,6 +129,15 @@ struct omap_hwmod_addr_space omap2xxx_mcbsp2_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap2_rng_addr_space[] = {
+        {
+                .pa_start       = 0x480a0000,
+                .pa_end         = 0x480a004f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 /*
  * Common interconnect data
  */
@@ -372,3 +381,11 @@ struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/* l4_core -> rng */
+struct omap_hwmod_ocp_if omap2xxx_l4_core__rng = {
+        .master         = &omap2xxx_l4_core_hwmod,
+        .slave          = &omap2xxx_rng_hwmod,
+        .clk            = "rng_ick",
+        .addr           = omap2_rng_addr_space,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
index feeb401cf87e..35dcdb66a4e0 100644
--- a/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_2xxx_ipblock_data.c
@@ -173,6 +173,26 @@ struct omap_hwmod_class omap2xxx_mcspi_class = {
 };
 
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap2xxx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2xxx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap2xxx_gpmc_sysc,
+};
+
+/*
  * IP blocks
  */
 
@@ -198,8 +218,14 @@ struct omap_hwmod omap2xxx_l4_wkup_hwmod = {
 };
 
 /* MPU */
+static struct omap_hwmod_irq_info omap2xxx_mpu_irqs[] = {
+        { .name = "pmu", .irq = 3 },
+        { .irq = -1 }
+};
+
 struct omap_hwmod omap2xxx_mpu_hwmod = {
         .name           = "mpu",
+        .mpu_irqs       = omap2xxx_mpu_irqs,
         .class          = &mpu_hwmod_class,
         .main_clk       = "mpu_ck",
 };
@@ -220,6 +246,11 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
         .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
 /* timer1 */
 
 struct omap_hwmod omap2xxx_timer1_hwmod = {
@@ -308,6 +339,7 @@ struct omap_hwmod omap2xxx_timer5_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT5_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -326,6 +358,7 @@ struct omap_hwmod omap2xxx_timer6_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT6_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -344,6 +377,7 @@ struct omap_hwmod omap2xxx_timer7_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT7_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -362,6 +396,7 @@ struct omap_hwmod omap2xxx_timer8_hwmod = {
                         .idlest_idle_bit = OMAP24XX_ST_GPT8_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap2xxx_timer_hwmod_class,
 };
 
@@ -724,7 +759,6 @@ struct omap_hwmod omap2xxx_mcspi2_hwmod = {
         .dev_attr       = &omap_mcspi2_dev_attr,
 };
 
-
 static struct omap_hwmod_class omap2xxx_counter_hwmod_class = {
         .name   = "counter",
 };
@@ -743,3 +777,77 @@ struct omap_hwmod omap2xxx_counter_32k_hwmod = {
         },
         .class          = &omap2xxx_counter_hwmod_class,
 };
+
+/* gpmc */
+static struct omap_hwmod_irq_info omap2xxx_gpmc_irqs[] = {
+        { .irq = 20 },
+        { .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap2xxx_gpmc_hwmod_class,
+        .mpu_irqs       = omap2xxx_gpmc_irqs,
+        .main_clk       = "gpmc_fck",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+                           HWMOD_NO_IDLEST),
+        .prcm           = {
+                .omap2  = {
+                        .prcm_reg_id = 3,
+                        .module_bit = OMAP24XX_EN_GPMC_MASK,
+                        .module_offs = CORE_MOD,
+                },
+        },
+};
+
+/* RNG */
+
+static struct omap_hwmod_class_sysconfig omap2_rng_sysc = {
+        .rev_offs       = 0x3c,
+        .sysc_offs      = 0x40,
+        .syss_offs      = 0x44,
+        .sysc_flags     = (SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE |
+                           SYSS_HAS_RESET_STATUS),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap2_rng_hwmod_class = {
+        .name           = "rng",
+        .sysc           = &omap2_rng_sysc,
+};
+
+static struct omap_hwmod_irq_info omap2_rng_mpu_irqs[] = {
+        { .irq = 52 },
+        { .irq = -1 }
+};
+
+struct omap_hwmod omap2xxx_rng_hwmod = {
+        .name           = "rng",
+        .mpu_irqs       = omap2_rng_mpu_irqs,
+        .main_clk       = "l4_ck",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 4,
+                        .module_bit = OMAP24XX_EN_RNG_SHIFT,
+                        .idlest_reg_id = 4,
+                        .idlest_idle_bit = OMAP24XX_ST_RNG_SHIFT,
+                },
+        },
+        /*
+         * XXX The first read from the SYSSTATUS register of the RNG
+         * after the SYSCONFIG SOFTRESET bit is set triggers an
+         * imprecise external abort.  It's unclear why this happens.
+         * Until this is analyzed, skip the IP block reset.
+         */
+        .flags          = HWMOD_INIT_NO_RESET,
+        .class          = &omap2_rng_hwmod_class,
+};
diff --git a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
index 94b38af17055..285777241d5a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
@@ -27,6 +27,7 @@
 #include <linux/platform_data/asoc-ti-mcbsp.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 #include <plat/dmtimer.h>
+#include <plat/iommu.h>
 
 #include "am35xx.h"
 
@@ -92,8 +93,14 @@ static struct omap_hwmod omap3xxx_l4_sec_hwmod = {
 };
 
 /* MPU */
+static struct omap_hwmod_irq_info omap3xxx_mpu_irqs[] = {
+        { .name = "pmu", .irq = 3 },
+        { .irq = -1 }
+};
+
 static struct omap_hwmod omap3xxx_mpu_hwmod = {
         .name           = "mpu",
+        .mpu_irqs       = omap3xxx_mpu_irqs,
         .class          = &mpu_hwmod_class,
         .main_clk       = "arm_fck",
 };
@@ -123,6 +130,24 @@ static struct omap_hwmod omap3xxx_iva_hwmod = {
         },
 };
 
+/*
+ * 'debugss' class
+ * debug and emulation sub system
+ */
+
+static struct omap_hwmod_class omap3xxx_debugss_hwmod_class = {
+        .name   = "debugss",
+};
+
+/* debugss */
+static struct omap_hwmod omap3xxx_debugss_hwmod = {
+        .name           = "debugss",
+        .class          = &omap3xxx_debugss_hwmod_class,
+        .clkdm_name     = "emu_clkdm",
+        .main_clk       = "emu_src_ck",
+        .flags          = HWMOD_NO_IDLEST,
+};
+
 /* timer class */
 static struct omap_hwmod_class_sysconfig omap3xxx_timer_1ms_sysc = {
         .rev_offs       = 0x0000,
@@ -170,6 +195,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
         .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod omap3xxx_timer1_hwmod = {
         .name           = "timer1",
@@ -253,6 +288,7 @@ static struct omap_hwmod omap3xxx_timer5_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT5_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -270,6 +306,7 @@ static struct omap_hwmod omap3xxx_timer6_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT6_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -287,6 +324,7 @@ static struct omap_hwmod omap3xxx_timer7_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT7_SHIFT,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -304,7 +342,7 @@ static struct omap_hwmod omap3xxx_timer8_hwmod = {
                         .idlest_idle_bit = OMAP3430_ST_GPT8_SHIFT,
                 },
         },
-        .dev_attr       = &capability_pwm_dev_attr,
+        .dev_attr       = &capability_dsp_pwm_dev_attr,
         .class          = &omap3xxx_timer_hwmod_class,
 };
 
@@ -2033,6 +2071,33 @@ static struct omap_hwmod omap3xxx_hdq1w_hwmod = {
         .class          = &omap2_hdq1w_class,
 };
 
+/* SAD2D */
+static struct omap_hwmod_rst_info omap3xxx_sad2d_resets[] = {
+        { .name = "rst_modem_pwron_sw", .rst_shift = 0 },
+        { .name = "rst_modem_sw", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_class omap3xxx_sad2d_class = {
+        .name                   = "sad2d",
+};
+
+static struct omap_hwmod omap3xxx_sad2d_hwmod = {
+        .name           = "sad2d",
+        .rst_lines      = omap3xxx_sad2d_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_sad2d_resets),
+        .main_clk       = "sad2d_ick",
+        .prcm           = {
+                .omap2 = {
+                        .module_offs = CORE_MOD,
+                        .prcm_reg_id = 1,
+                        .module_bit = OMAP3430_EN_SAD2D_SHIFT,
+                        .idlest_reg_id = 1,
+                        .idlest_idle_bit = OMAP3430_ST_SAD2D_SHIFT,
+                },
+        },
+        .class          = &omap3xxx_sad2d_class,
+};
+
 /*
  * '32K sync counter' class
  * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock
@@ -2068,6 +2133,49 @@ static struct omap_hwmod omap3xxx_counter_32k_hwmod = {
 };
 
 /*
+ * 'gpmc' class
+ * general purpose memory controller
+ */
+
+static struct omap_hwmod_class_sysconfig omap3xxx_gpmc_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_gpmc_hwmod_class = {
+        .name   = "gpmc",
+        .sysc   = &omap3xxx_gpmc_sysc,
+};
+
+static struct omap_hwmod_irq_info omap3xxx_gpmc_irqs[] = {
+        { .irq = 20 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod omap3xxx_gpmc_hwmod = {
+        .name           = "gpmc",
+        .class          = &omap3xxx_gpmc_hwmod_class,
+        .clkdm_name     = "core_l3_clkdm",
+        .mpu_irqs       = omap3xxx_gpmc_irqs,
+        .main_clk       = "gpmc_fck",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
+        .flags          = (HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET |
+                           HWMOD_NO_IDLEST),
+};
+
+/*
  * interfaces
  */
 
@@ -2102,6 +2210,23 @@ static struct omap_hwmod_ocp_if omap3xxx_mpu__l3_main = {
         .user   = OCP_USER_MPU,
 };
 
+static struct omap_hwmod_addr_space omap3xxx_l4_emu_addrs[] = {
+        {
+                .pa_start       = 0x54000000,
+                .pa_end         = 0x547fffff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l3 -> debugss */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__l4_debugss = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_debugss_hwmod,
+        .addr           = omap3xxx_l4_emu_addrs,
+        .user           = OCP_USER_MPU,
+};
+
 /* DSS -> l3 */
 static struct omap_hwmod_ocp_if omap3430es1_dss__l3 = {
         .master         = &omap3430es1_dss_core_hwmod,
@@ -2137,6 +2262,14 @@ static struct omap_hwmod_ocp_if am35xx_usbhsotg__l3 = {
         .user           = OCP_USER_MPU,
 };
 
+/* l3_core -> sad2d interface */
+static struct omap_hwmod_ocp_if omap3xxx_sad2d__l3 = {
+        .master         = &omap3xxx_sad2d_hwmod,
+        .slave          = &omap3xxx_l3_main_hwmod,
+        .clk            = "core_l3_ick",
+        .user           = OCP_USER_MPU,
+};
+
 /* L4_CORE -> L4_WKUP interface */
 static struct omap_hwmod_ocp_if omap3xxx_l4_core__l4_wkup = {
         .master = &omap3xxx_l4_core_hwmod,
@@ -2823,6 +2956,122 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_per__gpio3 = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+/*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap3xxx_mmu_hwmod_class = {
+        .name = "mmu",
+        .sysc = &mmu_sysc,
+};
+
+/* mmu isp */
+
+static struct omap_mmu_dev_attr mmu_isp_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 8,
+};
+
+static struct omap_hwmod omap3xxx_mmu_isp_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mmu_isp_irqs[] = {
+        { .irq = 24 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mmu_isp_addrs[] = {
+        {
+                .pa_start       = 0x480bd400,
+                .pa_end         = 0x480bd47f,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_core -> mmu isp */
+static struct omap_hwmod_ocp_if omap3xxx_l4_core__mmu_isp = {
+        .master         = &omap3xxx_l4_core_hwmod,
+        .slave          = &omap3xxx_mmu_isp_hwmod,
+        .addr           = omap3xxx_mmu_isp_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap3xxx_mmu_isp_hwmod = {
+        .name           = "mmu_isp",
+        .class          = &omap3xxx_mmu_hwmod_class,
+        .mpu_irqs       = omap3xxx_mmu_isp_irqs,
+        .main_clk       = "cam_ick",
+        .dev_attr       = &mmu_isp_dev_attr,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+
+/* mmu iva */
+
+static struct omap_mmu_dev_attr mmu_iva_dev_attr = {
+        .da_start       = 0x11000000,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap3xxx_mmu_iva_hwmod;
+static struct omap_hwmod_irq_info omap3xxx_mmu_iva_irqs[] = {
+        { .irq = 28 },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap3xxx_mmu_iva_resets[] = {
+        { .name = "mmu", .rst_shift = 1, .st_shift = 9 },
+};
+
+static struct omap_hwmod_addr_space omap3xxx_mmu_iva_addrs[] = {
+        {
+                .pa_start       = 0x5d000000,
+                .pa_end         = 0x5d00007f,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l3_main -> iva mmu */
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__mmu_iva = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_mmu_iva_hwmod,
+        .addr           = omap3xxx_mmu_iva_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap3xxx_mmu_iva_hwmod = {
+        .name           = "mmu_iva",
+        .class          = &omap3xxx_mmu_hwmod_class,
+        .mpu_irqs       = omap3xxx_mmu_iva_irqs,
+        .rst_lines      = omap3xxx_mmu_iva_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap3xxx_mmu_iva_resets),
+        .main_clk       = "iva2_ck",
+        .prcm = {
+                .omap2 = {
+                        .module_offs = OMAP3430_IVA2_MOD,
+                },
+        },
+        .dev_attr       = &mmu_iva_dev_attr,
+        .flags          = HWMOD_NO_IDLEST,
+};
+
+#endif
+
 /* l4_per -> gpio4 */
 static struct omap_hwmod_addr_space omap3xxx_gpio4_addrs[] = {
         {
@@ -3168,6 +3417,15 @@ static struct omap_hwmod_addr_space omap3xxx_counter_32k_addrs[] = {
         { }
 };
 
+static struct omap_hwmod_addr_space omap3xxx_gpmc_addrs[] = {
+        {
+                .pa_start       = 0x6e000000,
+                .pa_end         = 0x6e000fff,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 static struct omap_hwmod_ocp_if omap3xxx_l4_wkup__counter_32k = {
         .master         = &omap3xxx_l4_wkup_hwmod,
         .slave          = &omap3xxx_counter_32k_hwmod,
@@ -3277,10 +3535,19 @@ static struct omap_hwmod_ocp_if am35xx_l4_core__emac = {
         .user           = OCP_USER_MPU,
 };
 
+static struct omap_hwmod_ocp_if omap3xxx_l3_main__gpmc = {
+        .master         = &omap3xxx_l3_main_hwmod,
+        .slave          = &omap3xxx_gpmc_hwmod,
+        .clk            = "core_l3_ick",
+        .addr           = omap3xxx_gpmc_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
 static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l3_main__l4_core,
         &omap3xxx_l3_main__l4_per,
         &omap3xxx_mpu__l3_main,
+        &omap3xxx_l3_main__l4_debugss,
         &omap3xxx_l4_core__l4_wkup,
         &omap3xxx_l4_core__mmc3,
         &omap3_l4_core__uart1,
@@ -3322,6 +3589,7 @@ static struct omap_hwmod_ocp_if *omap3xxx_hwmod_ocp_ifs[] __initdata = {
         &omap34xx_l4_core__mcspi3,
         &omap34xx_l4_core__mcspi4,
         &omap3xxx_l4_wkup__counter_32k,
+        &omap3xxx_l3_main__gpmc,
         NULL,
 };
 
@@ -3371,6 +3639,11 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
         &omap34xx_l4_core__sr2,
         &omap3xxx_l4_core__mailbox,
         &omap3xxx_l4_core__hdq1w,
+        &omap3xxx_sad2d__l3,
+        &omap3xxx_l4_core__mmu_isp,
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+        &omap3xxx_l3_main__mmu_iva,
+#endif
         NULL
 };
 
@@ -3391,6 +3664,11 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
         &omap3xxx_l4_core__es3plus_mmc1,
         &omap3xxx_l4_core__es3plus_mmc2,
         &omap3xxx_l4_core__hdq1w,
+        &omap3xxx_sad2d__l3,
+        &omap3xxx_l4_core__mmu_isp,
+#ifdef CONFIG_OMAP_IOMMU_IVA2
+        &omap3xxx_l3_main__mmu_iva,
+#endif
         NULL
 };
 
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
index c7dcb606cd0c..8d7a93525bc6 100644
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
@@ -30,6 +30,7 @@
 #include <plat/mmc.h>
 #include <plat/dmtimer.h>
 #include <plat/common.h>
+#include <plat/iommu.h>
 
 #include "omap_hwmod_common_data.h"
 #include "cm1_44xx.h"
@@ -202,6 +203,9 @@ static struct omap_hwmod omap44xx_l4_abe_hwmod = {
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+                        .lostcontext_mask = OMAP4430_LOSTMEM_AESSMEM_MASK,
+                        .flags        = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
                 },
         },
 };
@@ -258,6 +262,11 @@ static struct omap_hwmod omap44xx_mpu_private_hwmod = {
         .name           = "mpu_private",
         .class          = &omap44xx_mpu_bus_hwmod_class,
         .clkdm_name     = "mpuss_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /*
@@ -342,6 +351,7 @@ static struct omap_hwmod omap44xx_aess_hwmod = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET,
                         .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET,
+                        .lostcontext_mask = OMAP4430_LOSTCONTEXT_DFF_MASK,
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
@@ -446,6 +456,11 @@ static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_cfg_clkdm",
         .mpu_irqs       = omap44xx_ctrl_module_core_irqs,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* ctrl_module_pad_core */
@@ -453,6 +468,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
         .name           = "ctrl_module_pad_core",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_cfg_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* ctrl_module_wkup */
@@ -460,6 +480,11 @@ static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
         .name           = "ctrl_module_wkup",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* ctrl_module_pad_wkup */
@@ -467,6 +492,11 @@ static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
         .name           = "ctrl_module_pad_wkup",
         .class          = &omap44xx_ctrl_module_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /*
@@ -611,7 +641,6 @@ static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = {
 
 static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = {
         { .name = "dsp", .rst_shift = 0 },
-        { .name = "mmu_cache", .rst_shift = 1 },
 };
 
 static struct omap_hwmod omap44xx_dsp_hwmod = {
@@ -1323,6 +1352,14 @@ static struct omap_hwmod omap44xx_gpmc_hwmod = {
         .name           = "gpmc",
         .class          = &omap44xx_gpmc_hwmod_class,
         .clkdm_name     = "l3_2_clkdm",
+        /*
+         * XXX HWMOD_INIT_NO_RESET should not be needed for this IP
+         * block.  It is not being added due to any known bugs with
+         * resetting the GPMC IP block, but rather because any timings
+         * set by the bootloader are not being correctly programmed by
+         * the kernel from the board file or DT data.
+         * HWMOD_INIT_NO_RESET should be removed ASAP.
+         */
         .flags          = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
         .mpu_irqs       = omap44xx_gpmc_irqs,
         .sdma_reqs      = omap44xx_gpmc_sdma_reqs,
@@ -1631,7 +1668,6 @@ static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = {
 static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = {
         { .name = "cpu0", .rst_shift = 0 },
         { .name = "cpu1", .rst_shift = 1 },
-        { .name = "mmu_cache", .rst_shift = 2 },
 };
 
 static struct omap_hwmod omap44xx_ipu_hwmod = {
@@ -2438,6 +2474,137 @@ static struct omap_hwmod omap44xx_mmc5_hwmod = {
 };
 
 /*
+ * 'mmu' class
+ * The memory management unit performs virtual to physical address translation
+ * for its requestors.
+ */
+
+static struct omap_hwmod_class_sysconfig mmu_sysc = {
+        .rev_offs       = 0x000,
+        .sysc_offs      = 0x010,
+        .syss_offs      = 0x014,
+        .sysc_flags     = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSC_HAS_AUTOIDLE),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
+static struct omap_hwmod_class omap44xx_mmu_hwmod_class = {
+        .name = "mmu",
+        .sysc = &mmu_sysc,
+};
+
+/* mmu ipu */
+
+static struct omap_mmu_dev_attr mmu_ipu_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_mmu_ipu_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmu_ipu_irqs[] = {
+        { .irq = 100 + OMAP44XX_IRQ_GIC_START, },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap44xx_mmu_ipu_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 2 },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmu_ipu_addrs[] = {
+        {
+                .pa_start       = 0x55082000,
+                .pa_end         = 0x550820ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l3_main_2 -> mmu_ipu */
+static struct omap_hwmod_ocp_if omap44xx_l3_main_2__mmu_ipu = {
+        .master         = &omap44xx_l3_main_2_hwmod,
+        .slave          = &omap44xx_mmu_ipu_hwmod,
+        .clk            = "l3_div_ck",
+        .addr           = omap44xx_mmu_ipu_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap44xx_mmu_ipu_hwmod = {
+        .name           = "mmu_ipu",
+        .class          = &omap44xx_mmu_hwmod_class,
+        .clkdm_name     = "ducati_clkdm",
+        .mpu_irqs       = omap44xx_mmu_ipu_irqs,
+        .rst_lines      = omap44xx_mmu_ipu_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_ipu_resets),
+        .main_clk       = "ducati_clk_mux_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .dev_attr       = &mmu_ipu_dev_attr,
+};
+
+/* mmu dsp */
+
+static struct omap_mmu_dev_attr mmu_dsp_dev_attr = {
+        .da_start       = 0x0,
+        .da_end         = 0xfffff000,
+        .nr_tlb_entries = 32,
+};
+
+static struct omap_hwmod omap44xx_mmu_dsp_hwmod;
+static struct omap_hwmod_irq_info omap44xx_mmu_dsp_irqs[] = {
+        { .irq = 28 + OMAP44XX_IRQ_GIC_START },
+        { .irq = -1 }
+};
+
+static struct omap_hwmod_rst_info omap44xx_mmu_dsp_resets[] = {
+        { .name = "mmu_cache", .rst_shift = 1 },
+};
+
+static struct omap_hwmod_addr_space omap44xx_mmu_dsp_addrs[] = {
+        {
+                .pa_start       = 0x4a066000,
+                .pa_end         = 0x4a0660ff,
+                .flags          = ADDR_TYPE_RT,
+        },
+        { }
+};
+
+/* l4_cfg -> dsp */
+static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mmu_dsp = {
+        .master         = &omap44xx_l4_cfg_hwmod,
+        .slave          = &omap44xx_mmu_dsp_hwmod,
+        .clk            = "l4_div_ck",
+        .addr           = omap44xx_mmu_dsp_addrs,
+        .user           = OCP_USER_MPU | OCP_USER_SDMA,
+};
+
+static struct omap_hwmod omap44xx_mmu_dsp_hwmod = {
+        .name           = "mmu_dsp",
+        .class          = &omap44xx_mmu_hwmod_class,
+        .clkdm_name     = "tesla_clkdm",
+        .mpu_irqs       = omap44xx_mmu_dsp_irqs,
+        .rst_lines      = omap44xx_mmu_dsp_resets,
+        .rst_lines_cnt  = ARRAY_SIZE(omap44xx_mmu_dsp_resets),
+        .main_clk       = "dpll_iva_m4x2_ck",
+        .prcm = {
+                .omap4 = {
+                        .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET,
+                        .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET,
+                        .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET,
+                        .modulemode   = MODULEMODE_HWCTRL,
+                },
+        },
+        .dev_attr       = &mmu_dsp_dev_attr,
+};
+
+/*
  * 'mpu' class
  * mpu sub-system
  */
@@ -2448,6 +2615,8 @@ static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
 
 /* mpu */
 static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = {
+        { .name = "pmu0", .irq = 54 + OMAP44XX_IRQ_GIC_START },
+        { .name = "pmu1", .irq = 55 + OMAP44XX_IRQ_GIC_START },
         { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START },
         { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START },
         { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START },
@@ -2497,19 +2666,27 @@ static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
  * protocol
  */
 
+static struct omap_hwmod_class_sysconfig omap44xx_ocp2scp_sysc = {
+        .rev_offs       = 0x0000,
+        .sysc_offs      = 0x0010,
+        .syss_offs      = 0x0014,
+        .sysc_flags     = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
+                           SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
+        .idlemodes      = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
+        .sysc_fields    = &omap_hwmod_sysc_type1,
+};
+
 static struct omap_hwmod_class omap44xx_ocp2scp_hwmod_class = {
         .name   = "ocp2scp",
+        .sysc   = &omap44xx_ocp2scp_sysc,
 };
 
 /* ocp2scp_usb_phy */
-static struct omap_hwmod_opt_clk ocp2scp_usb_phy_opt_clks[] = {
-        { .role = "phy_48m", .clk = "ocp2scp_usb_phy_phy_48m" },
-};
-
 static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
         .name           = "ocp2scp_usb_phy",
         .class          = &omap44xx_ocp2scp_hwmod_class,
         .clkdm_name     = "l3_init_clkdm",
+        .main_clk       = "ocp2scp_usb_phy_phy_48m",
         .prcm = {
                 .omap4 = {
                         .clkctrl_offs = OMAP4_CM_L3INIT_USBPHYOCP2SCP_CLKCTRL_OFFSET,
@@ -2517,8 +2694,6 @@ static struct omap_hwmod omap44xx_ocp2scp_usb_phy_hwmod = {
                         .modulemode   = MODULEMODE_HWCTRL,
                 },
         },
-        .opt_clks       = ocp2scp_usb_phy_opt_clks,
-        .opt_clks_cnt   = ARRAY_SIZE(ocp2scp_usb_phy_opt_clks),
 };
 
 /*
@@ -2536,18 +2711,36 @@ static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
         .name           = "prcm_mpu",
         .class          = &omap44xx_prcm_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* cm_core_aon */
 static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
         .name           = "cm_core_aon",
         .class          = &omap44xx_prcm_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* cm_core */
 static struct omap_hwmod omap44xx_cm_core_hwmod = {
         .name           = "cm_core",
         .class          = &omap44xx_prcm_hwmod_class,
+        .flags          = HWMOD_NO_IDLEST,
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /* prm */
@@ -2583,6 +2776,11 @@ static struct omap_hwmod omap44xx_scrm_hwmod = {
         .name           = "scrm",
         .class          = &omap44xx_scrm_hwmod_class,
         .clkdm_name     = "l4_wkup_clkdm",
+        .prcm = {
+                .omap4 = {
+                        .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
+                },
+        },
 };
 
 /*
@@ -2901,6 +3099,16 @@ static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = {
         .timer_capability       = OMAP_TIMER_HAS_PWM,
 };
 
+/* timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ,
+};
+
+/* pwm timers with DSP interrupt dev attribute */
+static struct omap_timer_capability_dev_attr capability_dsp_pwm_dev_attr = {
+        .timer_capability       = OMAP_TIMER_HAS_DSP_IRQ | OMAP_TIMER_HAS_PWM,
+};
+
 /* timer1 */
 static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = {
         { .irq = 37 + OMAP44XX_IRQ_GIC_START },
@@ -3005,6 +3213,7 @@ static struct omap_hwmod omap44xx_timer5_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer6 */
@@ -3027,6 +3236,7 @@ static struct omap_hwmod omap44xx_timer6_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer7 */
@@ -3048,6 +3258,7 @@ static struct omap_hwmod omap44xx_timer7_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
+        .dev_attr       = &capability_dsp_dev_attr,
 };
 
 /* timer8 */
@@ -3069,7 +3280,7 @@ static struct omap_hwmod omap44xx_timer8_hwmod = {
                         .modulemode   = MODULEMODE_SWCTRL,
                 },
         },
-        .dev_attr       = &capability_pwm_dev_attr,
+        .dev_attr       = &capability_dsp_pwm_dev_attr,
 };
 
 /* timer9 */
@@ -5262,11 +5473,21 @@ static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
+static struct omap_hwmod_addr_space omap44xx_ocp2scp_usb_phy_addrs[] = {
+        {
+                .pa_start       = 0x4a0ad000,
+                .pa_end         = 0x4a0ad01f,
+                .flags          = ADDR_TYPE_RT
+        },
+        { }
+};
+
 /* l4_cfg -> ocp2scp_usb_phy */
 static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp2scp_usb_phy = {
         .master         = &omap44xx_l4_cfg_hwmod,
         .slave          = &omap44xx_ocp2scp_usb_phy_hwmod,
         .clk            = "l4_div_ck",
+        .addr           = omap44xx_ocp2scp_usb_phy_addrs,
         .user           = OCP_USER_MPU | OCP_USER_SDMA,
 };
 
@@ -5886,7 +6107,7 @@ static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = {
 static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = {
         {
                 .pa_start       = 0x4a0ab000,
-                .pa_end         = 0x4a0ab003,
+                .pa_end         = 0x4a0ab7ff,
                 .flags          = ADDR_TYPE_RT
         },
         {
@@ -6097,6 +6318,8 @@ static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
         &omap44xx_l4_per__mmc3,
         &omap44xx_l4_per__mmc4,
         &omap44xx_l4_per__mmc5,
+        &omap44xx_l3_main_2__mmu_ipu,
+        &omap44xx_l4_cfg__mmu_dsp,
         &omap44xx_l3_main_2__ocmc_ram,
         &omap44xx_l4_cfg__ocp2scp_usb_phy,
         &omap44xx_mpu_private__prcm_mpu,
diff --git a/arch/arm/mach-omap2/omap_hwmod_common_data.h b/arch/arm/mach-omap2/omap_hwmod_common_data.h
index dddb677fed68..2bc8f1705d4a 100644
--- a/arch/arm/mach-omap2/omap_hwmod_common_data.h
+++ b/arch/arm/mach-omap2/omap_hwmod_common_data.h
@@ -2,9 +2,8 @@
  * omap_hwmod_common_data.h - OMAP hwmod common macros and declarations
  *
  * Copyright (C) 2010-2011 Nokia Corporation
+ * Copyright (C) 2010-2012 Texas Instruments, Inc.
  * Paul Walmsley
- *
- * Copyright (C) 2010-2011 Texas Instruments, Inc.
  * Benoît Cousson
  *
  * This program is free software; you can redistribute it and/or modify
@@ -77,6 +76,8 @@ extern struct omap_hwmod omap2xxx_gpio4_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi1_hwmod;
 extern struct omap_hwmod omap2xxx_mcspi2_hwmod;
 extern struct omap_hwmod omap2xxx_counter_32k_hwmod;
+extern struct omap_hwmod omap2xxx_gpmc_hwmod;
+extern struct omap_hwmod omap2xxx_rng_hwmod;
 
 /* Common interface data across OMAP2xxx */
 extern struct omap_hwmod_ocp_if omap2xxx_l3_main__l4_core;
@@ -103,6 +104,7 @@ extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_dispc;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_rfbi;
 extern struct omap_hwmod_ocp_if omap2xxx_l4_core__dss_venc;
+extern struct omap_hwmod_ocp_if omap2xxx_l4_core__rng;
 
 /* Common IP block data */
 extern struct omap_hwmod_dma_info omap2_uart1_sdma_reqs[];
diff --git a/arch/arm/mach-omap2/pm.c b/arch/arm/mach-omap2/pm.c
index 939bd6f70b51..abefbc4d8e0b 100644
--- a/arch/arm/mach-omap2/pm.c
+++ b/arch/arm/mach-omap2/pm.c
@@ -80,7 +80,8 @@ static void __init omap2_init_processor_devices(void)
 
 int __init omap_pm_clkdms_setup(struct clockdomain *clkdm, void *unused)
 {
-        if (clkdm->flags & CLKDM_CAN_ENABLE_AUTO)
+        if ((clkdm->flags & CLKDM_CAN_ENABLE_AUTO) &&
+            !(clkdm->flags & CLKDM_MISSING_IDLE_REPORTING))
                 clkdm_allow_idle(clkdm);
         else if (clkdm->flags & CLKDM_CAN_FORCE_SLEEP &&
                  atomic_read(&clkdm->usecount) == 0)
@@ -188,7 +189,7 @@ static int __init omap2_set_init_voltage(char *vdd_name, char *clk_name,
                 goto exit;
         }
 
-        freq = clk->rate;
+        freq = clk_get_rate(clk);
         clk_put(clk);
 
         rcu_read_lock();
diff --git a/arch/arm/mach-omap2/pmu.c b/arch/arm/mach-omap2/pmu.c
new file mode 100644
index 000000000000..2a791766283d
--- /dev/null
+++ b/arch/arm/mach-omap2/pmu.c
@@ -0,0 +1,95 @@
+/*
+ * OMAP2 ARM Performance Monitoring Unit (PMU) Support
+ *
+ * Copyright (C) 2012 Texas Instruments, Inc.
+ *
+ * Contacts:
+ * Jon Hunter <jon-hunter@ti.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#include <linux/pm_runtime.h>
+
+#include <asm/pmu.h>
+
+#include <plat/omap_hwmod.h>
+#include <plat/omap_device.h>
+
+static char *omap2_pmu_oh_names[] = {"mpu"};
+static char *omap3_pmu_oh_names[] = {"mpu", "debugss"};
+static char *omap4430_pmu_oh_names[] = {"l3_main_3", "l3_instr", "debugss"};
+static struct platform_device *omap_pmu_dev;
+
+/**
+ * omap2_init_pmu - creates and registers PMU platform device
+ * @oh_num:     Number of OMAP HWMODs required to create PMU device
+ * @oh_names:   Array of OMAP HWMODS names required to create PMU device
+ *
+ * Uses OMAP HWMOD framework to create and register an ARM PMU device
+ * from a list of HWMOD names passed. Currently supports OMAP2, OMAP3
+ * and OMAP4 devices.
+ */
+static int __init omap2_init_pmu(unsigned oh_num, char *oh_names[])
+{
+        int i;
+        struct omap_hwmod *oh[3];
+        char *dev_name = "arm-pmu";
+
+        if ((!oh_num) || (oh_num > 3))
+                return -EINVAL;
+
+        for (i = 0; i < oh_num; i++) {
+                oh[i] = omap_hwmod_lookup(oh_names[i]);
+                if (!oh[i]) {
+                        pr_err("Could not look up %s hwmod\n", oh_names[i]);
+                        return -ENODEV;
+                }
+        }
+
+        omap_pmu_dev = omap_device_build_ss(dev_name, -1, oh, oh_num, NULL, 0,
+                                            NULL, 0, 0);
+        WARN(IS_ERR(omap_pmu_dev), "Can't build omap_device for %s.\n",
+             dev_name);
+
+        if (IS_ERR(omap_pmu_dev))
+                return PTR_ERR(omap_pmu_dev);
+
+        pm_runtime_enable(&omap_pmu_dev->dev);
+
+        return 0;
+}
+
+static int __init omap_init_pmu(void)
+{
+        unsigned oh_num;
+        char **oh_names;
+
+        /*
+         * To create an ARM-PMU device the following HWMODs
+         * are required for the various OMAP2+ devices.
+         *
+         * OMAP24xx:    mpu
+         * OMAP3xxx:    mpu, debugss
+         * OMAP4430:    l3_main_3, l3_instr, debugss
+         * OMAP4460/70: mpu, debugss
+         */
+        if (cpu_is_omap443x()) {
+                oh_num = ARRAY_SIZE(omap4430_pmu_oh_names);
+                oh_names = omap4430_pmu_oh_names;
+                /* XXX Remove the next two lines when CTI driver available */
+                pr_info("ARM PMU: not yet supported on OMAP4430 due to missing CTI driver\n");
+                return 0;
+        } else if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+                oh_num = ARRAY_SIZE(omap3_pmu_oh_names);
+                oh_names = omap3_pmu_oh_names;
+        } else {
+                oh_num = ARRAY_SIZE(omap2_pmu_oh_names);
+                oh_names = omap2_pmu_oh_names;
+        }
+
+        return omap2_init_pmu(oh_num, oh_names);
+}
+subsys_initcall(omap_init_pmu);
diff --git a/arch/arm/mach-omap2/powerdomain44xx.c b/arch/arm/mach-omap2/powerdomain44xx.c
index aeac6f35ca10..aceb4f464c9b 100644
--- a/arch/arm/mach-omap2/powerdomain44xx.c
+++ b/arch/arm/mach-omap2/powerdomain44xx.c
@@ -1,7 +1,7 @@
 /*
  * OMAP4 powerdomain control
  *
- * Copyright (C) 2009-2010 Texas Instruments, Inc.
+ * Copyright (C) 2009-2010, 2012 Texas Instruments, Inc.
  * Copyright (C) 2007-2009 Nokia Corporation
  *
  * Derived from mach-omap2/powerdomain.c written by Paul Walmsley
@@ -151,6 +151,34 @@ static int omap4_pwrdm_read_logic_retst(struct powerdomain *pwrdm)
         return v;
 }
 
+/**
+ * omap4_pwrdm_read_prev_logic_pwrst - read the previous logic powerstate
+ * @pwrdm: struct powerdomain * to read the state for
+ *
+ * Reads the previous logic powerstate for a powerdomain. This
+ * function must determine the previous logic powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next retention logic state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether the logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_logic_pwrst(struct powerdomain *pwrdm)
+{
+        int state;
+
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+
+        return omap4_pwrdm_read_logic_retst(pwrdm);
+}
+
 static int omap4_pwrdm_read_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
 {
         u32 m, v;
@@ -179,6 +207,35 @@ static int omap4_pwrdm_read_mem_retst(struct powerdomain *pwrdm, u8 bank)
         return v;
 }
 
+/**
+ * omap4_pwrdm_read_prev_mem_pwrst - reads the previous memory powerstate
+ * @pwrdm: struct powerdomain * to read mem powerstate for
+ * @bank: memory bank index
+ *
+ * Reads the previous memory powerstate for a powerdomain. This
+ * function must determine the previous memory powerstate by first
+ * checking the previous powerstate for the domain. If that was OFF,
+ * then logic has been lost. If previous state was RETENTION, the
+ * function reads the setting for the next memory retention state to
+ * see the actual value.  In every other case, the logic is
+ * retained. Returns either PWRDM_POWER_OFF or PWRDM_POWER_RET
+ * depending whether logic was retained or not.
+ */
+static int omap4_pwrdm_read_prev_mem_pwrst(struct powerdomain *pwrdm, u8 bank)
+{
+        int state;
+
+        state = omap4_pwrdm_read_prev_pwrst(pwrdm);
+
+        if (state == PWRDM_POWER_OFF)
+                return PWRDM_POWER_OFF;
+
+        if (state != PWRDM_POWER_RET)
+                return PWRDM_POWER_RET;
+
+        return omap4_pwrdm_read_mem_retst(pwrdm, bank);
+}
+
 static int omap4_pwrdm_wait_transition(struct powerdomain *pwrdm)
 {
         u32 c = 0;
@@ -217,9 +274,11 @@ struct pwrdm_ops omap4_pwrdm_operations = {
         .pwrdm_clear_all_prev_pwrst     = omap4_pwrdm_clear_all_prev_pwrst,
         .pwrdm_set_logic_retst  = omap4_pwrdm_set_logic_retst,
         .pwrdm_read_logic_pwrst = omap4_pwrdm_read_logic_pwrst,
+        .pwrdm_read_prev_logic_pwrst    = omap4_pwrdm_read_prev_logic_pwrst,
         .pwrdm_read_logic_retst = omap4_pwrdm_read_logic_retst,
         .pwrdm_read_mem_pwrst   = omap4_pwrdm_read_mem_pwrst,
         .pwrdm_read_mem_retst   = omap4_pwrdm_read_mem_retst,
+        .pwrdm_read_prev_mem_pwrst      = omap4_pwrdm_read_prev_mem_pwrst,
         .pwrdm_set_mem_onst     = omap4_pwrdm_set_mem_onst,
         .pwrdm_set_mem_retst    = omap4_pwrdm_set_mem_retst,
         .pwrdm_wait_transition  = omap4_pwrdm_wait_transition,
diff --git a/arch/arm/mach-omap2/prcm-common.h b/arch/arm/mach-omap2/prcm-common.h
index e5f0503a68b0..72df97482cc0 100644
--- a/arch/arm/mach-omap2/prcm-common.h
+++ b/arch/arm/mach-omap2/prcm-common.h
@@ -109,6 +109,8 @@
 #define OMAP2430_EN_MDM_INTC_MASK                       (1 << 11)
 #define OMAP2430_EN_USBHS_SHIFT                         6
 #define OMAP2430_EN_USBHS_MASK                          (1 << 6)
+#define OMAP24XX_EN_GPMC_SHIFT                          1
+#define OMAP24XX_EN_GPMC_MASK                           (1 << 1)
 
 /* CM_IDLEST1_CORE, PM_WKST1_CORE shared bits */
 #define OMAP2420_ST_MMC_SHIFT                           26
diff --git a/arch/arm/mach-orion5x/addr-map.c b/arch/arm/mach-orion5x/addr-map.c
index eaac83d1df6f..b5efc0fd31cb 100644
--- a/arch/arm/mach-orion5x/addr-map.c
+++ b/arch/arm/mach-orion5x/addr-map.c
@@ -113,7 +113,8 @@ void __init orion5x_setup_cpu_mbus_bridge(void)
         /*
          * Setup MBUS dram target info.
          */
-        orion_setup_cpu_mbus_target(&addr_map_cfg, ORION5X_DDR_WINDOW_CPU_BASE);
+        orion_setup_cpu_mbus_target(&addr_map_cfg,
+                                    (void __iomem *) ORION5X_DDR_WINDOW_CPU_BASE);
 }
 
 void __init orion5x_setup_dev_boot_win(u32 base, u32 size)
diff --git a/arch/arm/mach-orion5x/common.c b/arch/arm/mach-orion5x/common.c
index 073c7d799068..b3eb3da01160 100644
--- a/arch/arm/mach-orion5x/common.c
+++ b/arch/arm/mach-orion5x/common.c
@@ -42,12 +42,12 @@
  ****************************************************************************/
 static struct map_desc orion5x_io_desc[] __initdata = {
         {
-                .virtual        = ORION5X_REGS_VIRT_BASE,
+                .virtual        = (unsigned long) ORION5X_REGS_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_REGS_PHYS_BASE),
                 .length         = ORION5X_REGS_SIZE,
                 .type           = MT_DEVICE,
         }, {
-                .virtual        = ORION5X_PCIE_WA_VIRT_BASE,
+                .virtual        = (unsigned long) ORION5X_PCIE_WA_VIRT_BASE,
                 .pfn            = __phys_to_pfn(ORION5X_PCIE_WA_PHYS_BASE),
                 .length         = ORION5X_PCIE_WA_SIZE,
                 .type           = MT_DEVICE,
diff --git a/arch/arm/mach-orion5x/dns323-setup.c b/arch/arm/mach-orion5x/dns323-setup.c
index 0e19db69f5c4..e533588880ff 100644
--- a/arch/arm/mach-orion5x/dns323-setup.c
+++ b/arch/arm/mach-orion5x/dns323-setup.c
@@ -701,7 +701,7 @@ static void __init dns323_init(void)
                  * Note: AFAIK, rev B1 needs the same treatement but I'll let
                  * somebody else test it.
                  */
-                writel(0x5, ORION5X_SATA_VIRT_BASE | 0x2c);
+                writel(0x5, ORION5X_SATA_VIRT_BASE + 0x2c);
                 break;
         }
 }
diff --git a/arch/arm/mach-orion5x/include/mach/bridge-regs.h b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
index 11a3c1e9801f..461fd69a10ae 100644
--- a/arch/arm/mach-orion5x/include/mach/bridge-regs.h
+++ b/arch/arm/mach-orion5x/include/mach/bridge-regs.h
@@ -13,27 +13,27 @@
 
 #include <mach/orion5x.h>
 
-#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE | 0x100)
+#define CPU_CONF                (ORION5X_BRIDGE_VIRT_BASE + 0x100)
 
-#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE | 0x104)
+#define CPU_CTRL                (ORION5X_BRIDGE_VIRT_BASE + 0x104)
 
-#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE | 0x108)
+#define RSTOUTn_MASK            (ORION5X_BRIDGE_VIRT_BASE + 0x108)
 #define WDT_RESET_OUT_EN        0x0002
 
-#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE | 0x10c)
+#define CPU_SOFT_RESET          (ORION5X_BRIDGE_VIRT_BASE + 0x10c)
 
-#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE | 0x110)
+#define BRIDGE_CAUSE            (ORION5X_BRIDGE_VIRT_BASE + 0x110)
 
-#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE | 0x11C)
+#define POWER_MNG_CTRL_REG      (ORION5X_BRIDGE_VIRT_BASE + 0x11C)
 
 #define WDT_INT_REQ             0x0008
 
 #define BRIDGE_INT_TIMER1_CLR   (~0x0004)
 
-#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE | 0x200)
+#define MAIN_IRQ_CAUSE          (ORION5X_BRIDGE_VIRT_BASE + 0x200)
 
-#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE | 0x204)
+#define MAIN_IRQ_MASK           (ORION5X_BRIDGE_VIRT_BASE + 0x204)
 
-#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE | 0x300)
-#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE | 0x300)
+#define TIMER_VIRT_BASE         (ORION5X_BRIDGE_VIRT_BASE + 0x300)
+#define TIMER_PHYS_BASE         (ORION5X_BRIDGE_PHYS_BASE + 0x300)
 #endif
diff --git a/arch/arm/mach-orion5x/include/mach/orion5x.h b/arch/arm/mach-orion5x/include/mach/orion5x.h
index 1b60131b7f60..d265f5484a8e 100644
--- a/arch/arm/mach-orion5x/include/mach/orion5x.h
+++ b/arch/arm/mach-orion5x/include/mach/orion5x.h
@@ -37,7 +37,7 @@
  * fd000000     f0000000        16M     PCIe WA space (Orion-1/Orion-NAS only)
  ****************************************************************************/
 #define ORION5X_REGS_PHYS_BASE          0xf1000000
-#define ORION5X_REGS_VIRT_BASE          0xfe000000
+#define ORION5X_REGS_VIRT_BASE          IOMEM(0xfe000000)
 #define ORION5X_REGS_SIZE               SZ_1M
 
 #define ORION5X_PCIE_IO_PHYS_BASE       0xf2000000
@@ -53,7 +53,7 @@
 
 /* Relevant only for Orion-1/Orion-NAS */
 #define ORION5X_PCIE_WA_PHYS_BASE       0xf0000000
-#define ORION5X_PCIE_WA_VIRT_BASE       0xfd000000
+#define ORION5X_PCIE_WA_VIRT_BASE       IOMEM(0xfd000000)
 #define ORION5X_PCIE_WA_SIZE            SZ_16M
 
 #define ORION5X_PCIE_MEM_PHYS_BASE      0xe0000000
@@ -66,42 +66,42 @@
  * Orion Registers Map
  ******************************************************************************/
 
-#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x00000)
-#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE | 0x1500)
-#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE | 0x10000)
-#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE | 0x10000)
-#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE | (x))
+#define ORION5X_DDR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x00000)
+#define  ORION5X_DDR_WINDOW_CPU_BASE    (ORION5X_DDR_VIRT_BASE + 0x1500)
+#define ORION5X_DEV_BUS_PHYS_BASE       (ORION5X_REGS_PHYS_BASE + 0x10000)
+#define ORION5X_DEV_BUS_VIRT_BASE       (ORION5X_REGS_VIRT_BASE + 0x10000)
+#define ORION5X_DEV_BUS_REG(x)          (ORION5X_DEV_BUS_VIRT_BASE + (x))
 #define  GPIO_VIRT_BASE                 ORION5X_DEV_BUS_REG(0x0100)
-#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x0600)
-#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE | 0x1000)
-#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2000)
-#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2000)
-#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE | 0x2100)
-#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE | 0x2100)
+#define  SPI_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x0600)
+#define  I2C_PHYS_BASE                  (ORION5X_DEV_BUS_PHYS_BASE + 0x1000)
+#define  UART0_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2000)
+#define  UART0_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2000)
+#define  UART1_PHYS_BASE                (ORION5X_DEV_BUS_PHYS_BASE + 0x2100)
+#define  UART1_VIRT_BASE                (ORION5X_DEV_BUS_VIRT_BASE + 0x2100)
 
-#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE | 0x20000)
-#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x20000)
+#define ORION5X_BRIDGE_VIRT_BASE        (ORION5X_REGS_VIRT_BASE + 0x20000)
+#define ORION5X_BRIDGE_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x20000)
 
-#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x30000)
+#define ORION5X_PCI_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x30000)
 
-#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x40000)
+#define ORION5X_PCIE_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x40000)
 
-#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x50000)
-#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x50000)
+#define ORION5X_USB0_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x50000)
+#define ORION5X_USB0_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x50000)
 
-#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x60900)
-#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x60900)
+#define ORION5X_XOR_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x60900)
+#define ORION5X_XOR_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x60900)
 
-#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE | 0x70000)
-#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE | 0x70000)
+#define ORION5X_ETH_PHYS_BASE           (ORION5X_REGS_PHYS_BASE + 0x70000)
+#define ORION5X_ETH_VIRT_BASE           (ORION5X_REGS_VIRT_BASE + 0x70000)
 
-#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0x80000)
-#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0x80000)
+#define ORION5X_SATA_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0x80000)
+#define ORION5X_SATA_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0x80000)
 
-#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE | 0x90000)
+#define ORION5X_CRYPTO_PHYS_BASE        (ORION5X_REGS_PHYS_BASE + 0x90000)
 
-#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE | 0xa0000)
-#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE | 0xa0000)
+#define ORION5X_USB1_PHYS_BASE          (ORION5X_REGS_PHYS_BASE + 0xa0000)
+#define ORION5X_USB1_VIRT_BASE          (ORION5X_REGS_VIRT_BASE + 0xa0000)
 
 /*******************************************************************************
  * Device Bus Registers
diff --git a/arch/arm/mach-orion5x/irq.c b/arch/arm/mach-orion5x/irq.c
index e152641cdb0e..30a192b9c517 100644
--- a/arch/arm/mach-orion5x/irq.c
+++ b/arch/arm/mach-orion5x/irq.c
@@ -12,6 +12,7 @@
 #include <linux/gpio.h>
 #include <linux/kernel.h>
 #include <linux/irq.h>
+#include <linux/io.h>
 #include <mach/bridge-regs.h>
 #include <plat/orion-gpio.h>
 #include <plat/irq.h>
@@ -25,11 +26,11 @@ static int __initdata gpio0_irqs[4] = {
 
 void __init orion5x_init_irq(void)
 {
-        orion_irq_init(0, (void __iomem *)MAIN_IRQ_MASK);
+        orion_irq_init(0, MAIN_IRQ_MASK);
 
         /*
          * Initialize gpiolib for GPIOs 0-31.
          */
-        orion_gpio_init(NULL, 0, 32, (void __iomem *)GPIO_VIRT_BASE, 0,
+        orion_gpio_init(NULL, 0, 32, GPIO_VIRT_BASE, 0,
                         IRQ_ORION5X_GPIO_START, gpio0_irqs);
 }
diff --git a/arch/arm/mach-orion5x/pci.c b/arch/arm/mach-orion5x/pci.c
index 6921d49b988d..cd50e328db2a 100644
--- a/arch/arm/mach-orion5x/pci.c
+++ b/arch/arm/mach-orion5x/pci.c
@@ -38,7 +38,7 @@
 /*****************************************************************************
  * PCIe controller
  ****************************************************************************/
-#define PCIE_BASE       ((void __iomem *)ORION5X_PCIE_VIRT_BASE)
+#define PCIE_BASE       (ORION5X_PCIE_VIRT_BASE)
 
 void __init orion5x_pcie_id(u32 *dev, u32 *rev)
 {
@@ -111,7 +111,7 @@ static int pcie_rd_conf_wa(struct pci_bus *bus, u32 devfn,
                 return PCIBIOS_DEVICE_NOT_FOUND;
         }
 
-        ret = orion_pcie_rd_conf_wa((void __iomem *)ORION5X_PCIE_WA_VIRT_BASE,
+        ret = orion_pcie_rd_conf_wa(ORION5X_PCIE_WA_VIRT_BASE,
                                     bus, devfn, where, size, val);
 
         return ret;
@@ -188,7 +188,7 @@ static int __init pcie_setup(struct pci_sys_data *sys)
 /*****************************************************************************
  * PCI controller
  ****************************************************************************/
-#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE | (x))
+#define ORION5X_PCI_REG(x)      (ORION5X_PCI_VIRT_BASE + (x))
 #define PCI_MODE                ORION5X_PCI_REG(0xd00)
 #define PCI_CMD                 ORION5X_PCI_REG(0xc00)
 #define PCI_P2P_CONF            ORION5X_PCI_REG(0x1d14)
diff --git a/arch/arm/plat-omap/clock.c b/arch/arm/plat-omap/clock.c
index 706b7e29397f..9d7ac20ef8f9 100644
--- a/arch/arm/plat-omap/clock.c
+++ b/arch/arm/plat-omap/clock.c
@@ -312,33 +312,6 @@ void clk_enable_init_clocks(void)
         }
 }
 
-/**
- * omap_clk_get_by_name - locate OMAP struct clk by its name
- * @name: name of the struct clk to locate
- *
- * Locate an OMAP struct clk by its name.  Assumes that struct clk
- * names are unique.  Returns NULL if not found or a pointer to the
- * struct clk if found.
- */
-struct clk *omap_clk_get_by_name(const char *name)
-{
-        struct clk *c;
-        struct clk *ret = NULL;
-
-        mutex_lock(&clocks_mutex);
-
-        list_for_each_entry(c, &clocks, node) {
-                if (!strcmp(c->name, name)) {
-                        ret = c;
-                        break;
-                }
-        }
-
-        mutex_unlock(&clocks_mutex);
-
-        return ret;
-}
-
 int omap_clk_enable_autoidle_all(void)
 {
         struct clk *c;
diff --git a/arch/arm/plat-omap/include/plat/clock.h b/arch/arm/plat-omap/include/plat/clock.h
index 656b9862279e..e2e2d045e428 100644
--- a/arch/arm/plat-omap/include/plat/clock.h
+++ b/arch/arm/plat-omap/include/plat/clock.h
@@ -19,6 +19,11 @@ struct module;
 struct clk;
 struct clockdomain;
 
+/* Temporary, needed during the common clock framework conversion */
+#define __clk_get_name(clk)     (clk->name)
+#define __clk_get_parent(clk)   (clk->parent)
+#define __clk_get_rate(clk)     (clk->rate)
+
 /**
  * struct clkops - some clock function pointers
  * @enable: fn ptr that enables the current clock in hardware
diff --git a/arch/arm/plat-omap/include/plat/dmtimer.h b/arch/arm/plat-omap/include/plat/dmtimer.h
index 19e7fa577bd0..85868e98c11c 100644
--- a/arch/arm/plat-omap/include/plat/dmtimer.h
+++ b/arch/arm/plat-omap/include/plat/dmtimer.h
@@ -60,6 +60,7 @@
 #define OMAP_TIMER_ALWON                                0x40000000
 #define OMAP_TIMER_HAS_PWM                              0x20000000
 #define OMAP_TIMER_NEEDS_RESET                          0x10000000
+#define OMAP_TIMER_HAS_DSP_IRQ                          0x08000000
 
 struct omap_timer_capability_dev_attr {
         u32 timer_capability;
diff --git a/arch/arm/plat-omap/include/plat/iommu.h b/arch/arm/plat-omap/include/plat/iommu.h
index 88be3e628b33..68b5f0362f35 100644
--- a/arch/arm/plat-omap/include/plat/iommu.h
+++ b/arch/arm/plat-omap/include/plat/iommu.h
@@ -103,6 +103,19 @@ struct iommu_functions {
         ssize_t (*dump_ctx)(struct omap_iommu *obj, char *buf, ssize_t len);
 };
 
+/**
+ * struct omap_mmu_dev_attr - OMAP mmu device attributes for omap_hwmod
+ * @da_start:           device address where the va space starts.
+ * @da_end:             device address where the va space ends.
+ * @nr_tlb_entries:     number of entries supported by the translation
+ *                      look-aside buffer (TLB).
+ */
+struct omap_mmu_dev_attr {
+        u32 da_start;
+        u32 da_end;
+        int nr_tlb_entries;
+};
+
 struct iommu_platform_data {
         const char *name;
         const char *clk_name;
@@ -126,6 +139,7 @@ struct omap_iommu_arch_data {
         struct omap_iommu *iommu_dev;
 };
 
+#ifdef CONFIG_IOMMU_API
 /**
  * dev_to_omap_iommu() - retrieves an omap iommu object from a user device
  * @dev: iommu client device
@@ -136,6 +150,7 @@ static inline struct omap_iommu *dev_to_omap_iommu(struct device *dev)
 
         return arch_data->iommu_dev;
 }
+#endif
 
 /* IOMMU errors */
 #define OMAP_IOMMU_ERR_TLB_MISS         (1 << 0)
diff --git a/arch/arm/plat-omap/include/plat/omap_device.h b/arch/arm/plat-omap/include/plat/omap_device.h
index e7259c0d33ec..106f50665804 100644
--- a/arch/arm/plat-omap/include/plat/omap_device.h
+++ b/arch/arm/plat-omap/include/plat/omap_device.h
@@ -120,6 +120,10 @@ int omap_device_get_context_loss_count(struct platform_device *pdev);
 
 /* Other */
 
+int omap_device_assert_hardreset(struct platform_device *pdev,
+                                 const char *name);
+int omap_device_deassert_hardreset(struct platform_device *pdev,
+                                 const char *name);
 int omap_device_idle_hwmods(struct omap_device *od);
 int omap_device_enable_hwmods(struct omap_device *od);
 
diff --git a/arch/arm/plat-omap/include/plat/omap_hwmod.h b/arch/arm/plat-omap/include/plat/omap_hwmod.h
index 05330735f23f..b3349f7b1a2c 100644
--- a/arch/arm/plat-omap/include/plat/omap_hwmod.h
+++ b/arch/arm/plat-omap/include/plat/omap_hwmod.h
@@ -2,7 +2,7 @@
  * omap_hwmod macros, structures
  *
  * Copyright (C) 2009-2011 Nokia Corporation
- * Copyright (C) 2011 Texas Instruments, Inc.
+ * Copyright (C) 2012 Texas Instruments, Inc.
  * Paul Walmsley
  *
  * Created in collaboration with (alphabetical order): Benoît Cousson,
@@ -384,21 +384,38 @@ struct omap_hwmod_omap2_prcm {
         u8 idlest_stdby_bit;
 };
 
+/*
+ * Possible values for struct omap_hwmod_omap4_prcm.flags
+ *
+ * HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT: Some IP blocks don't have a PRCM
+ *     module-level context loss register associated with them; this
+ *     flag bit should be set in those cases
+ */
+#define HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT         (1 << 0)
 
 /**
  * struct omap_hwmod_omap4_prcm - OMAP4-specific PRCM data
  * @clkctrl_reg: PRCM address of the clock control register
  * @rstctrl_reg: address of the XXX_RSTCTRL register located in the PRM
+ * @lostcontext_mask: bitmask for selecting bits from RM_*_CONTEXT register
  * @rstst_reg: (AM33XX only) address of the XXX_RSTST register in the PRM
  * @submodule_wkdep_bit: bit shift of the WKDEP range
+ * @flags: PRCM register capabilities for this IP block
+ *
+ * If @lostcontext_mask is not defined, context loss check code uses
+ * whole register without masking. @lostcontext_mask should only be
+ * defined in cases where @context_offs register is shared by two or
+ * more hwmods.
  */
 struct omap_hwmod_omap4_prcm {
         u16             clkctrl_offs;
         u16             rstctrl_offs;
         u16             rstst_offs;
         u16             context_offs;
+        u32             lostcontext_mask;
         u8              submodule_wkdep_bit;
         u8              modulemode;
+        u8              flags;
 };
 
 
@@ -591,9 +608,7 @@ int omap_hwmod_for_each(int (*fn)(struct omap_hwmod *oh, void *data),
 int __init omap_hwmod_setup_one(const char *name);
 
 int omap_hwmod_enable(struct omap_hwmod *oh);
-int _omap_hwmod_enable(struct omap_hwmod *oh);
 int omap_hwmod_idle(struct omap_hwmod *oh);
-int _omap_hwmod_idle(struct omap_hwmod *oh);
 int omap_hwmod_shutdown(struct omap_hwmod *oh);
 
 int omap_hwmod_assert_hardreset(struct omap_hwmod *oh, const char *name);
@@ -627,11 +642,6 @@ int omap_hwmod_add_initiator_dep(struct omap_hwmod *oh,
 int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
                                  struct omap_hwmod *init_oh);
 
-int omap_hwmod_set_clockact_both(struct omap_hwmod *oh);
-int omap_hwmod_set_clockact_main(struct omap_hwmod *oh);
-int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh);
-int omap_hwmod_set_clockact_none(struct omap_hwmod *oh);
-
 int omap_hwmod_enable_wakeup(struct omap_hwmod *oh);
 int omap_hwmod_disable_wakeup(struct omap_hwmod *oh);
 
diff --git a/arch/arm/plat-omap/omap_device.c b/arch/arm/plat-omap/omap_device.c
index d5f617c542d3..cee85a55bd82 100644
--- a/arch/arm/plat-omap/omap_device.c
+++ b/arch/arm/plat-omap/omap_device.c
@@ -261,10 +261,10 @@ static void _add_clkdev(struct omap_device *od, const char *clk_alias,
                 return;
         }
 
-        r = omap_clk_get_by_name(clk_name);
+        r = clk_get(NULL, clk_name);
         if (IS_ERR(r)) {
                 dev_err(&od->pdev->dev,
-                        "omap_clk_get_by_name for %s failed\n", clk_name);
+                        "clk_get for %s failed\n", clk_name);
                 return;
         }
 
@@ -983,6 +983,61 @@ int omap_device_shutdown(struct platform_device *pdev)
 }
 
 /**
+ * omap_device_assert_hardreset - set a device's hardreset line
+ * @pdev: struct platform_device * to reset
+ * @name: const char * name of the reset line
+ *
+ * Set the hardreset line identified by @name on the IP blocks
+ * associated with the hwmods backing the platform_device @pdev.  All
+ * of the hwmods associated with @pdev must have the same hardreset
+ * line linked to them for this to work.  Passes along the return value
+ * of omap_hwmod_assert_hardreset() in the event of any failure, or
+ * returns 0 upon success.
+ */
+int omap_device_assert_hardreset(struct platform_device *pdev, const char *name)
+{
+        struct omap_device *od = to_omap_device(pdev);
+        int ret = 0;
+        int i;
+
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                ret = omap_hwmod_assert_hardreset(od->hwmods[i], name);
+                if (ret)
+                        break;
+        }
+
+        return ret;
+}
+
+/**
+ * omap_device_deassert_hardreset - release a device's hardreset line
+ * @pdev: struct platform_device * to reset
+ * @name: const char * name of the reset line
+ *
+ * Release the hardreset line identified by @name on the IP blocks
+ * associated with the hwmods backing the platform_device @pdev.  All
+ * of the hwmods associated with @pdev must have the same hardreset
+ * line linked to them for this to work.  Passes along the return
+ * value of omap_hwmod_deassert_hardreset() in the event of any
+ * failure, or returns 0 upon success.
+ */
+int omap_device_deassert_hardreset(struct platform_device *pdev,
+                                   const char *name)
+{
+        struct omap_device *od = to_omap_device(pdev);
+        int ret = 0;
+        int i;
+
+        for (i = 0; i < od->hwmods_cnt; i++) {
+                ret = omap_hwmod_deassert_hardreset(od->hwmods[i], name);
+                if (ret)
+                        break;
+        }
+
+        return ret;
+}
+
+/**
  * omap_device_align_pm_lat - activate/deactivate device to match wakeup lat lim
  * @od: struct omap_device *
  *
diff --git a/arch/arm/plat-orion/Makefile b/arch/arm/plat-orion/Makefile
index c20ce0f5ce33..a82cecb84948 100644
--- a/arch/arm/plat-orion/Makefile
+++ b/arch/arm/plat-orion/Makefile
@@ -1,10 +1,10 @@
 #
 # Makefile for the linux kernel.
 #
+ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
 
-obj-y   := irq.o pcie.o time.o common.o mpp.o addr-map.o
-obj-m   :=
-obj-n   :=
-obj-    :=
+obj-y                             += addr-map.o
 
-obj-$(CONFIG_GENERIC_GPIO) += gpio.o
+orion-gpio-$(CONFIG_GENERIC_GPIO) += gpio.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += irq.o pcie.o time.o common.o mpp.o
+obj-$(CONFIG_PLAT_ORION_LEGACY)   += $(orion-gpio-y)
diff --git a/arch/arm/plat-orion/addr-map.c b/arch/arm/plat-orion/addr-map.c
index 367ca89ac403..a7b8060c293a 100644
--- a/arch/arm/plat-orion/addr-map.c
+++ b/arch/arm/plat-orion/addr-map.c
@@ -48,7 +48,7 @@ EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
 static void __init __iomem *
 orion_win_cfg_base(const struct orion_addr_map_cfg *cfg, int win)
 {
-        return (void __iomem *)(cfg->bridge_virt_base + (win << 4));
+        return cfg->bridge_virt_base + (win << 4);
 }
 
 /*
@@ -143,19 +143,16 @@ void __init orion_config_wins(struct orion_addr_map_cfg * cfg,
  * Setup MBUS dram target info.
  */
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-                                        const u32 ddr_window_cpu_base)
+                                        const void __iomem *ddr_window_cpu_base)
 {
-        void __iomem *addr;
         int i;
         int cs;
 
         orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
 
-        addr = (void __iomem *)ddr_window_cpu_base;
-
         for (i = 0, cs = 0; i < 4; i++) {
-                u32 base = readl(addr + DDR_BASE_CS_OFF(i));
-                u32 size = readl(addr + DDR_SIZE_CS_OFF(i));
+                u32 base = readl(ddr_window_cpu_base + DDR_BASE_CS_OFF(i));
+                u32 size = readl(ddr_window_cpu_base + DDR_SIZE_CS_OFF(i));
 
                 /*
                  * Chip select enabled?
diff --git a/arch/arm/plat-orion/common.c b/arch/arm/plat-orion/common.c
index 87f53caef655..b8a688cad4c2 100644
--- a/arch/arm/plat-orion/common.c
+++ b/arch/arm/plat-orion/common.c
@@ -86,13 +86,13 @@ static void __init uart_complete(
         struct platform_device *orion_uart,
         struct plat_serial8250_port *data,
         struct resource *resources,
-        unsigned int membase,
+        void __iomem *membase,
         resource_size_t mapbase,
         unsigned int irq,
         struct clk *clk)
 {
         data->mapbase = mapbase;
-        data->membase = (void __iomem *)membase;
+        data->membase = membase;
         data->irq = irq;
         data->uartclk = uart_get_clk_rate(clk);
         orion_uart->dev.platform_data = data;
@@ -120,7 +120,7 @@ static struct platform_device orion_uart0 = {
         .id                     = PLAT8250_DEV_PLATFORM,
 };
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
@@ -148,7 +148,7 @@ static struct platform_device orion_uart1 = {
         .id                     = PLAT8250_DEV_PLATFORM1,
 };
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
@@ -176,7 +176,7 @@ static struct platform_device orion_uart2 = {
         .id                     = PLAT8250_DEV_PLATFORM2,
 };
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
@@ -204,7 +204,7 @@ static struct platform_device orion_uart3 = {
         .id                     = 3,
 };
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk)
diff --git a/arch/arm/plat-orion/include/plat/addr-map.h b/arch/arm/plat-orion/include/plat/addr-map.h
index fd556f77562c..ec63e4a627d0 100644
--- a/arch/arm/plat-orion/include/plat/addr-map.h
+++ b/arch/arm/plat-orion/include/plat/addr-map.h
@@ -16,7 +16,7 @@ extern struct mbus_dram_target_info orion_mbus_dram_info;
 struct orion_addr_map_cfg {
         const int num_wins;     /* Total number of windows */
         const int remappable_wins;
-        const u32 bridge_virt_base;
+        void __iomem *bridge_virt_base;
 
         /* If NULL, the default cpu_win_can_remap will be used, using
            the value in remappable_wins */
@@ -49,5 +49,5 @@ void __init orion_setup_cpu_win(const struct orion_addr_map_cfg *cfg,
                                 const u8 attr, const int remap);
 
 void __init orion_setup_cpu_mbus_target(const struct orion_addr_map_cfg *cfg,
-                                        const u32 ddr_window_cpu_base);
+                                        const void __iomem *ddr_window_cpu_base);
 #endif
diff --git a/arch/arm/plat-orion/include/plat/common.h b/arch/arm/plat-orion/include/plat/common.h
index ae2377ef63e5..6bbc3fe5f58e 100644
--- a/arch/arm/plat-orion/include/plat/common.h
+++ b/arch/arm/plat-orion/include/plat/common.h
@@ -13,22 +13,22 @@
 
 struct dsa_platform_data;
 
-void __init orion_uart0_init(unsigned int membase,
+void __init orion_uart0_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
 
-void __init orion_uart1_init(unsigned int membase,
+void __init orion_uart1_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
 
-void __init orion_uart2_init(unsigned int membase,
+void __init orion_uart2_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
 
-void __init orion_uart3_init(unsigned int membase,
+void __init orion_uart3_init(void __iomem *membase,
                              resource_size_t mapbase,
                              unsigned int irq,
                              struct clk *clk);
diff --git a/arch/arm/plat-orion/include/plat/mpp.h b/arch/arm/plat-orion/include/plat/mpp.h
index 723adce99f41..254552fee889 100644
--- a/arch/arm/plat-orion/include/plat/mpp.h
+++ b/arch/arm/plat-orion/include/plat/mpp.h
@@ -29,6 +29,6 @@
 #define MPP_OUTPUT_MASK         GENERIC_MPP(0, 0x0, 0, 1)
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-                           unsigned int mpp_max, unsigned int dev_bus);
+                           unsigned int mpp_max, void __iomem *dev_bus);
 
 #endif
diff --git a/arch/arm/plat-orion/include/plat/time.h b/arch/arm/plat-orion/include/plat/time.h
index 4d5f1f6e18df..07527e417c62 100644
--- a/arch/arm/plat-orion/include/plat/time.h
+++ b/arch/arm/plat-orion/include/plat/time.h
@@ -11,9 +11,9 @@
 #ifndef __PLAT_TIME_H
 #define __PLAT_TIME_H
 
-void orion_time_set_base(u32 timer_base);
+void orion_time_set_base(void __iomem *timer_base);
 
-void orion_time_init(u32 bridge_base, u32 bridge_timer1_clr_mask,
+void orion_time_init(void __iomem *bridge_base, u32 bridge_timer1_clr_mask,
                      unsigned int irq, unsigned int tclk);
 
 
diff --git a/arch/arm/plat-orion/mpp.c b/arch/arm/plat-orion/mpp.c
index 7740bb31d662..e686fe76a96b 100644
--- a/arch/arm/plat-orion/mpp.c
+++ b/arch/arm/plat-orion/mpp.c
@@ -18,15 +18,15 @@
 #include <plat/mpp.h>
 
 /* Address of the ith MPP control register */
-static __init unsigned long mpp_ctrl_addr(unsigned int i,
-                                          unsigned long dev_bus)
+static __init void __iomem *mpp_ctrl_addr(unsigned int i,
+                                          void __iomem *dev_bus)
 {
         return dev_bus + (i) * 4;
 }
 
 
 void __init orion_mpp_conf(unsigned int *mpp_list, unsigned int variant_mask,
-                           unsigned int mpp_max, unsigned int dev_bus)
+                           unsigned int mpp_max, void __iomem *dev_bus)
 {
         unsigned int mpp_nr_regs = (1 + mpp_max/8);
         u32 mpp_ctrl[mpp_nr_regs];
diff --git a/arch/arm/plat-orion/time.c b/arch/arm/plat-orion/time.c
index 1ed8d1397fcf..0f4fa863dd55 100644
--- a/arch/arm/plat-orion/time.c
+++ b/arch/arm/plat-orion/time.c
@@ -180,13 +180,13 @@ static struct irqaction orion_timer_irq = {
 };
 
 void __init
-orion_time_set_base(u32 _timer_base)
+orion_time_set_base(void __iomem *_timer_base)
 {
-        timer_base = (void __iomem *)_timer_base;
+        timer_base = _timer_base;
 }
 
 void __init
-orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
+orion_time_init(void __iomem *_bridge_base, u32 _bridge_timer1_clr_mask,
                 unsigned int irq, unsigned int tclk)
 {
         u32 u;
@@ -194,7 +194,7 @@ orion_time_init(u32 _bridge_base, u32 _bridge_timer1_clr_mask,
         /*
          * Set SoC-specific data.
          */
-        bridge_base = (void __iomem *)_bridge_base;
+        bridge_base = _bridge_base;
         bridge_timer1_clr_mask = _bridge_timer1_clr_mask;
 
         ticks_per_jiffy = (tclk + HZ/2) / HZ;
diff --git a/drivers/char/hw_random/omap-rng.c b/drivers/char/hw_random/omap-rng.c
index 4fbdceb6f773..a5effd813abd 100644
--- a/drivers/char/hw_random/omap-rng.c
+++ b/drivers/char/hw_random/omap-rng.c
@@ -18,11 +18,12 @@
 #include <linux/module.h>
 #include <linux/init.h>
 #include <linux/random.h>
-#include <linux/clk.h>
 #include <linux/err.h>
 #include <linux/platform_device.h>
 #include <linux/hw_random.h>
 #include <linux/delay.h>
+#include <linux/slab.h>
+#include <linux/pm_runtime.h>
 
 #include <asm/io.h>
 
@@ -46,26 +47,36 @@
 #define RNG_SYSSTATUS           0x44            /* System status
                                                         [0] = RESETDONE */
 
-static void __iomem *rng_base;
-static struct clk *rng_ick;
-static struct platform_device *rng_dev;
+/**
+ * struct omap_rng_private_data - RNG IP block-specific data
+ * @base: virtual address of the beginning of the RNG IP block registers
+ * @mem_res: struct resource * for the IP block registers physical memory
+ */
+struct omap_rng_private_data {
+        void __iomem *base;
+        struct resource *mem_res;
+};
 
-static inline u32 omap_rng_read_reg(int reg)
+static inline u32 omap_rng_read_reg(struct omap_rng_private_data *priv, int reg)
 {
-        return __raw_readl(rng_base + reg);
+        return __raw_readl(priv->base + reg);
 }
 
-static inline void omap_rng_write_reg(int reg, u32 val)
+static inline void omap_rng_write_reg(struct omap_rng_private_data *priv,
+                                      int reg, u32 val)
 {
-        __raw_writel(val, rng_base + reg);
+        __raw_writel(val, priv->base + reg);
 }
 
 static int omap_rng_data_present(struct hwrng *rng, int wait)
 {
+        struct omap_rng_private_data *priv;
         int data, i;
 
+        priv = (struct omap_rng_private_data *)rng->priv;
+
         for (i = 0; i < 20; i++) {
-                data = omap_rng_read_reg(RNG_STAT_REG) ? 0 : 1;
+                data = omap_rng_read_reg(priv, RNG_STAT_REG) ? 0 : 1;
                 if (data || !wait)
                         break;
                 /* RNG produces data fast enough (2+ MBit/sec, even
@@ -80,9 +91,13 @@ static int omap_rng_data_present(struct hwrng *rng, int wait)
 
 static int omap_rng_data_read(struct hwrng *rng, u32 *data)
 {
-        *data = omap_rng_read_reg(RNG_OUT_REG);
+        struct omap_rng_private_data *priv;
+
+        priv = (struct omap_rng_private_data *)rng->priv;
+
+        *data = omap_rng_read_reg(priv, RNG_OUT_REG);
 
-        return 4;
+        return sizeof(u32);
 }
 
 static struct hwrng omap_rng_ops = {
@@ -93,69 +108,68 @@ static struct hwrng omap_rng_ops = {
 
 static int __devinit omap_rng_probe(struct platform_device *pdev)
 {
-        struct resource *res;
+        struct omap_rng_private_data *priv;
         int ret;
 
-        /*
-         * A bit ugly, and it will never actually happen but there can
-         * be only one RNG and this catches any bork
-         */
-        if (rng_dev)
-                return -EBUSY;
-
-        if (cpu_is_omap24xx()) {
-                rng_ick = clk_get(&pdev->dev, "ick");
-                if (IS_ERR(rng_ick)) {
-                        dev_err(&pdev->dev, "Could not get rng_ick\n");
-                        ret = PTR_ERR(rng_ick);
-                        return ret;
-                } else
-                        clk_enable(rng_ick);
-        }
+        priv = kzalloc(sizeof(struct omap_rng_private_data), GFP_KERNEL);
+        if (!priv) {
+                dev_err(&pdev->dev, "could not allocate memory\n");
+                return -ENOMEM;
+        };
 
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        omap_rng_ops.priv = (unsigned long)priv;
+        dev_set_drvdata(&pdev->dev, priv);
 
-        rng_base = devm_request_and_ioremap(&pdev->dev, res);
-        if (!rng_base) {
+        priv->mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (!priv->mem_res) {
+                ret = -ENOENT;
+                goto err_ioremap;
+        }
+
+        priv->base = devm_request_and_ioremap(&pdev->dev, priv->mem_res);
+        if (!priv->base) {
                 ret = -ENOMEM;
                 goto err_ioremap;
         }
-        dev_set_drvdata(&pdev->dev, res);
+        dev_set_drvdata(&pdev->dev, priv);
+
+        pm_runtime_enable(&pdev->dev);
+        pm_runtime_get_sync(&pdev->dev);
 
         ret = hwrng_register(&omap_rng_ops);
         if (ret)
                 goto err_register;
 
         dev_info(&pdev->dev, "OMAP Random Number Generator ver. %02x\n",
-                omap_rng_read_reg(RNG_REV_REG));
-        omap_rng_write_reg(RNG_MASK_REG, 0x1);
+                 omap_rng_read_reg(priv, RNG_REV_REG));
 
-        rng_dev = pdev;
+        omap_rng_write_reg(priv, RNG_MASK_REG, 0x1);
 
         return 0;
 
 err_register:
-        rng_base = NULL;
+        priv->base = NULL;
+        pm_runtime_disable(&pdev->dev);
 err_ioremap:
-        if (cpu_is_omap24xx()) {
-                clk_disable(rng_ick);
-                clk_put(rng_ick);
-        }
+        kfree(priv);
+
         return ret;
 }
 
 static int __exit omap_rng_remove(struct platform_device *pdev)
 {
+        struct omap_rng_private_data *priv = dev_get_drvdata(&pdev->dev);
+
         hwrng_unregister(&omap_rng_ops);
 
-        omap_rng_write_reg(RNG_MASK_REG, 0x0);
+        omap_rng_write_reg(priv, RNG_MASK_REG, 0x0);
 
-        if (cpu_is_omap24xx()) {
-                clk_disable(rng_ick);
-                clk_put(rng_ick);
-        }
+        pm_runtime_put_sync(&pdev->dev);
+        pm_runtime_disable(&pdev->dev);
+
+        release_mem_region(priv->mem_res->start, resource_size(priv->mem_res));
 
-        rng_base = NULL;
+        kfree(priv);
 
         return 0;
 }
@@ -164,13 +178,21 @@ static int __exit omap_rng_remove(struct platform_device *pdev)
 
 static int omap_rng_suspend(struct device *dev)
 {
-        omap_rng_write_reg(RNG_MASK_REG, 0x0);
+        struct omap_rng_private_data *priv = dev_get_drvdata(dev);
+
+        omap_rng_write_reg(priv, RNG_MASK_REG, 0x0);
+        pm_runtime_put_sync(dev);
+
         return 0;
 }
 
 static int omap_rng_resume(struct device *dev)
 {
-        omap_rng_write_reg(RNG_MASK_REG, 0x1);
+        struct omap_rng_private_data *priv = dev_get_drvdata(dev);
+
+        pm_runtime_get_sync(dev);
+        omap_rng_write_reg(priv, RNG_MASK_REG, 0x1);
+
         return 0;
 }
 
@@ -198,9 +220,6 @@ static struct platform_driver omap_rng_driver = {
 
 static int __init omap_rng_init(void)
 {
-        if (!cpu_is_omap16xx() && !cpu_is_omap24xx())
-                return -ENODEV;
-
         return platform_driver_register(&omap_rng_driver);
 }
 
diff --git a/drivers/crypto/mv_cesa.c b/drivers/crypto/mv_cesa.c
index 21c1a87032b7..24ccae453e79 100644
--- a/drivers/crypto/mv_cesa.c
+++ b/drivers/crypto/mv_cesa.c
@@ -19,6 +19,9 @@
 #include <linux/clk.h>
 #include <crypto/internal/hash.h>
 #include <crypto/sha.h>
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_irq.h>
 
 #include "mv_cesa.h"
 
@@ -1062,7 +1065,10 @@ static int mv_probe(struct platform_device *pdev)
                 goto err_unmap_reg;
         }
 
-        irq = platform_get_irq(pdev, 0);
+        if (pdev->dev.of_node)
+                irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+        else
+                irq = platform_get_irq(pdev, 0);
         if (irq < 0 || irq == NO_IRQ) {
                 ret = irq;
                 goto err_unmap_sram;
@@ -1170,12 +1176,19 @@ static int mv_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id mv_cesa_of_match_table[] = {
+        { .compatible = "marvell,orion-crypto", },
+        {}
+};
+MODULE_DEVICE_TABLE(of, mv_cesa_of_match_table);
+
 static struct platform_driver marvell_crypto = {
         .probe          = mv_probe,
-        .remove         = mv_remove,
+        .remove         = __devexit_p(mv_remove),
         .driver         = {
                 .owner  = THIS_MODULE,
                 .name   = "mv_crypto",
+                .of_match_table = of_match_ptr(mv_cesa_of_match_table),
         },
 };
 MODULE_ALIAS("platform:mv_crypto");
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index aa73ef3233b8..d055cee36942 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -150,6 +150,12 @@ config GPIO_MSM_V2
           Qualcomm MSM chips.  Most of the pins on the MSM can be
           selected for GPIO, and are controlled by this driver.
 
+config GPIO_MVEBU
+        def_bool y
+        depends on ARCH_MVEBU
+        select GPIO_GENERIC
+        select GENERIC_IRQ_CHIP
+
 config GPIO_MXC
         def_bool y
         depends on ARCH_MXC
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index b2c109d1303d..9aeed6707326 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -42,6 +42,7 @@ obj-$(CONFIG_GPIO_MPC8XXX)	+= gpio-mpc8xxx.o
 obj-$(CONFIG_GPIO_MSIC)         += gpio-msic.o
 obj-$(CONFIG_GPIO_MSM_V1)       += gpio-msm-v1.o
 obj-$(CONFIG_GPIO_MSM_V2)       += gpio-msm-v2.o
+obj-$(CONFIG_GPIO_MVEBU)        += gpio-mvebu.o
 obj-$(CONFIG_GPIO_MXC)          += gpio-mxc.o
 obj-$(CONFIG_GPIO_MXS)          += gpio-mxs.o
 obj-$(CONFIG_ARCH_OMAP)         += gpio-omap.o
diff --git a/drivers/gpio/gpio-mvebu.c b/drivers/gpio/gpio-mvebu.c
new file mode 100644
index 000000000000..902af437eaf2
--- /dev/null
+++ b/drivers/gpio/gpio-mvebu.c
@@ -0,0 +1,679 @@
+/*
+ * GPIO driver for Marvell SoCs
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ *
+ * This driver is a fairly straightforward GPIO driver for the
+ * complete family of Marvell EBU SoC platforms (Orion, Dove,
+ * Kirkwood, Discovery, Armada 370/XP). The only complexity of this
+ * driver is the different register layout that exists between the
+ * non-SMP platforms (Orion, Dove, Kirkwood, Armada 370) and the SMP
+ * platforms (MV78200 from the Discovery family and the Armada
+ * XP). Therefore, this driver handles three variants of the GPIO
+ * block:
+ * - the basic variant, called "orion-gpio", with the simplest
+ *   register set. Used on Orion, Dove, Kirkwoord, Armada 370 and
+ *   non-SMP Discovery systems
+ * - the mv78200 variant for MV78200 Discovery systems. This variant
+ *   turns the edge mask and level mask registers into CPU0 edge
+ *   mask/level mask registers, and adds CPU1 edge mask/level mask
+ *   registers.
+ * - the armadaxp variant for Armada XP systems. This variant keeps
+ *   the normal cause/edge mask/level mask registers when the global
+ *   interrupts are used, but adds per-CPU cause/edge mask/level mask
+ *   registers n a separate memory area for the per-CPU GPIO
+ *   interrupts.
+ */
+
+#include <linux/module.h>
+#include <linux/gpio.h>
+#include <linux/irq.h>
+#include <linux/slab.h>
+#include <linux/irqdomain.h>
+#include <linux/io.h>
+#include <linux/of_irq.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/consumer.h>
+
+/*
+ * GPIO unit register offsets.
+ */
+#define GPIO_OUT_OFF            0x0000
+#define GPIO_IO_CONF_OFF        0x0004
+#define GPIO_BLINK_EN_OFF       0x0008
+#define GPIO_IN_POL_OFF         0x000c
+#define GPIO_DATA_IN_OFF        0x0010
+#define GPIO_EDGE_CAUSE_OFF     0x0014
+#define GPIO_EDGE_MASK_OFF      0x0018
+#define GPIO_LEVEL_MASK_OFF     0x001c
+
+/* The MV78200 has per-CPU registers for edge mask and level mask */
+#define GPIO_EDGE_MASK_MV78200_OFF(cpu)   ((cpu) ? 0x30 : 0x18)
+#define GPIO_LEVEL_MASK_MV78200_OFF(cpu)  ((cpu) ? 0x34 : 0x1C)
+
+/* The Armada XP has per-CPU registers for interrupt cause, interrupt
+ * mask and interrupt level mask. Those are relative to the
+ * percpu_membase. */
+#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
+#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu)  (0x10 + (cpu) * 0x4)
+#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
+
+#define MVEBU_GPIO_SOC_VARIANT_ORION    0x1
+#define MVEBU_GPIO_SOC_VARIANT_MV78200  0x2
+#define MVEBU_GPIO_SOC_VARIANT_ARMADAXP 0x3
+
+#define MVEBU_MAX_GPIO_PER_BANK         32
+
+struct mvebu_gpio_chip {
+        struct gpio_chip   chip;
+        spinlock_t         lock;
+        void __iomem      *membase;
+        void __iomem      *percpu_membase;
+        unsigned int       irqbase;
+        struct irq_domain *domain;
+        int                soc_variant;
+};
+
+/*
+ * Functions returning addresses of individual registers for a given
+ * GPIO controller.
+ */
+static inline void __iomem *mvebu_gpioreg_out(struct mvebu_gpio_chip *mvchip)
+{
+        return mvchip->membase + GPIO_OUT_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_io_conf(struct mvebu_gpio_chip *mvchip)
+{
+        return mvchip->membase + GPIO_IO_CONF_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_in_pol(struct mvebu_gpio_chip *mvchip)
+{
+        return mvchip->membase + GPIO_IN_POL_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_data_in(struct mvebu_gpio_chip *mvchip)
+{
+        return mvchip->membase + GPIO_DATA_IN_OFF;
+}
+
+static inline void __iomem *mvebu_gpioreg_edge_cause(struct mvebu_gpio_chip *mvchip)
+{
+        int cpu;
+
+        switch(mvchip->soc_variant) {
+        case MVEBU_GPIO_SOC_VARIANT_ORION:
+        case MVEBU_GPIO_SOC_VARIANT_MV78200:
+                return mvchip->membase + GPIO_EDGE_CAUSE_OFF;
+        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+                cpu = smp_processor_id();
+                return mvchip->percpu_membase + GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu);
+        default:
+                BUG();
+        }
+}
+
+static inline void __iomem *mvebu_gpioreg_edge_mask(struct mvebu_gpio_chip *mvchip)
+{
+        int cpu;
+
+        switch(mvchip->soc_variant) {
+        case MVEBU_GPIO_SOC_VARIANT_ORION:
+                return mvchip->membase + GPIO_EDGE_MASK_OFF;
+        case MVEBU_GPIO_SOC_VARIANT_MV78200:
+                cpu = smp_processor_id();
+                return mvchip->membase + GPIO_EDGE_MASK_MV78200_OFF(cpu);
+        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+                cpu = smp_processor_id();
+                return mvchip->percpu_membase + GPIO_EDGE_MASK_ARMADAXP_OFF(cpu);
+        default:
+                BUG();
+        }
+}
+
+static void __iomem *mvebu_gpioreg_level_mask(struct mvebu_gpio_chip *mvchip)
+{
+        int cpu;
+
+        switch(mvchip->soc_variant) {
+        case MVEBU_GPIO_SOC_VARIANT_ORION:
+                return mvchip->membase + GPIO_LEVEL_MASK_OFF;
+        case MVEBU_GPIO_SOC_VARIANT_MV78200:
+                cpu = smp_processor_id();
+                return mvchip->membase + GPIO_LEVEL_MASK_MV78200_OFF(cpu);
+        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+                cpu = smp_processor_id();
+                return mvchip->percpu_membase + GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu);
+        default:
+                BUG();
+        }
+}
+
+/*
+ * Functions implementing the gpio_chip methods
+ */
+
+int mvebu_gpio_request(struct gpio_chip *chip, unsigned pin)
+{
+        return pinctrl_request_gpio(chip->base + pin);
+}
+
+void mvebu_gpio_free(struct gpio_chip *chip, unsigned pin)
+{
+        pinctrl_free_gpio(chip->base + pin);
+}
+
+static void mvebu_gpio_set(struct gpio_chip *chip, unsigned pin, int value)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        unsigned long flags;
+        u32 u;
+
+        spin_lock_irqsave(&mvchip->lock, flags);
+        u = readl_relaxed(mvebu_gpioreg_out(mvchip));
+        if (value)
+                u |= 1 << pin;
+        else
+                u &= ~(1 << pin);
+        writel_relaxed(u, mvebu_gpioreg_out(mvchip));
+        spin_unlock_irqrestore(&mvchip->lock, flags);
+}
+
+static int mvebu_gpio_get(struct gpio_chip *chip, unsigned pin)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        u32 u;
+
+        if (readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin)) {
+                u = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) ^
+                        readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+        } else {
+                u = readl_relaxed(mvebu_gpioreg_out(mvchip));
+        }
+
+        return (u >> pin) & 1;
+}
+
+static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        unsigned long flags;
+        int ret;
+        u32 u;
+
+        /* Check with the pinctrl driver whether this pin is usable as
+         * an input GPIO */
+        ret = pinctrl_gpio_direction_input(chip->base + pin);
+        if (ret)
+                return ret;
+
+        spin_lock_irqsave(&mvchip->lock, flags);
+        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
+        u |= 1 << pin;
+        writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
+        spin_unlock_irqrestore(&mvchip->lock, flags);
+
+        return 0;
+}
+
+static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
+                                       int value)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        unsigned long flags;
+        int ret;
+        u32 u;
+
+        /* Check with the pinctrl driver whether this pin is usable as
+         * an output GPIO */
+        ret = pinctrl_gpio_direction_output(chip->base + pin);
+        if (ret)
+                return ret;
+
+        spin_lock_irqsave(&mvchip->lock, flags);
+        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip));
+        u &= ~(1 << pin);
+        writel_relaxed(u, mvebu_gpioreg_io_conf(mvchip));
+        spin_unlock_irqrestore(&mvchip->lock, flags);
+
+        return 0;
+}
+
+static int mvebu_gpio_to_irq(struct gpio_chip *chip, unsigned pin)
+{
+        struct mvebu_gpio_chip *mvchip =
+                container_of(chip, struct mvebu_gpio_chip, chip);
+        return irq_create_mapping(mvchip->domain, pin);
+}
+
+/*
+ * Functions implementing the irq_chip methods
+ */
+static void mvebu_gpio_irq_ack(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = ~(1 << (d->irq - gc->irq_base));
+
+        irq_gc_lock(gc);
+        writel_relaxed(mask, mvebu_gpioreg_edge_cause(mvchip));
+        irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_mask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = 1 << (d->irq - gc->irq_base);
+
+        irq_gc_lock(gc);
+        gc->mask_cache &= ~mask;
+        writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
+        irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = 1 << (d->irq - gc->irq_base);
+
+        irq_gc_lock(gc);
+        gc->mask_cache |= mask;
+        writel_relaxed(gc->mask_cache, mvebu_gpioreg_edge_mask(mvchip));
+        irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_mask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = 1 << (d->irq - gc->irq_base);
+
+        irq_gc_lock(gc);
+        gc->mask_cache &= ~mask;
+        writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
+        irq_gc_unlock(gc);
+}
+
+static void mvebu_gpio_level_irq_unmask(struct irq_data *d)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        u32 mask = 1 << (d->irq - gc->irq_base);
+
+        irq_gc_lock(gc);
+        gc->mask_cache |= mask;
+        writel_relaxed(gc->mask_cache, mvebu_gpioreg_level_mask(mvchip));
+        irq_gc_unlock(gc);
+}
+
+/*****************************************************************************
+ * MVEBU GPIO IRQ
+ *
+ * GPIO_IN_POL register controls whether GPIO_DATA_IN will hold the same
+ * value of the line or the opposite value.
+ *
+ * Level IRQ handlers: DATA_IN is used directly as cause register.
+ *                     Interrupt are masked by LEVEL_MASK registers.
+ * Edge IRQ handlers:  Change in DATA_IN are latched in EDGE_CAUSE.
+ *                     Interrupt are masked by EDGE_MASK registers.
+ * Both-edge handlers: Similar to regular Edge handlers, but also swaps
+ *                     the polarity to catch the next line transaction.
+ *                     This is a race condition that might not perfectly
+ *                     work on some use cases.
+ *
+ * Every eight GPIO lines are grouped (OR'ed) before going up to main
+ * cause register.
+ *
+ *                    EDGE  cause    mask
+ *        data-in   /--------| |-----| |----\
+ *     -----| |-----                         ---- to main cause reg
+ *           X      \----------------| |----/
+ *        polarity    LEVEL          mask
+ *
+ ****************************************************************************/
+
+static int mvebu_gpio_irq_set_type(struct irq_data *d, unsigned int type)
+{
+        struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);
+        struct irq_chip_type *ct = irq_data_get_chip_type(d);
+        struct mvebu_gpio_chip *mvchip = gc->private;
+        int pin;
+        u32 u;
+
+        pin = d->hwirq;
+
+        u = readl_relaxed(mvebu_gpioreg_io_conf(mvchip)) & (1 << pin);
+        if (!u) {
+                return -EINVAL;
+        }
+
+        type &= IRQ_TYPE_SENSE_MASK;
+        if (type == IRQ_TYPE_NONE)
+                return -EINVAL;
+
+        /* Check if we need to change chip and handler */
+        if (!(ct->type & type))
+                if (irq_setup_alt_chip(d, type))
+                        return -EINVAL;
+
+        /*
+         * Configure interrupt polarity.
+         */
+        switch(type) {
+        case IRQ_TYPE_EDGE_RISING:
+        case IRQ_TYPE_LEVEL_HIGH:
+                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+                u &= ~(1 << pin);
+                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+        case IRQ_TYPE_EDGE_FALLING:
+        case IRQ_TYPE_LEVEL_LOW:
+                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+                u |= 1 << pin;
+                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+        case IRQ_TYPE_EDGE_BOTH: {
+                u32 v;
+
+                v = readl_relaxed(mvebu_gpioreg_in_pol(mvchip)) ^
+                        readl_relaxed(mvebu_gpioreg_data_in(mvchip));
+
+                /*
+                 * set initial polarity based on current input level
+                 */
+                u = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+                if (v & (1 << pin))
+                        u |= 1 << pin;          /* falling */
+                else
+                        u &= ~(1 << pin);       /* rising */
+                writel_relaxed(u, mvebu_gpioreg_in_pol(mvchip));
+        }
+        }
+        return 0;
+}
+
+static void mvebu_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
+{
+        struct mvebu_gpio_chip *mvchip = irq_get_handler_data(irq);
+        u32 cause, type;
+        int i;
+
+        if (mvchip == NULL)
+                return;
+
+        cause = readl_relaxed(mvebu_gpioreg_data_in(mvchip)) &
+                readl_relaxed(mvebu_gpioreg_level_mask(mvchip));
+        cause |= readl_relaxed(mvebu_gpioreg_edge_cause(mvchip)) &
+                readl_relaxed(mvebu_gpioreg_edge_mask(mvchip));
+
+        for (i = 0; i < mvchip->chip.ngpio; i++) {
+                int irq;
+
+                irq = mvchip->irqbase + i;
+
+                if (!(cause & (1 << i)))
+                        continue;
+
+                type = irqd_get_trigger_type(irq_get_irq_data(irq));
+                if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH) {
+                        /* Swap polarity (race with GPIO line) */
+                        u32 polarity;
+
+                        polarity = readl_relaxed(mvebu_gpioreg_in_pol(mvchip));
+                        polarity ^= 1 << i;
+                        writel_relaxed(polarity, mvebu_gpioreg_in_pol(mvchip));
+                }
+                generic_handle_irq(irq);
+        }
+}
+
+static struct platform_device_id mvebu_gpio_ids[] = {
+        {
+                .name = "orion-gpio",
+        }, {
+                .name = "mv78200-gpio",
+        }, {
+                .name = "armadaxp-gpio",
+        }, {
+                /* sentinel */
+        },
+};
+MODULE_DEVICE_TABLE(platform, mvebu_gpio_ids);
+
+static struct of_device_id mvebu_gpio_of_match[] __devinitdata = {
+        {
+                .compatible = "marvell,orion-gpio",
+                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_ORION,
+        },
+        {
+                .compatible = "marvell,mv78200-gpio",
+                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_MV78200,
+        },
+        {
+                .compatible = "marvell,armadaxp-gpio",
+                .data       = (void*) MVEBU_GPIO_SOC_VARIANT_ARMADAXP,
+        },
+        {
+                /* sentinel */
+        },
+};
+MODULE_DEVICE_TABLE(of, mvebu_gpio_of_match);
+
+static int __devinit mvebu_gpio_probe(struct platform_device *pdev)
+{
+        struct mvebu_gpio_chip *mvchip;
+        const struct of_device_id *match;
+        struct device_node *np = pdev->dev.of_node;
+        struct resource *res;
+        struct irq_chip_generic *gc;
+        struct irq_chip_type *ct;
+        unsigned int ngpios;
+        int soc_variant;
+        int i, cpu, id;
+
+        match = of_match_device(mvebu_gpio_of_match, &pdev->dev);
+        if (match)
+                soc_variant = (int) match->data;
+        else
+                soc_variant = MVEBU_GPIO_SOC_VARIANT_ORION;
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        if (! res) {
+                dev_err(&pdev->dev, "Cannot get memory resource\n");
+                return -ENODEV;
+        }
+
+        mvchip = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_gpio_chip), GFP_KERNEL);
+        if (! mvchip){
+                dev_err(&pdev->dev, "Cannot allocate memory\n");
+                return -ENOMEM;
+        }
+
+        if (of_property_read_u32(pdev->dev.of_node, "ngpios", &ngpios)) {
+                dev_err(&pdev->dev, "Missing ngpios OF property\n");
+                return -ENODEV;
+        }
+
+        id = of_alias_get_id(pdev->dev.of_node, "gpio");
+        if (id < 0) {
+                dev_err(&pdev->dev, "Couldn't get OF id\n");
+                return id;
+        }
+
+        mvchip->soc_variant = soc_variant;
+        mvchip->chip.label = dev_name(&pdev->dev);
+        mvchip->chip.dev = &pdev->dev;
+        mvchip->chip.request = mvebu_gpio_request;
+        mvchip->chip.direction_input = mvebu_gpio_direction_input;
+        mvchip->chip.get = mvebu_gpio_get;
+        mvchip->chip.direction_output = mvebu_gpio_direction_output;
+        mvchip->chip.set = mvebu_gpio_set;
+        mvchip->chip.to_irq = mvebu_gpio_to_irq;
+        mvchip->chip.base = id * MVEBU_MAX_GPIO_PER_BANK;
+        mvchip->chip.ngpio = ngpios;
+        mvchip->chip.can_sleep = 0;
+#ifdef CONFIG_OF
+        mvchip->chip.of_node = np;
+#endif
+
+        spin_lock_init(&mvchip->lock);
+        mvchip->membase = devm_request_and_ioremap(&pdev->dev, res);
+        if (! mvchip->membase) {
+                dev_err(&pdev->dev, "Cannot ioremap\n");
+                kfree(mvchip->chip.label);
+                return -ENOMEM;
+        }
+
+        /* The Armada XP has a second range of registers for the
+         * per-CPU registers */
+        if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
+                res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+                if (! res) {
+                        dev_err(&pdev->dev, "Cannot get memory resource\n");
+                        kfree(mvchip->chip.label);
+                        return -ENODEV;
+                }
+
+                mvchip->percpu_membase = devm_request_and_ioremap(&pdev->dev, res);
+                if (! mvchip->percpu_membase) {
+                        dev_err(&pdev->dev, "Cannot ioremap\n");
+                        kfree(mvchip->chip.label);
+                        return -ENOMEM;
+                }
+        }
+
+        /*
+         * Mask and clear GPIO interrupts.
+         */
+        switch(soc_variant) {
+        case MVEBU_GPIO_SOC_VARIANT_ORION:
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+                writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+                break;
+        case MVEBU_GPIO_SOC_VARIANT_MV78200:
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+                for (cpu = 0; cpu < 2; cpu++) {
+                        writel_relaxed(0, mvchip->membase +
+                                       GPIO_EDGE_MASK_MV78200_OFF(cpu));
+                        writel_relaxed(0, mvchip->membase +
+                                       GPIO_LEVEL_MASK_MV78200_OFF(cpu));
+                }
+                break;
+        case MVEBU_GPIO_SOC_VARIANT_ARMADAXP:
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_CAUSE_OFF);
+                writel_relaxed(0, mvchip->membase + GPIO_EDGE_MASK_OFF);
+                writel_relaxed(0, mvchip->membase + GPIO_LEVEL_MASK_OFF);
+                for (cpu = 0; cpu < 4; cpu++) {
+                        writel_relaxed(0, mvchip->percpu_membase +
+                                       GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu));
+                        writel_relaxed(0, mvchip->percpu_membase +
+                                       GPIO_EDGE_MASK_ARMADAXP_OFF(cpu));
+                        writel_relaxed(0, mvchip->percpu_membase +
+                                       GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu));
+                }
+                break;
+        default:
+                BUG();
+        }
+
+        gpiochip_add(&mvchip->chip);
+
+        /* Some gpio controllers do not provide irq support */
+        if (!of_irq_count(np))
+                return 0;
+
+        /* Setup the interrupt handlers. Each chip can have up to 4
+         * interrupt handlers, with each handler dealing with 8 GPIO
+         * pins. */
+        for (i = 0; i < 4; i++) {
+                int irq;
+                irq = platform_get_irq(pdev, i);
+                if (irq < 0)
+                        continue;
+                irq_set_handler_data(irq, mvchip);
+                irq_set_chained_handler(irq, mvebu_gpio_irq_handler);
+        }
+
+        mvchip->irqbase = irq_alloc_descs(-1, 0, ngpios, -1);
+        if (mvchip->irqbase < 0) {
+                dev_err(&pdev->dev, "no irqs\n");
+                kfree(mvchip->chip.label);
+                return -ENOMEM;
+        }
+
+        gc = irq_alloc_generic_chip("mvebu_gpio_irq", 2, mvchip->irqbase,
+                                    mvchip->membase, handle_level_irq);
+        if (! gc) {
+                dev_err(&pdev->dev, "Cannot allocate generic irq_chip\n");
+                kfree(mvchip->chip.label);
+                return -ENOMEM;
+        }
+
+        gc->private = mvchip;
+        ct = &gc->chip_types[0];
+        ct->type = IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW;
+        ct->chip.irq_mask = mvebu_gpio_level_irq_mask;
+        ct->chip.irq_unmask = mvebu_gpio_level_irq_unmask;
+        ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+        ct->chip.name = mvchip->chip.label;
+
+        ct = &gc->chip_types[1];
+        ct->type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
+        ct->chip.irq_ack = mvebu_gpio_irq_ack;
+        ct->chip.irq_mask = mvebu_gpio_edge_irq_mask;
+        ct->chip.irq_unmask = mvebu_gpio_edge_irq_unmask;
+        ct->chip.irq_set_type = mvebu_gpio_irq_set_type;
+        ct->handler = handle_edge_irq;
+        ct->chip.name = mvchip->chip.label;
+
+        irq_setup_generic_chip(gc, IRQ_MSK(ngpios), IRQ_GC_INIT_MASK_CACHE,
+                               IRQ_NOREQUEST, IRQ_LEVEL | IRQ_NOPROBE);
+
+        /* Setup irq domain on top of the generic chip. */
+        mvchip->domain = irq_domain_add_legacy(np, mvchip->chip.ngpio,
+                                               mvchip->irqbase, 0,
+                                               &irq_domain_simple_ops,
+                                               mvchip);
+        if (!mvchip->domain) {
+                dev_err(&pdev->dev, "couldn't allocate irq domain %s (DT).\n",
+                        mvchip->chip.label);
+                irq_remove_generic_chip(gc, IRQ_MSK(ngpios), IRQ_NOREQUEST,
+                                        IRQ_LEVEL | IRQ_NOPROBE);
+                kfree(gc);
+                kfree(mvchip->chip.label);
+                return -ENODEV;
+        }
+
+        return 0;
+}
+
+static struct platform_driver mvebu_gpio_driver = {
+        .driver         = {
+                .name           = "mvebu-gpio",
+                .owner          = THIS_MODULE,
+                .of_match_table = mvebu_gpio_of_match,
+        },
+        .probe          = mvebu_gpio_probe,
+        .id_table       = mvebu_gpio_ids,
+};
+
+static int __init mvebu_gpio_init(void)
+{
+        return platform_driver_register(&mvebu_gpio_driver);
+}
+postcore_initcall(mvebu_gpio_init);
diff --git a/drivers/hwmon/gpio-fan.c b/drivers/hwmon/gpio-fan.c
index 2f4b01bda87c..36509ae32083 100644
--- a/drivers/hwmon/gpio-fan.c
+++ b/drivers/hwmon/gpio-fan.c
@@ -31,6 +31,8 @@
 #include <linux/hwmon.h>
 #include <linux/gpio.h>
 #include <linux/gpio-fan.h>
+#include <linux/of_platform.h>
+#include <linux/of_gpio.h>
 
 struct gpio_fan_data {
         struct platform_device  *pdev;
@@ -400,14 +402,131 @@ static ssize_t show_name(struct device *dev,
 
 static DEVICE_ATTR(name, S_IRUGO, show_name, NULL);
 
+
+#ifdef CONFIG_OF_GPIO
+/*
+ * Translate OpenFirmware node properties into platform_data
+ */
+static int gpio_fan_get_of_pdata(struct device *dev,
+                            struct gpio_fan_platform_data *pdata)
+{
+        struct device_node *node;
+        struct gpio_fan_speed *speed;
+        unsigned *ctrl;
+        unsigned i;
+        u32 u;
+        struct property *prop;
+        const __be32 *p;
+
+        node = dev->of_node;
+
+        /* Fill GPIO pin array */
+        pdata->num_ctrl = of_gpio_count(node);
+        if (!pdata->num_ctrl) {
+                dev_err(dev, "gpios DT property empty / missing");
+                return -ENODEV;
+        }
+        ctrl = devm_kzalloc(dev, pdata->num_ctrl * sizeof(unsigned),
+                                GFP_KERNEL);
+        if (!ctrl)
+                return -ENOMEM;
+        for (i = 0; i < pdata->num_ctrl; i++) {
+                int val;
+
+                val = of_get_gpio(node, i);
+                if (val < 0)
+                        return val;
+                ctrl[i] = val;
+        }
+        pdata->ctrl = ctrl;
+
+        /* Get number of RPM/ctrl_val pairs in speed map */
+        prop = of_find_property(node, "gpio-fan,speed-map", &i);
+        if (!prop) {
+                dev_err(dev, "gpio-fan,speed-map DT property missing");
+                return -ENODEV;
+        }
+        i = i / sizeof(u32);
+        if (i == 0 || i & 1) {
+                dev_err(dev, "gpio-fan,speed-map contains zero/odd number of entries");
+                return -ENODEV;
+        }
+        pdata->num_speed = i / 2;
+
+        /*
+         * Populate speed map
+         * Speed map is in the form <RPM ctrl_val RPM ctrl_val ...>
+         * this needs splitting into pairs to create gpio_fan_speed structs
+         */
+        speed = devm_kzalloc(dev,
+                        pdata->num_speed * sizeof(struct gpio_fan_speed),
+                        GFP_KERNEL);
+        if (!speed)
+                return -ENOMEM;
+        p = NULL;
+        for (i = 0; i < pdata->num_speed; i++) {
+                p = of_prop_next_u32(prop, p, &u);
+                if (!p)
+                        return -ENODEV;
+                speed[i].rpm = u;
+                p = of_prop_next_u32(prop, p, &u);
+                if (!p)
+                        return -ENODEV;
+                speed[i].ctrl_val = u;
+        }
+        pdata->speed = speed;
+
+        /* Alarm GPIO if one exists */
+        if (of_gpio_named_count(node, "alarm-gpios")) {
+                struct gpio_fan_alarm *alarm;
+                int val;
+                enum of_gpio_flags flags;
+
+                alarm = devm_kzalloc(dev, sizeof(struct gpio_fan_alarm),
+                                        GFP_KERNEL);
+                if (!alarm)
+                        return -ENOMEM;
+
+                val = of_get_named_gpio_flags(node, "alarm-gpios", 0, &flags);
+                if (val < 0)
+                        return val;
+                alarm->gpio = val;
+                alarm->active_low = flags & OF_GPIO_ACTIVE_LOW;
+
+                pdata->alarm = alarm;
+        }
+
+        return 0;
+}
+
+static struct of_device_id of_gpio_fan_match[] __devinitdata = {
+        { .compatible = "gpio-fan", },
+        {},
+};
+#endif /* CONFIG_OF_GPIO */
+
 static int __devinit gpio_fan_probe(struct platform_device *pdev)
 {
         int err;
         struct gpio_fan_data *fan_data;
         struct gpio_fan_platform_data *pdata = pdev->dev.platform_data;
 
+#ifdef CONFIG_OF_GPIO
+        if (!pdata) {
+                pdata = devm_kzalloc(&pdev->dev,
+                                        sizeof(struct gpio_fan_platform_data),
+                                        GFP_KERNEL);
+                if (!pdata)
+                        return -ENOMEM;
+
+                err = gpio_fan_get_of_pdata(&pdev->dev, pdata);
+                if (err)
+                        return err;
+        }
+#else /* CONFIG_OF_GPIO */
         if (!pdata)
                 return -EINVAL;
+#endif /* CONFIG_OF_GPIO */
 
         fan_data = devm_kzalloc(&pdev->dev, sizeof(struct gpio_fan_data),
                                 GFP_KERNEL);
@@ -511,6 +630,7 @@ static struct platform_driver gpio_fan_driver = {
         .driver = {
                 .name   = "gpio-fan",
                 .pm     = GPIO_FAN_PM,
+                .of_match_table = of_match_ptr(of_gpio_fan_match),
         },
 };
 
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 1ef6e1e8c6c6..33e3df9e39ca 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -175,6 +175,28 @@ config PINCTRL_EXYNOS4
         bool "Pinctrl driver data for Exynos4 SoC"
         select PINCTRL_SAMSUNG
 
+config PINCTRL_MVEBU
+        bool
+        depends on ARCH_MVEBU
+        select PINMUX
+        select PINCONF
+
+config PINCTRL_DOVE
+        bool
+        select PINCTRL_MVEBU
+
+config PINCTRL_KIRKWOOD
+        bool
+        select PINCTRL_MVEBU
+
+config PINCTRL_ARMADA_370
+        bool
+        select PINCTRL_MVEBU
+
+config PINCTRL_ARMADA_XP
+        bool
+        select PINCTRL_MVEBU
+
 source "drivers/pinctrl/spear/Kconfig"
 
 endmenu
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 698527dce29d..f162e0196300 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -35,5 +35,10 @@ obj-$(CONFIG_PINCTRL_U300)	+= pinctrl-u300.o
 obj-$(CONFIG_PINCTRL_COH901)    += pinctrl-coh901.o
 obj-$(CONFIG_PINCTRL_SAMSUNG)   += pinctrl-samsung.o
 obj-$(CONFIG_PINCTRL_EXYNOS4)   += pinctrl-exynos.o
+obj-$(CONFIG_PINCTRL_MVEBU)     += pinctrl-mvebu.o
+obj-$(CONFIG_PINCTRL_DOVE)      += pinctrl-dove.o
+obj-$(CONFIG_PINCTRL_KIRKWOOD)  += pinctrl-kirkwood.o
+obj-$(CONFIG_PINCTRL_ARMADA_370) += pinctrl-armada-370.o
+obj-$(CONFIG_PINCTRL_ARMADA_XP)  += pinctrl-armada-xp.o
 
 obj-$(CONFIG_PLAT_SPEAR)        += spear/
diff --git a/drivers/pinctrl/pinctrl-armada-370.c b/drivers/pinctrl/pinctrl-armada-370.c
new file mode 100644
index 000000000000..c907647de6ad
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-370.c
@@ -0,0 +1,421 @@
+/*
+ * Marvell Armada 370 pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+static struct mvebu_mpp_mode mv88f6710_mpp_modes[] = {
+        MPP_MODE(0,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "uart0", "rxd")),
+        MPP_MODE(1,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "uart0", "txd")),
+        MPP_MODE(2,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "i2c0", "sck"),
+           MPP_FUNCTION(0x2, "uart0", "txd")),
+        MPP_MODE(3,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "i2c0", "sda"),
+           MPP_FUNCTION(0x2, "uart0", "rxd")),
+        MPP_MODE(4,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "cpu_pd", "vdd")),
+        MPP_MODE(5,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txclko"),
+           MPP_FUNCTION(0x2, "uart1", "txd"),
+           MPP_FUNCTION(0x4, "spi1", "clk"),
+           MPP_FUNCTION(0x5, "audio", "mclk")),
+        MPP_MODE(6,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd0"),
+           MPP_FUNCTION(0x2, "sata0", "prsnt"),
+           MPP_FUNCTION(0x4, "tdm", "rst"),
+           MPP_FUNCTION(0x5, "audio", "sdo")),
+        MPP_MODE(7,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd1"),
+           MPP_FUNCTION(0x4, "tdm", "tdx"),
+           MPP_FUNCTION(0x5, "audio", "lrclk")),
+        MPP_MODE(8,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd2"),
+           MPP_FUNCTION(0x2, "uart0", "rts"),
+           MPP_FUNCTION(0x4, "tdm", "drx"),
+           MPP_FUNCTION(0x5, "audio", "bclk")),
+        MPP_MODE(9,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd3"),
+           MPP_FUNCTION(0x2, "uart1", "txd"),
+           MPP_FUNCTION(0x3, "sd0", "clk"),
+           MPP_FUNCTION(0x5, "audio", "spdifo")),
+        MPP_MODE(10,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txctl"),
+           MPP_FUNCTION(0x2, "uart0", "cts"),
+           MPP_FUNCTION(0x4, "tdm", "fsync"),
+           MPP_FUNCTION(0x5, "audio", "sdi")),
+        MPP_MODE(11,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd0"),
+           MPP_FUNCTION(0x2, "uart1", "rxd"),
+           MPP_FUNCTION(0x3, "sd0", "cmd"),
+           MPP_FUNCTION(0x4, "spi0", "cs1"),
+           MPP_FUNCTION(0x5, "sata1", "prsnt"),
+           MPP_FUNCTION(0x6, "spi1", "cs1")),
+        MPP_MODE(12,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd1"),
+           MPP_FUNCTION(0x2, "i2c1", "sda"),
+           MPP_FUNCTION(0x3, "sd0", "d0"),
+           MPP_FUNCTION(0x4, "spi1", "cs0"),
+           MPP_FUNCTION(0x5, "audio", "spdifi")),
+        MPP_MODE(13,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd2"),
+           MPP_FUNCTION(0x2, "i2c1", "sck"),
+           MPP_FUNCTION(0x3, "sd0", "d1"),
+           MPP_FUNCTION(0x4, "tdm", "pclk"),
+           MPP_FUNCTION(0x5, "audio", "rmclk")),
+        MPP_MODE(14,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd3"),
+           MPP_FUNCTION(0x2, "pcie", "clkreq0"),
+           MPP_FUNCTION(0x3, "sd0", "d2"),
+           MPP_FUNCTION(0x4, "spi1", "mosi"),
+           MPP_FUNCTION(0x5, "spi0", "cs2")),
+        MPP_MODE(15,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxctl"),
+           MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+           MPP_FUNCTION(0x3, "sd0", "d3"),
+           MPP_FUNCTION(0x4, "spi1", "miso"),
+           MPP_FUNCTION(0x5, "spi0", "cs3")),
+        MPP_MODE(16,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxclk"),
+           MPP_FUNCTION(0x2, "uart1", "rxd"),
+           MPP_FUNCTION(0x4, "tdm", "int"),
+           MPP_FUNCTION(0x5, "audio", "extclk")),
+        MPP_MODE(17,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge", "mdc")),
+        MPP_MODE(18,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge", "mdio")),
+        MPP_MODE(19,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txclk"),
+           MPP_FUNCTION(0x2, "ge1", "txclkout"),
+           MPP_FUNCTION(0x4, "tdm", "pclk")),
+        MPP_MODE(20,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd4"),
+           MPP_FUNCTION(0x2, "ge1", "txd0")),
+        MPP_MODE(21,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd5"),
+           MPP_FUNCTION(0x2, "ge1", "txd1"),
+           MPP_FUNCTION(0x4, "uart1", "txd")),
+        MPP_MODE(22,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd6"),
+           MPP_FUNCTION(0x2, "ge1", "txd2"),
+           MPP_FUNCTION(0x4, "uart0", "rts")),
+        MPP_MODE(23,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "ge0", "txd7"),
+           MPP_FUNCTION(0x2, "ge1", "txd3"),
+           MPP_FUNCTION(0x4, "spi1", "mosi")),
+        MPP_MODE(24,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "col"),
+           MPP_FUNCTION(0x2, "ge1", "txctl"),
+           MPP_FUNCTION(0x4, "spi1", "cs0")),
+        MPP_MODE(25,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxerr"),
+           MPP_FUNCTION(0x2, "ge1", "rxd0"),
+           MPP_FUNCTION(0x4, "uart1", "rxd")),
+        MPP_MODE(26,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "crs"),
+           MPP_FUNCTION(0x2, "ge1", "rxd1"),
+           MPP_FUNCTION(0x4, "spi1", "miso")),
+        MPP_MODE(27,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd4"),
+           MPP_FUNCTION(0x2, "ge1", "rxd2"),
+           MPP_FUNCTION(0x4, "uart0", "cts")),
+        MPP_MODE(28,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd5"),
+           MPP_FUNCTION(0x2, "ge1", "rxd3")),
+        MPP_MODE(29,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd6"),
+           MPP_FUNCTION(0x2, "ge1", "rxctl"),
+           MPP_FUNCTION(0x4, "i2c1", "sda")),
+        MPP_MODE(30,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "ge0", "rxd7"),
+           MPP_FUNCTION(0x2, "ge1", "rxclk"),
+           MPP_FUNCTION(0x4, "i2c1", "sck")),
+        MPP_MODE(31,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x3, "tclk", NULL),
+           MPP_FUNCTION(0x4, "ge0", "txerr")),
+        MPP_MODE(32,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "spi0", "cs0")),
+        MPP_MODE(33,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "bootcs"),
+           MPP_FUNCTION(0x2, "spi0", "cs0")),
+        MPP_MODE(34,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "wen0"),
+           MPP_FUNCTION(0x2, "spi0", "mosi")),
+        MPP_MODE(35,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "oen"),
+           MPP_FUNCTION(0x2, "spi0", "sck")),
+        MPP_MODE(36,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "a1"),
+           MPP_FUNCTION(0x2, "spi0", "miso")),
+        MPP_MODE(37,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "a0"),
+           MPP_FUNCTION(0x2, "sata0", "prsnt")),
+        MPP_MODE(38,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ready"),
+           MPP_FUNCTION(0x2, "uart1", "cts"),
+           MPP_FUNCTION(0x3, "uart0", "cts")),
+        MPP_MODE(39,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad0"),
+           MPP_FUNCTION(0x2, "audio", "spdifo")),
+        MPP_MODE(40,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad1"),
+           MPP_FUNCTION(0x2, "uart1", "rts"),
+           MPP_FUNCTION(0x3, "uart0", "rts")),
+        MPP_MODE(41,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad2"),
+           MPP_FUNCTION(0x2, "uart1", "rxd")),
+        MPP_MODE(42,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad3"),
+           MPP_FUNCTION(0x2, "uart1", "txd")),
+        MPP_MODE(43,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad4"),
+           MPP_FUNCTION(0x2, "audio", "bclk")),
+        MPP_MODE(44,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad5"),
+           MPP_FUNCTION(0x2, "audio", "mclk")),
+        MPP_MODE(45,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad6"),
+           MPP_FUNCTION(0x2, "audio", "lrclk")),
+        MPP_MODE(46,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad7"),
+           MPP_FUNCTION(0x2, "audio", "sdo")),
+        MPP_MODE(47,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad8"),
+           MPP_FUNCTION(0x3, "sd0", "clk"),
+           MPP_FUNCTION(0x5, "audio", "spdifo")),
+        MPP_MODE(48,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad9"),
+           MPP_FUNCTION(0x2, "uart0", "rts"),
+           MPP_FUNCTION(0x3, "sd0", "cmd"),
+           MPP_FUNCTION(0x4, "sata1", "prsnt"),
+           MPP_FUNCTION(0x5, "spi0", "cs1")),
+        MPP_MODE(49,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad10"),
+           MPP_FUNCTION(0x2, "pcie", "clkreq1"),
+           MPP_FUNCTION(0x3, "sd0", "d0"),
+           MPP_FUNCTION(0x4, "spi1", "cs0"),
+           MPP_FUNCTION(0x5, "audio", "spdifi")),
+        MPP_MODE(50,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad11"),
+           MPP_FUNCTION(0x2, "uart0", "cts"),
+           MPP_FUNCTION(0x3, "sd0", "d1"),
+           MPP_FUNCTION(0x4, "spi1", "miso"),
+           MPP_FUNCTION(0x5, "audio", "rmclk")),
+        MPP_MODE(51,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad12"),
+           MPP_FUNCTION(0x2, "i2c1", "sda"),
+           MPP_FUNCTION(0x3, "sd0", "d2"),
+           MPP_FUNCTION(0x4, "spi1", "mosi")),
+        MPP_MODE(52,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad13"),
+           MPP_FUNCTION(0x2, "i2c1", "sck"),
+           MPP_FUNCTION(0x3, "sd0", "d3"),
+           MPP_FUNCTION(0x4, "spi1", "sck")),
+        MPP_MODE(53,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad14"),
+           MPP_FUNCTION(0x2, "sd0", "clk"),
+           MPP_FUNCTION(0x3, "tdm", "pclk"),
+           MPP_FUNCTION(0x4, "spi0", "cs2"),
+           MPP_FUNCTION(0x5, "pcie", "clkreq1")),
+        MPP_MODE(54,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ad15"),
+           MPP_FUNCTION(0x3, "tdm", "dtx")),
+        MPP_MODE(55,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "cs1"),
+           MPP_FUNCTION(0x2, "uart1", "txd"),
+           MPP_FUNCTION(0x3, "tdm", "rst"),
+           MPP_FUNCTION(0x4, "sata1", "prsnt"),
+           MPP_FUNCTION(0x5, "sata0", "prsnt")),
+        MPP_MODE(56,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "cs2"),
+           MPP_FUNCTION(0x2, "uart1", "cts"),
+           MPP_FUNCTION(0x3, "uart0", "cts"),
+           MPP_FUNCTION(0x4, "spi0", "cs3"),
+           MPP_FUNCTION(0x5, "pcie", "clkreq0"),
+           MPP_FUNCTION(0x6, "spi1", "cs1")),
+        MPP_MODE(57,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "cs3"),
+           MPP_FUNCTION(0x2, "uart1", "rxd"),
+           MPP_FUNCTION(0x3, "tdm", "fsync"),
+           MPP_FUNCTION(0x4, "sata0", "prsnt"),
+           MPP_FUNCTION(0x5, "audio", "sdo")),
+        MPP_MODE(58,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "cs0"),
+           MPP_FUNCTION(0x2, "uart1", "rts"),
+           MPP_FUNCTION(0x3, "tdm", "int"),
+           MPP_FUNCTION(0x5, "audio", "extclk"),
+           MPP_FUNCTION(0x6, "uart0", "rts")),
+        MPP_MODE(59,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "ale0"),
+           MPP_FUNCTION(0x2, "uart1", "rts"),
+           MPP_FUNCTION(0x3, "uart0", "rts"),
+           MPP_FUNCTION(0x5, "audio", "bclk")),
+        MPP_MODE(60,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "ale1"),
+           MPP_FUNCTION(0x2, "uart1", "rxd"),
+           MPP_FUNCTION(0x3, "sata0", "prsnt"),
+           MPP_FUNCTION(0x4, "pcie", "rst-out"),
+           MPP_FUNCTION(0x5, "audio", "sdi")),
+        MPP_MODE(61,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "dev", "wen1"),
+           MPP_FUNCTION(0x2, "uart1", "txd"),
+           MPP_FUNCTION(0x5, "audio", "rclk")),
+        MPP_MODE(62,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "dev", "a2"),
+           MPP_FUNCTION(0x2, "uart1", "cts"),
+           MPP_FUNCTION(0x3, "tdm", "drx"),
+           MPP_FUNCTION(0x4, "pcie", "clkreq0"),
+           MPP_FUNCTION(0x5, "audio", "mclk"),
+           MPP_FUNCTION(0x6, "uart0", "cts")),
+        MPP_MODE(63,
+           MPP_FUNCTION(0x0, "gpo", NULL),
+           MPP_FUNCTION(0x1, "spi0", "sck"),
+           MPP_FUNCTION(0x2, "tclk", NULL)),
+        MPP_MODE(64,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "spi0", "miso"),
+           MPP_FUNCTION(0x2, "spi0-1", "cs1")),
+        MPP_MODE(65,
+           MPP_FUNCTION(0x0, "gpio", NULL),
+           MPP_FUNCTION(0x1, "spi0", "mosi"),
+           MPP_FUNCTION(0x2, "spi0-1", "cs2")),
+};
+
+static struct mvebu_pinctrl_soc_info armada_370_pinctrl_info;
+
+static struct of_device_id armada_370_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "marvell,mv88f6710-pinctrl" },
+        { },
+};
+
+static struct mvebu_mpp_ctrl mv88f6710_mpp_controls[] = {
+        MPP_REG_CTRL(0, 65),
+};
+
+static struct pinctrl_gpio_range mv88f6710_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,   0,  0, 32),
+        MPP_GPIO_RANGE(1,  32, 32, 32),
+        MPP_GPIO_RANGE(2,  64, 64,  2),
+};
+
+static int __devinit armada_370_pinctrl_probe(struct platform_device *pdev)
+{
+        struct mvebu_pinctrl_soc_info *soc = &armada_370_pinctrl_info;
+
+        soc->variant = 0; /* no variants for Armada 370 */
+        soc->controls = mv88f6710_mpp_controls;
+        soc->ncontrols = ARRAY_SIZE(mv88f6710_mpp_controls);
+        soc->modes = mv88f6710_mpp_modes;
+        soc->nmodes = ARRAY_SIZE(mv88f6710_mpp_modes);
+        soc->gpioranges = mv88f6710_mpp_gpio_ranges;
+        soc->ngpioranges = ARRAY_SIZE(mv88f6710_mpp_gpio_ranges);
+
+        pdev->dev.platform_data = soc;
+
+        return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_370_pinctrl_remove(struct platform_device *pdev)
+{
+        return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_370_pinctrl_driver = {
+        .driver = {
+                .name = "armada-370-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(armada_370_pinctrl_of_match),
+        },
+        .probe = armada_370_pinctrl_probe,
+        .remove = __devexit_p(armada_370_pinctrl_remove),
+};
+
+module_platform_driver(armada_370_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada 370 pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-armada-xp.c b/drivers/pinctrl/pinctrl-armada-xp.c
new file mode 100644
index 000000000000..40bd52a46b4e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-armada-xp.c
@@ -0,0 +1,468 @@
+/*
+ * Marvell Armada XP pinctrl driver based on mvebu pinctrl core
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file supports the three variants of Armada XP SoCs that are
+ * available: mv78230, mv78260 and mv78460. From a pin muxing
+ * perspective, the mv78230 has 49 MPP pins. The mv78260 and mv78460
+ * both have 67 MPP pins (more GPIOs and address lines for the memory
+ * bus mainly). The only difference between the mv78260 and the
+ * mv78460 in terms of pin muxing is the addition of two functions on
+ * pins 43 and 56 to access the VDD of the CPU2 and 3 (mv78260 has two
+ * cores, mv78460 has four cores).
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/bitops.h>
+
+#include "pinctrl-mvebu.h"
+
+enum armada_xp_variant {
+        V_MV78230       = BIT(0),
+        V_MV78260       = BIT(1),
+        V_MV78460       = BIT(2),
+        V_MV78230_PLUS  = (V_MV78230 | V_MV78260 | V_MV78460),
+        V_MV78260_PLUS  = (V_MV78260 | V_MV78460),
+};
+
+static struct mvebu_mpp_mode armada_xp_mpp_modes[] = {
+        MPP_MODE(0,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txclko",     V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d0",         V_MV78230_PLUS)),
+        MPP_MODE(1,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d1",         V_MV78230_PLUS)),
+        MPP_MODE(2,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd1",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d2",         V_MV78230_PLUS)),
+        MPP_MODE(3,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d3",         V_MV78230_PLUS)),
+        MPP_MODE(4,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d4",         V_MV78230_PLUS)),
+        MPP_MODE(5,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txctl",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d5",         V_MV78230_PLUS)),
+        MPP_MODE(6,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d6",         V_MV78230_PLUS)),
+        MPP_MODE(7,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd1",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d7",         V_MV78230_PLUS)),
+        MPP_MODE(8,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d8",         V_MV78230_PLUS)),
+        MPP_MODE(9,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d9",         V_MV78230_PLUS)),
+        MPP_MODE(10,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxctl",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d10",        V_MV78230_PLUS)),
+        MPP_MODE(11,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxclk",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d11",        V_MV78230_PLUS)),
+        MPP_MODE(12,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd4",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "clkout",     V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d12",        V_MV78230_PLUS)),
+        MPP_MODE(13,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd5",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txd0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d13",        V_MV78230_PLUS)),
+        MPP_MODE(14,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd6",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txd1",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d14",        V_MV78230_PLUS)),
+        MPP_MODE(15,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txd7",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txd2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d15",        V_MV78230_PLUS)),
+        MPP_MODE(16,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "txclk",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txd3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d16",        V_MV78230_PLUS)),
+        MPP_MODE(17,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "col",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "txctl",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d17",        V_MV78230_PLUS)),
+        MPP_MODE(18,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxerr",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxd0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "ptp", "trig",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d18",        V_MV78230_PLUS)),
+        MPP_MODE(19,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "crs",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxd1",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "ptp", "evreq",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d19",        V_MV78230_PLUS)),
+        MPP_MODE(20,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd4",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxd2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "ptp", "clk",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d20",        V_MV78230_PLUS)),
+        MPP_MODE(21,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd5",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxd3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "mem", "bat",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d21",        V_MV78230_PLUS)),
+        MPP_MODE(22,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd6",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxctl",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "sata0", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d22",        V_MV78230_PLUS)),
+        MPP_MODE(23,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ge0", "rxd7",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "ge1", "rxclk",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "d23",        V_MV78230_PLUS)),
+        MPP_MODE(24,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sata1", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-re",   V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "rst",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "hsync",      V_MV78230_PLUS)),
+        MPP_MODE(25,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sata0", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "nf", "bootcs-we",   V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "pclk",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "vsync",      V_MV78230_PLUS)),
+        MPP_MODE(26,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "fsync",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "clk",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+        MPP_MODE(27,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ptp", "trig",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "dtx",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "e",          V_MV78230_PLUS)),
+        MPP_MODE(28,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ptp", "evreq",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "drx",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "pwm",        V_MV78230_PLUS)),
+        MPP_MODE(29,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "ptp", "clk",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int0",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "ref-clk",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+        MPP_MODE(30,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "clk",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int1",       V_MV78230_PLUS)),
+        MPP_MODE(31,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "cmd",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int2",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+        MPP_MODE(32,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "d0",         V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int3",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu1-pd",    V_MV78230_PLUS)),
+        MPP_MODE(33,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "d1",         V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int4",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "mem", "bat",        V_MV78230_PLUS)),
+        MPP_MODE(34,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "d2",         V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "sata0", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int5",       V_MV78230_PLUS)),
+        MPP_MODE(35,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "sd0", "d3",         V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "sata1", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int6",       V_MV78230_PLUS)),
+        MPP_MODE(36,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "mosi",       V_MV78230_PLUS)),
+        MPP_MODE(37,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "miso",       V_MV78230_PLUS)),
+        MPP_MODE(38,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "sck",        V_MV78230_PLUS)),
+        MPP_MODE(39,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "cs0",        V_MV78230_PLUS)),
+        MPP_MODE(40,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "cs1",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart2", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "vdd", "cpu1-pd",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "vga-hsync",  V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq0",   V_MV78230_PLUS)),
+        MPP_MODE(41,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "spi", "cs2",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart2", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "sata1", "prsnt",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "lcd", "vga-vsync",  V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq1",   V_MV78230_PLUS)),
+        MPP_MODE(42,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart2", "rxd",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart0", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "tdm", "int7",       V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "tdm-1", "timer",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu0-pd",    V_MV78230_PLUS)),
+        MPP_MODE(43,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart2", "txd",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart0", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs3",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "pcie", "rstout",    V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "vdd", "cpu2-3-pd",  V_MV78460)),
+        MPP_MODE(44,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart2", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart3", "rxd",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs4",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "mem", "bat",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq2",   V_MV78230_PLUS)),
+        MPP_MODE(45,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart2", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart3", "txd",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs5",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",    V_MV78230_PLUS)),
+        MPP_MODE(46,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart3", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart1", "rts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs6",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",    V_MV78230_PLUS)),
+        MPP_MODE(47,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "uart3", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "uart1", "cts",      V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x3, "spi", "cs7",        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x4, "ref", "clkout",     V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x5, "pcie", "clkreq3",   V_MV78230_PLUS)),
+        MPP_MODE(48,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "tclk", NULL,        V_MV78230_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "dev", "burst/last", V_MV78230_PLUS)),
+        MPP_MODE(49,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "we3",        V_MV78260_PLUS)),
+        MPP_MODE(50,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "we2",        V_MV78260_PLUS)),
+        MPP_MODE(51,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad16",       V_MV78260_PLUS)),
+        MPP_MODE(52,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad17",       V_MV78260_PLUS)),
+        MPP_MODE(53,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad18",       V_MV78260_PLUS)),
+        MPP_MODE(54,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad19",       V_MV78260_PLUS)),
+        MPP_MODE(55,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad20",       V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "vdd", "cpu0-pd",    V_MV78260_PLUS)),
+        MPP_MODE(56,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad21",       V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "vdd", "cpu1-pd",    V_MV78260_PLUS)),
+        MPP_MODE(57,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad22",       V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x2, "vdd", "cpu2-3-pd",  V_MV78460)),
+        MPP_MODE(58,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad23",       V_MV78260_PLUS)),
+        MPP_MODE(59,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad24",       V_MV78260_PLUS)),
+        MPP_MODE(60,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad25",       V_MV78260_PLUS)),
+        MPP_MODE(61,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad26",       V_MV78260_PLUS)),
+        MPP_MODE(62,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad27",       V_MV78260_PLUS)),
+        MPP_MODE(63,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad28",       V_MV78260_PLUS)),
+        MPP_MODE(64,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad29",       V_MV78260_PLUS)),
+        MPP_MODE(65,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad30",       V_MV78260_PLUS)),
+        MPP_MODE(66,
+                 MPP_VAR_FUNCTION(0x0, "gpio", NULL,        V_MV78260_PLUS),
+                 MPP_VAR_FUNCTION(0x1, "dev", "ad31",       V_MV78260_PLUS)),
+};
+
+static struct mvebu_pinctrl_soc_info armada_xp_pinctrl_info;
+
+static struct of_device_id armada_xp_pinctrl_of_match[] __devinitdata = {
+        {
+                .compatible = "marvell,mv78230-pinctrl",
+                .data       = (void *) V_MV78230,
+        },
+        {
+                .compatible = "marvell,mv78260-pinctrl",
+                .data       = (void *) V_MV78260,
+        },
+        {
+                .compatible = "marvell,mv78460-pinctrl",
+                .data       = (void *) V_MV78460,
+        },
+        { },
+};
+
+static struct mvebu_mpp_ctrl mv78230_mpp_controls[] = {
+        MPP_REG_CTRL(0, 48),
+};
+
+static struct pinctrl_gpio_range mv78230_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,   0,  0, 32),
+        MPP_GPIO_RANGE(1,  32, 32, 17),
+};
+
+static struct mvebu_mpp_ctrl mv78260_mpp_controls[] = {
+        MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78260_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,   0,  0, 32),
+        MPP_GPIO_RANGE(1,  32, 32, 32),
+        MPP_GPIO_RANGE(2,  64, 64,  3),
+};
+
+static struct mvebu_mpp_ctrl mv78460_mpp_controls[] = {
+        MPP_REG_CTRL(0, 66),
+};
+
+static struct pinctrl_gpio_range mv78460_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,   0,  0, 32),
+        MPP_GPIO_RANGE(1,  32, 32, 32),
+        MPP_GPIO_RANGE(2,  64, 64,  3),
+};
+
+static int __devinit armada_xp_pinctrl_probe(struct platform_device *pdev)
+{
+        struct mvebu_pinctrl_soc_info *soc = &armada_xp_pinctrl_info;
+        const struct of_device_id *match =
+                of_match_device(armada_xp_pinctrl_of_match, &pdev->dev);
+
+        if (!match)
+                return -ENODEV;
+
+        soc->variant = (unsigned) match->data & 0xff;
+
+        switch (soc->variant) {
+        case V_MV78230:
+                soc->controls = mv78230_mpp_controls;
+                soc->ncontrols = ARRAY_SIZE(mv78230_mpp_controls);
+                soc->modes = armada_xp_mpp_modes;
+                /* We don't necessarily want the full list of the
+                 * armada_xp_mpp_modes, but only the first 'n' ones
+                 * that are available on this SoC */
+                soc->nmodes = mv78230_mpp_controls[0].npins;
+                soc->gpioranges = mv78230_mpp_gpio_ranges;
+                soc->ngpioranges = ARRAY_SIZE(mv78230_mpp_gpio_ranges);
+                break;
+        case V_MV78260:
+                soc->controls = mv78260_mpp_controls;
+                soc->ncontrols = ARRAY_SIZE(mv78260_mpp_controls);
+                soc->modes = armada_xp_mpp_modes;
+                /* We don't necessarily want the full list of the
+                 * armada_xp_mpp_modes, but only the first 'n' ones
+                 * that are available on this SoC */
+                soc->nmodes = mv78260_mpp_controls[0].npins;
+                soc->gpioranges = mv78260_mpp_gpio_ranges;
+                soc->ngpioranges = ARRAY_SIZE(mv78260_mpp_gpio_ranges);
+                break;
+        case V_MV78460:
+                soc->controls = mv78460_mpp_controls;
+                soc->ncontrols = ARRAY_SIZE(mv78460_mpp_controls);
+                soc->modes = armada_xp_mpp_modes;
+                /* We don't necessarily want the full list of the
+                 * armada_xp_mpp_modes, but only the first 'n' ones
+                 * that are available on this SoC */
+                soc->nmodes = mv78460_mpp_controls[0].npins;
+                soc->gpioranges = mv78460_mpp_gpio_ranges;
+                soc->ngpioranges = ARRAY_SIZE(mv78460_mpp_gpio_ranges);
+                break;
+        }
+
+        pdev->dev.platform_data = soc;
+
+        return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit armada_xp_pinctrl_remove(struct platform_device *pdev)
+{
+        return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver armada_xp_pinctrl_driver = {
+        .driver = {
+                .name = "armada-xp-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(armada_xp_pinctrl_of_match),
+        },
+        .probe = armada_xp_pinctrl_probe,
+        .remove = __devexit_p(armada_xp_pinctrl_remove),
+};
+
+module_platform_driver(armada_xp_pinctrl_driver);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
+MODULE_DESCRIPTION("Marvell Armada XP pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-dove.c b/drivers/pinctrl/pinctrl-dove.c
new file mode 100644
index 000000000000..ffe74b27d66d
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-dove.c
@@ -0,0 +1,620 @@
+/*
+ * Marvell Dove pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/bitops.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define DOVE_SB_REGS_VIRT_BASE          0xfde00000
+#define DOVE_MPP_VIRT_BASE              (DOVE_SB_REGS_VIRT_BASE | 0xd0200)
+#define DOVE_PMU_MPP_GENERAL_CTRL       (DOVE_MPP_VIRT_BASE + 0x10)
+#define  DOVE_AU0_AC97_SEL              BIT(16)
+#define DOVE_GLOBAL_CONFIG_1            (DOVE_SB_REGS_VIRT_BASE | 0xe802C)
+#define  DOVE_TWSI_ENABLE_OPTION1       BIT(7)
+#define DOVE_GLOBAL_CONFIG_2            (DOVE_SB_REGS_VIRT_BASE | 0xe8030)
+#define  DOVE_TWSI_ENABLE_OPTION2       BIT(20)
+#define  DOVE_TWSI_ENABLE_OPTION3       BIT(21)
+#define  DOVE_TWSI_OPTION3_GPIO         BIT(22)
+#define DOVE_SSP_CTRL_STATUS_1          (DOVE_SB_REGS_VIRT_BASE | 0xe8034)
+#define  DOVE_SSP_ON_AU1                BIT(0)
+#define DOVE_MPP_GENERAL_VIRT_BASE      (DOVE_SB_REGS_VIRT_BASE | 0xe803c)
+#define  DOVE_AU1_SPDIFO_GPIO_EN        BIT(1)
+#define  DOVE_NAND_GPIO_EN              BIT(0)
+#define DOVE_GPIO_LO_VIRT_BASE          (DOVE_SB_REGS_VIRT_BASE | 0xd0400)
+#define DOVE_MPP_CTRL4_VIRT_BASE        (DOVE_GPIO_LO_VIRT_BASE + 0x40)
+#define  DOVE_SPI_GPIO_SEL              BIT(5)
+#define  DOVE_UART1_GPIO_SEL            BIT(4)
+#define  DOVE_AU1_GPIO_SEL              BIT(3)
+#define  DOVE_CAM_GPIO_SEL              BIT(2)
+#define  DOVE_SD1_GPIO_SEL              BIT(1)
+#define  DOVE_SD0_GPIO_SEL              BIT(0)
+
+#define MPPS_PER_REG    8
+#define MPP_BITS        4
+#define MPP_MASK        0xf
+
+#define CONFIG_PMU      BIT(4)
+
+static int dove_pmu_mpp_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                                 unsigned long *config)
+{
+        unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
+        unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
+        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+        if (pmu & (1 << ctrl->pid))
+                *config = CONFIG_PMU;
+        else
+                *config = (mpp >> shift) & MPP_MASK;
+        return 0;
+}
+
+static int dove_pmu_mpp_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                                 unsigned long config)
+{
+        unsigned off = (ctrl->pid / MPPS_PER_REG) * MPP_BITS;
+        unsigned shift = (ctrl->pid % MPPS_PER_REG) * MPP_BITS;
+        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+        unsigned long mpp = readl(DOVE_MPP_VIRT_BASE + off);
+
+        if (config == CONFIG_PMU)
+                writel(pmu | (1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+        else {
+                writel(pmu & ~(1 << ctrl->pid), DOVE_PMU_MPP_GENERAL_CTRL);
+                mpp &= ~(MPP_MASK << shift);
+                mpp |= config << shift;
+                writel(mpp, DOVE_MPP_VIRT_BASE + off);
+        }
+        return 0;
+}
+
+static int dove_mpp4_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long *config)
+{
+        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long mask;
+
+        switch (ctrl->pid) {
+        case 24: /* mpp_camera */
+                mask = DOVE_CAM_GPIO_SEL;
+                break;
+        case 40: /* mpp_sdio0 */
+                mask = DOVE_SD0_GPIO_SEL;
+                break;
+        case 46: /* mpp_sdio1 */
+                mask = DOVE_SD1_GPIO_SEL;
+                break;
+        case 58: /* mpp_spi0 */
+                mask = DOVE_SPI_GPIO_SEL;
+                break;
+        case 62: /* mpp_uart1 */
+                mask = DOVE_UART1_GPIO_SEL;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        *config = ((mpp4 & mask) != 0);
+
+        return 0;
+}
+
+static int dove_mpp4_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long config)
+{
+        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long mask;
+
+        switch (ctrl->pid) {
+        case 24: /* mpp_camera */
+                mask = DOVE_CAM_GPIO_SEL;
+                break;
+        case 40: /* mpp_sdio0 */
+                mask = DOVE_SD0_GPIO_SEL;
+                break;
+        case 46: /* mpp_sdio1 */
+                mask = DOVE_SD1_GPIO_SEL;
+                break;
+        case 58: /* mpp_spi0 */
+                mask = DOVE_SPI_GPIO_SEL;
+                break;
+        case 62: /* mpp_uart1 */
+                mask = DOVE_UART1_GPIO_SEL;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        mpp4 &= ~mask;
+        if (config)
+                mpp4 |= mask;
+
+        writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+
+        return 0;
+}
+
+static int dove_nand_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long *config)
+{
+        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+        *config = ((gmpp & DOVE_NAND_GPIO_EN) != 0);
+
+        return 0;
+}
+
+static int dove_nand_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long config)
+{
+        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+
+        gmpp &= ~DOVE_NAND_GPIO_EN;
+        if (config)
+                gmpp |= DOVE_NAND_GPIO_EN;
+
+        writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+
+        return 0;
+}
+
+static int dove_audio0_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long *config)
+{
+        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+        *config = ((pmu & DOVE_AU0_AC97_SEL) != 0);
+
+        return 0;
+}
+
+static int dove_audio0_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long config)
+{
+        unsigned long pmu = readl(DOVE_PMU_MPP_GENERAL_CTRL);
+
+        pmu &= ~DOVE_AU0_AC97_SEL;
+        if (config)
+                pmu |= DOVE_AU0_AC97_SEL;
+        writel(pmu, DOVE_PMU_MPP_GENERAL_CTRL);
+
+        return 0;
+}
+
+static int dove_audio1_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long *config)
+{
+        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        *config = 0;
+        if (mpp4 & DOVE_AU1_GPIO_SEL)
+                *config |= BIT(3);
+        if (sspc1 & DOVE_SSP_ON_AU1)
+                *config |= BIT(2);
+        if (gmpp & DOVE_AU1_SPDIFO_GPIO_EN)
+                *config |= BIT(1);
+        if (gcfg2 & DOVE_TWSI_OPTION3_GPIO)
+                *config |= BIT(0);
+
+        /* SSP/TWSI only if I2S1 not set*/
+        if ((*config & BIT(3)) == 0)
+                *config &= ~(BIT(2) | BIT(0));
+        /* TWSI only if SPDIFO not set*/
+        if ((*config & BIT(1)) == 0)
+                *config &= ~BIT(0);
+        return 0;
+}
+
+static int dove_audio1_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long config)
+{
+        unsigned long mpp4 = readl(DOVE_MPP_CTRL4_VIRT_BASE);
+        unsigned long sspc1 = readl(DOVE_SSP_CTRL_STATUS_1);
+        unsigned long gmpp = readl(DOVE_MPP_GENERAL_VIRT_BASE);
+        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        if (config & BIT(0))
+                gcfg2 |= DOVE_TWSI_OPTION3_GPIO;
+        if (config & BIT(1))
+                gmpp |= DOVE_AU1_SPDIFO_GPIO_EN;
+        if (config & BIT(2))
+                sspc1 |= DOVE_SSP_ON_AU1;
+        if (config & BIT(3))
+                mpp4 |= DOVE_AU1_GPIO_SEL;
+
+        writel(mpp4, DOVE_MPP_CTRL4_VIRT_BASE);
+        writel(sspc1, DOVE_SSP_CTRL_STATUS_1);
+        writel(gmpp, DOVE_MPP_GENERAL_VIRT_BASE);
+        writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+        return 0;
+}
+
+/* mpp[52:57] gpio pins depend heavily on current config;
+ * gpio_req does not try to mux in gpio capabilities to not
+ * break other functions. If you require all mpps as gpio
+ * enforce gpio setting by pinctrl mapping.
+ */
+static int dove_audio1_ctrl_gpio_req(struct mvebu_mpp_ctrl *ctrl, u8 pid)
+{
+        unsigned long config;
+
+        dove_audio1_ctrl_get(ctrl, &config);
+
+        switch (config) {
+        case 0x02: /* i2s1 : gpio[56:57] */
+        case 0x0e: /* ssp  : gpio[56:57] */
+                if (pid >= 56)
+                        return 0;
+                return -ENOTSUPP;
+        case 0x08: /* spdifo : gpio[52:55] */
+        case 0x0b: /* twsi   : gpio[52:55] */
+                if (pid <= 55)
+                        return 0;
+                return -ENOTSUPP;
+        case 0x0a: /* all gpio */
+                return 0;
+        /* 0x00 : i2s1/spdifo : no gpio */
+        /* 0x0c : ssp/spdifo  : no gpio */
+        /* 0x0f : ssp/twsi    : no gpio */
+        }
+        return -ENOTSUPP;
+}
+
+/* mpp[52:57] has gpio pins capable of in and out */
+static int dove_audio1_ctrl_gpio_dir(struct mvebu_mpp_ctrl *ctrl, u8 pid,
+                                bool input)
+{
+        if (pid < 52 || pid > 57)
+                return -ENOTSUPP;
+        return 0;
+}
+
+static int dove_twsi_ctrl_get(struct mvebu_mpp_ctrl *ctrl,
+                              unsigned long *config)
+{
+        unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        *config = 0;
+        if (gcfg1 & DOVE_TWSI_ENABLE_OPTION1)
+                *config = 1;
+        else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION2)
+                *config = 2;
+        else if (gcfg2 & DOVE_TWSI_ENABLE_OPTION3)
+                *config = 3;
+
+        return 0;
+}
+
+static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
+                                unsigned long config)
+{
+        unsigned long gcfg1 = readl(DOVE_GLOBAL_CONFIG_1);
+        unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
+
+        gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
+        gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2);
+
+        switch (config) {
+        case 1:
+                gcfg1 |= DOVE_TWSI_ENABLE_OPTION1;
+                break;
+        case 2:
+                gcfg2 |= DOVE_TWSI_ENABLE_OPTION2;
+                break;
+        case 3:
+                gcfg2 |= DOVE_TWSI_ENABLE_OPTION3;
+                break;
+        }
+
+        writel(gcfg1, DOVE_GLOBAL_CONFIG_1);
+        writel(gcfg2, DOVE_GLOBAL_CONFIG_2);
+
+        return 0;
+}
+
+static struct mvebu_mpp_ctrl dove_mpp_controls[] = {
+        MPP_FUNC_CTRL(0, 0, "mpp0", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(1, 1, "mpp1", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(2, 2, "mpp2", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(3, 3, "mpp3", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(4, 4, "mpp4", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(5, 5, "mpp5", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(6, 6, "mpp6", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(7, 7, "mpp7", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(8, 8, "mpp8", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(9, 9, "mpp9", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(10, 10, "mpp10", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(11, 11, "mpp11", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(12, 12, "mpp12", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(13, 13, "mpp13", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(14, 14, "mpp14", dove_pmu_mpp_ctrl),
+        MPP_FUNC_CTRL(15, 15, "mpp15", dove_pmu_mpp_ctrl),
+        MPP_REG_CTRL(16, 23),
+        MPP_FUNC_CTRL(24, 39, "mpp_camera", dove_mpp4_ctrl),
+        MPP_FUNC_CTRL(40, 45, "mpp_sdio0", dove_mpp4_ctrl),
+        MPP_FUNC_CTRL(46, 51, "mpp_sdio1", dove_mpp4_ctrl),
+        MPP_FUNC_GPIO_CTRL(52, 57, "mpp_audio1", dove_audio1_ctrl),
+        MPP_FUNC_CTRL(58, 61, "mpp_spi0", dove_mpp4_ctrl),
+        MPP_FUNC_CTRL(62, 63, "mpp_uart1", dove_mpp4_ctrl),
+        MPP_FUNC_CTRL(64, 71, "mpp_nand", dove_nand_ctrl),
+        MPP_FUNC_CTRL(72, 72, "audio0", dove_audio0_ctrl),
+        MPP_FUNC_CTRL(73, 73, "twsi", dove_twsi_ctrl),
+};
+
+static struct mvebu_mpp_mode dove_mpp_modes[] = {
+        MPP_MODE(0,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "rts"),
+                MPP_FUNCTION(0x03, "sdio0", "cd"),
+                MPP_FUNCTION(0x0f, "lcd0", "pwm"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(1,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "cts"),
+                MPP_FUNCTION(0x03, "sdio0", "wp"),
+                MPP_FUNCTION(0x0f, "lcd1", "pwm"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(2,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "sata", "prsnt"),
+                MPP_FUNCTION(0x02, "uart2", "txd"),
+                MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+                MPP_FUNCTION(0x04, "uart1", "rts"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(3,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "sata", "act"),
+                MPP_FUNCTION(0x02, "uart2", "rxd"),
+                MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+                MPP_FUNCTION(0x04, "uart1", "cts"),
+                MPP_FUNCTION(0x0f, "lcd-spi", "cs1"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(4,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "rts"),
+                MPP_FUNCTION(0x03, "sdio1", "cd"),
+                MPP_FUNCTION(0x04, "spi1", "miso"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(5,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "cts"),
+                MPP_FUNCTION(0x03, "sdio1", "wp"),
+                MPP_FUNCTION(0x04, "spi1", "cs"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(6,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "txd"),
+                MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+                MPP_FUNCTION(0x04, "spi1", "mosi"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(7,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "rxd"),
+                MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+                MPP_FUNCTION(0x04, "spi1", "sck"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(8,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "watchdog", "rstout"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(9,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x05, "pex1", "clkreq"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(10,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x05, "ssp", "sclk"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(11,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "sata", "prsnt"),
+                MPP_FUNCTION(0x02, "sata-1", "act"),
+                MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+                MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+                MPP_FUNCTION(0x05, "pex0", "clkreq"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(12,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "sata", "act"),
+                MPP_FUNCTION(0x02, "uart2", "rts"),
+                MPP_FUNCTION(0x03, "audio0", "extclk"),
+                MPP_FUNCTION(0x04, "sdio1", "cd"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(13,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "cts"),
+                MPP_FUNCTION(0x03, "audio1", "extclk"),
+                MPP_FUNCTION(0x04, "sdio1", "wp"),
+                MPP_FUNCTION(0x05, "ssp", "extclk"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(14,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "txd"),
+                MPP_FUNCTION(0x04, "sdio1", "buspwr"),
+                MPP_FUNCTION(0x05, "ssp", "rxd"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(15,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart2", "rxd"),
+                MPP_FUNCTION(0x04, "sdio1", "ledctrl"),
+                MPP_FUNCTION(0x05, "ssp", "sfrm"),
+                MPP_FUNCTION(0x10, "pmu", NULL)),
+        MPP_MODE(16,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "rts"),
+                MPP_FUNCTION(0x03, "sdio0", "cd"),
+                MPP_FUNCTION(0x04, "lcd-spi", "cs1"),
+                MPP_FUNCTION(0x05, "ac97", "sdi1")),
+        MPP_MODE(17,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "ac97-1", "sysclko"),
+                MPP_FUNCTION(0x02, "uart3", "cts"),
+                MPP_FUNCTION(0x03, "sdio0", "wp"),
+                MPP_FUNCTION(0x04, "twsi", "sda"),
+                MPP_FUNCTION(0x05, "ac97", "sdi2")),
+        MPP_MODE(18,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "txd"),
+                MPP_FUNCTION(0x03, "sdio0", "buspwr"),
+                MPP_FUNCTION(0x04, "lcd0", "pwm"),
+                MPP_FUNCTION(0x05, "ac97", "sdi3")),
+        MPP_MODE(19,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "uart3", "rxd"),
+                MPP_FUNCTION(0x03, "sdio0", "ledctrl"),
+                MPP_FUNCTION(0x04, "twsi", "sck")),
+        MPP_MODE(20,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "ac97", "sysclko"),
+                MPP_FUNCTION(0x02, "lcd-spi", "miso"),
+                MPP_FUNCTION(0x03, "sdio1", "cd"),
+                MPP_FUNCTION(0x05, "sdio0", "cd"),
+                MPP_FUNCTION(0x06, "spi1", "miso")),
+        MPP_MODE(21,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "uart1", "rts"),
+                MPP_FUNCTION(0x02, "lcd-spi", "cs0"),
+                MPP_FUNCTION(0x03, "sdio1", "wp"),
+                MPP_FUNCTION(0x04, "ssp", "sfrm"),
+                MPP_FUNCTION(0x05, "sdio0", "wp"),
+                MPP_FUNCTION(0x06, "spi1", "cs")),
+        MPP_MODE(22,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x01, "uart1", "cts"),
+                MPP_FUNCTION(0x02, "lcd-spi", "mosi"),
+                MPP_FUNCTION(0x03, "sdio1", "buspwr"),
+                MPP_FUNCTION(0x04, "ssp", "txd"),
+                MPP_FUNCTION(0x05, "sdio0", "buspwr"),
+                MPP_FUNCTION(0x06, "spi1", "mosi")),
+        MPP_MODE(23,
+                MPP_FUNCTION(0x00, "gpio", NULL),
+                MPP_FUNCTION(0x02, "lcd-spi", "sck"),
+                MPP_FUNCTION(0x03, "sdio1", "ledctrl"),
+                MPP_FUNCTION(0x04, "ssp", "sclk"),
+                MPP_FUNCTION(0x05, "sdio0", "ledctrl"),
+                MPP_FUNCTION(0x06, "spi1", "sck")),
+        MPP_MODE(24,
+                MPP_FUNCTION(0x00, "camera", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(40,
+                MPP_FUNCTION(0x00, "sdio0", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(46,
+                MPP_FUNCTION(0x00, "sdio1", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(52,
+                MPP_FUNCTION(0x00, "i2s1/spdifo", NULL),
+                MPP_FUNCTION(0x02, "i2s1", NULL),
+                MPP_FUNCTION(0x08, "spdifo", NULL),
+                MPP_FUNCTION(0x0a, "gpio", NULL),
+                MPP_FUNCTION(0x0b, "twsi", NULL),
+                MPP_FUNCTION(0x0c, "ssp/spdifo", NULL),
+                MPP_FUNCTION(0x0e, "ssp", NULL),
+                MPP_FUNCTION(0x0f, "ssp/twsi", NULL)),
+        MPP_MODE(58,
+                MPP_FUNCTION(0x00, "spi0", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(62,
+                MPP_FUNCTION(0x00, "uart1", NULL),
+                MPP_FUNCTION(0x01, "gpio", NULL)),
+        MPP_MODE(64,
+                MPP_FUNCTION(0x00, "nand", NULL),
+                MPP_FUNCTION(0x01, "gpo", NULL)),
+        MPP_MODE(72,
+                MPP_FUNCTION(0x00, "i2s", NULL),
+                MPP_FUNCTION(0x01, "ac97", NULL)),
+        MPP_MODE(73,
+                MPP_FUNCTION(0x00, "twsi-none", NULL),
+                MPP_FUNCTION(0x01, "twsi-opt1", NULL),
+                MPP_FUNCTION(0x02, "twsi-opt2", NULL),
+                MPP_FUNCTION(0x03, "twsi-opt3", NULL)),
+};
+
+static struct pinctrl_gpio_range dove_mpp_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,  0,  0, 32),
+        MPP_GPIO_RANGE(1, 32, 32, 32),
+        MPP_GPIO_RANGE(2, 64, 64,  8),
+};
+
+static struct mvebu_pinctrl_soc_info dove_pinctrl_info = {
+        .controls = dove_mpp_controls,
+        .ncontrols = ARRAY_SIZE(dove_mpp_controls),
+        .modes = dove_mpp_modes,
+        .nmodes = ARRAY_SIZE(dove_mpp_modes),
+        .gpioranges = dove_mpp_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(dove_mpp_gpio_ranges),
+        .variant = 0,
+};
+
+static struct clk *clk;
+
+static struct of_device_id dove_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "marvell,dove-pinctrl", .data = &dove_pinctrl_info },
+        { }
+};
+
+static int __devinit dove_pinctrl_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *match =
+                of_match_device(dove_pinctrl_of_match, &pdev->dev);
+        pdev->dev.platform_data = match->data;
+
+        /*
+         * General MPP Configuration Register is part of pdma registers.
+         * grab clk to make sure it is ticking.
+         */
+        clk = devm_clk_get(&pdev->dev, NULL);
+        if (!IS_ERR(clk))
+                clk_prepare_enable(clk);
+
+        return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit dove_pinctrl_remove(struct platform_device *pdev)
+{
+        int ret;
+
+        ret = mvebu_pinctrl_remove(pdev);
+        if (!IS_ERR(clk))
+                clk_disable_unprepare(clk);
+        return ret;
+}
+
+static struct platform_driver dove_pinctrl_driver = {
+        .driver = {
+                .name = "dove-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(dove_pinctrl_of_match),
+        },
+        .probe = dove_pinctrl_probe,
+        .remove = __devexit_p(dove_pinctrl_remove),
+};
+
+module_platform_driver(dove_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>");
+MODULE_DESCRIPTION("Marvell Dove pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-kirkwood.c b/drivers/pinctrl/pinctrl-kirkwood.c
new file mode 100644
index 000000000000..9a74ef674a0e
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-kirkwood.c
@@ -0,0 +1,472 @@
+/*
+ * Marvell Kirkwood pinctrl driver based on mvebu pinctrl core
+ *
+ * Author: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/err.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include <linux/clk.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-mvebu.h"
+
+#define V(f6180, f6190, f6192, f6281, f6282)            \
+        ((f6180 << 0) | (f6190 << 1) | (f6192 << 2) |   \
+         (f6281 << 3) | (f6282 << 4))
+
+enum kirkwood_variant {
+        VARIANT_MV88F6180 = V(1, 0, 0, 0, 0),
+        VARIANT_MV88F6190 = V(0, 1, 0, 0, 0),
+        VARIANT_MV88F6192 = V(0, 0, 1, 0, 0),
+        VARIANT_MV88F6281 = V(0, 0, 0, 1, 0),
+        VARIANT_MV88F6282 = V(0, 0, 0, 0, 1),
+};
+
+static struct mvebu_mpp_mode mv88f6xxx_mpp_modes[] = {
+        MPP_MODE(0,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io2",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1))),
+        MPP_MODE(1,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io3",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "mosi",     V(1, 1, 1, 1, 1))),
+        MPP_MODE(2,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io4",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(3,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io5",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1))),
+        MPP_MODE(4,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io6",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0))),
+        MPP_MODE(5,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io7",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(6,
+                MPP_VAR_FUNCTION(0x0, "sysrst", "out",   V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "spi", "mosi",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+        MPP_MODE(7,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "pex", "rsto",     V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0x2, "spi", "cs",       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ptp", "trig",     V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(8,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "twsi0", "sda",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "rts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "mii-1", "rxerr",  V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xc, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(9,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "twsi0", "sck",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "cts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xc, "ptp", "evreq",    V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(10,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "sck",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0X3, "uart0", "txd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xc, "ptp", "trig",     V(1, 1, 1, 1, 0))),
+        MPP_MODE(11,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "spi", "miso",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart0", "rxd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "ptp-1", "evreq",  V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xc, "ptp-2", "trig",   V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0xd, "ptp", "clk",      V(1, 1, 1, 1, 0)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1))),
+        MPP_MODE(12,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 0, 1)),
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "clk",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xa, "audio", "spdifo", V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xb, "spi", "mosi",     V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(13,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "cmd",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xa, "audio", "rmclk",  V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "pwm",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(14,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "d0",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xa, "audio", "spdifi", V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xb, "audio-1", "sdi",  V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "mii", "col",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(15,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "d1",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "rts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "txd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "sata0", "act",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "spi", "cs",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(16,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "d2",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "uart0", "cts",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "uart1", "rxd",    V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "sata1", "act",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "extclk",   V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "mii", "crs",      V(1, 1, 1, 1, 1))),
+        MPP_MODE(17,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "sdio", "d3",      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xa, "sata1", "act",    V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xd, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(18,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io0",     V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "pex", "clkreq",   V(0, 0, 0, 0, 1))),
+        MPP_MODE(19,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "nand", "io1",     V(1, 1, 1, 1, 1))),
+        MPP_MODE(20,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txd0",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d0",       V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(1, 0, 0, 0, 0))),
+        MPP_MODE(21,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txd1",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d1",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(22,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txd2",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "prsnt",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d2",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(23,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txd3",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "prsnt",  V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d3",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(24,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxd0",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d4",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(25,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxd1",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d5",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(26,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxd2",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d6",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(27,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxd3",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d7",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(28,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "col",      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d8",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(29,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(1, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txclk",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(1, 0, 0, 0, 0)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d9",       V(0, 0, 0, 0, 1))),
+        MPP_MODE(30,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxctl",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d10",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(31,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxclk",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d11",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(32,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txclko",   V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d12",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(33,
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txctl",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d13",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(34,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "txen",     V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata1", "act",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d14",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(35,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "tx0ql",    V(0, 0, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x3, "ge1", "rxerr",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "sata0", "act",    V(0, 1, 1, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d15",      V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xc, "mii", "rxerr",    V(0, 1, 1, 1, 1))),
+        MPP_MODE(36,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp0",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs1",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifi", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "twsi1", "sda",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(37,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp1",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "tx2ql",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "spdifo", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "twsi1", "sck",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(38,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp2",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rx2ql",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "rmclk",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d18",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(39,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp3",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-cs0",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "bclk",   V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d19",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(40,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp4",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-sck",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdo",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d20",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(41,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp5",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-miso", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "lrclk",  V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d21",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(42,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp6",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "spi-mosi", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "mclk",   V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d22",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(43,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp7",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "int",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "sdi",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d23",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(44,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp8",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rst",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x4, "audio", "extclk", V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "clk",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(45,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "pclk",     V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "e",        V(0, 0, 0, 0, 1))),
+        MPP_MODE(46,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp10",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "fs",       V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "hsync",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(47,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp11",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "drx",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "vsync",    V(0, 0, 0, 0, 1))),
+        MPP_MODE(48,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp12",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "dtx",      V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d16",      V(0, 0, 0, 0, 1))),
+        MPP_MODE(49,
+                MPP_VAR_FUNCTION(0x0, "gpio", NULL,      V(0, 0, 0, 1, 0)),
+                MPP_VAR_FUNCTION(0x0, "gpo", NULL,       V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0x1, "ts", "mp9",       V(0, 0, 0, 1, 0)),
+                MPP_VAR_FUNCTION(0x2, "tdm", "rx0ql",    V(0, 0, 0, 1, 1)),
+                MPP_VAR_FUNCTION(0x5, "ptp", "clk",      V(0, 0, 0, 1, 0)),
+                MPP_VAR_FUNCTION(0xa, "pex", "clkreq",   V(0, 0, 0, 0, 1)),
+                MPP_VAR_FUNCTION(0xb, "lcd", "d17",      V(0, 0, 0, 0, 1))),
+};
+
+static struct mvebu_mpp_ctrl mv88f6180_mpp_controls[] = {
+        MPP_REG_CTRL(0, 29),
+};
+
+static struct pinctrl_gpio_range mv88f6180_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0, 0, 0, 30),
+};
+
+static struct mvebu_mpp_ctrl mv88f619x_mpp_controls[] = {
+        MPP_REG_CTRL(0, 35),
+};
+
+static struct pinctrl_gpio_range mv88f619x_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,  0,  0, 32),
+        MPP_GPIO_RANGE(1, 32, 32,  4),
+};
+
+static struct mvebu_mpp_ctrl mv88f628x_mpp_controls[] = {
+        MPP_REG_CTRL(0, 49),
+};
+
+static struct pinctrl_gpio_range mv88f628x_gpio_ranges[] = {
+        MPP_GPIO_RANGE(0,  0,  0, 32),
+        MPP_GPIO_RANGE(1, 32, 32, 18),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6180_info = {
+        .variant = VARIANT_MV88F6180,
+        .controls = mv88f6180_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f6180_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f6180_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f6180_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6190_info = {
+        .variant = VARIANT_MV88F6190,
+        .controls = mv88f619x_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f619x_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6192_info = {
+        .variant = VARIANT_MV88F6192,
+        .controls = mv88f619x_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f619x_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f619x_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f619x_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6281_info = {
+        .variant = VARIANT_MV88F6281,
+        .controls = mv88f628x_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f628x_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
+};
+
+static struct mvebu_pinctrl_soc_info mv88f6282_info = {
+        .variant = VARIANT_MV88F6282,
+        .controls = mv88f628x_mpp_controls,
+        .ncontrols = ARRAY_SIZE(mv88f628x_mpp_controls),
+        .modes = mv88f6xxx_mpp_modes,
+        .nmodes = ARRAY_SIZE(mv88f6xxx_mpp_modes),
+        .gpioranges = mv88f628x_gpio_ranges,
+        .ngpioranges = ARRAY_SIZE(mv88f628x_gpio_ranges),
+};
+
+static struct of_device_id kirkwood_pinctrl_of_match[] __devinitdata = {
+        { .compatible = "marvell,88f6180-pinctrl", .data = &mv88f6180_info },
+        { .compatible = "marvell,88f6190-pinctrl", .data = &mv88f6190_info },
+        { .compatible = "marvell,88f6192-pinctrl", .data = &mv88f6192_info },
+        { .compatible = "marvell,88f6281-pinctrl", .data = &mv88f6281_info },
+        { .compatible = "marvell,88f6282-pinctrl", .data = &mv88f6282_info },
+        { }
+};
+
+static int __devinit kirkwood_pinctrl_probe(struct platform_device *pdev)
+{
+        const struct of_device_id *match =
+                of_match_device(kirkwood_pinctrl_of_match, &pdev->dev);
+        pdev->dev.platform_data = match->data;
+        return mvebu_pinctrl_probe(pdev);
+}
+
+static int __devexit kirkwood_pinctrl_remove(struct platform_device *pdev)
+{
+        return mvebu_pinctrl_remove(pdev);
+}
+
+static struct platform_driver kirkwood_pinctrl_driver = {
+        .driver = {
+                .name = "kirkwood-pinctrl",
+                .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(kirkwood_pinctrl_of_match),
+        },
+        .probe = kirkwood_pinctrl_probe,
+        .remove = __devexit_p(kirkwood_pinctrl_remove),
+};
+
+module_platform_driver(kirkwood_pinctrl_driver);
+
+MODULE_AUTHOR("Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>");
+MODULE_DESCRIPTION("Marvell Kirkwood pinctrl driver");
+MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-mvebu.c b/drivers/pinctrl/pinctrl-mvebu.c
new file mode 100644
index 000000000000..8e6266c6249a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.c
@@ -0,0 +1,754 @@
+/*
+ * Marvell MVEBU pinctrl core driver
+ *
+ * Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *          Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/platform_device.h>
+#include <linux/module.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_platform.h>
+#include <linux/err.h>
+#include <linux/gpio.h>
+#include <linux/pinctrl/machine.h>
+#include <linux/pinctrl/pinconf.h>
+#include <linux/pinctrl/pinctrl.h>
+#include <linux/pinctrl/pinmux.h>
+
+#include "core.h"
+#include "pinctrl-mvebu.h"
+
+#define MPPS_PER_REG    8
+#define MPP_BITS        4
+#define MPP_MASK        0xf
+
+struct mvebu_pinctrl_function {
+        const char *name;
+        const char **groups;
+        unsigned num_groups;
+};
+
+struct mvebu_pinctrl_group {
+        const char *name;
+        struct mvebu_mpp_ctrl *ctrl;
+        struct mvebu_mpp_ctrl_setting *settings;
+        unsigned num_settings;
+        unsigned gid;
+        unsigned *pins;
+        unsigned npins;
+};
+
+struct mvebu_pinctrl {
+        struct device *dev;
+        struct pinctrl_dev *pctldev;
+        struct pinctrl_desc desc;
+        void __iomem *base;
+        struct mvebu_pinctrl_group *groups;
+        unsigned num_groups;
+        struct mvebu_pinctrl_function *functions;
+        unsigned num_functions;
+        u8 variant;
+};
+
+static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_pid(
+        struct mvebu_pinctrl *pctl, unsigned pid)
+{
+        unsigned n;
+        for (n = 0; n < pctl->num_groups; n++) {
+                if (pid >= pctl->groups[n].pins[0] &&
+                    pid < pctl->groups[n].pins[0] +
+                        pctl->groups[n].npins)
+                        return &pctl->groups[n];
+        }
+        return NULL;
+}
+
+static struct mvebu_pinctrl_group *mvebu_pinctrl_find_group_by_name(
+        struct mvebu_pinctrl *pctl, const char *name)
+{
+        unsigned n;
+        for (n = 0; n < pctl->num_groups; n++) {
+                if (strcmp(name, pctl->groups[n].name) == 0)
+                        return &pctl->groups[n];
+        }
+        return NULL;
+}
+
+static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_val(
+        struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+        unsigned long config)
+{
+        unsigned n;
+        for (n = 0; n < grp->num_settings; n++) {
+                if (config == grp->settings[n].val) {
+                        if (!pctl->variant || (pctl->variant &
+                                               grp->settings[n].variant))
+                                return &grp->settings[n];
+                }
+        }
+        return NULL;
+}
+
+static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_setting_by_name(
+        struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp,
+        const char *name)
+{
+        unsigned n;
+        for (n = 0; n < grp->num_settings; n++) {
+                if (strcmp(name, grp->settings[n].name) == 0) {
+                        if (!pctl->variant || (pctl->variant &
+                                               grp->settings[n].variant))
+                                return &grp->settings[n];
+                }
+        }
+        return NULL;
+}
+
+static struct mvebu_mpp_ctrl_setting *mvebu_pinctrl_find_gpio_setting(
+        struct mvebu_pinctrl *pctl, struct mvebu_pinctrl_group *grp)
+{
+        unsigned n;
+        for (n = 0; n < grp->num_settings; n++) {
+                if (grp->settings[n].flags &
+                        (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+                        if (!pctl->variant || (pctl->variant &
+                                                grp->settings[n].variant))
+                                return &grp->settings[n];
+                }
+        }
+        return NULL;
+}
+
+static struct mvebu_pinctrl_function *mvebu_pinctrl_find_function_by_name(
+        struct mvebu_pinctrl *pctl, const char *name)
+{
+        unsigned n;
+        for (n = 0; n < pctl->num_functions; n++) {
+                if (strcmp(name, pctl->functions[n].name) == 0)
+                        return &pctl->functions[n];
+        }
+        return NULL;
+}
+
+/*
+ * Common mpp pin configuration registers on MVEBU are
+ * registers of eight 4-bit values for each mpp setting.
+ * Register offset and bit mask are calculated accordingly below.
+ */
+static int mvebu_common_mpp_get(struct mvebu_pinctrl *pctl,
+                                struct mvebu_pinctrl_group *grp,
+                                unsigned long *config)
+{
+        unsigned pin = grp->gid;
+        unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
+        unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
+
+        *config = readl(pctl->base + off);
+        *config >>= shift;
+        *config &= MPP_MASK;
+
+        return 0;
+}
+
+static int mvebu_common_mpp_set(struct mvebu_pinctrl *pctl,
+                                struct mvebu_pinctrl_group *grp,
+                                unsigned long config)
+{
+        unsigned pin = grp->gid;
+        unsigned off = (pin / MPPS_PER_REG) * MPP_BITS;
+        unsigned shift = (pin % MPPS_PER_REG) * MPP_BITS;
+        unsigned long reg;
+
+        reg = readl(pctl->base + off);
+        reg &= ~(MPP_MASK << shift);
+        reg |= (config << shift);
+        writel(reg, pctl->base + off);
+
+        return 0;
+}
+
+static int mvebu_pinconf_group_get(struct pinctrl_dev *pctldev,
+                                unsigned gid, unsigned long *config)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+        if (!grp->ctrl)
+                return -EINVAL;
+
+        if (grp->ctrl->mpp_get)
+                return grp->ctrl->mpp_get(grp->ctrl, config);
+
+        return mvebu_common_mpp_get(pctl, grp, config);
+}
+
+static int mvebu_pinconf_group_set(struct pinctrl_dev *pctldev,
+                                unsigned gid, unsigned long config)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+
+        if (!grp->ctrl)
+                return -EINVAL;
+
+        if (grp->ctrl->mpp_set)
+                return grp->ctrl->mpp_set(grp->ctrl, config);
+
+        return mvebu_common_mpp_set(pctl, grp, config);
+}
+
+static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
+                                        struct seq_file *s, unsigned gid)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+        struct mvebu_mpp_ctrl_setting *curr;
+        unsigned long config;
+        unsigned n;
+
+        if (mvebu_pinconf_group_get(pctldev, gid, &config))
+                return;
+
+        curr = mvebu_pinctrl_find_setting_by_val(pctl, grp, config);
+
+        if (curr) {
+                seq_printf(s, "current: %s", curr->name);
+                if (curr->subname)
+                        seq_printf(s, "(%s)", curr->subname);
+                if (curr->flags & (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+                        seq_printf(s, "(");
+                        if (curr->flags & MVEBU_SETTING_GPI)
+                                seq_printf(s, "i");
+                        if (curr->flags & MVEBU_SETTING_GPO)
+                                seq_printf(s, "o");
+                        seq_printf(s, ")");
+                }
+        } else
+                seq_printf(s, "current: UNKNOWN");
+
+        if (grp->num_settings > 1) {
+                seq_printf(s, ", available = [");
+                for (n = 0; n < grp->num_settings; n++) {
+                        if (curr == &grp->settings[n])
+                                continue;
+
+                        /* skip unsupported settings for this variant */
+                        if (pctl->variant &&
+                            !(pctl->variant & grp->settings[n].variant))
+                                continue;
+
+                        seq_printf(s, " %s", grp->settings[n].name);
+                        if (grp->settings[n].subname)
+                                seq_printf(s, "(%s)", grp->settings[n].subname);
+                        if (grp->settings[n].flags &
+                                (MVEBU_SETTING_GPO | MVEBU_SETTING_GPI)) {
+                                seq_printf(s, "(");
+                                if (grp->settings[n].flags & MVEBU_SETTING_GPI)
+                                        seq_printf(s, "i");
+                                if (grp->settings[n].flags & MVEBU_SETTING_GPO)
+                                        seq_printf(s, "o");
+                                seq_printf(s, ")");
+                        }
+                }
+                seq_printf(s, " ]");
+        }
+        return;
+}
+
+static struct pinconf_ops mvebu_pinconf_ops = {
+        .pin_config_group_get = mvebu_pinconf_group_get,
+        .pin_config_group_set = mvebu_pinconf_group_set,
+        .pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
+};
+
+static int mvebu_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->num_functions;
+}
+
+static const char *mvebu_pinmux_get_func_name(struct pinctrl_dev *pctldev,
+                                        unsigned fid)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        return pctl->functions[fid].name;
+}
+
+static int mvebu_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned fid,
+                                const char * const **groups,
+                                unsigned * const num_groups)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+
+        *groups = pctl->functions[fid].groups;
+        *num_groups = pctl->functions[fid].num_groups;
+        return 0;
+}
+
+static int mvebu_pinmux_enable(struct pinctrl_dev *pctldev, unsigned fid,
+                        unsigned gid)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_function *func = &pctl->functions[fid];
+        struct mvebu_pinctrl_group *grp = &pctl->groups[gid];
+        struct mvebu_mpp_ctrl_setting *setting;
+        int ret;
+
+        setting = mvebu_pinctrl_find_setting_by_name(pctl, grp,
+                                                     func->name);
+        if (!setting) {
+                dev_err(pctl->dev,
+                        "unable to find setting %s in group %s\n",
+                        func->name, func->groups[gid]);
+                return -EINVAL;
+        }
+
+        ret = mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+        if (ret) {
+                dev_err(pctl->dev, "cannot set group %s to %s\n",
+                        func->groups[gid], func->name);
+                return ret;
+        }
+
+        return 0;
+}
+
+static int mvebu_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
+                        struct pinctrl_gpio_range *range, unsigned offset)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp;
+        struct mvebu_mpp_ctrl_setting *setting;
+
+        grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+        if (!grp)
+                return -EINVAL;
+
+        if (grp->ctrl->mpp_gpio_req)
+                return grp->ctrl->mpp_gpio_req(grp->ctrl, offset);
+
+        setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+        if (!setting)
+                return -ENOTSUPP;
+
+        return mvebu_pinconf_group_set(pctldev, grp->gid, setting->val);
+}
+
+static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
+           struct pinctrl_gpio_range *range, unsigned offset, bool input)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct mvebu_pinctrl_group *grp;
+        struct mvebu_mpp_ctrl_setting *setting;
+
+        grp = mvebu_pinctrl_find_group_by_pid(pctl, offset);
+        if (!grp)
+                return -EINVAL;
+
+        if (grp->ctrl->mpp_gpio_dir)
+                return grp->ctrl->mpp_gpio_dir(grp->ctrl, offset, input);
+
+        setting = mvebu_pinctrl_find_gpio_setting(pctl, grp);
+        if (!setting)
+                return -ENOTSUPP;
+
+        if ((input && (setting->flags & MVEBU_SETTING_GPI)) ||
+            (!input && (setting->flags & MVEBU_SETTING_GPO)))
+                return 0;
+
+        return -ENOTSUPP;
+}
+
+static struct pinmux_ops mvebu_pinmux_ops = {
+        .get_functions_count = mvebu_pinmux_get_funcs_count,
+        .get_function_name = mvebu_pinmux_get_func_name,
+        .get_function_groups = mvebu_pinmux_get_groups,
+        .gpio_request_enable = mvebu_pinmux_gpio_request_enable,
+        .gpio_set_direction = mvebu_pinmux_gpio_set_direction,
+        .enable = mvebu_pinmux_enable,
+};
+
+static int mvebu_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        return pctl->num_groups;
+}
+
+static const char *mvebu_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
+                                                unsigned gid)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        return pctl->groups[gid].name;
+}
+
+static int mvebu_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
+                                        unsigned gid, const unsigned **pins,
+                                        unsigned *num_pins)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        *pins = pctl->groups[gid].pins;
+        *num_pins = pctl->groups[gid].npins;
+        return 0;
+}
+
+static int mvebu_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
+                                        struct device_node *np,
+                                        struct pinctrl_map **map,
+                                        unsigned *num_maps)
+{
+        struct mvebu_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
+        struct property *prop;
+        const char *function;
+        const char *group;
+        int ret, nmaps, n;
+
+        *map = NULL;
+        *num_maps = 0;
+
+        ret = of_property_read_string(np, "marvell,function", &function);
+        if (ret) {
+                dev_err(pctl->dev,
+                        "missing marvell,function in node %s\n", np->name);
+                return 0;
+        }
+
+        nmaps = of_property_count_strings(np, "marvell,pins");
+        if (nmaps < 0) {
+                dev_err(pctl->dev,
+                        "missing marvell,pins in node %s\n", np->name);
+                return 0;
+        }
+
+        *map = kmalloc(nmaps * sizeof(struct pinctrl_map), GFP_KERNEL);
+        if (map == NULL) {
+                dev_err(pctl->dev,
+                        "cannot allocate pinctrl_map memory for %s\n",
+                        np->name);
+                return -ENOMEM;
+        }
+
+        n = 0;
+        of_property_for_each_string(np, "marvell,pins", prop, group) {
+                struct mvebu_pinctrl_group *grp =
+                        mvebu_pinctrl_find_group_by_name(pctl, group);
+
+                if (!grp) {
+                        dev_err(pctl->dev, "unknown pin %s", group);
+                        continue;
+                }
+
+                if (!mvebu_pinctrl_find_setting_by_name(pctl, grp, function)) {
+                        dev_err(pctl->dev, "unsupported function %s on pin %s",
+                                function, group);
+                        continue;
+                }
+
+                (*map)[n].type = PIN_MAP_TYPE_MUX_GROUP;
+                (*map)[n].data.mux.group = group;
+                (*map)[n].data.mux.function = function;
+                n++;
+        }
+
+        *num_maps = nmaps;
+
+        return 0;
+}
+
+static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
+                                struct pinctrl_map *map, unsigned num_maps)
+{
+        kfree(map);
+}
+
+static struct pinctrl_ops mvebu_pinctrl_ops = {
+        .get_groups_count = mvebu_pinctrl_get_groups_count,
+        .get_group_name = mvebu_pinctrl_get_group_name,
+        .get_group_pins = mvebu_pinctrl_get_group_pins,
+        .dt_node_to_map = mvebu_pinctrl_dt_node_to_map,
+        .dt_free_map = mvebu_pinctrl_dt_free_map,
+};
+
+static int __devinit _add_function(struct mvebu_pinctrl_function *funcs,
+                                   const char *name)
+{
+        while (funcs->num_groups) {
+                /* function already there */
+                if (strcmp(funcs->name, name) == 0) {
+                        funcs->num_groups++;
+                        return -EEXIST;
+                }
+                funcs++;
+        }
+        funcs->name = name;
+        funcs->num_groups = 1;
+        return 0;
+}
+
+static int __devinit mvebu_pinctrl_build_functions(struct platform_device *pdev,
+                                                   struct mvebu_pinctrl *pctl)
+{
+        struct mvebu_pinctrl_function *funcs;
+        int num = 0;
+        int n, s;
+
+        /* we allocate functions for number of pins and hope
+         * there are less unique functions than pins available */
+        funcs = devm_kzalloc(&pdev->dev, pctl->desc.npins *
+                             sizeof(struct mvebu_pinctrl_function), GFP_KERNEL);
+        if (!funcs)
+                return -ENOMEM;
+
+        for (n = 0; n < pctl->num_groups; n++) {
+                struct mvebu_pinctrl_group *grp = &pctl->groups[n];
+                for (s = 0; s < grp->num_settings; s++) {
+                        /* skip unsupported settings on this variant */
+                        if (pctl->variant &&
+                            !(pctl->variant & grp->settings[s].variant))
+                                continue;
+
+                        /* check for unique functions and count groups */
+                        if (_add_function(funcs, grp->settings[s].name))
+                                continue;
+
+                        num++;
+                }
+        }
+
+        /* with the number of unique functions and it's groups known,
+           reallocate functions and assign group names */
+        funcs = krealloc(funcs, num * sizeof(struct mvebu_pinctrl_function),
+                         GFP_KERNEL);
+        if (!funcs)
+                return -ENOMEM;
+
+        pctl->num_functions = num;
+        pctl->functions = funcs;
+
+        for (n = 0; n < pctl->num_groups; n++) {
+                struct mvebu_pinctrl_group *grp = &pctl->groups[n];
+                for (s = 0; s < grp->num_settings; s++) {
+                        struct mvebu_pinctrl_function *f;
+                        const char **groups;
+
+                        /* skip unsupported settings on this variant */
+                        if (pctl->variant &&
+                            !(pctl->variant & grp->settings[s].variant))
+                                continue;
+
+                        f = mvebu_pinctrl_find_function_by_name(pctl,
+                                                        grp->settings[s].name);
+
+                        /* allocate group name array if not done already */
+                        if (!f->groups) {
+                                f->groups = devm_kzalloc(&pdev->dev,
+                                                 f->num_groups * sizeof(char *),
+                                                 GFP_KERNEL);
+                                if (!f->groups)
+                                        return -ENOMEM;
+                        }
+
+                        /* find next free group name and assign current name */
+                        groups = f->groups;
+                        while (*groups)
+                                groups++;
+                        *groups = grp->name;
+                }
+        }
+
+        return 0;
+}
+
+int __devinit mvebu_pinctrl_probe(struct platform_device *pdev)
+{
+        struct mvebu_pinctrl_soc_info *soc = dev_get_platdata(&pdev->dev);
+        struct device_node *np = pdev->dev.of_node;
+        struct mvebu_pinctrl *pctl;
+        void __iomem *base;
+        struct pinctrl_pin_desc *pdesc;
+        unsigned gid, n, k;
+        int ret;
+
+        if (!soc || !soc->controls || !soc->modes) {
+                dev_err(&pdev->dev, "wrong pinctrl soc info\n");
+                return -EINVAL;
+        }
+
+        base = of_iomap(np, 0);
+        if (!base) {
+                dev_err(&pdev->dev, "unable to get base address\n");
+                return -ENODEV;
+        }
+
+        pctl = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pinctrl),
+                        GFP_KERNEL);
+        if (!pctl) {
+                dev_err(&pdev->dev, "unable to alloc driver\n");
+                return -ENOMEM;
+        }
+
+        pctl->desc.name = dev_name(&pdev->dev);
+        pctl->desc.owner = THIS_MODULE;
+        pctl->desc.pctlops = &mvebu_pinctrl_ops;
+        pctl->desc.pmxops = &mvebu_pinmux_ops;
+        pctl->desc.confops = &mvebu_pinconf_ops;
+        pctl->variant = soc->variant;
+        pctl->base = base;
+        pctl->dev = &pdev->dev;
+        platform_set_drvdata(pdev, pctl);
+
+        /* count controls and create names for mvebu generic
+           register controls; also does sanity checks */
+        pctl->num_groups = 0;
+        pctl->desc.npins = 0;
+        for (n = 0; n < soc->ncontrols; n++) {
+                struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+                char *names;
+
+                pctl->desc.npins += ctrl->npins;
+                /* initial control pins */
+                for (k = 0; k < ctrl->npins; k++)
+                        ctrl->pins[k] = ctrl->pid + k;
+
+                /* special soc specific control */
+                if (ctrl->mpp_get || ctrl->mpp_set) {
+                        if (!ctrl->name || !ctrl->mpp_set || !ctrl->mpp_set) {
+                                dev_err(&pdev->dev, "wrong soc control info\n");
+                                return -EINVAL;
+                        }
+                        pctl->num_groups += 1;
+                        continue;
+                }
+
+                /* generic mvebu register control */
+                names = devm_kzalloc(&pdev->dev, ctrl->npins * 8, GFP_KERNEL);
+                if (!names) {
+                        dev_err(&pdev->dev, "failed to alloc mpp names\n");
+                        return -ENOMEM;
+                }
+                for (k = 0; k < ctrl->npins; k++)
+                        sprintf(names + 8*k, "mpp%d", ctrl->pid+k);
+                ctrl->name = names;
+                pctl->num_groups += ctrl->npins;
+        }
+
+        pdesc = devm_kzalloc(&pdev->dev, pctl->desc.npins *
+                             sizeof(struct pinctrl_pin_desc), GFP_KERNEL);
+        if (!pdesc) {
+                dev_err(&pdev->dev, "failed to alloc pinctrl pins\n");
+                return -ENOMEM;
+        }
+
+        for (n = 0; n < pctl->desc.npins; n++)
+                pdesc[n].number = n;
+        pctl->desc.pins = pdesc;
+
+        pctl->groups = devm_kzalloc(&pdev->dev, pctl->num_groups *
+                             sizeof(struct mvebu_pinctrl_group), GFP_KERNEL);
+        if (!pctl->groups) {
+                dev_err(&pdev->dev, "failed to alloc pinctrl groups\n");
+                return -ENOMEM;
+        }
+
+        /* assign mpp controls to groups */
+        gid = 0;
+        for (n = 0; n < soc->ncontrols; n++) {
+                struct mvebu_mpp_ctrl *ctrl = &soc->controls[n];
+                pctl->groups[gid].gid = gid;
+                pctl->groups[gid].ctrl = ctrl;
+                pctl->groups[gid].name = ctrl->name;
+                pctl->groups[gid].pins = ctrl->pins;
+                pctl->groups[gid].npins = ctrl->npins;
+
+                /* generic mvebu register control maps to a number of groups */
+                if (!ctrl->mpp_get && !ctrl->mpp_set) {
+                        pctl->groups[gid].npins = 1;
+
+                        for (k = 1; k < ctrl->npins; k++) {
+                                gid++;
+                                pctl->groups[gid].gid = gid;
+                                pctl->groups[gid].ctrl = ctrl;
+                                pctl->groups[gid].name = &ctrl->name[8*k];
+                                pctl->groups[gid].pins = &ctrl->pins[k];
+                                pctl->groups[gid].npins = 1;
+                        }
+                }
+                gid++;
+        }
+
+        /* assign mpp modes to groups */
+        for (n = 0; n < soc->nmodes; n++) {
+                struct mvebu_mpp_mode *mode = &soc->modes[n];
+                struct mvebu_pinctrl_group *grp =
+                        mvebu_pinctrl_find_group_by_pid(pctl, mode->pid);
+                unsigned num_settings;
+
+                if (!grp) {
+                        dev_warn(&pdev->dev, "unknown pinctrl group %d\n",
+                                mode->pid);
+                        continue;
+                }
+
+                for (num_settings = 0; ;) {
+                        struct mvebu_mpp_ctrl_setting *set =
+                                &mode->settings[num_settings];
+
+                        if (!set->name)
+                                break;
+                        num_settings++;
+
+                        /* skip unsupported settings for this variant */
+                        if (pctl->variant && !(pctl->variant & set->variant))
+                                continue;
+
+                        /* find gpio/gpo/gpi settings */
+                        if (strcmp(set->name, "gpio") == 0)
+                                set->flags = MVEBU_SETTING_GPI |
+                                        MVEBU_SETTING_GPO;
+                        else if (strcmp(set->name, "gpo") == 0)
+                                set->flags = MVEBU_SETTING_GPO;
+                        else if (strcmp(set->name, "gpi") == 0)
+                                set->flags = MVEBU_SETTING_GPI;
+                }
+
+                grp->settings = mode->settings;
+                grp->num_settings = num_settings;
+        }
+
+        ret = mvebu_pinctrl_build_functions(pdev, pctl);
+        if (ret) {
+                dev_err(&pdev->dev, "unable to build functions\n");
+                return ret;
+        }
+
+        pctl->pctldev = pinctrl_register(&pctl->desc, &pdev->dev, pctl);
+        if (!pctl->pctldev) {
+                dev_err(&pdev->dev, "unable to register pinctrl driver\n");
+                return -EINVAL;
+        }
+
+        dev_info(&pdev->dev, "registered pinctrl driver\n");
+
+        /* register gpio ranges */
+        for (n = 0; n < soc->ngpioranges; n++)
+                pinctrl_add_gpio_range(pctl->pctldev, &soc->gpioranges[n]);
+
+        return 0;
+}
+
+int __devexit mvebu_pinctrl_remove(struct platform_device *pdev)
+{
+        struct mvebu_pinctrl *pctl = platform_get_drvdata(pdev);
+        pinctrl_unregister(pctl->pctldev);
+        return 0;
+}
diff --git a/drivers/pinctrl/pinctrl-mvebu.h b/drivers/pinctrl/pinctrl-mvebu.h
new file mode 100644
index 000000000000..90bd3beee860
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-mvebu.h
@@ -0,0 +1,192 @@
+/*
+ * Marvell MVEBU pinctrl driver
+ *
+ * Authors: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ *          Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __PINCTRL_MVEBU_H__
+#define __PINCTRL_MVEBU_H__
+
+/**
+ * struct mvebu_mpp_ctrl - describe a mpp control
+ * @name: name of the control group
+ * @pid: first pin id handled by this control
+ * @npins: number of pins controlled by this control
+ * @mpp_get: (optional) special function to get mpp setting
+ * @mpp_set: (optional) special function to set mpp setting
+ * @mpp_gpio_req: (optional) special function to request gpio
+ * @mpp_gpio_dir: (optional) special function to set gpio direction
+ *
+ * A mpp_ctrl describes a muxable unit, e.g. pin, group of pins, or
+ * internal function, inside the SoC. Each muxable unit can be switched
+ * between two or more different settings, e.g. assign mpp pin 13 to
+ * uart1 or sata.
+ *
+ * If optional mpp_get/_set functions are set these are used to get/set
+ * a specific mode. Otherwise it is assumed that the mpp control is based
+ * on 4-bit groups in subsequent registers. The optional mpp_gpio_req/_dir
+ * functions can be used to allow pin settings with varying gpio pins.
+ */
+struct mvebu_mpp_ctrl {
+        const char *name;
+        u8 pid;
+        u8 npins;
+        unsigned *pins;
+        int (*mpp_get)(struct mvebu_mpp_ctrl *ctrl, unsigned long *config);
+        int (*mpp_set)(struct mvebu_mpp_ctrl *ctrl, unsigned long config);
+        int (*mpp_gpio_req)(struct mvebu_mpp_ctrl *ctrl, u8 pid);
+        int (*mpp_gpio_dir)(struct mvebu_mpp_ctrl *ctrl, u8 pid, bool input);
+};
+
+/**
+ * struct mvebu_mpp_ctrl_setting - describe a mpp ctrl setting
+ * @val: ctrl setting value
+ * @name: ctrl setting name, e.g. uart2, spi0 - unique per mpp_mode
+ * @subname: (optional) additional ctrl setting name, e.g. rts, cts
+ * @variant: (optional) variant identifier mask
+ * @flags: (private) flags to store gpi/gpo/gpio capabilities
+ *
+ * A ctrl_setting describes a specific internal mux function that a mpp pin
+ * can be switched to. The value (val) will be written in the corresponding
+ * register for common mpp pin configuration registers on MVEBU. SoC specific
+ * mpp_get/_set function may use val to distinguish between different settings.
+ *
+ * The name will be used to switch to this setting in DT description, e.g.
+ * marvell,function = "uart2". subname is only for debugging purposes.
+ *
+ * If name is one of "gpi", "gpo", "gpio" gpio capabilities are
+ * parsed during initialization and stored in flags.
+ *
+ * The variant can be used to combine different revisions of one SoC to a
+ * common pinctrl driver. It is matched (AND) with variant of soc_info to
+ * determine if a setting is available on the current SoC revision.
+ */
+struct mvebu_mpp_ctrl_setting {
+        u8 val;
+        const char *name;
+        const char *subname;
+        u8 variant;
+        u8 flags;
+#define  MVEBU_SETTING_GPO      (1 << 0)
+#define  MVEBU_SETTING_GPI      (1 << 1)
+};
+
+/**
+ * struct mvebu_mpp_mode - link ctrl and settings
+ * @pid: first pin id handled by this mode
+ * @settings: list of settings available for this mode
+ *
+ * A mode connects all available settings with the corresponding mpp_ctrl
+ * given by pid.
+ */
+struct mvebu_mpp_mode {
+        u8 pid;
+        struct mvebu_mpp_ctrl_setting *settings;
+};
+
+/**
+ * struct mvebu_pinctrl_soc_info - SoC specific info passed to pinctrl-mvebu
+ * @variant: variant mask of soc_info
+ * @controls: list of available mvebu_mpp_ctrls
+ * @ncontrols: number of available mvebu_mpp_ctrls
+ * @modes: list of available mvebu_mpp_modes
+ * @nmodes: number of available mvebu_mpp_modes
+ * @gpioranges: list of pinctrl_gpio_ranges
+ * @ngpioranges: number of available pinctrl_gpio_ranges
+ *
+ * This struct describes all pinctrl related information for a specific SoC.
+ * If variant is unequal 0 it will be matched (AND) with variant of each
+ * setting and allows to distinguish between different revisions of one SoC.
+ */
+struct mvebu_pinctrl_soc_info {
+        u8 variant;
+        struct mvebu_mpp_ctrl *controls;
+        int ncontrols;
+        struct mvebu_mpp_mode *modes;
+        int nmodes;
+        struct pinctrl_gpio_range *gpioranges;
+        int ngpioranges;
+};
+
+#define MPP_REG_CTRL(_idl, _idh)                                \
+        {                                                       \
+                .name = NULL,                                   \
+                .pid = _idl,                                    \
+                .npins = _idh - _idl + 1,                       \
+                .pins = (unsigned[_idh - _idl + 1]) { },        \
+                .mpp_get = NULL,                                \
+                .mpp_set = NULL,                                \
+                .mpp_gpio_req = NULL,                           \
+                .mpp_gpio_dir = NULL,                           \
+        }
+
+#define MPP_FUNC_CTRL(_idl, _idh, _name, _func)                 \
+        {                                                       \
+                .name = _name,                                  \
+                .pid = _idl,                                    \
+                .npins = _idh - _idl + 1,                       \
+                .pins = (unsigned[_idh - _idl + 1]) { },        \
+                .mpp_get = _func ## _get,                       \
+                .mpp_set = _func ## _set,                       \
+                .mpp_gpio_req = NULL,                           \
+                .mpp_gpio_dir = NULL,                           \
+        }
+
+#define MPP_FUNC_GPIO_CTRL(_idl, _idh, _name, _func)            \
+        {                                                       \
+                .name = _name,                                  \
+                .pid = _idl,                                    \
+                .npins = _idh - _idl + 1,                       \
+                .pins = (unsigned[_idh - _idl + 1]) { },        \
+                .mpp_get = _func ## _get,                       \
+                .mpp_set = _func ## _set,                       \
+                .mpp_gpio_req = _func ## _gpio_req,             \
+                .mpp_gpio_dir = _func ## _gpio_dir,             \
+        }
+
+#define _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)         \
+        {                                                       \
+                .val = _val,                                    \
+                .name = _name,                                  \
+                .subname = _subname,                            \
+                .variant = _mask,                               \
+                .flags = 0,                                     \
+        }
+
+#if defined(CONFIG_DEBUG_FS)
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)          \
+        _MPP_VAR_FUNCTION(_val, _name, _subname, _mask)
+#else
+#define MPP_VAR_FUNCTION(_val, _name, _subname, _mask)          \
+        _MPP_VAR_FUNCTION(_val, _name, NULL, _mask)
+#endif
+
+#define MPP_FUNCTION(_val, _name, _subname)                     \
+        MPP_VAR_FUNCTION(_val, _name, _subname, (u8)-1)
+
+#define MPP_MODE(_id, ...)                                      \
+        {                                                       \
+                .pid = _id,                                     \
+                .settings = (struct mvebu_mpp_ctrl_setting[]){  \
+                        __VA_ARGS__, { } },                     \
+        }
+
+#define MPP_GPIO_RANGE(_id, _pinbase, _gpiobase, _npins)        \
+        {                                                       \
+                .name = "mvebu-gpio",                           \
+                .id = _id,                                      \
+                .pin_base = _pinbase,                           \
+                .base = _gpiobase,                              \
+                .npins = _npins,                                \
+        }
+
+int mvebu_pinctrl_probe(struct platform_device *pdev);
+int mvebu_pinctrl_remove(struct platform_device *pdev);
+
+#endif
diff --git a/drivers/spi/spi-omap-100k.c b/drivers/spi/spi-omap-100k.c
index 9bd1c92ad96e..dfb4b7f448c5 100644
--- a/drivers/spi/spi-omap-100k.c
+++ b/drivers/spi/spi-omap-100k.c
@@ -37,8 +37,6 @@
 
 #include <linux/spi/spi.h>
 
-#include <plat/clock.h>
-
 #define OMAP1_SPI100K_MAX_FREQ          48000000
 
 #define ICR_SPITAS      (OMAP7XX_ICR_BASE + 0x12)
diff --git a/drivers/spi/spi-omap2-mcspi.c b/drivers/spi/spi-omap2-mcspi.c
index 474e2174e08a..3542fdc664b1 100644
--- a/drivers/spi/spi-omap2-mcspi.c
+++ b/drivers/spi/spi-omap2-mcspi.c
@@ -43,7 +43,6 @@
 
 #include <linux/spi/spi.h>
 
-#include <plat/clock.h>
 #include <linux/platform_data/spi-omap2-mcspi.h>
 
 #define OMAP2_MCSPI_MAX_FREQ            48000000