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-rw-r--r--drivers/media/rc/fintek-cir.c32
-rw-r--r--drivers/media/rc/nuvoton-cir.c145
2 files changed, 90 insertions, 87 deletions
diff --git a/drivers/media/rc/fintek-cir.c b/drivers/media/rc/fintek-cir.c
index 6aabf7ae3a31..ab30c64f8124 100644
--- a/drivers/media/rc/fintek-cir.c
+++ b/drivers/media/rc/fintek-cir.c
@@ -23,6 +23,8 @@
23 * USA 23 * USA
24 */ 24 */
25 25
26#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
27
26#include <linux/kernel.h> 28#include <linux/kernel.h>
27#include <linux/module.h> 29#include <linux/module.h>
28#include <linux/pnp.h> 30#include <linux/pnp.h>
@@ -110,30 +112,32 @@ static u8 fintek_cir_reg_read(struct fintek_dev *fintek, u8 offset)
110 return val; 112 return val;
111} 113}
112 114
113#define pr_reg(text, ...) \
114 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
115
116/* dump current cir register contents */ 115/* dump current cir register contents */
117static void cir_dump_regs(struct fintek_dev *fintek) 116static void cir_dump_regs(struct fintek_dev *fintek)
118{ 117{
119 fintek_config_mode_enable(fintek); 118 fintek_config_mode_enable(fintek);
120 fintek_select_logical_dev(fintek, fintek->logical_dev_cir); 119 fintek_select_logical_dev(fintek, fintek->logical_dev_cir);
121 120
122 pr_reg("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME); 121 pr_info("%s: Dump CIR logical device registers:\n", FINTEK_DRIVER_NAME);
123 pr_reg(" * CR CIR BASE ADDR: 0x%x\n", 122 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
124 (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) | 123 (fintek_cr_read(fintek, CIR_CR_BASE_ADDR_HI) << 8) |
125 fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO)); 124 fintek_cr_read(fintek, CIR_CR_BASE_ADDR_LO));
126 pr_reg(" * CR CIR IRQ NUM: 0x%x\n", 125 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
127 fintek_cr_read(fintek, CIR_CR_IRQ_SEL)); 126 fintek_cr_read(fintek, CIR_CR_IRQ_SEL));
128 127
129 fintek_config_mode_disable(fintek); 128 fintek_config_mode_disable(fintek);
130 129
131 pr_reg("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME); 130 pr_info("%s: Dump CIR registers:\n", FINTEK_DRIVER_NAME);
132 pr_reg(" * STATUS: 0x%x\n", fintek_cir_reg_read(fintek, CIR_STATUS)); 131 pr_info(" * STATUS: 0x%x\n",
133 pr_reg(" * CONTROL: 0x%x\n", fintek_cir_reg_read(fintek, CIR_CONTROL)); 132 fintek_cir_reg_read(fintek, CIR_STATUS));
134 pr_reg(" * RX_DATA: 0x%x\n", fintek_cir_reg_read(fintek, CIR_RX_DATA)); 133 pr_info(" * CONTROL: 0x%x\n",
135 pr_reg(" * TX_CONTROL: 0x%x\n", fintek_cir_reg_read(fintek, CIR_TX_CONTROL)); 134 fintek_cir_reg_read(fintek, CIR_CONTROL));
136 pr_reg(" * TX_DATA: 0x%x\n", fintek_cir_reg_read(fintek, CIR_TX_DATA)); 135 pr_info(" * RX_DATA: 0x%x\n",
136 fintek_cir_reg_read(fintek, CIR_RX_DATA));
137 pr_info(" * TX_CONTROL: 0x%x\n",
138 fintek_cir_reg_read(fintek, CIR_TX_CONTROL));
139 pr_info(" * TX_DATA: 0x%x\n",
140 fintek_cir_reg_read(fintek, CIR_TX_DATA));
137} 141}
138 142
139/* detect hardware features */ 143/* detect hardware features */
diff --git a/drivers/media/rc/nuvoton-cir.c b/drivers/media/rc/nuvoton-cir.c
index dc8a7dddccd4..699eef39128b 100644
--- a/drivers/media/rc/nuvoton-cir.c
+++ b/drivers/media/rc/nuvoton-cir.c
@@ -25,6 +25,8 @@
25 * USA 25 * USA
26 */ 26 */
27 27
28#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
29
28#include <linux/kernel.h> 30#include <linux/kernel.h>
29#include <linux/module.h> 31#include <linux/module.h>
30#include <linux/pnp.h> 32#include <linux/pnp.h>
@@ -123,43 +125,40 @@ static u8 nvt_cir_wake_reg_read(struct nvt_dev *nvt, u8 offset)
123 return val; 125 return val;
124} 126}
125 127
126#define pr_reg(text, ...) \
127 printk(KERN_INFO KBUILD_MODNAME ": " text, ## __VA_ARGS__)
128
129/* dump current cir register contents */ 128/* dump current cir register contents */
130static void cir_dump_regs(struct nvt_dev *nvt) 129static void cir_dump_regs(struct nvt_dev *nvt)
131{ 130{
132 nvt_efm_enable(nvt); 131 nvt_efm_enable(nvt);
133 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR); 132 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR);
134 133
135 pr_reg("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME); 134 pr_info("%s: Dump CIR logical device registers:\n", NVT_DRIVER_NAME);
136 pr_reg(" * CR CIR ACTIVE : 0x%x\n", 135 pr_info(" * CR CIR ACTIVE : 0x%x\n",
137 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); 136 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
138 pr_reg(" * CR CIR BASE ADDR: 0x%x\n", 137 pr_info(" * CR CIR BASE ADDR: 0x%x\n",
139 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | 138 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
140 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); 139 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
141 pr_reg(" * CR CIR IRQ NUM: 0x%x\n", 140 pr_info(" * CR CIR IRQ NUM: 0x%x\n",
142 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); 141 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
143 142
144 nvt_efm_disable(nvt); 143 nvt_efm_disable(nvt);
145 144
146 pr_reg("%s: Dump CIR registers:\n", NVT_DRIVER_NAME); 145 pr_info("%s: Dump CIR registers:\n", NVT_DRIVER_NAME);
147 pr_reg(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON)); 146 pr_info(" * IRCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRCON));
148 pr_reg(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS)); 147 pr_info(" * IRSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRSTS));
149 pr_reg(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN)); 148 pr_info(" * IREN: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IREN));
150 pr_reg(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT)); 149 pr_info(" * RXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_RXFCONT));
151 pr_reg(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP)); 150 pr_info(" * CP: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CP));
152 pr_reg(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC)); 151 pr_info(" * CC: 0x%x\n", nvt_cir_reg_read(nvt, CIR_CC));
153 pr_reg(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH)); 152 pr_info(" * SLCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCH));
154 pr_reg(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL)); 153 pr_info(" * SLCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SLCL));
155 pr_reg(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON)); 154 pr_info(" * FIFOCON: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FIFOCON));
156 pr_reg(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS)); 155 pr_info(" * IRFIFOSTS: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFIFOSTS));
157 pr_reg(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO)); 156 pr_info(" * SRXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_SRXFIFO));
158 pr_reg(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT)); 157 pr_info(" * TXFCONT: 0x%x\n", nvt_cir_reg_read(nvt, CIR_TXFCONT));
159 pr_reg(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO)); 158 pr_info(" * STXFIFO: 0x%x\n", nvt_cir_reg_read(nvt, CIR_STXFIFO));
160 pr_reg(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH)); 159 pr_info(" * FCCH: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCH));
161 pr_reg(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL)); 160 pr_info(" * FCCL: 0x%x\n", nvt_cir_reg_read(nvt, CIR_FCCL));
162 pr_reg(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM)); 161 pr_info(" * IRFSM: 0x%x\n", nvt_cir_reg_read(nvt, CIR_IRFSM));
163} 162}
164 163
165/* dump current cir wake register contents */ 164/* dump current cir wake register contents */
@@ -170,59 +169,59 @@ static void cir_wake_dump_regs(struct nvt_dev *nvt)
170 nvt_efm_enable(nvt); 169 nvt_efm_enable(nvt);
171 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE); 170 nvt_select_logical_dev(nvt, LOGICAL_DEV_CIR_WAKE);
172 171
173 pr_reg("%s: Dump CIR WAKE logical device registers:\n", 172 pr_info("%s: Dump CIR WAKE logical device registers:\n",
174 NVT_DRIVER_NAME); 173 NVT_DRIVER_NAME);
175 pr_reg(" * CR CIR WAKE ACTIVE : 0x%x\n", 174 pr_info(" * CR CIR WAKE ACTIVE : 0x%x\n",
176 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN)); 175 nvt_cr_read(nvt, CR_LOGICAL_DEV_EN));
177 pr_reg(" * CR CIR WAKE BASE ADDR: 0x%x\n", 176 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n",
178 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) | 177 (nvt_cr_read(nvt, CR_CIR_BASE_ADDR_HI) << 8) |
179 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO)); 178 nvt_cr_read(nvt, CR_CIR_BASE_ADDR_LO));
180 pr_reg(" * CR CIR WAKE IRQ NUM: 0x%x\n", 179 pr_info(" * CR CIR WAKE IRQ NUM: 0x%x\n",
181 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC)); 180 nvt_cr_read(nvt, CR_CIR_IRQ_RSRC));
182 181
183 nvt_efm_disable(nvt); 182 nvt_efm_disable(nvt);
184 183
185 pr_reg("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME); 184 pr_info("%s: Dump CIR WAKE registers\n", NVT_DRIVER_NAME);
186 pr_reg(" * IRCON: 0x%x\n", 185 pr_info(" * IRCON: 0x%x\n",
187 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON)); 186 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRCON));
188 pr_reg(" * IRSTS: 0x%x\n", 187 pr_info(" * IRSTS: 0x%x\n",
189 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS)); 188 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRSTS));
190 pr_reg(" * IREN: 0x%x\n", 189 pr_info(" * IREN: 0x%x\n",
191 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN)); 190 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IREN));
192 pr_reg(" * FIFO CMP DEEP: 0x%x\n", 191 pr_info(" * FIFO CMP DEEP: 0x%x\n",
193 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP)); 192 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_DEEP));
194 pr_reg(" * FIFO CMP TOL: 0x%x\n", 193 pr_info(" * FIFO CMP TOL: 0x%x\n",
195 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL)); 194 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_CMP_TOL));
196 pr_reg(" * FIFO COUNT: 0x%x\n", 195 pr_info(" * FIFO COUNT: 0x%x\n",
197 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT)); 196 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT));
198 pr_reg(" * SLCH: 0x%x\n", 197 pr_info(" * SLCH: 0x%x\n",
199 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH)); 198 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCH));
200 pr_reg(" * SLCL: 0x%x\n", 199 pr_info(" * SLCL: 0x%x\n",
201 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL)); 200 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SLCL));
202 pr_reg(" * FIFOCON: 0x%x\n", 201 pr_info(" * FIFOCON: 0x%x\n",
203 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON)); 202 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFOCON));
204 pr_reg(" * SRXFSTS: 0x%x\n", 203 pr_info(" * SRXFSTS: 0x%x\n",
205 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS)); 204 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SRXFSTS));
206 pr_reg(" * SAMPLE RX FIFO: 0x%x\n", 205 pr_info(" * SAMPLE RX FIFO: 0x%x\n",
207 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO)); 206 nvt_cir_wake_reg_read(nvt, CIR_WAKE_SAMPLE_RX_FIFO));
208 pr_reg(" * WR FIFO DATA: 0x%x\n", 207 pr_info(" * WR FIFO DATA: 0x%x\n",
209 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA)); 208 nvt_cir_wake_reg_read(nvt, CIR_WAKE_WR_FIFO_DATA));
210 pr_reg(" * RD FIFO ONLY: 0x%x\n", 209 pr_info(" * RD FIFO ONLY: 0x%x\n",
211 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); 210 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
212 pr_reg(" * RD FIFO ONLY IDX: 0x%x\n", 211 pr_info(" * RD FIFO ONLY IDX: 0x%x\n",
213 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX)); 212 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY_IDX));
214 pr_reg(" * FIFO IGNORE: 0x%x\n", 213 pr_info(" * FIFO IGNORE: 0x%x\n",
215 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE)); 214 nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_IGNORE));
216 pr_reg(" * IRFSM: 0x%x\n", 215 pr_info(" * IRFSM: 0x%x\n",
217 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM)); 216 nvt_cir_wake_reg_read(nvt, CIR_WAKE_IRFSM));
218 217
219 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT); 218 fifo_len = nvt_cir_wake_reg_read(nvt, CIR_WAKE_FIFO_COUNT);
220 pr_reg("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len); 219 pr_info("%s: Dump CIR WAKE FIFO (len %d)\n", NVT_DRIVER_NAME, fifo_len);
221 pr_reg("* Contents = "); 220 pr_info("* Contents =");
222 for (i = 0; i < fifo_len; i++) 221 for (i = 0; i < fifo_len; i++)
223 printk(KERN_CONT "%02x ", 222 pr_cont(" %02x",
224 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY)); 223 nvt_cir_wake_reg_read(nvt, CIR_WAKE_RD_FIFO_ONLY));
225 printk(KERN_CONT "\n"); 224 pr_cont("\n");
226} 225}
227 226
228/* detect hardware features */ 227/* detect hardware features */
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-25 09:24:00 -0500