diff options
-rw-r--r-- | drivers/thermal/ti-soc-thermal/dra752-thermal-data.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c index e5d8326a54d6..a4929272074f 100644 --- a/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c +++ b/drivers/thermal/ti-soc-thermal/dra752-thermal-data.c | |||
@@ -42,6 +42,7 @@ dra752_core_temp_sensor_registers = { | |||
42 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK, | 42 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_CORE_MASK, |
43 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK, | 43 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_CORE_MASK, |
44 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | 44 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, |
45 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, | ||
45 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK, | 46 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_CORE_MASK, |
46 | .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK, | 47 | .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_CORE_MASK, |
47 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK, | 48 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_CORE_MASK, |
@@ -77,6 +78,7 @@ dra752_iva_temp_sensor_registers = { | |||
77 | .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK, | 78 | .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_IVA_MASK, |
78 | .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK, | 79 | .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_IVA_MASK, |
79 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | 80 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, |
81 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, | ||
80 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK, | 82 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_IVA_MASK, |
81 | .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK, | 83 | .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_IVA_MASK, |
82 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK, | 84 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_IVA_MASK, |
@@ -112,6 +114,7 @@ dra752_mpu_temp_sensor_registers = { | |||
112 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK, | 114 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_MPU_MASK, |
113 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK, | 115 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_MPU_MASK, |
114 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | 116 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, |
117 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, | ||
115 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK, | 118 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_MPU_MASK, |
116 | .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK, | 119 | .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_MPU_MASK, |
117 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK, | 120 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_MPU_MASK, |
@@ -147,6 +150,7 @@ dra752_dspeve_temp_sensor_registers = { | |||
147 | .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK, | 150 | .mask_hot_mask = DRA752_BANDGAP_CTRL_2_MASK_HOT_DSPEVE_MASK, |
148 | .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK, | 151 | .mask_cold_mask = DRA752_BANDGAP_CTRL_2_MASK_COLD_DSPEVE_MASK, |
149 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | 152 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, |
153 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, | ||
150 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK, | 154 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_2_FREEZE_DSPEVE_MASK, |
151 | .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK, | 155 | .mask_clear_mask = DRA752_BANDGAP_CTRL_2_CLEAR_DSPEVE_MASK, |
152 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK, | 156 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_2_CLEAR_ACCUM_DSPEVE_MASK, |
@@ -182,6 +186,7 @@ dra752_gpu_temp_sensor_registers = { | |||
182 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK, | 186 | .mask_hot_mask = DRA752_BANDGAP_CTRL_1_MASK_HOT_GPU_MASK, |
183 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK, | 187 | .mask_cold_mask = DRA752_BANDGAP_CTRL_1_MASK_COLD_GPU_MASK, |
184 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, | 188 | .mask_sidlemode_mask = DRA752_BANDGAP_CTRL_1_SIDLEMODE_MASK, |
189 | .mask_counter_delay_mask = DRA752_BANDGAP_CTRL_1_COUNTER_DELAY_MASK, | ||
185 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK, | 190 | .mask_freeze_mask = DRA752_BANDGAP_CTRL_1_FREEZE_GPU_MASK, |
186 | .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK, | 191 | .mask_clear_mask = DRA752_BANDGAP_CTRL_1_CLEAR_GPU_MASK, |
187 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK, | 192 | .mask_clear_accum_mask = DRA752_BANDGAP_CTRL_1_CLEAR_ACCUM_GPU_MASK, |