2 files changed, 28 insertions, 0 deletions

diff --git a/arch/mips/include/asm/mach-ralink/mt7620.h b/arch/mips/include/asm/mach-ralink/mt7620.h
index b272649933c9..9809972ea882 100644
--- a/arch/mips/include/asm/mach-ralink/mt7620.h
+++ b/arch/mips/include/asm/mach-ralink/mt7620.h
@@ -50,6 +50,14 @@
 #define SYSCFG0_DRAM_TYPE_DDR1          1
 #define SYSCFG0_DRAM_TYPE_DDR2          2
 
+#define MT7620_DRAM_BASE                0x0
+#define MT7620_SDRAM_SIZE_MIN           2
+#define MT7620_SDRAM_SIZE_MAX           64
+#define MT7620_DDR1_SIZE_MIN            32
+#define MT7620_DDR1_SIZE_MAX            128
+#define MT7620_DDR2_SIZE_MIN            32
+#define MT7620_DDR2_SIZE_MAX            256
+
 #define MT7620_GPIO_MODE_I2C            BIT(0)
 #define MT7620_GPIO_MODE_UART0_SHIFT    2
 #define MT7620_GPIO_MODE_UART0_MASK     0x7
diff --git a/arch/mips/ralink/mt7620.c b/arch/mips/ralink/mt7620.c
index af19ae740162..0018b1a661f6 100644
--- a/arch/mips/ralink/mt7620.c
+++ b/arch/mips/ralink/mt7620.c
@@ -211,4 +211,24 @@ void prom_soc_init(struct ralink_soc_info *soc_info)
 
         cfg0 = __raw_readl(sysc + SYSC_REG_SYSTEM_CONFIG0);
         dram_type = (cfg0 >> SYSCFG0_DRAM_TYPE_SHIFT) & SYSCFG0_DRAM_TYPE_MASK;
+
+        switch (dram_type) {
+        case SYSCFG0_DRAM_TYPE_SDRAM:
+                soc_info->mem_size_min = MT7620_SDRAM_SIZE_MIN;
+                soc_info->mem_size_max = MT7620_SDRAM_SIZE_MAX;
+                break;
+
+        case SYSCFG0_DRAM_TYPE_DDR1:
+                soc_info->mem_size_min = MT7620_DDR1_SIZE_MIN;
+                soc_info->mem_size_max = MT7620_DDR1_SIZE_MAX;
+                break;
+
+        case SYSCFG0_DRAM_TYPE_DDR2:
+                soc_info->mem_size_min = MT7620_DDR2_SIZE_MIN;
+                soc_info->mem_size_max = MT7620_DDR2_SIZE_MAX;
+                break;
+        default:
+                BUG();
+        }
+        soc_info->mem_base = MT7620_DRAM_BASE;
 }