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-rw-r--r--drivers/net/wireless/ath/ath9k/ahb.c2
-rw-r--r--drivers/net/wireless/ath/ath9k/ani.c44
-rw-r--r--drivers/net/wireless/ath/ath9k/beacon.c32
-rw-r--r--drivers/net/wireless/ath/ath9k/btcoex.c8
-rw-r--r--drivers/net/wireless/ath/ath9k/calib.c102
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.c16
-rw-r--r--drivers/net/wireless/ath/ath9k/debug.h15
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_4k.c24
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_9287.c24
-rw-r--r--drivers/net/wireless/ath/ath9k/eeprom_def.c24
-rw-r--r--drivers/net/wireless/ath/ath9k/hw.c120
-rw-r--r--drivers/net/wireless/ath/ath9k/mac.c48
-rw-r--r--drivers/net/wireless/ath/ath9k/main.c148
-rw-r--r--drivers/net/wireless/ath/ath9k/phy.c10
-rw-r--r--drivers/net/wireless/ath/ath9k/rc.c15
-rw-r--r--drivers/net/wireless/ath/ath9k/recv.c18
-rw-r--r--drivers/net/wireless/ath/ath9k/xmit.c46
17 files changed, 356 insertions, 340 deletions
diff --git a/drivers/net/wireless/ath/ath9k/ahb.c b/drivers/net/wireless/ath/ath9k/ahb.c
index 2ad7d0280f7a..41e16ed2f07d 100644
--- a/drivers/net/wireless/ath/ath9k/ahb.c
+++ b/drivers/net/wireless/ath/ath9k/ahb.c
@@ -40,7 +40,7 @@ static bool ath_ahb_eeprom_read(struct ath_hw *ah, u32 off, u16 *data)
40 40
41 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data; 41 pdata = (struct ath9k_platform_data *) pdev->dev.platform_data;
42 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) { 42 if (off >= (ARRAY_SIZE(pdata->eeprom_data))) {
43 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 43 DPRINTF(ah, ATH_DBG_FATAL,
44 "%s: flash read failed, offset %08x is out of range\n", 44 "%s: flash read failed, offset %08x is out of range\n",
45 __func__, off); 45 __func__, off);
46 return false; 46 return false;
diff --git a/drivers/net/wireless/ath/ath9k/ani.c b/drivers/net/wireless/ath/ath9k/ani.c
index 2b493742ef10..e4f9559d25b6 100644
--- a/drivers/net/wireless/ath/ath9k/ani.c
+++ b/drivers/net/wireless/ath/ath9k/ani.c
@@ -31,7 +31,7 @@ static int ath9k_hw_get_ani_channel_idx(struct ath_hw *ah,
31 } 31 }
32 } 32 }
33 33
34 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 34 DPRINTF(ah, ATH_DBG_ANI,
35 "No more channel states left. Using channel 0\n"); 35 "No more channel states left. Using channel 0\n");
36 36
37 return 0; 37 return 0;
@@ -47,7 +47,7 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
47 u32 level = param; 47 u32 level = param;
48 48
49 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) { 49 if (level >= ARRAY_SIZE(ah->totalSizeDesired)) {
50 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 50 DPRINTF(ah, ATH_DBG_ANI,
51 "level out of range (%u > %u)\n", 51 "level out of range (%u > %u)\n",
52 level, 52 level,
53 (unsigned)ARRAY_SIZE(ah->totalSizeDesired)); 53 (unsigned)ARRAY_SIZE(ah->totalSizeDesired));
@@ -152,7 +152,7 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
152 u32 level = param; 152 u32 level = param;
153 153
154 if (level >= ARRAY_SIZE(firstep)) { 154 if (level >= ARRAY_SIZE(firstep)) {
155 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 155 DPRINTF(ah, ATH_DBG_ANI,
156 "level out of range (%u > %u)\n", 156 "level out of range (%u > %u)\n",
157 level, 157 level,
158 (unsigned) ARRAY_SIZE(firstep)); 158 (unsigned) ARRAY_SIZE(firstep));
@@ -174,7 +174,7 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
174 u32 level = param; 174 u32 level = param;
175 175
176 if (level >= ARRAY_SIZE(cycpwrThr1)) { 176 if (level >= ARRAY_SIZE(cycpwrThr1)) {
177 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 177 DPRINTF(ah, ATH_DBG_ANI,
178 "level out of range (%u > %u)\n", 178 "level out of range (%u > %u)\n",
179 level, 179 level,
180 (unsigned) 180 (unsigned)
@@ -194,23 +194,23 @@ static bool ath9k_hw_ani_control(struct ath_hw *ah,
194 case ATH9K_ANI_PRESENT: 194 case ATH9K_ANI_PRESENT:
195 break; 195 break;
196 default: 196 default:
197 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 197 DPRINTF(ah, ATH_DBG_ANI,
198 "invalid cmd %u\n", cmd); 198 "invalid cmd %u\n", cmd);
199 return false; 199 return false;
200 } 200 }
201 201
202 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "ANI parameters:\n"); 202 DPRINTF(ah, ATH_DBG_ANI, "ANI parameters:\n");
203 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 203 DPRINTF(ah, ATH_DBG_ANI,
204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, " 204 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
205 "ofdmWeakSigDetectOff=%d\n", 205 "ofdmWeakSigDetectOff=%d\n",
206 aniState->noiseImmunityLevel, aniState->spurImmunityLevel, 206 aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
207 !aniState->ofdmWeakSigDetectOff); 207 !aniState->ofdmWeakSigDetectOff);
208 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 208 DPRINTF(ah, ATH_DBG_ANI,
209 "cckWeakSigThreshold=%d, " 209 "cckWeakSigThreshold=%d, "
210 "firstepLevel=%d, listenTime=%d\n", 210 "firstepLevel=%d, listenTime=%d\n",
211 aniState->cckWeakSigThreshold, aniState->firstepLevel, 211 aniState->cckWeakSigThreshold, aniState->firstepLevel,
212 aniState->listenTime); 212 aniState->listenTime);
213 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 213 DPRINTF(ah, ATH_DBG_ANI,
214 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n", 214 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
215 aniState->cycleCount, aniState->ofdmPhyErrCount, 215 aniState->cycleCount, aniState->ofdmPhyErrCount,
216 aniState->cckPhyErrCount); 216 aniState->cckPhyErrCount);
@@ -240,7 +240,7 @@ static void ath9k_ani_restart(struct ath_hw *ah)
240 240
241 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) { 241 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
242 aniState->ofdmPhyErrBase = 0; 242 aniState->ofdmPhyErrBase = 0;
243 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 243 DPRINTF(ah, ATH_DBG_ANI,
244 "OFDM Trigger is too high for hw counters\n"); 244 "OFDM Trigger is too high for hw counters\n");
245 } else { 245 } else {
246 aniState->ofdmPhyErrBase = 246 aniState->ofdmPhyErrBase =
@@ -248,13 +248,13 @@ static void ath9k_ani_restart(struct ath_hw *ah)
248 } 248 }
249 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) { 249 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
250 aniState->cckPhyErrBase = 0; 250 aniState->cckPhyErrBase = 0;
251 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 251 DPRINTF(ah, ATH_DBG_ANI,
252 "CCK Trigger is too high for hw counters\n"); 252 "CCK Trigger is too high for hw counters\n");
253 } else { 253 } else {
254 aniState->cckPhyErrBase = 254 aniState->cckPhyErrBase =
255 AR_PHY_COUNTMAX - aniState->cckTrigHigh; 255 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
256 } 256 }
257 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 257 DPRINTF(ah, ATH_DBG_ANI,
258 "Writing ofdmbase=%u cckbase=%u\n", 258 "Writing ofdmbase=%u cckbase=%u\n",
259 aniState->ofdmPhyErrBase, 259 aniState->ofdmPhyErrBase,
260 aniState->cckPhyErrBase); 260 aniState->cckPhyErrBase);
@@ -475,7 +475,7 @@ void ath9k_ani_reset(struct ath_hw *ah)
475 475
476 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION 476 if (DO_ANI(ah) && ah->opmode != NL80211_IFTYPE_STATION
477 && ah->opmode != NL80211_IFTYPE_ADHOC) { 477 && ah->opmode != NL80211_IFTYPE_ADHOC) {
478 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 478 DPRINTF(ah, ATH_DBG_ANI,
479 "Reset ANI state opmode %u\n", ah->opmode); 479 "Reset ANI state opmode %u\n", ah->opmode);
480 ah->stats.ast_ani_reset++; 480 ah->stats.ast_ani_reset++;
481 481
@@ -569,7 +569,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
569 if (phyCnt1 < aniState->ofdmPhyErrBase || 569 if (phyCnt1 < aniState->ofdmPhyErrBase ||
570 phyCnt2 < aniState->cckPhyErrBase) { 570 phyCnt2 < aniState->cckPhyErrBase) {
571 if (phyCnt1 < aniState->ofdmPhyErrBase) { 571 if (phyCnt1 < aniState->ofdmPhyErrBase) {
572 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 572 DPRINTF(ah, ATH_DBG_ANI,
573 "phyCnt1 0x%x, resetting " 573 "phyCnt1 0x%x, resetting "
574 "counter value to 0x%x\n", 574 "counter value to 0x%x\n",
575 phyCnt1, aniState->ofdmPhyErrBase); 575 phyCnt1, aniState->ofdmPhyErrBase);
@@ -579,7 +579,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
579 AR_PHY_ERR_OFDM_TIMING); 579 AR_PHY_ERR_OFDM_TIMING);
580 } 580 }
581 if (phyCnt2 < aniState->cckPhyErrBase) { 581 if (phyCnt2 < aniState->cckPhyErrBase) {
582 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 582 DPRINTF(ah, ATH_DBG_ANI,
583 "phyCnt2 0x%x, resetting " 583 "phyCnt2 0x%x, resetting "
584 "counter value to 0x%x\n", 584 "counter value to 0x%x\n",
585 phyCnt2, aniState->cckPhyErrBase); 585 phyCnt2, aniState->cckPhyErrBase);
@@ -624,7 +624,7 @@ void ath9k_hw_ani_monitor(struct ath_hw *ah,
624 624
625void ath9k_enable_mib_counters(struct ath_hw *ah) 625void ath9k_enable_mib_counters(struct ath_hw *ah)
626{ 626{
627 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Enable MIB counters\n"); 627 DPRINTF(ah, ATH_DBG_ANI, "Enable MIB counters\n");
628 628
629 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 629 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
630 630
@@ -640,7 +640,7 @@ void ath9k_enable_mib_counters(struct ath_hw *ah)
640/* Freeze the MIB counters, get the stats and then clear them */ 640/* Freeze the MIB counters, get the stats and then clear them */
641void ath9k_hw_disable_mib_counters(struct ath_hw *ah) 641void ath9k_hw_disable_mib_counters(struct ath_hw *ah)
642{ 642{
643 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disable MIB counters\n"); 643 DPRINTF(ah, ATH_DBG_ANI, "Disable MIB counters\n");
644 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC); 644 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC);
645 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats); 645 ath9k_hw_update_mibstats(ah, &ah->ah_mibStats);
646 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC); 646 REG_WRITE(ah, AR_MIBC, AR_MIBC_CMC);
@@ -662,7 +662,7 @@ u32 ath9k_hw_GetMibCycleCountsPct(struct ath_hw *ah,
662 u32 cc = REG_READ(ah, AR_CCCNT); 662 u32 cc = REG_READ(ah, AR_CCCNT);
663 663
664 if (cycles == 0 || cycles > cc) { 664 if (cycles == 0 || cycles > cc) {
665 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 665 DPRINTF(ah, ATH_DBG_ANI,
666 "cycle counter wrap. ExtBusy = 0\n"); 666 "cycle counter wrap. ExtBusy = 0\n");
667 good = 0; 667 good = 0;
668 } else { 668 } else {
@@ -764,7 +764,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
764{ 764{
765 int i; 765 int i;
766 766
767 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Initialize ANI\n"); 767 DPRINTF(ah, ATH_DBG_ANI, "Initialize ANI\n");
768 768
769 memset(ah->ani, 0, sizeof(ah->ani)); 769 memset(ah->ani, 0, sizeof(ah->ani));
770 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) { 770 for (i = 0; i < ARRAY_SIZE(ah->ani); i++) {
@@ -786,10 +786,10 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
786 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH; 786 AR_PHY_COUNTMAX - ATH9K_ANI_CCK_TRIG_HIGH;
787 } 787 }
788 788
789 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 789 DPRINTF(ah, ATH_DBG_ANI,
790 "Setting OfdmErrBase = 0x%08x\n", 790 "Setting OfdmErrBase = 0x%08x\n",
791 ah->ani[0].ofdmPhyErrBase); 791 ah->ani[0].ofdmPhyErrBase);
792 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n", 792 DPRINTF(ah, ATH_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
793 ah->ani[0].cckPhyErrBase); 793 ah->ani[0].cckPhyErrBase);
794 794
795 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase); 795 REG_WRITE(ah, AR_PHY_ERR_1, ah->ani[0].ofdmPhyErrBase);
@@ -803,7 +803,7 @@ void ath9k_hw_ani_init(struct ath_hw *ah)
803 803
804void ath9k_hw_ani_disable(struct ath_hw *ah) 804void ath9k_hw_ani_disable(struct ath_hw *ah)
805{ 805{
806 DPRINTF(ah->ah_sc, ATH_DBG_ANI, "Disabling ANI\n"); 806 DPRINTF(ah, ATH_DBG_ANI, "Disabling ANI\n");
807 807
808 ath9k_hw_disable_mib_counters(ah); 808 ath9k_hw_disable_mib_counters(ah);
809 REG_WRITE(ah, AR_PHY_ERR_1, 0); 809 REG_WRITE(ah, AR_PHY_ERR_1, 0);
diff --git a/drivers/net/wireless/ath/ath9k/beacon.c b/drivers/net/wireless/ath/ath9k/beacon.c
index 45c4ea57616b..6e7a519d0a9c 100644
--- a/drivers/net/wireless/ath/ath9k/beacon.c
+++ b/drivers/net/wireless/ath/ath9k/beacon.c
@@ -42,7 +42,7 @@ static int ath_beaconq_config(struct ath_softc *sc)
42 } 42 }
43 43
44 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) { 44 if (!ath9k_hw_set_txq_props(ah, sc->beacon.beaconq, &qi)) {
45 DPRINTF(sc, ATH_DBG_FATAL, 45 DPRINTF(ah, ATH_DBG_FATAL,
46 "Unable to update h/w beacon queue parameters\n"); 46 "Unable to update h/w beacon queue parameters\n");
47 return 0; 47 return 0;
48 } else { 48 } else {
@@ -172,7 +172,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
172 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 172 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
173 dev_kfree_skb_any(skb); 173 dev_kfree_skb_any(skb);
174 bf->bf_mpdu = NULL; 174 bf->bf_mpdu = NULL;
175 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error on beaconing\n"); 175 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "dma_mapping_error on beaconing\n");
176 return NULL; 176 return NULL;
177 } 177 }
178 178
@@ -192,7 +192,7 @@ static struct ath_buf *ath_beacon_generate(struct ieee80211_hw *hw,
192 192
193 if (skb && cabq_depth) { 193 if (skb && cabq_depth) {
194 if (sc->nvifs > 1) { 194 if (sc->nvifs > 1) {
195 DPRINTF(sc, ATH_DBG_BEACON, 195 DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
196 "Flushing previous cabq traffic\n"); 196 "Flushing previous cabq traffic\n");
197 ath_draintxq(sc, cabq, false); 197 ath_draintxq(sc, cabq, false);
198 } 198 }
@@ -233,7 +233,7 @@ static void ath_beacon_start_adhoc(struct ath_softc *sc,
233 /* NB: caller is known to have already stopped tx dma */ 233 /* NB: caller is known to have already stopped tx dma */
234 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr); 234 ath9k_hw_puttxbuf(ah, sc->beacon.beaconq, bf->bf_daddr);
235 ath9k_hw_txstart(ah, sc->beacon.beaconq); 235 ath9k_hw_txstart(ah, sc->beacon.beaconq);
236 DPRINTF(sc, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n", 236 DPRINTF(ah, ATH_DBG_BEACON, "TXDP%u = %llx (%p)\n",
237 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc); 237 sc->beacon.beaconq, ito64(bf->bf_daddr), bf->bf_desc);
238} 238}
239 239
@@ -309,7 +309,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
309 /* NB: the beacon data buffer must be 32-bit aligned. */ 309 /* NB: the beacon data buffer must be 32-bit aligned. */
310 skb = ieee80211_beacon_get(sc->hw, vif); 310 skb = ieee80211_beacon_get(sc->hw, vif);
311 if (skb == NULL) { 311 if (skb == NULL) {
312 DPRINTF(sc, ATH_DBG_BEACON, "cannot get skb\n"); 312 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "cannot get skb\n");
313 return -ENOMEM; 313 return -ENOMEM;
314 } 314 }
315 315
@@ -333,7 +333,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
333 tsfadjust = intval * avp->av_bslot / ATH_BCBUF; 333 tsfadjust = intval * avp->av_bslot / ATH_BCBUF;
334 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust)); 334 avp->tsf_adjust = cpu_to_le64(TU_TO_USEC(tsfadjust));
335 335
336 DPRINTF(sc, ATH_DBG_BEACON, 336 DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
337 "stagger beacons, bslot %d intval %u tsfadjust %llu\n", 337 "stagger beacons, bslot %d intval %u tsfadjust %llu\n",
338 avp->av_bslot, intval, (unsigned long long)tsfadjust); 338 avp->av_bslot, intval, (unsigned long long)tsfadjust);
339 339
@@ -349,7 +349,7 @@ int ath_beacon_alloc(struct ath_wiphy *aphy, struct ieee80211_vif *vif)
349 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) { 349 if (unlikely(dma_mapping_error(sc->dev, bf->bf_buf_addr))) {
350 dev_kfree_skb_any(skb); 350 dev_kfree_skb_any(skb);
351 bf->bf_mpdu = NULL; 351 bf->bf_mpdu = NULL;
352 DPRINTF(sc, ATH_DBG_FATAL, 352 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
353 "dma_mapping_error on beacon alloc\n"); 353 "dma_mapping_error on beacon alloc\n");
354 return -ENOMEM; 354 return -ENOMEM;
355 } 355 }
@@ -405,11 +405,11 @@ void ath_beacon_tasklet(unsigned long data)
405 sc->beacon.bmisscnt++; 405 sc->beacon.bmisscnt++;
406 406
407 if (sc->beacon.bmisscnt < BSTUCK_THRESH) { 407 if (sc->beacon.bmisscnt < BSTUCK_THRESH) {
408 DPRINTF(sc, ATH_DBG_BEACON, 408 DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
409 "missed %u consecutive beacons\n", 409 "missed %u consecutive beacons\n",
410 sc->beacon.bmisscnt); 410 sc->beacon.bmisscnt);
411 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) { 411 } else if (sc->beacon.bmisscnt >= BSTUCK_THRESH) {
412 DPRINTF(sc, ATH_DBG_BEACON, 412 DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
413 "beacon is officially stuck\n"); 413 "beacon is officially stuck\n");
414 sc->sc_flags |= SC_OP_TSF_RESET; 414 sc->sc_flags |= SC_OP_TSF_RESET;
415 ath_reset(sc, false); 415 ath_reset(sc, false);
@@ -419,7 +419,7 @@ void ath_beacon_tasklet(unsigned long data)
419 } 419 }
420 420
421 if (sc->beacon.bmisscnt != 0) { 421 if (sc->beacon.bmisscnt != 0) {
422 DPRINTF(sc, ATH_DBG_BEACON, 422 DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
423 "resume beacon xmit after %u misses\n", 423 "resume beacon xmit after %u misses\n",
424 sc->beacon.bmisscnt); 424 sc->beacon.bmisscnt);
425 sc->beacon.bmisscnt = 0; 425 sc->beacon.bmisscnt = 0;
@@ -447,7 +447,7 @@ void ath_beacon_tasklet(unsigned long data)
447 vif = sc->beacon.bslot[slot]; 447 vif = sc->beacon.bslot[slot];
448 aphy = sc->beacon.bslot_aphy[slot]; 448 aphy = sc->beacon.bslot_aphy[slot];
449 449
450 DPRINTF(sc, ATH_DBG_BEACON, 450 DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
451 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n", 451 "slot %d [tsf %llu tsftu %u intval %u] vif %p\n",
452 slot, tsf, tsftu, intval, vif); 452 slot, tsf, tsftu, intval, vif);
453 453
@@ -490,7 +490,7 @@ void ath_beacon_tasklet(unsigned long data)
490 * are still pending on the queue. 490 * are still pending on the queue.
491 */ 491 */
492 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) { 492 if (!ath9k_hw_stoptxdma(ah, sc->beacon.beaconq)) {
493 DPRINTF(sc, ATH_DBG_FATAL, 493 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
494 "beacon queue %u did not stop?\n", sc->beacon.beaconq); 494 "beacon queue %u did not stop?\n", sc->beacon.beaconq);
495 } 495 }
496 496
@@ -651,8 +651,8 @@ static void ath_beacon_config_sta(struct ath_softc *sc,
651 /* TSF out of range threshold fixed at 1 second */ 651 /* TSF out of range threshold fixed at 1 second */
652 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD; 652 bs.bs_tsfoor_threshold = ATH9K_TSFOOR_THRESHOLD;
653 653
654 DPRINTF(sc, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu); 654 DPRINTF(sc->sc_ah, ATH_DBG_BEACON, "tsf: %llu tsftu: %u\n", tsf, tsftu);
655 DPRINTF(sc, ATH_DBG_BEACON, 655 DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
656 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n", 656 "bmiss: %u sleep: %u cfp-period: %u maxdur: %u next: %u\n",
657 bs.bs_bmissthreshold, bs.bs_sleepduration, 657 bs.bs_bmissthreshold, bs.bs_sleepduration,
658 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext); 658 bs.bs_cfpperiod, bs.bs_cfpmaxduration, bs.bs_cfpnext);
@@ -689,7 +689,7 @@ static void ath_beacon_config_adhoc(struct ath_softc *sc,
689 nexttbtt += intval; 689 nexttbtt += intval;
690 } while (nexttbtt < tsftu); 690 } while (nexttbtt < tsftu);
691 691
692 DPRINTF(sc, ATH_DBG_BEACON, 692 DPRINTF(sc->sc_ah, ATH_DBG_BEACON,
693 "IBSS nexttbtt %u intval %u (%u)\n", 693 "IBSS nexttbtt %u intval %u (%u)\n",
694 nexttbtt, intval, conf->beacon_interval); 694 nexttbtt, intval, conf->beacon_interval);
695 695
@@ -759,7 +759,7 @@ void ath_beacon_config(struct ath_softc *sc, struct ieee80211_vif *vif)
759 ath_beacon_config_sta(sc, cur_conf); 759 ath_beacon_config_sta(sc, cur_conf);
760 break; 760 break;
761 default: 761 default:
762 DPRINTF(sc, ATH_DBG_CONFIG, 762 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
763 "Unsupported beaconing mode\n"); 763 "Unsupported beaconing mode\n");
764 return; 764 return;
765 } 765 }
diff --git a/drivers/net/wireless/ath/ath9k/btcoex.c b/drivers/net/wireless/ath/ath9k/btcoex.c
index 55f607b7699e..e19a9c99fb20 100644
--- a/drivers/net/wireless/ath/ath9k/btcoex.c
+++ b/drivers/net/wireless/ath/ath9k/btcoex.c
@@ -56,7 +56,7 @@ static void ath_detect_bt_priority(struct ath_softc *sc)
56 if (time_after(jiffies, btinfo->bt_priority_time + 56 if (time_after(jiffies, btinfo->bt_priority_time +
57 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) { 57 msecs_to_jiffies(ATH_BT_PRIORITY_TIME_THRESHOLD))) {
58 if (btinfo->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) { 58 if (btinfo->bt_priority_cnt >= ATH_BT_CNT_THRESHOLD) {
59 DPRINTF(sc, ATH_DBG_BTCOEX, 59 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX,
60 "BT priority traffic detected"); 60 "BT priority traffic detected");
61 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED; 61 sc->sc_flags |= SC_OP_BT_PRIORITY_DETECTED;
62 } else { 62 } else {
@@ -90,7 +90,7 @@ static void ath_btcoex_bt_stomp(struct ath_softc *sc,
90 AR_STOMP_NONE_WLAN_WGHT); 90 AR_STOMP_NONE_WLAN_WGHT);
91 break; 91 break;
92 default: 92 default:
93 DPRINTF(sc, ATH_DBG_BTCOEX, "Invalid Stomptype\n"); 93 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX, "Invalid Stomptype\n");
94 break; 94 break;
95 } 95 }
96 96
@@ -142,7 +142,7 @@ static void ath_btcoex_no_stomp_timer(void *arg)
142 struct ath_softc *sc = (struct ath_softc *)arg; 142 struct ath_softc *sc = (struct ath_softc *)arg;
143 struct ath_btcoex_info *btinfo = &sc->btcoex_info; 143 struct ath_btcoex_info *btinfo = &sc->btcoex_info;
144 144
145 DPRINTF(sc, ATH_DBG_BTCOEX, "no stomp timer running \n"); 145 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX, "no stomp timer running \n");
146 146
147 spin_lock_bh(&btinfo->btcoex_lock); 147 spin_lock_bh(&btinfo->btcoex_lock);
148 148
@@ -326,7 +326,7 @@ void ath_btcoex_timer_resume(struct ath_softc *sc,
326 struct ath_btcoex_info *btinfo) 326 struct ath_btcoex_info *btinfo)
327{ 327{
328 328
329 DPRINTF(sc, ATH_DBG_BTCOEX, "Starting btcoex timers"); 329 DPRINTF(sc->sc_ah, ATH_DBG_BTCOEX, "Starting btcoex timers");
330 330
331 /* make sure duty cycle timer is also stopped when resuming */ 331 /* make sure duty cycle timer is also stopped when resuming */
332 if (btinfo->hw_timer_enabled) 332 if (btinfo->hw_timer_enabled)
diff --git a/drivers/net/wireless/ath/ath9k/calib.c b/drivers/net/wireless/ath/ath9k/calib.c
index 0ad6d0b76e9e..30106f49322a 100644
--- a/drivers/net/wireless/ath/ath9k/calib.c
+++ b/drivers/net/wireless/ath/ath9k/calib.c
@@ -26,7 +26,7 @@
26static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf) 26static bool ath9k_hw_nf_in_range(struct ath_hw *ah, s16 nf)
27{ 27{
28 if (nf > ATH9K_NF_TOO_LOW) { 28 if (nf > ATH9K_NF_TOO_LOW) {
29 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 29 DPRINTF(ah, ATH_DBG_CALIBRATE,
30 "noise floor value detected (%d) is " 30 "noise floor value detected (%d) is "
31 "lower than what we think is a " 31 "lower than what we think is a "
32 "reasonable value (%d)\n", 32 "reasonable value (%d)\n",
@@ -98,7 +98,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
98 98
99 if (nf & 0x100) 99 if (nf & 0x100)
100 nf = 0 - ((nf ^ 0x1ff) + 1); 100 nf = 0 - ((nf ^ 0x1ff) + 1);
101 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 101 DPRINTF(ah, ATH_DBG_CALIBRATE,
102 "NF calibrated [ctl] [chain 0] is %d\n", nf); 102 "NF calibrated [ctl] [chain 0] is %d\n", nf);
103 nfarray[0] = nf; 103 nfarray[0] = nf;
104 104
@@ -112,7 +112,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
112 112
113 if (nf & 0x100) 113 if (nf & 0x100)
114 nf = 0 - ((nf ^ 0x1ff) + 1); 114 nf = 0 - ((nf ^ 0x1ff) + 1);
115 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 115 DPRINTF(ah, ATH_DBG_CALIBRATE,
116 "NF calibrated [ctl] [chain 1] is %d\n", nf); 116 "NF calibrated [ctl] [chain 1] is %d\n", nf);
117 nfarray[1] = nf; 117 nfarray[1] = nf;
118 118
@@ -121,7 +121,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
121 AR_PHY_CH2_MINCCA_PWR); 121 AR_PHY_CH2_MINCCA_PWR);
122 if (nf & 0x100) 122 if (nf & 0x100)
123 nf = 0 - ((nf ^ 0x1ff) + 1); 123 nf = 0 - ((nf ^ 0x1ff) + 1);
124 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 124 DPRINTF(ah, ATH_DBG_CALIBRATE,
125 "NF calibrated [ctl] [chain 2] is %d\n", nf); 125 "NF calibrated [ctl] [chain 2] is %d\n", nf);
126 nfarray[2] = nf; 126 nfarray[2] = nf;
127 } 127 }
@@ -136,7 +136,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
136 136
137 if (nf & 0x100) 137 if (nf & 0x100)
138 nf = 0 - ((nf ^ 0x1ff) + 1); 138 nf = 0 - ((nf ^ 0x1ff) + 1);
139 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 139 DPRINTF(ah, ATH_DBG_CALIBRATE,
140 "NF calibrated [ext] [chain 0] is %d\n", nf); 140 "NF calibrated [ext] [chain 0] is %d\n", nf);
141 nfarray[3] = nf; 141 nfarray[3] = nf;
142 142
@@ -150,7 +150,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
150 150
151 if (nf & 0x100) 151 if (nf & 0x100)
152 nf = 0 - ((nf ^ 0x1ff) + 1); 152 nf = 0 - ((nf ^ 0x1ff) + 1);
153 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 153 DPRINTF(ah, ATH_DBG_CALIBRATE,
154 "NF calibrated [ext] [chain 1] is %d\n", nf); 154 "NF calibrated [ext] [chain 1] is %d\n", nf);
155 nfarray[4] = nf; 155 nfarray[4] = nf;
156 156
@@ -159,7 +159,7 @@ static void ath9k_hw_do_getnf(struct ath_hw *ah,
159 AR_PHY_CH2_EXT_MINCCA_PWR); 159 AR_PHY_CH2_EXT_MINCCA_PWR);
160 if (nf & 0x100) 160 if (nf & 0x100)
161 nf = 0 - ((nf ^ 0x1ff) + 1); 161 nf = 0 - ((nf ^ 0x1ff) + 1);
162 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 162 DPRINTF(ah, ATH_DBG_CALIBRATE,
163 "NF calibrated [ext] [chain 2] is %d\n", nf); 163 "NF calibrated [ext] [chain 2] is %d\n", nf);
164 nfarray[5] = nf; 164 nfarray[5] = nf;
165 } 165 }
@@ -195,22 +195,22 @@ static void ath9k_hw_setup_calibration(struct ath_hw *ah,
195 switch (currCal->calData->calType) { 195 switch (currCal->calData->calType) {
196 case IQ_MISMATCH_CAL: 196 case IQ_MISMATCH_CAL:
197 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 197 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
198 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 198 DPRINTF(ah, ATH_DBG_CALIBRATE,
199 "starting IQ Mismatch Calibration\n"); 199 "starting IQ Mismatch Calibration\n");
200 break; 200 break;
201 case ADC_GAIN_CAL: 201 case ADC_GAIN_CAL:
202 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN); 202 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
203 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 203 DPRINTF(ah, ATH_DBG_CALIBRATE,
204 "starting ADC Gain Calibration\n"); 204 "starting ADC Gain Calibration\n");
205 break; 205 break;
206 case ADC_DC_CAL: 206 case ADC_DC_CAL:
207 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER); 207 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
208 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 208 DPRINTF(ah, ATH_DBG_CALIBRATE,
209 "starting ADC DC Calibration\n"); 209 "starting ADC DC Calibration\n");
210 break; 210 break;
211 case ADC_DC_INIT_CAL: 211 case ADC_DC_INIT_CAL:
212 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT); 212 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
213 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 213 DPRINTF(ah, ATH_DBG_CALIBRATE,
214 "starting Init ADC DC Calibration\n"); 214 "starting Init ADC DC Calibration\n");
215 break; 215 break;
216 } 216 }
@@ -304,7 +304,7 @@ static void ath9k_hw_iqcal_collect(struct ath_hw *ah)
304 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 304 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
305 ah->totalIqCorrMeas[i] += 305 ah->totalIqCorrMeas[i] +=
306 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 306 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
307 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 307 DPRINTF(ah, ATH_DBG_CALIBRATE,
308 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 308 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
309 ah->cal_samples, i, ah->totalPowerMeasI[i], 309 ah->cal_samples, i, ah->totalPowerMeasI[i],
310 ah->totalPowerMeasQ[i], 310 ah->totalPowerMeasQ[i],
@@ -326,7 +326,7 @@ static void ath9k_hw_adc_gaincal_collect(struct ath_hw *ah)
326 ah->totalAdcQEvenPhase[i] += 326 ah->totalAdcQEvenPhase[i] +=
327 REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 327 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
328 328
329 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 329 DPRINTF(ah, ATH_DBG_CALIBRATE,
330 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 330 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
331 "oddq=0x%08x; evenq=0x%08x;\n", 331 "oddq=0x%08x; evenq=0x%08x;\n",
332 ah->cal_samples, i, 332 ah->cal_samples, i,
@@ -351,7 +351,7 @@ static void ath9k_hw_adc_dccal_collect(struct ath_hw *ah)
351 ah->totalAdcDcOffsetQEvenPhase[i] += 351 ah->totalAdcDcOffsetQEvenPhase[i] +=
352 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i)); 352 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
353 353
354 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 354 DPRINTF(ah, ATH_DBG_CALIBRATE,
355 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; " 355 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
356 "oddq=0x%08x; evenq=0x%08x;\n", 356 "oddq=0x%08x; evenq=0x%08x;\n",
357 ah->cal_samples, i, 357 ah->cal_samples, i,
@@ -374,11 +374,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
374 powerMeasQ = ah->totalPowerMeasQ[i]; 374 powerMeasQ = ah->totalPowerMeasQ[i];
375 iqCorrMeas = ah->totalIqCorrMeas[i]; 375 iqCorrMeas = ah->totalIqCorrMeas[i];
376 376
377 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 377 DPRINTF(ah, ATH_DBG_CALIBRATE,
378 "Starting IQ Cal and Correction for Chain %d\n", 378 "Starting IQ Cal and Correction for Chain %d\n",
379 i); 379 i);
380 380
381 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 381 DPRINTF(ah, ATH_DBG_CALIBRATE,
382 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 382 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
383 i, ah->totalIqCorrMeas[i]); 383 i, ah->totalIqCorrMeas[i]);
384 384
@@ -389,11 +389,11 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
389 iqCorrNeg = 1; 389 iqCorrNeg = 1;
390 } 390 }
391 391
392 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 392 DPRINTF(ah, ATH_DBG_CALIBRATE,
393 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 393 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
394 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 394 DPRINTF(ah, ATH_DBG_CALIBRATE,
395 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 395 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
396 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 396 DPRINTF(ah, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
397 iqCorrNeg); 397 iqCorrNeg);
398 398
399 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128; 399 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
@@ -402,13 +402,13 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
402 if (powerMeasQ != 0) { 402 if (powerMeasQ != 0) {
403 iCoff = iqCorrMeas / iCoffDenom; 403 iCoff = iqCorrMeas / iCoffDenom;
404 qCoff = powerMeasI / qCoffDenom - 64; 404 qCoff = powerMeasI / qCoffDenom - 64;
405 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 405 DPRINTF(ah, ATH_DBG_CALIBRATE,
406 "Chn %d iCoff = 0x%08x\n", i, iCoff); 406 "Chn %d iCoff = 0x%08x\n", i, iCoff);
407 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 407 DPRINTF(ah, ATH_DBG_CALIBRATE,
408 "Chn %d qCoff = 0x%08x\n", i, qCoff); 408 "Chn %d qCoff = 0x%08x\n", i, qCoff);
409 409
410 iCoff = iCoff & 0x3f; 410 iCoff = iCoff & 0x3f;
411 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 411 DPRINTF(ah, ATH_DBG_CALIBRATE,
412 "New: Chn %d iCoff = 0x%08x\n", i, iCoff); 412 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
413 if (iqCorrNeg == 0x0) 413 if (iqCorrNeg == 0x0)
414 iCoff = 0x40 - iCoff; 414 iCoff = 0x40 - iCoff;
@@ -418,7 +418,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
418 else if (qCoff <= -16) 418 else if (qCoff <= -16)
419 qCoff = 16; 419 qCoff = 16;
420 420
421 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 421 DPRINTF(ah, ATH_DBG_CALIBRATE,
422 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", 422 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
423 i, iCoff, qCoff); 423 i, iCoff, qCoff);
424 424
@@ -428,7 +428,7 @@ static void ath9k_hw_iqcalibrate(struct ath_hw *ah, u8 numChains)
428 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i), 428 REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
429 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, 429 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
430 qCoff); 430 qCoff);
431 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 431 DPRINTF(ah, ATH_DBG_CALIBRATE,
432 "IQ Cal and Correction done for Chain %d\n", 432 "IQ Cal and Correction done for Chain %d\n",
433 i); 433 i);
434 } 434 }
@@ -449,19 +449,19 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
449 qOddMeasOffset = ah->totalAdcQOddPhase[i]; 449 qOddMeasOffset = ah->totalAdcQOddPhase[i];
450 qEvenMeasOffset = ah->totalAdcQEvenPhase[i]; 450 qEvenMeasOffset = ah->totalAdcQEvenPhase[i];
451 451
452 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 452 DPRINTF(ah, ATH_DBG_CALIBRATE,
453 "Starting ADC Gain Cal for Chain %d\n", i); 453 "Starting ADC Gain Cal for Chain %d\n", i);
454 454
455 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 455 DPRINTF(ah, ATH_DBG_CALIBRATE,
456 "Chn %d pwr_meas_odd_i = 0x%08x\n", i, 456 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
457 iOddMeasOffset); 457 iOddMeasOffset);
458 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 458 DPRINTF(ah, ATH_DBG_CALIBRATE,
459 "Chn %d pwr_meas_even_i = 0x%08x\n", i, 459 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
460 iEvenMeasOffset); 460 iEvenMeasOffset);
461 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 461 DPRINTF(ah, ATH_DBG_CALIBRATE,
462 "Chn %d pwr_meas_odd_q = 0x%08x\n", i, 462 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
463 qOddMeasOffset); 463 qOddMeasOffset);
464 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 464 DPRINTF(ah, ATH_DBG_CALIBRATE,
465 "Chn %d pwr_meas_even_q = 0x%08x\n", i, 465 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
466 qEvenMeasOffset); 466 qEvenMeasOffset);
467 467
@@ -473,10 +473,10 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
473 ((qOddMeasOffset * 32) / 473 ((qOddMeasOffset * 32) /
474 qEvenMeasOffset) & 0x3f; 474 qEvenMeasOffset) & 0x3f;
475 475
476 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 476 DPRINTF(ah, ATH_DBG_CALIBRATE,
477 "Chn %d gain_mismatch_i = 0x%08x\n", i, 477 "Chn %d gain_mismatch_i = 0x%08x\n", i,
478 iGainMismatch); 478 iGainMismatch);
479 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 479 DPRINTF(ah, ATH_DBG_CALIBRATE,
480 "Chn %d gain_mismatch_q = 0x%08x\n", i, 480 "Chn %d gain_mismatch_q = 0x%08x\n", i,
481 qGainMismatch); 481 qGainMismatch);
482 482
@@ -485,7 +485,7 @@ static void ath9k_hw_adc_gaincal_calibrate(struct ath_hw *ah, u8 numChains)
485 val |= (qGainMismatch) | (iGainMismatch << 6); 485 val |= (qGainMismatch) | (iGainMismatch << 6);
486 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 486 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
487 487
488 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 488 DPRINTF(ah, ATH_DBG_CALIBRATE,
489 "ADC Gain Cal done for Chain %d\n", i); 489 "ADC Gain Cal done for Chain %d\n", i);
490 } 490 }
491 } 491 }
@@ -510,19 +510,19 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
510 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i]; 510 qOddMeasOffset = ah->totalAdcDcOffsetQOddPhase[i];
511 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i]; 511 qEvenMeasOffset = ah->totalAdcDcOffsetQEvenPhase[i];
512 512
513 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 513 DPRINTF(ah, ATH_DBG_CALIBRATE,
514 "Starting ADC DC Offset Cal for Chain %d\n", i); 514 "Starting ADC DC Offset Cal for Chain %d\n", i);
515 515
516 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 516 DPRINTF(ah, ATH_DBG_CALIBRATE,
517 "Chn %d pwr_meas_odd_i = %d\n", i, 517 "Chn %d pwr_meas_odd_i = %d\n", i,
518 iOddMeasOffset); 518 iOddMeasOffset);
519 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 519 DPRINTF(ah, ATH_DBG_CALIBRATE,
520 "Chn %d pwr_meas_even_i = %d\n", i, 520 "Chn %d pwr_meas_even_i = %d\n", i,
521 iEvenMeasOffset); 521 iEvenMeasOffset);
522 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 522 DPRINTF(ah, ATH_DBG_CALIBRATE,
523 "Chn %d pwr_meas_odd_q = %d\n", i, 523 "Chn %d pwr_meas_odd_q = %d\n", i,
524 qOddMeasOffset); 524 qOddMeasOffset);
525 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 525 DPRINTF(ah, ATH_DBG_CALIBRATE,
526 "Chn %d pwr_meas_even_q = %d\n", i, 526 "Chn %d pwr_meas_even_q = %d\n", i,
527 qEvenMeasOffset); 527 qEvenMeasOffset);
528 528
@@ -531,10 +531,10 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
531 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) / 531 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
532 numSamples) & 0x1ff; 532 numSamples) & 0x1ff;
533 533
534 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 534 DPRINTF(ah, ATH_DBG_CALIBRATE,
535 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i, 535 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
536 iDcMismatch); 536 iDcMismatch);
537 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 537 DPRINTF(ah, ATH_DBG_CALIBRATE,
538 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i, 538 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
539 qDcMismatch); 539 qDcMismatch);
540 540
@@ -543,7 +543,7 @@ static void ath9k_hw_adc_dccal_calibrate(struct ath_hw *ah, u8 numChains)
543 val |= (qDcMismatch << 12) | (iDcMismatch << 21); 543 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
544 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val); 544 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
545 545
546 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 546 DPRINTF(ah, ATH_DBG_CALIBRATE,
547 "ADC DC Offset Cal done for Chain %d\n", i); 547 "ADC DC Offset Cal done for Chain %d\n", i);
548 } 548 }
549 549
@@ -568,7 +568,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
568 return true; 568 return true;
569 569
570 if (currCal->calState != CAL_DONE) { 570 if (currCal->calState != CAL_DONE) {
571 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 571 DPRINTF(ah, ATH_DBG_CALIBRATE,
572 "Calibration state incorrect, %d\n", 572 "Calibration state incorrect, %d\n",
573 currCal->calState); 573 currCal->calState);
574 return true; 574 return true;
@@ -577,7 +577,7 @@ bool ath9k_hw_reset_calvalid(struct ath_hw *ah)
577 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType)) 577 if (!ath9k_hw_iscal_supported(ah, currCal->calData->calType))
578 return true; 578 return true;
579 579
580 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 580 DPRINTF(ah, ATH_DBG_CALIBRATE,
581 "Resetting Cal %d state for channel %u\n", 581 "Resetting Cal %d state for channel %u\n",
582 currCal->calData->calType, conf->channel->center_freq); 582 currCal->calData->calType, conf->channel->center_freq);
583 583
@@ -672,7 +672,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
672 672
673 chan->channelFlags &= (~CHANNEL_CW_INT); 673 chan->channelFlags &= (~CHANNEL_CW_INT);
674 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) { 674 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
675 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 675 DPRINTF(ah, ATH_DBG_CALIBRATE,
676 "NF did not complete in calibration window\n"); 676 "NF did not complete in calibration window\n");
677 nf = 0; 677 nf = 0;
678 chan->rawNoiseFloor = nf; 678 chan->rawNoiseFloor = nf;
@@ -682,7 +682,7 @@ int16_t ath9k_hw_getnf(struct ath_hw *ah,
682 nf = nfarray[0]; 682 nf = nfarray[0];
683 if (getNoiseFloorThresh(ah, c->band, &nfThresh) 683 if (getNoiseFloorThresh(ah, c->band, &nfThresh)
684 && nf > nfThresh) { 684 && nf > nfThresh) {
685 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 685 DPRINTF(ah, ATH_DBG_CALIBRATE,
686 "noise floor failed detected; " 686 "noise floor failed detected; "
687 "detected %d, threshold %d\n", 687 "detected %d, threshold %d\n",
688 nf, nfThresh); 688 nf, nfThresh);
@@ -889,7 +889,7 @@ static inline void ath9k_hw_9285_pa_cal(struct ath_hw *ah, bool is_reset)
889 { 0x7838, 0 }, 889 { 0x7838, 0 },
890 }; 890 };
891 891
892 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "Running PA Calibration\n"); 892 DPRINTF(ah, ATH_DBG_CALIBRATE, "Running PA Calibration\n");
893 893
894 /* PA CAL is not needed for high power solution */ 894 /* PA CAL is not needed for high power solution */
895 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) == 895 if (ah->eep_ops->get_eeprom(ah, EEP_TXGAIN_TYPE) ==
@@ -1049,7 +1049,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1049 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 1049 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1050 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, 1050 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL,
1051 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) { 1051 AR_PHY_AGC_CONTROL_CAL, 0, AH_WAIT_TIMEOUT)) {
1052 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset " 1052 DPRINTF(ah, ATH_DBG_CALIBRATE, "offset "
1053 "calibration failed to complete in " 1053 "calibration failed to complete in "
1054 "1ms; noisy ??\n"); 1054 "1ms; noisy ??\n");
1055 return false; 1055 return false;
@@ -1064,7 +1064,7 @@ static bool ar9285_clc(struct ath_hw *ah, struct ath9k_channel *chan)
1064 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); 1064 REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL);
1065 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 1065 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1066 0, AH_WAIT_TIMEOUT)) { 1066 0, AH_WAIT_TIMEOUT)) {
1067 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, "offset calibration " 1067 DPRINTF(ah, ATH_DBG_CALIBRATE, "offset calibration "
1068 "failed to complete in 1ms; noisy ??\n"); 1068 "failed to complete in 1ms; noisy ??\n");
1069 return false; 1069 return false;
1070 } 1070 }
@@ -1098,7 +1098,7 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1098 /* Poll for offset calibration complete */ 1098 /* Poll for offset calibration complete */
1099 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 1099 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL,
1100 0, AH_WAIT_TIMEOUT)) { 1100 0, AH_WAIT_TIMEOUT)) {
1101 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1101 DPRINTF(ah, ATH_DBG_CALIBRATE,
1102 "offset calibration failed to complete in 1ms; " 1102 "offset calibration failed to complete in 1ms; "
1103 "noisy environment?\n"); 1103 "noisy environment?\n");
1104 return false; 1104 return false;
@@ -1128,19 +1128,19 @@ bool ath9k_hw_init_cal(struct ath_hw *ah, struct ath9k_channel *chan)
1128 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) { 1128 if (ath9k_hw_iscal_supported(ah, ADC_GAIN_CAL)) {
1129 INIT_CAL(&ah->adcgain_caldata); 1129 INIT_CAL(&ah->adcgain_caldata);
1130 INSERT_CAL(ah, &ah->adcgain_caldata); 1130 INSERT_CAL(ah, &ah->adcgain_caldata);
1131 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1131 DPRINTF(ah, ATH_DBG_CALIBRATE,
1132 "enabling ADC Gain Calibration.\n"); 1132 "enabling ADC Gain Calibration.\n");
1133 } 1133 }
1134 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) { 1134 if (ath9k_hw_iscal_supported(ah, ADC_DC_CAL)) {
1135 INIT_CAL(&ah->adcdc_caldata); 1135 INIT_CAL(&ah->adcdc_caldata);
1136 INSERT_CAL(ah, &ah->adcdc_caldata); 1136 INSERT_CAL(ah, &ah->adcdc_caldata);
1137 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1137 DPRINTF(ah, ATH_DBG_CALIBRATE,
1138 "enabling ADC DC Calibration.\n"); 1138 "enabling ADC DC Calibration.\n");
1139 } 1139 }
1140 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { 1140 if (ath9k_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) {
1141 INIT_CAL(&ah->iq_caldata); 1141 INIT_CAL(&ah->iq_caldata);
1142 INSERT_CAL(ah, &ah->iq_caldata); 1142 INSERT_CAL(ah, &ah->iq_caldata);
1143 DPRINTF(ah->ah_sc, ATH_DBG_CALIBRATE, 1143 DPRINTF(ah, ATH_DBG_CALIBRATE,
1144 "enabling IQ Calibration.\n"); 1144 "enabling IQ Calibration.\n");
1145 } 1145 }
1146 1146
diff --git a/drivers/net/wireless/ath/ath9k/debug.c b/drivers/net/wireless/ath/ath9k/debug.c
index 2be4c2252047..babfd3780a9a 100644
--- a/drivers/net/wireless/ath/ath9k/debug.c
+++ b/drivers/net/wireless/ath/ath9k/debug.c
@@ -23,12 +23,12 @@ module_param_named(debug, ath9k_debug, uint, 0);
23 23
24static struct dentry *ath9k_debugfs_root; 24static struct dentry *ath9k_debugfs_root;
25 25
26void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...) 26void DPRINTF(struct ath_hw *ah, int dbg_mask, const char *fmt, ...)
27{ 27{
28 if (!sc) 28 if (!ah->ah_sc)
29 return; 29 return;
30 30
31 if (sc->debug.debug_mask & dbg_mask) { 31 if (ah->ah_sc->debug.debug_mask & dbg_mask) {
32 va_list args; 32 va_list args;
33 33
34 va_start(args, fmt); 34 va_start(args, fmt);
@@ -568,8 +568,10 @@ static const struct file_operations fops_xmit = {
568 .owner = THIS_MODULE 568 .owner = THIS_MODULE
569}; 569};
570 570
571int ath9k_init_debug(struct ath_softc *sc) 571int ath9k_init_debug(struct ath_hw *ah)
572{ 572{
573 struct ath_softc *sc = ah->ah_sc;
574
573 sc->debug.debug_mask = ath9k_debug; 575 sc->debug.debug_mask = ath9k_debug;
574 576
575 if (!ath9k_debugfs_root) 577 if (!ath9k_debugfs_root)
@@ -619,12 +621,14 @@ int ath9k_init_debug(struct ath_softc *sc)
619 621
620 return 0; 622 return 0;
621err: 623err:
622 ath9k_exit_debug(sc); 624 ath9k_exit_debug(ah);
623 return -ENOMEM; 625 return -ENOMEM;
624} 626}
625 627
626void ath9k_exit_debug(struct ath_softc *sc) 628void ath9k_exit_debug(struct ath_hw *ah)
627{ 629{
630 struct ath_softc *sc = ah->ah_sc;
631
628 debugfs_remove(sc->debug.debugfs_xmit); 632 debugfs_remove(sc->debug.debugfs_xmit);
629 debugfs_remove(sc->debug.debugfs_wiphy); 633 debugfs_remove(sc->debug.debugfs_wiphy);
630 debugfs_remove(sc->debug.debugfs_rcstat); 634 debugfs_remove(sc->debug.debugfs_rcstat);
diff --git a/drivers/net/wireless/ath/ath9k/debug.h b/drivers/net/wireless/ath/ath9k/debug.h
index 7241f4748338..c9c1aac95aef 100644
--- a/drivers/net/wireless/ath/ath9k/debug.h
+++ b/drivers/net/wireless/ath/ath9k/debug.h
@@ -17,6 +17,8 @@
17#ifndef DEBUG_H 17#ifndef DEBUG_H
18#define DEBUG_H 18#define DEBUG_H
19 19
20#include "hw.h"
21
20enum ATH_DEBUG { 22enum ATH_DEBUG {
21 ATH_DBG_RESET = 0x00000001, 23 ATH_DBG_RESET = 0x00000001,
22 ATH_DBG_QUEUE = 0x00000002, 24 ATH_DBG_QUEUE = 0x00000002,
@@ -151,9 +153,10 @@ struct ath9k_debug {
151 struct ath_stats stats; 153 struct ath_stats stats;
152}; 154};
153 155
154void DPRINTF(struct ath_softc *sc, int dbg_mask, const char *fmt, ...); 156void DPRINTF(struct ath_hw *ah, int dbg_mask, const char *fmt, ...);
155int ath9k_init_debug(struct ath_softc *sc); 157int ath9k_init_debug(struct ath_hw *ah);
156void ath9k_exit_debug(struct ath_softc *sc); 158void ath9k_exit_debug(struct ath_hw *ah);
159
157int ath9k_debug_create_root(void); 160int ath9k_debug_create_root(void);
158void ath9k_debug_remove_root(void); 161void ath9k_debug_remove_root(void);
159void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status); 162void ath_debug_stat_interrupt(struct ath_softc *sc, enum ath9k_int status);
@@ -165,17 +168,17 @@ void ath_debug_stat_retries(struct ath_softc *sc, int rix,
165 168
166#else 169#else
167 170
168static inline void DPRINTF(struct ath_softc *sc, int dbg_mask, 171static inline void DPRINTF(struct ath_hw *ah, int dbg_mask,
169 const char *fmt, ...) 172 const char *fmt, ...)
170{ 173{
171} 174}
172 175
173static inline int ath9k_init_debug(struct ath_softc *sc) 176static inline int ath9k_init_debug(struct ath_hw *ah)
174{ 177{
175 return 0; 178 return 0;
176} 179}
177 180
178static inline void ath9k_exit_debug(struct ath_softc *sc) 181static inline void ath9k_exit_debug(struct ath_hw *ah)
179{ 182{
180} 183}
181 184
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_4k.c b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
index b8eca7be5f3a..0675cd5edf0d 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_4k.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_4k.c
@@ -35,13 +35,13 @@ static bool ath9k_hw_4k_fill_eeprom(struct ath_hw *ah)
35 eep_start_loc = 64; 35 eep_start_loc = 64;
36 36
37 if (!ath9k_hw_use_flash(ah)) { 37 if (!ath9k_hw_use_flash(ah)) {
38 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 38 DPRINTF(ah, ATH_DBG_EEPROM,
39 "Reading from EEPROM, not flash\n"); 39 "Reading from EEPROM, not flash\n");
40 } 40 }
41 41
42 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) { 42 for (addr = 0; addr < SIZE_EEPROM_4K; addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
44 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 44 DPRINTF(ah, ATH_DBG_EEPROM,
45 "Unable to read eeprom region \n"); 45 "Unable to read eeprom region \n");
46 return false; 46 return false;
47 } 47 }
@@ -66,12 +66,12 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
66 if (!ath9k_hw_use_flash(ah)) { 66 if (!ath9k_hw_use_flash(ah)) {
67 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, 67 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
68 &magic)) { 68 &magic)) {
69 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 69 DPRINTF(ah, ATH_DBG_FATAL,
70 "Reading Magic # failed\n"); 70 "Reading Magic # failed\n");
71 return false; 71 return false;
72 } 72 }
73 73
74 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 74 DPRINTF(ah, ATH_DBG_EEPROM,
75 "Read Magic = 0x%04X\n", magic); 75 "Read Magic = 0x%04X\n", magic);
76 76
77 if (magic != AR5416_EEPROM_MAGIC) { 77 if (magic != AR5416_EEPROM_MAGIC) {
@@ -87,7 +87,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
87 eepdata++; 87 eepdata++;
88 } 88 }
89 } else { 89 } else {
90 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 90 DPRINTF(ah, ATH_DBG_FATAL,
91 "Invalid EEPROM Magic. " 91 "Invalid EEPROM Magic. "
92 "endianness mismatch.\n"); 92 "endianness mismatch.\n");
93 return -EINVAL; 93 return -EINVAL;
@@ -95,7 +95,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
95 } 95 }
96 } 96 }
97 97
98 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", 98 DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n",
99 need_swap ? "True" : "False"); 99 need_swap ? "True" : "False");
100 100
101 if (need_swap) 101 if (need_swap)
@@ -117,7 +117,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
117 u32 integer; 117 u32 integer;
118 u16 word; 118 u16 word;
119 119
120 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 120 DPRINTF(ah, ATH_DBG_EEPROM,
121 "EEPROM Endianness is not native.. Changing\n"); 121 "EEPROM Endianness is not native.. Changing\n");
122 122
123 word = swab16(eep->baseEepHeader.length); 123 word = swab16(eep->baseEepHeader.length);
@@ -160,7 +160,7 @@ static int ath9k_hw_4k_check_eeprom(struct ath_hw *ah)
160 160
161 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 161 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
162 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 162 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
163 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 163 DPRINTF(ah, ATH_DBG_FATAL,
164 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 164 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
165 sum, ah->eep_ops->get_eeprom_ver(ah)); 165 sum, ah->eep_ops->get_eeprom_ver(ah));
166 return -EINVAL; 166 return -EINVAL;
@@ -470,11 +470,11 @@ static void ath9k_hw_set_4k_power_cal_table(struct ath_hw *ah,
470 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 470 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
471 REG_WRITE(ah, regOffset, reg32); 471 REG_WRITE(ah, regOffset, reg32);
472 472
473 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 473 DPRINTF(ah, ATH_DBG_EEPROM,
474 "PDADC (%d,%4x): %4.4x %8.8x\n", 474 "PDADC (%d,%4x): %4.4x %8.8x\n",
475 i, regChainOffset, regOffset, 475 i, regChainOffset, regOffset,
476 reg32); 476 reg32);
477 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 477 DPRINTF(ah, ATH_DBG_EEPROM,
478 "PDADC: Chain %d | " 478 "PDADC: Chain %d | "
479 "PDADC %3d Value %3d | " 479 "PDADC %3d Value %3d | "
480 "PDADC %3d Value %3d | " 480 "PDADC %3d Value %3d | "
@@ -1151,7 +1151,7 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1151 1151
1152 u16 spur_val = AR_NO_SPUR; 1152 u16 spur_val = AR_NO_SPUR;
1153 1153
1154 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1154 DPRINTF(ah, ATH_DBG_ANI,
1155 "Getting spur idx %d is2Ghz. %d val %x\n", 1155 "Getting spur idx %d is2Ghz. %d val %x\n",
1156 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1156 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1157 1157
@@ -1160,7 +1160,7 @@ static u16 ath9k_hw_4k_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1160 break; 1160 break;
1161 case SPUR_ENABLE_IOCTL: 1161 case SPUR_ENABLE_IOCTL:
1162 spur_val = ah->config.spurchans[i][is2GHz]; 1162 spur_val = ah->config.spurchans[i][is2GHz];
1163 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1163 DPRINTF(ah, ATH_DBG_ANI,
1164 "Getting spur val from new loc. %d\n", spur_val); 1164 "Getting spur val from new loc. %d\n", spur_val);
1165 break; 1165 break;
1166 case SPUR_ENABLE_EEPROM: 1166 case SPUR_ENABLE_EEPROM:
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_9287.c b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
index c20c21a79b21..c6a4325019d5 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_9287.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_9287.c
@@ -34,14 +34,14 @@ static bool ath9k_hw_AR9287_fill_eeprom(struct ath_hw *ah)
34 eep_data = (u16 *)eep; 34 eep_data = (u16 *)eep;
35 35
36 if (!ath9k_hw_use_flash(ah)) { 36 if (!ath9k_hw_use_flash(ah)) {
37 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 37 DPRINTF(ah, ATH_DBG_EEPROM,
38 "Reading from EEPROM, not flash\n"); 38 "Reading from EEPROM, not flash\n");
39 } 39 }
40 40
41 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16); 41 for (addr = 0; addr < sizeof(struct ar9287_eeprom) / sizeof(u16);
42 addr++) { 42 addr++) {
43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) { 43 if (!ath9k_hw_nvram_read(ah, addr + eep_start_loc, eep_data)) {
44 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 44 DPRINTF(ah, ATH_DBG_EEPROM,
45 "Unable to read eeprom region \n"); 45 "Unable to read eeprom region \n");
46 return false; 46 return false;
47 } 47 }
@@ -61,12 +61,12 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
61 if (!ath9k_hw_use_flash(ah)) { 61 if (!ath9k_hw_use_flash(ah)) {
62 if (!ath9k_hw_nvram_read 62 if (!ath9k_hw_nvram_read
63 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 63 (ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
64 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 64 DPRINTF(ah, ATH_DBG_FATAL,
65 "Reading Magic # failed\n"); 65 "Reading Magic # failed\n");
66 return false; 66 return false;
67 } 67 }
68 68
69 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 69 DPRINTF(ah, ATH_DBG_EEPROM,
70 "Read Magic = 0x%04X\n", magic); 70 "Read Magic = 0x%04X\n", magic);
71 if (magic != AR5416_EEPROM_MAGIC) { 71 if (magic != AR5416_EEPROM_MAGIC) {
72 magic2 = swab16(magic); 72 magic2 = swab16(magic);
@@ -83,14 +83,14 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
83 eepdata++; 83 eepdata++;
84 } 84 }
85 } else { 85 } else {
86 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 86 DPRINTF(ah, ATH_DBG_FATAL,
87 "Invalid EEPROM Magic. " 87 "Invalid EEPROM Magic. "
88 "endianness mismatch.\n"); 88 "endianness mismatch.\n");
89 return -EINVAL; 89 return -EINVAL;
90 } 90 }
91 } 91 }
92 } 92 }
93 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ? 93 DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n", need_swap ?
94 "True" : "False"); 94 "True" : "False");
95 95
96 if (need_swap) 96 if (need_swap)
@@ -148,7 +148,7 @@ static int ath9k_hw_AR9287_check_eeprom(struct ath_hw *ah)
148 148
149 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER 149 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR9287_EEP_VER
150 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 150 || ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
151 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 151 DPRINTF(ah, ATH_DBG_FATAL,
152 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 152 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
153 sum, ah->eep_ops->get_eeprom_ver(ah)); 153 sum, ah->eep_ops->get_eeprom_ver(ah));
154 return -EINVAL; 154 return -EINVAL;
@@ -564,12 +564,12 @@ static void ath9k_hw_set_AR9287_power_cal_table(struct ath_hw *ah,
564 & 0xFF) << 24) ; 564 & 0xFF) << 24) ;
565 REG_WRITE(ah, regOffset, reg32); 565 REG_WRITE(ah, regOffset, reg32);
566 566
567 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 567 DPRINTF(ah, ATH_DBG_EEPROM,
568 "PDADC (%d,%4x): %4.4x %8.8x\n", 568 "PDADC (%d,%4x): %4.4x %8.8x\n",
569 i, regChainOffset, regOffset, 569 i, regChainOffset, regOffset,
570 reg32); 570 reg32);
571 571
572 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 572 DPRINTF(ah, ATH_DBG_EEPROM,
573 "PDADC: Chain %d | " 573 "PDADC: Chain %d | "
574 "PDADC %3d Value %3d | " 574 "PDADC %3d Value %3d | "
575 "PDADC %3d Value %3d | " 575 "PDADC %3d Value %3d | "
@@ -966,7 +966,7 @@ static void ath9k_hw_AR9287_set_txpower(struct ath_hw *ah,
966 INCREASE_MAXPOW_BY_THREE_CHAIN; 966 INCREASE_MAXPOW_BY_THREE_CHAIN;
967 break; 967 break;
968 default: 968 default:
969 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 969 DPRINTF(ah, ATH_DBG_EEPROM,
970 "Invalid chainmask configuration\n"); 970 "Invalid chainmask configuration\n");
971 break; 971 break;
972 } 972 }
@@ -1140,7 +1140,7 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
1140 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan) 1140 (ah->eeprom.map9287.modalHeader.spurChans[i].spurChan)
1141 u16 spur_val = AR_NO_SPUR; 1141 u16 spur_val = AR_NO_SPUR;
1142 1142
1143 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1143 DPRINTF(ah, ATH_DBG_ANI,
1144 "Getting spur idx %d is2Ghz. %d val %x\n", 1144 "Getting spur idx %d is2Ghz. %d val %x\n",
1145 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1145 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1146 1146
@@ -1149,7 +1149,7 @@ static u16 ath9k_hw_AR9287_get_spur_channel(struct ath_hw *ah,
1149 break; 1149 break;
1150 case SPUR_ENABLE_IOCTL: 1150 case SPUR_ENABLE_IOCTL:
1151 spur_val = ah->config.spurchans[i][is2GHz]; 1151 spur_val = ah->config.spurchans[i][is2GHz];
1152 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1152 DPRINTF(ah, ATH_DBG_ANI,
1153 "Getting spur val from new loc. %d\n", spur_val); 1153 "Getting spur val from new loc. %d\n", spur_val);
1154 break; 1154 break;
1155 case SPUR_ENABLE_EEPROM: 1155 case SPUR_ENABLE_EEPROM:
diff --git a/drivers/net/wireless/ath/ath9k/eeprom_def.c b/drivers/net/wireless/ath/ath9k/eeprom_def.c
index 4071fc91da0a..8a7fc3962a16 100644
--- a/drivers/net/wireless/ath/ath9k/eeprom_def.c
+++ b/drivers/net/wireless/ath/ath9k/eeprom_def.c
@@ -95,7 +95,7 @@ static bool ath9k_hw_def_fill_eeprom(struct ath_hw *ah)
95 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) { 95 for (addr = 0; addr < SIZE_EEPROM_DEF; addr++) {
96 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc, 96 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
97 eep_data)) { 97 eep_data)) {
98 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 98 DPRINTF(ah, ATH_DBG_FATAL,
99 "Unable to read eeprom region\n"); 99 "Unable to read eeprom region\n");
100 return false; 100 return false;
101 } 101 }
@@ -115,12 +115,12 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
115 int i, addr, size; 115 int i, addr, size;
116 116
117 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) { 117 if (!ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET, &magic)) {
118 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Reading Magic # failed\n"); 118 DPRINTF(ah, ATH_DBG_FATAL, "Reading Magic # failed\n");
119 return false; 119 return false;
120 } 120 }
121 121
122 if (!ath9k_hw_use_flash(ah)) { 122 if (!ath9k_hw_use_flash(ah)) {
123 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 123 DPRINTF(ah, ATH_DBG_EEPROM,
124 "Read Magic = 0x%04X\n", magic); 124 "Read Magic = 0x%04X\n", magic);
125 125
126 if (magic != AR5416_EEPROM_MAGIC) { 126 if (magic != AR5416_EEPROM_MAGIC) {
@@ -137,7 +137,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
137 eepdata++; 137 eepdata++;
138 } 138 }
139 } else { 139 } else {
140 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 140 DPRINTF(ah, ATH_DBG_FATAL,
141 "Invalid EEPROM Magic. " 141 "Invalid EEPROM Magic. "
142 "Endianness mismatch.\n"); 142 "Endianness mismatch.\n");
143 return -EINVAL; 143 return -EINVAL;
@@ -145,7 +145,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
145 } 145 }
146 } 146 }
147 147
148 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, "need_swap = %s.\n", 148 DPRINTF(ah, ATH_DBG_EEPROM, "need_swap = %s.\n",
149 need_swap ? "True" : "False"); 149 need_swap ? "True" : "False");
150 150
151 if (need_swap) 151 if (need_swap)
@@ -167,7 +167,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
167 u32 integer, j; 167 u32 integer, j;
168 u16 word; 168 u16 word;
169 169
170 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 170 DPRINTF(ah, ATH_DBG_EEPROM,
171 "EEPROM Endianness is not native.. Changing.\n"); 171 "EEPROM Endianness is not native.. Changing.\n");
172 172
173 word = swab16(eep->baseEepHeader.length); 173 word = swab16(eep->baseEepHeader.length);
@@ -214,7 +214,7 @@ static int ath9k_hw_def_check_eeprom(struct ath_hw *ah)
214 214
215 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER || 215 if (sum != 0xffff || ah->eep_ops->get_eeprom_ver(ah) != AR5416_EEP_VER ||
216 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) { 216 ah->eep_ops->get_eeprom_rev(ah) < AR5416_EEP_NO_BACK_VER) {
217 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 217 DPRINTF(ah, ATH_DBG_FATAL,
218 "Bad EEPROM checksum 0x%x or revision 0x%04x\n", 218 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
219 sum, ah->eep_ops->get_eeprom_ver(ah)); 219 sum, ah->eep_ops->get_eeprom_ver(ah));
220 return -EINVAL; 220 return -EINVAL;
@@ -870,11 +870,11 @@ static void ath9k_hw_set_def_power_cal_table(struct ath_hw *ah,
870 ((pdadcValues[4 * j + 3] & 0xFF) << 24); 870 ((pdadcValues[4 * j + 3] & 0xFF) << 24);
871 REG_WRITE(ah, regOffset, reg32); 871 REG_WRITE(ah, regOffset, reg32);
872 872
873 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 873 DPRINTF(ah, ATH_DBG_EEPROM,
874 "PDADC (%d,%4x): %4.4x %8.8x\n", 874 "PDADC (%d,%4x): %4.4x %8.8x\n",
875 i, regChainOffset, regOffset, 875 i, regChainOffset, regOffset,
876 reg32); 876 reg32);
877 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 877 DPRINTF(ah, ATH_DBG_EEPROM,
878 "PDADC: Chain %d | PDADC %3d " 878 "PDADC: Chain %d | PDADC %3d "
879 "Value %3d | PDADC %3d Value %3d | " 879 "Value %3d | PDADC %3d Value %3d | "
880 "PDADC %3d Value %3d | PDADC %3d " 880 "PDADC %3d Value %3d | PDADC %3d "
@@ -1311,7 +1311,7 @@ static void ath9k_hw_def_set_txpower(struct ath_hw *ah,
1311 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN; 1311 regulatory->max_power_level += INCREASE_MAXPOW_BY_THREE_CHAIN;
1312 break; 1312 break;
1313 default: 1313 default:
1314 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1314 DPRINTF(ah, ATH_DBG_EEPROM,
1315 "Invalid chainmask configuration\n"); 1315 "Invalid chainmask configuration\n");
1316 break; 1316 break;
1317 } 1317 }
@@ -1352,7 +1352,7 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1352 1352
1353 u16 spur_val = AR_NO_SPUR; 1353 u16 spur_val = AR_NO_SPUR;
1354 1354
1355 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1355 DPRINTF(ah, ATH_DBG_ANI,
1356 "Getting spur idx %d is2Ghz. %d val %x\n", 1356 "Getting spur idx %d is2Ghz. %d val %x\n",
1357 i, is2GHz, ah->config.spurchans[i][is2GHz]); 1357 i, is2GHz, ah->config.spurchans[i][is2GHz]);
1358 1358
@@ -1361,7 +1361,7 @@ static u16 ath9k_hw_def_get_spur_channel(struct ath_hw *ah, u16 i, bool is2GHz)
1361 break; 1361 break;
1362 case SPUR_ENABLE_IOCTL: 1362 case SPUR_ENABLE_IOCTL:
1363 spur_val = ah->config.spurchans[i][is2GHz]; 1363 spur_val = ah->config.spurchans[i][is2GHz];
1364 DPRINTF(ah->ah_sc, ATH_DBG_ANI, 1364 DPRINTF(ah, ATH_DBG_ANI,
1365 "Getting spur val from new loc. %d\n", spur_val); 1365 "Getting spur val from new loc. %d\n", spur_val);
1366 break; 1366 break;
1367 case SPUR_ENABLE_EEPROM: 1367 case SPUR_ENABLE_EEPROM:
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index ca7694caf364..0342091dfe7d 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -126,7 +126,7 @@ bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
126 udelay(AH_TIME_QUANTUM); 126 udelay(AH_TIME_QUANTUM);
127 } 127 }
128 128
129 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 129 DPRINTF(ah, ATH_DBG_ANY,
130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n", 130 "timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
131 timeout, reg, REG_READ(ah, reg), mask, val); 131 timeout, reg, REG_READ(ah, reg), mask, val);
132 132
@@ -210,7 +210,7 @@ u16 ath9k_hw_computetxtime(struct ath_hw *ah,
210 } 210 }
211 break; 211 break;
212 default: 212 default:
213 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 213 DPRINTF(ah, ATH_DBG_FATAL,
214 "Unknown phy %u (rate ix %u)\n", 214 "Unknown phy %u (rate ix %u)\n",
215 rates->info[rateix].phy, rateix); 215 rates->info[rateix].phy, rateix);
216 txTime = 0; 216 txTime = 0;
@@ -335,7 +335,7 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
335 REG_WRITE(ah, addr, wrData); 335 REG_WRITE(ah, addr, wrData);
336 rdData = REG_READ(ah, addr); 336 rdData = REG_READ(ah, addr);
337 if (rdData != wrData) { 337 if (rdData != wrData) {
338 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 338 DPRINTF(ah, ATH_DBG_FATAL,
339 "address test failed " 339 "address test failed "
340 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 340 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
341 addr, wrData, rdData); 341 addr, wrData, rdData);
@@ -347,7 +347,7 @@ static bool ath9k_hw_chip_test(struct ath_hw *ah)
347 REG_WRITE(ah, addr, wrData); 347 REG_WRITE(ah, addr, wrData);
348 rdData = REG_READ(ah, addr); 348 rdData = REG_READ(ah, addr);
349 if (wrData != rdData) { 349 if (wrData != rdData) {
350 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 350 DPRINTF(ah, ATH_DBG_FATAL,
351 "address test failed " 351 "address test failed "
352 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n", 352 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
353 addr, wrData, rdData); 353 addr, wrData, rdData);
@@ -472,7 +472,7 @@ static int ath9k_hw_rfattach(struct ath_hw *ah)
472 472
473 rfStatus = ath9k_hw_init_rf(ah, &ecode); 473 rfStatus = ath9k_hw_init_rf(ah, &ecode);
474 if (!rfStatus) { 474 if (!rfStatus) {
475 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 475 DPRINTF(ah, ATH_DBG_FATAL,
476 "RF setup failed, status: %u\n", ecode); 476 "RF setup failed, status: %u\n", ecode);
477 return ecode; 477 return ecode;
478 } 478 }
@@ -497,7 +497,7 @@ static int ath9k_hw_rf_claim(struct ath_hw *ah)
497 case AR_RAD2122_SREV_MAJOR: 497 case AR_RAD2122_SREV_MAJOR:
498 break; 498 break;
499 default: 499 default:
500 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 500 DPRINTF(ah, ATH_DBG_FATAL,
501 "Radio Chip Rev 0x%02X not supported\n", 501 "Radio Chip Rev 0x%02X not supported\n",
502 val & AR_RADIO_SREV_MAJOR); 502 val & AR_RADIO_SREV_MAJOR);
503 return -EOPNOTSUPP; 503 return -EOPNOTSUPP;
@@ -590,7 +590,7 @@ static int ath9k_hw_post_init(struct ath_hw *ah)
590 if (ecode != 0) 590 if (ecode != 0)
591 return ecode; 591 return ecode;
592 592
593 DPRINTF(ah->ah_sc, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n", 593 DPRINTF(ah, ATH_DBG_CONFIG, "Eeprom VER: %d, REV: %d\n",
594 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah)); 594 ah->eep_ops->get_eeprom_ver(ah), ah->eep_ops->get_eeprom_rev(ah));
595 595
596 ecode = ath9k_hw_rfattach(ah); 596 ecode = ath9k_hw_rfattach(ah);
@@ -914,12 +914,12 @@ int ath9k_hw_init(struct ath_hw *ah)
914 ath9k_hw_init_config(ah); 914 ath9k_hw_init_config(ah);
915 915
916 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) { 916 if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
917 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't reset chip\n"); 917 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't reset chip\n");
918 return -EIO; 918 return -EIO;
919 } 919 }
920 920
921 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) { 921 if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
922 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Couldn't wakeup chip\n"); 922 DPRINTF(ah, ATH_DBG_FATAL, "Couldn't wakeup chip\n");
923 return -EIO; 923 return -EIO;
924 } 924 }
925 925
@@ -934,11 +934,11 @@ int ath9k_hw_init(struct ath_hw *ah)
934 } 934 }
935 } 935 }
936 936
937 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "serialize_regmode is %d\n", 937 DPRINTF(ah, ATH_DBG_RESET, "serialize_regmode is %d\n",
938 ah->config.serialize_regmode); 938 ah->config.serialize_regmode);
939 939
940 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) { 940 if (!ath9k_hw_macversion_supported(ah->hw_version.macVersion)) {
941 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 941 DPRINTF(ah, ATH_DBG_FATAL,
942 "Mac Chip Rev 0x%02x.%x is not supported by " 942 "Mac Chip Rev 0x%02x.%x is not supported by "
943 "this driver\n", ah->hw_version.macVersion, 943 "this driver\n", ah->hw_version.macVersion,
944 ah->hw_version.macRev); 944 ah->hw_version.macRev);
@@ -979,7 +979,7 @@ int ath9k_hw_init(struct ath_hw *ah)
979 979
980 r = ath9k_hw_init_macaddr(ah); 980 r = ath9k_hw_init_macaddr(ah);
981 if (r) { 981 if (r) {
982 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 982 DPRINTF(ah, ATH_DBG_FATAL,
983 "Failed to initialize MAC address\n"); 983 "Failed to initialize MAC address\n");
984 return r; 984 return r;
985 } 985 }
@@ -1164,7 +1164,7 @@ static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
1164static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us) 1164static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1165{ 1165{
1166 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) { 1166 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
1167 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad ack timeout %u\n", us); 1167 DPRINTF(ah, ATH_DBG_RESET, "bad ack timeout %u\n", us);
1168 ah->acktimeout = (u32) -1; 1168 ah->acktimeout = (u32) -1;
1169 return false; 1169 return false;
1170 } else { 1170 } else {
@@ -1178,7 +1178,7 @@ static bool ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1178static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us) 1178static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1179{ 1179{
1180 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) { 1180 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
1181 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad cts timeout %u\n", us); 1181 DPRINTF(ah, ATH_DBG_RESET, "bad cts timeout %u\n", us);
1182 ah->ctstimeout = (u32) -1; 1182 ah->ctstimeout = (u32) -1;
1183 return false; 1183 return false;
1184 } else { 1184 } else {
@@ -1192,7 +1192,7 @@ static bool ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1192static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu) 1192static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1193{ 1193{
1194 if (tu > 0xFFFF) { 1194 if (tu > 0xFFFF) {
1195 DPRINTF(ah->ah_sc, ATH_DBG_XMIT, 1195 DPRINTF(ah, ATH_DBG_XMIT,
1196 "bad global tx timeout %u\n", tu); 1196 "bad global tx timeout %u\n", tu);
1197 ah->globaltxtimeout = (u32) -1; 1197 ah->globaltxtimeout = (u32) -1;
1198 return false; 1198 return false;
@@ -1205,7 +1205,7 @@ static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1205 1205
1206static void ath9k_hw_init_user_settings(struct ath_hw *ah) 1206static void ath9k_hw_init_user_settings(struct ath_hw *ah)
1207{ 1207{
1208 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "ah->misc_mode 0x%x\n", 1208 DPRINTF(ah, ATH_DBG_RESET, "ah->misc_mode 0x%x\n",
1209 ah->misc_mode); 1209 ah->misc_mode);
1210 1210
1211 if (ah->misc_mode != 0) 1211 if (ah->misc_mode != 0)
@@ -1302,23 +1302,23 @@ static u32 ath9k_hw_def_ini_fixup(struct ath_hw *ah,
1302 switch (ah->hw_version.devid) { 1302 switch (ah->hw_version.devid) {
1303 case AR9280_DEVID_PCI: 1303 case AR9280_DEVID_PCI:
1304 if (reg == 0x7894) { 1304 if (reg == 0x7894) {
1305 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1305 DPRINTF(ah, ATH_DBG_EEPROM,
1306 "ini VAL: %x EEPROM: %x\n", value, 1306 "ini VAL: %x EEPROM: %x\n", value,
1307 (pBase->version & 0xff)); 1307 (pBase->version & 0xff));
1308 1308
1309 if ((pBase->version & 0xff) > 0x0a) { 1309 if ((pBase->version & 0xff) > 0x0a) {
1310 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1310 DPRINTF(ah, ATH_DBG_EEPROM,
1311 "PWDCLKIND: %d\n", 1311 "PWDCLKIND: %d\n",
1312 pBase->pwdclkind); 1312 pBase->pwdclkind);
1313 value &= ~AR_AN_TOP2_PWDCLKIND; 1313 value &= ~AR_AN_TOP2_PWDCLKIND;
1314 value |= AR_AN_TOP2_PWDCLKIND & 1314 value |= AR_AN_TOP2_PWDCLKIND &
1315 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S); 1315 (pBase->pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
1316 } else { 1316 } else {
1317 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1317 DPRINTF(ah, ATH_DBG_EEPROM,
1318 "PWDCLKIND Earlier Rev\n"); 1318 "PWDCLKIND Earlier Rev\n");
1319 } 1319 }
1320 1320
1321 DPRINTF(ah->ah_sc, ATH_DBG_EEPROM, 1321 DPRINTF(ah, ATH_DBG_EEPROM,
1322 "final ini VAL: %x\n", value); 1322 "final ini VAL: %x\n", value);
1323 } 1323 }
1324 break; 1324 break;
@@ -1491,7 +1491,7 @@ static int ath9k_hw_process_ini(struct ath_hw *ah,
1491 (u32) regulatory->power_limit)); 1491 (u32) regulatory->power_limit));
1492 1492
1493 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) { 1493 if (!ath9k_hw_set_rf_regs(ah, chan, freqIndex)) {
1494 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1494 DPRINTF(ah, ATH_DBG_FATAL,
1495 "ar5416SetRfRegs failed\n"); 1495 "ar5416SetRfRegs failed\n");
1496 return -EIO; 1496 return -EIO;
1497 } 1497 }
@@ -1697,7 +1697,7 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1697 1697
1698 REG_WRITE(ah, AR_RTC_RC, 0); 1698 REG_WRITE(ah, AR_RTC_RC, 0);
1699 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) { 1699 if (!ath9k_hw_wait(ah, AR_RTC_RC, AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1700 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 1700 DPRINTF(ah, ATH_DBG_RESET,
1701 "RTC stuck in MAC reset\n"); 1701 "RTC stuck in MAC reset\n");
1702 return false; 1702 return false;
1703 } 1703 }
@@ -1734,7 +1734,7 @@ static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1734 AR_RTC_STATUS_M, 1734 AR_RTC_STATUS_M,
1735 AR_RTC_STATUS_ON, 1735 AR_RTC_STATUS_ON,
1736 AH_WAIT_TIMEOUT)) { 1736 AH_WAIT_TIMEOUT)) {
1737 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "RTC not waking up\n"); 1737 DPRINTF(ah, ATH_DBG_RESET, "RTC not waking up\n");
1738 return false; 1738 return false;
1739 } 1739 }
1740 1740
@@ -1819,7 +1819,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1819 1819
1820 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) { 1820 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1821 if (ath9k_hw_numtxpending(ah, qnum)) { 1821 if (ath9k_hw_numtxpending(ah, qnum)) {
1822 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 1822 DPRINTF(ah, ATH_DBG_QUEUE,
1823 "Transmit frames pending on queue %d\n", qnum); 1823 "Transmit frames pending on queue %d\n", qnum);
1824 return false; 1824 return false;
1825 } 1825 }
@@ -1828,7 +1828,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1828 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN); 1828 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
1829 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN, 1829 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
1830 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) { 1830 AR_PHY_RFBUS_GRANT_EN, AH_WAIT_TIMEOUT)) {
1831 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1831 DPRINTF(ah, ATH_DBG_FATAL,
1832 "Could not kill baseband RX\n"); 1832 "Could not kill baseband RX\n");
1833 return false; 1833 return false;
1834 } 1834 }
@@ -1839,7 +1839,7 @@ static bool ath9k_hw_channel_change(struct ath_hw *ah,
1839 ath9k_hw_ar9280_set_channel(ah, chan); 1839 ath9k_hw_ar9280_set_channel(ah, chan);
1840 } else { 1840 } else {
1841 if (!(ath9k_hw_set_channel(ah, chan))) { 1841 if (!(ath9k_hw_set_channel(ah, chan))) {
1842 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 1842 DPRINTF(ah, ATH_DBG_FATAL,
1843 "Failed to set channel\n"); 1843 "Failed to set channel\n");
1844 return false; 1844 return false;
1845 } 1845 }
@@ -2400,7 +2400,7 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2400 } 2400 }
2401 2401
2402 if (!ath9k_hw_chip_reset(ah, chan)) { 2402 if (!ath9k_hw_chip_reset(ah, chan)) {
2403 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Chip reset failed\n"); 2403 DPRINTF(ah, ATH_DBG_FATAL, "Chip reset failed\n");
2404 return -EINVAL; 2404 return -EINVAL;
2405 } 2405 }
2406 2406
@@ -2558,13 +2558,13 @@ int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
2558 u32 mask; 2558 u32 mask;
2559 mask = REG_READ(ah, AR_CFG); 2559 mask = REG_READ(ah, AR_CFG);
2560 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) { 2560 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
2561 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2561 DPRINTF(ah, ATH_DBG_RESET,
2562 "CFG Byte Swap Set 0x%x\n", mask); 2562 "CFG Byte Swap Set 0x%x\n", mask);
2563 } else { 2563 } else {
2564 mask = 2564 mask =
2565 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB; 2565 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
2566 REG_WRITE(ah, AR_CFG, mask); 2566 REG_WRITE(ah, AR_CFG, mask);
2567 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 2567 DPRINTF(ah, ATH_DBG_RESET,
2568 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG)); 2568 "Setting CFG 0x%x\n", REG_READ(ah, AR_CFG));
2569 } 2569 }
2570 } else { 2570 } else {
@@ -2592,7 +2592,7 @@ bool ath9k_hw_keyreset(struct ath_hw *ah, u16 entry)
2592 u32 keyType; 2592 u32 keyType;
2593 2593
2594 if (entry >= ah->caps.keycache_size) { 2594 if (entry >= ah->caps.keycache_size) {
2595 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2595 DPRINTF(ah, ATH_DBG_FATAL,
2596 "keychache entry %u out of range\n", entry); 2596 "keychache entry %u out of range\n", entry);
2597 return false; 2597 return false;
2598 } 2598 }
@@ -2626,7 +2626,7 @@ bool ath9k_hw_keysetmac(struct ath_hw *ah, u16 entry, const u8 *mac)
2626 u32 macHi, macLo; 2626 u32 macHi, macLo;
2627 2627
2628 if (entry >= ah->caps.keycache_size) { 2628 if (entry >= ah->caps.keycache_size) {
2629 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2629 DPRINTF(ah, ATH_DBG_FATAL,
2630 "keychache entry %u out of range\n", entry); 2630 "keychache entry %u out of range\n", entry);
2631 return false; 2631 return false;
2632 } 2632 }
@@ -2658,7 +2658,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2658 u32 keyType; 2658 u32 keyType;
2659 2659
2660 if (entry >= pCap->keycache_size) { 2660 if (entry >= pCap->keycache_size) {
2661 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2661 DPRINTF(ah, ATH_DBG_FATAL,
2662 "keycache entry %u out of range\n", entry); 2662 "keycache entry %u out of range\n", entry);
2663 return false; 2663 return false;
2664 } 2664 }
@@ -2669,7 +2669,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2669 break; 2669 break;
2670 case ATH9K_CIPHER_AES_CCM: 2670 case ATH9K_CIPHER_AES_CCM:
2671 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) { 2671 if (!(pCap->hw_caps & ATH9K_HW_CAP_CIPHER_AESCCM)) {
2672 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2672 DPRINTF(ah, ATH_DBG_ANY,
2673 "AES-CCM not supported by mac rev 0x%x\n", 2673 "AES-CCM not supported by mac rev 0x%x\n",
2674 ah->hw_version.macRev); 2674 ah->hw_version.macRev);
2675 return false; 2675 return false;
@@ -2680,14 +2680,14 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2680 keyType = AR_KEYTABLE_TYPE_TKIP; 2680 keyType = AR_KEYTABLE_TYPE_TKIP;
2681 if (ATH9K_IS_MIC_ENABLED(ah) 2681 if (ATH9K_IS_MIC_ENABLED(ah)
2682 && entry + 64 >= pCap->keycache_size) { 2682 && entry + 64 >= pCap->keycache_size) {
2683 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2683 DPRINTF(ah, ATH_DBG_ANY,
2684 "entry %u inappropriate for TKIP\n", entry); 2684 "entry %u inappropriate for TKIP\n", entry);
2685 return false; 2685 return false;
2686 } 2686 }
2687 break; 2687 break;
2688 case ATH9K_CIPHER_WEP: 2688 case ATH9K_CIPHER_WEP:
2689 if (k->kv_len < WLAN_KEY_LEN_WEP40) { 2689 if (k->kv_len < WLAN_KEY_LEN_WEP40) {
2690 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 2690 DPRINTF(ah, ATH_DBG_ANY,
2691 "WEP key length %u too small\n", k->kv_len); 2691 "WEP key length %u too small\n", k->kv_len);
2692 return false; 2692 return false;
2693 } 2693 }
@@ -2702,7 +2702,7 @@ bool ath9k_hw_set_keycache_entry(struct ath_hw *ah, u16 entry,
2702 keyType = AR_KEYTABLE_TYPE_CLR; 2702 keyType = AR_KEYTABLE_TYPE_CLR;
2703 break; 2703 break;
2704 default: 2704 default:
2705 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2705 DPRINTF(ah, ATH_DBG_FATAL,
2706 "cipher %u not supported\n", k->kv_type); 2706 "cipher %u not supported\n", k->kv_type);
2707 return false; 2707 return false;
2708 } 2708 }
@@ -2920,7 +2920,7 @@ static bool ath9k_hw_set_power_awake(struct ath_hw *ah, int setChip)
2920 AR_RTC_FORCE_WAKE_EN); 2920 AR_RTC_FORCE_WAKE_EN);
2921 } 2921 }
2922 if (i == 0) { 2922 if (i == 0) {
2923 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2923 DPRINTF(ah, ATH_DBG_FATAL,
2924 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20); 2924 "Failed to wakeup in %uus\n", POWER_UP_TIME / 20);
2925 return false; 2925 return false;
2926 } 2926 }
@@ -2945,7 +2945,7 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2945 if (ah->power_mode == mode) 2945 if (ah->power_mode == mode)
2946 return status; 2946 return status;
2947 2947
2948 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "%s -> %s\n", 2948 DPRINTF(ah, ATH_DBG_RESET, "%s -> %s\n",
2949 modes[ah->power_mode], modes[mode]); 2949 modes[ah->power_mode], modes[mode]);
2950 2950
2951 switch (mode) { 2951 switch (mode) {
@@ -2960,7 +2960,7 @@ static bool ath9k_hw_setpower_nolock(struct ath_hw *ah,
2960 ath9k_set_power_network_sleep(ah, setChip); 2960 ath9k_set_power_network_sleep(ah, setChip);
2961 break; 2961 break;
2962 default: 2962 default:
2963 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 2963 DPRINTF(ah, ATH_DBG_FATAL,
2964 "Unknown power mode %u\n", mode); 2964 "Unknown power mode %u\n", mode);
2965 return false; 2965 return false;
2966 } 2966 }
@@ -3249,7 +3249,7 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3249 } 3249 }
3250 3250
3251 if (isr & AR_ISR_RXORN) { 3251 if (isr & AR_ISR_RXORN) {
3252 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 3252 DPRINTF(ah, ATH_DBG_INTERRUPT,
3253 "receive FIFO overrun interrupt\n"); 3253 "receive FIFO overrun interrupt\n");
3254 } 3254 }
3255 3255
@@ -3292,24 +3292,24 @@ bool ath9k_hw_getisr(struct ath_hw *ah, enum ath9k_int *masked)
3292 3292
3293 if (fatal_int) { 3293 if (fatal_int) {
3294 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) { 3294 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
3295 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 3295 DPRINTF(ah, ATH_DBG_ANY,
3296 "received PCI FATAL interrupt\n"); 3296 "received PCI FATAL interrupt\n");
3297 } 3297 }
3298 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) { 3298 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
3299 DPRINTF(ah->ah_sc, ATH_DBG_ANY, 3299 DPRINTF(ah, ATH_DBG_ANY,
3300 "received PCI PERR interrupt\n"); 3300 "received PCI PERR interrupt\n");
3301 } 3301 }
3302 *masked |= ATH9K_INT_FATAL; 3302 *masked |= ATH9K_INT_FATAL;
3303 } 3303 }
3304 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) { 3304 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
3305 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 3305 DPRINTF(ah, ATH_DBG_INTERRUPT,
3306 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n"); 3306 "AR_INTR_SYNC_RADM_CPL_TIMEOUT\n");
3307 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF); 3307 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
3308 REG_WRITE(ah, AR_RC, 0); 3308 REG_WRITE(ah, AR_RC, 0);
3309 *masked |= ATH9K_INT_FATAL; 3309 *masked |= ATH9K_INT_FATAL;
3310 } 3310 }
3311 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) { 3311 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
3312 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 3312 DPRINTF(ah, ATH_DBG_INTERRUPT,
3313 "AR_INTR_SYNC_LOCAL_TIMEOUT\n"); 3313 "AR_INTR_SYNC_LOCAL_TIMEOUT\n");
3314 } 3314 }
3315 3315
@@ -3326,10 +3326,10 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3326 u32 mask, mask2; 3326 u32 mask, mask2;
3327 struct ath9k_hw_capabilities *pCap = &ah->caps; 3327 struct ath9k_hw_capabilities *pCap = &ah->caps;
3328 3328
3329 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints); 3329 DPRINTF(ah, ATH_DBG_INTERRUPT, "0x%x => 0x%x\n", omask, ints);
3330 3330
3331 if (omask & ATH9K_INT_GLOBAL) { 3331 if (omask & ATH9K_INT_GLOBAL) {
3332 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "disable IER\n"); 3332 DPRINTF(ah, ATH_DBG_INTERRUPT, "disable IER\n");
3333 REG_WRITE(ah, AR_IER, AR_IER_DISABLE); 3333 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
3334 (void) REG_READ(ah, AR_IER); 3334 (void) REG_READ(ah, AR_IER);
3335 if (!AR_SREV_9100(ah)) { 3335 if (!AR_SREV_9100(ah)) {
@@ -3386,7 +3386,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3386 mask2 |= AR_IMR_S2_CST; 3386 mask2 |= AR_IMR_S2_CST;
3387 } 3387 }
3388 3388
3389 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask); 3389 DPRINTF(ah, ATH_DBG_INTERRUPT, "new IMR 0x%x\n", mask);
3390 REG_WRITE(ah, AR_IMR, mask); 3390 REG_WRITE(ah, AR_IMR, mask);
3391 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM | 3391 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
3392 AR_IMR_S2_DTIM | 3392 AR_IMR_S2_DTIM |
@@ -3406,7 +3406,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3406 } 3406 }
3407 3407
3408 if (ints & ATH9K_INT_GLOBAL) { 3408 if (ints & ATH9K_INT_GLOBAL) {
3409 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "enable IER\n"); 3409 DPRINTF(ah, ATH_DBG_INTERRUPT, "enable IER\n");
3410 REG_WRITE(ah, AR_IER, AR_IER_ENABLE); 3410 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
3411 if (!AR_SREV_9100(ah)) { 3411 if (!AR_SREV_9100(ah)) {
3412 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 3412 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
@@ -3419,7 +3419,7 @@ enum ath9k_int ath9k_hw_set_interrupts(struct ath_hw *ah, enum ath9k_int ints)
3419 REG_WRITE(ah, AR_INTR_SYNC_MASK, 3419 REG_WRITE(ah, AR_INTR_SYNC_MASK,
3420 AR_INTR_SYNC_DEFAULT); 3420 AR_INTR_SYNC_DEFAULT);
3421 } 3421 }
3422 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n", 3422 DPRINTF(ah, ATH_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
3423 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER)); 3423 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
3424 } 3424 }
3425 3425
@@ -3467,7 +3467,7 @@ void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
3467 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN; 3467 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
3468 break; 3468 break;
3469 default: 3469 default:
3470 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, 3470 DPRINTF(ah, ATH_DBG_BEACON,
3471 "%s: unsupported opmode: %d\n", 3471 "%s: unsupported opmode: %d\n",
3472 __func__, ah->opmode); 3472 __func__, ah->opmode);
3473 return; 3473 return;
@@ -3518,10 +3518,10 @@ void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
3518 else 3518 else
3519 nextTbtt = bs->bs_nexttbtt; 3519 nextTbtt = bs->bs_nexttbtt;
3520 3520
3521 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim); 3521 DPRINTF(ah, ATH_DBG_BEACON, "next DTIM %d\n", bs->bs_nextdtim);
3522 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt); 3522 DPRINTF(ah, ATH_DBG_BEACON, "next beacon %d\n", nextTbtt);
3523 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "beacon period %d\n", beaconintval); 3523 DPRINTF(ah, ATH_DBG_BEACON, "beacon period %d\n", beaconintval);
3524 DPRINTF(ah->ah_sc, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod); 3524 DPRINTF(ah, ATH_DBG_BEACON, "DTIM period %d\n", dtimperiod);
3525 3525
3526 REG_WRITE(ah, AR_NEXT_DTIM, 3526 REG_WRITE(ah, AR_NEXT_DTIM,
3527 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP)); 3527 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
@@ -3579,7 +3579,7 @@ void ath9k_hw_fill_cap_info(struct ath_hw *ah)
3579 regulatory->current_rd += 5; 3579 regulatory->current_rd += 5;
3580 else if (regulatory->current_rd == 0x41) 3580 else if (regulatory->current_rd == 0x41)
3581 regulatory->current_rd = 0x43; 3581 regulatory->current_rd = 0x43;
3582 DPRINTF(ah->ah_sc, ATH_DBG_REGULATORY, 3582 DPRINTF(ah, ATH_DBG_REGULATORY,
3583 "regdomain mapped to 0x%x\n", regulatory->current_rd); 3583 "regdomain mapped to 0x%x\n", regulatory->current_rd);
3584 } 3584 }
3585 3585
@@ -4103,7 +4103,7 @@ void ath9k_hw_reset_tsf(struct ath_hw *ah)
4103 ath9k_ps_wakeup(ah->ah_sc); 4103 ath9k_ps_wakeup(ah->ah_sc);
4104 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0, 4104 if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
4105 AH_TSF_WRITE_TIMEOUT)) 4105 AH_TSF_WRITE_TIMEOUT))
4106 DPRINTF(ah->ah_sc, ATH_DBG_RESET, 4106 DPRINTF(ah, ATH_DBG_RESET,
4107 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n"); 4107 "AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
4108 4108
4109 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE); 4109 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
@@ -4121,7 +4121,7 @@ void ath9k_hw_set_tsfadjust(struct ath_hw *ah, u32 setting)
4121bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us) 4121bool ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
4122{ 4122{
4123 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) { 4123 if (us < ATH9K_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
4124 DPRINTF(ah->ah_sc, ATH_DBG_RESET, "bad slot time %u\n", us); 4124 DPRINTF(ah, ATH_DBG_RESET, "bad slot time %u\n", us);
4125 ah->slottime = (u32) -1; 4125 ah->slottime = (u32) -1;
4126 return false; 4126 return false;
4127 } else { 4127 } else {
@@ -4234,7 +4234,7 @@ void ath_gen_timer_start(struct ath_hw *ah,
4234 4234
4235 tsf = ath9k_hw_gettsf32(ah); 4235 tsf = ath9k_hw_gettsf32(ah);
4236 4236
4237 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, "curent tsf %x period %x" 4237 DPRINTF(ah, ATH_DBG_HWTIMER, "curent tsf %x period %x"
4238 "timer_next %x\n", tsf, timer_period, timer_next); 4238 "timer_next %x\n", tsf, timer_period, timer_next);
4239 4239
4240 /* 4240 /*
@@ -4324,7 +4324,7 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4324 index = rightmost_index(timer_table, &thresh_mask); 4324 index = rightmost_index(timer_table, &thresh_mask);
4325 timer = timer_table->timers[index]; 4325 timer = timer_table->timers[index];
4326 BUG_ON(!timer); 4326 BUG_ON(!timer);
4327 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, 4327 DPRINTF(ah, ATH_DBG_HWTIMER,
4328 "TSF overflow for Gen timer %d\n", index); 4328 "TSF overflow for Gen timer %d\n", index);
4329 timer->overflow(timer->arg); 4329 timer->overflow(timer->arg);
4330 } 4330 }
@@ -4333,7 +4333,7 @@ void ath_gen_timer_isr(struct ath_hw *ah)
4333 index = rightmost_index(timer_table, &trigger_mask); 4333 index = rightmost_index(timer_table, &trigger_mask);
4334 timer = timer_table->timers[index]; 4334 timer = timer_table->timers[index];
4335 BUG_ON(!timer); 4335 BUG_ON(!timer);
4336 DPRINTF(ah->ah_sc, ATH_DBG_HWTIMER, 4336 DPRINTF(ah, ATH_DBG_HWTIMER,
4337 "Gen timer[%d] trigger\n", index); 4337 "Gen timer[%d] trigger\n", index);
4338 timer->trigger(timer->arg); 4338 timer->trigger(timer->arg);
4339 } 4339 }
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 800bfab94635..b4d2f207857d 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -19,7 +19,7 @@
19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah, 19static void ath9k_hw_set_txq_interrupts(struct ath_hw *ah,
20 struct ath9k_tx_queue_info *qi) 20 struct ath9k_tx_queue_info *qi)
21{ 21{
22 DPRINTF(ah->ah_sc, ATH_DBG_INTERRUPT, 22 DPRINTF(ah, ATH_DBG_INTERRUPT,
23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n", 23 "tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask, 24 ah->txok_interrupt_mask, ah->txerr_interrupt_mask,
25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask, 25 ah->txdesc_interrupt_mask, ah->txeol_interrupt_mask,
@@ -47,7 +47,7 @@ void ath9k_hw_puttxbuf(struct ath_hw *ah, u32 q, u32 txdp)
47 47
48void ath9k_hw_txstart(struct ath_hw *ah, u32 q) 48void ath9k_hw_txstart(struct ath_hw *ah, u32 q)
49{ 49{
50 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q); 50 DPRINTF(ah, ATH_DBG_QUEUE, "Enable TXE on queue: %u\n", q);
51 REG_WRITE(ah, AR_Q_TXE, 1 << q); 51 REG_WRITE(ah, AR_Q_TXE, 1 << q);
52} 52}
53 53
@@ -105,14 +105,14 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
105 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM; 105 u32 wait_time = ATH9K_TX_STOP_DMA_TIMEOUT / ATH9K_TIME_QUANTUM;
106 106
107 if (q >= pCap->total_queues) { 107 if (q >= pCap->total_queues) {
108 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, " 108 DPRINTF(ah, ATH_DBG_QUEUE, "Stopping TX DMA, "
109 "invalid queue: %u\n", q); 109 "invalid queue: %u\n", q);
110 return false; 110 return false;
111 } 111 }
112 112
113 qi = &ah->txq[q]; 113 qi = &ah->txq[q];
114 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 114 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
115 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Stopping TX DMA, " 115 DPRINTF(ah, ATH_DBG_QUEUE, "Stopping TX DMA, "
116 "inactive queue: %u\n", q); 116 "inactive queue: %u\n", q);
117 return false; 117 return false;
118 } 118 }
@@ -126,7 +126,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
126 } 126 }
127 127
128 if (ath9k_hw_numtxpending(ah, q)) { 128 if (ath9k_hw_numtxpending(ah, q)) {
129 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 129 DPRINTF(ah, ATH_DBG_QUEUE,
130 "%s: Num of pending TX Frames %d on Q %d\n", 130 "%s: Num of pending TX Frames %d on Q %d\n",
131 __func__, ath9k_hw_numtxpending(ah, q), q); 131 __func__, ath9k_hw_numtxpending(ah, q), q);
132 132
@@ -142,7 +142,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
142 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10)) 142 if ((REG_READ(ah, AR_TSF_L32) >> 10) == (tsfLow >> 10))
143 break; 143 break;
144 144
145 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 145 DPRINTF(ah, ATH_DBG_QUEUE,
146 "TSF has moved while trying to set " 146 "TSF has moved while trying to set "
147 "quiet time TSF: 0x%08x\n", tsfLow); 147 "quiet time TSF: 0x%08x\n", tsfLow);
148 } 148 }
@@ -155,7 +155,7 @@ bool ath9k_hw_stoptxdma(struct ath_hw *ah, u32 q)
155 wait = wait_time; 155 wait = wait_time;
156 while (ath9k_hw_numtxpending(ah, q)) { 156 while (ath9k_hw_numtxpending(ah, q)) {
157 if ((--wait) == 0) { 157 if ((--wait) == 0) {
158 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, 158 DPRINTF(ah, ATH_DBG_QUEUE,
159 "Failed to stop TX DMA in 100 " 159 "Failed to stop TX DMA in 100 "
160 "msec after killing last frame\n"); 160 "msec after killing last frame\n");
161 break; 161 break;
@@ -449,19 +449,19 @@ bool ath9k_hw_set_txq_props(struct ath_hw *ah, int q,
449 struct ath9k_tx_queue_info *qi; 449 struct ath9k_tx_queue_info *qi;
450 450
451 if (q >= pCap->total_queues) { 451 if (q >= pCap->total_queues) {
452 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, " 452 DPRINTF(ah, ATH_DBG_QUEUE, "Set TXQ properties, "
453 "invalid queue: %u\n", q); 453 "invalid queue: %u\n", q);
454 return false; 454 return false;
455 } 455 }
456 456
457 qi = &ah->txq[q]; 457 qi = &ah->txq[q];
458 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 458 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
459 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set TXQ properties, " 459 DPRINTF(ah, ATH_DBG_QUEUE, "Set TXQ properties, "
460 "inactive queue: %u\n", q); 460 "inactive queue: %u\n", q);
461 return false; 461 return false;
462 } 462 }
463 463
464 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q); 464 DPRINTF(ah, ATH_DBG_QUEUE, "Set queue properties for: %u\n", q);
465 465
466 qi->tqi_ver = qinfo->tqi_ver; 466 qi->tqi_ver = qinfo->tqi_ver;
467 qi->tqi_subtype = qinfo->tqi_subtype; 467 qi->tqi_subtype = qinfo->tqi_subtype;
@@ -518,14 +518,14 @@ bool ath9k_hw_get_txq_props(struct ath_hw *ah, int q,
518 struct ath9k_tx_queue_info *qi; 518 struct ath9k_tx_queue_info *qi;
519 519
520 if (q >= pCap->total_queues) { 520 if (q >= pCap->total_queues) {
521 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, " 521 DPRINTF(ah, ATH_DBG_QUEUE, "Get TXQ properties, "
522 "invalid queue: %u\n", q); 522 "invalid queue: %u\n", q);
523 return false; 523 return false;
524 } 524 }
525 525
526 qi = &ah->txq[q]; 526 qi = &ah->txq[q];
527 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 527 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
528 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Get TXQ properties, " 528 DPRINTF(ah, ATH_DBG_QUEUE, "Get TXQ properties, "
529 "inactive queue: %u\n", q); 529 "inactive queue: %u\n", q);
530 return false; 530 return false;
531 } 531 }
@@ -574,22 +574,22 @@ int ath9k_hw_setuptxqueue(struct ath_hw *ah, enum ath9k_tx_queue type,
574 ATH9K_TX_QUEUE_INACTIVE) 574 ATH9K_TX_QUEUE_INACTIVE)
575 break; 575 break;
576 if (q == pCap->total_queues) { 576 if (q == pCap->total_queues) {
577 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 577 DPRINTF(ah, ATH_DBG_FATAL,
578 "No available TX queue\n"); 578 "No available TX queue\n");
579 return -1; 579 return -1;
580 } 580 }
581 break; 581 break;
582 default: 582 default:
583 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, "Invalid TX queue type: %u\n", 583 DPRINTF(ah, ATH_DBG_FATAL, "Invalid TX queue type: %u\n",
584 type); 584 type);
585 return -1; 585 return -1;
586 } 586 }
587 587
588 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q); 588 DPRINTF(ah, ATH_DBG_QUEUE, "Setup TX queue: %u\n", q);
589 589
590 qi = &ah->txq[q]; 590 qi = &ah->txq[q];
591 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) { 591 if (qi->tqi_type != ATH9K_TX_QUEUE_INACTIVE) {
592 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 592 DPRINTF(ah, ATH_DBG_FATAL,
593 "TX queue: %u already active\n", q); 593 "TX queue: %u already active\n", q);
594 return -1; 594 return -1;
595 } 595 }
@@ -620,18 +620,18 @@ bool ath9k_hw_releasetxqueue(struct ath_hw *ah, u32 q)
620 struct ath9k_tx_queue_info *qi; 620 struct ath9k_tx_queue_info *qi;
621 621
622 if (q >= pCap->total_queues) { 622 if (q >= pCap->total_queues) {
623 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, " 623 DPRINTF(ah, ATH_DBG_QUEUE, "Release TXQ, "
624 "invalid queue: %u\n", q); 624 "invalid queue: %u\n", q);
625 return false; 625 return false;
626 } 626 }
627 qi = &ah->txq[q]; 627 qi = &ah->txq[q];
628 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 628 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
629 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TXQ, " 629 DPRINTF(ah, ATH_DBG_QUEUE, "Release TXQ, "
630 "inactive queue: %u\n", q); 630 "inactive queue: %u\n", q);
631 return false; 631 return false;
632 } 632 }
633 633
634 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Release TX queue: %u\n", q); 634 DPRINTF(ah, ATH_DBG_QUEUE, "Release TX queue: %u\n", q);
635 635
636 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE; 636 qi->tqi_type = ATH9K_TX_QUEUE_INACTIVE;
637 ah->txok_interrupt_mask &= ~(1 << q); 637 ah->txok_interrupt_mask &= ~(1 << q);
@@ -652,19 +652,19 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
652 u32 cwMin, chanCwMin, value; 652 u32 cwMin, chanCwMin, value;
653 653
654 if (q >= pCap->total_queues) { 654 if (q >= pCap->total_queues) {
655 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, " 655 DPRINTF(ah, ATH_DBG_QUEUE, "Reset TXQ, "
656 "invalid queue: %u\n", q); 656 "invalid queue: %u\n", q);
657 return false; 657 return false;
658 } 658 }
659 659
660 qi = &ah->txq[q]; 660 qi = &ah->txq[q];
661 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) { 661 if (qi->tqi_type == ATH9K_TX_QUEUE_INACTIVE) {
662 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TXQ, " 662 DPRINTF(ah, ATH_DBG_QUEUE, "Reset TXQ, "
663 "inactive queue: %u\n", q); 663 "inactive queue: %u\n", q);
664 return true; 664 return true;
665 } 665 }
666 666
667 DPRINTF(ah->ah_sc, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q); 667 DPRINTF(ah, ATH_DBG_QUEUE, "Reset TX queue: %u\n", q);
668 668
669 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) { 669 if (qi->tqi_cwmin == ATH9K_TXQ_USEDEFAULT) {
670 if (chan && IS_CHAN_B(chan)) 670 if (chan && IS_CHAN_B(chan))
@@ -911,7 +911,7 @@ bool ath9k_hw_setrxabort(struct ath_hw *ah, bool set)
911 AR_DIAG_RX_ABORT)); 911 AR_DIAG_RX_ABORT));
912 912
913 reg = REG_READ(ah, AR_OBS_BUS_1); 913 reg = REG_READ(ah, AR_OBS_BUS_1);
914 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 914 DPRINTF(ah, ATH_DBG_FATAL,
915 "RX failed to go idle in 10 ms RXSM=0x%x\n", reg); 915 "RX failed to go idle in 10 ms RXSM=0x%x\n", reg);
916 916
917 return false; 917 return false;
@@ -967,7 +967,7 @@ bool ath9k_hw_stopdmarecv(struct ath_hw *ah)
967 } 967 }
968 968
969 if (i == 0) { 969 if (i == 0) {
970 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 970 DPRINTF(ah, ATH_DBG_FATAL,
971 "DMA failed to stop in %d ms " 971 "DMA failed to stop in %d ms "
972 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n", 972 "AR_CR=0x%08x AR_DIAG_SW=0x%08x\n",
973 AH_RX_STOP_DMA_TIMEOUT / 1000, 973 AH_RX_STOP_DMA_TIMEOUT / 1000,
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 52bed89063d4..68d8dd9602dc 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -224,7 +224,7 @@ static void ath_setup_rates(struct ath_softc *sc, enum ieee80211_band band)
224 } 224 }
225 sband->n_bitrates++; 225 sband->n_bitrates++;
226 226
227 DPRINTF(sc, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n", 227 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Rate: %2dMbps, ratecode: %2d\n",
228 rate[i].bitrate / 10, rate[i].hw_value); 228 rate[i].bitrate / 10, rate[i].hw_value);
229 } 229 }
230} 230}
@@ -280,7 +280,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET)) 280 if (!stopped || (sc->sc_flags & SC_OP_FULL_RESET))
281 fastcc = false; 281 fastcc = false;
282 282
283 DPRINTF(sc, ATH_DBG_CONFIG, 283 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
284 "(%u MHz) -> (%u MHz), chanwidth: %d\n", 284 "(%u MHz) -> (%u MHz), chanwidth: %d\n",
285 sc->sc_ah->curchan->channel, 285 sc->sc_ah->curchan->channel,
286 channel->center_freq, sc->tx_chan_width); 286 channel->center_freq, sc->tx_chan_width);
@@ -289,7 +289,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
289 289
290 r = ath9k_hw_reset(ah, hchan, fastcc); 290 r = ath9k_hw_reset(ah, hchan, fastcc);
291 if (r) { 291 if (r) {
292 DPRINTF(sc, ATH_DBG_FATAL, 292 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
293 "Unable to reset channel (%u Mhz) " 293 "Unable to reset channel (%u Mhz) "
294 "reset status %d\n", 294 "reset status %d\n",
295 channel->center_freq, r); 295 channel->center_freq, r);
@@ -301,7 +301,7 @@ int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
301 sc->sc_flags &= ~SC_OP_FULL_RESET; 301 sc->sc_flags &= ~SC_OP_FULL_RESET;
302 302
303 if (ath_startrecv(sc) != 0) { 303 if (ath_startrecv(sc) != 0) {
304 DPRINTF(sc, ATH_DBG_FATAL, 304 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
305 "Unable to restart recv logic\n"); 305 "Unable to restart recv logic\n");
306 r = -EIO; 306 r = -EIO;
307 goto ps_restore; 307 goto ps_restore;
@@ -353,7 +353,7 @@ static void ath_ani_calibrate(unsigned long data)
353 /* Long calibration runs independently of short calibration. */ 353 /* Long calibration runs independently of short calibration. */
354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) { 354 if ((timestamp - sc->ani.longcal_timer) >= ATH_LONG_CALINTERVAL) {
355 longcal = true; 355 longcal = true;
356 DPRINTF(sc, ATH_DBG_ANI, "longcal @%lu\n", jiffies); 356 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
357 sc->ani.longcal_timer = timestamp; 357 sc->ani.longcal_timer = timestamp;
358 } 358 }
359 359
@@ -361,7 +361,7 @@ static void ath_ani_calibrate(unsigned long data)
361 if (!sc->ani.caldone) { 361 if (!sc->ani.caldone) {
362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) { 362 if ((timestamp - sc->ani.shortcal_timer) >= short_cal_interval) {
363 shortcal = true; 363 shortcal = true;
364 DPRINTF(sc, ATH_DBG_ANI, "shortcal @%lu\n", jiffies); 364 DPRINTF(sc->sc_ah, ATH_DBG_ANI, "shortcal @%lu\n", jiffies);
365 sc->ani.shortcal_timer = timestamp; 365 sc->ani.shortcal_timer = timestamp;
366 sc->ani.resetcal_timer = timestamp; 366 sc->ani.resetcal_timer = timestamp;
367 } 367 }
@@ -395,7 +395,7 @@ static void ath_ani_calibrate(unsigned long data)
395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah, 395 sc->ani.noise_floor = ath9k_hw_getchan_noise(ah,
396 ah->curchan); 396 ah->curchan);
397 397
398 DPRINTF(sc, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n", 398 DPRINTF(sc->sc_ah, ATH_DBG_ANI," calibrate chan %u/%x nf: %d\n",
399 ah->curchan->channel, ah->curchan->channelFlags, 399 ah->curchan->channel, ah->curchan->channelFlags,
400 sc->ani.noise_floor); 400 sc->ani.noise_floor);
401 } 401 }
@@ -448,7 +448,7 @@ void ath_update_chainmask(struct ath_softc *sc, int is_ht)
448 sc->rx_chainmask = 1; 448 sc->rx_chainmask = 1;
449 } 449 }
450 450
451 DPRINTF(sc, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n", 451 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "tx chmask: %d, rx chmask: %d\n",
452 sc->tx_chainmask, sc->rx_chainmask); 452 sc->tx_chainmask, sc->rx_chainmask);
453} 453}
454 454
@@ -502,7 +502,7 @@ static void ath9k_tasklet(unsigned long data)
502 * TSF sync does not look correct; remain awake to sync with 502 * TSF sync does not look correct; remain awake to sync with
503 * the next Beacon. 503 * the next Beacon.
504 */ 504 */
505 DPRINTF(sc, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n"); 505 DPRINTF(sc->sc_ah, ATH_DBG_PS, "TSFOOR - Sync with next Beacon\n");
506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC; 506 sc->sc_flags |= SC_OP_WAIT_FOR_BEACON | SC_OP_BEACON_SYNC;
507 } 507 }
508 508
@@ -702,7 +702,7 @@ static int ath_setkey_tkip(struct ath_softc *sc, u16 keyix, const u8 *key,
702 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic)); 702 memcpy(hk->kv_mic, key_txmic, sizeof(hk->kv_mic));
703 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) { 703 if (!ath9k_hw_set_keycache_entry(sc->sc_ah, keyix, hk, NULL)) {
704 /* TX MIC entry failed. No need to proceed further */ 704 /* TX MIC entry failed. No need to proceed further */
705 DPRINTF(sc, ATH_DBG_FATAL, 705 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
706 "Setting TX MIC Key Failed\n"); 706 "Setting TX MIC Key Failed\n");
707 return 0; 707 return 0;
708 } 708 }
@@ -907,7 +907,7 @@ static void setup_ht_cap(struct ath_softc *sc,
907 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2; 907 rx_streams = !(sc->rx_chainmask & (sc->rx_chainmask - 1)) ? 1 : 2;
908 908
909 if (tx_streams != rx_streams) { 909 if (tx_streams != rx_streams) {
910 DPRINTF(sc, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n", 910 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "TX streams %d, RX streams: %d\n",
911 tx_streams, rx_streams); 911 tx_streams, rx_streams);
912 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 912 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF;
913 ht_info->mcs.tx_params |= ((tx_streams - 1) << 913 ht_info->mcs.tx_params |= ((tx_streams - 1) <<
@@ -927,7 +927,7 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
927{ 927{
928 928
929 if (bss_conf->assoc) { 929 if (bss_conf->assoc) {
930 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n", 930 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info ASSOC %d, bssid: %pM\n",
931 bss_conf->aid, sc->curbssid); 931 bss_conf->aid, sc->curbssid);
932 932
933 /* New association, store aid */ 933 /* New association, store aid */
@@ -949,7 +949,7 @@ static void ath9k_bss_assoc_info(struct ath_softc *sc,
949 949
950 ath_start_ani(sc); 950 ath_start_ani(sc);
951 } else { 951 } else {
952 DPRINTF(sc, ATH_DBG_CONFIG, "Bss Info DISASSOC\n"); 952 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
953 sc->curaid = 0; 953 sc->curaid = 0;
954 /* Stop ANI */ 954 /* Stop ANI */
955 del_timer_sync(&sc->ani.timer); 955 del_timer_sync(&sc->ani.timer);
@@ -1042,7 +1042,7 @@ static int ath_register_led(struct ath_softc *sc, struct ath_led *led,
1042 1042
1043 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev); 1043 ret = led_classdev_register(wiphy_dev(sc->hw->wiphy), &led->led_cdev);
1044 if (ret) 1044 if (ret)
1045 DPRINTF(sc, ATH_DBG_FATAL, 1045 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1046 "Failed to register led:%s", led->name); 1046 "Failed to register led:%s", led->name);
1047 else 1047 else
1048 led->registered = 1; 1048 led->registered = 1;
@@ -1139,7 +1139,7 @@ void ath_radio_enable(struct ath_softc *sc)
1139 spin_lock_bh(&sc->sc_resetlock); 1139 spin_lock_bh(&sc->sc_resetlock);
1140 r = ath9k_hw_reset(ah, ah->curchan, false); 1140 r = ath9k_hw_reset(ah, ah->curchan, false);
1141 if (r) { 1141 if (r) {
1142 DPRINTF(sc, ATH_DBG_FATAL, 1142 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1143 "Unable to reset channel %u (%uMhz) ", 1143 "Unable to reset channel %u (%uMhz) ",
1144 "reset status %d\n", 1144 "reset status %d\n",
1145 channel->center_freq, r); 1145 channel->center_freq, r);
@@ -1148,7 +1148,7 @@ void ath_radio_enable(struct ath_softc *sc)
1148 1148
1149 ath_update_txpow(sc); 1149 ath_update_txpow(sc);
1150 if (ath_startrecv(sc) != 0) { 1150 if (ath_startrecv(sc) != 0) {
1151 DPRINTF(sc, ATH_DBG_FATAL, 1151 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1152 "Unable to restart recv logic\n"); 1152 "Unable to restart recv logic\n");
1153 return; 1153 return;
1154 } 1154 }
@@ -1194,7 +1194,7 @@ void ath_radio_disable(struct ath_softc *sc)
1194 spin_lock_bh(&sc->sc_resetlock); 1194 spin_lock_bh(&sc->sc_resetlock);
1195 r = ath9k_hw_reset(ah, ah->curchan, false); 1195 r = ath9k_hw_reset(ah, ah->curchan, false);
1196 if (r) { 1196 if (r) {
1197 DPRINTF(sc, ATH_DBG_FATAL, 1197 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1198 "Unable to reset channel %u (%uMhz) " 1198 "Unable to reset channel %u (%uMhz) "
1199 "reset status %d\n", 1199 "reset status %d\n",
1200 channel->center_freq, r); 1200 channel->center_freq, r);
@@ -1248,11 +1248,12 @@ void ath_cleanup(struct ath_softc *sc)
1248void ath_detach(struct ath_softc *sc) 1248void ath_detach(struct ath_softc *sc)
1249{ 1249{
1250 struct ieee80211_hw *hw = sc->hw; 1250 struct ieee80211_hw *hw = sc->hw;
1251 struct ath_hw *ah = sc->sc_ah;
1251 int i = 0; 1252 int i = 0;
1252 1253
1253 ath9k_ps_wakeup(sc); 1254 ath9k_ps_wakeup(sc);
1254 1255
1255 DPRINTF(sc, ATH_DBG_CONFIG, "Detach ATH hw\n"); 1256 dev_dbg(sc->dev, "Detach ATH hw\n");
1256 1257
1257 ath_deinit_leds(sc); 1258 ath_deinit_leds(sc);
1258 wiphy_rfkill_stop_polling(sc->hw->wiphy); 1259 wiphy_rfkill_stop_polling(sc->hw->wiphy);
@@ -1273,7 +1274,7 @@ void ath_detach(struct ath_softc *sc)
1273 tasklet_kill(&sc->bcon_tasklet); 1274 tasklet_kill(&sc->bcon_tasklet);
1274 1275
1275 if (!(sc->sc_flags & SC_OP_INVALID)) 1276 if (!(sc->sc_flags & SC_OP_INVALID))
1276 ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE); 1277 ath9k_hw_setpower(ah, ATH9K_PM_AWAKE);
1277 1278
1278 /* cleanup tx queues */ 1279 /* cleanup tx queues */
1279 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) 1280 for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
@@ -1282,11 +1283,11 @@ void ath_detach(struct ath_softc *sc)
1282 1283
1283 if ((sc->btcoex_info.no_stomp_timer) && 1284 if ((sc->btcoex_info.no_stomp_timer) &&
1284 sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE) 1285 sc->btcoex_info.btcoex_scheme == ATH_BTCOEX_CFG_3WIRE)
1285 ath_gen_timer_free(sc->sc_ah, sc->btcoex_info.no_stomp_timer); 1286 ath_gen_timer_free(ah, sc->btcoex_info.no_stomp_timer);
1286 1287
1287 ath9k_hw_detach(sc->sc_ah); 1288 ath9k_hw_detach(ah);
1289 ath9k_exit_debug(sc->sc_ah);
1288 sc->sc_ah = NULL; 1290 sc->sc_ah = NULL;
1289 ath9k_exit_debug(sc);
1290} 1291}
1291 1292
1292static int ath9k_reg_notifier(struct wiphy *wiphy, 1293static int ath9k_reg_notifier(struct wiphy *wiphy,
@@ -1315,9 +1316,6 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1315 /* XXX: hardware will not be ready until ath_open() being called */ 1316 /* XXX: hardware will not be ready until ath_open() being called */
1316 sc->sc_flags |= SC_OP_INVALID; 1317 sc->sc_flags |= SC_OP_INVALID;
1317 1318
1318 if (ath9k_init_debug(sc) < 0)
1319 printk(KERN_ERR "Unable to create debugfs files\n");
1320
1321 spin_lock_init(&sc->wiphy_lock); 1319 spin_lock_init(&sc->wiphy_lock);
1322 spin_lock_init(&sc->sc_resetlock); 1320 spin_lock_init(&sc->sc_resetlock);
1323 spin_lock_init(&sc->sc_serial_rw); 1321 spin_lock_init(&sc->sc_serial_rw);
@@ -1347,9 +1345,12 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1347 ah->hw_version.subsysid = subsysid; 1345 ah->hw_version.subsysid = subsysid;
1348 sc->sc_ah = ah; 1346 sc->sc_ah = ah;
1349 1347
1348 if (ath9k_init_debug(ah) < 0)
1349 dev_err(sc->dev, "Unable to create debugfs files\n");
1350
1350 r = ath9k_hw_init(ah); 1351 r = ath9k_hw_init(ah);
1351 if (r) { 1352 if (r) {
1352 DPRINTF(sc, ATH_DBG_FATAL, 1353 DPRINTF(ah, ATH_DBG_FATAL,
1353 "Unable to initialize hardware; " 1354 "Unable to initialize hardware; "
1354 "initialization status: %d\n", r); 1355 "initialization status: %d\n", r);
1355 goto bad; 1356 goto bad;
@@ -1358,7 +1359,7 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1358 /* Get the hardware key cache size. */ 1359 /* Get the hardware key cache size. */
1359 sc->keymax = ah->caps.keycache_size; 1360 sc->keymax = ah->caps.keycache_size;
1360 if (sc->keymax > ATH_KEYMAX) { 1361 if (sc->keymax > ATH_KEYMAX) {
1361 DPRINTF(sc, ATH_DBG_ANY, 1362 DPRINTF(ah, ATH_DBG_ANY,
1362 "Warning, using only %u entries in %u key cache\n", 1363 "Warning, using only %u entries in %u key cache\n",
1363 ATH_KEYMAX, sc->keymax); 1364 ATH_KEYMAX, sc->keymax);
1364 sc->keymax = ATH_KEYMAX; 1365 sc->keymax = ATH_KEYMAX;
@@ -1388,14 +1389,14 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1388 */ 1389 */
1389 sc->beacon.beaconq = ath_beaconq_setup(ah); 1390 sc->beacon.beaconq = ath_beaconq_setup(ah);
1390 if (sc->beacon.beaconq == -1) { 1391 if (sc->beacon.beaconq == -1) {
1391 DPRINTF(sc, ATH_DBG_FATAL, 1392 DPRINTF(ah, ATH_DBG_FATAL,
1392 "Unable to setup a beacon xmit queue\n"); 1393 "Unable to setup a beacon xmit queue\n");
1393 r = -EIO; 1394 r = -EIO;
1394 goto bad2; 1395 goto bad2;
1395 } 1396 }
1396 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0); 1397 sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
1397 if (sc->beacon.cabq == NULL) { 1398 if (sc->beacon.cabq == NULL) {
1398 DPRINTF(sc, ATH_DBG_FATAL, 1399 DPRINTF(ah, ATH_DBG_FATAL,
1399 "Unable to setup CAB xmit queue\n"); 1400 "Unable to setup CAB xmit queue\n");
1400 r = -EIO; 1401 r = -EIO;
1401 goto bad2; 1402 goto bad2;
@@ -1410,26 +1411,26 @@ static int ath_init_softc(u16 devid, struct ath_softc *sc, u16 subsysid)
1410 /* Setup data queues */ 1411 /* Setup data queues */
1411 /* NB: ensure BK queue is the lowest priority h/w queue */ 1412 /* NB: ensure BK queue is the lowest priority h/w queue */
1412 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) { 1413 if (!ath_tx_setup(sc, ATH9K_WME_AC_BK)) {
1413 DPRINTF(sc, ATH_DBG_FATAL, 1414 DPRINTF(ah, ATH_DBG_FATAL,
1414 "Unable to setup xmit queue for BK traffic\n"); 1415 "Unable to setup xmit queue for BK traffic\n");
1415 r = -EIO; 1416 r = -EIO;
1416 goto bad2; 1417 goto bad2;
1417 } 1418 }
1418 1419
1419 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) { 1420 if (!ath_tx_setup(sc, ATH9K_WME_AC_BE)) {
1420 DPRINTF(sc, ATH_DBG_FATAL, 1421 DPRINTF(ah, ATH_DBG_FATAL,
1421 "Unable to setup xmit queue for BE traffic\n"); 1422 "Unable to setup xmit queue for BE traffic\n");
1422 r = -EIO; 1423 r = -EIO;
1423 goto bad2; 1424 goto bad2;
1424 } 1425 }
1425 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) { 1426 if (!ath_tx_setup(sc, ATH9K_WME_AC_VI)) {
1426 DPRINTF(sc, ATH_DBG_FATAL, 1427 DPRINTF(ah, ATH_DBG_FATAL,
1427 "Unable to setup xmit queue for VI traffic\n"); 1428 "Unable to setup xmit queue for VI traffic\n");
1428 r = -EIO; 1429 r = -EIO;
1429 goto bad2; 1430 goto bad2;
1430 } 1431 }
1431 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) { 1432 if (!ath_tx_setup(sc, ATH9K_WME_AC_VO)) {
1432 DPRINTF(sc, ATH_DBG_FATAL, 1433 DPRINTF(ah, ATH_DBG_FATAL,
1433 "Unable to setup xmit queue for VO traffic\n"); 1434 "Unable to setup xmit queue for VO traffic\n");
1434 r = -EIO; 1435 r = -EIO;
1435 goto bad2; 1436 goto bad2;
@@ -1529,9 +1530,9 @@ bad2:
1529 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 1530 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1530bad: 1531bad:
1531 ath9k_hw_detach(ah); 1532 ath9k_hw_detach(ah);
1532 sc->sc_ah = NULL;
1533bad_no_ah: 1533bad_no_ah:
1534 ath9k_exit_debug(sc); 1534 ath9k_exit_debug(sc->sc_ah);
1535 sc->sc_ah = NULL;
1535 1536
1536 return r; 1537 return r;
1537} 1538}
@@ -1577,18 +1578,21 @@ void ath_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
1577int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid) 1578int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1578{ 1579{
1579 struct ieee80211_hw *hw = sc->hw; 1580 struct ieee80211_hw *hw = sc->hw;
1581 struct ath_hw *ah;
1580 int error = 0, i; 1582 int error = 0, i;
1581 struct ath_regulatory *reg; 1583 struct ath_regulatory *reg;
1582 1584
1583 DPRINTF(sc, ATH_DBG_CONFIG, "Attach ATH hw\n"); 1585 dev_dbg(sc->dev, "Attach ATH hw\n");
1584 1586
1585 error = ath_init_softc(devid, sc, subsysid); 1587 error = ath_init_softc(devid, sc, subsysid);
1586 if (error != 0) 1588 if (error != 0)
1587 return error; 1589 return error;
1588 1590
1591 ah = sc->sc_ah;
1592
1589 /* get mac address from hardware and set in mac80211 */ 1593 /* get mac address from hardware and set in mac80211 */
1590 1594
1591 SET_IEEE80211_PERM_ADDR(hw, sc->sc_ah->macaddr); 1595 SET_IEEE80211_PERM_ADDR(hw, ah->macaddr);
1592 1596
1593 ath_set_hw_capab(sc, hw); 1597 ath_set_hw_capab(sc, hw);
1594 1598
@@ -1599,9 +1603,9 @@ int ath_init_device(u16 devid, struct ath_softc *sc, u16 subsysid)
1599 1603
1600 reg = &sc->common.regulatory; 1604 reg = &sc->common.regulatory;
1601 1605
1602 if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 1606 if (ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
1603 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap); 1607 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_2GHZ].ht_cap);
1604 if (test_bit(ATH9K_MODE_11A, sc->sc_ah->caps.wireless_modes)) 1608 if (test_bit(ATH9K_MODE_11A, ah->caps.wireless_modes))
1605 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap); 1609 setup_ht_cap(sc, &sc->sbands[IEEE80211_BAND_5GHZ].ht_cap);
1606 } 1610 }
1607 1611
@@ -1639,9 +1643,9 @@ error_attach:
1639 if (ATH_TXQ_SETUP(sc, i)) 1643 if (ATH_TXQ_SETUP(sc, i))
1640 ath_tx_cleanupq(sc, &sc->tx.txq[i]); 1644 ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1641 1645
1642 ath9k_hw_detach(sc->sc_ah); 1646 ath9k_hw_detach(ah);
1647 ath9k_exit_debug(ah);
1643 sc->sc_ah = NULL; 1648 sc->sc_ah = NULL;
1644 ath9k_exit_debug(sc);
1645 1649
1646 return error; 1650 return error;
1647} 1651}
@@ -1660,12 +1664,12 @@ int ath_reset(struct ath_softc *sc, bool retry_tx)
1660 spin_lock_bh(&sc->sc_resetlock); 1664 spin_lock_bh(&sc->sc_resetlock);
1661 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false); 1665 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, false);
1662 if (r) 1666 if (r)
1663 DPRINTF(sc, ATH_DBG_FATAL, 1667 DPRINTF(ah, ATH_DBG_FATAL,
1664 "Unable to reset hardware; reset status %d\n", r); 1668 "Unable to reset hardware; reset status %d\n", r);
1665 spin_unlock_bh(&sc->sc_resetlock); 1669 spin_unlock_bh(&sc->sc_resetlock);
1666 1670
1667 if (ath_startrecv(sc) != 0) 1671 if (ath_startrecv(sc) != 0)
1668 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); 1672 DPRINTF(ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
1669 1673
1670 /* 1674 /*
1671 * We may be doing a reset in response to a request 1675 * We may be doing a reset in response to a request
@@ -1713,13 +1717,13 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1713 struct ath_buf *bf; 1717 struct ath_buf *bf;
1714 int i, bsize, error; 1718 int i, bsize, error;
1715 1719
1716 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n", 1720 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA: %u buffers %u desc/buf\n",
1717 name, nbuf, ndesc); 1721 name, nbuf, ndesc);
1718 1722
1719 INIT_LIST_HEAD(head); 1723 INIT_LIST_HEAD(head);
1720 /* ath_desc must be a multiple of DWORDs */ 1724 /* ath_desc must be a multiple of DWORDs */
1721 if ((sizeof(struct ath_desc) % 4) != 0) { 1725 if ((sizeof(struct ath_desc) % 4) != 0) {
1722 DPRINTF(sc, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n"); 1726 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "ath_desc not DWORD aligned\n");
1723 ASSERT((sizeof(struct ath_desc) % 4) == 0); 1727 ASSERT((sizeof(struct ath_desc) % 4) == 0);
1724 error = -ENOMEM; 1728 error = -ENOMEM;
1725 goto fail; 1729 goto fail;
@@ -1753,7 +1757,7 @@ int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
1753 goto fail; 1757 goto fail;
1754 } 1758 }
1755 ds = dd->dd_desc; 1759 ds = dd->dd_desc;
1756 DPRINTF(sc, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n", 1760 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
1757 name, ds, (u32) dd->dd_desc_len, 1761 name, ds, (u32) dd->dd_desc_len,
1758 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len); 1762 ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
1759 1763
@@ -1905,7 +1909,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1905 struct ath9k_channel *init_channel; 1909 struct ath9k_channel *init_channel;
1906 int r; 1910 int r;
1907 1911
1908 DPRINTF(sc, ATH_DBG_CONFIG, "Starting driver with " 1912 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Starting driver with "
1909 "initial channel: %d MHz\n", curchan->center_freq); 1913 "initial channel: %d MHz\n", curchan->center_freq);
1910 1914
1911 mutex_lock(&sc->mutex); 1915 mutex_lock(&sc->mutex);
@@ -1950,7 +1954,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1950 spin_lock_bh(&sc->sc_resetlock); 1954 spin_lock_bh(&sc->sc_resetlock);
1951 r = ath9k_hw_reset(sc->sc_ah, init_channel, false); 1955 r = ath9k_hw_reset(sc->sc_ah, init_channel, false);
1952 if (r) { 1956 if (r) {
1953 DPRINTF(sc, ATH_DBG_FATAL, 1957 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1954 "Unable to reset hardware; reset status %d " 1958 "Unable to reset hardware; reset status %d "
1955 "(freq %u MHz)\n", r, 1959 "(freq %u MHz)\n", r,
1956 curchan->center_freq); 1960 curchan->center_freq);
@@ -1973,7 +1977,7 @@ static int ath9k_start(struct ieee80211_hw *hw)
1973 * here except setup the interrupt mask. 1977 * here except setup the interrupt mask.
1974 */ 1978 */
1975 if (ath_startrecv(sc) != 0) { 1979 if (ath_startrecv(sc) != 0) {
1976 DPRINTF(sc, ATH_DBG_FATAL, "Unable to start recv logic\n"); 1980 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to start recv logic\n");
1977 r = -EIO; 1981 r = -EIO;
1978 goto mutex_unlock; 1982 goto mutex_unlock;
1979 } 1983 }
@@ -2042,7 +2046,7 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2042 if (ieee80211_is_data(hdr->frame_control) && 2046 if (ieee80211_is_data(hdr->frame_control) &&
2043 !ieee80211_is_nullfunc(hdr->frame_control) && 2047 !ieee80211_is_nullfunc(hdr->frame_control) &&
2044 !ieee80211_has_pm(hdr->frame_control)) { 2048 !ieee80211_has_pm(hdr->frame_control)) {
2045 DPRINTF(sc, ATH_DBG_PS, "Add PM=1 for a TX frame " 2049 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Add PM=1 for a TX frame "
2046 "while in PS mode\n"); 2050 "while in PS mode\n");
2047 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM); 2051 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
2048 } 2052 }
@@ -2058,11 +2062,11 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2058 ath9k_ps_wakeup(sc); 2062 ath9k_ps_wakeup(sc);
2059 ath9k_hw_setrxabort(sc->sc_ah, 0); 2063 ath9k_hw_setrxabort(sc->sc_ah, 0);
2060 if (ieee80211_is_pspoll(hdr->frame_control)) { 2064 if (ieee80211_is_pspoll(hdr->frame_control)) {
2061 DPRINTF(sc, ATH_DBG_PS, "Sending PS-Poll to pick a " 2065 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Sending PS-Poll to pick a "
2062 "buffered frame\n"); 2066 "buffered frame\n");
2063 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA; 2067 sc->sc_flags |= SC_OP_WAIT_FOR_PSPOLL_DATA;
2064 } else { 2068 } else {
2065 DPRINTF(sc, ATH_DBG_PS, "Wake up to complete TX\n"); 2069 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Wake up to complete TX\n");
2066 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK; 2070 sc->sc_flags |= SC_OP_WAIT_FOR_TX_ACK;
2067 } 2071 }
2068 /* 2072 /*
@@ -2104,10 +2108,10 @@ static int ath9k_tx(struct ieee80211_hw *hw,
2104 if (!txctl.txq) 2108 if (!txctl.txq)
2105 goto exit; 2109 goto exit;
2106 2110
2107 DPRINTF(sc, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb); 2111 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
2108 2112
2109 if (ath_tx_start(hw, skb, &txctl) != 0) { 2113 if (ath_tx_start(hw, skb, &txctl) != 0) {
2110 DPRINTF(sc, ATH_DBG_XMIT, "TX failed\n"); 2114 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX failed\n");
2111 goto exit; 2115 goto exit;
2112 } 2116 }
2113 2117
@@ -2135,7 +2139,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2135 } 2139 }
2136 2140
2137 if (sc->sc_flags & SC_OP_INVALID) { 2141 if (sc->sc_flags & SC_OP_INVALID) {
2138 DPRINTF(sc, ATH_DBG_ANY, "Device not present\n"); 2142 DPRINTF(sc->sc_ah, ATH_DBG_ANY, "Device not present\n");
2139 mutex_unlock(&sc->mutex); 2143 mutex_unlock(&sc->mutex);
2140 return; 2144 return;
2141 } 2145 }
@@ -2171,7 +2175,7 @@ static void ath9k_stop(struct ieee80211_hw *hw)
2171 2175
2172 mutex_unlock(&sc->mutex); 2176 mutex_unlock(&sc->mutex);
2173 2177
2174 DPRINTF(sc, ATH_DBG_CONFIG, "Driver halt\n"); 2178 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Driver halt\n");
2175} 2179}
2176 2180
2177static int ath9k_add_interface(struct ieee80211_hw *hw, 2181static int ath9k_add_interface(struct ieee80211_hw *hw,
@@ -2205,13 +2209,13 @@ static int ath9k_add_interface(struct ieee80211_hw *hw,
2205 ic_opmode = conf->type; 2209 ic_opmode = conf->type;
2206 break; 2210 break;
2207 default: 2211 default:
2208 DPRINTF(sc, ATH_DBG_FATAL, 2212 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
2209 "Interface type %d not yet supported\n", conf->type); 2213 "Interface type %d not yet supported\n", conf->type);
2210 ret = -EOPNOTSUPP; 2214 ret = -EOPNOTSUPP;
2211 goto out; 2215 goto out;
2212 } 2216 }
2213 2217
2214 DPRINTF(sc, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode); 2218 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Attach a VIF of type: %d\n", ic_opmode);
2215 2219
2216 /* Set the VIF opmode */ 2220 /* Set the VIF opmode */
2217 avp->av_opmode = ic_opmode; 2221 avp->av_opmode = ic_opmode;
@@ -2264,7 +2268,7 @@ static void ath9k_remove_interface(struct ieee80211_hw *hw,
2264 struct ath_vif *avp = (void *)conf->vif->drv_priv; 2268 struct ath_vif *avp = (void *)conf->vif->drv_priv;
2265 int i; 2269 int i;
2266 2270
2267 DPRINTF(sc, ATH_DBG_CONFIG, "Detach Interface\n"); 2271 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Detach Interface\n");
2268 2272
2269 mutex_lock(&sc->mutex); 2273 mutex_lock(&sc->mutex);
2270 2274
@@ -2318,7 +2322,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2318 } 2322 }
2319 else if (all_wiphys_idle) { 2323 else if (all_wiphys_idle) {
2320 ath_radio_enable(sc); 2324 ath_radio_enable(sc);
2321 DPRINTF(sc, ATH_DBG_CONFIG, 2325 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2322 "not-idle: enabling radio\n"); 2326 "not-idle: enabling radio\n");
2323 } 2327 }
2324 } 2328 }
@@ -2372,7 +2376,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2372 goto skip_chan_change; 2376 goto skip_chan_change;
2373 } 2377 }
2374 2378
2375 DPRINTF(sc, ATH_DBG_CONFIG, "Set channel: %d MHz\n", 2379 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
2376 curchan->center_freq); 2380 curchan->center_freq);
2377 2381
2378 /* XXX: remove me eventualy */ 2382 /* XXX: remove me eventualy */
@@ -2381,7 +2385,7 @@ static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
2381 ath_update_chainmask(sc, conf_is_ht(conf)); 2385 ath_update_chainmask(sc, conf_is_ht(conf));
2382 2386
2383 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) { 2387 if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
2384 DPRINTF(sc, ATH_DBG_FATAL, "Unable to set channel\n"); 2388 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unable to set channel\n");
2385 mutex_unlock(&sc->mutex); 2389 mutex_unlock(&sc->mutex);
2386 return -EINVAL; 2390 return -EINVAL;
2387 } 2391 }
@@ -2392,7 +2396,7 @@ skip_chan_change:
2392 sc->config.txpowlimit = 2 * conf->power_level; 2396 sc->config.txpowlimit = 2 * conf->power_level;
2393 2397
2394 if (disable_radio) { 2398 if (disable_radio) {
2395 DPRINTF(sc, ATH_DBG_CONFIG, "idle: disabling radio\n"); 2399 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "idle: disabling radio\n");
2396 ath_radio_disable(sc); 2400 ath_radio_disable(sc);
2397 } 2401 }
2398 2402
@@ -2429,7 +2433,7 @@ static void ath9k_configure_filter(struct ieee80211_hw *hw,
2429 ath9k_hw_setrxfilter(sc->sc_ah, rfilt); 2433 ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
2430 ath9k_ps_restore(sc); 2434 ath9k_ps_restore(sc);
2431 2435
2432 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt); 2436 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW RX filter: 0x%x\n", rfilt);
2433} 2437}
2434 2438
2435static void ath9k_sta_notify(struct ieee80211_hw *hw, 2439static void ath9k_sta_notify(struct ieee80211_hw *hw,
@@ -2473,7 +2477,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2473 qi.tqi_burstTime = params->txop; 2477 qi.tqi_burstTime = params->txop;
2474 qnum = ath_get_hal_qnum(queue, sc); 2478 qnum = ath_get_hal_qnum(queue, sc);
2475 2479
2476 DPRINTF(sc, ATH_DBG_CONFIG, 2480 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2477 "Configure tx [queue/halq] [%d/%d], " 2481 "Configure tx [queue/halq] [%d/%d], "
2478 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n", 2482 "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
2479 queue, qnum, params->aifs, params->cw_min, 2483 queue, qnum, params->aifs, params->cw_min,
@@ -2481,7 +2485,7 @@ static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
2481 2485
2482 ret = ath_txq_update(sc, qnum, &qi); 2486 ret = ath_txq_update(sc, qnum, &qi);
2483 if (ret) 2487 if (ret)
2484 DPRINTF(sc, ATH_DBG_FATAL, "TXQ Update failed\n"); 2488 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TXQ Update failed\n");
2485 2489
2486 mutex_unlock(&sc->mutex); 2490 mutex_unlock(&sc->mutex);
2487 2491
@@ -2503,7 +2507,7 @@ static int ath9k_set_key(struct ieee80211_hw *hw,
2503 2507
2504 mutex_lock(&sc->mutex); 2508 mutex_lock(&sc->mutex);
2505 ath9k_ps_wakeup(sc); 2509 ath9k_ps_wakeup(sc);
2506 DPRINTF(sc, ATH_DBG_CONFIG, "Set HW Key\n"); 2510 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Set HW Key\n");
2507 2511
2508 switch (cmd) { 2512 switch (cmd) {
2509 case SET_KEY: 2513 case SET_KEY:
@@ -2577,7 +2581,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2577 /* Set aggregation protection mode parameters */ 2581 /* Set aggregation protection mode parameters */
2578 sc->config.ath_aggr_prot = 0; 2582 sc->config.ath_aggr_prot = 0;
2579 2583
2580 DPRINTF(sc, ATH_DBG_CONFIG, 2584 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
2581 "RX filter 0x%x bssid %pM aid 0x%x\n", 2585 "RX filter 0x%x bssid %pM aid 0x%x\n",
2582 rfilt, sc->curbssid, sc->curaid); 2586 rfilt, sc->curbssid, sc->curaid);
2583 2587
@@ -2626,7 +2630,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2626 ath_update_chainmask(sc, 0); 2630 ath_update_chainmask(sc, 0);
2627 2631
2628 if (changed & BSS_CHANGED_ERP_PREAMBLE) { 2632 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
2629 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n", 2633 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
2630 bss_conf->use_short_preamble); 2634 bss_conf->use_short_preamble);
2631 if (bss_conf->use_short_preamble) 2635 if (bss_conf->use_short_preamble)
2632 sc->sc_flags |= SC_OP_PREAMBLE_SHORT; 2636 sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
@@ -2635,7 +2639,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2635 } 2639 }
2636 2640
2637 if (changed & BSS_CHANGED_ERP_CTS_PROT) { 2641 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
2638 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n", 2642 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
2639 bss_conf->use_cts_prot); 2643 bss_conf->use_cts_prot);
2640 if (bss_conf->use_cts_prot && 2644 if (bss_conf->use_cts_prot &&
2641 hw->conf.channel->band != IEEE80211_BAND_5GHZ) 2645 hw->conf.channel->band != IEEE80211_BAND_5GHZ)
@@ -2645,7 +2649,7 @@ static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
2645 } 2649 }
2646 2650
2647 if (changed & BSS_CHANGED_ASSOC) { 2651 if (changed & BSS_CHANGED_ASSOC) {
2648 DPRINTF(sc, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n", 2652 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
2649 bss_conf->assoc); 2653 bss_conf->assoc);
2650 ath9k_bss_assoc_info(sc, vif, bss_conf); 2654 ath9k_bss_assoc_info(sc, vif, bss_conf);
2651 } 2655 }
@@ -2726,7 +2730,7 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
2726 ath_tx_aggr_resume(sc, sta, tid); 2730 ath_tx_aggr_resume(sc, sta, tid);
2727 break; 2731 break;
2728 default: 2732 default:
2729 DPRINTF(sc, ATH_DBG_FATAL, "Unknown AMPDU action\n"); 2733 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "Unknown AMPDU action\n");
2730 } 2734 }
2731 2735
2732 return ret; 2736 return ret;
diff --git a/drivers/net/wireless/ath/ath9k/phy.c b/drivers/net/wireless/ath/ath9k/phy.c
index 63bf9a307c6a..1166f725f556 100644
--- a/drivers/net/wireless/ath/ath9k/phy.c
+++ b/drivers/net/wireless/ath/ath9k/phy.c
@@ -46,7 +46,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
46 channelSel = ((freq - 704) * 2 - 3040) / 10; 46 channelSel = ((freq - 704) * 2 - 3040) / 10;
47 bModeSynth = 1; 47 bModeSynth = 1;
48 } else { 48 } else {
49 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 49 DPRINTF(ah, ATH_DBG_FATAL,
50 "Invalid channel %u MHz\n", freq); 50 "Invalid channel %u MHz\n", freq);
51 return false; 51 return false;
52 } 52 }
@@ -79,7 +79,7 @@ ath9k_hw_set_channel(struct ath_hw *ah, struct ath9k_channel *chan)
79 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8); 79 channelSel = ath9k_hw_reverse_bits((freq - 4800) / 5, 8);
80 aModeRefSel = ath9k_hw_reverse_bits(1, 2); 80 aModeRefSel = ath9k_hw_reverse_bits(1, 2);
81 } else { 81 } else {
82 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 82 DPRINTF(ah, ATH_DBG_FATAL,
83 "Invalid channel %u MHz\n", freq); 83 "Invalid channel %u MHz\n", freq);
84 return false; 84 return false;
85 } 85 }
@@ -315,7 +315,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
315 || ah->analogBank6Data == NULL 315 || ah->analogBank6Data == NULL
316 || ah->analogBank6TPCData == NULL 316 || ah->analogBank6TPCData == NULL
317 || ah->analogBank7Data == NULL) { 317 || ah->analogBank7Data == NULL) {
318 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 318 DPRINTF(ah, ATH_DBG_FATAL,
319 "Cannot allocate RF banks\n"); 319 "Cannot allocate RF banks\n");
320 *status = -ENOMEM; 320 *status = -ENOMEM;
321 return false; 321 return false;
@@ -326,7 +326,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
326 ah->iniAddac.ia_rows * 326 ah->iniAddac.ia_rows *
327 ah->iniAddac.ia_columns), GFP_KERNEL); 327 ah->iniAddac.ia_columns), GFP_KERNEL);
328 if (ah->addac5416_21 == NULL) { 328 if (ah->addac5416_21 == NULL) {
329 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 329 DPRINTF(ah, ATH_DBG_FATAL,
330 "Cannot allocate addac5416_21\n"); 330 "Cannot allocate addac5416_21\n");
331 *status = -ENOMEM; 331 *status = -ENOMEM;
332 return false; 332 return false;
@@ -336,7 +336,7 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, int *status)
336 kzalloc((sizeof(u32) * 336 kzalloc((sizeof(u32) *
337 ah->iniBank6.ia_rows), GFP_KERNEL); 337 ah->iniBank6.ia_rows), GFP_KERNEL);
338 if (ah->bank6Temp == NULL) { 338 if (ah->bank6Temp == NULL) {
339 DPRINTF(ah->ah_sc, ATH_DBG_FATAL, 339 DPRINTF(ah, ATH_DBG_FATAL,
340 "Cannot allocate bank6Temp\n"); 340 "Cannot allocate bank6Temp\n");
341 *status = -ENOMEM; 341 *status = -ENOMEM;
342 return false; 342 return false;
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index 16a271787b85..cafe1ec7bdbb 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1177,13 +1177,14 @@ struct ath_rate_table *ath_choose_rate_table(struct ath_softc *sc,
1177 mode = ATH9K_MODE_11NA_HT40PLUS; 1177 mode = ATH9K_MODE_11NA_HT40PLUS;
1178 break; 1178 break;
1179 default: 1179 default:
1180 DPRINTF(sc, ATH_DBG_CONFIG, "Invalid band\n"); 1180 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "Invalid band\n");
1181 return NULL; 1181 return NULL;
1182 } 1182 }
1183 1183
1184 BUG_ON(mode >= ATH9K_MODE_MAX); 1184 BUG_ON(mode >= ATH9K_MODE_MAX);
1185 1185
1186 DPRINTF(sc, ATH_DBG_CONFIG, "Choosing rate table for mode: %d\n", mode); 1186 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
1187 "Choosing rate table for mode: %d\n", mode);
1187 return sc->hw_rate_table[mode]; 1188 return sc->hw_rate_table[mode];
1188} 1189}
1189 1190
@@ -1198,7 +1199,8 @@ static void ath_rc_init(struct ath_softc *sc,
1198 u8 i, j, k, hi = 0, hthi = 0; 1199 u8 i, j, k, hi = 0, hthi = 0;
1199 1200
1200 if (!rate_table) { 1201 if (!rate_table) {
1201 DPRINTF(sc, ATH_DBG_FATAL, "Rate table not initialized\n"); 1202 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1203 "Rate table not initialized\n");
1202 return; 1204 return;
1203 } 1205 }
1204 1206
@@ -1261,7 +1263,8 @@ static void ath_rc_init(struct ath_softc *sc,
1261 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4]; 1263 ath_rc_priv->rate_max_phy = ath_rc_priv->valid_rate_index[k-4];
1262 sc->cur_rate_table = rate_table; 1264 sc->cur_rate_table = rate_table;
1263 1265
1264 DPRINTF(sc, ATH_DBG_CONFIG, "RC Initialized with capabilities: 0x%x\n", 1266 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
1267 "RC Initialized with capabilities: 0x%x\n",
1265 ath_rc_priv->ht_cap); 1268 ath_rc_priv->ht_cap);
1266} 1269}
1267 1270
@@ -1438,7 +1441,7 @@ static void ath_rate_update(void *priv, struct ieee80211_supported_band *sband,
1438 oper_cw40, oper_sgi40); 1441 oper_cw40, oper_sgi40);
1439 ath_rc_init(sc, priv_sta, sband, sta, rate_table); 1442 ath_rc_init(sc, priv_sta, sband, sta, rate_table);
1440 1443
1441 DPRINTF(sc, ATH_DBG_CONFIG, 1444 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG,
1442 "Operating HT Bandwidth changed to: %d\n", 1445 "Operating HT Bandwidth changed to: %d\n",
1443 sc->hw->conf.channel_type); 1446 sc->hw->conf.channel_type);
1444 } 1447 }
@@ -1463,7 +1466,7 @@ static void *ath_rate_alloc_sta(void *priv, struct ieee80211_sta *sta, gfp_t gfp
1463 1466
1464 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp); 1467 rate_priv = kzalloc(sizeof(struct ath_rate_priv), gfp);
1465 if (!rate_priv) { 1468 if (!rate_priv) {
1466 DPRINTF(sc, ATH_DBG_FATAL, 1469 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1467 "Unable to allocate private rc structure\n"); 1470 "Unable to allocate private rc structure\n");
1468 return NULL; 1471 return NULL;
1469 } 1472 }
diff --git a/drivers/net/wireless/ath/ath9k/recv.c b/drivers/net/wireless/ath/ath9k/recv.c
index ec0abf823995..ee1e8b47496a 100644
--- a/drivers/net/wireless/ath/ath9k/recv.c
+++ b/drivers/net/wireless/ath/ath9k/recv.c
@@ -306,7 +306,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
306 sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN, 306 sc->rx.bufsize = roundup(IEEE80211_MAX_MPDU_LEN,
307 min(sc->common.cachelsz, (u16)64)); 307 min(sc->common.cachelsz, (u16)64));
308 308
309 DPRINTF(sc, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n", 309 DPRINTF(sc->sc_ah, ATH_DBG_CONFIG, "cachelsz %u rxbufsize %u\n",
310 sc->common.cachelsz, sc->rx.bufsize); 310 sc->common.cachelsz, sc->rx.bufsize);
311 311
312 /* Initialize rx descriptors */ 312 /* Initialize rx descriptors */
@@ -314,7 +314,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
314 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf, 314 error = ath_descdma_setup(sc, &sc->rx.rxdma, &sc->rx.rxbuf,
315 "rx", nbufs, 1); 315 "rx", nbufs, 1);
316 if (error != 0) { 316 if (error != 0) {
317 DPRINTF(sc, ATH_DBG_FATAL, 317 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
318 "failed to allocate rx descriptors: %d\n", error); 318 "failed to allocate rx descriptors: %d\n", error);
319 goto err; 319 goto err;
320 } 320 }
@@ -334,7 +334,7 @@ int ath_rx_init(struct ath_softc *sc, int nbufs)
334 bf->bf_buf_addr))) { 334 bf->bf_buf_addr))) {
335 dev_kfree_skb_any(skb); 335 dev_kfree_skb_any(skb);
336 bf->bf_mpdu = NULL; 336 bf->bf_mpdu = NULL;
337 DPRINTF(sc, ATH_DBG_FATAL, 337 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
338 "dma_mapping_error() on RX init\n"); 338 "dma_mapping_error() on RX init\n");
339 error = -ENOMEM; 339 error = -ENOMEM;
340 goto err; 340 goto err;
@@ -539,7 +539,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
539 539
540 if (sc->sc_flags & SC_OP_BEACON_SYNC) { 540 if (sc->sc_flags & SC_OP_BEACON_SYNC) {
541 sc->sc_flags &= ~SC_OP_BEACON_SYNC; 541 sc->sc_flags &= ~SC_OP_BEACON_SYNC;
542 DPRINTF(sc, ATH_DBG_PS, "Reconfigure Beacon timers based on " 542 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Reconfigure Beacon timers based on "
543 "timestamp from the AP\n"); 543 "timestamp from the AP\n");
544 ath_beacon_config(sc, NULL); 544 ath_beacon_config(sc, NULL);
545 } 545 }
@@ -552,7 +552,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
552 * a backup trigger for returning into NETWORK SLEEP state, 552 * a backup trigger for returning into NETWORK SLEEP state,
553 * so we are waiting for it as well. 553 * so we are waiting for it as well.
554 */ 554 */
555 DPRINTF(sc, ATH_DBG_PS, "Received DTIM beacon indicating " 555 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Received DTIM beacon indicating "
556 "buffered broadcast/multicast frame(s)\n"); 556 "buffered broadcast/multicast frame(s)\n");
557 sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON; 557 sc->sc_flags |= SC_OP_WAIT_FOR_CAB | SC_OP_WAIT_FOR_BEACON;
558 return; 558 return;
@@ -565,7 +565,7 @@ static void ath_rx_ps_beacon(struct ath_softc *sc, struct sk_buff *skb)
565 * been delivered. 565 * been delivered.
566 */ 566 */
567 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; 567 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
568 DPRINTF(sc, ATH_DBG_PS, "PS wait for CAB frames timed out\n"); 568 DPRINTF(sc->sc_ah, ATH_DBG_PS, "PS wait for CAB frames timed out\n");
569 } 569 }
570} 570}
571 571
@@ -589,13 +589,13 @@ static void ath_rx_ps(struct ath_softc *sc, struct sk_buff *skb)
589 * point. 589 * point.
590 */ 590 */
591 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB; 591 sc->sc_flags &= ~SC_OP_WAIT_FOR_CAB;
592 DPRINTF(sc, ATH_DBG_PS, "All PS CAB frames received, back to " 592 DPRINTF(sc->sc_ah, ATH_DBG_PS, "All PS CAB frames received, back to "
593 "sleep\n"); 593 "sleep\n");
594 } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) && 594 } else if ((sc->sc_flags & SC_OP_WAIT_FOR_PSPOLL_DATA) &&
595 !is_multicast_ether_addr(hdr->addr1) && 595 !is_multicast_ether_addr(hdr->addr1) &&
596 !ieee80211_has_morefrags(hdr->frame_control)) { 596 !ieee80211_has_morefrags(hdr->frame_control)) {
597 sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA; 597 sc->sc_flags &= ~SC_OP_WAIT_FOR_PSPOLL_DATA;
598 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " 598 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Going back to sleep after having "
599 "received PS-Poll data (0x%x)\n", 599 "received PS-Poll data (0x%x)\n",
600 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 600 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
601 SC_OP_WAIT_FOR_CAB | 601 SC_OP_WAIT_FOR_CAB |
@@ -811,7 +811,7 @@ int ath_rx_tasklet(struct ath_softc *sc, int flush)
811 bf->bf_buf_addr))) { 811 bf->bf_buf_addr))) {
812 dev_kfree_skb_any(requeue_skb); 812 dev_kfree_skb_any(requeue_skb);
813 bf->bf_mpdu = NULL; 813 bf->bf_mpdu = NULL;
814 DPRINTF(sc, ATH_DBG_FATAL, 814 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
815 "dma_mapping_error() on RX\n"); 815 "dma_mapping_error() on RX\n");
816 ath_rx_send_to_mac80211(sc, skb, &rx_status); 816 ath_rx_send_to_mac80211(sc, skb, &rx_status);
817 break; 817 break;
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 42551a48c8ac..ddd3062186a7 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -854,7 +854,7 @@ struct ath_txq *ath_txq_setup(struct ath_softc *sc, int qtype, int subtype)
854 return NULL; 854 return NULL;
855 } 855 }
856 if (qnum >= ARRAY_SIZE(sc->tx.txq)) { 856 if (qnum >= ARRAY_SIZE(sc->tx.txq)) {
857 DPRINTF(sc, ATH_DBG_FATAL, 857 DPRINTF(ah, ATH_DBG_FATAL,
858 "qnum %u out of range, max %u!\n", 858 "qnum %u out of range, max %u!\n",
859 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq)); 859 qnum, (unsigned int)ARRAY_SIZE(sc->tx.txq));
860 ath9k_hw_releasetxqueue(ah, qnum); 860 ath9k_hw_releasetxqueue(ah, qnum);
@@ -884,7 +884,7 @@ int ath_tx_get_qnum(struct ath_softc *sc, int qtype, int haltype)
884 switch (qtype) { 884 switch (qtype) {
885 case ATH9K_TX_QUEUE_DATA: 885 case ATH9K_TX_QUEUE_DATA:
886 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 886 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
887 DPRINTF(sc, ATH_DBG_FATAL, 887 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
888 "HAL AC %u out of range, max %zu!\n", 888 "HAL AC %u out of range, max %zu!\n",
889 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 889 haltype, ARRAY_SIZE(sc->tx.hwq_map));
890 return -1; 890 return -1;
@@ -914,7 +914,7 @@ struct ath_txq *ath_test_get_txq(struct ath_softc *sc, struct sk_buff *skb)
914 spin_lock_bh(&txq->axq_lock); 914 spin_lock_bh(&txq->axq_lock);
915 915
916 if (txq->axq_depth >= (ATH_TXBUF - 20)) { 916 if (txq->axq_depth >= (ATH_TXBUF - 20)) {
917 DPRINTF(sc, ATH_DBG_XMIT, 917 DPRINTF(sc->sc_ah, ATH_DBG_XMIT,
918 "TX queue: %d is full, depth: %d\n", 918 "TX queue: %d is full, depth: %d\n",
919 qnum, txq->axq_depth); 919 qnum, txq->axq_depth);
920 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb)); 920 ieee80211_stop_queue(sc->hw, skb_get_queue_mapping(skb));
@@ -955,7 +955,7 @@ int ath_txq_update(struct ath_softc *sc, int qnum,
955 qi.tqi_readyTime = qinfo->tqi_readyTime; 955 qi.tqi_readyTime = qinfo->tqi_readyTime;
956 956
957 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) { 957 if (!ath9k_hw_set_txq_props(ah, qnum, &qi)) {
958 DPRINTF(sc, ATH_DBG_FATAL, 958 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
959 "Unable to update hardware queue %u!\n", qnum); 959 "Unable to update hardware queue %u!\n", qnum);
960 error = -EIO; 960 error = -EIO;
961 } else { 961 } else {
@@ -1076,12 +1076,12 @@ void ath_drain_all_txq(struct ath_softc *sc, bool retry_tx)
1076 if (npend) { 1076 if (npend) {
1077 int r; 1077 int r;
1078 1078
1079 DPRINTF(sc, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n"); 1079 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "Unable to stop TxDMA. Reset HAL!\n");
1080 1080
1081 spin_lock_bh(&sc->sc_resetlock); 1081 spin_lock_bh(&sc->sc_resetlock);
1082 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true); 1082 r = ath9k_hw_reset(ah, sc->sc_ah->curchan, true);
1083 if (r) 1083 if (r)
1084 DPRINTF(sc, ATH_DBG_FATAL, 1084 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1085 "Unable to reset hardware; reset status %d\n", 1085 "Unable to reset hardware; reset status %d\n",
1086 r); 1086 r);
1087 spin_unlock_bh(&sc->sc_resetlock); 1087 spin_unlock_bh(&sc->sc_resetlock);
@@ -1147,7 +1147,7 @@ int ath_tx_setup(struct ath_softc *sc, int haltype)
1147 struct ath_txq *txq; 1147 struct ath_txq *txq;
1148 1148
1149 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) { 1149 if (haltype >= ARRAY_SIZE(sc->tx.hwq_map)) {
1150 DPRINTF(sc, ATH_DBG_FATAL, 1150 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1151 "HAL AC %u out of range, max %zu!\n", 1151 "HAL AC %u out of range, max %zu!\n",
1152 haltype, ARRAY_SIZE(sc->tx.hwq_map)); 1152 haltype, ARRAY_SIZE(sc->tx.hwq_map));
1153 return 0; 1153 return 0;
@@ -1188,17 +1188,17 @@ static void ath_tx_txqaddbuf(struct ath_softc *sc, struct ath_txq *txq,
1188 txq->axq_depth++; 1188 txq->axq_depth++;
1189 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list); 1189 txq->axq_linkbuf = list_entry(txq->axq_q.prev, struct ath_buf, list);
1190 1190
1191 DPRINTF(sc, ATH_DBG_QUEUE, 1191 DPRINTF(sc->sc_ah, ATH_DBG_QUEUE,
1192 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth); 1192 "qnum: %d, txq depth: %d\n", txq->axq_qnum, txq->axq_depth);
1193 1193
1194 if (txq->axq_link == NULL) { 1194 if (txq->axq_link == NULL) {
1195 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr); 1195 ath9k_hw_puttxbuf(ah, txq->axq_qnum, bf->bf_daddr);
1196 DPRINTF(sc, ATH_DBG_XMIT, 1196 DPRINTF(sc->sc_ah, ATH_DBG_XMIT,
1197 "TXDP[%u] = %llx (%p)\n", 1197 "TXDP[%u] = %llx (%p)\n",
1198 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc); 1198 txq->axq_qnum, ito64(bf->bf_daddr), bf->bf_desc);
1199 } else { 1199 } else {
1200 *txq->axq_link = bf->bf_daddr; 1200 *txq->axq_link = bf->bf_daddr;
1201 DPRINTF(sc, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n", 1201 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "link[%u] (%p)=%llx (%p)\n",
1202 txq->axq_qnum, txq->axq_link, 1202 txq->axq_qnum, txq->axq_link,
1203 ito64(bf->bf_daddr), bf->bf_desc); 1203 ito64(bf->bf_daddr), bf->bf_desc);
1204 } 1204 }
@@ -1587,7 +1587,8 @@ static int ath_tx_setup_buffer(struct ieee80211_hw *hw, struct ath_buf *bf,
1587 bf->bf_mpdu = NULL; 1587 bf->bf_mpdu = NULL;
1588 kfree(tx_info_priv); 1588 kfree(tx_info_priv);
1589 tx_info->rate_driver_data[0] = NULL; 1589 tx_info->rate_driver_data[0] = NULL;
1590 DPRINTF(sc, ATH_DBG_FATAL, "dma_mapping_error() on TX\n"); 1590 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
1591 "dma_mapping_error() on TX\n");
1591 return -ENOMEM; 1592 return -ENOMEM;
1592 } 1593 }
1593 1594
@@ -1674,7 +1675,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1674 1675
1675 bf = ath_tx_get_buffer(sc); 1676 bf = ath_tx_get_buffer(sc);
1676 if (!bf) { 1677 if (!bf) {
1677 DPRINTF(sc, ATH_DBG_XMIT, "TX buffers are full\n"); 1678 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX buffers are full\n");
1678 return -1; 1679 return -1;
1679 } 1680 }
1680 1681
@@ -1682,7 +1683,7 @@ int ath_tx_start(struct ieee80211_hw *hw, struct sk_buff *skb,
1682 if (unlikely(r)) { 1683 if (unlikely(r)) {
1683 struct ath_txq *txq = txctl->txq; 1684 struct ath_txq *txq = txctl->txq;
1684 1685
1685 DPRINTF(sc, ATH_DBG_FATAL, "TX mem alloc failure\n"); 1686 DPRINTF(sc->sc_ah, ATH_DBG_FATAL, "TX mem alloc failure\n");
1686 1687
1687 /* upon ath_tx_processq() this TX queue will be resumed, we 1688 /* upon ath_tx_processq() this TX queue will be resumed, we
1688 * guarantee this will happen by knowing beforehand that 1689 * guarantee this will happen by knowing beforehand that
@@ -1736,7 +1737,8 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1736 if (hdrlen & 3) { 1737 if (hdrlen & 3) {
1737 padsize = hdrlen % 4; 1738 padsize = hdrlen % 4;
1738 if (skb_headroom(skb) < padsize) { 1739 if (skb_headroom(skb) < padsize) {
1739 DPRINTF(sc, ATH_DBG_XMIT, "TX CABQ padding failed\n"); 1740 DPRINTF(sc->sc_ah, ATH_DBG_XMIT,
1741 "TX CABQ padding failed\n");
1740 dev_kfree_skb_any(skb); 1742 dev_kfree_skb_any(skb);
1741 return; 1743 return;
1742 } 1744 }
@@ -1746,10 +1748,10 @@ void ath_tx_cabq(struct ieee80211_hw *hw, struct sk_buff *skb)
1746 1748
1747 txctl.txq = sc->beacon.cabq; 1749 txctl.txq = sc->beacon.cabq;
1748 1750
1749 DPRINTF(sc, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb); 1751 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "transmitting CABQ packet, skb: %p\n", skb);
1750 1752
1751 if (ath_tx_start(hw, skb, &txctl) != 0) { 1753 if (ath_tx_start(hw, skb, &txctl) != 0) {
1752 DPRINTF(sc, ATH_DBG_XMIT, "CABQ TX failed\n"); 1754 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "CABQ TX failed\n");
1753 goto exit; 1755 goto exit;
1754 } 1756 }
1755 1757
@@ -1771,7 +1773,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1771 int hdrlen, padsize; 1773 int hdrlen, padsize;
1772 int frame_type = ATH9K_NOT_INTERNAL; 1774 int frame_type = ATH9K_NOT_INTERNAL;
1773 1775
1774 DPRINTF(sc, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb); 1776 DPRINTF(sc->sc_ah, ATH_DBG_XMIT, "TX complete: skb: %p\n", skb);
1775 1777
1776 if (tx_info_priv) { 1778 if (tx_info_priv) {
1777 hw = tx_info_priv->aphy->hw; 1779 hw = tx_info_priv->aphy->hw;
@@ -1805,7 +1807,7 @@ static void ath_tx_complete(struct ath_softc *sc, struct sk_buff *skb,
1805 1807
1806 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) { 1808 if (sc->sc_flags & SC_OP_WAIT_FOR_TX_ACK) {
1807 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK; 1809 sc->sc_flags &= ~SC_OP_WAIT_FOR_TX_ACK;
1808 DPRINTF(sc, ATH_DBG_PS, "Going back to sleep after having " 1810 DPRINTF(sc->sc_ah, ATH_DBG_PS, "Going back to sleep after having "
1809 "received TX status (0x%x)\n", 1811 "received TX status (0x%x)\n",
1810 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON | 1812 sc->sc_flags & (SC_OP_WAIT_FOR_BEACON |
1811 SC_OP_WAIT_FOR_CAB | 1813 SC_OP_WAIT_FOR_CAB |
@@ -1942,7 +1944,7 @@ static void ath_tx_processq(struct ath_softc *sc, struct ath_txq *txq)
1942 int txok; 1944 int txok;
1943 int status; 1945 int status;
1944 1946
1945 DPRINTF(sc, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n", 1947 DPRINTF(ah, ATH_DBG_QUEUE, "tx queue %d (%x), link %p\n",
1946 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum), 1948 txq->axq_qnum, ath9k_hw_gettxbuf(sc->sc_ah, txq->axq_qnum),
1947 txq->axq_link); 1949 txq->axq_link);
1948 1950
@@ -2064,7 +2066,7 @@ static void ath_tx_complete_poll_work(struct work_struct *work)
2064 } 2066 }
2065 2067
2066 if (needreset) { 2068 if (needreset) {
2067 DPRINTF(sc, ATH_DBG_RESET, "tx hung, resetting the chip\n"); 2069 DPRINTF(sc->sc_ah, ATH_DBG_RESET, "tx hung, resetting the chip\n");
2068 ath_reset(sc, false); 2070 ath_reset(sc, false);
2069 } 2071 }
2070 2072
@@ -2100,7 +2102,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2100 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf, 2102 error = ath_descdma_setup(sc, &sc->tx.txdma, &sc->tx.txbuf,
2101 "tx", nbufs, 1); 2103 "tx", nbufs, 1);
2102 if (error != 0) { 2104 if (error != 0) {
2103 DPRINTF(sc, ATH_DBG_FATAL, 2105 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
2104 "Failed to allocate tx descriptors: %d\n", error); 2106 "Failed to allocate tx descriptors: %d\n", error);
2105 goto err; 2107 goto err;
2106 } 2108 }
@@ -2108,7 +2110,7 @@ int ath_tx_init(struct ath_softc *sc, int nbufs)
2108 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf, 2110 error = ath_descdma_setup(sc, &sc->beacon.bdma, &sc->beacon.bbuf,
2109 "beacon", ATH_BCBUF, 1); 2111 "beacon", ATH_BCBUF, 1);
2110 if (error != 0) { 2112 if (error != 0) {
2111 DPRINTF(sc, ATH_DBG_FATAL, 2113 DPRINTF(sc->sc_ah, ATH_DBG_FATAL,
2112 "Failed to allocate beacon descriptors: %d\n", error); 2114 "Failed to allocate beacon descriptors: %d\n", error);
2113 goto err; 2115 goto err;
2114 } 2116 }
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-20 17:36:38 -0500