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-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro-gic.S89
-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro-intc.S39
-rw-r--r--arch/arm/mach-shmobile/include/mach/entry-macro.S104
3 files changed, 132 insertions, 100 deletions
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro-gic.S b/arch/arm/mach-shmobile/include/mach/entry-macro-gic.S
new file mode 100644
index 000000000000..50b1f16d54a2
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro-gic.S
@@ -0,0 +1,89 @@
1/*
2 * Copyright (C) 2010 Renesas Solutions Corp.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
16 */
17#include <mach/hardware.h>
18#include <asm/hardware/gic.h>
19
20 .macro disable_fiq
21 .endm
22
23 .macro get_irqnr_preamble, base, tmp
24 ldr \base, =(0xf0000100)
25 .endm
26
27 .macro arch_ret_to_user, tmp1, tmp2
28 .endm
29
30 /*
31 * The interrupt numbering scheme is defined in the
32 * interrupt controller spec. To wit:
33 *
34 * Interrupts 0-15 are IPI
35 * 16-28 are reserved
36 * 29-31 are local. We allow 30 to be used for the watchdog.
37 * 32-1020 are global
38 * 1021-1022 are reserved
39 * 1023 is "spurious" (no interrupt)
40 *
41 * For now, we ignore all local interrupts so only return an
42 * interrupt if it's between 30 and 1020. The test_for_ipi
43 * routine below will pick up on IPIs.
44 *
45 * A simple read from the controller will tell us the number of
46 * the highest priority enabled interrupt. We then just need to
47 * check whether it is in the valid range for an IRQ (30-1020
48 * inclusive).
49 */
50
51 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
52
53 ldr \irqstat, [\base, #GIC_CPU_INTACK]
54 /* bits 12-10 = src CPU, 9-0 = int # */
55
56 ldr \tmp, =1021
57 bic \irqnr, \irqstat, #0x1c00
58 cmp \irqnr, #29
59 cmpcc \irqnr, \irqnr
60 cmpne \irqnr, \tmp
61 cmpcs \irqnr, \irqnr
62
63 .endm
64
65 /*
66 * We assume that irqstat (the raw value of the IRQ acknowledge
67 * register) is preserved from the macro above.
68 * If there is an IPI, we immediately signal end of interrupt on the
69 * controller, since this requires the original irqstat value which
70 * we won't easily be able to recreate later.
71 */
72
73 .macro test_for_ipi, irqnr, irqstat, base, tmp
74 bic \irqnr, \irqstat, #0x1c00
75 cmp \irqnr, #16
76 strcc \irqstat, [\base, #GIC_CPU_EOI]
77 cmpcs \irqnr, \irqnr
78 .endm
79
80 /* As above, this assumes that irqstat and base are preserved.. */
81
82 .macro test_for_ltirq, irqnr, irqstat, base, tmp
83 bic \irqnr, \irqstat, #0x1c00
84 mov \tmp, #0
85 cmp \irqnr, #29
86 moveq \tmp, #1
87 streq \irqstat, [\base, #GIC_CPU_EOI]
88 cmp \tmp, #0
89 .endm
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro-intc.S b/arch/arm/mach-shmobile/include/mach/entry-macro-intc.S
new file mode 100644
index 000000000000..a285d13c7416
--- /dev/null
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro-intc.S
@@ -0,0 +1,39 @@
1/*
2 * Copyright (C) 2008 Renesas Solutions Corp.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; version 2 of the License.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
16 */
17#include <mach/hardware.h>
18#include <mach/irqs.h>
19
20 .macro disable_fiq
21 .endm
22
23 .macro get_irqnr_preamble, base, tmp
24 ldr \base, =INTFLGA
25 .endm
26
27 .macro arch_ret_to_user, tmp1, tmp2
28 .endm
29
30 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
31 ldr \irqnr, [\base]
32 cmp \irqnr, #0
33 beq 1000f
34 /* intevt to irq number */
35 lsr \irqnr, \irqnr, #0x5
36 subs \irqnr, \irqnr, #16
37
381000:
39 .endm
diff --git a/arch/arm/mach-shmobile/include/mach/entry-macro.S b/arch/arm/mach-shmobile/include/mach/entry-macro.S
index c0c264366d7a..26e401167605 100644
--- a/arch/arm/mach-shmobile/include/mach/entry-macro.S
+++ b/arch/arm/mach-shmobile/include/mach/entry-macro.S
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (C) 2008 Renesas Solutions Corp. 2 * Copyright (C) 2010 Paul Mundt
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify 4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by 5 * it under the terms of the GNU General Public License as published by
@@ -14,104 +14,8 @@
14 * along with this program; if not, write to the Free Software 14 * along with this program; if not, write to the Free Software
15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA 15 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
16 */ 16 */
17#include <mach/hardware.h> 17#if defined(CONFIG_ARM_GIC)
18#include <mach/irqs.h> 18#include <mach/entry-macro-gic.S>
19
20 .macro disable_fiq
21 .endm
22
23#if !defined(CONFIG_ARCH_SH73A0)
24 .macro get_irqnr_preamble, base, tmp
25 ldr \base, =INTFLGA
26 .endm
27
28 .macro arch_ret_to_user, tmp1, tmp2
29 .endm
30
31 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
32 ldr \irqnr, [\base]
33 cmp \irqnr, #0
34 beq 1000f
35 /* intevt to irq number */
36 lsr \irqnr, \irqnr, #0x5
37 subs \irqnr, \irqnr, #16
38
391000:
40 .endm
41#else 19#else
42/* 20#include <mach/entry-macro-intc.S>
43 * arch/arm/mach-realview/include/mach/entry-macro.S
44 *
45 * Low-level IRQ helper macros for RealView platforms
46 *
47 * This file is licensed under the terms of the GNU General Public
48 * License version 2. This program is licensed "as is" without any
49 * warranty of any kind, whether express or implied.
50 */
51#include <asm/hardware/gic.h>
52
53 .macro get_irqnr_preamble, base, tmp
54 ldr \base, =(0xf0000100)
55 .endm
56
57 .macro arch_ret_to_user, tmp1, tmp2
58 .endm
59
60/*
61 * The interrupt numbering scheme is defined in the
62 * interrupt controller spec. To wit:
63 *
64 * Interrupts 0-15 are IPI
65 * 16-28 are reserved
66 * 29-31 are local. We allow 30 to be used for the watchdog.
67 * 32-1020 are global
68 * 1021-1022 are reserved
69 * 1023 is "spurious" (no interrupt)
70 *
71 * For now, we ignore all local interrupts so only return an interrupt if it's
72 * between 30 and 1020. The test_for_ipi routine below will pick up on IPIs.
73 *
74 * A simple read from the controller will tell us the number of the highest
75 * priority enabled interrupt. We then just need to check whether it is in the
76 * valid range for an IRQ (30-1020 inclusive).
77 */
78
79 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
80
81 ldr \irqstat, [\base, #GIC_CPU_INTACK]
82 /* bits 12-10 = src CPU, 9-0 = int # */
83
84 ldr \tmp, =1021
85 bic \irqnr, \irqstat, #0x1c00
86 cmp \irqnr, #29
87 cmpcc \irqnr, \irqnr
88 cmpne \irqnr, \tmp
89 cmpcs \irqnr, \irqnr
90
91 .endm
92
93 /* We assume that irqstat (the raw value of the IRQ acknowledge
94 * register) is preserved from the macro above.
95 * If there is an IPI, we immediately signal end of interrupt on the
96 * controller, since this requires the original irqstat value which
97 * we won't easily be able to recreate later.
98 */
99
100 .macro test_for_ipi, irqnr, irqstat, base, tmp
101 bic \irqnr, \irqstat, #0x1c00
102 cmp \irqnr, #16
103 strcc \irqstat, [\base, #GIC_CPU_EOI]
104 cmpcs \irqnr, \irqnr
105 .endm
106
107 /* As above, this assumes that irqstat and base are preserved.. */
108
109 .macro test_for_ltirq, irqnr, irqstat, base, tmp
110 bic \irqnr, \irqstat, #0x1c00
111 mov \tmp, #0
112 cmp \irqnr, #29
113 moveq \tmp, #1
114 streq \irqstat, [\base, #GIC_CPU_EOI]
115 cmp \tmp, #0
116 .endm
117#endif 21#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-18 02:13:27 -0500