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-rw-r--r--drivers/clk/samsung/clk-exynos5420.c85
-rw-r--r--include/dt-bindings/clock/exynos5420.h1
2 files changed, 55 insertions, 31 deletions
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 9d7d7eed03fd..61eccf0dd72f 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -890,8 +890,6 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
890 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0), 890 GATE_BUS_TOP, 9, CLK_IGNORE_UNUSED, 0),
891 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen", 891 GATE(0, "aclk66_psgen", "mout_user_aclk66_psgen",
892 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0), 892 GATE_BUS_TOP, 10, CLK_IGNORE_UNUSED, 0),
893 GATE(CLK_ACLK66_PERIC, "aclk66_peric", "mout_user_aclk66_peric",
894 GATE_BUS_TOP, 11, CLK_IGNORE_UNUSED, 0),
895 GATE(0, "aclk266_isp", "mout_user_aclk266_isp", 893 GATE(0, "aclk266_isp", "mout_user_aclk266_isp",
896 GATE_BUS_TOP, 13, 0, 0), 894 GATE_BUS_TOP, 13, 0, 0),
897 GATE(0, "aclk166", "mout_user_aclk166", 895 GATE(0, "aclk166", "mout_user_aclk166",
@@ -994,34 +992,61 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
994 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0), 992 SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
995 993
996 /* PERIC Block */ 994 /* PERIC Block */
997 GATE(CLK_UART0, "uart0", "aclk66_peric", GATE_IP_PERIC, 0, 0, 0), 995 GATE(CLK_UART0, "uart0", "mout_user_aclk66_peric",
998 GATE(CLK_UART1, "uart1", "aclk66_peric", GATE_IP_PERIC, 1, 0, 0), 996 GATE_IP_PERIC, 0, 0, 0),
999 GATE(CLK_UART2, "uart2", "aclk66_peric", GATE_IP_PERIC, 2, 0, 0), 997 GATE(CLK_UART1, "uart1", "mout_user_aclk66_peric",
1000 GATE(CLK_UART3, "uart3", "aclk66_peric", GATE_IP_PERIC, 3, 0, 0), 998 GATE_IP_PERIC, 1, 0, 0),
1001 GATE(CLK_I2C0, "i2c0", "aclk66_peric", GATE_IP_PERIC, 6, 0, 0), 999 GATE(CLK_UART2, "uart2", "mout_user_aclk66_peric",
1002 GATE(CLK_I2C1, "i2c1", "aclk66_peric", GATE_IP_PERIC, 7, 0, 0), 1000 GATE_IP_PERIC, 2, 0, 0),
1003 GATE(CLK_I2C2, "i2c2", "aclk66_peric", GATE_IP_PERIC, 8, 0, 0), 1001 GATE(CLK_UART3, "uart3", "mout_user_aclk66_peric",
1004 GATE(CLK_I2C3, "i2c3", "aclk66_peric", GATE_IP_PERIC, 9, 0, 0), 1002 GATE_IP_PERIC, 3, 0, 0),
1005 GATE(CLK_USI0, "usi0", "aclk66_peric", GATE_IP_PERIC, 10, 0, 0), 1003 GATE(CLK_I2C0, "i2c0", "mout_user_aclk66_peric",
1006 GATE(CLK_USI1, "usi1", "aclk66_peric", GATE_IP_PERIC, 11, 0, 0), 1004 GATE_IP_PERIC, 6, 0, 0),
1007 GATE(CLK_USI2, "usi2", "aclk66_peric", GATE_IP_PERIC, 12, 0, 0), 1005 GATE(CLK_I2C1, "i2c1", "mout_user_aclk66_peric",
1008 GATE(CLK_USI3, "usi3", "aclk66_peric", GATE_IP_PERIC, 13, 0, 0), 1006 GATE_IP_PERIC, 7, 0, 0),
1009 GATE(CLK_I2C_HDMI, "i2c_hdmi", "aclk66_peric", GATE_IP_PERIC, 14, 0, 0), 1007 GATE(CLK_I2C2, "i2c2", "mout_user_aclk66_peric",
1010 GATE(CLK_TSADC, "tsadc", "aclk66_peric", GATE_IP_PERIC, 15, 0, 0), 1008 GATE_IP_PERIC, 8, 0, 0),
1011 GATE(CLK_SPI0, "spi0", "aclk66_peric", GATE_IP_PERIC, 16, 0, 0), 1009 GATE(CLK_I2C3, "i2c3", "mout_user_aclk66_peric",
1012 GATE(CLK_SPI1, "spi1", "aclk66_peric", GATE_IP_PERIC, 17, 0, 0), 1010 GATE_IP_PERIC, 9, 0, 0),
1013 GATE(CLK_SPI2, "spi2", "aclk66_peric", GATE_IP_PERIC, 18, 0, 0), 1011 GATE(CLK_USI0, "usi0", "mout_user_aclk66_peric",
1014 GATE(CLK_I2S1, "i2s1", "aclk66_peric", GATE_IP_PERIC, 20, 0, 0), 1012 GATE_IP_PERIC, 10, 0, 0),
1015 GATE(CLK_I2S2, "i2s2", "aclk66_peric", GATE_IP_PERIC, 21, 0, 0), 1013 GATE(CLK_USI1, "usi1", "mout_user_aclk66_peric",
1016 GATE(CLK_PCM1, "pcm1", "aclk66_peric", GATE_IP_PERIC, 22, 0, 0), 1014 GATE_IP_PERIC, 11, 0, 0),
1017 GATE(CLK_PCM2, "pcm2", "aclk66_peric", GATE_IP_PERIC, 23, 0, 0), 1015 GATE(CLK_USI2, "usi2", "mout_user_aclk66_peric",
1018 GATE(CLK_PWM, "pwm", "aclk66_peric", GATE_IP_PERIC, 24, 0, 0), 1016 GATE_IP_PERIC, 12, 0, 0),
1019 GATE(CLK_SPDIF, "spdif", "aclk66_peric", GATE_IP_PERIC, 26, 0, 0), 1017 GATE(CLK_USI3, "usi3", "mout_user_aclk66_peric",
1020 GATE(CLK_USI4, "usi4", "aclk66_peric", GATE_IP_PERIC, 28, 0, 0), 1018 GATE_IP_PERIC, 13, 0, 0),
1021 GATE(CLK_USI5, "usi5", "aclk66_peric", GATE_IP_PERIC, 30, 0, 0), 1019 GATE(CLK_I2C_HDMI, "i2c_hdmi", "mout_user_aclk66_peric",
1022 GATE(CLK_USI6, "usi6", "aclk66_peric", GATE_IP_PERIC, 31, 0, 0), 1020 GATE_IP_PERIC, 14, 0, 0),
1023 1021 GATE(CLK_TSADC, "tsadc", "mout_user_aclk66_peric",
1024 GATE(CLK_KEYIF, "keyif", "aclk66_peric", GATE_BUS_PERIC, 22, 0, 0), 1022 GATE_IP_PERIC, 15, 0, 0),
1023 GATE(CLK_SPI0, "spi0", "mout_user_aclk66_peric",
1024 GATE_IP_PERIC, 16, 0, 0),
1025 GATE(CLK_SPI1, "spi1", "mout_user_aclk66_peric",
1026 GATE_IP_PERIC, 17, 0, 0),
1027 GATE(CLK_SPI2, "spi2", "mout_user_aclk66_peric",
1028 GATE_IP_PERIC, 18, 0, 0),
1029 GATE(CLK_I2S1, "i2s1", "mout_user_aclk66_peric",
1030 GATE_IP_PERIC, 20, 0, 0),
1031 GATE(CLK_I2S2, "i2s2", "mout_user_aclk66_peric",
1032 GATE_IP_PERIC, 21, 0, 0),
1033 GATE(CLK_PCM1, "pcm1", "mout_user_aclk66_peric",
1034 GATE_IP_PERIC, 22, 0, 0),
1035 GATE(CLK_PCM2, "pcm2", "mout_user_aclk66_peric",
1036 GATE_IP_PERIC, 23, 0, 0),
1037 GATE(CLK_PWM, "pwm", "mout_user_aclk66_peric",
1038 GATE_IP_PERIC, 24, 0, 0),
1039 GATE(CLK_SPDIF, "spdif", "mout_user_aclk66_peric",
1040 GATE_IP_PERIC, 26, 0, 0),
1041 GATE(CLK_USI4, "usi4", "mout_user_aclk66_peric",
1042 GATE_IP_PERIC, 28, 0, 0),
1043 GATE(CLK_USI5, "usi5", "mout_user_aclk66_peric",
1044 GATE_IP_PERIC, 30, 0, 0),
1045 GATE(CLK_USI6, "usi6", "mout_user_aclk66_peric",
1046 GATE_IP_PERIC, 31, 0, 0),
1047
1048 GATE(CLK_KEYIF, "keyif", "mout_user_aclk66_peric",
1049 GATE_BUS_PERIC, 22, 0, 0),
1025 1050
1026 /* PERIS Block */ 1051 /* PERIS Block */
1027 GATE(CLK_CHIPID, "chipid", "aclk66_psgen", 1052 GATE(CLK_CHIPID, "chipid", "aclk66_psgen",
diff --git a/include/dt-bindings/clock/exynos5420.h b/include/dt-bindings/clock/exynos5420.h
index 97dcb89d37d3..14e1c8f9640c 100644
--- a/include/dt-bindings/clock/exynos5420.h
+++ b/include/dt-bindings/clock/exynos5420.h
@@ -63,7 +63,6 @@
63#define CLK_SCLK_MPHY_IXTAL24 161 63#define CLK_SCLK_MPHY_IXTAL24 161
64 64
65/* gate clocks */ 65/* gate clocks */
66#define CLK_ACLK66_PERIC 256
67#define CLK_UART0 257 66#define CLK_UART0 257
68#define CLK_UART1 258 67#define CLK_UART1 258
69#define CLK_UART2 259 68#define CLK_UART2 259
generated by cgit v1.2.2 (git 2.25.0) at 2025-05-31 18:01:34 -0400