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-rw-r--r--drivers/media/video/Kconfig6
-rw-r--r--drivers/media/video/Makefile1
-rw-r--r--drivers/media/video/sr030pc30.c893
-rw-r--r--include/media/sr030pc30.h21
4 files changed, 921 insertions, 0 deletions
diff --git a/drivers/media/video/Kconfig b/drivers/media/video/Kconfig
index 8db8c6fd6fb1..2d4226710ed5 100644
--- a/drivers/media/video/Kconfig
+++ b/drivers/media/video/Kconfig
@@ -706,6 +706,12 @@ config VIDEO_CAFE_CCIC
706 CMOS camera controller. This is the controller found on first- 706 CMOS camera controller. This is the controller found on first-
707 generation OLPC systems. 707 generation OLPC systems.
708 708
709config VIDEO_SR030PC30
710 tristate "SR030PC30 VGA camera sensor support"
711 depends on I2C && VIDEO_V4L2
712 ---help---
713 This driver supports SR030PC30 VGA camera from Siliconfile
714
709config SOC_CAMERA 715config SOC_CAMERA
710 tristate "SoC camera support" 716 tristate "SoC camera support"
711 depends on VIDEO_V4L2 && HAS_DMA && I2C 717 depends on VIDEO_V4L2 && HAS_DMA && I2C
diff --git a/drivers/media/video/Makefile b/drivers/media/video/Makefile
index 4f0952a758da..d5e49ddbf9dd 100644
--- a/drivers/media/video/Makefile
+++ b/drivers/media/video/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_VIDEO_OV7670) += ov7670.o
71obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o 71obj-$(CONFIG_VIDEO_TCM825X) += tcm825x.o
72obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o 72obj-$(CONFIG_VIDEO_TVEEPROM) += tveeprom.o
73obj-$(CONFIG_VIDEO_MT9V011) += mt9v011.o 73obj-$(CONFIG_VIDEO_MT9V011) += mt9v011.o
74obj-$(CONFIG_VIDEO_SR030PC30) += sr030pc30.o
74 75
75obj-$(CONFIG_SOC_CAMERA_IMX074) += imx074.o 76obj-$(CONFIG_SOC_CAMERA_IMX074) += imx074.o
76obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o 77obj-$(CONFIG_SOC_CAMERA_MT9M001) += mt9m001.o
diff --git a/drivers/media/video/sr030pc30.c b/drivers/media/video/sr030pc30.c
new file mode 100644
index 000000000000..f82e1f30988b
--- /dev/null
+++ b/drivers/media/video/sr030pc30.c
@@ -0,0 +1,893 @@
1/*
2 * Driver for SiliconFile SR030PC30 VGA (1/10-Inch) Image Sensor with ISP
3 *
4 * Copyright (C) 2010 Samsung Electronics Co., Ltd
5 * Author: Sylwester Nawrocki, s.nawrocki@samsung.com
6 *
7 * Based on original driver authored by Dongsoo Nathaniel Kim
8 * and HeungJun Kim <riverful.kim@samsung.com>.
9 *
10 * Based on mt9v011 Micron Digital Image Sensor driver
11 * Copyright (c) 2009 Mauro Carvalho Chehab (mchehab@redhat.com)
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; either version 2 of the License, or
16 * (at your option) any later version.
17 */
18
19#include <linux/i2c.h>
20#include <linux/delay.h>
21#include <media/v4l2-device.h>
22#include <media/v4l2-subdev.h>
23#include <media/v4l2-mediabus.h>
24#include <media/sr030pc30.h>
25
26static int debug;
27module_param(debug, int, 0644);
28
29#define MODULE_NAME "SR030PC30"
30
31/*
32 * Register offsets within a page
33 * b15..b8 - page id, b7..b0 - register address
34 */
35#define POWER_CTRL_REG 0x0001
36#define PAGEMODE_REG 0x03
37#define DEVICE_ID_REG 0x0004
38#define NOON010PC30_ID 0x86
39#define SR030PC30_ID 0x8C
40#define VDO_CTL1_REG 0x0010
41#define SUBSAMPL_NONE_VGA 0
42#define SUBSAMPL_QVGA 0x10
43#define SUBSAMPL_QQVGA 0x20
44#define VDO_CTL2_REG 0x0011
45#define SYNC_CTL_REG 0x0012
46#define WIN_ROWH_REG 0x0020
47#define WIN_ROWL_REG 0x0021
48#define WIN_COLH_REG 0x0022
49#define WIN_COLL_REG 0x0023
50#define WIN_HEIGHTH_REG 0x0024
51#define WIN_HEIGHTL_REG 0x0025
52#define WIN_WIDTHH_REG 0x0026
53#define WIN_WIDTHL_REG 0x0027
54#define HBLANKH_REG 0x0040
55#define HBLANKL_REG 0x0041
56#define VSYNCH_REG 0x0042
57#define VSYNCL_REG 0x0043
58/* page 10 */
59#define ISP_CTL_REG(n) (0x1010 + (n))
60#define YOFS_REG 0x1040
61#define DARK_YOFS_REG 0x1041
62#define AG_ABRTH_REG 0x1050
63#define SAT_CTL_REG 0x1060
64#define BSAT_REG 0x1061
65#define RSAT_REG 0x1062
66#define AG_SAT_TH_REG 0x1063
67/* page 11 */
68#define ZLPF_CTRL_REG 0x1110
69#define ZLPF_CTRL2_REG 0x1112
70#define ZLPF_AGH_THR_REG 0x1121
71#define ZLPF_THR_REG 0x1160
72#define ZLPF_DYN_THR_REG 0x1160
73/* page 12 */
74#define YCLPF_CTL1_REG 0x1240
75#define YCLPF_CTL2_REG 0x1241
76#define YCLPF_THR_REG 0x1250
77#define BLPF_CTL_REG 0x1270
78#define BLPF_THR1_REG 0x1274
79#define BLPF_THR2_REG 0x1275
80/* page 14 - Lens Shading Compensation */
81#define LENS_CTRL_REG 0x1410
82#define LENS_XCEN_REG 0x1420
83#define LENS_YCEN_REG 0x1421
84#define LENS_R_COMP_REG 0x1422
85#define LENS_G_COMP_REG 0x1423
86#define LENS_B_COMP_REG 0x1424
87/* page 15 - Color correction */
88#define CMC_CTL_REG 0x1510
89#define CMC_OFSGH_REG 0x1514
90#define CMC_OFSGL_REG 0x1516
91#define CMC_SIGN_REG 0x1517
92/* Color correction coefficients */
93#define CMC_COEF_REG(n) (0x1530 + (n))
94/* Color correction offset coefficients */
95#define CMC_OFS_REG(n) (0x1540 + (n))
96/* page 16 - Gamma correction */
97#define GMA_CTL_REG 0x1610
98/* Gamma correction coefficients 0.14 */
99#define GMA_COEF_REG(n) (0x1630 + (n))
100/* page 20 - Auto Exposure */
101#define AE_CTL1_REG 0x2010
102#define AE_CTL2_REG 0x2011
103#define AE_FRM_CTL_REG 0x2020
104#define AE_FINE_CTL_REG(n) (0x2028 + (n))
105#define EXP_TIMEH_REG 0x2083
106#define EXP_TIMEM_REG 0x2084
107#define EXP_TIMEL_REG 0x2085
108#define EXP_MMINH_REG 0x2086
109#define EXP_MMINL_REG 0x2087
110#define EXP_MMAXH_REG 0x2088
111#define EXP_MMAXM_REG 0x2089
112#define EXP_MMAXL_REG 0x208A
113/* page 22 - Auto White Balance */
114#define AWB_CTL1_REG 0x2210
115#define AWB_ENABLE 0x80
116#define AWB_CTL2_REG 0x2211
117#define MWB_ENABLE 0x01
118/* RGB gain control (manual WB) when AWB_CTL1[7]=0 */
119#define AWB_RGAIN_REG 0x2280
120#define AWB_GGAIN_REG 0x2281
121#define AWB_BGAIN_REG 0x2282
122#define AWB_RMAX_REG 0x2283
123#define AWB_RMIN_REG 0x2284
124#define AWB_BMAX_REG 0x2285
125#define AWB_BMIN_REG 0x2286
126/* R, B gain range in bright light conditions */
127#define AWB_RMAXB_REG 0x2287
128#define AWB_RMINB_REG 0x2288
129#define AWB_BMAXB_REG 0x2289
130#define AWB_BMINB_REG 0x228A
131/* manual white balance, when AWB_CTL2[0]=1 */
132#define MWB_RGAIN_REG 0x22B2
133#define MWB_BGAIN_REG 0x22B3
134/* the token to mark an array end */
135#define REG_TERM 0xFFFF
136
137/* Minimum and maximum exposure time in ms */
138#define EXPOS_MIN_MS 1
139#define EXPOS_MAX_MS 125
140
141struct sr030pc30_info {
142 struct v4l2_subdev sd;
143 const struct sr030pc30_platform_data *pdata;
144 const struct sr030pc30_format *curr_fmt;
145 const struct sr030pc30_frmsize *curr_win;
146 unsigned int auto_wb:1;
147 unsigned int auto_exp:1;
148 unsigned int hflip:1;
149 unsigned int vflip:1;
150 unsigned int sleep:1;
151 unsigned int exposure;
152 u8 blue_balance;
153 u8 red_balance;
154 u8 i2c_reg_page;
155};
156
157struct sr030pc30_format {
158 enum v4l2_mbus_pixelcode code;
159 enum v4l2_colorspace colorspace;
160 u16 ispctl1_reg;
161};
162
163struct sr030pc30_frmsize {
164 u16 width;
165 u16 height;
166 int vid_ctl1;
167};
168
169struct i2c_regval {
170 u16 addr;
171 u16 val;
172};
173
174static const struct v4l2_queryctrl sr030pc30_ctrl[] = {
175 {
176 .id = V4L2_CID_AUTO_WHITE_BALANCE,
177 .type = V4L2_CTRL_TYPE_BOOLEAN,
178 .name = "Auto White Balance",
179 .minimum = 0,
180 .maximum = 1,
181 .step = 1,
182 .default_value = 1,
183 }, {
184 .id = V4L2_CID_RED_BALANCE,
185 .type = V4L2_CTRL_TYPE_INTEGER,
186 .name = "Red Balance",
187 .minimum = 0,
188 .maximum = 127,
189 .step = 1,
190 .default_value = 64,
191 .flags = 0,
192 }, {
193 .id = V4L2_CID_BLUE_BALANCE,
194 .type = V4L2_CTRL_TYPE_INTEGER,
195 .name = "Blue Balance",
196 .minimum = 0,
197 .maximum = 127,
198 .step = 1,
199 .default_value = 64,
200 }, {
201 .id = V4L2_CID_EXPOSURE_AUTO,
202 .type = V4L2_CTRL_TYPE_INTEGER,
203 .name = "Auto Exposure",
204 .minimum = 0,
205 .maximum = 1,
206 .step = 1,
207 .default_value = 1,
208 }, {
209 .id = V4L2_CID_EXPOSURE,
210 .type = V4L2_CTRL_TYPE_INTEGER,
211 .name = "Exposure",
212 .minimum = EXPOS_MIN_MS,
213 .maximum = EXPOS_MAX_MS,
214 .step = 1,
215 .default_value = 1,
216 }, {
217 }
218};
219
220/* supported resolutions */
221static const struct sr030pc30_frmsize sr030pc30_sizes[] = {
222 {
223 .width = 640,
224 .height = 480,
225 .vid_ctl1 = SUBSAMPL_NONE_VGA,
226 }, {
227 .width = 320,
228 .height = 240,
229 .vid_ctl1 = SUBSAMPL_QVGA,
230 }, {
231 .width = 160,
232 .height = 120,
233 .vid_ctl1 = SUBSAMPL_QQVGA,
234 },
235};
236
237/* supported pixel formats */
238static const struct sr030pc30_format sr030pc30_formats[] = {
239 {
240 .code = V4L2_MBUS_FMT_YUYV8_2X8,
241 .colorspace = V4L2_COLORSPACE_JPEG,
242 .ispctl1_reg = 0x03,
243 }, {
244 .code = V4L2_MBUS_FMT_YVYU8_2X8,
245 .colorspace = V4L2_COLORSPACE_JPEG,
246 .ispctl1_reg = 0x02,
247 }, {
248 .code = V4L2_MBUS_FMT_VYUY8_2X8,
249 .colorspace = V4L2_COLORSPACE_JPEG,
250 .ispctl1_reg = 0,
251 }, {
252 .code = V4L2_MBUS_FMT_UYVY8_2X8,
253 .colorspace = V4L2_COLORSPACE_JPEG,
254 .ispctl1_reg = 0x01,
255 }, {
256 .code = V4L2_MBUS_FMT_RGB565_2X8_BE,
257 .colorspace = V4L2_COLORSPACE_JPEG,
258 .ispctl1_reg = 0x40,
259 },
260};
261
262static const struct i2c_regval sr030pc30_base_regs[] = {
263 /* Window size and position within pixel matrix */
264 { WIN_ROWH_REG, 0x00 }, { WIN_ROWL_REG, 0x06 },
265 { WIN_COLH_REG, 0x00 }, { WIN_COLL_REG, 0x06 },
266 { WIN_HEIGHTH_REG, 0x01 }, { WIN_HEIGHTL_REG, 0xE0 },
267 { WIN_WIDTHH_REG, 0x02 }, { WIN_WIDTHL_REG, 0x80 },
268 { HBLANKH_REG, 0x01 }, { HBLANKL_REG, 0x50 },
269 { VSYNCH_REG, 0x00 }, { VSYNCL_REG, 0x14 },
270 { SYNC_CTL_REG, 0 },
271 /* Color corection and saturation */
272 { ISP_CTL_REG(0), 0x30 }, { YOFS_REG, 0x80 },
273 { DARK_YOFS_REG, 0x04 }, { AG_ABRTH_REG, 0x78 },
274 { SAT_CTL_REG, 0x1F }, { BSAT_REG, 0x90 },
275 { AG_SAT_TH_REG, 0xF0 }, { 0x1064, 0x80 },
276 { CMC_CTL_REG, 0x03 }, { CMC_OFSGH_REG, 0x3C },
277 { CMC_OFSGL_REG, 0x2C }, { CMC_SIGN_REG, 0x2F },
278 { CMC_COEF_REG(0), 0xCB }, { CMC_OFS_REG(0), 0x87 },
279 { CMC_COEF_REG(1), 0x61 }, { CMC_OFS_REG(1), 0x18 },
280 { CMC_COEF_REG(2), 0x16 }, { CMC_OFS_REG(2), 0x91 },
281 { CMC_COEF_REG(3), 0x23 }, { CMC_OFS_REG(3), 0x94 },
282 { CMC_COEF_REG(4), 0xCE }, { CMC_OFS_REG(4), 0x9f },
283 { CMC_COEF_REG(5), 0x2B }, { CMC_OFS_REG(5), 0x33 },
284 { CMC_COEF_REG(6), 0x01 }, { CMC_OFS_REG(6), 0x00 },
285 { CMC_COEF_REG(7), 0x34 }, { CMC_OFS_REG(7), 0x94 },
286 { CMC_COEF_REG(8), 0x75 }, { CMC_OFS_REG(8), 0x14 },
287 /* Color corection coefficients */
288 { GMA_CTL_REG, 0x03 }, { GMA_COEF_REG(0), 0x00 },
289 { GMA_COEF_REG(1), 0x19 }, { GMA_COEF_REG(2), 0x26 },
290 { GMA_COEF_REG(3), 0x3B }, { GMA_COEF_REG(4), 0x5D },
291 { GMA_COEF_REG(5), 0x79 }, { GMA_COEF_REG(6), 0x8E },
292 { GMA_COEF_REG(7), 0x9F }, { GMA_COEF_REG(8), 0xAF },
293 { GMA_COEF_REG(9), 0xBD }, { GMA_COEF_REG(10), 0xCA },
294 { GMA_COEF_REG(11), 0xDD }, { GMA_COEF_REG(12), 0xEC },
295 { GMA_COEF_REG(13), 0xF7 }, { GMA_COEF_REG(14), 0xFF },
296 /* Noise reduction, Z-LPF, YC-LPF and BLPF filters setup */
297 { ZLPF_CTRL_REG, 0x99 }, { ZLPF_CTRL2_REG, 0x0E },
298 { ZLPF_AGH_THR_REG, 0x29 }, { ZLPF_THR_REG, 0x0F },
299 { ZLPF_DYN_THR_REG, 0x63 }, { YCLPF_CTL1_REG, 0x23 },
300 { YCLPF_CTL2_REG, 0x3B }, { YCLPF_THR_REG, 0x05 },
301 { BLPF_CTL_REG, 0x1D }, { BLPF_THR1_REG, 0x05 },
302 { BLPF_THR2_REG, 0x04 },
303 /* Automatic white balance */
304 { AWB_CTL1_REG, 0xFB }, { AWB_CTL2_REG, 0x26 },
305 { AWB_RMAX_REG, 0x54 }, { AWB_RMIN_REG, 0x2B },
306 { AWB_BMAX_REG, 0x57 }, { AWB_BMIN_REG, 0x29 },
307 { AWB_RMAXB_REG, 0x50 }, { AWB_RMINB_REG, 0x43 },
308 { AWB_BMAXB_REG, 0x30 }, { AWB_BMINB_REG, 0x22 },
309 /* Auto exposure */
310 { AE_CTL1_REG, 0x8C }, { AE_CTL2_REG, 0x04 },
311 { AE_FRM_CTL_REG, 0x01 }, { AE_FINE_CTL_REG(0), 0x3F },
312 { AE_FINE_CTL_REG(1), 0xA3 }, { AE_FINE_CTL_REG(3), 0x34 },
313 /* Lens shading compensation */
314 { LENS_CTRL_REG, 0x01 }, { LENS_XCEN_REG, 0x80 },
315 { LENS_YCEN_REG, 0x70 }, { LENS_R_COMP_REG, 0x53 },
316 { LENS_G_COMP_REG, 0x40 }, { LENS_B_COMP_REG, 0x3e },
317 { REG_TERM, 0 },
318};
319
320static inline struct sr030pc30_info *to_sr030pc30(struct v4l2_subdev *sd)
321{
322 return container_of(sd, struct sr030pc30_info, sd);
323}
324
325static inline int set_i2c_page(struct sr030pc30_info *info,
326 struct i2c_client *client, unsigned int reg)
327{
328 int ret;
329 u32 page = reg >> 8 & 0xFF;
330
331 if (info->i2c_reg_page != page && (reg & 0xFF) != 0x03) {
332 ret = i2c_smbus_write_byte_data(client, PAGEMODE_REG, page);
333 if (!ret)
334 info->i2c_reg_page = page;
335 }
336 return ret;
337}
338
339static int cam_i2c_read(struct v4l2_subdev *sd, u32 reg_addr)
340{
341 struct i2c_client *client = v4l2_get_subdevdata(sd);
342 struct sr030pc30_info *info = to_sr030pc30(sd);
343
344 int ret = set_i2c_page(info, client, reg_addr);
345 if (!ret)
346 ret = i2c_smbus_read_byte_data(client, reg_addr & 0xFF);
347 return ret;
348}
349
350static int cam_i2c_write(struct v4l2_subdev *sd, u32 reg_addr, u32 val)
351{
352 struct i2c_client *client = v4l2_get_subdevdata(sd);
353 struct sr030pc30_info *info = to_sr030pc30(sd);
354
355 int ret = set_i2c_page(info, client, reg_addr);
356 if (!ret)
357 ret = i2c_smbus_write_byte_data(
358 client, reg_addr & 0xFF, val);
359 return ret;
360}
361
362static inline int sr030pc30_bulk_write_reg(struct v4l2_subdev *sd,
363 const struct i2c_regval *msg)
364{
365 while (msg->addr != REG_TERM) {
366 int ret = cam_i2c_write(sd, msg->addr, msg->val);
367 if (ret)
368 return ret;
369 msg++;
370 }
371 return 0;
372}
373
374/* Device reset and sleep mode control */
375static int sr030pc30_pwr_ctrl(struct v4l2_subdev *sd,
376 bool reset, bool sleep)
377{
378 struct sr030pc30_info *info = to_sr030pc30(sd);
379 u8 reg = sleep ? 0xF1 : 0xF0;
380 int ret = 0;
381
382 if (reset)
383 ret = cam_i2c_write(sd, POWER_CTRL_REG, reg | 0x02);
384 if (!ret) {
385 ret = cam_i2c_write(sd, POWER_CTRL_REG, reg);
386 if (!ret) {
387 info->sleep = sleep;
388 if (reset)
389 info->i2c_reg_page = -1;
390 }
391 }
392 return ret;
393}
394
395static inline int sr030pc30_enable_autoexposure(struct v4l2_subdev *sd, int on)
396{
397 struct sr030pc30_info *info = to_sr030pc30(sd);
398 /* auto anti-flicker is also enabled here */
399 int ret = cam_i2c_write(sd, AE_CTL1_REG, on ? 0xDC : 0x0C);
400 if (!ret)
401 info->auto_exp = on;
402 return ret;
403}
404
405static int sr030pc30_set_exposure(struct v4l2_subdev *sd, int value)
406{
407 struct sr030pc30_info *info = to_sr030pc30(sd);
408
409 unsigned long expos = value * info->pdata->clk_rate / (8 * 1000);
410
411 int ret = cam_i2c_write(sd, EXP_TIMEH_REG, expos >> 16 & 0xFF);
412 if (!ret)
413 ret = cam_i2c_write(sd, EXP_TIMEM_REG, expos >> 8 & 0xFF);
414 if (!ret)
415 ret = cam_i2c_write(sd, EXP_TIMEL_REG, expos & 0xFF);
416 if (!ret) { /* Turn off AE */
417 info->exposure = value;
418 ret = sr030pc30_enable_autoexposure(sd, 0);
419 }
420 return ret;
421}
422
423/* Automatic white balance control */
424static int sr030pc30_enable_autowhitebalance(struct v4l2_subdev *sd, int on)
425{
426 struct sr030pc30_info *info = to_sr030pc30(sd);
427
428 int ret = cam_i2c_write(sd, AWB_CTL2_REG, on ? 0x2E : 0x2F);
429 if (!ret)
430 ret = cam_i2c_write(sd, AWB_CTL1_REG, on ? 0xFB : 0x7B);
431 if (!ret)
432 info->auto_wb = on;
433
434 return ret;
435}
436
437static int sr030pc30_set_flip(struct v4l2_subdev *sd)
438{
439 struct sr030pc30_info *info = to_sr030pc30(sd);
440
441 s32 reg = cam_i2c_read(sd, VDO_CTL2_REG);
442 if (reg < 0)
443 return reg;
444
445 reg &= 0x7C;
446 if (info->hflip)
447 reg |= 0x01;
448 if (info->vflip)
449 reg |= 0x02;
450 return cam_i2c_write(sd, VDO_CTL2_REG, reg | 0x80);
451}
452
453/* Configure resolution, color format and image flip */
454static int sr030pc30_set_params(struct v4l2_subdev *sd)
455{
456 struct sr030pc30_info *info = to_sr030pc30(sd);
457 int ret;
458
459 if (!info->curr_win)
460 return -EINVAL;
461
462 /* Configure the resolution through subsampling */
463 ret = cam_i2c_write(sd, VDO_CTL1_REG,
464 info->curr_win->vid_ctl1);
465
466 if (!ret && info->curr_fmt)
467 ret = cam_i2c_write(sd, ISP_CTL_REG(0),
468 info->curr_fmt->ispctl1_reg);
469 if (!ret)
470 ret = sr030pc30_set_flip(sd);
471
472 return ret;
473}
474
475/* Find nearest matching image pixel size. */
476static int sr030pc30_try_frame_size(struct v4l2_mbus_framefmt *mf)
477{
478 unsigned int min_err = ~0;
479 int i = ARRAY_SIZE(sr030pc30_sizes);
480 const struct sr030pc30_frmsize *fsize = &sr030pc30_sizes[0],
481 *match = NULL;
482 while (i--) {
483 int err = abs(fsize->width - mf->width)
484 + abs(fsize->height - mf->height);
485 if (err < min_err) {
486 min_err = err;
487 match = fsize;
488 }
489 fsize++;
490 }
491 if (match) {
492 mf->width = match->width;
493 mf->height = match->height;
494 return 0;
495 }
496 return -EINVAL;
497}
498
499static int sr030pc30_queryctrl(struct v4l2_subdev *sd,
500 struct v4l2_queryctrl *qc)
501{
502 int i;
503
504 for (i = 0; i < ARRAY_SIZE(sr030pc30_ctrl); i++)
505 if (qc->id == sr030pc30_ctrl[i].id) {
506 *qc = sr030pc30_ctrl[i];
507 v4l2_dbg(1, debug, sd, "%s id: %d\n",
508 __func__, qc->id);
509 return 0;
510 }
511
512 return -EINVAL;
513}
514
515static inline int sr030pc30_set_bluebalance(struct v4l2_subdev *sd, int value)
516{
517 int ret = cam_i2c_write(sd, MWB_BGAIN_REG, value);
518 if (!ret)
519 to_sr030pc30(sd)->blue_balance = value;
520 return ret;
521}
522
523static inline int sr030pc30_set_redbalance(struct v4l2_subdev *sd, int value)
524{
525 int ret = cam_i2c_write(sd, MWB_RGAIN_REG, value);
526 if (!ret)
527 to_sr030pc30(sd)->red_balance = value;
528 return ret;
529}
530
531static int sr030pc30_s_ctrl(struct v4l2_subdev *sd,
532 struct v4l2_control *ctrl)
533{
534 int i, ret = 0;
535
536 for (i = 0; i < ARRAY_SIZE(sr030pc30_ctrl); i++)
537 if (ctrl->id == sr030pc30_ctrl[i].id)
538 break;
539
540 if (i == ARRAY_SIZE(sr030pc30_ctrl))
541 return -EINVAL;
542
543 if (ctrl->value < sr030pc30_ctrl[i].minimum ||
544 ctrl->value > sr030pc30_ctrl[i].maximum)
545 return -ERANGE;
546
547 v4l2_dbg(1, debug, sd, "%s: ctrl_id: %d, value: %d\n",
548 __func__, ctrl->id, ctrl->value);
549
550 switch (ctrl->id) {
551 case V4L2_CID_AUTO_WHITE_BALANCE:
552 sr030pc30_enable_autowhitebalance(sd, ctrl->value);
553 break;
554 case V4L2_CID_BLUE_BALANCE:
555 ret = sr030pc30_set_bluebalance(sd, ctrl->value);
556 break;
557 case V4L2_CID_RED_BALANCE:
558 ret = sr030pc30_set_redbalance(sd, ctrl->value);
559 break;
560 case V4L2_CID_EXPOSURE_AUTO:
561 sr030pc30_enable_autoexposure(sd,
562 ctrl->value == V4L2_EXPOSURE_AUTO);
563 break;
564 case V4L2_CID_EXPOSURE:
565 ret = sr030pc30_set_exposure(sd, ctrl->value);
566 break;
567 default:
568 return -EINVAL;
569 }
570
571 return ret;
572}
573
574static int sr030pc30_g_ctrl(struct v4l2_subdev *sd,
575 struct v4l2_control *ctrl)
576{
577 struct sr030pc30_info *info = to_sr030pc30(sd);
578
579 v4l2_dbg(1, debug, sd, "%s: id: %d\n", __func__, ctrl->id);
580
581 switch (ctrl->id) {
582 case V4L2_CID_AUTO_WHITE_BALANCE:
583 ctrl->value = info->auto_wb;
584 break;
585 case V4L2_CID_BLUE_BALANCE:
586 ctrl->value = info->blue_balance;
587 break;
588 case V4L2_CID_RED_BALANCE:
589 ctrl->value = info->red_balance;
590 break;
591 case V4L2_CID_EXPOSURE_AUTO:
592 ctrl->value = info->auto_exp;
593 break;
594 case V4L2_CID_EXPOSURE:
595 ctrl->value = info->exposure;
596 break;
597 default:
598 return -EINVAL;
599 }
600 return 0;
601}
602
603static int sr030pc30_enum_fmt(struct v4l2_subdev *sd, unsigned int index,
604 enum v4l2_mbus_pixelcode *code)
605{
606 if (!code || index >= ARRAY_SIZE(sr030pc30_formats))
607 return -EINVAL;
608
609 *code = sr030pc30_formats[index].code;
610 return 0;
611}
612
613static int sr030pc30_g_fmt(struct v4l2_subdev *sd,
614 struct v4l2_mbus_framefmt *mf)
615{
616 struct sr030pc30_info *info = to_sr030pc30(sd);
617 int ret;
618
619 if (!mf)
620 return -EINVAL;
621
622 if (!info->curr_win || !info->curr_fmt) {
623 ret = sr030pc30_set_params(sd);
624 if (ret)
625 return ret;
626 }
627
628 mf->width = info->curr_win->width;
629 mf->height = info->curr_win->height;
630 mf->code = info->curr_fmt->code;
631 mf->colorspace = info->curr_fmt->colorspace;
632 mf->field = V4L2_FIELD_NONE;
633
634 return 0;
635}
636
637/* Return nearest media bus frame format. */
638static const struct sr030pc30_format *try_fmt(struct v4l2_subdev *sd,
639 struct v4l2_mbus_framefmt *mf)
640{
641 int i = ARRAY_SIZE(sr030pc30_formats);
642
643 sr030pc30_try_frame_size(mf);
644
645 while (i--)
646 if (mf->code == sr030pc30_formats[i].code)
647 break;
648
649 mf->code = sr030pc30_formats[i].code;
650
651 return &sr030pc30_formats[i];
652}
653
654/* Return nearest media bus frame format. */
655static int sr030pc30_try_fmt(struct v4l2_subdev *sd,
656 struct v4l2_mbus_framefmt *mf)
657{
658 if (!sd || !mf)
659 return -EINVAL;
660
661 try_fmt(sd, mf);
662 return 0;
663}
664
665static int sr030pc30_s_fmt(struct v4l2_subdev *sd,
666 struct v4l2_mbus_framefmt *mf)
667{
668 struct sr030pc30_info *info = to_sr030pc30(sd);
669
670 if (!sd || !mf)
671 return -EINVAL;
672
673 info->curr_fmt = try_fmt(sd, mf);
674
675 return sr030pc30_set_params(sd);
676}
677
678static int sr030pc30_base_config(struct v4l2_subdev *sd)
679{
680 struct sr030pc30_info *info = to_sr030pc30(sd);
681 int ret;
682 unsigned long expmin, expmax;
683
684 ret = sr030pc30_bulk_write_reg(sd, sr030pc30_base_regs);
685 if (!ret) {
686 info->curr_fmt = &sr030pc30_formats[0];
687 info->curr_win = &sr030pc30_sizes[0];
688 ret = sr030pc30_set_params(sd);
689 }
690 if (!ret)
691 ret = sr030pc30_pwr_ctrl(sd, false, false);
692
693 if (!ret && !info->pdata)
694 return ret;
695
696 expmin = EXPOS_MIN_MS * info->pdata->clk_rate / (8 * 1000);
697 expmax = EXPOS_MAX_MS * info->pdata->clk_rate / (8 * 1000);
698
699 v4l2_dbg(1, debug, sd, "%s: expmin= %lx, expmax= %lx", __func__,
700 expmin, expmax);
701
702 /* Setting up manual exposure time range */
703 ret = cam_i2c_write(sd, EXP_MMINH_REG, expmin >> 8 & 0xFF);
704 if (!ret)
705 ret = cam_i2c_write(sd, EXP_MMINL_REG, expmin & 0xFF);
706 if (!ret)
707 ret = cam_i2c_write(sd, EXP_MMAXH_REG, expmax >> 16 & 0xFF);
708 if (!ret)
709 ret = cam_i2c_write(sd, EXP_MMAXM_REG, expmax >> 8 & 0xFF);
710 if (!ret)
711 ret = cam_i2c_write(sd, EXP_MMAXL_REG, expmax & 0xFF);
712
713 return ret;
714}
715
716static int sr030pc30_s_config(struct v4l2_subdev *sd,
717 int irq, void *platform_data)
718{
719 struct sr030pc30_info *info = to_sr030pc30(sd);
720
721 info->pdata = platform_data;
722 return 0;
723}
724
725static int sr030pc30_s_stream(struct v4l2_subdev *sd, int enable)
726{
727 return 0;
728}
729
730static int sr030pc30_s_power(struct v4l2_subdev *sd, int on)
731{
732 struct i2c_client *client = v4l2_get_subdevdata(sd);
733 struct sr030pc30_info *info = to_sr030pc30(sd);
734 const struct sr030pc30_platform_data *pdata = info->pdata;
735 int ret;
736
737 if (WARN(pdata == NULL, "No platform data!"))
738 return -ENOMEM;
739
740 /*
741 * Put sensor into power sleep mode before switching off
742 * power and disabling MCLK.
743 */
744 if (!on)
745 sr030pc30_pwr_ctrl(sd, false, true);
746
747 /* set_power controls sensor's power and clock */
748 if (pdata->set_power) {
749 ret = pdata->set_power(&client->dev, on);
750 if (ret)
751 return ret;
752 }
753
754 if (on) {
755 ret = sr030pc30_base_config(sd);
756 } else {
757 info->curr_win = NULL;
758 info->curr_fmt = NULL;
759 }
760
761 return ret;
762}
763
764static const struct v4l2_subdev_core_ops sr030pc30_core_ops = {
765 .s_config = sr030pc30_s_config,
766 .s_power = sr030pc30_s_power,
767 .queryctrl = sr030pc30_queryctrl,
768 .s_ctrl = sr030pc30_s_ctrl,
769 .g_ctrl = sr030pc30_g_ctrl,
770};
771
772static const struct v4l2_subdev_video_ops sr030pc30_video_ops = {
773 .s_stream = sr030pc30_s_stream,
774 .g_mbus_fmt = sr030pc30_g_fmt,
775 .s_mbus_fmt = sr030pc30_s_fmt,
776 .try_mbus_fmt = sr030pc30_try_fmt,
777 .enum_mbus_fmt = sr030pc30_enum_fmt,
778};
779
780static const struct v4l2_subdev_ops sr030pc30_ops = {
781 .core = &sr030pc30_core_ops,
782 .video = &sr030pc30_video_ops,
783};
784
785/*
786 * Detect sensor type. Return 0 if SR030PC30 was detected
787 * or -ENODEV otherwise.
788 */
789static int sr030pc30_detect(struct i2c_client *client)
790{
791 const struct sr030pc30_platform_data *pdata
792 = client->dev.platform_data;
793 int ret;
794
795 /* Enable sensor's power and clock */
796 if (pdata->set_power) {
797 ret = pdata->set_power(&client->dev, 1);
798 if (ret)
799 return ret;
800 }
801
802 ret = i2c_smbus_read_byte_data(client, DEVICE_ID_REG);
803
804 if (pdata->set_power)
805 pdata->set_power(&client->dev, 0);
806
807 if (ret < 0) {
808 dev_err(&client->dev, "%s: I2C read failed\n", __func__);
809 return ret;
810 }
811
812 return ret == SR030PC30_ID ? 0 : -ENODEV;
813}
814
815
816static int sr030pc30_probe(struct i2c_client *client,
817 const struct i2c_device_id *id)
818{
819 struct sr030pc30_info *info;
820 struct v4l2_subdev *sd;
821 const struct sr030pc30_platform_data *pdata
822 = client->dev.platform_data;
823 int ret;
824
825 if (!pdata) {
826 dev_err(&client->dev, "No platform data!");
827 return -EIO;
828 }
829
830 ret = sr030pc30_detect(client);
831 if (ret)
832 return ret;
833
834 info = kzalloc(sizeof(*info), GFP_KERNEL);
835 if (!info)
836 return -ENOMEM;
837
838 sd = &info->sd;
839 strcpy(sd->name, MODULE_NAME);
840 info->pdata = client->dev.platform_data;
841
842 v4l2_i2c_subdev_init(sd, client, &sr030pc30_ops);
843
844 info->i2c_reg_page = -1;
845 info->hflip = 1;
846 info->auto_exp = 1;
847 info->exposure = 30;
848
849 return 0;
850}
851
852static int sr030pc30_remove(struct i2c_client *client)
853{
854 struct v4l2_subdev *sd = i2c_get_clientdata(client);
855 struct sr030pc30_info *info = to_sr030pc30(sd);
856
857 v4l2_device_unregister_subdev(sd);
858 kfree(info);
859 return 0;
860}
861
862static const struct i2c_device_id sr030pc30_id[] = {
863 { MODULE_NAME, 0 },
864 { },
865};
866MODULE_DEVICE_TABLE(i2c, sr030pc30_id);
867
868
869static struct i2c_driver sr030pc30_i2c_driver = {
870 .driver = {
871 .name = MODULE_NAME
872 },
873 .probe = sr030pc30_probe,
874 .remove = sr030pc30_remove,
875 .id_table = sr030pc30_id,
876};
877
878static int __init sr030pc30_init(void)
879{
880 return i2c_add_driver(&sr030pc30_i2c_driver);
881}
882
883static void __exit sr030pc30_exit(void)
884{
885 i2c_del_driver(&sr030pc30_i2c_driver);
886}
887
888module_init(sr030pc30_init);
889module_exit(sr030pc30_exit);
890
891MODULE_DESCRIPTION("Siliconfile SR030PC30 camera driver");
892MODULE_AUTHOR("Sylwester Nawrocki <s.nawrocki@samsung.com>");
893MODULE_LICENSE("GPL");
diff --git a/include/media/sr030pc30.h b/include/media/sr030pc30.h
new file mode 100644
index 000000000000..6f901a653ba2
--- /dev/null
+++ b/include/media/sr030pc30.h
@@ -0,0 +1,21 @@
1/*
2 * Driver header for SR030PC30 camera sensor
3 *
4 * Copyright (c) 2010 Samsung Electronics, Co. Ltd
5 * Contact: Sylwester Nawrocki <s.nawrocki@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef SR030PC30_H
14#define SR030PC30_H
15
16struct sr030pc30_platform_data {
17 unsigned long clk_rate; /* master clock frequency in Hz */
18 int (*set_power)(struct device *dev, int on);
19};
20
21#endif /* SR030PC30_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-24 05:57:59 -0500