aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/blackfin/mach-bf518/include/mach/defBF51x_base.h45
-rw-r--r--arch/blackfin/mach-bf527/include/mach/defBF52x_base.h45
-rw-r--r--arch/blackfin/mach-bf533/include/mach/defBF532.h70
-rw-r--r--arch/blackfin/mach-bf537/include/mach/defBF534.h44
-rw-r--r--arch/blackfin/mach-bf538/include/mach/defBF539.h72
-rw-r--r--arch/blackfin/mach-bf548/include/mach/defBF54x_base.h50
-rw-r--r--arch/blackfin/mach-bf561/include/mach/defBF561.h57
7 files changed, 0 insertions, 383 deletions
diff --git a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
index 037a51fd8e93..5f84913dcd91 100644
--- a/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
+++ b/arch/blackfin/mach-bf518/include/mach/defBF51x_base.h
@@ -748,51 +748,6 @@
748#define FFE 0x20 /* Force Framing Error On Transmit */ 748#define FFE 0x20 /* Force Framing Error On Transmit */
749 749
750 750
751/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
752/* SPI_CTL Masks */
753#define TIMOD 0x0003 /* Transfer Initiate Mode */
754#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
755#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
756#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
757#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
758#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
759#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
760#define PSSE 0x0010 /* Slave-Select Input Enable */
761#define EMISO 0x0020 /* Enable MISO As Output */
762#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
763#define LSBF 0x0200 /* LSB First */
764#define CPHA 0x0400 /* Clock Phase */
765#define CPOL 0x0800 /* Clock Polarity */
766#define MSTR 0x1000 /* Master/Slave* */
767#define WOM 0x2000 /* Write Open Drain Master */
768#define SPE 0x4000 /* SPI Enable */
769
770/* SPI_FLG Masks */
771#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
772#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
773#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
774#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
775#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
776#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
777#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
778#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
779#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
780#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
781#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
782#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
783#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
784#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
785
786/* SPI_STAT Masks */
787#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
788#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
789#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
790#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
791#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
792#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
793#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
794
795
796/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 751/* **************** GENERAL PURPOSE TIMER MASKS **********************/
797/* TIMER_ENABLE Masks */ 752/* TIMER_ENABLE Masks */
798#define TIMEN0 0x0001 /* Enable Timer 0 */ 753#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
index 3e000756aacd..09475034c6a1 100644
--- a/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
+++ b/arch/blackfin/mach-bf527/include/mach/defBF52x_base.h
@@ -749,51 +749,6 @@
749#define FFE 0x20 /* Force Framing Error On Transmit */ 749#define FFE 0x20 /* Force Framing Error On Transmit */
750 750
751 751
752/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
753/* SPI_CTL Masks */
754#define TIMOD 0x0003 /* Transfer Initiate Mode */
755#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
756#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
757#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
758#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
759#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
760#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
761#define PSSE 0x0010 /* Slave-Select Input Enable */
762#define EMISO 0x0020 /* Enable MISO As Output */
763#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
764#define LSBF 0x0200 /* LSB First */
765#define CPHA 0x0400 /* Clock Phase */
766#define CPOL 0x0800 /* Clock Polarity */
767#define MSTR 0x1000 /* Master/Slave* */
768#define WOM 0x2000 /* Write Open Drain Master */
769#define SPE 0x4000 /* SPI Enable */
770
771/* SPI_FLG Masks */
772#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
773#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
774#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
775#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
776#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
777#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
778#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
779#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
780#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
781#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
782#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
783#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
784#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
785#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
786
787/* SPI_STAT Masks */
788#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
789#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
790#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
791#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
792#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
793#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
794#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
795
796
797/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 752/* **************** GENERAL PURPOSE TIMER MASKS **********************/
798/* TIMER_ENABLE Masks */ 753/* TIMER_ENABLE Masks */
799#define TIMEN0 0x0001 /* Enable Timer 0 */ 754#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf533/include/mach/defBF532.h b/arch/blackfin/mach-bf533/include/mach/defBF532.h
index 04acf1ed10f9..3adb0b44e597 100644
--- a/arch/blackfin/mach-bf533/include/mach/defBF532.h
+++ b/arch/blackfin/mach-bf533/include/mach/defBF532.h
@@ -681,76 +681,6 @@
681#define PF14_P 14 681#define PF14_P 14
682#define PF15_P 15 682#define PF15_P 15
683 683
684/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
685
686/* SPI_CTL Masks */
687#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
688#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
689#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
690#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
691#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
692#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
693#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
694#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
695#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
696#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
697#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
698#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
699#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
700#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
701#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
702#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
703
704/* SPI_FLG Masks */
705#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
706#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
707#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
708#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
709#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
710#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
711#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
712#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
713#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
714#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
715#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
716#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
717#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
718#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
719
720/* SPI_FLG Bit Positions */
721#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
722#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
723#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
724#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
725#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
726#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
727#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
728#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
729#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
730#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
731#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
732#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
733#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
734#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
735
736/* SPI_STAT Masks */
737#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
738#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
739#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
740#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
741#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
742#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
743#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
744
745/* SPIx_FLG Masks */
746#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
747#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
748#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
749#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
750#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
751#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
752#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
753
754/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 684/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
755 685
756/* AMGCTL Masks */ 686/* AMGCTL Masks */
diff --git a/arch/blackfin/mach-bf537/include/mach/defBF534.h b/arch/blackfin/mach-bf537/include/mach/defBF534.h
index 6f56907a18c0..0323e6bacdae 100644
--- a/arch/blackfin/mach-bf537/include/mach/defBF534.h
+++ b/arch/blackfin/mach-bf537/include/mach/defBF534.h
@@ -1071,50 +1071,6 @@
1071#define FPE 0x10 /* Force Parity Error On Transmit */ 1071#define FPE 0x10 /* Force Parity Error On Transmit */
1072#define FFE 0x20 /* Force Framing Error On Transmit */ 1072#define FFE 0x20 /* Force Framing Error On Transmit */
1073 1073
1074/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS ****************************/
1075/* SPI_CTL Masks */
1076#define TIMOD 0x0003 /* Transfer Initiate Mode */
1077#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1078#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1079#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1080#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1081#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1082#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1083#define PSSE 0x0010 /* Slave-Select Input Enable */
1084#define EMISO 0x0020 /* Enable MISO As Output */
1085#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1086#define LSBF 0x0200 /* LSB First */
1087#define CPHA 0x0400 /* Clock Phase */
1088#define CPOL 0x0800 /* Clock Polarity */
1089#define MSTR 0x1000 /* Master/Slave* */
1090#define WOM 0x2000 /* Write Open Drain Master */
1091#define SPE 0x4000 /* SPI Enable */
1092
1093/* SPI_FLG Masks */
1094#define FLS1 0x0002 /* Enables SPI_FLOUT1 as SPI Slave-Select Output */
1095#define FLS2 0x0004 /* Enables SPI_FLOUT2 as SPI Slave-Select Output */
1096#define FLS3 0x0008 /* Enables SPI_FLOUT3 as SPI Slave-Select Output */
1097#define FLS4 0x0010 /* Enables SPI_FLOUT4 as SPI Slave-Select Output */
1098#define FLS5 0x0020 /* Enables SPI_FLOUT5 as SPI Slave-Select Output */
1099#define FLS6 0x0040 /* Enables SPI_FLOUT6 as SPI Slave-Select Output */
1100#define FLS7 0x0080 /* Enables SPI_FLOUT7 as SPI Slave-Select Output */
1101#define FLG1 0xFDFF /* Activates SPI_FLOUT1 */
1102#define FLG2 0xFBFF /* Activates SPI_FLOUT2 */
1103#define FLG3 0xF7FF /* Activates SPI_FLOUT3 */
1104#define FLG4 0xEFFF /* Activates SPI_FLOUT4 */
1105#define FLG5 0xDFFF /* Activates SPI_FLOUT5 */
1106#define FLG6 0xBFFF /* Activates SPI_FLOUT6 */
1107#define FLG7 0x7FFF /* Activates SPI_FLOUT7 */
1108
1109/* SPI_STAT Masks */
1110#define SPIF 0x0001 /* SPI Finished (Single-Word Transfer Complete) */
1111#define MODF 0x0002 /* Mode Fault Error (Another Device Tried To Become Master) */
1112#define TXE 0x0004 /* Transmission Error (Data Sent With No New Data In TDBR) */
1113#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (Full/Empty*) */
1114#define RBSY 0x0010 /* Receive Error (Data Received With RDBR Full) */
1115#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (Full/Empty*) */
1116#define TXCOL 0x0040 /* Transmit Collision Error (Corrupt Data May Have Been Sent) */
1117
1118/* **************** GENERAL PURPOSE TIMER MASKS **********************/ 1074/* **************** GENERAL PURPOSE TIMER MASKS **********************/
1119/* TIMER_ENABLE Masks */ 1075/* TIMER_ENABLE Masks */
1120#define TIMEN0 0x0001 /* Enable Timer 0 */ 1076#define TIMEN0 0x0001 /* Enable Timer 0 */
diff --git a/arch/blackfin/mach-bf538/include/mach/defBF539.h b/arch/blackfin/mach-bf538/include/mach/defBF539.h
index fe43062b4975..72e17ec147ca 100644
--- a/arch/blackfin/mach-bf538/include/mach/defBF539.h
+++ b/arch/blackfin/mach-bf538/include/mach/defBF539.h
@@ -1894,78 +1894,6 @@
1894#define PE14_P 0xE 1894#define PE14_P 0xE
1895#define PE15_P 0xF 1895#define PE15_P 0xF
1896 1896
1897
1898/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
1899/* SPIx_CTL Masks */
1900#define TIMOD 0x0003 /* Transfer Initiate Mode */
1901#define RDBR_CORE 0x0000 /* RDBR Read Initiates, IRQ When RDBR Full */
1902#define TDBR_CORE 0x0001 /* TDBR Write Initiates, IRQ When TDBR Empty */
1903#define RDBR_DMA 0x0002 /* DMA Read, DMA Until FIFO Empty */
1904#define TDBR_DMA 0x0003 /* DMA Write, DMA Until FIFO Full */
1905#define SZ 0x0004 /* Send Zero (When TDBR Empty, Send Zero/Last*) */
1906#define GM 0x0008 /* Get More (When RDBR Full, Overwrite/Discard*) */
1907#define PSSE 0x0010 /* Slave-Select Input Enable */
1908#define EMISO 0x0020 /* Enable MISO As Output */
1909#define SIZE 0x0100 /* Size of Words (16/8* Bits) */
1910#define LSBF 0x0200 /* LSB First */
1911#define CPHA 0x0400 /* Clock Phase */
1912#define CPOL 0x0800 /* Clock Polarity */
1913#define MSTR 0x1000 /* Master/Slave* */
1914#define WOM 0x2000 /* Write Open Drain Master */
1915#define SPE 0x4000 /* SPI Enable */
1916
1917/* SPIx_FLG Masks */
1918#define FLS1 0x0002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1919#define FLS2 0x0004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1920#define FLS3 0x0008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1921#define FLS4 0x0010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1922#define FLS5 0x0020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1923#define FLS6 0x0040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1924#define FLS7 0x0080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1925
1926#define FLG1 0x0200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1927#define FLG2 0x0400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1928#define FLG3 0x0800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1929#define FLG4 0x1000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1930#define FLG5 0x2000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1931#define FLG6 0x4000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1932#define FLG7 0x8000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1933
1934/* SPIx_FLG Bit Positions */
1935#define FLS1_P 0x0001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1936#define FLS2_P 0x0002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1937#define FLS3_P 0x0003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1938#define FLS4_P 0x0004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1939#define FLS5_P 0x0005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1940#define FLS6_P 0x0006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1941#define FLS7_P 0x0007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1942#define FLG1_P 0x0009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1943#define FLG2_P 0x000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1944#define FLG3_P 0x000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1945#define FLG4_P 0x000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1946#define FLG5_P 0x000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1947#define FLG6_P 0x000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1948#define FLG7_P 0x000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1949
1950/* SPIx_STAT Masks */
1951#define SPIF 0x0001 /* Set (=1) when SPI single-word transfer complete */
1952#define MODF 0x0002 /* Set (=1) in a master device when some other device tries to become master */
1953#define TXE 0x0004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
1954#define TXS 0x0008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
1955#define RBSY 0x0010 /* Set (=1) when data is received with RDBR full */
1956#define RXS 0x0020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
1957#define TXCOL 0x0040 /* When set (=1), corrupt data may have been transmitted */
1958
1959/* SPIx_FLG Masks */
1960#define FLG1E 0xFDFF /* Activates SPI_FLOUT1 */
1961#define FLG2E 0xFBFF /* Activates SPI_FLOUT2 */
1962#define FLG3E 0xF7FF /* Activates SPI_FLOUT3 */
1963#define FLG4E 0xEFFF /* Activates SPI_FLOUT4 */
1964#define FLG5E 0xDFFF /* Activates SPI_FLOUT5 */
1965#define FLG6E 0xBFFF /* Activates SPI_FLOUT6 */
1966#define FLG7E 0x7FFF /* Activates SPI_FLOUT7 */
1967
1968
1969/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1897/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1970/* EBIU_AMGCTL Masks */ 1898/* EBIU_AMGCTL Masks */
1971#define AMCKEN 0x0001 /* Enable CLKOUT */ 1899#define AMCKEN 0x0001 /* Enable CLKOUT */
diff --git a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
index 7866197f5485..35707b17020e 100644
--- a/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
+++ b/arch/blackfin/mach-bf548/include/mach/defBF54x_base.h
@@ -2061,56 +2061,6 @@
2061#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */ 2061#define LOW_EVEN 0xff0000 /* Lower Limit for Even Bytes (Luma) */
2062#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */ 2062#define HIGH_EVEN 0xff000000 /* Upper Limit for Even Bytes (Luma) */
2063 2063
2064/* Bit masks for SPIx_BAUD */
2065
2066#define SPI_BAUD 0xffff /* Baud Rate */
2067
2068/* Bit masks for SPIx_CTL */
2069
2070#define SPE 0x4000 /* SPI Enable */
2071#define WOM 0x2000 /* Write Open Drain Master */
2072#define MSTR 0x1000 /* Master Mode */
2073#define CPOL 0x800 /* Clock Polarity */
2074#define CPHA 0x400 /* Clock Phase */
2075#define LSBF 0x200 /* LSB First */
2076#define SIZE 0x100 /* Size of Words */
2077#define EMISO 0x20 /* Enable MISO Output */
2078#define PSSE 0x10 /* Slave-Select Enable */
2079#define GM 0x8 /* Get More Data */
2080#define SZ 0x4 /* Send Zero */
2081#define TIMOD 0x3 /* Transfer Initiation Mode */
2082
2083/* Bit masks for SPIx_FLG */
2084
2085#define FLS1 0x2 /* Slave Select Enable 1 */
2086#define FLS2 0x4 /* Slave Select Enable 2 */
2087#define FLS3 0x8 /* Slave Select Enable 3 */
2088#define FLG1 0x200 /* Slave Select Value 1 */
2089#define FLG2 0x400 /* Slave Select Value 2 */
2090#define FLG3 0x800 /* Slave Select Value 3 */
2091
2092/* Bit masks for SPIx_STAT */
2093
2094#define TXCOL 0x40 /* Transmit Collision Error */
2095#define RXS 0x20 /* RDBR Data Buffer Status */
2096#define RBSY 0x10 /* Receive Error */
2097#define TXS 0x8 /* TDBR Data Buffer Status */
2098#define TXE 0x4 /* Transmission Error */
2099#define MODF 0x2 /* Mode Fault Error */
2100#define SPIF 0x1 /* SPI Finished */
2101
2102/* Bit masks for SPIx_TDBR */
2103
2104#define TDBR 0xffff /* Transmit Data Buffer */
2105
2106/* Bit masks for SPIx_RDBR */
2107
2108#define RDBR 0xffff /* Receive Data Buffer */
2109
2110/* Bit masks for SPIx_SHADOW */
2111
2112#define SHADOW 0xffff /* RDBR Shadow */
2113
2114/* ************************************************ */ 2064/* ************************************************ */
2115/* The TWI bit masks fields are from the ADSP-BF538 */ 2065/* The TWI bit masks fields are from the ADSP-BF538 */
2116/* and they have not been verified as the final */ 2066/* and they have not been verified as the final */
diff --git a/arch/blackfin/mach-bf561/include/mach/defBF561.h b/arch/blackfin/mach-bf561/include/mach/defBF561.h
index 2674f0097576..6f59ac669f10 100644
--- a/arch/blackfin/mach-bf561/include/mach/defBF561.h
+++ b/arch/blackfin/mach-bf561/include/mach/defBF561.h
@@ -1271,63 +1271,6 @@
1271#define PF14_P 14 1271#define PF14_P 14
1272#define PF15_P 15 1272#define PF15_P 15
1273 1273
1274/* *********** SERIAL PERIPHERAL INTERFACE (SPI) MASKS **************** */
1275
1276/* SPI_CTL Masks */
1277#define TIMOD 0x00000003 /* Transfer initiation mode and interrupt generation */
1278#define SZ 0x00000004 /* Send Zero (=0) or last (=1) word when TDBR empty. */
1279#define GM 0x00000008 /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
1280#define PSSE 0x00000010 /* Enable (=1) Slave-Select input for Master. */
1281#define EMISO 0x00000020 /* Enable (=1) MISO pin as an output. */
1282#define SIZE 0x00000100 /* Word length (0 => 8 bits, 1 => 16 bits) */
1283#define LSBF 0x00000200 /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
1284#define CPHA 0x00000400 /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
1285#define CPOL 0x00000800 /* Clock polarity (0 => active-high, 1 => active-low) */
1286#define MSTR 0x00001000 /* Configures SPI as master (=1) or slave (=0) */
1287#define WOM 0x00002000 /* Open drain (=1) data output enable (for MOSI and MISO) */
1288#define SPE 0x00004000 /* SPI module enable (=1), disable (=0) */
1289
1290/* SPI_FLG Masks */
1291#define FLS1 0x00000002 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1292#define FLS2 0x00000004 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1293#define FLS3 0x00000008 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1294#define FLS4 0x00000010 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1295#define FLS5 0x00000020 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1296#define FLS6 0x00000040 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1297#define FLS7 0x00000080 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1298#define FLG1 0x00000200 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1299#define FLG2 0x00000400 /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1300#define FLG3 0x00000800 /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1301#define FLG4 0x00001000 /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1302#define FLG5 0x00002000 /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1303#define FLG6 0x00004000 /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1304#define FLG7 0x00008000 /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1305
1306/* SPI_FLG Bit Positions */
1307#define FLS1_P 0x00000001 /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
1308#define FLS2_P 0x00000002 /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
1309#define FLS3_P 0x00000003 /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
1310#define FLS4_P 0x00000004 /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
1311#define FLS5_P 0x00000005 /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
1312#define FLS6_P 0x00000006 /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
1313#define FLS7_P 0x00000007 /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
1314#define FLG1_P 0x00000009 /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select */
1315#define FLG2_P 0x0000000A /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
1316#define FLG3_P 0x0000000B /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select */
1317#define FLG4_P 0x0000000C /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select */
1318#define FLG5_P 0x0000000D /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select */
1319#define FLG6_P 0x0000000E /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select */
1320#define FLG7_P 0x0000000F /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
1321
1322/* SPI_STAT Masks */
1323#define SPIF 0x00000001 /* Set (=1) when SPI single-word transfer complete */
1324#define MODF 0x00000002 /* Set (=1) in a master device when some other device tries to become master */
1325#define TXE 0x00000004 /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
1326#define TXS 0x00000008 /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
1327#define RBSY 0x00000010 /* Set (=1) when data is received with RDBR full */
1328#define RXS 0x00000020 /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full) */
1329#define TXCOL 0x00000040 /* When set (=1), corrupt data may have been transmitted */
1330
1331/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */ 1274/* ********************* ASYNCHRONOUS MEMORY CONTROLLER MASKS ************* */
1332 1275
1333/* AMGCTL Masks */ 1276/* AMGCTL Masks */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-26 14:54:09 -0500