diff options
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_vm.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_vm.c b/drivers/gpu/drm/radeon/radeon_vm.c index 1491be90755e..c11b71d249e3 100644 --- a/drivers/gpu/drm/radeon/radeon_vm.c +++ b/drivers/gpu/drm/radeon/radeon_vm.c | |||
@@ -585,7 +585,8 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev, | |||
585 | { | 585 | { |
586 | static const uint32_t incr = RADEON_VM_PTE_COUNT * 8; | 586 | static const uint32_t incr = RADEON_VM_PTE_COUNT * 8; |
587 | 587 | ||
588 | uint64_t pd_addr = radeon_bo_gpu_offset(vm->page_directory); | 588 | struct radeon_bo *pd = vm->page_directory; |
589 | uint64_t pd_addr = radeon_bo_gpu_offset(pd); | ||
589 | uint64_t last_pde = ~0, last_pt = ~0; | 590 | uint64_t last_pde = ~0, last_pt = ~0; |
590 | unsigned count = 0, pt_idx, ndw; | 591 | unsigned count = 0, pt_idx, ndw; |
591 | struct radeon_ib ib; | 592 | struct radeon_ib ib; |
@@ -642,6 +643,7 @@ int radeon_vm_update_page_directory(struct radeon_device *rdev, | |||
642 | incr, R600_PTE_VALID); | 643 | incr, R600_PTE_VALID); |
643 | 644 | ||
644 | if (ib.length_dw != 0) { | 645 | if (ib.length_dw != 0) { |
646 | radeon_semaphore_sync_to(ib.semaphore, pd->tbo.sync_obj); | ||
645 | radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use); | 647 | radeon_semaphore_sync_to(ib.semaphore, vm->last_id_use); |
646 | r = radeon_ib_schedule(rdev, &ib, NULL); | 648 | r = radeon_ib_schedule(rdev, &ib, NULL); |
647 | if (r) { | 649 | if (r) { |
@@ -689,15 +691,18 @@ static void radeon_vm_update_ptes(struct radeon_device *rdev, | |||
689 | /* walk over the address space and update the page tables */ | 691 | /* walk over the address space and update the page tables */ |
690 | for (addr = start; addr < end; ) { | 692 | for (addr = start; addr < end; ) { |
691 | uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE; | 693 | uint64_t pt_idx = addr >> RADEON_VM_BLOCK_SIZE; |
694 | struct radeon_bo *pt = vm->page_tables[pt_idx].bo; | ||
692 | unsigned nptes; | 695 | unsigned nptes; |
693 | uint64_t pte; | 696 | uint64_t pte; |
694 | 697 | ||
698 | radeon_semaphore_sync_to(ib->semaphore, pt->tbo.sync_obj); | ||
699 | |||
695 | if ((addr & ~mask) == (end & ~mask)) | 700 | if ((addr & ~mask) == (end & ~mask)) |
696 | nptes = end - addr; | 701 | nptes = end - addr; |
697 | else | 702 | else |
698 | nptes = RADEON_VM_PTE_COUNT - (addr & mask); | 703 | nptes = RADEON_VM_PTE_COUNT - (addr & mask); |
699 | 704 | ||
700 | pte = radeon_bo_gpu_offset(vm->page_tables[pt_idx].bo); | 705 | pte = radeon_bo_gpu_offset(pt); |
701 | pte += (addr & mask) * 8; | 706 | pte += (addr & mask) * 8; |
702 | 707 | ||
703 | if ((last_pte + 8 * count) != pte) { | 708 | if ((last_pte + 8 * count) != pte) { |