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-rw-r--r--drivers/serial/sh-sci.c22
-rw-r--r--drivers/serial/sh-sci.h21
2 files changed, 27 insertions, 16 deletions
diff --git a/drivers/serial/sh-sci.c b/drivers/serial/sh-sci.c
index 0a051bca01c7..8fdafc27fce8 100644
--- a/drivers/serial/sh-sci.c
+++ b/drivers/serial/sh-sci.c
@@ -363,21 +363,19 @@ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
363static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) 363static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag)
364{ 364{
365 unsigned int fcr_val = 0; 365 unsigned int fcr_val = 0;
366 unsigned short data;
366 367
367 if (cflag & CRTSCTS) { 368 if (port->mapbase == 0xffe00000) {
368 fcr_val |= SCFCR_MCE; 369 data = ctrl_inw(PSCR);
369 370 data &= ~0x03cf;
370 ctrl_outw(0x0000, PORT_PSCR); 371 if (cflag & CRTSCTS)
371 } else { 372 fcr_val |= SCFCR_MCE;
372 unsigned short data; 373 else
373 374 data |= 0x0340;
374 data = ctrl_inw(PORT_PSCR);
375 data &= 0x033f;
376 data |= 0x0400;
377 ctrl_outw(data, PORT_PSCR);
378 375
379 ctrl_outw(ctrl_inw(SCSPTR0) & 0x17, SCSPTR0); 376 ctrl_outw(data, PSCR);
380 } 377 }
378 /* SCIF1 and SCIF2 should be setup by board code */
381 379
382 sci_out(port, SCFCR, fcr_val); 380 sci_out(port, SCFCR, fcr_val);
383} 381}
diff --git a/drivers/serial/sh-sci.h b/drivers/serial/sh-sci.h
index fa8700a968fc..4d1c0e328a03 100644
--- a/drivers/serial/sh-sci.h
+++ b/drivers/serial/sh-sci.h
@@ -76,12 +76,13 @@
76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ 76# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */
77# define SCIF_ONLY 77# define SCIF_ONLY
78#elif defined(CONFIG_CPU_SUBTYPE_SH7722) 78#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
79# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 79# define PADR 0xA4050120
80# define SCSPTR0 SCPDR0 80# define PSDR 0xA405013e
81# define PWDR 0xA4050166
82# define PSCR 0xA405011E
81# define SCIF_ORER 0x0001 /* overrun error bit */ 83# define SCIF_ORER 0x0001 /* overrun error bit */
82# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ 84# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
83# define SCIF_ONLY 85# define SCIF_ONLY
84# define PORT_PSCR 0xA405011E
85#elif defined(CONFIG_CPU_SUBTYPE_SH7366) 86#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
86# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ 87# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */
87# define SCSPTR0 SCPDR0 88# define SCSPTR0 SCPDR0
@@ -593,13 +594,25 @@ static inline int sci_rxd_in(struct uart_port *port)
593 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */ 594 return ctrl_inw(SCSPTR3) & 0x0001 ? 1 : 0; /* SCIF */
594 return 1; 595 return 1;
595} 596}
596#elif defined(CONFIG_CPU_SUBTYPE_SH7722) || defined(CONFIG_CPU_SUBTYPE_SH7366) 597#elif defined(CONFIG_CPU_SUBTYPE_SH7366)
597static inline int sci_rxd_in(struct uart_port *port) 598static inline int sci_rxd_in(struct uart_port *port)
598{ 599{
599 if (port->mapbase == 0xffe00000) 600 if (port->mapbase == 0xffe00000)
600 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */ 601 return ctrl_inb(SCPDR0) & 0x0001 ? 1 : 0; /* SCIF0 */
601 return 1; 602 return 1;
602} 603}
604#elif defined(CONFIG_CPU_SUBTYPE_SH7722)
605static inline int sci_rxd_in(struct uart_port *port)
606{
607 if (port->mapbase == 0xffe00000)
608 return ctrl_inb(PSDR) & 0x02 ? 1 : 0; /* SCIF0 */
609 if (port->mapbase == 0xffe10000)
610 return ctrl_inb(PADR) & 0x40 ? 1 : 0; /* SCIF1 */
611 if (port->mapbase == 0xffe20000)
612 return ctrl_inb(PWDR) & 0x04 ? 1 : 0; /* SCIF2 */
613
614 return 1;
615}
603#elif defined(CONFIG_CPU_SUBTYPE_SH7723) 616#elif defined(CONFIG_CPU_SUBTYPE_SH7723)
604static inline int sci_rxd_in(struct uart_port *port) 617static inline int sci_rxd_in(struct uart_port *port)
605{ 618{