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-rw-r--r--drivers/net/wireless/ath/carl9170/mac.c604
-rw-r--r--drivers/net/wireless/ath/carl9170/phy.c1805
2 files changed, 2409 insertions, 0 deletions
diff --git a/drivers/net/wireless/ath/carl9170/mac.c b/drivers/net/wireless/ath/carl9170/mac.c
new file mode 100644
index 000000000000..2305bc27151c
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/mac.c
@@ -0,0 +1,604 @@
1/*
2 * Atheros CARL9170 driver
3 *
4 * MAC programming
5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
21 *
22 * This file incorporates work covered by the following copyright and
23 * permission notice:
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
25 *
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
37 */
38
39#include <asm/unaligned.h>
40
41#include "carl9170.h"
42#include "cmd.h"
43
44int carl9170_set_dyn_sifs_ack(struct ar9170 *ar)
45{
46 u32 val;
47
48 if (conf_is_ht40(&ar->hw->conf))
49 val = 0x010a;
50 else {
51 if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ)
52 val = 0x105;
53 else
54 val = 0x104;
55 }
56
57 return carl9170_write_reg(ar, AR9170_MAC_REG_DYNAMIC_SIFS_ACK, val);
58}
59
60int carl9170_set_rts_cts_rate(struct ar9170 *ar)
61{
62 u32 rts_rate, cts_rate;
63
64 if (conf_is_ht(&ar->hw->conf)) {
65 /* 12 mbit OFDM */
66 rts_rate = 0x1da;
67 cts_rate = 0x10a;
68 } else {
69 if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
70 /* 11 mbit CCK */
71 rts_rate = 033;
72 cts_rate = 003;
73 } else {
74 /* 6 mbit OFDM */
75 rts_rate = 0x1bb;
76 cts_rate = 0x10b;
77 }
78 }
79
80 return carl9170_write_reg(ar, AR9170_MAC_REG_RTS_CTS_RATE,
81 rts_rate | (cts_rate) << 16);
82}
83
84int carl9170_set_slot_time(struct ar9170 *ar)
85{
86 struct ieee80211_vif *vif;
87 u32 slottime = 20;
88
89 rcu_read_lock();
90 vif = carl9170_get_main_vif(ar);
91 if (!vif) {
92 rcu_read_unlock();
93 return 0;
94 }
95
96 if ((ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ) ||
97 vif->bss_conf.use_short_slot)
98 slottime = 9;
99
100 rcu_read_unlock();
101
102 return carl9170_write_reg(ar, AR9170_MAC_REG_SLOT_TIME,
103 slottime << 10);
104}
105
106int carl9170_set_mac_rates(struct ar9170 *ar)
107{
108 struct ieee80211_vif *vif;
109 u32 basic, mandatory;
110
111 rcu_read_lock();
112 vif = carl9170_get_main_vif(ar);
113
114 if (!vif) {
115 rcu_read_unlock();
116 return 0;
117 }
118
119 basic = (vif->bss_conf.basic_rates & 0xf);
120 basic |= (vif->bss_conf.basic_rates & 0xff0) << 4;
121 rcu_read_unlock();
122
123 if (ar->hw->conf.channel->band == IEEE80211_BAND_5GHZ)
124 mandatory = 0xff00; /* OFDM 6/9/12/18/24/36/48/54 */
125 else
126 mandatory = 0xff0f; /* OFDM (6/9../54) + CCK (1/2/5.5/11) */
127
128 carl9170_regwrite_begin(ar);
129 carl9170_regwrite(AR9170_MAC_REG_BASIC_RATE, basic);
130 carl9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, mandatory);
131 carl9170_regwrite_finish();
132
133 return carl9170_regwrite_result();
134}
135
136int carl9170_set_qos(struct ar9170 *ar)
137{
138 carl9170_regwrite_begin(ar);
139
140 carl9170_regwrite(AR9170_MAC_REG_AC0_CW, ar->edcf[0].cw_min |
141 (ar->edcf[0].cw_max << 16));
142 carl9170_regwrite(AR9170_MAC_REG_AC1_CW, ar->edcf[1].cw_min |
143 (ar->edcf[1].cw_max << 16));
144 carl9170_regwrite(AR9170_MAC_REG_AC2_CW, ar->edcf[2].cw_min |
145 (ar->edcf[2].cw_max << 16));
146 carl9170_regwrite(AR9170_MAC_REG_AC3_CW, ar->edcf[3].cw_min |
147 (ar->edcf[3].cw_max << 16));
148 carl9170_regwrite(AR9170_MAC_REG_AC4_CW, ar->edcf[4].cw_min |
149 (ar->edcf[4].cw_max << 16));
150
151 carl9170_regwrite(AR9170_MAC_REG_AC2_AC1_AC0_AIFS,
152 ((ar->edcf[0].aifs * 9 + 10)) |
153 ((ar->edcf[1].aifs * 9 + 10) << 12) |
154 ((ar->edcf[2].aifs * 9 + 10) << 24));
155 carl9170_regwrite(AR9170_MAC_REG_AC4_AC3_AC2_AIFS,
156 ((ar->edcf[2].aifs * 9 + 10) >> 8) |
157 ((ar->edcf[3].aifs * 9 + 10) << 4) |
158 ((ar->edcf[4].aifs * 9 + 10) << 16));
159
160 carl9170_regwrite(AR9170_MAC_REG_AC1_AC0_TXOP,
161 ar->edcf[0].txop | ar->edcf[1].txop << 16);
162 carl9170_regwrite(AR9170_MAC_REG_AC3_AC2_TXOP,
163 ar->edcf[2].txop | ar->edcf[3].txop << 16 |
164 ar->edcf[4].txop << 24);
165
166 carl9170_regwrite_finish();
167
168 return carl9170_regwrite_result();
169}
170
171int carl9170_init_mac(struct ar9170 *ar)
172{
173 carl9170_regwrite_begin(ar);
174
175 /* switch MAC to OTUS interface */
176 carl9170_regwrite(0x1c3600, 0x3);
177
178 carl9170_regwrite(AR9170_MAC_REG_ACK_EXTENSION, 0x40);
179
180 carl9170_regwrite(AR9170_MAC_REG_RETRY_MAX, 0x0);
181
182 carl9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
183 AR9170_MAC_FTF_MONITOR);
184
185 /* enable MMIC */
186 carl9170_regwrite(AR9170_MAC_REG_SNIFFER,
187 AR9170_MAC_SNIFFER_DEFAULTS);
188
189 carl9170_regwrite(AR9170_MAC_REG_RX_THRESHOLD, 0xc1f80);
190
191 carl9170_regwrite(AR9170_MAC_REG_RX_PE_DELAY, 0x70);
192 carl9170_regwrite(AR9170_MAC_REG_EIFS_AND_SIFS, 0xa144000);
193 carl9170_regwrite(AR9170_MAC_REG_SLOT_TIME, 9 << 10);
194
195 /* CF-END & CF-ACK rate => 24M OFDM */
196 carl9170_regwrite(AR9170_MAC_REG_TID_CFACK_CFEND_RATE, 0x59900000);
197
198 /* NAV protects ACK only (in TXOP) */
199 carl9170_regwrite(AR9170_MAC_REG_TXOP_DURATION, 0x201);
200
201 /* Set Beacon PHY CTRL's TPC to 0x7, TA1=1 */
202 /* OTUS set AM to 0x1 */
203 carl9170_regwrite(AR9170_MAC_REG_BCN_HT1, 0x8000170);
204
205 carl9170_regwrite(AR9170_MAC_REG_BACKOFF_PROTECT, 0x105);
206
207 /* Aggregation MAX number and timeout */
208 carl9170_regwrite(AR9170_MAC_REG_AMPDU_FACTOR, 0xa);
209 carl9170_regwrite(AR9170_MAC_REG_AMPDU_DENSITY, 0x140a00);
210
211 carl9170_regwrite(AR9170_MAC_REG_FRAMETYPE_FILTER,
212 AR9170_MAC_FTF_DEFAULTS);
213
214 carl9170_regwrite(AR9170_MAC_REG_RX_CONTROL,
215 AR9170_MAC_RX_CTRL_DEAGG |
216 AR9170_MAC_RX_CTRL_SHORT_FILTER);
217
218 /* rate sets */
219 carl9170_regwrite(AR9170_MAC_REG_BASIC_RATE, 0x150f);
220 carl9170_regwrite(AR9170_MAC_REG_MANDATORY_RATE, 0x150f);
221 carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_RATE, 0x0030033);
222
223 /* MIMO response control */
224 carl9170_regwrite(AR9170_MAC_REG_ACK_TPC, 0x4003c1e);
225
226 carl9170_regwrite(AR9170_MAC_REG_AMPDU_RX_THRESH, 0xffff);
227
228 /* set PHY register read timeout (??) */
229 carl9170_regwrite(AR9170_MAC_REG_MISC_680, 0xf00008);
230
231 /* Disable Rx TimeOut, workaround for BB. */
232 carl9170_regwrite(AR9170_MAC_REG_RX_TIMEOUT, 0x0);
233
234 /* Set WLAN DMA interrupt mode: generate int per packet */
235 carl9170_regwrite(AR9170_MAC_REG_TXRX_MPI, 0x110011);
236
237 carl9170_regwrite(AR9170_MAC_REG_FCS_SELECT,
238 AR9170_MAC_FCS_FIFO_PROT);
239
240 /* Disables the CF_END frame, undocumented register */
241 carl9170_regwrite(AR9170_MAC_REG_TXOP_NOT_ENOUGH_IND,
242 0x141e0f48);
243
244 /* reset group hash table */
245 carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, 0xffffffff);
246 carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, 0xffffffff);
247
248 /* disable PRETBTT interrupt */
249 carl9170_regwrite(AR9170_MAC_REG_PRETBTT, 0x0);
250 carl9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, 0x0);
251
252 carl9170_regwrite_finish();
253
254 return carl9170_regwrite_result();
255}
256
257static int carl9170_set_mac_reg(struct ar9170 *ar,
258 const u32 reg, const u8 *mac)
259{
260 static const u8 zero[ETH_ALEN] = { 0 };
261
262 if (!mac)
263 mac = zero;
264
265 carl9170_regwrite_begin(ar);
266
267 carl9170_regwrite(reg, get_unaligned_le32(mac));
268 carl9170_regwrite(reg + 4, get_unaligned_le16(mac + 4));
269
270 carl9170_regwrite_finish();
271
272 return carl9170_regwrite_result();
273}
274
275int carl9170_mod_virtual_mac(struct ar9170 *ar, const unsigned int id,
276 const u8 *mac)
277{
278 if (WARN_ON(id >= ar->fw.vif_num))
279 return -EINVAL;
280
281 return carl9170_set_mac_reg(ar,
282 AR9170_MAC_REG_ACK_TABLE + (id - 1) * 8, mac);
283}
284
285int carl9170_update_multicast(struct ar9170 *ar, const u64 mc_hash)
286{
287 int err;
288
289 carl9170_regwrite_begin(ar);
290 carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_H, mc_hash >> 32);
291 carl9170_regwrite(AR9170_MAC_REG_GROUP_HASH_TBL_L, mc_hash);
292 carl9170_regwrite_finish();
293 err = carl9170_regwrite_result();
294 if (err)
295 return err;
296
297 ar->cur_mc_hash = mc_hash;
298 return 0;
299}
300
301int carl9170_set_operating_mode(struct ar9170 *ar)
302{
303 struct ieee80211_vif *vif;
304 struct ath_common *common = &ar->common;
305 u8 *mac_addr, *bssid;
306 u32 cam_mode = AR9170_MAC_CAM_DEFAULTS;
307 u32 enc_mode = AR9170_MAC_ENCRYPTION_DEFAULTS;
308 u32 rx_ctrl = AR9170_MAC_RX_CTRL_DEAGG |
309 AR9170_MAC_RX_CTRL_SHORT_FILTER;
310 u32 sniffer = AR9170_MAC_SNIFFER_DEFAULTS;
311 int err = 0;
312
313 rcu_read_lock();
314 vif = carl9170_get_main_vif(ar);
315
316 if (vif) {
317 mac_addr = common->macaddr;
318 bssid = common->curbssid;
319
320 switch (vif->type) {
321 case NL80211_IFTYPE_MESH_POINT:
322 case NL80211_IFTYPE_ADHOC:
323 cam_mode |= AR9170_MAC_CAM_IBSS;
324 break;
325 case NL80211_IFTYPE_AP:
326 cam_mode |= AR9170_MAC_CAM_AP;
327
328 /* iwlagn 802.11n STA Workaround */
329 rx_ctrl |= AR9170_MAC_RX_CTRL_PASS_TO_HOST;
330 break;
331 case NL80211_IFTYPE_WDS:
332 cam_mode |= AR9170_MAC_CAM_AP_WDS;
333 rx_ctrl |= AR9170_MAC_RX_CTRL_PASS_TO_HOST;
334 break;
335 case NL80211_IFTYPE_STATION:
336 cam_mode |= AR9170_MAC_CAM_STA;
337 rx_ctrl |= AR9170_MAC_RX_CTRL_PASS_TO_HOST;
338 break;
339 default:
340 WARN(1, "Unsupported operation mode %x\n", vif->type);
341 err = -EOPNOTSUPP;
342 break;
343 }
344 } else {
345 mac_addr = NULL;
346 bssid = NULL;
347 }
348 rcu_read_unlock();
349
350 if (err)
351 return err;
352
353 if (ar->rx_software_decryption)
354 enc_mode |= AR9170_MAC_ENCRYPTION_RX_SOFTWARE;
355
356 if (ar->sniffer_enabled) {
357 rx_ctrl |= AR9170_MAC_RX_CTRL_ACK_IN_SNIFFER;
358 sniffer |= AR9170_MAC_SNIFFER_ENABLE_PROMISC;
359 enc_mode |= AR9170_MAC_ENCRYPTION_RX_SOFTWARE;
360 }
361
362 err = carl9170_set_mac_reg(ar, AR9170_MAC_REG_MAC_ADDR_L, mac_addr);
363 if (err)
364 return err;
365
366 err = carl9170_set_mac_reg(ar, AR9170_MAC_REG_BSSID_L, bssid);
367 if (err)
368 return err;
369
370 carl9170_regwrite_begin(ar);
371 carl9170_regwrite(AR9170_MAC_REG_SNIFFER, sniffer);
372 carl9170_regwrite(AR9170_MAC_REG_CAM_MODE, cam_mode);
373 carl9170_regwrite(AR9170_MAC_REG_ENCRYPTION, enc_mode);
374 carl9170_regwrite(AR9170_MAC_REG_RX_CONTROL, rx_ctrl);
375 carl9170_regwrite_finish();
376
377 return carl9170_regwrite_result();
378}
379
380int carl9170_set_hwretry_limit(struct ar9170 *ar, const unsigned int max_retry)
381{
382 u32 tmp = min_t(u32, 0x33333, max_retry * 0x11111);
383
384 return carl9170_write_reg(ar, AR9170_MAC_REG_RETRY_MAX, tmp);
385}
386
387int carl9170_set_beacon_timers(struct ar9170 *ar)
388{
389 struct ieee80211_vif *vif;
390 u32 v = 0;
391 u32 pretbtt = 0;
392
393 rcu_read_lock();
394 vif = carl9170_get_main_vif(ar);
395
396 if (vif) {
397 struct carl9170_vif_info *mvif;
398 mvif = (void *) vif->drv_priv;
399
400 if (mvif->enable_beacon && !WARN_ON(!ar->beacon_enabled)) {
401 ar->global_beacon_int = vif->bss_conf.beacon_int /
402 ar->beacon_enabled;
403
404 SET_VAL(AR9170_MAC_BCN_DTIM, v,
405 vif->bss_conf.dtim_period);
406
407 switch (vif->type) {
408 case NL80211_IFTYPE_MESH_POINT:
409 case NL80211_IFTYPE_ADHOC:
410 v |= AR9170_MAC_BCN_IBSS_MODE;
411 break;
412 case NL80211_IFTYPE_AP:
413 v |= AR9170_MAC_BCN_AP_MODE;
414 break;
415 default:
416 WARN_ON_ONCE(1);
417 break;
418 }
419 } else if (vif->type == NL80211_IFTYPE_STATION) {
420 ar->global_beacon_int = vif->bss_conf.beacon_int;
421
422 SET_VAL(AR9170_MAC_BCN_DTIM, v,
423 ar->hw->conf.ps_dtim_period);
424
425 v |= AR9170_MAC_BCN_STA_PS |
426 AR9170_MAC_BCN_PWR_MGT;
427 }
428
429 if (ar->global_beacon_int) {
430 if (ar->global_beacon_int < 15) {
431 rcu_read_unlock();
432 return -ERANGE;
433 }
434
435 ar->global_pretbtt = ar->global_beacon_int -
436 CARL9170_PRETBTT_KUS;
437 } else {
438 ar->global_pretbtt = 0;
439 }
440 } else {
441 ar->global_beacon_int = 0;
442 ar->global_pretbtt = 0;
443 }
444
445 rcu_read_unlock();
446
447 SET_VAL(AR9170_MAC_BCN_PERIOD, v, ar->global_beacon_int);
448 SET_VAL(AR9170_MAC_PRETBTT, pretbtt, ar->global_pretbtt);
449 SET_VAL(AR9170_MAC_PRETBTT2, pretbtt, ar->global_pretbtt);
450
451 carl9170_regwrite_begin(ar);
452 carl9170_regwrite(AR9170_MAC_REG_PRETBTT, pretbtt);
453 carl9170_regwrite(AR9170_MAC_REG_BCN_PERIOD, v);
454 carl9170_regwrite_finish();
455 return carl9170_regwrite_result();
456}
457
458int carl9170_update_beacon(struct ar9170 *ar, const bool submit)
459{
460 struct sk_buff *skb;
461 struct carl9170_vif_info *cvif;
462 __le32 *data, *old = NULL;
463 u32 word, off, addr, len;
464 int i = 0, err = 0;
465
466 rcu_read_lock();
467 cvif = rcu_dereference(ar->beacon_iter);
468retry:
469 if (ar->vifs == 0 || !cvif)
470 goto out_unlock;
471
472 list_for_each_entry_continue_rcu(cvif, &ar->vif_list, list) {
473 if (cvif->active && cvif->enable_beacon)
474 goto found;
475 }
476
477 if (!ar->beacon_enabled || i++)
478 goto out_unlock;
479
480 goto retry;
481
482found:
483 rcu_assign_pointer(ar->beacon_iter, cvif);
484
485 skb = ieee80211_beacon_get_tim(ar->hw, carl9170_get_vif(cvif),
486 NULL, NULL);
487
488 if (!skb) {
489 err = -ENOMEM;
490 goto out_unlock;
491 }
492
493 spin_lock_bh(&ar->beacon_lock);
494 data = (__le32 *)skb->data;
495 if (cvif->beacon)
496 old = (__le32 *)cvif->beacon->data;
497
498 off = cvif->id * AR9170_MAC_BCN_LENGTH_MAX;
499 addr = ar->fw.beacon_addr + off;
500 len = roundup(skb->len + FCS_LEN, 4);
501
502 if ((off + len) > ar->fw.beacon_max_len) {
503 if (net_ratelimit()) {
504 wiphy_err(ar->hw->wiphy, "beacon does not "
505 "fit into device memory!\n");
506 }
507
508 spin_unlock_bh(&ar->beacon_lock);
509 dev_kfree_skb_any(skb);
510 err = -EINVAL;
511 goto out_unlock;
512 }
513
514 if (len > AR9170_MAC_BCN_LENGTH_MAX) {
515 if (net_ratelimit()) {
516 wiphy_err(ar->hw->wiphy, "no support for beacons "
517 "bigger than %d (yours:%d).\n",
518 AR9170_MAC_BCN_LENGTH_MAX, len);
519 }
520
521 spin_unlock_bh(&ar->beacon_lock);
522 dev_kfree_skb_any(skb);
523 err = -EMSGSIZE;
524 goto out_unlock;
525 }
526
527 carl9170_async_regwrite_begin(ar);
528
529 /* XXX: use skb->cb info */
530 if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
531 carl9170_async_regwrite(AR9170_MAC_REG_BCN_PLCP,
532 ((skb->len + FCS_LEN) << (3 + 16)) + 0x0400);
533 } else {
534 carl9170_async_regwrite(AR9170_MAC_REG_BCN_PLCP,
535 ((skb->len + FCS_LEN) << 16) + 0x001b);
536 }
537
538 for (i = 0; i < DIV_ROUND_UP(skb->len, 4); i++) {
539 /*
540 * XXX: This accesses beyond skb data for up
541 * to the last 3 bytes!!
542 */
543
544 if (old && (data[i] == old[i]))
545 continue;
546
547 word = le32_to_cpu(data[i]);
548 carl9170_async_regwrite(addr + 4 * i, word);
549 }
550 carl9170_async_regwrite_finish();
551
552 dev_kfree_skb_any(cvif->beacon);
553 cvif->beacon = NULL;
554
555 err = carl9170_async_regwrite_result();
556 if (!err)
557 cvif->beacon = skb;
558 spin_unlock_bh(&ar->beacon_lock);
559 if (err)
560 goto out_unlock;
561
562 if (submit) {
563 err = carl9170_bcn_ctrl(ar, cvif->id,
564 CARL9170_BCN_CTRL_CAB_TRIGGER,
565 addr, skb->len + FCS_LEN);
566
567 if (err)
568 goto out_unlock;
569 }
570out_unlock:
571 rcu_read_unlock();
572 return err;
573}
574
575int carl9170_upload_key(struct ar9170 *ar, const u8 id, const u8 *mac,
576 const u8 ktype, const u8 keyidx, const u8 *keydata,
577 const int keylen)
578{
579 struct carl9170_set_key_cmd key = { };
580 static const u8 bcast[ETH_ALEN] = {
581 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
582
583 mac = mac ? : bcast;
584
585 key.user = cpu_to_le16(id);
586 key.keyId = cpu_to_le16(keyidx);
587 key.type = cpu_to_le16(ktype);
588 memcpy(&key.macAddr, mac, ETH_ALEN);
589 if (keydata)
590 memcpy(&key.key, keydata, keylen);
591
592 return carl9170_exec_cmd(ar, CARL9170_CMD_EKEY,
593 sizeof(key), (u8 *)&key, 0, NULL);
594}
595
596int carl9170_disable_key(struct ar9170 *ar, const u8 id)
597{
598 struct carl9170_disable_key_cmd key = { };
599
600 key.user = cpu_to_le16(id);
601
602 return carl9170_exec_cmd(ar, CARL9170_CMD_DKEY,
603 sizeof(key), (u8 *)&key, 0, NULL);
604}
diff --git a/drivers/net/wireless/ath/carl9170/phy.c b/drivers/net/wireless/ath/carl9170/phy.c
new file mode 100644
index 000000000000..47709c13d964
--- /dev/null
+++ b/drivers/net/wireless/ath/carl9170/phy.c
@@ -0,0 +1,1805 @@
1/*
2 * Atheros CARL9170 driver
3 *
4 * PHY and RF code
5 *
6 * Copyright 2008, Johannes Berg <johannes@sipsolutions.net>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, see
20 * http://www.gnu.org/licenses/.
21 *
22 * This file incorporates work covered by the following copyright and
23 * permission notice:
24 * Copyright (c) 2007-2008 Atheros Communications, Inc.
25 *
26 * Permission to use, copy, modify, and/or distribute this software for any
27 * purpose with or without fee is hereby granted, provided that the above
28 * copyright notice and this permission notice appear in all copies.
29 *
30 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
31 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
32 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
33 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
34 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
35 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
36 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
37 */
38
39#include <linux/bitrev.h>
40#include "carl9170.h"
41#include "cmd.h"
42#include "phy.h"
43
44static int carl9170_init_power_cal(struct ar9170 *ar)
45{
46 carl9170_regwrite_begin(ar);
47
48 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE_MAX, 0x7f);
49 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE1, 0x3f3f3f3f);
50 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE2, 0x3f3f3f3f);
51 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE3, 0x3f3f3f3f);
52 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE4, 0x3f3f3f3f);
53 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE5, 0x3f3f3f3f);
54 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE6, 0x3f3f3f3f);
55 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE7, 0x3f3f3f3f);
56 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE8, 0x3f3f3f3f);
57 carl9170_regwrite(AR9170_PHY_REG_POWER_TX_RATE9, 0x3f3f3f3f);
58
59 carl9170_regwrite_finish();
60 return carl9170_regwrite_result();
61}
62
63struct carl9170_phy_init {
64 u32 reg, _5ghz_20, _5ghz_40, _2ghz_40, _2ghz_20;
65};
66
67static struct carl9170_phy_init ar5416_phy_init[] = {
68 { 0x1c5800, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
69 { 0x1c5804, 0x00000300, 0x000003c4, 0x000003c4, 0x00000300, },
70 { 0x1c5808, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
71 { 0x1c580c, 0xad848e19, 0xad848e19, 0xad848e19, 0xad848e19, },
72 { 0x1c5810, 0x7d14e000, 0x7d14e000, 0x7d14e000, 0x7d14e000, },
73 { 0x1c5814, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, 0x9c0a9f6b, },
74 { 0x1c5818, 0x00000090, 0x00000090, 0x00000090, 0x00000090, },
75 { 0x1c581c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
76 { 0x1c5820, 0x02020200, 0x02020200, 0x02020200, 0x02020200, },
77 { 0x1c5824, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, },
78 { 0x1c5828, 0x0a020001, 0x0a020001, 0x0a020001, 0x0a020001, },
79 { 0x1c582c, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, },
80 { 0x1c5830, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
81 { 0x1c5834, 0x00000e0e, 0x00000e0e, 0x00000e0e, 0x00000e0e, },
82 { 0x1c5838, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
83 { 0x1c583c, 0x00200400, 0x00200400, 0x00200400, 0x00200400, },
84 { 0x1c5840, 0x206a002e, 0x206a002e, 0x206a002e, 0x206a002e, },
85 { 0x1c5844, 0x1372161e, 0x13721c1e, 0x13721c24, 0x137216a4, },
86 { 0x1c5848, 0x001a6a65, 0x001a6a65, 0x00197a68, 0x00197a68, },
87 { 0x1c584c, 0x1284233c, 0x1284233c, 0x1284233c, 0x1284233c, },
88 { 0x1c5850, 0x6c48b4e4, 0x6c48b4e4, 0x6c48b0e4, 0x6c48b0e4, },
89 { 0x1c5854, 0x00000859, 0x00000859, 0x00000859, 0x00000859, },
90 { 0x1c5858, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, 0x7ec80d2e, },
91 { 0x1c585c, 0x31395c5e, 0x31395c5e, 0x31395c5e, 0x31395c5e, },
92 { 0x1c5860, 0x0004dd10, 0x0004dd10, 0x0004dd20, 0x0004dd20, },
93 { 0x1c5868, 0x409a4190, 0x409a4190, 0x409a4190, 0x409a4190, },
94 { 0x1c586c, 0x050cb081, 0x050cb081, 0x050cb081, 0x050cb081, },
95 { 0x1c5900, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
96 { 0x1c5904, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
97 { 0x1c5908, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
98 { 0x1c590c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
99 { 0x1c5914, 0x000007d0, 0x000007d0, 0x00000898, 0x00000898, },
100 { 0x1c5918, 0x00000118, 0x00000230, 0x00000268, 0x00000134, },
101 { 0x1c591c, 0x10000fff, 0x10000fff, 0x10000fff, 0x10000fff, },
102 { 0x1c5920, 0x0510081c, 0x0510081c, 0x0510001c, 0x0510001c, },
103 { 0x1c5924, 0xd0058a15, 0xd0058a15, 0xd0058a15, 0xd0058a15, },
104 { 0x1c5928, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
105 { 0x1c592c, 0x00000004, 0x00000004, 0x00000004, 0x00000004, },
106 { 0x1c5934, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
107 { 0x1c5938, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
108 { 0x1c593c, 0x0000007f, 0x0000007f, 0x0000007f, 0x0000007f, },
109 { 0x1c5944, 0xdfb81020, 0xdfb81020, 0xdfb81020, 0xdfb81020, },
110 { 0x1c5948, 0x9280b212, 0x9280b212, 0x9280b212, 0x9280b212, },
111 { 0x1c594c, 0x00020028, 0x00020028, 0x00020028, 0x00020028, },
112 { 0x1c5954, 0x5d50e188, 0x5d50e188, 0x5d50e188, 0x5d50e188, },
113 { 0x1c5958, 0x00081fff, 0x00081fff, 0x00081fff, 0x00081fff, },
114 { 0x1c5960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
115 { 0x1c5964, 0x00001120, 0x00001120, 0x00001120, 0x00001120, },
116 { 0x1c5970, 0x190fb515, 0x190fb515, 0x190fb515, 0x190fb515, },
117 { 0x1c5974, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
118 { 0x1c5978, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
119 { 0x1c597c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
120 { 0x1c5980, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
121 { 0x1c5984, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
122 { 0x1c5988, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
123 { 0x1c598c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
124 { 0x1c5990, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
125 { 0x1c5994, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
126 { 0x1c5998, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
127 { 0x1c599c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
128 { 0x1c59a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
129 { 0x1c59a4, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
130 { 0x1c59a8, 0x001fff00, 0x001fff00, 0x001fff00, 0x001fff00, },
131 { 0x1c59ac, 0x006f00c4, 0x006f00c4, 0x006f00c4, 0x006f00c4, },
132 { 0x1c59b0, 0x03051000, 0x03051000, 0x03051000, 0x03051000, },
133 { 0x1c59b4, 0x00000820, 0x00000820, 0x00000820, 0x00000820, },
134 { 0x1c59c0, 0x038919be, 0x038919be, 0x038919be, 0x038919be, },
135 { 0x1c59c4, 0x06336f77, 0x06336f77, 0x06336f77, 0x06336f77, },
136 { 0x1c59c8, 0x60f6532c, 0x60f6532c, 0x60f6532c, 0x60f6532c, },
137 { 0x1c59cc, 0x08f186c8, 0x08f186c8, 0x08f186c8, 0x08f186c8, },
138 { 0x1c59d0, 0x00046384, 0x00046384, 0x00046384, 0x00046384, },
139 { 0x1c59d4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
140 { 0x1c59d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
141 { 0x1c59dc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
142 { 0x1c59e0, 0x00000200, 0x00000200, 0x00000200, 0x00000200, },
143 { 0x1c59e4, 0x64646464, 0x64646464, 0x64646464, 0x64646464, },
144 { 0x1c59e8, 0x3c787878, 0x3c787878, 0x3c787878, 0x3c787878, },
145 { 0x1c59ec, 0x000000aa, 0x000000aa, 0x000000aa, 0x000000aa, },
146 { 0x1c59f0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
147 { 0x1c59fc, 0x00001042, 0x00001042, 0x00001042, 0x00001042, },
148 { 0x1c5a00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
149 { 0x1c5a04, 0x00000040, 0x00000040, 0x00000040, 0x00000040, },
150 { 0x1c5a08, 0x00000080, 0x00000080, 0x00000080, 0x00000080, },
151 { 0x1c5a0c, 0x000001a1, 0x000001a1, 0x00000141, 0x00000141, },
152 { 0x1c5a10, 0x000001e1, 0x000001e1, 0x00000181, 0x00000181, },
153 { 0x1c5a14, 0x00000021, 0x00000021, 0x000001c1, 0x000001c1, },
154 { 0x1c5a18, 0x00000061, 0x00000061, 0x00000001, 0x00000001, },
155 { 0x1c5a1c, 0x00000168, 0x00000168, 0x00000041, 0x00000041, },
156 { 0x1c5a20, 0x000001a8, 0x000001a8, 0x000001a8, 0x000001a8, },
157 { 0x1c5a24, 0x000001e8, 0x000001e8, 0x000001e8, 0x000001e8, },
158 { 0x1c5a28, 0x00000028, 0x00000028, 0x00000028, 0x00000028, },
159 { 0x1c5a2c, 0x00000068, 0x00000068, 0x00000068, 0x00000068, },
160 { 0x1c5a30, 0x00000189, 0x00000189, 0x000000a8, 0x000000a8, },
161 { 0x1c5a34, 0x000001c9, 0x000001c9, 0x00000169, 0x00000169, },
162 { 0x1c5a38, 0x00000009, 0x00000009, 0x000001a9, 0x000001a9, },
163 { 0x1c5a3c, 0x00000049, 0x00000049, 0x000001e9, 0x000001e9, },
164 { 0x1c5a40, 0x00000089, 0x00000089, 0x00000029, 0x00000029, },
165 { 0x1c5a44, 0x00000170, 0x00000170, 0x00000069, 0x00000069, },
166 { 0x1c5a48, 0x000001b0, 0x000001b0, 0x00000190, 0x00000190, },
167 { 0x1c5a4c, 0x000001f0, 0x000001f0, 0x000001d0, 0x000001d0, },
168 { 0x1c5a50, 0x00000030, 0x00000030, 0x00000010, 0x00000010, },
169 { 0x1c5a54, 0x00000070, 0x00000070, 0x00000050, 0x00000050, },
170 { 0x1c5a58, 0x00000191, 0x00000191, 0x00000090, 0x00000090, },
171 { 0x1c5a5c, 0x000001d1, 0x000001d1, 0x00000151, 0x00000151, },
172 { 0x1c5a60, 0x00000011, 0x00000011, 0x00000191, 0x00000191, },
173 { 0x1c5a64, 0x00000051, 0x00000051, 0x000001d1, 0x000001d1, },
174 { 0x1c5a68, 0x00000091, 0x00000091, 0x00000011, 0x00000011, },
175 { 0x1c5a6c, 0x000001b8, 0x000001b8, 0x00000051, 0x00000051, },
176 { 0x1c5a70, 0x000001f8, 0x000001f8, 0x00000198, 0x00000198, },
177 { 0x1c5a74, 0x00000038, 0x00000038, 0x000001d8, 0x000001d8, },
178 { 0x1c5a78, 0x00000078, 0x00000078, 0x00000018, 0x00000018, },
179 { 0x1c5a7c, 0x00000199, 0x00000199, 0x00000058, 0x00000058, },
180 { 0x1c5a80, 0x000001d9, 0x000001d9, 0x00000098, 0x00000098, },
181 { 0x1c5a84, 0x00000019, 0x00000019, 0x00000159, 0x00000159, },
182 { 0x1c5a88, 0x00000059, 0x00000059, 0x00000199, 0x00000199, },
183 { 0x1c5a8c, 0x00000099, 0x00000099, 0x000001d9, 0x000001d9, },
184 { 0x1c5a90, 0x000000d9, 0x000000d9, 0x00000019, 0x00000019, },
185 { 0x1c5a94, 0x000000f9, 0x000000f9, 0x00000059, 0x00000059, },
186 { 0x1c5a98, 0x000000f9, 0x000000f9, 0x00000099, 0x00000099, },
187 { 0x1c5a9c, 0x000000f9, 0x000000f9, 0x000000d9, 0x000000d9, },
188 { 0x1c5aa0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
189 { 0x1c5aa4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
190 { 0x1c5aa8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
191 { 0x1c5aac, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
192 { 0x1c5ab0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
193 { 0x1c5ab4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
194 { 0x1c5ab8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
195 { 0x1c5abc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
196 { 0x1c5ac0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
197 { 0x1c5ac4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
198 { 0x1c5ac8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
199 { 0x1c5acc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
200 { 0x1c5ad0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
201 { 0x1c5ad4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
202 { 0x1c5ad8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
203 { 0x1c5adc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
204 { 0x1c5ae0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
205 { 0x1c5ae4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
206 { 0x1c5ae8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
207 { 0x1c5aec, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
208 { 0x1c5af0, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
209 { 0x1c5af4, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
210 { 0x1c5af8, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
211 { 0x1c5afc, 0x000000f9, 0x000000f9, 0x000000f9, 0x000000f9, },
212 { 0x1c5b00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
213 { 0x1c5b04, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
214 { 0x1c5b08, 0x00000002, 0x00000002, 0x00000002, 0x00000002, },
215 { 0x1c5b0c, 0x00000003, 0x00000003, 0x00000003, 0x00000003, },
216 { 0x1c5b10, 0x00000004, 0x00000004, 0x00000004, 0x00000004, },
217 { 0x1c5b14, 0x00000005, 0x00000005, 0x00000005, 0x00000005, },
218 { 0x1c5b18, 0x00000008, 0x00000008, 0x00000008, 0x00000008, },
219 { 0x1c5b1c, 0x00000009, 0x00000009, 0x00000009, 0x00000009, },
220 { 0x1c5b20, 0x0000000a, 0x0000000a, 0x0000000a, 0x0000000a, },
221 { 0x1c5b24, 0x0000000b, 0x0000000b, 0x0000000b, 0x0000000b, },
222 { 0x1c5b28, 0x0000000c, 0x0000000c, 0x0000000c, 0x0000000c, },
223 { 0x1c5b2c, 0x0000000d, 0x0000000d, 0x0000000d, 0x0000000d, },
224 { 0x1c5b30, 0x00000010, 0x00000010, 0x00000010, 0x00000010, },
225 { 0x1c5b34, 0x00000011, 0x00000011, 0x00000011, 0x00000011, },
226 { 0x1c5b38, 0x00000012, 0x00000012, 0x00000012, 0x00000012, },
227 { 0x1c5b3c, 0x00000013, 0x00000013, 0x00000013, 0x00000013, },
228 { 0x1c5b40, 0x00000014, 0x00000014, 0x00000014, 0x00000014, },
229 { 0x1c5b44, 0x00000015, 0x00000015, 0x00000015, 0x00000015, },
230 { 0x1c5b48, 0x00000018, 0x00000018, 0x00000018, 0x00000018, },
231 { 0x1c5b4c, 0x00000019, 0x00000019, 0x00000019, 0x00000019, },
232 { 0x1c5b50, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, },
233 { 0x1c5b54, 0x0000001b, 0x0000001b, 0x0000001b, 0x0000001b, },
234 { 0x1c5b58, 0x0000001c, 0x0000001c, 0x0000001c, 0x0000001c, },
235 { 0x1c5b5c, 0x0000001d, 0x0000001d, 0x0000001d, 0x0000001d, },
236 { 0x1c5b60, 0x00000020, 0x00000020, 0x00000020, 0x00000020, },
237 { 0x1c5b64, 0x00000021, 0x00000021, 0x00000021, 0x00000021, },
238 { 0x1c5b68, 0x00000022, 0x00000022, 0x00000022, 0x00000022, },
239 { 0x1c5b6c, 0x00000023, 0x00000023, 0x00000023, 0x00000023, },
240 { 0x1c5b70, 0x00000024, 0x00000024, 0x00000024, 0x00000024, },
241 { 0x1c5b74, 0x00000025, 0x00000025, 0x00000025, 0x00000025, },
242 { 0x1c5b78, 0x00000028, 0x00000028, 0x00000028, 0x00000028, },
243 { 0x1c5b7c, 0x00000029, 0x00000029, 0x00000029, 0x00000029, },
244 { 0x1c5b80, 0x0000002a, 0x0000002a, 0x0000002a, 0x0000002a, },
245 { 0x1c5b84, 0x0000002b, 0x0000002b, 0x0000002b, 0x0000002b, },
246 { 0x1c5b88, 0x0000002c, 0x0000002c, 0x0000002c, 0x0000002c, },
247 { 0x1c5b8c, 0x0000002d, 0x0000002d, 0x0000002d, 0x0000002d, },
248 { 0x1c5b90, 0x00000030, 0x00000030, 0x00000030, 0x00000030, },
249 { 0x1c5b94, 0x00000031, 0x00000031, 0x00000031, 0x00000031, },
250 { 0x1c5b98, 0x00000032, 0x00000032, 0x00000032, 0x00000032, },
251 { 0x1c5b9c, 0x00000033, 0x00000033, 0x00000033, 0x00000033, },
252 { 0x1c5ba0, 0x00000034, 0x00000034, 0x00000034, 0x00000034, },
253 { 0x1c5ba4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
254 { 0x1c5ba8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
255 { 0x1c5bac, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
256 { 0x1c5bb0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
257 { 0x1c5bb4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
258 { 0x1c5bb8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
259 { 0x1c5bbc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
260 { 0x1c5bc0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
261 { 0x1c5bc4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
262 { 0x1c5bc8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
263 { 0x1c5bcc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
264 { 0x1c5bd0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
265 { 0x1c5bd4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
266 { 0x1c5bd8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
267 { 0x1c5bdc, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
268 { 0x1c5be0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
269 { 0x1c5be4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
270 { 0x1c5be8, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
271 { 0x1c5bec, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
272 { 0x1c5bf0, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
273 { 0x1c5bf4, 0x00000035, 0x00000035, 0x00000035, 0x00000035, },
274 { 0x1c5bf8, 0x00000010, 0x00000010, 0x00000010, 0x00000010, },
275 { 0x1c5bfc, 0x0000001a, 0x0000001a, 0x0000001a, 0x0000001a, },
276 { 0x1c5c00, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
277 { 0x1c5c0c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
278 { 0x1c5c10, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
279 { 0x1c5c14, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
280 { 0x1c5c18, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
281 { 0x1c5c1c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
282 { 0x1c5c20, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
283 { 0x1c5c24, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
284 { 0x1c5c28, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
285 { 0x1c5c2c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
286 { 0x1c5c30, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
287 { 0x1c5c34, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
288 { 0x1c5c38, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
289 { 0x1c5c3c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
290 { 0x1c5cf0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
291 { 0x1c5cf4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
292 { 0x1c5cf8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
293 { 0x1c5cfc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
294 { 0x1c6200, 0x00000008, 0x00000008, 0x0000000e, 0x0000000e, },
295 { 0x1c6204, 0x00000440, 0x00000440, 0x00000440, 0x00000440, },
296 { 0x1c6208, 0xd6be4788, 0xd6be4788, 0xd03e4788, 0xd03e4788, },
297 { 0x1c620c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
298 { 0x1c6210, 0x40806333, 0x40806333, 0x40806333, 0x40806333, },
299 { 0x1c6214, 0x00106c10, 0x00106c10, 0x00106c10, 0x00106c10, },
300 { 0x1c6218, 0x009c4060, 0x009c4060, 0x009c4060, 0x009c4060, },
301 { 0x1c621c, 0x1883800a, 0x1883800a, 0x1883800a, 0x1883800a, },
302 { 0x1c6220, 0x018830c6, 0x018830c6, 0x018830c6, 0x018830c6, },
303 { 0x1c6224, 0x00000400, 0x00000400, 0x00000400, 0x00000400, },
304 { 0x1c6228, 0x000009b5, 0x000009b5, 0x000009b5, 0x000009b5, },
305 { 0x1c622c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
306 { 0x1c6230, 0x00000108, 0x00000210, 0x00000210, 0x00000108, },
307 { 0x1c6234, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
308 { 0x1c6238, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
309 { 0x1c623c, 0x13c889af, 0x13c889af, 0x13c889af, 0x13c889af, },
310 { 0x1c6240, 0x38490a20, 0x38490a20, 0x38490a20, 0x38490a20, },
311 { 0x1c6244, 0x00007bb6, 0x00007bb6, 0x00007bb6, 0x00007bb6, },
312 { 0x1c6248, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, 0x0fff3ffc, },
313 { 0x1c624c, 0x00000001, 0x00000001, 0x00000001, 0x00000001, },
314 { 0x1c6250, 0x0000a000, 0x0000a000, 0x0000a000, 0x0000a000, },
315 { 0x1c6254, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
316 { 0x1c6258, 0x0cc75380, 0x0cc75380, 0x0cc75380, 0x0cc75380, },
317 { 0x1c625c, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, 0x0f0f0f01, },
318 { 0x1c6260, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, 0xdfa91f01, },
319 { 0x1c6264, 0x00418a11, 0x00418a11, 0x00418a11, 0x00418a11, },
320 { 0x1c6268, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
321 { 0x1c626c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
322 { 0x1c6274, 0x0a1a9caa, 0x0a1a9caa, 0x0a1a7caa, 0x0a1a7caa, },
323 { 0x1c6278, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
324 { 0x1c627c, 0x051701ce, 0x051701ce, 0x051701ce, 0x051701ce, },
325 { 0x1c6300, 0x18010000, 0x18010000, 0x18010000, 0x18010000, },
326 { 0x1c6304, 0x30032602, 0x30032602, 0x2e032402, 0x2e032402, },
327 { 0x1c6308, 0x48073e06, 0x48073e06, 0x4a0a3c06, 0x4a0a3c06, },
328 { 0x1c630c, 0x560b4c0a, 0x560b4c0a, 0x621a540b, 0x621a540b, },
329 { 0x1c6310, 0x641a600f, 0x641a600f, 0x764f6c1b, 0x764f6c1b, },
330 { 0x1c6314, 0x7a4f6e1b, 0x7a4f6e1b, 0x845b7a5a, 0x845b7a5a, },
331 { 0x1c6318, 0x8c5b7e5a, 0x8c5b7e5a, 0x950f8ccf, 0x950f8ccf, },
332 { 0x1c631c, 0x9d0f96cf, 0x9d0f96cf, 0xa5cf9b4f, 0xa5cf9b4f, },
333 { 0x1c6320, 0xb51fa69f, 0xb51fa69f, 0xbddfaf1f, 0xbddfaf1f, },
334 { 0x1c6324, 0xcb3fbd07, 0xcb3fbcbf, 0xd1ffc93f, 0xd1ffc93f, },
335 { 0x1c6328, 0x0000d7bf, 0x0000d7bf, 0x00000000, 0x00000000, },
336 { 0x1c632c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
337 { 0x1c6330, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
338 { 0x1c6334, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
339 { 0x1c6338, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
340 { 0x1c633c, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
341 { 0x1c6340, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
342 { 0x1c6344, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
343 { 0x1c6348, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
344 { 0x1c634c, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
345 { 0x1c6350, 0x3fffffff, 0x3fffffff, 0x3fffffff, 0x3fffffff, },
346 { 0x1c6354, 0x0003ffff, 0x0003ffff, 0x0003ffff, 0x0003ffff, },
347 { 0x1c6358, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, 0x79a8aa1f, },
348 { 0x1c6388, 0x08000000, 0x08000000, 0x08000000, 0x08000000, },
349 { 0x1c638c, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
350 { 0x1c6390, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
351 { 0x1c6394, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
352 { 0x1c6398, 0x000001ce, 0x000001ce, 0x000001ce, 0x000001ce, },
353 { 0x1c639c, 0x00000007, 0x00000007, 0x00000007, 0x00000007, },
354 { 0x1c63a0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
355 { 0x1c63a4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
356 { 0x1c63a8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
357 { 0x1c63ac, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
358 { 0x1c63b0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
359 { 0x1c63b4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
360 { 0x1c63b8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
361 { 0x1c63bc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
362 { 0x1c63c0, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
363 { 0x1c63c4, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
364 { 0x1c63c8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
365 { 0x1c63cc, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
366 { 0x1c63d0, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
367 { 0x1c63d4, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, 0x3f3f3f3f, },
368 { 0x1c63d8, 0x00000000, 0x00000000, 0x00000000, 0x00000000, },
369 { 0x1c63dc, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, 0x1ce739ce, },
370 { 0x1c63e0, 0x000000c0, 0x000000c0, 0x000000c0, 0x000000c0, },
371 { 0x1c6848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, },
372 { 0x1c6920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, },
373 { 0x1c6960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
374 { 0x1c720c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
375 { 0x1c726c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
376 { 0x1c7848, 0x00180a65, 0x00180a65, 0x00180a68, 0x00180a68, },
377 { 0x1c7920, 0x0510001c, 0x0510001c, 0x0510001c, 0x0510001c, },
378 { 0x1c7960, 0x00009b40, 0x00009b40, 0x00009b40, 0x00009b40, },
379 { 0x1c820c, 0x012e8160, 0x012e8160, 0x012a8160, 0x012a8160, },
380 { 0x1c826c, 0x09249126, 0x09249126, 0x09249126, 0x09249126, },
381/* { 0x1c8864, 0x0001ce00, 0x0001ce00, 0x0001ce00, 0x0001ce00, }, */
382 { 0x1c8864, 0x0001c600, 0x0001c600, 0x0001c600, 0x0001c600, },
383 { 0x1c895c, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, 0x004b6a8e, },
384 { 0x1c8968, 0x000003ce, 0x000003ce, 0x000003ce, 0x000003ce, },
385 { 0x1c89bc, 0x00181400, 0x00181400, 0x00181400, 0x00181400, },
386 { 0x1c9270, 0x00820820, 0x00820820, 0x00820820, 0x00820820, },
387 { 0x1c935c, 0x066c420f, 0x066c420f, 0x066c420f, 0x066c420f, },
388 { 0x1c9360, 0x0f282207, 0x0f282207, 0x0f282207, 0x0f282207, },
389 { 0x1c9364, 0x17601685, 0x17601685, 0x17601685, 0x17601685, },
390 { 0x1c9368, 0x1f801104, 0x1f801104, 0x1f801104, 0x1f801104, },
391 { 0x1c936c, 0x37a00c03, 0x37a00c03, 0x37a00c03, 0x37a00c03, },
392 { 0x1c9370, 0x3fc40883, 0x3fc40883, 0x3fc40883, 0x3fc40883, },
393 { 0x1c9374, 0x57c00803, 0x57c00803, 0x57c00803, 0x57c00803, },
394 { 0x1c9378, 0x5fd80682, 0x5fd80682, 0x5fd80682, 0x5fd80682, },
395 { 0x1c937c, 0x7fe00482, 0x7fe00482, 0x7fe00482, 0x7fe00482, },
396 { 0x1c9380, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, 0x7f3c7bba, },
397 { 0x1c9384, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, 0xf3307ff0, }
398};
399
400/*
401 * look up a certain register in ar5416_phy_init[] and return the init. value
402 * for the band and bandwidth given. Return 0 if register address not found.
403 */
404static u32 carl9170_def_val(u32 reg, bool is_2ghz, bool is_40mhz)
405{
406 unsigned int i;
407 for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
408 if (ar5416_phy_init[i].reg != reg)
409 continue;
410
411 if (is_2ghz) {
412 if (is_40mhz)
413 return ar5416_phy_init[i]._2ghz_40;
414 else
415 return ar5416_phy_init[i]._2ghz_20;
416 } else {
417 if (is_40mhz)
418 return ar5416_phy_init[i]._5ghz_40;
419 else
420 return ar5416_phy_init[i]._5ghz_20;
421 }
422 }
423 return 0;
424}
425
426/*
427 * initialize some phy regs from eeprom values in modal_header[]
428 * acc. to band and bandwith
429 */
430static int carl9170_init_phy_from_eeprom(struct ar9170 *ar,
431 bool is_2ghz, bool is_40mhz)
432{
433 static const u8 xpd2pd[16] = {
434 0x2, 0x2, 0x2, 0x1, 0x2, 0x2, 0x6, 0x2,
435 0x2, 0x3, 0x7, 0x2, 0xb, 0x2, 0x2, 0x2
436 };
437 /* pointer to the modal_header acc. to band */
438 struct ar9170_eeprom_modal *m = &ar->eeprom.modal_header[is_2ghz];
439 u32 val;
440
441 carl9170_regwrite_begin(ar);
442
443 /* ant common control (index 0) */
444 carl9170_regwrite(AR9170_PHY_REG_SWITCH_COM,
445 le32_to_cpu(m->antCtrlCommon));
446
447 /* ant control chain 0 (index 1) */
448 carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_0,
449 le32_to_cpu(m->antCtrlChain[0]));
450
451 /* ant control chain 2 (index 2) */
452 carl9170_regwrite(AR9170_PHY_REG_SWITCH_CHAIN_2,
453 le32_to_cpu(m->antCtrlChain[1]));
454
455 /* SwSettle (index 3) */
456 if (!is_40mhz) {
457 val = carl9170_def_val(AR9170_PHY_REG_SETTLING,
458 is_2ghz, is_40mhz);
459 SET_VAL(AR9170_PHY_SETTLING_SWITCH, val, m->switchSettling);
460 carl9170_regwrite(AR9170_PHY_REG_SETTLING, val);
461 }
462
463 /* adcDesired, pdaDesired (index 4) */
464 val = carl9170_def_val(AR9170_PHY_REG_DESIRED_SZ, is_2ghz, is_40mhz);
465 SET_VAL(AR9170_PHY_DESIRED_SZ_PGA, val, m->pgaDesiredSize);
466 SET_VAL(AR9170_PHY_DESIRED_SZ_ADC, val, m->adcDesiredSize);
467 carl9170_regwrite(AR9170_PHY_REG_DESIRED_SZ, val);
468
469 /* TxEndToXpaOff, TxFrameToXpaOn (index 5) */
470 val = carl9170_def_val(AR9170_PHY_REG_RF_CTL4, is_2ghz, is_40mhz);
471 SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAB_OFF, val, m->txEndToXpaOff);
472 SET_VAL(AR9170_PHY_RF_CTL4_TX_END_XPAA_OFF, val, m->txEndToXpaOff);
473 SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAB_ON, val, m->txFrameToXpaOn);
474 SET_VAL(AR9170_PHY_RF_CTL4_FRAME_XPAA_ON, val, m->txFrameToXpaOn);
475 carl9170_regwrite(AR9170_PHY_REG_RF_CTL4, val);
476
477 /* TxEndToRxOn (index 6) */
478 val = carl9170_def_val(AR9170_PHY_REG_RF_CTL3, is_2ghz, is_40mhz);
479 SET_VAL(AR9170_PHY_RF_CTL3_TX_END_TO_A2_RX_ON, val, m->txEndToRxOn);
480 carl9170_regwrite(AR9170_PHY_REG_RF_CTL3, val);
481
482 /* thresh62 (index 7) */
483 val = carl9170_def_val(0x1c8864, is_2ghz, is_40mhz);
484 val = (val & ~0x7f000) | (m->thresh62 << 12);
485 carl9170_regwrite(0x1c8864, val);
486
487 /* tx/rx attenuation chain 0 (index 8) */
488 val = carl9170_def_val(AR9170_PHY_REG_RXGAIN, is_2ghz, is_40mhz);
489 SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[0]);
490 carl9170_regwrite(AR9170_PHY_REG_RXGAIN, val);
491
492 /* tx/rx attenuation chain 2 (index 9) */
493 val = carl9170_def_val(AR9170_PHY_REG_RXGAIN_CHAIN_2,
494 is_2ghz, is_40mhz);
495 SET_VAL(AR9170_PHY_RXGAIN_TXRX_ATTEN, val, m->txRxAttenCh[1]);
496 carl9170_regwrite(AR9170_PHY_REG_RXGAIN_CHAIN_2, val);
497
498 /* tx/rx margin chain 0 (index 10) */
499 val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ, is_2ghz, is_40mhz);
500 SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[0]);
501 /* bsw margin chain 0 for 5GHz only */
502 if (!is_2ghz)
503 SET_VAL(AR9170_PHY_GAIN_2GHZ_BSW_MARGIN, val, m->bswMargin[0]);
504 carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ, val);
505
506 /* tx/rx margin chain 2 (index 11) */
507 val = carl9170_def_val(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2,
508 is_2ghz, is_40mhz);
509 SET_VAL(AR9170_PHY_GAIN_2GHZ_RXTX_MARGIN, val, m->rxTxMarginCh[1]);
510 carl9170_regwrite(AR9170_PHY_REG_GAIN_2GHZ_CHAIN_2, val);
511
512 /* iqCall, iqCallq chain 0 (index 12) */
513 val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(0),
514 is_2ghz, is_40mhz);
515 SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[0]);
516 SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[0]);
517 carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(0), val);
518
519 /* iqCall, iqCallq chain 2 (index 13) */
520 val = carl9170_def_val(AR9170_PHY_REG_TIMING_CTRL4(2),
521 is_2ghz, is_40mhz);
522 SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF, val, m->iqCalICh[1]);
523 SET_VAL(AR9170_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF, val, m->iqCalQCh[1]);
524 carl9170_regwrite(AR9170_PHY_REG_TIMING_CTRL4(2), val);
525
526 /* xpd gain mask (index 14) */
527 val = carl9170_def_val(AR9170_PHY_REG_TPCRG1, is_2ghz, is_40mhz);
528 SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_1, val,
529 xpd2pd[m->xpdGain & 0xf] & 3);
530 SET_VAL(AR9170_PHY_TPCRG1_PD_GAIN_2, val,
531 xpd2pd[m->xpdGain & 0xf] >> 2);
532 carl9170_regwrite(AR9170_PHY_REG_TPCRG1, val);
533 carl9170_regwrite_finish();
534
535 return carl9170_regwrite_result();
536}
537
538static int carl9170_init_phy(struct ar9170 *ar, enum ieee80211_band band)
539{
540 int i, err;
541 u32 val;
542 bool is_2ghz = band == IEEE80211_BAND_2GHZ;
543 bool is_40mhz = conf_is_ht40(&ar->hw->conf);
544
545 carl9170_regwrite_begin(ar);
546
547 for (i = 0; i < ARRAY_SIZE(ar5416_phy_init); i++) {
548 if (is_40mhz) {
549 if (is_2ghz)
550 val = ar5416_phy_init[i]._2ghz_40;
551 else
552 val = ar5416_phy_init[i]._5ghz_40;
553 } else {
554 if (is_2ghz)
555 val = ar5416_phy_init[i]._2ghz_20;
556 else
557 val = ar5416_phy_init[i]._5ghz_20;
558 }
559
560 carl9170_regwrite(ar5416_phy_init[i].reg, val);
561 }
562
563 carl9170_regwrite_finish();
564 err = carl9170_regwrite_result();
565 if (err)
566 return err;
567
568 err = carl9170_init_phy_from_eeprom(ar, is_2ghz, is_40mhz);
569 if (err)
570 return err;
571
572 err = carl9170_init_power_cal(ar);
573 if (err)
574 return err;
575
576 /* XXX: remove magic! */
577 if (is_2ghz)
578 err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5163);
579 else
580 err = carl9170_write_reg(ar, AR9170_PWR_REG_PLL_ADDAC, 0x5143);
581
582 return err;
583}
584
585struct carl9170_rf_initvals {
586 u32 reg, _5ghz, _2ghz;
587};
588
589static struct carl9170_rf_initvals carl9170_rf_initval[] = {
590 /* bank 0 */
591 { 0x1c58b0, 0x1e5795e5, 0x1e5795e5},
592 { 0x1c58e0, 0x02008020, 0x02008020},
593 /* bank 1 */
594 { 0x1c58b0, 0x02108421, 0x02108421},
595 { 0x1c58ec, 0x00000008, 0x00000008},
596 /* bank 2 */
597 { 0x1c58b0, 0x0e73ff17, 0x0e73ff17},
598 { 0x1c58e0, 0x00000420, 0x00000420},
599 /* bank 3 */
600 { 0x1c58f0, 0x01400018, 0x01c00018},
601 /* bank 4 */
602 { 0x1c58b0, 0x000001a1, 0x000001a1},
603 { 0x1c58e8, 0x00000001, 0x00000001},
604 /* bank 5 */
605 { 0x1c58b0, 0x00000013, 0x00000013},
606 { 0x1c58e4, 0x00000002, 0x00000002},
607 /* bank 6 */
608 { 0x1c58b0, 0x00000000, 0x00000000},
609 { 0x1c58b0, 0x00000000, 0x00000000},
610 { 0x1c58b0, 0x00000000, 0x00000000},
611 { 0x1c58b0, 0x00000000, 0x00000000},
612 { 0x1c58b0, 0x00000000, 0x00000000},
613 { 0x1c58b0, 0x00004000, 0x00004000},
614 { 0x1c58b0, 0x00006c00, 0x00006c00},
615 { 0x1c58b0, 0x00002c00, 0x00002c00},
616 { 0x1c58b0, 0x00004800, 0x00004800},
617 { 0x1c58b0, 0x00004000, 0x00004000},
618 { 0x1c58b0, 0x00006000, 0x00006000},
619 { 0x1c58b0, 0x00001000, 0x00001000},
620 { 0x1c58b0, 0x00004000, 0x00004000},
621 { 0x1c58b0, 0x00007c00, 0x00007c00},
622 { 0x1c58b0, 0x00007c00, 0x00007c00},
623 { 0x1c58b0, 0x00007c00, 0x00007c00},
624 { 0x1c58b0, 0x00007c00, 0x00007c00},
625 { 0x1c58b0, 0x00007c00, 0x00007c00},
626 { 0x1c58b0, 0x00087c00, 0x00087c00},
627 { 0x1c58b0, 0x00007c00, 0x00007c00},
628 { 0x1c58b0, 0x00005400, 0x00005400},
629 { 0x1c58b0, 0x00000c00, 0x00000c00},
630 { 0x1c58b0, 0x00001800, 0x00001800},
631 { 0x1c58b0, 0x00007c00, 0x00007c00},
632 { 0x1c58b0, 0x00006c00, 0x00006c00},
633 { 0x1c58b0, 0x00006c00, 0x00006c00},
634 { 0x1c58b0, 0x00007c00, 0x00007c00},
635 { 0x1c58b0, 0x00002c00, 0x00002c00},
636 { 0x1c58b0, 0x00003c00, 0x00003c00},
637 { 0x1c58b0, 0x00003800, 0x00003800},
638 { 0x1c58b0, 0x00001c00, 0x00001c00},
639 { 0x1c58b0, 0x00000800, 0x00000800},
640 { 0x1c58b0, 0x00000408, 0x00000408},
641 { 0x1c58b0, 0x00004c15, 0x00004c15},
642 { 0x1c58b0, 0x00004188, 0x00004188},
643 { 0x1c58b0, 0x0000201e, 0x0000201e},
644 { 0x1c58b0, 0x00010408, 0x00010408},
645 { 0x1c58b0, 0x00000801, 0x00000801},
646 { 0x1c58b0, 0x00000c08, 0x00000c08},
647 { 0x1c58b0, 0x0000181e, 0x0000181e},
648 { 0x1c58b0, 0x00001016, 0x00001016},
649 { 0x1c58b0, 0x00002800, 0x00002800},
650 { 0x1c58b0, 0x00004010, 0x00004010},
651 { 0x1c58b0, 0x0000081c, 0x0000081c},
652 { 0x1c58b0, 0x00000115, 0x00000115},
653 { 0x1c58b0, 0x00000015, 0x00000015},
654 { 0x1c58b0, 0x00000066, 0x00000066},
655 { 0x1c58b0, 0x0000001c, 0x0000001c},
656 { 0x1c58b0, 0x00000000, 0x00000000},
657 { 0x1c58b0, 0x00000004, 0x00000004},
658 { 0x1c58b0, 0x00000015, 0x00000015},
659 { 0x1c58b0, 0x0000001f, 0x0000001f},
660 { 0x1c58e0, 0x00000000, 0x00000400},
661 /* bank 7 */
662 { 0x1c58b0, 0x000000a0, 0x000000a0},
663 { 0x1c58b0, 0x00000000, 0x00000000},
664 { 0x1c58b0, 0x00000040, 0x00000040},
665 { 0x1c58f0, 0x0000001c, 0x0000001c},
666};
667
668static int carl9170_init_rf_banks_0_7(struct ar9170 *ar, bool band5ghz)
669{
670 int err, i;
671
672 carl9170_regwrite_begin(ar);
673
674 for (i = 0; i < ARRAY_SIZE(carl9170_rf_initval); i++)
675 carl9170_regwrite(carl9170_rf_initval[i].reg,
676 band5ghz ? carl9170_rf_initval[i]._5ghz
677 : carl9170_rf_initval[i]._2ghz);
678
679 carl9170_regwrite_finish();
680 err = carl9170_regwrite_result();
681 if (err)
682 wiphy_err(ar->hw->wiphy, "rf init failed\n");
683
684 return err;
685}
686
687struct carl9170_phy_freq_params {
688 u8 coeff_exp;
689 u16 coeff_man;
690 u8 coeff_exp_shgi;
691 u16 coeff_man_shgi;
692};
693
694enum carl9170_bw {
695 CARL9170_BW_20,
696 CARL9170_BW_40_BELOW,
697 CARL9170_BW_40_ABOVE,
698
699 __CARL9170_NUM_BW,
700};
701
702struct carl9170_phy_freq_entry {
703 u16 freq;
704 struct carl9170_phy_freq_params params[__CARL9170_NUM_BW];
705};
706
707/* NB: must be in sync with channel tables in main! */
708static const struct carl9170_phy_freq_entry carl9170_phy_freq_params[] = {
709/*
710 * freq,
711 * 20MHz,
712 * 40MHz (below),
713 * 40Mhz (above),
714 */
715 { 2412, {
716 { 3, 21737, 3, 19563, },
717 { 3, 21827, 3, 19644, },
718 { 3, 21647, 3, 19482, },
719 } },
720 { 2417, {
721 { 3, 21692, 3, 19523, },
722 { 3, 21782, 3, 19604, },
723 { 3, 21602, 3, 19442, },
724 } },
725 { 2422, {
726 { 3, 21647, 3, 19482, },
727 { 3, 21737, 3, 19563, },
728 { 3, 21558, 3, 19402, },
729 } },
730 { 2427, {
731 { 3, 21602, 3, 19442, },
732 { 3, 21692, 3, 19523, },
733 { 3, 21514, 3, 19362, },
734 } },
735 { 2432, {
736 { 3, 21558, 3, 19402, },
737 { 3, 21647, 3, 19482, },
738 { 3, 21470, 3, 19323, },
739 } },
740 { 2437, {
741 { 3, 21514, 3, 19362, },
742 { 3, 21602, 3, 19442, },
743 { 3, 21426, 3, 19283, },
744 } },
745 { 2442, {
746 { 3, 21470, 3, 19323, },
747 { 3, 21558, 3, 19402, },
748 { 3, 21382, 3, 19244, },
749 } },
750 { 2447, {
751 { 3, 21426, 3, 19283, },
752 { 3, 21514, 3, 19362, },
753 { 3, 21339, 3, 19205, },
754 } },
755 { 2452, {
756 { 3, 21382, 3, 19244, },
757 { 3, 21470, 3, 19323, },
758 { 3, 21295, 3, 19166, },
759 } },
760 { 2457, {
761 { 3, 21339, 3, 19205, },
762 { 3, 21426, 3, 19283, },
763 { 3, 21252, 3, 19127, },
764 } },
765 { 2462, {
766 { 3, 21295, 3, 19166, },
767 { 3, 21382, 3, 19244, },
768 { 3, 21209, 3, 19088, },
769 } },
770 { 2467, {
771 { 3, 21252, 3, 19127, },
772 { 3, 21339, 3, 19205, },
773 { 3, 21166, 3, 19050, },
774 } },
775 { 2472, {
776 { 3, 21209, 3, 19088, },
777 { 3, 21295, 3, 19166, },
778 { 3, 21124, 3, 19011, },
779 } },
780 { 2484, {
781 { 3, 21107, 3, 18996, },
782 { 3, 21192, 3, 19073, },
783 { 3, 21022, 3, 18920, },
784 } },
785 { 4920, {
786 { 4, 21313, 4, 19181, },
787 { 4, 21356, 4, 19220, },
788 { 4, 21269, 4, 19142, },
789 } },
790 { 4940, {
791 { 4, 21226, 4, 19104, },
792 { 4, 21269, 4, 19142, },
793 { 4, 21183, 4, 19065, },
794 } },
795 { 4960, {
796 { 4, 21141, 4, 19027, },
797 { 4, 21183, 4, 19065, },
798 { 4, 21098, 4, 18988, },
799 } },
800 { 4980, {
801 { 4, 21056, 4, 18950, },
802 { 4, 21098, 4, 18988, },
803 { 4, 21014, 4, 18912, },
804 } },
805 { 5040, {
806 { 4, 20805, 4, 18725, },
807 { 4, 20846, 4, 18762, },
808 { 4, 20764, 4, 18687, },
809 } },
810 { 5060, {
811 { 4, 20723, 4, 18651, },
812 { 4, 20764, 4, 18687, },
813 { 4, 20682, 4, 18614, },
814 } },
815 { 5080, {
816 { 4, 20641, 4, 18577, },
817 { 4, 20682, 4, 18614, },
818 { 4, 20601, 4, 18541, },
819 } },
820 { 5180, {
821 { 4, 20243, 4, 18219, },
822 { 4, 20282, 4, 18254, },
823 { 4, 20204, 4, 18183, },
824 } },
825 { 5200, {
826 { 4, 20165, 4, 18148, },
827 { 4, 20204, 4, 18183, },
828 { 4, 20126, 4, 18114, },
829 } },
830 { 5220, {
831 { 4, 20088, 4, 18079, },
832 { 4, 20126, 4, 18114, },
833 { 4, 20049, 4, 18044, },
834 } },
835 { 5240, {
836 { 4, 20011, 4, 18010, },
837 { 4, 20049, 4, 18044, },
838 { 4, 19973, 4, 17976, },
839 } },
840 { 5260, {
841 { 4, 19935, 4, 17941, },
842 { 4, 19973, 4, 17976, },
843 { 4, 19897, 4, 17907, },
844 } },
845 { 5280, {
846 { 4, 19859, 4, 17873, },
847 { 4, 19897, 4, 17907, },
848 { 4, 19822, 4, 17840, },
849 } },
850 { 5300, {
851 { 4, 19784, 4, 17806, },
852 { 4, 19822, 4, 17840, },
853 { 4, 19747, 4, 17772, },
854 } },
855 { 5320, {
856 { 4, 19710, 4, 17739, },
857 { 4, 19747, 4, 17772, },
858 { 4, 19673, 4, 17706, },
859 } },
860 { 5500, {
861 { 4, 19065, 4, 17159, },
862 { 4, 19100, 4, 17190, },
863 { 4, 19030, 4, 17127, },
864 } },
865 { 5520, {
866 { 4, 18996, 4, 17096, },
867 { 4, 19030, 4, 17127, },
868 { 4, 18962, 4, 17065, },
869 } },
870 { 5540, {
871 { 4, 18927, 4, 17035, },
872 { 4, 18962, 4, 17065, },
873 { 4, 18893, 4, 17004, },
874 } },
875 { 5560, {
876 { 4, 18859, 4, 16973, },
877 { 4, 18893, 4, 17004, },
878 { 4, 18825, 4, 16943, },
879 } },
880 { 5580, {
881 { 4, 18792, 4, 16913, },
882 { 4, 18825, 4, 16943, },
883 { 4, 18758, 4, 16882, },
884 } },
885 { 5600, {
886 { 4, 18725, 4, 16852, },
887 { 4, 18758, 4, 16882, },
888 { 4, 18691, 4, 16822, },
889 } },
890 { 5620, {
891 { 4, 18658, 4, 16792, },
892 { 4, 18691, 4, 16822, },
893 { 4, 18625, 4, 16762, },
894 } },
895 { 5640, {
896 { 4, 18592, 4, 16733, },
897 { 4, 18625, 4, 16762, },
898 { 4, 18559, 4, 16703, },
899 } },
900 { 5660, {
901 { 4, 18526, 4, 16673, },
902 { 4, 18559, 4, 16703, },
903 { 4, 18493, 4, 16644, },
904 } },
905 { 5680, {
906 { 4, 18461, 4, 16615, },
907 { 4, 18493, 4, 16644, },
908 { 4, 18428, 4, 16586, },
909 } },
910 { 5700, {
911 { 4, 18396, 4, 16556, },
912 { 4, 18428, 4, 16586, },
913 { 4, 18364, 4, 16527, },
914 } },
915 { 5745, {
916 { 4, 18252, 4, 16427, },
917 { 4, 18284, 4, 16455, },
918 { 4, 18220, 4, 16398, },
919 } },
920 { 5765, {
921 { 4, 18189, 5, 32740, },
922 { 4, 18220, 4, 16398, },
923 { 4, 18157, 5, 32683, },
924 } },
925 { 5785, {
926 { 4, 18126, 5, 32626, },
927 { 4, 18157, 5, 32683, },
928 { 4, 18094, 5, 32570, },
929 } },
930 { 5805, {
931 { 4, 18063, 5, 32514, },
932 { 4, 18094, 5, 32570, },
933 { 4, 18032, 5, 32458, },
934 } },
935 { 5825, {
936 { 4, 18001, 5, 32402, },
937 { 4, 18032, 5, 32458, },
938 { 4, 17970, 5, 32347, },
939 } },
940 { 5170, {
941 { 4, 20282, 4, 18254, },
942 { 4, 20321, 4, 18289, },
943 { 4, 20243, 4, 18219, },
944 } },
945 { 5190, {
946 { 4, 20204, 4, 18183, },
947 { 4, 20243, 4, 18219, },
948 { 4, 20165, 4, 18148, },
949 } },
950 { 5210, {
951 { 4, 20126, 4, 18114, },
952 { 4, 20165, 4, 18148, },
953 { 4, 20088, 4, 18079, },
954 } },
955 { 5230, {
956 { 4, 20049, 4, 18044, },
957 { 4, 20088, 4, 18079, },
958 { 4, 20011, 4, 18010, },
959 } },
960};
961
962static int carl9170_init_rf_bank4_pwr(struct ar9170 *ar, bool band5ghz,
963 u32 freq, enum carl9170_bw bw)
964{
965 int err;
966 u32 d0, d1, td0, td1, fd0, fd1;
967 u8 chansel;
968 u8 refsel0 = 1, refsel1 = 0;
969 u8 lf_synth = 0;
970
971 switch (bw) {
972 case CARL9170_BW_40_ABOVE:
973 freq += 10;
974 break;
975 case CARL9170_BW_40_BELOW:
976 freq -= 10;
977 break;
978 case CARL9170_BW_20:
979 break;
980 default:
981 BUG();
982 return -ENOSYS;
983 }
984
985 if (band5ghz) {
986 if (freq % 10) {
987 chansel = (freq - 4800) / 5;
988 } else {
989 chansel = ((freq - 4800) / 10) * 2;
990 refsel0 = 0;
991 refsel1 = 1;
992 }
993 chansel = byte_rev_table[chansel];
994 } else {
995 if (freq == 2484) {
996 chansel = 10 + (freq - 2274) / 5;
997 lf_synth = 1;
998 } else
999 chansel = 16 + (freq - 2272) / 5;
1000 chansel *= 4;
1001 chansel = byte_rev_table[chansel];
1002 }
1003
1004 d1 = chansel;
1005 d0 = 0x21 |
1006 refsel0 << 3 |
1007 refsel1 << 2 |
1008 lf_synth << 1;
1009 td0 = d0 & 0x1f;
1010 td1 = d1 & 0x1f;
1011 fd0 = td1 << 5 | td0;
1012
1013 td0 = (d0 >> 5) & 0x7;
1014 td1 = (d1 >> 5) & 0x7;
1015 fd1 = td1 << 5 | td0;
1016
1017 carl9170_regwrite_begin(ar);
1018
1019 carl9170_regwrite(0x1c58b0, fd0);
1020 carl9170_regwrite(0x1c58e8, fd1);
1021
1022 carl9170_regwrite_finish();
1023 err = carl9170_regwrite_result();
1024 if (err)
1025 return err;
1026
1027 msleep(20);
1028
1029 return 0;
1030}
1031
1032static const struct carl9170_phy_freq_params *
1033carl9170_get_hw_dyn_params(struct ieee80211_channel *channel,
1034 enum carl9170_bw bw)
1035{
1036 unsigned int chanidx = 0;
1037 u16 freq = 2412;
1038
1039 if (channel) {
1040 chanidx = channel->hw_value;
1041 freq = channel->center_freq;
1042 }
1043
1044 BUG_ON(chanidx >= ARRAY_SIZE(carl9170_phy_freq_params));
1045
1046 BUILD_BUG_ON(__CARL9170_NUM_BW != 3);
1047
1048 WARN_ON(carl9170_phy_freq_params[chanidx].freq != freq);
1049
1050 return &carl9170_phy_freq_params[chanidx].params[bw];
1051}
1052
1053static int carl9170_find_freq_idx(int nfreqs, u8 *freqs, u8 f)
1054{
1055 int idx = nfreqs - 2;
1056
1057 while (idx >= 0) {
1058 if (f >= freqs[idx])
1059 return idx;
1060 idx--;
1061 }
1062
1063 return 0;
1064}
1065
1066static s32 carl9170_interpolate_s32(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
1067{
1068 /* nothing to interpolate, it's horizontal */
1069 if (y2 == y1)
1070 return y1;
1071
1072 /* check if we hit one of the edges */
1073 if (x == x1)
1074 return y1;
1075 if (x == x2)
1076 return y2;
1077
1078 /* x1 == x2 is bad, hopefully == x */
1079 if (x2 == x1)
1080 return y1;
1081
1082 return y1 + (((y2 - y1) * (x - x1)) / (x2 - x1));
1083}
1084
1085static u8 carl9170_interpolate_u8(u8 x, u8 x1, u8 y1, u8 x2, u8 y2)
1086{
1087#define SHIFT 8
1088 s32 y;
1089
1090 y = carl9170_interpolate_s32(x << SHIFT, x1 << SHIFT,
1091 y1 << SHIFT, x2 << SHIFT, y2 << SHIFT);
1092
1093 /*
1094 * XXX: unwrap this expression
1095 * Isn't it just DIV_ROUND_UP(y, 1<<SHIFT)?
1096 * Can we rely on the compiler to optimise away the div?
1097 */
1098 return (y >> SHIFT) + ((y & (1<<(SHIFT-1))) >> (SHIFT - 1));
1099#undef SHIFT
1100}
1101
1102static u8 carl9170_interpolate_val(u8 x, u8 *x_array, u8 *y_array)
1103{
1104 int i;
1105
1106 for (i = 0; i < 3; i++) {
1107 if (x <= x_array[i + 1])
1108 break;
1109 }
1110
1111 return carl9170_interpolate_u8(x, x_array[i], y_array[i],
1112 x_array[i + 1], y_array[i + 1]);
1113}
1114
1115static int carl9170_set_freq_cal_data(struct ar9170 *ar,
1116 struct ieee80211_channel *channel)
1117{
1118 u8 *cal_freq_pier;
1119 u8 vpds[2][AR5416_PD_GAIN_ICEPTS];
1120 u8 pwrs[2][AR5416_PD_GAIN_ICEPTS];
1121 int chain, idx, i;
1122 u32 phy_data = 0;
1123 u8 f, tmp;
1124
1125 switch (channel->band) {
1126 case IEEE80211_BAND_2GHZ:
1127 f = channel->center_freq - 2300;
1128 cal_freq_pier = ar->eeprom.cal_freq_pier_2G;
1129 i = AR5416_NUM_2G_CAL_PIERS - 1;
1130 break;
1131
1132 case IEEE80211_BAND_5GHZ:
1133 f = (channel->center_freq - 4800) / 5;
1134 cal_freq_pier = ar->eeprom.cal_freq_pier_5G;
1135 i = AR5416_NUM_5G_CAL_PIERS - 1;
1136 break;
1137
1138 default:
1139 return -EINVAL;
1140 break;
1141 }
1142
1143 for (; i >= 0; i--) {
1144 if (cal_freq_pier[i] != 0xff)
1145 break;
1146 }
1147 if (i < 0)
1148 return -EINVAL;
1149
1150 idx = carl9170_find_freq_idx(i, cal_freq_pier, f);
1151
1152 carl9170_regwrite_begin(ar);
1153
1154 for (chain = 0; chain < AR5416_MAX_CHAINS; chain++) {
1155 for (i = 0; i < AR5416_PD_GAIN_ICEPTS; i++) {
1156 struct ar9170_calibration_data_per_freq *cal_pier_data;
1157 int j;
1158
1159 switch (channel->band) {
1160 case IEEE80211_BAND_2GHZ:
1161 cal_pier_data = &ar->eeprom.
1162 cal_pier_data_2G[chain][idx];
1163 break;
1164
1165 case IEEE80211_BAND_5GHZ:
1166 cal_pier_data = &ar->eeprom.
1167 cal_pier_data_5G[chain][idx];
1168 break;
1169
1170 default:
1171 return -EINVAL;
1172 }
1173
1174 for (j = 0; j < 2; j++) {
1175 vpds[j][i] = carl9170_interpolate_u8(f,
1176 cal_freq_pier[idx],
1177 cal_pier_data->vpd_pdg[j][i],
1178 cal_freq_pier[idx + 1],
1179 cal_pier_data[1].vpd_pdg[j][i]);
1180
1181 pwrs[j][i] = carl9170_interpolate_u8(f,
1182 cal_freq_pier[idx],
1183 cal_pier_data->pwr_pdg[j][i],
1184 cal_freq_pier[idx + 1],
1185 cal_pier_data[1].pwr_pdg[j][i]) / 2;
1186 }
1187 }
1188
1189 for (i = 0; i < 76; i++) {
1190 if (i < 25) {
1191 tmp = carl9170_interpolate_val(i, &pwrs[0][0],
1192 &vpds[0][0]);
1193 } else {
1194 tmp = carl9170_interpolate_val(i - 12,
1195 &pwrs[1][0],
1196 &vpds[1][0]);
1197 }
1198
1199 phy_data |= tmp << ((i & 3) << 3);
1200 if ((i & 3) == 3) {
1201 carl9170_regwrite(0x1c6280 + chain * 0x1000 +
1202 (i & ~3), phy_data);
1203 phy_data = 0;
1204 }
1205 }
1206
1207 for (i = 19; i < 32; i++)
1208 carl9170_regwrite(0x1c6280 + chain * 0x1000 + (i << 2),
1209 0x0);
1210 }
1211
1212 carl9170_regwrite_finish();
1213 return carl9170_regwrite_result();
1214}
1215
1216static u8 carl9170_get_max_edge_power(struct ar9170 *ar,
1217 u32 freq, struct ar9170_calctl_edges edges[])
1218{
1219 int i;
1220 u8 rc = AR5416_MAX_RATE_POWER;
1221 u8 f;
1222 if (freq < 3000)
1223 f = freq - 2300;
1224 else
1225 f = (freq - 4800) / 5;
1226
1227 for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) {
1228 if (edges[i].channel == 0xff)
1229 break;
1230 if (f == edges[i].channel) {
1231 /* exact freq match */
1232 rc = edges[i].power_flags & ~AR9170_CALCTL_EDGE_FLAGS;
1233 break;
1234 }
1235 if (i > 0 && f < edges[i].channel) {
1236 if (f > edges[i - 1].channel &&
1237 edges[i - 1].power_flags &
1238 AR9170_CALCTL_EDGE_FLAGS) {
1239 /* lower channel has the inband flag set */
1240 rc = edges[i - 1].power_flags &
1241 ~AR9170_CALCTL_EDGE_FLAGS;
1242 }
1243 break;
1244 }
1245 }
1246
1247 if (i == AR5416_NUM_BAND_EDGES) {
1248 if (f > edges[i - 1].channel &&
1249 edges[i - 1].power_flags & AR9170_CALCTL_EDGE_FLAGS) {
1250 /* lower channel has the inband flag set */
1251 rc = edges[i - 1].power_flags &
1252 ~AR9170_CALCTL_EDGE_FLAGS;
1253 }
1254 }
1255 return rc;
1256}
1257
1258static u8 carl9170_get_heavy_clip(struct ar9170 *ar, u32 freq,
1259 enum carl9170_bw bw, struct ar9170_calctl_edges edges[])
1260{
1261 u8 f;
1262 int i;
1263 u8 rc = 0;
1264
1265 if (freq < 3000)
1266 f = freq - 2300;
1267 else
1268 f = (freq - 4800) / 5;
1269
1270 if (bw == CARL9170_BW_40_BELOW || bw == CARL9170_BW_40_ABOVE)
1271 rc |= 0xf0;
1272
1273 for (i = 0; i < AR5416_NUM_BAND_EDGES; i++) {
1274 if (edges[i].channel == 0xff)
1275 break;
1276 if (f == edges[i].channel) {
1277 if (!(edges[i].power_flags & AR9170_CALCTL_EDGE_FLAGS))
1278 rc |= 0x0f;
1279 break;
1280 }
1281 }
1282
1283 return rc;
1284}
1285
1286/*
1287 * calculate the conformance test limits and the heavy clip parameter
1288 * and apply them to ar->power* (derived from otus hal/hpmain.c, line 3706)
1289 */
1290static void carl9170_calc_ctl(struct ar9170 *ar, u32 freq, enum carl9170_bw bw)
1291{
1292 u8 ctl_grp; /* CTL group */
1293 u8 ctl_idx; /* CTL index */
1294 int i, j;
1295 struct ctl_modes {
1296 u8 ctl_mode;
1297 u8 max_power;
1298 u8 *pwr_cal_data;
1299 int pwr_cal_len;
1300 } *modes;
1301
1302 /*
1303 * order is relevant in the mode_list_*: we fall back to the
1304 * lower indices if any mode is missed in the EEPROM.
1305 */
1306 struct ctl_modes mode_list_2ghz[] = {
1307 { CTL_11B, 0, ar->power_2G_cck, 4 },
1308 { CTL_11G, 0, ar->power_2G_ofdm, 4 },
1309 { CTL_2GHT20, 0, ar->power_2G_ht20, 8 },
1310 { CTL_2GHT40, 0, ar->power_2G_ht40, 8 },
1311 };
1312 struct ctl_modes mode_list_5ghz[] = {
1313 { CTL_11A, 0, ar->power_5G_leg, 4 },
1314 { CTL_5GHT20, 0, ar->power_5G_ht20, 8 },
1315 { CTL_5GHT40, 0, ar->power_5G_ht40, 8 },
1316 };
1317 int nr_modes;
1318
1319#define EDGES(c, n) (ar->eeprom.ctl_data[c].control_edges[n])
1320
1321 ar->heavy_clip = 0;
1322
1323 /*
1324 * TODO: investigate the differences between OTUS'
1325 * hpreg.c::zfHpGetRegulatoryDomain() and
1326 * ath/regd.c::ath_regd_get_band_ctl() -
1327 * e.g. for FCC3_WORLD the OTUS procedure
1328 * always returns CTL_FCC, while the one in ath/ delivers
1329 * CTL_ETSI for 2GHz and CTL_FCC for 5GHz.
1330 */
1331 ctl_grp = ath_regd_get_band_ctl(&ar->common.regulatory,
1332 ar->hw->conf.channel->band);
1333
1334 /* ctl group not found - either invalid band (NO_CTL) or ww roaming */
1335 if (ctl_grp == NO_CTL || ctl_grp == SD_NO_CTL)
1336 ctl_grp = CTL_FCC;
1337
1338 if (ctl_grp != CTL_FCC)
1339 /* skip CTL and heavy clip for CTL_MKK and CTL_ETSI */
1340 return;
1341
1342 if (ar->hw->conf.channel->band == IEEE80211_BAND_2GHZ) {
1343 modes = mode_list_2ghz;
1344 nr_modes = ARRAY_SIZE(mode_list_2ghz);
1345 } else {
1346 modes = mode_list_5ghz;
1347 nr_modes = ARRAY_SIZE(mode_list_5ghz);
1348 }
1349
1350 for (i = 0; i < nr_modes; i++) {
1351 u8 c = ctl_grp | modes[i].ctl_mode;
1352 for (ctl_idx = 0; ctl_idx < AR5416_NUM_CTLS; ctl_idx++)
1353 if (c == ar->eeprom.ctl_index[ctl_idx])
1354 break;
1355 if (ctl_idx < AR5416_NUM_CTLS) {
1356 int f_off = 0;
1357
1358 /*
1359 * determine heavy clip parameter
1360 * from the 11G edges array
1361 */
1362 if (modes[i].ctl_mode == CTL_11G) {
1363 ar->heavy_clip =
1364 carl9170_get_heavy_clip(ar,
1365 freq, bw, EDGES(ctl_idx, 1));
1366 }
1367
1368 /* adjust freq for 40MHz */
1369 if (modes[i].ctl_mode == CTL_2GHT40 ||
1370 modes[i].ctl_mode == CTL_5GHT40) {
1371 if (bw == CARL9170_BW_40_BELOW)
1372 f_off = -10;
1373 else
1374 f_off = 10;
1375 }
1376
1377 modes[i].max_power =
1378 carl9170_get_max_edge_power(ar,
1379 freq+f_off, EDGES(ctl_idx, 1));
1380
1381 /*
1382 * TODO: check if the regulatory max. power is
1383 * controlled by cfg80211 for DFS.
1384 * (hpmain applies it to max_power itself for DFS freq)
1385 */
1386
1387 } else {
1388 /*
1389 * Workaround in otus driver, hpmain.c, line 3906:
1390 * if no data for 5GHT20 are found, take the
1391 * legacy 5G value. We extend this here to fallback
1392 * from any other HT* or 11G, too.
1393 */
1394 int k = i;
1395
1396 modes[i].max_power = AR5416_MAX_RATE_POWER;
1397 while (k-- > 0) {
1398 if (modes[k].max_power !=
1399 AR5416_MAX_RATE_POWER) {
1400 modes[i].max_power = modes[k].max_power;
1401 break;
1402 }
1403 }
1404 }
1405
1406 /* apply max power to pwr_cal_data (ar->power_*) */
1407 for (j = 0; j < modes[i].pwr_cal_len; j++) {
1408 modes[i].pwr_cal_data[j] = min(modes[i].pwr_cal_data[j],
1409 modes[i].max_power);
1410 }
1411 }
1412
1413 if (ar->heavy_clip & 0xf0) {
1414 ar->power_2G_ht40[0]--;
1415 ar->power_2G_ht40[1]--;
1416 ar->power_2G_ht40[2]--;
1417 }
1418 if (ar->heavy_clip & 0xf) {
1419 ar->power_2G_ht20[0]++;
1420 ar->power_2G_ht20[1]++;
1421 ar->power_2G_ht20[2]++;
1422 }
1423
1424#undef EDGES
1425}
1426
1427static int carl9170_set_power_cal(struct ar9170 *ar, u32 freq,
1428 enum carl9170_bw bw)
1429{
1430 struct ar9170_calibration_target_power_legacy *ctpl;
1431 struct ar9170_calibration_target_power_ht *ctph;
1432 u8 *ctpres;
1433 int ntargets;
1434 int idx, i, n;
1435 u8 ackpower, ackchains, f;
1436 u8 pwr_freqs[AR5416_MAX_NUM_TGT_PWRS];
1437
1438 if (freq < 3000)
1439 f = freq - 2300;
1440 else
1441 f = (freq - 4800)/5;
1442
1443 /*
1444 * cycle through the various modes
1445 *
1446 * legacy modes first: 5G, 2G CCK, 2G OFDM
1447 */
1448 for (i = 0; i < 3; i++) {
1449 switch (i) {
1450 case 0: /* 5 GHz legacy */
1451 ctpl = &ar->eeprom.cal_tgt_pwr_5G[0];
1452 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1453 ctpres = ar->power_5G_leg;
1454 break;
1455 case 1: /* 2.4 GHz CCK */
1456 ctpl = &ar->eeprom.cal_tgt_pwr_2G_cck[0];
1457 ntargets = AR5416_NUM_2G_CCK_TARGET_PWRS;
1458 ctpres = ar->power_2G_cck;
1459 break;
1460 case 2: /* 2.4 GHz OFDM */
1461 ctpl = &ar->eeprom.cal_tgt_pwr_2G_ofdm[0];
1462 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1463 ctpres = ar->power_2G_ofdm;
1464 break;
1465 default:
1466 BUG();
1467 }
1468
1469 for (n = 0; n < ntargets; n++) {
1470 if (ctpl[n].freq == 0xff)
1471 break;
1472 pwr_freqs[n] = ctpl[n].freq;
1473 }
1474 ntargets = n;
1475 idx = carl9170_find_freq_idx(ntargets, pwr_freqs, f);
1476 for (n = 0; n < 4; n++)
1477 ctpres[n] = carl9170_interpolate_u8(f,
1478 ctpl[idx + 0].freq, ctpl[idx + 0].power[n],
1479 ctpl[idx + 1].freq, ctpl[idx + 1].power[n]);
1480 }
1481
1482 /* HT modes now: 5G HT20, 5G HT40, 2G CCK, 2G OFDM, 2G HT20, 2G HT40 */
1483 for (i = 0; i < 4; i++) {
1484 switch (i) {
1485 case 0: /* 5 GHz HT 20 */
1486 ctph = &ar->eeprom.cal_tgt_pwr_5G_ht20[0];
1487 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1488 ctpres = ar->power_5G_ht20;
1489 break;
1490 case 1: /* 5 GHz HT 40 */
1491 ctph = &ar->eeprom.cal_tgt_pwr_5G_ht40[0];
1492 ntargets = AR5416_NUM_5G_TARGET_PWRS;
1493 ctpres = ar->power_5G_ht40;
1494 break;
1495 case 2: /* 2.4 GHz HT 20 */
1496 ctph = &ar->eeprom.cal_tgt_pwr_2G_ht20[0];
1497 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1498 ctpres = ar->power_2G_ht20;
1499 break;
1500 case 3: /* 2.4 GHz HT 40 */
1501 ctph = &ar->eeprom.cal_tgt_pwr_2G_ht40[0];
1502 ntargets = AR5416_NUM_2G_OFDM_TARGET_PWRS;
1503 ctpres = ar->power_2G_ht40;
1504 break;
1505 default:
1506 BUG();
1507 }
1508
1509 for (n = 0; n < ntargets; n++) {
1510 if (ctph[n].freq == 0xff)
1511 break;
1512 pwr_freqs[n] = ctph[n].freq;
1513 }
1514 ntargets = n;
1515 idx = carl9170_find_freq_idx(ntargets, pwr_freqs, f);
1516 for (n = 0; n < 8; n++)
1517 ctpres[n] = carl9170_interpolate_u8(f,
1518 ctph[idx + 0].freq, ctph[idx + 0].power[n],
1519 ctph[idx + 1].freq, ctph[idx + 1].power[n]);
1520 }
1521
1522 /* calc. conformance test limits and apply to ar->power*[] */
1523 carl9170_calc_ctl(ar, freq, bw);
1524
1525 /* set ACK/CTS TX power */
1526 carl9170_regwrite_begin(ar);
1527
1528 if (ar->eeprom.tx_mask != 1)
1529 ackchains = AR9170_TX_PHY_TXCHAIN_2;
1530 else
1531 ackchains = AR9170_TX_PHY_TXCHAIN_1;
1532
1533 if (freq < 3000)
1534 ackpower = ar->power_2G_ofdm[0] & 0x3f;
1535 else
1536 ackpower = ar->power_5G_leg[0] & 0x3f;
1537
1538 carl9170_regwrite(AR9170_MAC_REG_ACK_TPC,
1539 0x3c1e | ackpower << 20 | ackchains << 26);
1540 carl9170_regwrite(AR9170_MAC_REG_RTS_CTS_TPC,
1541 ackpower << 5 | ackchains << 11 |
1542 ackpower << 21 | ackchains << 27);
1543
1544 carl9170_regwrite(AR9170_MAC_REG_CFEND_QOSNULL_TPC,
1545 ackpower << 5 | ackchains << 11 |
1546 ackpower << 21 | ackchains << 27);
1547
1548 carl9170_regwrite_finish();
1549 return carl9170_regwrite_result();
1550}
1551
1552/* TODO: replace this with sign_extend32(noise, 8) */
1553static int carl9170_calc_noise_dbm(u32 raw_noise)
1554{
1555 if (raw_noise & 0x100)
1556 return ~((raw_noise & 0x0ff) >> 1);
1557 else
1558 return (raw_noise & 0xff) >> 1;
1559}
1560
1561int carl9170_get_noisefloor(struct ar9170 *ar)
1562{
1563 static const u32 phy_regs[] = {
1564 AR9170_PHY_REG_CCA, AR9170_PHY_REG_CH1_CCA,
1565 AR9170_PHY_REG_CH2_CCA, AR9170_PHY_REG_EXT_CCA,
1566 AR9170_PHY_REG_CH1_EXT_CCA, AR9170_PHY_REG_CH2_EXT_CCA };
1567 u32 phy_res[ARRAY_SIZE(phy_regs)];
1568 int err, i;
1569
1570 BUILD_BUG_ON(ARRAY_SIZE(phy_regs) != ARRAY_SIZE(ar->noise));
1571
1572 err = carl9170_read_mreg(ar, ARRAY_SIZE(phy_regs), phy_regs, phy_res);
1573 if (err)
1574 return err;
1575
1576 for (i = 0; i < 3; i++) {
1577 ar->noise[i] = carl9170_calc_noise_dbm(
1578 (phy_res[i] >> 19) & 0x1ff);
1579
1580 ar->noise[i + 3] = carl9170_calc_noise_dbm(
1581 (phy_res[i + 3] >> 23) & 0x1ff);
1582 }
1583
1584 return 0;
1585}
1586
1587static enum carl9170_bw nl80211_to_carl(enum nl80211_channel_type type)
1588{
1589 switch (type) {
1590 case NL80211_CHAN_NO_HT:
1591 case NL80211_CHAN_HT20:
1592 return CARL9170_BW_20;
1593 case NL80211_CHAN_HT40MINUS:
1594 return CARL9170_BW_40_BELOW;
1595 case NL80211_CHAN_HT40PLUS:
1596 return CARL9170_BW_40_ABOVE;
1597 default:
1598 BUG();
1599 }
1600}
1601
1602int carl9170_set_channel(struct ar9170 *ar, struct ieee80211_channel *channel,
1603 enum nl80211_channel_type _bw,
1604 enum carl9170_rf_init_mode rfi)
1605{
1606 const struct carl9170_phy_freq_params *freqpar;
1607 struct carl9170_rf_init_result rf_res;
1608 struct carl9170_rf_init rf;
1609 u32 cmd, tmp, offs = 0;
1610 int err;
1611 enum carl9170_bw bw;
1612 bool warm_reset;
1613 struct ieee80211_channel *old_channel = NULL;
1614
1615 bw = nl80211_to_carl(_bw);
1616
1617 /* may be NULL at first setup */
1618 if (ar->channel) {
1619 old_channel = ar->channel;
1620 warm_reset = (old_channel->band != channel->band) ||
1621 (old_channel->center_freq ==
1622 channel->center_freq);
1623
1624 ar->channel = NULL;
1625 } else {
1626 warm_reset = true;
1627 }
1628
1629 /* HW workaround */
1630 if (!ar->hw->wiphy->bands[IEEE80211_BAND_5GHZ] &&
1631 channel->center_freq <= 2417)
1632 warm_reset = true;
1633
1634 if (rfi != CARL9170_RFI_NONE || warm_reset) {
1635 u32 val;
1636
1637 if (rfi == CARL9170_RFI_COLD)
1638 val = AR9170_PWR_RESET_BB_COLD_RESET;
1639 else
1640 val = AR9170_PWR_RESET_BB_WARM_RESET;
1641
1642 /* warm/cold reset BB/ADDA */
1643 err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET, val);
1644 if (err)
1645 return err;
1646
1647 err = carl9170_write_reg(ar, AR9170_PWR_REG_RESET, 0x0);
1648 if (err)
1649 return err;
1650
1651 err = carl9170_init_phy(ar, channel->band);
1652 if (err)
1653 return err;
1654
1655 err = carl9170_init_rf_banks_0_7(ar,
1656 channel->band == IEEE80211_BAND_5GHZ);
1657 if (err)
1658 return err;
1659
1660 cmd = CARL9170_CMD_RF_INIT;
1661
1662 msleep(100);
1663
1664 err = carl9170_echo_test(ar, 0xaabbccdd);
1665 if (err)
1666 return err;
1667 } else {
1668 cmd = CARL9170_CMD_FREQUENCY;
1669 }
1670
1671 err = carl9170_exec_cmd(ar, CARL9170_CMD_FREQ_START, 0, NULL, 0, NULL);
1672 if (err)
1673 return err;
1674
1675 err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE,
1676 0x200);
1677
1678 err = carl9170_init_rf_bank4_pwr(ar,
1679 channel->band == IEEE80211_BAND_5GHZ,
1680 channel->center_freq, bw);
1681 if (err)
1682 return err;
1683
1684 tmp = AR9170_PHY_TURBO_FC_SINGLE_HT_LTF1 |
1685 AR9170_PHY_TURBO_FC_HT_EN;
1686
1687 switch (bw) {
1688 case CARL9170_BW_20:
1689 break;
1690 case CARL9170_BW_40_BELOW:
1691 tmp |= AR9170_PHY_TURBO_FC_DYN2040_EN |
1692 AR9170_PHY_TURBO_FC_SHORT_GI_40;
1693 offs = 3;
1694 break;
1695 case CARL9170_BW_40_ABOVE:
1696 tmp |= AR9170_PHY_TURBO_FC_DYN2040_EN |
1697 AR9170_PHY_TURBO_FC_SHORT_GI_40 |
1698 AR9170_PHY_TURBO_FC_DYN2040_PRI_CH;
1699 offs = 1;
1700 break;
1701 default:
1702 BUG();
1703 return -ENOSYS;
1704 }
1705
1706 if (ar->eeprom.tx_mask != 1)
1707 tmp |= AR9170_PHY_TURBO_FC_WALSH;
1708
1709 err = carl9170_write_reg(ar, AR9170_PHY_REG_TURBO, tmp);
1710 if (err)
1711 return err;
1712
1713 err = carl9170_set_freq_cal_data(ar, channel);
1714 if (err)
1715 return err;
1716
1717 err = carl9170_set_power_cal(ar, channel->center_freq, bw);
1718 if (err)
1719 return err;
1720
1721 freqpar = carl9170_get_hw_dyn_params(channel, bw);
1722
1723 rf.ht_settings = 0;
1724 if (conf_is_ht(&ar->hw->conf)) {
1725 rf.ht_settings |= CARL9170FW_PHY_HT_ENABLE;
1726
1727 if (conf_is_ht40(&ar->hw->conf)) {
1728 rf.ht_settings |= CARL9170FW_PHY_HT_DYN2040;
1729 SET_VAL(CARL9170FW_PHY_HT_EXT_CHAN_OFF,
1730 rf.ht_settings, offs);
1731 }
1732 }
1733
1734 rf.freq = cpu_to_le32(channel->center_freq * 1000);
1735 rf.delta_slope_coeff_exp = cpu_to_le32(freqpar->coeff_exp);
1736 rf.delta_slope_coeff_man = cpu_to_le32(freqpar->coeff_man);
1737 rf.delta_slope_coeff_exp_shgi = cpu_to_le32(freqpar->coeff_exp_shgi);
1738 rf.delta_slope_coeff_man_shgi = cpu_to_le32(freqpar->coeff_man_shgi);
1739
1740 if (rfi != CARL9170_RFI_NONE)
1741 rf.finiteLoopCount = cpu_to_le32(2000);
1742 else
1743 rf.finiteLoopCount = cpu_to_le32(1000);
1744
1745 err = carl9170_exec_cmd(ar, cmd, sizeof(rf), &rf,
1746 sizeof(rf_res), &rf_res);
1747 if (err)
1748 return err;
1749
1750 err = le32_to_cpu(rf_res.ret);
1751 if (err != 0) {
1752 ar->chan_fail++;
1753 ar->total_chan_fail++;
1754
1755 wiphy_err(ar->hw->wiphy, "channel change: %d -> %d "
1756 "failed (%d).\n", old_channel ?
1757 old_channel->center_freq : -1, channel->center_freq,
1758 err);
1759
1760 if ((rfi == CARL9170_RFI_COLD) || (ar->chan_fail > 3)) {
1761 /*
1762 * We have tried very hard to change to _another_
1763 * channel and we've failed to do so!
1764 * Chances are that the PHY/RF is no longer
1765 * operable (due to corruptions/fatal events/bugs?)
1766 * and we need to reset at a higher level.
1767 */
1768 carl9170_restart(ar, CARL9170_RR_TOO_MANY_PHY_ERRORS);
1769 return 0;
1770 }
1771
1772 err = carl9170_set_channel(ar, channel, _bw,
1773 CARL9170_RFI_COLD);
1774 if (err)
1775 return err;
1776 } else {
1777 ar->chan_fail = 0;
1778 }
1779
1780 err = carl9170_get_noisefloor(ar);
1781 if (err)
1782 return err;
1783
1784 if (ar->heavy_clip) {
1785 err = carl9170_write_reg(ar, AR9170_PHY_REG_HEAVY_CLIP_ENABLE,
1786 0x200 | ar->heavy_clip);
1787 if (err) {
1788 if (net_ratelimit()) {
1789 wiphy_err(ar->hw->wiphy, "failed to set "
1790 "heavy clip\n");
1791 }
1792
1793 return err;
1794 }
1795 }
1796
1797 /* FIXME: PSM does not work in 5GHz Band */
1798 if (channel->band == IEEE80211_BAND_5GHZ)
1799 ar->ps.off_override |= PS_OFF_5GHZ;
1800 else
1801 ar->ps.off_override &= ~PS_OFF_5GHZ;
1802
1803 ar->channel = channel;
1804 return 0;
1805}
generated by cgit v1.2.2 (git 2.25.0) at 2026-01-01 17:23:19 -0500