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-rw-r--r--drivers/infiniband/hw/mlx5/mr.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/infiniband/hw/mlx5/mr.c b/drivers/infiniband/hw/mlx5/mr.c
index d7f202290747..2c4626f7b1b8 100644
--- a/drivers/infiniband/hw/mlx5/mr.c
+++ b/drivers/infiniband/hw/mlx5/mr.c
@@ -40,7 +40,6 @@
40#include "mlx5_ib.h" 40#include "mlx5_ib.h"
41 41
42enum { 42enum {
43 DEF_CACHE_SIZE = 10,
44 MAX_PENDING_REG_MR = 8, 43 MAX_PENDING_REG_MR = 8,
45}; 44};
46 45
@@ -550,7 +549,6 @@ int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
550 struct mlx5_mr_cache *cache = &dev->cache; 549 struct mlx5_mr_cache *cache = &dev->cache;
551 struct mlx5_cache_ent *ent; 550 struct mlx5_cache_ent *ent;
552 int limit; 551 int limit;
553 int size;
554 int err; 552 int err;
555 int i; 553 int i;
556 554
@@ -571,13 +569,11 @@ int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
571 ent->order = i + 2; 569 ent->order = i + 2;
572 ent->dev = dev; 570 ent->dev = dev;
573 571
574 if (dev->mdev.profile->mask & MLX5_PROF_MASK_MR_CACHE) { 572 if (dev->mdev.profile->mask & MLX5_PROF_MASK_MR_CACHE)
575 size = dev->mdev.profile->mr_cache[i].size;
576 limit = dev->mdev.profile->mr_cache[i].limit; 573 limit = dev->mdev.profile->mr_cache[i].limit;
577 } else { 574 else
578 size = DEF_CACHE_SIZE;
579 limit = 0; 575 limit = 0;
580 } 576
581 INIT_WORK(&ent->work, cache_work_func); 577 INIT_WORK(&ent->work, cache_work_func);
582 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func); 578 INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
583 ent->limit = limit; 579 ent->limit = limit;