aboutsummaryrefslogtreecommitdiffstats
diff options
context:
space:
mode:
Diffstat
-rw-r--r--arch/arm/mach-at91/at91sam9260_devices.c2
-rw-r--r--drivers/mmc/host/atmel-mci-regs.h206
-rw-r--r--drivers/mmc/host/atmel-mci.c301
-rw-r--r--include/linux/atmel-mci.h4
4 files changed, 257 insertions, 256 deletions
diff --git a/arch/arm/mach-at91/at91sam9260_devices.c b/arch/arm/mach-at91/at91sam9260_devices.c
index 39f81f47b4ba..c49e84a39a6f 100644
--- a/arch/arm/mach-at91/at91sam9260_devices.c
+++ b/arch/arm/mach-at91/at91sam9260_devices.c
@@ -319,7 +319,7 @@ void __init at91_add_device_mci(short mmc_id, struct mci_platform_data *data)
319 if (!data) 319 if (!data)
320 return; 320 return;
321 321
322 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 322 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
323 if (data->slot[i].bus_width) { 323 if (data->slot[i].bus_width) {
324 /* input/irq */ 324 /* input/irq */
325 if (data->slot[i].detect_pin) { 325 if (data->slot[i].detect_pin) {
diff --git a/drivers/mmc/host/atmel-mci-regs.h b/drivers/mmc/host/atmel-mci-regs.h
index fc8a0fe7c5c5..29331ab67dc3 100644
--- a/drivers/mmc/host/atmel-mci-regs.h
+++ b/drivers/mmc/host/atmel-mci-regs.h
@@ -17,112 +17,112 @@
17#define __DRIVERS_MMC_ATMEL_MCI_H__ 17#define __DRIVERS_MMC_ATMEL_MCI_H__
18 18
19/* MCI Register Definitions */ 19/* MCI Register Definitions */
20#define MCI_CR 0x0000 /* Control */ 20#define ATMCI_CR 0x0000 /* Control */
21# define MCI_CR_MCIEN ( 1 << 0) /* MCI Enable */ 21# define ATMCI_CR_MCIEN ( 1 << 0) /* MCI Enable */
22# define MCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */ 22# define ATMCI_CR_MCIDIS ( 1 << 1) /* MCI Disable */
23# define MCI_CR_PWSEN ( 1 << 2) /* Power Save Enable */ 23# define ATMCI_CR_PWSEN ( 1 << 2) /* Power Save Enable */
24# define MCI_CR_PWSDIS ( 1 << 3) /* Power Save Disable */ 24# define ATMCI_CR_PWSDIS ( 1 << 3) /* Power Save Disable */
25# define MCI_CR_SWRST ( 1 << 7) /* Software Reset */ 25# define ATMCI_CR_SWRST ( 1 << 7) /* Software Reset */
26#define MCI_MR 0x0004 /* Mode */ 26#define ATMCI_MR 0x0004 /* Mode */
27# define MCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */ 27# define ATMCI_MR_CLKDIV(x) ((x) << 0) /* Clock Divider */
28# define MCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */ 28# define ATMCI_MR_PWSDIV(x) ((x) << 8) /* Power Saving Divider */
29# define MCI_MR_RDPROOF ( 1 << 11) /* Read Proof */ 29# define ATMCI_MR_RDPROOF ( 1 << 11) /* Read Proof */
30# define MCI_MR_WRPROOF ( 1 << 12) /* Write Proof */ 30# define ATMCI_MR_WRPROOF ( 1 << 12) /* Write Proof */
31# define MCI_MR_PDCFBYTE ( 1 << 13) /* Force Byte Transfer */ 31# define ATMCI_MR_PDCFBYTE ( 1 << 13) /* Force Byte Transfer */
32# define MCI_MR_PDCPADV ( 1 << 14) /* Padding Value */ 32# define ATMCI_MR_PDCPADV ( 1 << 14) /* Padding Value */
33# define MCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */ 33# define ATMCI_MR_PDCMODE ( 1 << 15) /* PDC-oriented Mode */
34#define MCI_DTOR 0x0008 /* Data Timeout */ 34#define ATMCI_DTOR 0x0008 /* Data Timeout */
35# define MCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */ 35# define ATMCI_DTOCYC(x) ((x) << 0) /* Data Timeout Cycles */
36# define MCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */ 36# define ATMCI_DTOMUL(x) ((x) << 4) /* Data Timeout Multiplier */
37#define MCI_SDCR 0x000c /* SD Card / SDIO */ 37#define ATMCI_SDCR 0x000c /* SD Card / SDIO */
38# define MCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */ 38# define ATMCI_SDCSEL_SLOT_A ( 0 << 0) /* Select SD slot A */
39# define MCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */ 39# define ATMCI_SDCSEL_SLOT_B ( 1 << 0) /* Select SD slot A */
40# define MCI_SDCSEL_MASK ( 3 << 0) 40# define ATMCI_SDCSEL_MASK ( 3 << 0)
41# define MCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */ 41# define ATMCI_SDCBUS_1BIT ( 0 << 6) /* 1-bit data bus */
42# define MCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */ 42# define ATMCI_SDCBUS_4BIT ( 2 << 6) /* 4-bit data bus */
43# define MCI_SDCBUS_8BIT ( 3 << 6) /* 8-bit data bus[2] */ 43# define ATMCI_SDCBUS_8BIT ( 3 << 6) /* 8-bit data bus[2] */
44# define MCI_SDCBUS_MASK ( 3 << 6) 44# define ATMCI_SDCBUS_MASK ( 3 << 6)
45#define MCI_ARGR 0x0010 /* Command Argument */ 45#define ATMCI_ARGR 0x0010 /* Command Argument */
46#define MCI_CMDR 0x0014 /* Command */ 46#define ATMCI_CMDR 0x0014 /* Command */
47# define MCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */ 47# define ATMCI_CMDR_CMDNB(x) ((x) << 0) /* Command Opcode */
48# define MCI_CMDR_RSPTYP_NONE ( 0 << 6) /* No response */ 48# define ATMCI_CMDR_RSPTYP_NONE ( 0 << 6) /* No response */
49# define MCI_CMDR_RSPTYP_48BIT ( 1 << 6) /* 48-bit response */ 49# define ATMCI_CMDR_RSPTYP_48BIT ( 1 << 6) /* 48-bit response */
50# define MCI_CMDR_RSPTYP_136BIT ( 2 << 6) /* 136-bit response */ 50# define ATMCI_CMDR_RSPTYP_136BIT ( 2 << 6) /* 136-bit response */
51# define MCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */ 51# define ATMCI_CMDR_SPCMD_INIT ( 1 << 8) /* Initialization command */
52# define MCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */ 52# define ATMCI_CMDR_SPCMD_SYNC ( 2 << 8) /* Synchronized command */
53# define MCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */ 53# define ATMCI_CMDR_SPCMD_INT ( 4 << 8) /* Interrupt command */
54# define MCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */ 54# define ATMCI_CMDR_SPCMD_INTRESP ( 5 << 8) /* Interrupt response */
55# define MCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */ 55# define ATMCI_CMDR_OPDCMD ( 1 << 11) /* Open Drain */
56# define MCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */ 56# define ATMCI_CMDR_MAXLAT_5CYC ( 0 << 12) /* Max latency 5 cycles */
57# define MCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */ 57# define ATMCI_CMDR_MAXLAT_64CYC ( 1 << 12) /* Max latency 64 cycles */
58# define MCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */ 58# define ATMCI_CMDR_START_XFER ( 1 << 16) /* Start data transfer */
59# define MCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */ 59# define ATMCI_CMDR_STOP_XFER ( 2 << 16) /* Stop data transfer */
60# define MCI_CMDR_TRDIR_WRITE ( 0 << 18) /* Write data */ 60# define ATMCI_CMDR_TRDIR_WRITE ( 0 << 18) /* Write data */
61# define MCI_CMDR_TRDIR_READ ( 1 << 18) /* Read data */ 61# define ATMCI_CMDR_TRDIR_READ ( 1 << 18) /* Read data */
62# define MCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */ 62# define ATMCI_CMDR_BLOCK ( 0 << 19) /* Single-block transfer */
63# define MCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */ 63# define ATMCI_CMDR_MULTI_BLOCK ( 1 << 19) /* Multi-block transfer */
64# define MCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */ 64# define ATMCI_CMDR_STREAM ( 2 << 19) /* MMC Stream transfer */
65# define MCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */ 65# define ATMCI_CMDR_SDIO_BYTE ( 4 << 19) /* SDIO Byte transfer */
66# define MCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */ 66# define ATMCI_CMDR_SDIO_BLOCK ( 5 << 19) /* SDIO Block transfer */
67# define MCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */ 67# define ATMCI_CMDR_SDIO_SUSPEND ( 1 << 24) /* SDIO Suspend Command */
68# define MCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */ 68# define ATMCI_CMDR_SDIO_RESUME ( 2 << 24) /* SDIO Resume Command */
69#define MCI_BLKR 0x0018 /* Block */ 69#define ATMCI_BLKR 0x0018 /* Block */
70# define MCI_BCNT(x) ((x) << 0) /* Data Block Count */ 70# define ATMCI_BCNT(x) ((x) << 0) /* Data Block Count */
71# define MCI_BLKLEN(x) ((x) << 16) /* Data Block Length */ 71# define ATMCI_BLKLEN(x) ((x) << 16) /* Data Block Length */
72#define MCI_CSTOR 0x001c /* Completion Signal Timeout[2] */ 72#define ATMCI_CSTOR 0x001c /* Completion Signal Timeout[2] */
73# define MCI_CSTOCYC(x) ((x) << 0) /* CST cycles */ 73# define ATMCI_CSTOCYC(x) ((x) << 0) /* CST cycles */
74# define MCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */ 74# define ATMCI_CSTOMUL(x) ((x) << 4) /* CST multiplier */
75#define MCI_RSPR 0x0020 /* Response 0 */ 75#define ATMCI_RSPR 0x0020 /* Response 0 */
76#define MCI_RSPR1 0x0024 /* Response 1 */ 76#define ATMCI_RSPR1 0x0024 /* Response 1 */
77#define MCI_RSPR2 0x0028 /* Response 2 */ 77#define ATMCI_RSPR2 0x0028 /* Response 2 */
78#define MCI_RSPR3 0x002c /* Response 3 */ 78#define ATMCI_RSPR3 0x002c /* Response 3 */
79#define MCI_RDR 0x0030 /* Receive Data */ 79#define ATMCI_RDR 0x0030 /* Receive Data */
80#define MCI_TDR 0x0034 /* Transmit Data */ 80#define ATMCI_TDR 0x0034 /* Transmit Data */
81#define MCI_SR 0x0040 /* Status */ 81#define ATMCI_SR 0x0040 /* Status */
82#define MCI_IER 0x0044 /* Interrupt Enable */ 82#define ATMCI_IER 0x0044 /* Interrupt Enable */
83#define MCI_IDR 0x0048 /* Interrupt Disable */ 83#define ATMCI_IDR 0x0048 /* Interrupt Disable */
84#define MCI_IMR 0x004c /* Interrupt Mask */ 84#define ATMCI_IMR 0x004c /* Interrupt Mask */
85# define MCI_CMDRDY ( 1 << 0) /* Command Ready */ 85# define ATMCI_CMDRDY ( 1 << 0) /* Command Ready */
86# define MCI_RXRDY ( 1 << 1) /* Receiver Ready */ 86# define ATMCI_RXRDY ( 1 << 1) /* Receiver Ready */
87# define MCI_TXRDY ( 1 << 2) /* Transmitter Ready */ 87# define ATMCI_TXRDY ( 1 << 2) /* Transmitter Ready */
88# define MCI_BLKE ( 1 << 3) /* Data Block Ended */ 88# define ATMCI_BLKE ( 1 << 3) /* Data Block Ended */
89# define MCI_DTIP ( 1 << 4) /* Data Transfer In Progress */ 89# define ATMCI_DTIP ( 1 << 4) /* Data Transfer In Progress */
90# define MCI_NOTBUSY ( 1 << 5) /* Data Not Busy */ 90# define ATMCI_NOTBUSY ( 1 << 5) /* Data Not Busy */
91# define MCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */ 91# define ATMCI_SDIOIRQA ( 1 << 8) /* SDIO IRQ in slot A */
92# define MCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */ 92# define ATMCI_SDIOIRQB ( 1 << 9) /* SDIO IRQ in slot B */
93# define MCI_RINDE ( 1 << 16) /* Response Index Error */ 93# define ATMCI_RINDE ( 1 << 16) /* Response Index Error */
94# define MCI_RDIRE ( 1 << 17) /* Response Direction Error */ 94# define ATMCI_RDIRE ( 1 << 17) /* Response Direction Error */
95# define MCI_RCRCE ( 1 << 18) /* Response CRC Error */ 95# define ATMCI_RCRCE ( 1 << 18) /* Response CRC Error */
96# define MCI_RENDE ( 1 << 19) /* Response End Bit Error */ 96# define ATMCI_RENDE ( 1 << 19) /* Response End Bit Error */
97# define MCI_RTOE ( 1 << 20) /* Response Time-Out Error */ 97# define ATMCI_RTOE ( 1 << 20) /* Response Time-Out Error */
98# define MCI_DCRCE ( 1 << 21) /* Data CRC Error */ 98# define ATMCI_DCRCE ( 1 << 21) /* Data CRC Error */
99# define MCI_DTOE ( 1 << 22) /* Data Time-Out Error */ 99# define ATMCI_DTOE ( 1 << 22) /* Data Time-Out Error */
100# define MCI_OVRE ( 1 << 30) /* RX Overrun Error */ 100# define ATMCI_OVRE ( 1 << 30) /* RX Overrun Error */
101# define MCI_UNRE ( 1 << 31) /* TX Underrun Error */ 101# define ATMCI_UNRE ( 1 << 31) /* TX Underrun Error */
102#define MCI_DMA 0x0050 /* DMA Configuration[2] */ 102#define ATMCI_DMA 0x0050 /* DMA Configuration[2] */
103# define MCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */ 103# define ATMCI_DMA_OFFSET(x) ((x) << 0) /* DMA Write Buffer Offset */
104# define MCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */ 104# define ATMCI_DMA_CHKSIZE(x) ((x) << 4) /* DMA Channel Read and Write Chunk Size */
105# define MCI_DMAEN ( 1 << 8) /* DMA Hardware Handshaking Enable */ 105# define ATMCI_DMAEN ( 1 << 8) /* DMA Hardware Handshaking Enable */
106#define MCI_CFG 0x0054 /* Configuration[2] */ 106#define ATMCI_CFG 0x0054 /* Configuration[2] */
107# define MCI_CFG_FIFOMODE_1DATA ( 1 << 0) /* MCI Internal FIFO control mode */ 107# define ATMCI_CFG_FIFOMODE_1DATA ( 1 << 0) /* MCI Internal FIFO control mode */
108# define MCI_CFG_FERRCTRL_COR ( 1 << 4) /* Flow Error flag reset control mode */ 108# define ATMCI_CFG_FERRCTRL_COR ( 1 << 4) /* Flow Error flag reset control mode */
109# define MCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */ 109# define ATMCI_CFG_HSMODE ( 1 << 8) /* High Speed Mode */
110# define MCI_CFG_LSYNC ( 1 << 12) /* Synchronize on the last block */ 110# define ATMCI_CFG_LSYNC ( 1 << 12) /* Synchronize on the last block */
111#define MCI_WPMR 0x00e4 /* Write Protection Mode[2] */ 111#define ATMCI_WPMR 0x00e4 /* Write Protection Mode[2] */
112# define MCI_WP_EN ( 1 << 0) /* WP Enable */ 112# define ATMCI_WP_EN ( 1 << 0) /* WP Enable */
113# define MCI_WP_KEY (0x4d4349 << 8) /* WP Key */ 113# define ATMCI_WP_KEY (0x4d4349 << 8) /* WP Key */
114#define MCI_WPSR 0x00e8 /* Write Protection Status[2] */ 114#define ATMCI_WPSR 0x00e8 /* Write Protection Status[2] */
115# define MCI_GET_WP_VS(x) ((x) & 0x0f) 115# define ATMCI_GET_WP_VS(x) ((x) & 0x0f)
116# define MCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff) 116# define ATMCI_GET_WP_VSRC(x) (((x) >> 8) & 0xffff)
117#define MCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */ 117#define ATMCI_FIFO_APERTURE 0x0200 /* FIFO Aperture[2] */
118 118
119/* This is not including the FIFO Aperture on MCI2 */ 119/* This is not including the FIFO Aperture on MCI2 */
120#define MCI_REGS_SIZE 0x100 120#define ATMCI_REGS_SIZE 0x100
121 121
122/* Register access macros */ 122/* Register access macros */
123#define mci_readl(port,reg) \ 123#define atmci_readl(port,reg) \
124 __raw_readl((port)->regs + MCI_##reg) 124 __raw_readl((port)->regs + ATMCI_##reg)
125#define mci_writel(port,reg,value) \ 125#define atmci_writel(port,reg,value) \
126 __raw_writel((value), (port)->regs + MCI_##reg) 126 __raw_writel((value), (port)->regs + ATMCI_##reg)
127 127
128#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */ 128#endif /* __DRIVERS_MMC_ATMEL_MCI_H__ */
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index fa8cae1d7005..c2a0949f3257 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -39,7 +39,7 @@
39 39
40#include "atmel-mci-regs.h" 40#include "atmel-mci-regs.h"
41 41
42#define ATMCI_DATA_ERROR_FLAGS (MCI_DCRCE | MCI_DTOE | MCI_OVRE | MCI_UNRE) 42#define ATMCI_DATA_ERROR_FLAGS (ATMCI_DCRCE | ATMCI_DTOE | ATMCI_OVRE | ATMCI_UNRE)
43#define ATMCI_DMA_THRESHOLD 16 43#define ATMCI_DMA_THRESHOLD 16
44 44
45enum { 45enum {
@@ -166,7 +166,7 @@ struct atmel_mci {
166 struct clk *mck; 166 struct clk *mck;
167 struct platform_device *pdev; 167 struct platform_device *pdev;
168 168
169 struct atmel_mci_slot *slot[ATMEL_MCI_MAX_NR_SLOTS]; 169 struct atmel_mci_slot *slot[ATMCI_MAX_NR_SLOTS];
170}; 170};
171 171
172/** 172/**
@@ -223,7 +223,7 @@ struct atmel_mci_slot {
223 * Enable or disable features/registers based on 223 * Enable or disable features/registers based on
224 * whether the processor supports them 224 * whether the processor supports them
225 */ 225 */
226static bool mci_has_rwproof(void) 226static bool atmci_has_rwproof(void)
227{ 227{
228 if (cpu_is_at91sam9261() || cpu_is_at91rm9200()) 228 if (cpu_is_at91sam9261() || cpu_is_at91rm9200())
229 return false; 229 return false;
@@ -352,7 +352,7 @@ static int atmci_regs_show(struct seq_file *s, void *v)
352 struct atmel_mci *host = s->private; 352 struct atmel_mci *host = s->private;
353 u32 *buf; 353 u32 *buf;
354 354
355 buf = kmalloc(MCI_REGS_SIZE, GFP_KERNEL); 355 buf = kmalloc(ATMCI_REGS_SIZE, GFP_KERNEL);
356 if (!buf) 356 if (!buf)
357 return -ENOMEM; 357 return -ENOMEM;
358 358
@@ -363,47 +363,47 @@ static int atmci_regs_show(struct seq_file *s, void *v)
363 */ 363 */
364 spin_lock_bh(&host->lock); 364 spin_lock_bh(&host->lock);
365 clk_enable(host->mck); 365 clk_enable(host->mck);
366 memcpy_fromio(buf, host->regs, MCI_REGS_SIZE); 366 memcpy_fromio(buf, host->regs, ATMCI_REGS_SIZE);
367 clk_disable(host->mck); 367 clk_disable(host->mck);
368 spin_unlock_bh(&host->lock); 368 spin_unlock_bh(&host->lock);
369 369
370 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n", 370 seq_printf(s, "MR:\t0x%08x%s%s CLKDIV=%u\n",
371 buf[MCI_MR / 4], 371 buf[ATMCI_MR / 4],
372 buf[MCI_MR / 4] & MCI_MR_RDPROOF ? " RDPROOF" : "", 372 buf[ATMCI_MR / 4] & ATMCI_MR_RDPROOF ? " RDPROOF" : "",
373 buf[MCI_MR / 4] & MCI_MR_WRPROOF ? " WRPROOF" : "", 373 buf[ATMCI_MR / 4] & ATMCI_MR_WRPROOF ? " WRPROOF" : "",
374 buf[MCI_MR / 4] & 0xff); 374 buf[ATMCI_MR / 4] & 0xff);
375 seq_printf(s, "DTOR:\t0x%08x\n", buf[MCI_DTOR / 4]); 375 seq_printf(s, "DTOR:\t0x%08x\n", buf[ATMCI_DTOR / 4]);
376 seq_printf(s, "SDCR:\t0x%08x\n", buf[MCI_SDCR / 4]); 376 seq_printf(s, "SDCR:\t0x%08x\n", buf[ATMCI_SDCR / 4]);
377 seq_printf(s, "ARGR:\t0x%08x\n", buf[MCI_ARGR / 4]); 377 seq_printf(s, "ARGR:\t0x%08x\n", buf[ATMCI_ARGR / 4]);
378 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n", 378 seq_printf(s, "BLKR:\t0x%08x BCNT=%u BLKLEN=%u\n",
379 buf[MCI_BLKR / 4], 379 buf[ATMCI_BLKR / 4],
380 buf[MCI_BLKR / 4] & 0xffff, 380 buf[ATMCI_BLKR / 4] & 0xffff,
381 (buf[MCI_BLKR / 4] >> 16) & 0xffff); 381 (buf[ATMCI_BLKR / 4] >> 16) & 0xffff);
382 if (atmci_is_mci2()) 382 if (atmci_is_mci2())
383 seq_printf(s, "CSTOR:\t0x%08x\n", buf[MCI_CSTOR / 4]); 383 seq_printf(s, "CSTOR:\t0x%08x\n", buf[ATMCI_CSTOR / 4]);
384 384
385 /* Don't read RSPR and RDR; it will consume the data there */ 385 /* Don't read RSPR and RDR; it will consume the data there */
386 386
387 atmci_show_status_reg(s, "SR", buf[MCI_SR / 4]); 387 atmci_show_status_reg(s, "SR", buf[ATMCI_SR / 4]);
388 atmci_show_status_reg(s, "IMR", buf[MCI_IMR / 4]); 388 atmci_show_status_reg(s, "IMR", buf[ATMCI_IMR / 4]);
389 389
390 if (atmci_is_mci2()) { 390 if (atmci_is_mci2()) {
391 u32 val; 391 u32 val;
392 392
393 val = buf[MCI_DMA / 4]; 393 val = buf[ATMCI_DMA / 4];
394 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n", 394 seq_printf(s, "DMA:\t0x%08x OFFSET=%u CHKSIZE=%u%s\n",
395 val, val & 3, 395 val, val & 3,
396 ((val >> 4) & 3) ? 396 ((val >> 4) & 3) ?
397 1 << (((val >> 4) & 3) + 1) : 1, 397 1 << (((val >> 4) & 3) + 1) : 1,
398 val & MCI_DMAEN ? " DMAEN" : ""); 398 val & ATMCI_DMAEN ? " DMAEN" : "");
399 399
400 val = buf[MCI_CFG / 4]; 400 val = buf[ATMCI_CFG / 4];
401 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n", 401 seq_printf(s, "CFG:\t0x%08x%s%s%s%s\n",
402 val, 402 val,
403 val & MCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "", 403 val & ATMCI_CFG_FIFOMODE_1DATA ? " FIFOMODE_ONE_DATA" : "",
404 val & MCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "", 404 val & ATMCI_CFG_FERRCTRL_COR ? " FERRCTRL_CLEAR_ON_READ" : "",
405 val & MCI_CFG_HSMODE ? " HSMODE" : "", 405 val & ATMCI_CFG_HSMODE ? " HSMODE" : "",
406 val & MCI_CFG_LSYNC ? " LSYNC" : ""); 406 val & ATMCI_CFG_LSYNC ? " LSYNC" : "");
407 } 407 }
408 408
409 kfree(buf); 409 kfree(buf);
@@ -466,7 +466,7 @@ err:
466 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n"); 466 dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
467} 467}
468 468
469static inline unsigned int ns_to_clocks(struct atmel_mci *host, 469static inline unsigned int atmci_ns_to_clocks(struct atmel_mci *host,
470 unsigned int ns) 470 unsigned int ns)
471{ 471{
472 return (ns * (host->bus_hz / 1000000) + 999) / 1000; 472 return (ns * (host->bus_hz / 1000000) + 999) / 1000;
@@ -482,7 +482,8 @@ static void atmci_set_timeout(struct atmel_mci *host,
482 unsigned dtocyc; 482 unsigned dtocyc;
483 unsigned dtomul; 483 unsigned dtomul;
484 484
485 timeout = ns_to_clocks(host, data->timeout_ns) + data->timeout_clks; 485 timeout = atmci_ns_to_clocks(host, data->timeout_ns)
486 + data->timeout_clks;
486 487
487 for (dtomul = 0; dtomul < 8; dtomul++) { 488 for (dtomul = 0; dtomul < 8; dtomul++) {
488 unsigned shift = dtomul_to_shift[dtomul]; 489 unsigned shift = dtomul_to_shift[dtomul];
@@ -498,7 +499,7 @@ static void atmci_set_timeout(struct atmel_mci *host,
498 499
499 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n", 500 dev_vdbg(&slot->mmc->class_dev, "setting timeout to %u cycles\n",
500 dtocyc << dtomul_to_shift[dtomul]); 501 dtocyc << dtomul_to_shift[dtomul]);
501 mci_writel(host, DTOR, (MCI_DTOMUL(dtomul) | MCI_DTOCYC(dtocyc))); 502 atmci_writel(host, DTOR, (ATMCI_DTOMUL(dtomul) | ATMCI_DTOCYC(dtocyc)));
502} 503}
503 504
504/* 505/*
@@ -512,13 +513,13 @@ static u32 atmci_prepare_command(struct mmc_host *mmc,
512 513
513 cmd->error = -EINPROGRESS; 514 cmd->error = -EINPROGRESS;
514 515
515 cmdr = MCI_CMDR_CMDNB(cmd->opcode); 516 cmdr = ATMCI_CMDR_CMDNB(cmd->opcode);
516 517
517 if (cmd->flags & MMC_RSP_PRESENT) { 518 if (cmd->flags & MMC_RSP_PRESENT) {
518 if (cmd->flags & MMC_RSP_136) 519 if (cmd->flags & MMC_RSP_136)
519 cmdr |= MCI_CMDR_RSPTYP_136BIT; 520 cmdr |= ATMCI_CMDR_RSPTYP_136BIT;
520 else 521 else
521 cmdr |= MCI_CMDR_RSPTYP_48BIT; 522 cmdr |= ATMCI_CMDR_RSPTYP_48BIT;
522 } 523 }
523 524
524 /* 525 /*
@@ -526,28 +527,28 @@ static u32 atmci_prepare_command(struct mmc_host *mmc,
526 * it's too difficult to determine whether this is an ACMD or 527 * it's too difficult to determine whether this is an ACMD or
527 * not. Better make it 64. 528 * not. Better make it 64.
528 */ 529 */
529 cmdr |= MCI_CMDR_MAXLAT_64CYC; 530 cmdr |= ATMCI_CMDR_MAXLAT_64CYC;
530 531
531 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN) 532 if (mmc->ios.bus_mode == MMC_BUSMODE_OPENDRAIN)
532 cmdr |= MCI_CMDR_OPDCMD; 533 cmdr |= ATMCI_CMDR_OPDCMD;
533 534
534 data = cmd->data; 535 data = cmd->data;
535 if (data) { 536 if (data) {
536 cmdr |= MCI_CMDR_START_XFER; 537 cmdr |= ATMCI_CMDR_START_XFER;
537 538
538 if (cmd->opcode == SD_IO_RW_EXTENDED) { 539 if (cmd->opcode == SD_IO_RW_EXTENDED) {
539 cmdr |= MCI_CMDR_SDIO_BLOCK; 540 cmdr |= ATMCI_CMDR_SDIO_BLOCK;
540 } else { 541 } else {
541 if (data->flags & MMC_DATA_STREAM) 542 if (data->flags & MMC_DATA_STREAM)
542 cmdr |= MCI_CMDR_STREAM; 543 cmdr |= ATMCI_CMDR_STREAM;
543 else if (data->blocks > 1) 544 else if (data->blocks > 1)
544 cmdr |= MCI_CMDR_MULTI_BLOCK; 545 cmdr |= ATMCI_CMDR_MULTI_BLOCK;
545 else 546 else
546 cmdr |= MCI_CMDR_BLOCK; 547 cmdr |= ATMCI_CMDR_BLOCK;
547 } 548 }
548 549
549 if (data->flags & MMC_DATA_READ) 550 if (data->flags & MMC_DATA_READ)
550 cmdr |= MCI_CMDR_TRDIR_READ; 551 cmdr |= ATMCI_CMDR_TRDIR_READ;
551 } 552 }
552 553
553 return cmdr; 554 return cmdr;
@@ -563,14 +564,14 @@ static void atmci_start_command(struct atmel_mci *host,
563 "start command: ARGR=0x%08x CMDR=0x%08x\n", 564 "start command: ARGR=0x%08x CMDR=0x%08x\n",
564 cmd->arg, cmd_flags); 565 cmd->arg, cmd_flags);
565 566
566 mci_writel(host, ARGR, cmd->arg); 567 atmci_writel(host, ARGR, cmd->arg);
567 mci_writel(host, CMDR, cmd_flags); 568 atmci_writel(host, CMDR, cmd_flags);
568} 569}
569 570
570static void send_stop_cmd(struct atmel_mci *host, struct mmc_data *data) 571static void atmci_send_stop_cmd(struct atmel_mci *host, struct mmc_data *data)
571{ 572{
572 atmci_start_command(host, data->stop, host->stop_cmdr); 573 atmci_start_command(host, data->stop, host->stop_cmdr);
573 mci_writel(host, IER, MCI_CMDRDY); 574 atmci_writel(host, IER, ATMCI_CMDRDY);
574} 575}
575 576
576#ifdef CONFIG_MMC_ATMELMCI_DMA 577#ifdef CONFIG_MMC_ATMELMCI_DMA
@@ -595,7 +596,7 @@ static void atmci_stop_dma(struct atmel_mci *host)
595 } else { 596 } else {
596 /* Data transfer was stopped by the interrupt handler */ 597 /* Data transfer was stopped by the interrupt handler */
597 atmci_set_pending(host, EVENT_XFER_COMPLETE); 598 atmci_set_pending(host, EVENT_XFER_COMPLETE);
598 mci_writel(host, IER, MCI_NOTBUSY); 599 atmci_writel(host, IER, ATMCI_NOTBUSY);
599 } 600 }
600} 601}
601 602
@@ -609,7 +610,7 @@ static void atmci_dma_complete(void *arg)
609 610
610 if (atmci_is_mci2()) 611 if (atmci_is_mci2())
611 /* Disable DMA hardware handshaking on MCI */ 612 /* Disable DMA hardware handshaking on MCI */
612 mci_writel(host, DMA, mci_readl(host, DMA) & ~MCI_DMAEN); 613 atmci_writel(host, DMA, atmci_readl(host, DMA) & ~ATMCI_DMAEN);
613 614
614 atmci_dma_cleanup(host); 615 atmci_dma_cleanup(host);
615 616
@@ -641,7 +642,7 @@ static void atmci_dma_complete(void *arg)
641 * completion callback" rule of the dma engine 642 * completion callback" rule of the dma engine
642 * framework. 643 * framework.
643 */ 644 */
644 mci_writel(host, IER, MCI_NOTBUSY); 645 atmci_writel(host, IER, ATMCI_NOTBUSY);
645 } 646 }
646} 647}
647 648
@@ -660,7 +661,7 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
660 * non-word-aligned buffers or lengths. Also, we don't bother 661 * non-word-aligned buffers or lengths. Also, we don't bother
661 * with all the DMA setup overhead for short transfers. 662 * with all the DMA setup overhead for short transfers.
662 */ 663 */
663 if (data->blocks * data->blksz < ATMCI_DMA_THRESHOLD) 664 if (data->blocks * data->blksz < ATATMCI_DMA_THRESHOLD)
664 return -EINVAL; 665 return -EINVAL;
665 if (data->blksz & 3) 666 if (data->blksz & 3)
666 return -EINVAL; 667 return -EINVAL;
@@ -679,7 +680,7 @@ atmci_prepare_data_dma(struct atmel_mci *host, struct mmc_data *data)
679 return -ENODEV; 680 return -ENODEV;
680 681
681 if (atmci_is_mci2()) 682 if (atmci_is_mci2())
682 mci_writel(host, DMA, MCI_DMA_CHKSIZE(3) | MCI_DMAEN); 683 atmci_writel(host, DMA, ATMCI_DMA_CHKSIZE(3) | ATMCI_DMAEN);
683 684
684 if (data->flags & MMC_DATA_READ) 685 if (data->flags & MMC_DATA_READ)
685 direction = DMA_FROM_DEVICE; 686 direction = DMA_FROM_DEVICE;
@@ -729,7 +730,7 @@ static void atmci_stop_dma(struct atmel_mci *host)
729{ 730{
730 /* Data transfer was stopped by the interrupt handler */ 731 /* Data transfer was stopped by the interrupt handler */
731 atmci_set_pending(host, EVENT_XFER_COMPLETE); 732 atmci_set_pending(host, EVENT_XFER_COMPLETE);
732 mci_writel(host, IER, MCI_NOTBUSY); 733 atmci_writel(host, IER, ATMCI_NOTBUSY);
733} 734}
734 735
735#endif /* CONFIG_MMC_ATMELMCI_DMA */ 736#endif /* CONFIG_MMC_ATMELMCI_DMA */
@@ -766,9 +767,9 @@ static u32 atmci_prepare_data(struct atmel_mci *host, struct mmc_data *data)
766 host->sg = data->sg; 767 host->sg = data->sg;
767 host->pio_offset = 0; 768 host->pio_offset = 0;
768 if (data->flags & MMC_DATA_READ) 769 if (data->flags & MMC_DATA_READ)
769 iflags |= MCI_RXRDY; 770 iflags |= ATMCI_RXRDY;
770 else 771 else
771 iflags |= MCI_TXRDY; 772 iflags |= ATMCI_TXRDY;
772 } 773 }
773 774
774 return iflags; 775 return iflags;
@@ -792,24 +793,24 @@ static void atmci_start_request(struct atmel_mci *host,
792 host->data_status = 0; 793 host->data_status = 0;
793 794
794 if (host->need_reset) { 795 if (host->need_reset) {
795 mci_writel(host, CR, MCI_CR_SWRST); 796 atmci_writel(host, CR, ATMCI_CR_SWRST);
796 mci_writel(host, CR, MCI_CR_MCIEN); 797 atmci_writel(host, CR, ATMCI_CR_MCIEN);
797 mci_writel(host, MR, host->mode_reg); 798 atmci_writel(host, MR, host->mode_reg);
798 if (atmci_is_mci2()) 799 if (atmci_is_mci2())
799 mci_writel(host, CFG, host->cfg_reg); 800 atmci_writel(host, CFG, host->cfg_reg);
800 host->need_reset = false; 801 host->need_reset = false;
801 } 802 }
802 mci_writel(host, SDCR, slot->sdc_reg); 803 atmci_writel(host, SDCR, slot->sdc_reg);
803 804
804 iflags = mci_readl(host, IMR); 805 iflags = atmci_readl(host, IMR);
805 if (iflags & ~(MCI_SDIOIRQA | MCI_SDIOIRQB)) 806 if (iflags & ~(ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
806 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n", 807 dev_warn(&slot->mmc->class_dev, "WARNING: IMR=0x%08x\n",
807 iflags); 808 iflags);
808 809
809 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) { 810 if (unlikely(test_and_clear_bit(ATMCI_CARD_NEED_INIT, &slot->flags))) {
810 /* Send init sequence (74 clock cycles) */ 811 /* Send init sequence (74 clock cycles) */
811 mci_writel(host, CMDR, MCI_CMDR_SPCMD_INIT); 812 atmci_writel(host, CMDR, ATMCI_CMDR_SPCMD_INIT);
812 while (!(mci_readl(host, SR) & MCI_CMDRDY)) 813 while (!(atmci_readl(host, SR) & ATMCI_CMDRDY))
813 cpu_relax(); 814 cpu_relax();
814 } 815 }
815 iflags = 0; 816 iflags = 0;
@@ -818,15 +819,15 @@ static void atmci_start_request(struct atmel_mci *host,
818 atmci_set_timeout(host, slot, data); 819 atmci_set_timeout(host, slot, data);
819 820
820 /* Must set block count/size before sending command */ 821 /* Must set block count/size before sending command */
821 mci_writel(host, BLKR, MCI_BCNT(data->blocks) 822 atmci_writel(host, BLKR, ATMCI_BCNT(data->blocks)
822 | MCI_BLKLEN(data->blksz)); 823 | ATMCI_BLKLEN(data->blksz));
823 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n", 824 dev_vdbg(&slot->mmc->class_dev, "BLKR=0x%08x\n",
824 MCI_BCNT(data->blocks) | MCI_BLKLEN(data->blksz)); 825 ATMCI_BCNT(data->blocks) | ATMCI_BLKLEN(data->blksz));
825 826
826 iflags |= atmci_prepare_data(host, data); 827 iflags |= atmci_prepare_data(host, data);
827 } 828 }
828 829
829 iflags |= MCI_CMDRDY; 830 iflags |= ATMCI_CMDRDY;
830 cmd = mrq->cmd; 831 cmd = mrq->cmd;
831 cmdflags = atmci_prepare_command(slot->mmc, cmd); 832 cmdflags = atmci_prepare_command(slot->mmc, cmd);
832 atmci_start_command(host, cmd, cmdflags); 833 atmci_start_command(host, cmd, cmdflags);
@@ -836,13 +837,13 @@ static void atmci_start_request(struct atmel_mci *host,
836 837
837 if (mrq->stop) { 838 if (mrq->stop) {
838 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop); 839 host->stop_cmdr = atmci_prepare_command(slot->mmc, mrq->stop);
839 host->stop_cmdr |= MCI_CMDR_STOP_XFER; 840 host->stop_cmdr |= ATMCI_CMDR_STOP_XFER;
840 if (!(data->flags & MMC_DATA_WRITE)) 841 if (!(data->flags & MMC_DATA_WRITE))
841 host->stop_cmdr |= MCI_CMDR_TRDIR_READ; 842 host->stop_cmdr |= ATMCI_CMDR_TRDIR_READ;
842 if (data->flags & MMC_DATA_STREAM) 843 if (data->flags & MMC_DATA_STREAM)
843 host->stop_cmdr |= MCI_CMDR_STREAM; 844 host->stop_cmdr |= ATMCI_CMDR_STREAM;
844 else 845 else
845 host->stop_cmdr |= MCI_CMDR_MULTI_BLOCK; 846 host->stop_cmdr |= ATMCI_CMDR_MULTI_BLOCK;
846 } 847 }
847 848
848 /* 849 /*
@@ -851,7 +852,7 @@ static void atmci_start_request(struct atmel_mci *host,
851 * conditions (e.g. command and data complete, but stop not 852 * conditions (e.g. command and data complete, but stop not
852 * prepared yet.) 853 * prepared yet.)
853 */ 854 */
854 mci_writel(host, IER, iflags); 855 atmci_writel(host, IER, iflags);
855} 856}
856 857
857static void atmci_queue_request(struct atmel_mci *host, 858static void atmci_queue_request(struct atmel_mci *host,
@@ -909,13 +910,13 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
909 struct atmel_mci *host = slot->host; 910 struct atmel_mci *host = slot->host;
910 unsigned int i; 911 unsigned int i;
911 912
912 slot->sdc_reg &= ~MCI_SDCBUS_MASK; 913 slot->sdc_reg &= ~ATMCI_SDCBUS_MASK;
913 switch (ios->bus_width) { 914 switch (ios->bus_width) {
914 case MMC_BUS_WIDTH_1: 915 case MMC_BUS_WIDTH_1:
915 slot->sdc_reg |= MCI_SDCBUS_1BIT; 916 slot->sdc_reg |= ATMCI_SDCBUS_1BIT;
916 break; 917 break;
917 case MMC_BUS_WIDTH_4: 918 case MMC_BUS_WIDTH_4:
918 slot->sdc_reg |= MCI_SDCBUS_4BIT; 919 slot->sdc_reg |= ATMCI_SDCBUS_4BIT;
919 break; 920 break;
920 } 921 }
921 922
@@ -926,10 +927,10 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
926 spin_lock_bh(&host->lock); 927 spin_lock_bh(&host->lock);
927 if (!host->mode_reg) { 928 if (!host->mode_reg) {
928 clk_enable(host->mck); 929 clk_enable(host->mck);
929 mci_writel(host, CR, MCI_CR_SWRST); 930 atmci_writel(host, CR, ATMCI_CR_SWRST);
930 mci_writel(host, CR, MCI_CR_MCIEN); 931 atmci_writel(host, CR, ATMCI_CR_MCIEN);
931 if (atmci_is_mci2()) 932 if (atmci_is_mci2())
932 mci_writel(host, CFG, host->cfg_reg); 933 atmci_writel(host, CFG, host->cfg_reg);
933 } 934 }
934 935
935 /* 936 /*
@@ -937,7 +938,7 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
937 * core ios update when finding the minimum. 938 * core ios update when finding the minimum.
938 */ 939 */
939 slot->clock = ios->clock; 940 slot->clock = ios->clock;
940 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 941 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
941 if (host->slot[i] && host->slot[i]->clock 942 if (host->slot[i] && host->slot[i]->clock
942 && host->slot[i]->clock < clock_min) 943 && host->slot[i]->clock < clock_min)
943 clock_min = host->slot[i]->clock; 944 clock_min = host->slot[i]->clock;
@@ -952,28 +953,28 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
952 clkdiv = 255; 953 clkdiv = 255;
953 } 954 }
954 955
955 host->mode_reg = MCI_MR_CLKDIV(clkdiv); 956 host->mode_reg = ATMCI_MR_CLKDIV(clkdiv);
956 957
957 /* 958 /*
958 * WRPROOF and RDPROOF prevent overruns/underruns by 959 * WRPROOF and RDPROOF prevent overruns/underruns by
959 * stopping the clock when the FIFO is full/empty. 960 * stopping the clock when the FIFO is full/empty.
960 * This state is not expected to last for long. 961 * This state is not expected to last for long.
961 */ 962 */
962 if (mci_has_rwproof()) 963 if (atmci_has_rwproof())
963 host->mode_reg |= (MCI_MR_WRPROOF | MCI_MR_RDPROOF); 964 host->mode_reg |= (ATMCI_MR_WRPROOF | ATMCI_MR_RDPROOF);
964 965
965 if (atmci_is_mci2()) { 966 if (atmci_is_mci2()) {
966 /* setup High Speed mode in relation with card capacity */ 967 /* setup High Speed mode in relation with card capacity */
967 if (ios->timing == MMC_TIMING_SD_HS) 968 if (ios->timing == MMC_TIMING_SD_HS)
968 host->cfg_reg |= MCI_CFG_HSMODE; 969 host->cfg_reg |= ATMCI_CFG_HSMODE;
969 else 970 else
970 host->cfg_reg &= ~MCI_CFG_HSMODE; 971 host->cfg_reg &= ~ATMCI_CFG_HSMODE;
971 } 972 }
972 973
973 if (list_empty(&host->queue)) { 974 if (list_empty(&host->queue)) {
974 mci_writel(host, MR, host->mode_reg); 975 atmci_writel(host, MR, host->mode_reg);
975 if (atmci_is_mci2()) 976 if (atmci_is_mci2())
976 mci_writel(host, CFG, host->cfg_reg); 977 atmci_writel(host, CFG, host->cfg_reg);
977 } else { 978 } else {
978 host->need_clock_update = true; 979 host->need_clock_update = true;
979 } 980 }
@@ -984,16 +985,16 @@ static void atmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
984 985
985 spin_lock_bh(&host->lock); 986 spin_lock_bh(&host->lock);
986 slot->clock = 0; 987 slot->clock = 0;
987 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 988 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
988 if (host->slot[i] && host->slot[i]->clock) { 989 if (host->slot[i] && host->slot[i]->clock) {
989 any_slot_active = true; 990 any_slot_active = true;
990 break; 991 break;
991 } 992 }
992 } 993 }
993 if (!any_slot_active) { 994 if (!any_slot_active) {
994 mci_writel(host, CR, MCI_CR_MCIDIS); 995 atmci_writel(host, CR, ATMCI_CR_MCIDIS);
995 if (host->mode_reg) { 996 if (host->mode_reg) {
996 mci_readl(host, MR); 997 atmci_readl(host, MR);
997 clk_disable(host->mck); 998 clk_disable(host->mck);
998 } 999 }
999 host->mode_reg = 0; 1000 host->mode_reg = 0;
@@ -1057,9 +1058,9 @@ static void atmci_enable_sdio_irq(struct mmc_host *mmc, int enable)
1057 struct atmel_mci *host = slot->host; 1058 struct atmel_mci *host = slot->host;
1058 1059
1059 if (enable) 1060 if (enable)
1060 mci_writel(host, IER, slot->sdio_irq); 1061 atmci_writel(host, IER, slot->sdio_irq);
1061 else 1062 else
1062 mci_writel(host, IDR, slot->sdio_irq); 1063 atmci_writel(host, IDR, slot->sdio_irq);
1063} 1064}
1064 1065
1065static const struct mmc_host_ops atmci_ops = { 1066static const struct mmc_host_ops atmci_ops = {
@@ -1086,9 +1087,9 @@ static void atmci_request_end(struct atmel_mci *host, struct mmc_request *mrq)
1086 * busy transferring data. 1087 * busy transferring data.
1087 */ 1088 */
1088 if (host->need_clock_update) { 1089 if (host->need_clock_update) {
1089 mci_writel(host, MR, host->mode_reg); 1090 atmci_writel(host, MR, host->mode_reg);
1090 if (atmci_is_mci2()) 1091 if (atmci_is_mci2())
1091 mci_writel(host, CFG, host->cfg_reg); 1092 atmci_writel(host, CFG, host->cfg_reg);
1092 } 1093 }
1093 1094
1094 host->cur_slot->mrq = NULL; 1095 host->cur_slot->mrq = NULL;
@@ -1117,16 +1118,16 @@ static void atmci_command_complete(struct atmel_mci *host,
1117 u32 status = host->cmd_status; 1118 u32 status = host->cmd_status;
1118 1119
1119 /* Read the response from the card (up to 16 bytes) */ 1120 /* Read the response from the card (up to 16 bytes) */
1120 cmd->resp[0] = mci_readl(host, RSPR); 1121 cmd->resp[0] = atmci_readl(host, RSPR);
1121 cmd->resp[1] = mci_readl(host, RSPR); 1122 cmd->resp[1] = atmci_readl(host, RSPR);
1122 cmd->resp[2] = mci_readl(host, RSPR); 1123 cmd->resp[2] = atmci_readl(host, RSPR);
1123 cmd->resp[3] = mci_readl(host, RSPR); 1124 cmd->resp[3] = atmci_readl(host, RSPR);
1124 1125
1125 if (status & MCI_RTOE) 1126 if (status & ATMCI_RTOE)
1126 cmd->error = -ETIMEDOUT; 1127 cmd->error = -ETIMEDOUT;
1127 else if ((cmd->flags & MMC_RSP_CRC) && (status & MCI_RCRCE)) 1128 else if ((cmd->flags & MMC_RSP_CRC) && (status & ATMCI_RCRCE))
1128 cmd->error = -EILSEQ; 1129 cmd->error = -EILSEQ;
1129 else if (status & (MCI_RINDE | MCI_RDIRE | MCI_RENDE)) 1130 else if (status & (ATMCI_RINDE | ATMCI_RDIRE | ATMCI_RENDE))
1130 cmd->error = -EIO; 1131 cmd->error = -EIO;
1131 else 1132 else
1132 cmd->error = 0; 1133 cmd->error = 0;
@@ -1138,8 +1139,8 @@ static void atmci_command_complete(struct atmel_mci *host,
1138 if (cmd->data) { 1139 if (cmd->data) {
1139 atmci_stop_dma(host); 1140 atmci_stop_dma(host);
1140 host->data = NULL; 1141 host->data = NULL;
1141 mci_writel(host, IDR, MCI_NOTBUSY 1142 atmci_writel(host, IDR, ATMCI_NOTBUSY
1142 | MCI_TXRDY | MCI_RXRDY 1143 | ATMCI_TXRDY | ATMCI_RXRDY
1143 | ATMCI_DATA_ERROR_FLAGS); 1144 | ATMCI_DATA_ERROR_FLAGS);
1144 } 1145 }
1145 } 1146 }
@@ -1191,11 +1192,11 @@ static void atmci_detect_change(unsigned long data)
1191 * Reset controller to terminate any ongoing 1192 * Reset controller to terminate any ongoing
1192 * commands or data transfers. 1193 * commands or data transfers.
1193 */ 1194 */
1194 mci_writel(host, CR, MCI_CR_SWRST); 1195 atmci_writel(host, CR, ATMCI_CR_SWRST);
1195 mci_writel(host, CR, MCI_CR_MCIEN); 1196 atmci_writel(host, CR, ATMCI_CR_MCIEN);
1196 mci_writel(host, MR, host->mode_reg); 1197 atmci_writel(host, MR, host->mode_reg);
1197 if (atmci_is_mci2()) 1198 if (atmci_is_mci2())
1198 mci_writel(host, CFG, host->cfg_reg); 1199 atmci_writel(host, CFG, host->cfg_reg);
1199 1200
1200 host->data = NULL; 1201 host->data = NULL;
1201 host->cmd = NULL; 1202 host->cmd = NULL;
@@ -1261,7 +1262,7 @@ static void atmci_tasklet_func(unsigned long priv)
1261 dev_vdbg(&host->pdev->dev, 1262 dev_vdbg(&host->pdev->dev,
1262 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n", 1263 "tasklet: state %u pending/completed/mask %lx/%lx/%x\n",
1263 state, host->pending_events, host->completed_events, 1264 state, host->pending_events, host->completed_events,
1264 mci_readl(host, IMR)); 1265 atmci_readl(host, IMR));
1265 1266
1266 do { 1267 do {
1267 prev_state = state; 1268 prev_state = state;
@@ -1291,7 +1292,7 @@ static void atmci_tasklet_func(unsigned long priv)
1291 EVENT_DATA_ERROR)) { 1292 EVENT_DATA_ERROR)) {
1292 atmci_stop_dma(host); 1293 atmci_stop_dma(host);
1293 if (data->stop) 1294 if (data->stop)
1294 send_stop_cmd(host, data); 1295 atmci_send_stop_cmd(host, data);
1295 state = STATE_DATA_ERROR; 1296 state = STATE_DATA_ERROR;
1296 break; 1297 break;
1297 } 1298 }
@@ -1313,11 +1314,11 @@ static void atmci_tasklet_func(unsigned long priv)
1313 atmci_set_completed(host, EVENT_DATA_COMPLETE); 1314 atmci_set_completed(host, EVENT_DATA_COMPLETE);
1314 status = host->data_status; 1315 status = host->data_status;
1315 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) { 1316 if (unlikely(status & ATMCI_DATA_ERROR_FLAGS)) {
1316 if (status & MCI_DTOE) { 1317 if (status & ATMCI_DTOE) {
1317 dev_dbg(&host->pdev->dev, 1318 dev_dbg(&host->pdev->dev,
1318 "data timeout error\n"); 1319 "data timeout error\n");
1319 data->error = -ETIMEDOUT; 1320 data->error = -ETIMEDOUT;
1320 } else if (status & MCI_DCRCE) { 1321 } else if (status & ATMCI_DCRCE) {
1321 dev_dbg(&host->pdev->dev, 1322 dev_dbg(&host->pdev->dev,
1322 "data CRC error\n"); 1323 "data CRC error\n");
1323 data->error = -EILSEQ; 1324 data->error = -EILSEQ;
@@ -1330,7 +1331,7 @@ static void atmci_tasklet_func(unsigned long priv)
1330 } else { 1331 } else {
1331 data->bytes_xfered = data->blocks * data->blksz; 1332 data->bytes_xfered = data->blocks * data->blksz;
1332 data->error = 0; 1333 data->error = 0;
1333 mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS); 1334 atmci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS);
1334 } 1335 }
1335 1336
1336 if (!data->stop) { 1337 if (!data->stop) {
@@ -1340,7 +1341,7 @@ static void atmci_tasklet_func(unsigned long priv)
1340 1341
1341 prev_state = state = STATE_SENDING_STOP; 1342 prev_state = state = STATE_SENDING_STOP;
1342 if (!data->error) 1343 if (!data->error)
1343 send_stop_cmd(host, data); 1344 atmci_send_stop_cmd(host, data);
1344 /* fall through */ 1345 /* fall through */
1345 1346
1346 case STATE_SENDING_STOP: 1347 case STATE_SENDING_STOP:
@@ -1380,7 +1381,7 @@ static void atmci_read_data_pio(struct atmel_mci *host)
1380 unsigned int nbytes = 0; 1381 unsigned int nbytes = 0;
1381 1382
1382 do { 1383 do {
1383 value = mci_readl(host, RDR); 1384 value = atmci_readl(host, RDR);
1384 if (likely(offset + 4 <= sg->length)) { 1385 if (likely(offset + 4 <= sg->length)) {
1385 put_unaligned(value, (u32 *)(buf + offset)); 1386 put_unaligned(value, (u32 *)(buf + offset));
1386 1387
@@ -1412,9 +1413,9 @@ static void atmci_read_data_pio(struct atmel_mci *host)
1412 nbytes += offset; 1413 nbytes += offset;
1413 } 1414 }
1414 1415
1415 status = mci_readl(host, SR); 1416 status = atmci_readl(host, SR);
1416 if (status & ATMCI_DATA_ERROR_FLAGS) { 1417 if (status & ATMCI_DATA_ERROR_FLAGS) {
1417 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_RXRDY 1418 atmci_writel(host, IDR, (ATMCI_NOTBUSY | ATMCI_RXRDY
1418 | ATMCI_DATA_ERROR_FLAGS)); 1419 | ATMCI_DATA_ERROR_FLAGS));
1419 host->data_status = status; 1420 host->data_status = status;
1420 data->bytes_xfered += nbytes; 1421 data->bytes_xfered += nbytes;
@@ -1423,7 +1424,7 @@ static void atmci_read_data_pio(struct atmel_mci *host)
1423 tasklet_schedule(&host->tasklet); 1424 tasklet_schedule(&host->tasklet);
1424 return; 1425 return;
1425 } 1426 }
1426 } while (status & MCI_RXRDY); 1427 } while (status & ATMCI_RXRDY);
1427 1428
1428 host->pio_offset = offset; 1429 host->pio_offset = offset;
1429 data->bytes_xfered += nbytes; 1430 data->bytes_xfered += nbytes;
@@ -1431,8 +1432,8 @@ static void atmci_read_data_pio(struct atmel_mci *host)
1431 return; 1432 return;
1432 1433
1433done: 1434done:
1434 mci_writel(host, IDR, MCI_RXRDY); 1435 atmci_writel(host, IDR, ATMCI_RXRDY);
1435 mci_writel(host, IER, MCI_NOTBUSY); 1436 atmci_writel(host, IER, ATMCI_NOTBUSY);
1436 data->bytes_xfered += nbytes; 1437 data->bytes_xfered += nbytes;
1437 smp_wmb(); 1438 smp_wmb();
1438 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1439 atmci_set_pending(host, EVENT_XFER_COMPLETE);
@@ -1451,7 +1452,7 @@ static void atmci_write_data_pio(struct atmel_mci *host)
1451 do { 1452 do {
1452 if (likely(offset + 4 <= sg->length)) { 1453 if (likely(offset + 4 <= sg->length)) {
1453 value = get_unaligned((u32 *)(buf + offset)); 1454 value = get_unaligned((u32 *)(buf + offset));
1454 mci_writel(host, TDR, value); 1455 atmci_writel(host, TDR, value);
1455 1456
1456 offset += 4; 1457 offset += 4;
1457 nbytes += 4; 1458 nbytes += 4;
@@ -1472,20 +1473,20 @@ static void atmci_write_data_pio(struct atmel_mci *host)
1472 1473
1473 host->sg = sg = sg_next(sg); 1474 host->sg = sg = sg_next(sg);
1474 if (!sg) { 1475 if (!sg) {
1475 mci_writel(host, TDR, value); 1476 atmci_writel(host, TDR, value);
1476 goto done; 1477 goto done;
1477 } 1478 }
1478 1479
1479 offset = 4 - remaining; 1480 offset = 4 - remaining;
1480 buf = sg_virt(sg); 1481 buf = sg_virt(sg);
1481 memcpy((u8 *)&value + remaining, buf, offset); 1482 memcpy((u8 *)&value + remaining, buf, offset);
1482 mci_writel(host, TDR, value); 1483 atmci_writel(host, TDR, value);
1483 nbytes += offset; 1484 nbytes += offset;
1484 } 1485 }
1485 1486
1486 status = mci_readl(host, SR); 1487 status = atmci_readl(host, SR);
1487 if (status & ATMCI_DATA_ERROR_FLAGS) { 1488 if (status & ATMCI_DATA_ERROR_FLAGS) {
1488 mci_writel(host, IDR, (MCI_NOTBUSY | MCI_TXRDY 1489 atmci_writel(host, IDR, (ATMCI_NOTBUSY | ATMCI_TXRDY
1489 | ATMCI_DATA_ERROR_FLAGS)); 1490 | ATMCI_DATA_ERROR_FLAGS));
1490 host->data_status = status; 1491 host->data_status = status;
1491 data->bytes_xfered += nbytes; 1492 data->bytes_xfered += nbytes;
@@ -1494,7 +1495,7 @@ static void atmci_write_data_pio(struct atmel_mci *host)
1494 tasklet_schedule(&host->tasklet); 1495 tasklet_schedule(&host->tasklet);
1495 return; 1496 return;
1496 } 1497 }
1497 } while (status & MCI_TXRDY); 1498 } while (status & ATMCI_TXRDY);
1498 1499
1499 host->pio_offset = offset; 1500 host->pio_offset = offset;
1500 data->bytes_xfered += nbytes; 1501 data->bytes_xfered += nbytes;
@@ -1502,8 +1503,8 @@ static void atmci_write_data_pio(struct atmel_mci *host)
1502 return; 1503 return;
1503 1504
1504done: 1505done:
1505 mci_writel(host, IDR, MCI_TXRDY); 1506 atmci_writel(host, IDR, ATMCI_TXRDY);
1506 mci_writel(host, IER, MCI_NOTBUSY); 1507 atmci_writel(host, IER, ATMCI_NOTBUSY);
1507 data->bytes_xfered += nbytes; 1508 data->bytes_xfered += nbytes;
1508 smp_wmb(); 1509 smp_wmb();
1509 atmci_set_pending(host, EVENT_XFER_COMPLETE); 1510 atmci_set_pending(host, EVENT_XFER_COMPLETE);
@@ -1511,7 +1512,7 @@ done:
1511 1512
1512static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status) 1513static void atmci_cmd_interrupt(struct atmel_mci *host, u32 status)
1513{ 1514{
1514 mci_writel(host, IDR, MCI_CMDRDY); 1515 atmci_writel(host, IDR, ATMCI_CMDRDY);
1515 1516
1516 host->cmd_status = status; 1517 host->cmd_status = status;
1517 smp_wmb(); 1518 smp_wmb();
@@ -1523,7 +1524,7 @@ static void atmci_sdio_interrupt(struct atmel_mci *host, u32 status)
1523{ 1524{
1524 int i; 1525 int i;
1525 1526
1526 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 1527 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1527 struct atmel_mci_slot *slot = host->slot[i]; 1528 struct atmel_mci_slot *slot = host->slot[i];
1528 if (slot && (status & slot->sdio_irq)) { 1529 if (slot && (status & slot->sdio_irq)) {
1529 mmc_signal_sdio_irq(slot->mmc); 1530 mmc_signal_sdio_irq(slot->mmc);
@@ -1539,40 +1540,40 @@ static irqreturn_t atmci_interrupt(int irq, void *dev_id)
1539 unsigned int pass_count = 0; 1540 unsigned int pass_count = 0;
1540 1541
1541 do { 1542 do {
1542 status = mci_readl(host, SR); 1543 status = atmci_readl(host, SR);
1543 mask = mci_readl(host, IMR); 1544 mask = atmci_readl(host, IMR);
1544 pending = status & mask; 1545 pending = status & mask;
1545 if (!pending) 1546 if (!pending)
1546 break; 1547 break;
1547 1548
1548 if (pending & ATMCI_DATA_ERROR_FLAGS) { 1549 if (pending & ATMCI_DATA_ERROR_FLAGS) {
1549 mci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS 1550 atmci_writel(host, IDR, ATMCI_DATA_ERROR_FLAGS
1550 | MCI_RXRDY | MCI_TXRDY); 1551 | ATMCI_RXRDY | ATMCI_TXRDY);
1551 pending &= mci_readl(host, IMR); 1552 pending &= atmci_readl(host, IMR);
1552 1553
1553 host->data_status = status; 1554 host->data_status = status;
1554 smp_wmb(); 1555 smp_wmb();
1555 atmci_set_pending(host, EVENT_DATA_ERROR); 1556 atmci_set_pending(host, EVENT_DATA_ERROR);
1556 tasklet_schedule(&host->tasklet); 1557 tasklet_schedule(&host->tasklet);
1557 } 1558 }
1558 if (pending & MCI_NOTBUSY) { 1559 if (pending & ATMCI_NOTBUSY) {
1559 mci_writel(host, IDR, 1560 atmci_writel(host, IDR,
1560 ATMCI_DATA_ERROR_FLAGS | MCI_NOTBUSY); 1561 ATMCI_DATA_ERROR_FLAGS | ATMCI_NOTBUSY);
1561 if (!host->data_status) 1562 if (!host->data_status)
1562 host->data_status = status; 1563 host->data_status = status;
1563 smp_wmb(); 1564 smp_wmb();
1564 atmci_set_pending(host, EVENT_DATA_COMPLETE); 1565 atmci_set_pending(host, EVENT_DATA_COMPLETE);
1565 tasklet_schedule(&host->tasklet); 1566 tasklet_schedule(&host->tasklet);
1566 } 1567 }
1567 if (pending & MCI_RXRDY) 1568 if (pending & ATMCI_RXRDY)
1568 atmci_read_data_pio(host); 1569 atmci_read_data_pio(host);
1569 if (pending & MCI_TXRDY) 1570 if (pending & ATMCI_TXRDY)
1570 atmci_write_data_pio(host); 1571 atmci_write_data_pio(host);
1571 1572
1572 if (pending & MCI_CMDRDY) 1573 if (pending & ATMCI_CMDRDY)
1573 atmci_cmd_interrupt(host, status); 1574 atmci_cmd_interrupt(host, status);
1574 1575
1575 if (pending & (MCI_SDIOIRQA | MCI_SDIOIRQB)) 1576 if (pending & (ATMCI_SDIOIRQA | ATMCI_SDIOIRQB))
1576 atmci_sdio_interrupt(host, status); 1577 atmci_sdio_interrupt(host, status);
1577 1578
1578 } while (pass_count++ < 5); 1579 } while (pass_count++ < 5);
@@ -1705,7 +1706,7 @@ static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
1705} 1706}
1706 1707
1707#ifdef CONFIG_MMC_ATMELMCI_DMA 1708#ifdef CONFIG_MMC_ATMELMCI_DMA
1708static bool filter(struct dma_chan *chan, void *slave) 1709static bool atmci_filter(struct dma_chan *chan, void *slave)
1709{ 1710{
1710 struct mci_dma_data *sl = slave; 1711 struct mci_dma_data *sl = slave;
1711 1712
@@ -1730,14 +1731,14 @@ static void atmci_configure_dma(struct atmel_mci *host)
1730 dma_cap_mask_t mask; 1731 dma_cap_mask_t mask;
1731 1732
1732 setup_dma_addr(pdata->dma_slave, 1733 setup_dma_addr(pdata->dma_slave,
1733 host->mapbase + MCI_TDR, 1734 host->mapbase + ATMCI_TDR,
1734 host->mapbase + MCI_RDR); 1735 host->mapbase + ATMCI_RDR);
1735 1736
1736 /* Try to grab a DMA channel */ 1737 /* Try to grab a DMA channel */
1737 dma_cap_zero(mask); 1738 dma_cap_zero(mask);
1738 dma_cap_set(DMA_SLAVE, mask); 1739 dma_cap_set(DMA_SLAVE, mask);
1739 host->dma.chan = 1740 host->dma.chan =
1740 dma_request_channel(mask, filter, pdata->dma_slave); 1741 dma_request_channel(mask, atmci_filter, pdata->dma_slave);
1741 } 1742 }
1742 if (!host->dma.chan) 1743 if (!host->dma.chan)
1743 dev_notice(&host->pdev->dev, "DMA not available, using PIO\n"); 1744 dev_notice(&host->pdev->dev, "DMA not available, using PIO\n");
@@ -1789,7 +1790,7 @@ static int __init atmci_probe(struct platform_device *pdev)
1789 goto err_ioremap; 1790 goto err_ioremap;
1790 1791
1791 clk_enable(host->mck); 1792 clk_enable(host->mck);
1792 mci_writel(host, CR, MCI_CR_SWRST); 1793 atmci_writel(host, CR, ATMCI_CR_SWRST);
1793 host->bus_hz = clk_get_rate(host->mck); 1794 host->bus_hz = clk_get_rate(host->mck);
1794 clk_disable(host->mck); 1795 clk_disable(host->mck);
1795 1796
@@ -1810,13 +1811,13 @@ static int __init atmci_probe(struct platform_device *pdev)
1810 ret = -ENODEV; 1811 ret = -ENODEV;
1811 if (pdata->slot[0].bus_width) { 1812 if (pdata->slot[0].bus_width) {
1812 ret = atmci_init_slot(host, &pdata->slot[0], 1813 ret = atmci_init_slot(host, &pdata->slot[0],
1813 0, MCI_SDCSEL_SLOT_A, MCI_SDIOIRQA); 1814 0, ATMCI_SDCSEL_SLOT_A, ATMCI_SDIOIRQA);
1814 if (!ret) 1815 if (!ret)
1815 nr_slots++; 1816 nr_slots++;
1816 } 1817 }
1817 if (pdata->slot[1].bus_width) { 1818 if (pdata->slot[1].bus_width) {
1818 ret = atmci_init_slot(host, &pdata->slot[1], 1819 ret = atmci_init_slot(host, &pdata->slot[1],
1819 1, MCI_SDCSEL_SLOT_B, MCI_SDIOIRQB); 1820 1, ATMCI_SDCSEL_SLOT_B, ATMCI_SDIOIRQB);
1820 if (!ret) 1821 if (!ret)
1821 nr_slots++; 1822 nr_slots++;
1822 } 1823 }
@@ -1854,15 +1855,15 @@ static int __exit atmci_remove(struct platform_device *pdev)
1854 1855
1855 platform_set_drvdata(pdev, NULL); 1856 platform_set_drvdata(pdev, NULL);
1856 1857
1857 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 1858 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1858 if (host->slot[i]) 1859 if (host->slot[i])
1859 atmci_cleanup_slot(host->slot[i], i); 1860 atmci_cleanup_slot(host->slot[i], i);
1860 } 1861 }
1861 1862
1862 clk_enable(host->mck); 1863 clk_enable(host->mck);
1863 mci_writel(host, IDR, ~0UL); 1864 atmci_writel(host, IDR, ~0UL);
1864 mci_writel(host, CR, MCI_CR_MCIDIS); 1865 atmci_writel(host, CR, ATMCI_CR_MCIDIS);
1865 mci_readl(host, SR); 1866 atmci_readl(host, SR);
1866 clk_disable(host->mck); 1867 clk_disable(host->mck);
1867 1868
1868#ifdef CONFIG_MMC_ATMELMCI_DMA 1869#ifdef CONFIG_MMC_ATMELMCI_DMA
@@ -1885,7 +1886,7 @@ static int atmci_suspend(struct device *dev)
1885 struct atmel_mci *host = dev_get_drvdata(dev); 1886 struct atmel_mci *host = dev_get_drvdata(dev);
1886 int i; 1887 int i;
1887 1888
1888 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 1889 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1889 struct atmel_mci_slot *slot = host->slot[i]; 1890 struct atmel_mci_slot *slot = host->slot[i];
1890 int ret; 1891 int ret;
1891 1892
@@ -1916,7 +1917,7 @@ static int atmci_resume(struct device *dev)
1916 int i; 1917 int i;
1917 int ret = 0; 1918 int ret = 0;
1918 1919
1919 for (i = 0; i < ATMEL_MCI_MAX_NR_SLOTS; i++) { 1920 for (i = 0; i < ATMCI_MAX_NR_SLOTS; i++) {
1920 struct atmel_mci_slot *slot = host->slot[i]; 1921 struct atmel_mci_slot *slot = host->slot[i];
1921 int err; 1922 int err;
1922 1923
diff --git a/include/linux/atmel-mci.h b/include/linux/atmel-mci.h
index 3e09b345f4d6..4c7a4b2104bf 100644
--- a/include/linux/atmel-mci.h
+++ b/include/linux/atmel-mci.h
@@ -1,7 +1,7 @@
1#ifndef __LINUX_ATMEL_MCI_H 1#ifndef __LINUX_ATMEL_MCI_H
2#define __LINUX_ATMEL_MCI_H 2#define __LINUX_ATMEL_MCI_H
3 3
4#define ATMEL_MCI_MAX_NR_SLOTS 2 4#define ATMCI_MAX_NR_SLOTS 2
5 5
6/** 6/**
7 * struct mci_slot_pdata - board-specific per-slot configuration 7 * struct mci_slot_pdata - board-specific per-slot configuration
@@ -33,7 +33,7 @@ struct mci_slot_pdata {
33 */ 33 */
34struct mci_platform_data { 34struct mci_platform_data {
35 struct mci_dma_data *dma_slave; 35 struct mci_dma_data *dma_slave;
36 struct mci_slot_pdata slot[ATMEL_MCI_MAX_NR_SLOTS]; 36 struct mci_slot_pdata slot[ATMCI_MAX_NR_SLOTS];
37}; 37};
38 38
39#endif /* __LINUX_ATMEL_MCI_H */ 39#endif /* __LINUX_ATMEL_MCI_H */
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-14 15:15:36 -0500